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///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_cmd_translator.v
//
// Description:
// INCR and WRAP burst modes are decoded in parallel and then the output is
// chosen based on the AxBURST value. FIXED burst mode is not supported and
// is mapped to the INCR command instead.
//
// Specifications:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_cmd_translator #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axaddr ,
input wire [7:0] s_axlen ,
input wire [2:0] s_axsize ,
input wire [1:0] s_axburst ,
input wire s_axhandshake ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr ,
output wire incr_burst ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr;
wire wrap_next_pending;
reg sel_first;
reg s_axburst_eq1;
reg s_axburst_eq0;
reg sel_first_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr :
(s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr :
wrap_cmd_byte_addr;
assign incr_burst = (s_axburst[1]) ? 1'b0 : 1'b1;
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | s_axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
always @( * ) begin
if (reset | s_axhandshake) begin
sel_first_i = 1'b1;
end else if (next) begin
sel_first_i = 1'b0;
end else begin
sel_first_i = sel_first;
end
end
assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
always @(posedge clk) begin
if (sel_first_i || s_axburst[1]) begin
s_axburst_eq1 <= wrap_next_pending;
end else begin
s_axburst_eq1 <= incr_next_pending;
end
if (sel_first_i || !s_axburst[1]) begin
s_axburst_eq0 <= incr_next_pending;
end else begin
s_axburst_eq0 <= wrap_next_pending;
end
end
axi_protocol_converter_v2_1_b2s_incr_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( incr_next_pending )
);
axi_protocol_converter_v2_1_b2s_wrap_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( wrap_next_pending )
);
endmodule
`default_nettype wire
|
//IEEE Floating Point Adder (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [31:0] a, b, z;
reg [26:0] a_m, b_m;
reg [23:0] z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [27:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[22 : 0], 3'd0};
b_m <= {b[22 : 0], 3'd0};
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
z[31] <= a_s & b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s;
z[30:23] <= a_e[7:0] + 127;
z[22:0] <= a_m[26:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[26] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[26] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= a_m + b_m;
z_s <= a_s;
end else begin
if (a_m >= b_m) begin
sum <= a_m - b_m;
z_s <= a_s;
end else begin
sum <= b_m - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[27]) begin
z_m <= sum[27:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[26:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Divider (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
//
module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [50:0] quotient, divisor, dividend, remainder;
reg [5:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 128) && (b_e == 128)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 27;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[50];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 49) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[26:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Multiplier (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [49:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[49:26];
guard <= product[25];
round_bit <= product[24];
sticky <= (product[23:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Divider (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
//
module double_divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [108:0] quotient, divisor, dividend, remainder;
reg [6:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 1024) && (b_e == 1024)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 56;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[108];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 107) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[55:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Multiplier (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-10
module double_multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [107:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[107:55];
guard <= product[54];
round_bit <= product[53];
sticky <= (product[52:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[11:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Adder (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module double_adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [63:0] a, b, z;
reg [55:0] a_m, b_m;
reg [52:0] z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [56:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[51 : 0], 3'd0};
b_m <= {b[51 : 0], 3'd0};
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -1023) && (a_m == 0)) && (($signed(b_e) == -1023) && (b_m == 0))) begin
z[63] <= a_s & b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s;
z[62:52] <= a_e[10:0] + 1023;
z[51:0] <= a_m[55:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[55] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[55] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= {1'd0, a_m} + b_m;
z_s <= a_s;
end else begin
if (a_m > b_m) begin
sum <= {1'd0, a_m} - b_m;
z_s <= a_s;
end else begin
sum <= {1'd0, b_m} - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[56]) begin
z_m <= sum[56:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[55:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module int_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [31:0] a, z, value;
reg [23:0] z_m;
reg [7:0] z_r;
reg [7:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -127;
state <= pack;
end else begin
value <= a[31] ? -a : a;
z_s <= a[31];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 31;
z_m <= value[31:8];
z_r <= value[7:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[23]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[7];
z_r <= z_r << 1;
end else begin
guard <= z_r[7];
round_bit <= z_r[6];
sticky <= z_r[5:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e + 127;
z[31] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_int(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [31:0] a_m, a, z;
reg [8:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[31:8] <= {1'b1, a[22 : 0]};
a_m[7:0] <= 0;
a_e <= a[30 : 23] - 127;
a_s <= a[31];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -127) begin
z <= 0;
state <= put_z;
end else if ($signed(a_e) > 31) begin
z <= 32'h80000000;
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 31 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[31]) begin
z <= 32'h80000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module long_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [63:0] a, z, value;
reg [52:0] z_m;
reg [10:0] z_r;
reg [10:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -1023;
state <= pack;
end else begin
value <= a[63] ? -a : a;
z_s <= a[63];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 63;
z_m <= value[63:11];
z_r <= value[10:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[52]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[10];
z_r <= z_r << 1;
end else begin
guard <= z_r[10];
round_bit <= z_r[9];
sticky <= z_r[8:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e + 1023;
z[63] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
module double_to_long(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [63:0] a_m, a, z;
reg [11:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[63:11] <= {1'b1, a[51 : 0]};
a_m[10:0] <= 0;
a_e <= a[62 : 52] - 1023;
a_s <= a[63];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -1023) begin
//zero
z <= 0;
state <= put_z;
end else if ($signed(a_e) == 1024 && a[51:0] != 0) begin
//nan
z <= 64'h8000000000000000;
state <= put_z;
end else if ($signed(a_e) > 63) begin
//too big
if (a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= 64'h0000000000000000;
end
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 63 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[63] && a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [1:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
normalise_0 = 3'd2,
put_z = 3'd3;
reg [63:0] z;
reg [10:0] z_e;
reg [52:0] z_m;
reg [31:0] a;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
z[63] <= a[31];
z[62:52] <= (a[30:23] - 127) + 1023;
z[51:0] <= {a[22:0], 29'd0};
if (a[30:23] == 255) begin
z[62:52] <= 2047;
end
state <= put_z;
if (a[30:23] == 0) begin
if (a[23:0]) begin
state <= normalise_0;
z_e <= 897;
z_m <= {1'd0, a[22:0], 29'd0};
end
z[62:52] <= 0;
end
end
normalise_0:
begin
if (z_m[52]) begin
z[62:52] <= z_e;
z[51:0] <= z_m[51:0];
state <= put_z;
end else begin
z_m <= {z_m[51:0], 1'd0};
z_e <= z_e - 1;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
module double_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [1:0] state;
parameter get_a = 3'd0,
unpack = 3'd1,
denormalise = 3'd2,
put_z = 3'd3;
reg [63:0] a;
reg [31:0] z;
reg [10:0] z_e;
reg [23:0] z_m;
reg guard;
reg round;
reg sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
z[31] <= a[63];
state <= put_z;
if (a[62:52] == 0) begin
z[30:23] <= 0;
z[22:0] <= 0;
end else if (a[62:52] < 897) begin
z[30:23] <= 0;
z_m <= {1'd1, a[51:29]};
z_e <= a[62:52];
guard <= a[28];
round <= a[27];
sticky <= a[26:0] != 0;
state <= denormalise;
end else if (a[62:52] == 2047) begin
z[30:23] <= 255;
z[22:0] <= 0;
if (a[51:0]) begin
z[22] <= 1;
end
end else if (a[62:52] > 1150) begin
z[30:23] <= 255;
z[22:0] <= 0;
end else begin
z[30:23] <= (a[62:52] - 1023) + 127;
if (a[28] && (a[27] || a[26:0])) begin
z[22:0] <= a[51:29] + 1;
end else begin
z[22:0] <= a[51:29];
end
end
end
denormalise:
begin
if (z_e == 897 || (z_m == 0 && guard == 0)) begin
state <= put_z;
z[22:0] <= z_m;
if (guard && (round || sticky)) begin
z[22:0] <= z_m + 1;
end
end else begin
z_e <= z_e + 1;
z_m <= {1'd0, z_m[23:1]};
guard <= z_m[0];
round <= guard;
sticky <= sticky | round;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
//IEEE Floating Point Adder (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [31:0] a, b, z;
reg [26:0] a_m, b_m;
reg [23:0] z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [27:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[22 : 0], 3'd0};
b_m <= {b[22 : 0], 3'd0};
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
z[31] <= a_s & b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s;
z[30:23] <= a_e[7:0] + 127;
z[22:0] <= a_m[26:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[26] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[26] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= a_m + b_m;
z_s <= a_s;
end else begin
if (a_m >= b_m) begin
sum <= a_m - b_m;
z_s <= a_s;
end else begin
sum <= b_m - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[27]) begin
z_m <= sum[27:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[26:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Divider (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
//
module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [50:0] quotient, divisor, dividend, remainder;
reg [5:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 128) && (b_e == 128)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 27;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[50];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 49) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[26:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Multiplier (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [49:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[49:26];
guard <= product[25];
round_bit <= product[24];
sticky <= (product[23:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Divider (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
//
module double_divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [108:0] quotient, divisor, dividend, remainder;
reg [6:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 1024) && (b_e == 1024)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 56;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[108];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 107) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[55:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Multiplier (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-10
module double_multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [107:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[107:55];
guard <= product[54];
round_bit <= product[53];
sticky <= (product[52:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[11:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Adder (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module double_adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [63:0] a, b, z;
reg [55:0] a_m, b_m;
reg [52:0] z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [56:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[51 : 0], 3'd0};
b_m <= {b[51 : 0], 3'd0};
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -1023) && (a_m == 0)) && (($signed(b_e) == -1023) && (b_m == 0))) begin
z[63] <= a_s & b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s;
z[62:52] <= a_e[10:0] + 1023;
z[51:0] <= a_m[55:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[55] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[55] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= {1'd0, a_m} + b_m;
z_s <= a_s;
end else begin
if (a_m > b_m) begin
sum <= {1'd0, a_m} - b_m;
z_s <= a_s;
end else begin
sum <= {1'd0, b_m} - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[56]) begin
z_m <= sum[56:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[55:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module int_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [31:0] a, z, value;
reg [23:0] z_m;
reg [7:0] z_r;
reg [7:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -127;
state <= pack;
end else begin
value <= a[31] ? -a : a;
z_s <= a[31];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 31;
z_m <= value[31:8];
z_r <= value[7:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[23]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[7];
z_r <= z_r << 1;
end else begin
guard <= z_r[7];
round_bit <= z_r[6];
sticky <= z_r[5:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e + 127;
z[31] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_int(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [31:0] a_m, a, z;
reg [8:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[31:8] <= {1'b1, a[22 : 0]};
a_m[7:0] <= 0;
a_e <= a[30 : 23] - 127;
a_s <= a[31];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -127) begin
z <= 0;
state <= put_z;
end else if ($signed(a_e) > 31) begin
z <= 32'h80000000;
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 31 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[31]) begin
z <= 32'h80000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module long_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [63:0] a, z, value;
reg [52:0] z_m;
reg [10:0] z_r;
reg [10:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -1023;
state <= pack;
end else begin
value <= a[63] ? -a : a;
z_s <= a[63];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 63;
z_m <= value[63:11];
z_r <= value[10:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[52]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[10];
z_r <= z_r << 1;
end else begin
guard <= z_r[10];
round_bit <= z_r[9];
sticky <= z_r[8:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e + 1023;
z[63] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
module double_to_long(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [63:0] a_m, a, z;
reg [11:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[63:11] <= {1'b1, a[51 : 0]};
a_m[10:0] <= 0;
a_e <= a[62 : 52] - 1023;
a_s <= a[63];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -1023) begin
//zero
z <= 0;
state <= put_z;
end else if ($signed(a_e) == 1024 && a[51:0] != 0) begin
//nan
z <= 64'h8000000000000000;
state <= put_z;
end else if ($signed(a_e) > 63) begin
//too big
if (a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= 64'h0000000000000000;
end
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 63 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[63] && a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [1:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
normalise_0 = 3'd2,
put_z = 3'd3;
reg [63:0] z;
reg [10:0] z_e;
reg [52:0] z_m;
reg [31:0] a;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
z[63] <= a[31];
z[62:52] <= (a[30:23] - 127) + 1023;
z[51:0] <= {a[22:0], 29'd0};
if (a[30:23] == 255) begin
z[62:52] <= 2047;
end
state <= put_z;
if (a[30:23] == 0) begin
if (a[23:0]) begin
state <= normalise_0;
z_e <= 897;
z_m <= {1'd0, a[22:0], 29'd0};
end
z[62:52] <= 0;
end
end
normalise_0:
begin
if (z_m[52]) begin
z[62:52] <= z_e;
z[51:0] <= z_m[51:0];
state <= put_z;
end else begin
z_m <= {z_m[51:0], 1'd0};
z_e <= z_e - 1;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
module double_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [1:0] state;
parameter get_a = 3'd0,
unpack = 3'd1,
denormalise = 3'd2,
put_z = 3'd3;
reg [63:0] a;
reg [31:0] z;
reg [10:0] z_e;
reg [23:0] z_m;
reg guard;
reg round;
reg sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
z[31] <= a[63];
state <= put_z;
if (a[62:52] == 0) begin
z[30:23] <= 0;
z[22:0] <= 0;
end else if (a[62:52] < 897) begin
z[30:23] <= 0;
z_m <= {1'd1, a[51:29]};
z_e <= a[62:52];
guard <= a[28];
round <= a[27];
sticky <= a[26:0] != 0;
state <= denormalise;
end else if (a[62:52] == 2047) begin
z[30:23] <= 255;
z[22:0] <= 0;
if (a[51:0]) begin
z[22] <= 1;
end
end else if (a[62:52] > 1150) begin
z[30:23] <= 255;
z[22:0] <= 0;
end else begin
z[30:23] <= (a[62:52] - 1023) + 127;
if (a[28] && (a[27] || a[26:0])) begin
z[22:0] <= a[51:29] + 1;
end else begin
z[22:0] <= a[51:29];
end
end
end
denormalise:
begin
if (z_e == 897 || (z_m == 0 && guard == 0)) begin
state <= put_z;
z[22:0] <= z_m;
if (guard && (round || sticky)) begin
z[22:0] <= z_m + 1;
end
end else begin
z_e <= z_e + 1;
z_m <= {1'd0, z_m[23:1]};
guard <= z_m[0];
round <= guard;
sticky <= sticky | round;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
`include "lo_read.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
`include "lo_read.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
`include "lo_read.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
`include "lo_read.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of Instruction cache data rams ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ic_ram.v,v $
// Revision 1.6 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.5 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
// Revision 1.4 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_ic_ram(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_IC
//
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of IC RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram_128x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we[0]),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule
|
//`timescale 1 ns / 100 ps
module m_port_ultra_quickhull
(
input clk,
input reset_n,
input processorEnable,
input [4095:0] points, //4096 / (8 * 2) = 256 points in each set
input [8:0] SS,
output [4095:0] convexPointsOutput,
output [7:0] convexSetSizeOutput
); //Same as points, 256 points
// Variables
localparam PTSIZE = 16; //Point Size: 16 bits long, two 8 bit dimensions
localparam LNSIZE = 32; //Line Size = 2 coordinates: 32 bits long
// localparam SS = 256; //Set Size, need to count up to 256 = 8 bits
reg [LNSIZE * 256 - 1 : 0] lineFIFO; //32 bits * number of points, just to be safe (100 points)
reg [15:0] lnIndex; //Line Index: only need 13 bits, but 16 just in case
reg [15:0] cxIndex; //Convex Index;only need 12 bits, but 16 just in case
reg [15:0] ptIndex;
reg [8:0] ptCount;
reg [4096:0] convexPoints;
reg [7:0] convexSetSize;
reg [PTSIZE - 1 : 0] xMinPoint;
reg [PTSIZE - 1 : 0] xMaxPoint;
reg [LNSIZE:0] line;
reg [8:0] positiveCrossCount;
reg [PTSIZE - 1 : 0] furthest;
reg [PTSIZE - 1 : 0] currPoint;
reg [(PTSIZE / 2) - 1 : 0] currPoint_X;
reg [(PTSIZE / 2) - 1 : 0] currPoint_Y;
reg [LNSIZE - 1 : 0] currLine;
reg [PTSIZE - 1 : 0] currLine_A;
reg [(PTSIZE / 2) - 1 : 0] currLine_AX;
reg [(PTSIZE / 2) - 1 : 0] currLine_AY;
reg [PTSIZE - 1 : 0] currLine_B;
reg [(PTSIZE / 2) - 1 : 0] currLine_BX;
reg [(PTSIZE / 2) - 1 : 0] currLine_BY;
reg signed [31:0] crossValue;
reg signed [31:0] furthestCrossValue;
reg [LNSIZE - 1: 0] nextLineAddr;
reg [LNSIZE - 1: 0] nextLineAddr2;
reg [PTSIZE - 1: 0] nextCXAddr;
reg [PTSIZE - 1: 0] nextCXAddr2;
reg furthestFlag;
// Output assignment
assign convexSetSizeOutput = convexSetSize;
assign convexPointsOutput = convexPoints;
// State Machine Implementation
reg[6:0] state;
assign { QEND, QHULL_RECURSE, QCROSS, QHULL_START, QFIND_MIN, QFIND_MAX, QINITIAL } = state;
localparam
INITIAL = 7'b0000001,
FIND_XMAX = 7'b0000010,
FIND_XMIN = 7'b0000100,
HULL_START = 7'b0001000,
CROSS = 7'b0010000,
HULL_RECURSE = 7'b0100000,
END = 7'b1000000;
// For loop integers
integer i;
integer j;
generate
always @(clk) begin
j = 0;
for (i = ptIndex; i < ptIndex + PTSIZE; i = i + 1) begin
currPoint[j] = points[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = ptIndex; i < ptIndex + (PTSIZE / 2); i = i + 1) begin
currPoint_X[j] = points[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = ptIndex + (PTSIZE / 2); i < ptIndex + PTSIZE; i = i + 1) begin
currPoint_Y[j] = points[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
currLine[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex; i < lnIndex + (LNSIZE/2); i = i + 1) begin
currLine_A[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex; i < lnIndex + (PTSIZE/2); i = i + 1) begin
currLine_AX[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex + (PTSIZE / 2); i < lnIndex + PTSIZE; i = i + 1) begin
currLine_AY[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex + (LNSIZE/2); i < lnIndex + LNSIZE; i = i + 1) begin
currLine_B [j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex + PTSIZE; i < lnIndex + LNSIZE - (PTSIZE/2); i = i + 1) begin
currLine_BX[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex + LNSIZE - (PTSIZE / 2); i < lnIndex + LNSIZE; i = i + 1) begin
currLine_BY[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
//NSL, register assignents, and State Machine
always @(posedge clk, negedge reset_n) begin
ptIndex = PTSIZE * ptCount;
/*
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
nextLineAddr[j] = lineFIFO[i];
j = j + 1;
end
j = 0;
for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin
nextLineAddr2[j] = lineFIFO[i];
j = j + 1;
end
j = 0;
for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin
nextCXAddr[j] = convexPoints[i];
j = j + 1;
end
j = 0;
for (i = cxIndex + PTSIZE; i < cxIndex + (PTSIZE * 2); i = i + 1) begin
nextCXAddr2[j] = convexPoints[i];
j = j + 1;
end
*/
crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));
if (!reset_n) begin
//Reset
state <= INITIAL;
end
case (state)
INITIAL: begin
// State Logic
lineFIFO <= 0;
lnIndex <= 32;
cxIndex <= 0;
line <= 0;
ptIndex <= 0;
ptCount <= 0;
positiveCrossCount <= 0;
xMinPoint <= 0;
xMaxPoint <= 0;
crossValue <= 0;
furthest <= 0;
furthestCrossValue <= 0;
furthestFlag <= 0;
convexSetSize <= 0;
convexPoints <= 0;
// NSL
if (processorEnable) begin
state <= FIND_XMAX;
end
end
FIND_XMAX: begin
//State Logic
if (ptCount == 0) begin
xMaxPoint <= currPoint;
end
else begin
if (xMaxPoint < currPoint) begin
xMaxPoint <= currPoint;
end
else begin
//Do nothing
end
end
//NSL
if (ptCount != (SS - 1)) begin
ptCount <= ptCount + 1;
state <= FIND_XMAX;
end
else begin
ptCount <= 0;
state <= FIND_XMIN;
end
end
FIND_XMIN: begin
//State Logic
if (ptCount == 0) begin
xMinPoint <= currPoint;
end
else begin
if (xMinPoint > currPoint) begin
xMinPoint <= currPoint;
end
else begin
//Do nothing
end
end
//NSL
if (ptCount != (SS - 1)) begin
ptCount <= ptCount + 1;
state <= FIND_XMIN;
end
else begin
ptCount <= 0;
state <= HULL_START;
end
end
HULL_START: begin
// State Logic
nextLineAddr = {xMinPoint, xMaxPoint};
j = 0;
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
lineFIFO[i] = nextLineAddr[j];
j = j + 1;
end
nextLineAddr2 = {xMaxPoint, xMinPoint};
j = 0;
for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin
lineFIFO[i] = nextLineAddr2[j];
j = j + 1;
end
lnIndex <= lnIndex + LNSIZE;
// NSL
ptCount <= 0;
state <= CROSS;
end
CROSS: begin
//State Logic
//if (crossValue > 0) begin
if (crossValue > 0 && ptCount != (SS)) begin
positiveCrossCount <= positiveCrossCount + 1;
if (furthestFlag == 0) begin
furthestCrossValue <= crossValue;
furthest <= currPoint;
furthestFlag <= 1;
end
else begin
if (furthestCrossValue < crossValue) begin
furthestCrossValue <= crossValue;
furthest <= currPoint;
end
end
end
//NSL
if (ptCount != (SS)) begin
ptCount <= ptCount + 1;
state <= CROSS;
end
else begin
ptCount <= 0;
furthestFlag <= 0;
state <= HULL_RECURSE;
end
end
HULL_RECURSE: begin
// State Logic
//TODO: get number of positive cross and furthest point
if (positiveCrossCount == 1 && lnIndex != 0) begin
nextCXAddr = currLine_A;
j = 0;
for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin
convexPoints[i] = nextCXAddr[j];
j = j + 1;
end
nextCXAddr2 = furthest;
j = 0;
for (i = cxIndex + PTSIZE; i < cxIndex + (PTSIZE * 2); i = i + 1) begin
convexPoints[i] = nextCXAddr2[j];
j = j + 1;
end
cxIndex <= cxIndex + (2 * PTSIZE);
convexSetSize <= convexSetSize + 2;
/*
//nextLineAddr <= 0;
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
lineFIFO[i] = 0;
j = j + 1;
end
*/
lnIndex <= lnIndex - LNSIZE;
end
else if (positiveCrossCount == 0 && lnIndex != 0) begin
nextCXAddr = currLine_A;
j = 0;
for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin
convexPoints[i] = nextCXAddr[j];
j = j + 1;
end
cxIndex <= cxIndex + PTSIZE;
convexSetSize <= convexSetSize + 1;
/*
//nextLineAddr <= 0;
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
lineFIFO[i] = 0;
j = j + 1;
end
*/
lnIndex <= lnIndex - LNSIZE;
end
else begin
nextLineAddr = {furthest, currLine_A};
nextLineAddr2 = {currLine_B, furthest};
//nextLineAddr = {currLine_A[15],currLine_A[14],currLine_A[13],currLine_A[12],currLine_A[11],currLine_A[10],currLine_A[9],currLine_A[8],currLine_A[7],currLine_A[6],currLine_A[5],currLine_A[4],currLine_A[3],currLine_A[2],currLine_A[1],currLine_A[0],furthest[15],furthest[14],furthest[13],furthest[12],furthest[11],furthest[10],furthest[9],furthest[8],furthest[7],furthest[6],furthest[5],furthest[4],furthest[3],furthest[2],furthest[1],furthest[0]};
//nextLineAddr2 = {furthest[15],furthest[14],furthest[13],furthest[12],furthest[11],furthest[10],furthest[9],furthest[8],furthest[7],furthest[6],furthest[5],furthest[4],furthest[3],furthest[2],furthest[1],furthest[0],currLine_B[15],currLine_B[14],currLine_B[13],currLine_B[12],currLine_B[11],currLine_B[10],currLine_B[9],currLine_B[8],currLine_B[7],currLine_B[6],currLine_B[5],currLine_B[4],currLine_B[3],currLine_B[2],currLine_B[1],currLine_B[0]};
j = 0;
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
lineFIFO[i] = nextLineAddr[j];
j = j + 1;
end
j = 0;
for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin
lineFIFO[i] = nextLineAddr2[j];
j = j + 1;
end
lnIndex <= lnIndex + LNSIZE;
end
// NSL
if ((lnIndex) != 0) begin
positiveCrossCount <= 0;
furthest <= 0;
furthestCrossValue <= 0;
ptCount <= 0;
state <= CROSS;
end
else begin
state <= END;
end
end
END: begin
//Wait
end
endcase
end
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: rx_descrambler
*
* Scrambler Logic (HMC Spec version 1.0)
* This module implements a parallel scrambler based on the
* polynomial 1+ x^(-14) + x^(-15).
*
* Such Scrambler is typically shown as a 15 bit Linear Feedback Shift Register
* (LFSR) with bits shifting from register 1 on the left to register 15 on the
* right, with register 14 and 15 combining to shift into register 1.
* The HMC Serializer outputs data[0] first from parallel tx data[n:0],
* so if data[n:0] is to be bitwise scrambled with LFSR[n:0], we need the LFSR
* to shift from n -> 0, the opposite direction from the typical illustration.
* This implementation shifts data from LFSR[14] on the left to LFSR[0] on the
* right, with LFSR[1] and [0] combining to shift into LFSR[14]. This way
* LFSR[14:0] can bitwise scramble data[14:0] and be compatible with serializ-
* ation that shifts out on the data[0] side.
* Put otherwise: Polynomial 1+ x^(-14) + x^(-15) is equiv to
* x^15 + x^1 + x^0
*
* This parallelized version calculates the next DWIDTH steps of values for
* the LFSR. These bits are used to scramble the parallel input, and to
* choose the next value of lfsr (lfsr_steps[DWIDTH-1]).
*
* This is the descrambler. It is self-seeding. When lock is asserted it has
* successfully found the correct value for the LFSR. It is only implemented
* for DWIDTH > 14.
*
* Since we know that scrambled zeros are being translated, we can calculate
* what the seed will be in the next timestep. In order to simplify the
* calculation, we assume that the top bit is a one. That has the happy side-
* effect of letting us know that the seed didn't get stuck at all zeros.
*
* After the scrambler is locked, the input word may need to be aligned. The
* bit_slip input allows the scrambler to shift one bit with the serializer
* to keep the scrambler in sync.
*/
`default_nettype none
module rx_descrambler #(
parameter DWIDTH=16,
parameter BITSLIP_SHIFT_RIGHT=1
)
(
input wire clk,
input wire res_n,
input wire bit_slip,
output reg locked,
input wire [DWIDTH-1:0] data_in,
output reg [DWIDTH-1:0] data_out
);
reg [14:0] lfsr; // LINEAR FEEDBACK SHIFT REGISTER
wire [14:0] lfsr_slipped; // Temporary lfsr for bitslip
wire [14:0] lfsr_steps [DWIDTH-1:0]; // LFSR values for serial time steps
wire [14:0] calculated_seed;
wire [DWIDTH-1:0] data_out_tmp;
generate
if(BITSLIP_SHIFT_RIGHT==1) begin
assign lfsr_slipped = { (lfsr_steps[DWIDTH-1][1] ^ lfsr_steps[DWIDTH-1][0]) , lfsr_steps[DWIDTH-1][14:1] };
end else begin
assign lfsr_slipped = { lfsr_steps[DWIDTH-1][13:0], (lfsr_steps[DWIDTH-1][14] ^ lfsr_steps[DWIDTH-1][0])};
end
endgenerate
// SEQUENTIAL PROCESS
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if (!res_n) begin
locked <= 1'b0;
lfsr <= 15'h0;
data_out <= {DWIDTH {1'b0}};
end else begin
data_out <= data_out_tmp;
if (!locked && |data_in) begin
lfsr <= calculated_seed;
// Locked when the calculated seeds match
if (calculated_seed == lfsr_steps[DWIDTH-1]) begin
locked <= 1'b1;
end
end else begin
if (bit_slip) begin
lfsr <= lfsr_slipped;
end else begin
lfsr <= lfsr_steps[DWIDTH-1];
end
end
end
end // serial shift right with left input
// SCRAMBLE
genvar j;
generate
localparam OFFSET = DWIDTH-15; // It breaks here if DWIDTH < 15
assign calculated_seed[14] = 1'b1; // Guess the top bit is 1
// data_in is the past state of the LFSR, so we can figure out
// the current value using a loop.
for(j = 0; j < 14; j = j + 1) begin : seed_calc
assign calculated_seed[j] = data_in[j+OFFSET] ^ data_in[j+OFFSET+1];
end
assign data_out_tmp [0] = data_in[0] ^ lfsr[0]; // single bit scrambled
assign lfsr_steps[0] = { (lfsr[1] ^ lfsr[0]) , lfsr[14:1] }; // lfsr at next bit clock
for(j = 1; j < DWIDTH; j = j + 1) begin : scrambler_gen
assign data_out_tmp[j] = data_in[j] ^ lfsr_steps[j-1][0];
assign lfsr_steps[j] = { (lfsr_steps[j-1][1] ^ lfsr_steps[j-1][0]) , lfsr_steps[j-1][14:1] };
end
endgenerate
endmodule
`default_nettype wire
|
`include "SVGA_DEFINES.v"
module COLOR_BARS
(
pixel_clock,
reset,
pixel_count0,
line_count0,
vga_red_data,
vga_green_data,
vga_blue_data
);
input pixel_clock;
input reset;
input [10:0] pixel_count0;
input [9:0] line_count0;
output vga_red_data;
output vga_green_data;
output vga_blue_data;
reg [10:0] pixel_count;
reg [9:0] line_count;
reg red_data;
reg green_data;
reg blue_data;
wire [2:0] write_data = {red_data, green_data, blue_data};
wire [2:0] read_data;
assign {vga_red_data, vga_green_data, vga_blue_data} = read_data;
// Create the color bars in memory, alternating memory locations every other
// line to allow for computation time.
// Only the least significant 10 bits are required out of the total 11 bits
// of pixel count, because active screen area has a maximum width of 1024.
// The remaining bits of pixel count are used to keep track of the front porch,
// synch, and back porch, which make up the blank period. It is OK that this
// module will output color data during the blank period, because the VIDEO_OUT
// module overrides the output of this module with zeros when the blank signal
// is high.
wire [10:0] write_addr = {!line_count0[0], pixel_count0[9:0]};
wire [10:0] read_addr = {line_count0[0], pixel_count0[9:0]};
wire write_enable = 1'b1; // write every clock posedge
reg [7:0] red_rainbow;
reg [7:0] green_rainbow;
reg [7:0] blue_rainbow;
// directions: 2'b00 == hold, 2'b01 == increase, 2'b10 == decrease
reg [1:0] red_direction;
reg [1:0] green_direction;
reg [1:0] blue_direction;
// compensate for the delay caused by displaying the previous line while
// calculating the current line by using a line counter that is one line
// ahead of the original line counter
always @ (posedge pixel_clock) begin
if ((line_count0 == (`V_TOTAL - 2)) & (pixel_count0 == (`H_TOTAL - 3)))
// last pixel in last line of frame, so reset line counter
line_count <= 10'h000;
else if (pixel_count0 == (`H_TOTAL - 3))
// last pixel but not last line, so increment line counter
line_count <= line_count + 1;
end
// compensate for putting the pixel_count generation and the code that
// checks it on the same clock edge
always @ (posedge pixel_clock) begin
if ((pixel_count0 == (`H_TOTAL - 3)))
// last pixel in last line of frame, so reset line counter
pixel_count <= 10'h000;
else
// last pixel but not last line, so increment line counter
pixel_count <= pixel_count + 1;
end
// cycle through all of the possible hues in a rainbow pattern
always @ (posedge pixel_clock) begin
// start last color bar at pure red
if (reset) begin
red_rainbow <= 8'hFF;
green_rainbow <= 8'h00;
blue_rainbow <= 8'h00;
red_direction <= 2'b00;
green_direction <= 2'b01;
blue_direction <= 2'b00;
end
else begin
// on the first line that is past the active region displayed,
// calculate the color for the last color bar
if ((pixel_count == 0) & (line_count == 480)) begin
if (red_direction[0]) begin
if (red_rainbow == 8'hFF) begin
red_direction <= 2'b00;
blue_direction <= 2'b10;
end
else
red_rainbow <= red_rainbow + 8'h01;
end
if (red_direction[1]) begin
if (red_rainbow == 8'h00) begin
red_direction <= 2'b00;
blue_direction <= 2'b01;
end
else
red_rainbow <= red_rainbow - 8'h01;
end
if (green_direction[0]) begin
if (green_rainbow == 8'hFF) begin
green_direction <= 2'b00;
red_direction <= 2'b10;
end
else
green_rainbow <= green_rainbow + 8'h01;
end
if (green_direction[1]) begin
if (green_rainbow == 8'h00) begin
green_direction <= 2'b00;
red_direction <= 2'b01;
end
else
green_rainbow <= green_rainbow - 8'h01;
end
if (blue_direction[0]) begin
if (blue_rainbow == 8'hFF) begin
blue_direction <= 2'b00;
green_direction <= 2'b10;
end
else
blue_rainbow <= blue_rainbow + 8'h01;
end
if (blue_direction[1]) begin
if (blue_rainbow == 8'h00) begin
blue_direction <= 2'b00;
green_direction <= 2'b01;
end
else
blue_rainbow <= blue_rainbow - 8'h01;
end
end
end
end
// select the color based on the horizontal position
always @ (posedge pixel_clock) begin
if (pixel_count < 79) begin //red
red_data <= 1'b1;
green_data <= 1'b0;
blue_data <= 1'b0;
end
else if ((pixel_count > 80) & (pixel_count < 159)) begin //yellow
red_data <= 1'b1;
green_data <= 1'b1;
blue_data <= 1'b0;
end
else if ((pixel_count > 160) & (pixel_count < 239)) begin //green
red_data <= 1'b0;
green_data <= 1'b1;
blue_data <= 1'b0;
end
else if ((pixel_count > 240) & (pixel_count < 319)) begin //cyan
red_data <= 1'b0;
green_data <= 1'b1;
blue_data <= 1'b1;
end
else if ((pixel_count > 320) & (pixel_count < 399)) begin //blue
red_data <= 1'b0;
green_data <= 1'b0;
blue_data <= 1'b1;
end
else if ((pixel_count > 400) & (pixel_count < 479)) begin //magenta
red_data <= 1'b1;
green_data <= 1'b0;
blue_data <= 1'b1;
end
else if ((pixel_count > 480) & (pixel_count < 559)) begin //white
red_data <= 1'b1;
green_data <= 1'b1;
blue_data <= 1'b1;
end
else if (pixel_count > 560) begin //rainbow pattern
red_data <= red_rainbow[7];
green_data <= green_rainbow[7];
blue_data <= blue_rainbow[7];
end
else begin //black
red_data <= 1'b0;
green_data <= 1'b0;
blue_data <= 1'b0;
end
end
// Instantiate the video RAM
VIDEO_RAM VIDEO_RAM
(
pixel_clock, // write clock
write_enable, // write eanble
write_addr, // write address
write_data, // write data
pixel_clock, // read clock
read_addr, // read address
read_data // read data
);
endmodule //COLOR_BARS |
`timescale 1 ns / 1 ps
module READ_ROM32 ( input[4:0] ADDR ,output[31:0] DATA_RE,output[31:0] DATA_IM);
reg [31:0] re[0:31];
initial begin
re[0] = 32'h00000000;re[1] = 32'hFFE4CC88;re[2] = 32'h002DA5B3;re[3] = 32'hFFCE9932;
re[4] = 32'h00254173;re[5] = 32'hFFF2E19A;re[6] = 32'hFFF0C26D;re[7] = 32'h0026B1CD;
re[8] = 32'hFFCE4E3A;re[9] = 32'h002CB328;re[10] = 32'hFFE6AE85;re[11] = 32'hFFFDC9B2;
re[12] = 32'h001D07D3;re[13] = 32'hFFD17EA5;re[14] = 32'h00310311;re[15] = 32'hFFDC4195;
re[16] = 32'h000AF8A5;re[17] = 32'h0011551D;re[18] = 32'hFFD7F13F;re[19] = 32'h0031E3D5;
re[20] = 32'hFFD455CB;re[21] = 32'h001762CC;re[22] = 32'h00046B81;re[23] = 32'hFFE13261;
re[24] = 32'h002F45B3;re[25] = 32'hFFCF793E;re[26] = 32'h00222978;re[27] = 32'hFFF7329D;
re[28] = 32'hFFEC9C0A;re[29] = 32'h002957A0;re[30] = 32'hFFCE0320;re[31] = 32'h002A8B5D;
end
reg [31:0] im[0:31];
initial begin
im[0] = 32'h00000000;im[1] = 32'h00000000;im[2] = 32'h00000000;im[3] = 32'h00000000;
im[4] = 32'h00000000;im[5] = 32'h00000000;im[6] = 32'h00000000;im[7] = 32'h00000000;
im[8] = 32'h00000000;im[9] = 32'h00000000;im[10] = 32'h00000000;im[11] = 32'h00000000;
im[12] = 32'h00000000;im[13] = 32'h00000000;im[14] = 32'h00000000;im[15] = 32'h00000000;
im[16] = 32'h00000000;im[17] = 32'h00000000;im[18] = 32'h00000000;im[19] = 32'h00000000;
im[20] = 32'h00000000;im[21] = 32'h00000000;im[22] = 32'h00000000;im[23] = 32'h00000000;
im[24] = 32'h00000000;im[25] = 32'h00000000;im[26] = 32'h00000000;im[27] = 32'h00000000;
im[28] = 32'h00000000;im[29] = 32'h00000000;im[30] = 32'h00000000;im[31] = 32'h00000000;
end
assign DATA_RE = re[ADDR];
assign DATA_IM = im[ADDR];
endmodule |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_dac_1c_2p (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
// vdma interface (for ddr-dds)
vdma_clk,
vdma_valid,
vdma_data,
vdma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack,
up_status,
// debug signals (vdma) for chipscope
vdma_dbg_data,
vdma_dbg_trigger,
// debug signals (dac) for chipscope
dac_div3_clk,
dac_dbg_data,
dac_dbg_trigger,
// delay clock (usually 200MHz)
delay_clk);
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
// vdma interface (for ddr-dds)
input vdma_clk;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
output [ 7:0] up_status;
// debug signals (vdma) for chipscope
output [198:0] vdma_dbg_data;
output [ 7:0] vdma_dbg_trigger;
// debug signals (dac) for chipscope
output dac_div3_clk;
output [292:0] dac_dbg_data;
output [ 7:0] dac_dbg_trigger;
// delay clock (usually 200MHz)
input delay_clk;
reg up_dds_sel = 'd0;
reg up_intp_enable = 'd0;
reg up_dds_enable = 'd0;
reg [15:0] up_dds_incr = 'd0;
reg [15:0] up_intp_scale_b = 'd0;
reg [15:0] up_intp_scale_a = 'd0;
reg [ 7:0] up_status = 'd0;
reg up_vdma_ovf_m1 = 'd0;
reg up_vdma_ovf_m2 = 'd0;
reg up_vdma_ovf = 'd0;
reg up_vdma_unf_m1 = 'd0;
reg up_vdma_unf_m2 = 'd0;
reg up_vdma_unf = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
wire up_wr_s;
wire up_ack_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire [13:0] dds_data_00_s;
wire [13:0] dds_data_01_s;
wire [13:0] dds_data_02_s;
wire [13:0] dds_data_03_s;
wire [13:0] dds_data_04_s;
wire [13:0] dds_data_05_s;
wire [13:0] dds_data_06_s;
wire [13:0] dds_data_07_s;
wire [13:0] dds_data_08_s;
wire [13:0] dds_data_09_s;
wire [13:0] dds_data_10_s;
wire [13:0] dds_data_11_s;
// processor write interface (see regmap.txt file for details of address definitions)
assign up_wr_s = up_sel & ~up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dds_sel <= 'd0;
up_intp_enable <= 'd0;
up_dds_enable <= 'd0;
up_dds_incr <= 'd0;
up_intp_scale_b <= 'd0;
up_intp_scale_a <= 'd0;
up_status <= 'd0;
up_vdma_ovf_m1 <= 'd0;
up_vdma_ovf_m2 <= 'd0;
up_vdma_ovf <= 'd0;
up_vdma_unf_m1 <= 'd0;
up_vdma_unf_m2 <= 'd0;
up_vdma_unf <= 'd0;
end else begin
if ((up_addr == 5'h01) && (up_wr_s == 1'b1)) begin
up_dds_sel <= up_wdata[18];
up_intp_enable <= up_wdata[17];
up_dds_enable <= up_wdata[16];
up_dds_incr <= up_wdata[15:0];
end
if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
up_intp_scale_b <= up_wdata[31:16];
up_intp_scale_a <= up_wdata[15:0];
end
up_status <= {5'd0, up_dds_sel, up_intp_enable, up_dds_enable};
up_vdma_ovf_m1 <= vdma_ovf_s;
up_vdma_ovf_m2 <= up_vdma_ovf_m1;
if (up_vdma_ovf_m2 == 1'b1) begin
up_vdma_ovf <= 1'b1;
end else if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_vdma_ovf <= up_vdma_ovf & (~up_wdata[1]);
end
up_vdma_unf_m1 <= vdma_unf_s;
up_vdma_unf_m2 <= up_vdma_unf_m1;
if (up_vdma_unf_m2 == 1'b1) begin
up_vdma_unf <= 1'b1;
end else if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_vdma_unf <= up_vdma_unf & (~up_wdata[0]);
end
end
end
// process read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= 32'h00010061;
5'h01: up_rdata <= {13'd0, up_dds_sel, up_intp_enable, up_dds_enable, up_dds_incr};
5'h06: up_rdata <= {up_intp_scale_b, up_intp_scale_a};
5'h09: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// DDS top, includes both DDR-DDS and Xilinx-DDS.
cf_dds_top i_dds_top (
.vdma_clk (vdma_clk),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.dac_div3_clk (dac_div3_clk),
.dds_data_00 (dds_data_00_s),
.dds_data_01 (dds_data_01_s),
.dds_data_02 (dds_data_02_s),
.dds_data_03 (dds_data_03_s),
.dds_data_04 (dds_data_04_s),
.dds_data_05 (dds_data_05_s),
.dds_data_06 (dds_data_06_s),
.dds_data_07 (dds_data_07_s),
.dds_data_08 (dds_data_08_s),
.dds_data_09 (dds_data_09_s),
.dds_data_10 (dds_data_10_s),
.dds_data_11 (dds_data_11_s),
.up_dds_sel (up_dds_sel),
.up_dds_incr (up_dds_incr),
.up_dds_enable (up_dds_enable),
.up_intp_enable (up_intp_enable),
.up_intp_scale_a (up_intp_scale_a),
.up_intp_scale_b (up_intp_scale_b),
.vdma_dbg_data (vdma_dbg_data),
.vdma_dbg_trigger (vdma_dbg_trigger),
.dac_dbg_data (dac_dbg_data),
.dac_dbg_trigger (dac_dbg_trigger));
// DAC interface, (transfer samples from low speed clock to the dac clock)
cf_dac_if i_dac_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_data_out_a_p (dac_data_out_a_p),
.dac_data_out_a_n (dac_data_out_a_n),
.dac_data_out_b_p (dac_data_out_b_p),
.dac_data_out_b_n (dac_data_out_b_n),
.dac_div3_clk (dac_div3_clk),
.dds_data_00 (dds_data_00_s),
.dds_data_01 (dds_data_01_s),
.dds_data_02 (dds_data_02_s),
.dds_data_03 (dds_data_03_s),
.dds_data_04 (dds_data_04_s),
.dds_data_05 (dds_data_05_s),
.dds_data_06 (dds_data_06_s),
.dds_data_07 (dds_data_07_s),
.dds_data_08 (dds_data_08_s),
.dds_data_09 (dds_data_09_s),
.dds_data_10 (dds_data_10_s),
.dds_data_11 (dds_data_11_s),
.up_dds_enable (up_dds_enable));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Hydra - An open source strand lighting controller
* (c) 2013-2014 Jon Evans <[email protected]>
* Released under the MIT License -- see LICENSE.txt for details.
*
* strand_driver.v - WS2801/WS2811 driver state machine
*
* Input clock is assumed to be 100 MHz, giving the following timings:
* WS2811 T0H = 50, T0L = 200, T1H = 120, T1L = 130
*
*
*
*/
module strand_driver (
clk,
rst_n,
ws2811_mode,
strand_length,
current_idx,
mem_data,
start_frame,
busy,
done,
strand_clk,
strand_data
);
parameter MEM_DATA_WIDTH = 24;
parameter STRAND_PARAM_WIDTH = 16;
input clk;
input rst_n;
// Parameter inputs (from registers)
input ws2811_mode;
input [STRAND_PARAM_WIDTH-1:0] strand_length;
// Current pixel index (used to control the pixel RAM)
output reg [STRAND_PARAM_WIDTH-1:0] current_idx;
// Data in from the pixel RAM
input [MEM_DATA_WIDTH-1:0] mem_data;
// Toggle high to begin the state machine
input start_frame;
// Control outputs
output reg busy;
output reg done;
// Outputs to IOB
output reg strand_clk;
output reg strand_data;
// Locals
reg [7:0] counter;
reg [7:0] counter_preset;
reg [7:0] bit_position;
reg [2:0] current_state;
reg [2:0] next_state;
reg [MEM_DATA_WIDTH-1:0] current_data;
reg strand_clk_i;
reg strand_data_i;
reg busy_i;
reg [7:0] bit_position_i;
reg [STRAND_PARAM_WIDTH-1:0] current_idx_i;
reg counter_set_i;
reg counter_running;
wire words_to_decode;
wire current_bit;
// FSM
localparam STATE_IDLE = 3'b000,
STATE_START = 3'b001,
STATE_UNPACK = 3'b010,
STATE_DECODE_1 = 3'b011,
STATE_DECODE_2 = 3'b100;
// Output timing
localparam T1H = 8'd120, // WS2811 1-bit high period
T1L = 8'd130,
T0H = 8'd50,
T0L = 8'd200,
TRESET = 8'd255,
TCLKDIV2 = 8'd10;
// State machine
always @(posedge clk) begin
if (rst_n == 1'b0) begin
current_idx <= { STRAND_PARAM_WIDTH {1'b0} };
current_data <= { MEM_DATA_WIDTH {1'b0} };
busy <= 1'b0;
done <= 1'b0;
strand_clk <= 1'b0;
strand_data <= 1'b0;
counter <= {8 {1'b0} };
bit_position <= {8 {1'b0} };
current_state <= STATE_IDLE;
counter_running <= 1'b0;
end
else begin
busy <= busy_i;
current_idx <= current_idx_i;
strand_clk <= strand_clk_i;
strand_data <= strand_data_i;
// Latch the new data word
if (current_state == STATE_UNPACK) begin
current_data <= mem_data;
bit_position <= {8 {1'b0} };
end else begin
bit_position <= bit_position_i;
end
// Manage the timing counter
if (counter_set_i == 1'b1) begin
counter <= counter_preset;
counter_running <= 1'b1;
end else begin
if (counter > 0) begin
counter <= counter - 1;
end else begin
counter_running <= 1'b0;
end
end
current_state <= next_state;
end
end
assign words_to_decode = (current_idx < strand_length);
assign current_bit = mem_data[bit_position];
// Next state process
always @(*) begin
next_state = current_state;
strand_data_i = strand_data;
strand_clk_i = strand_clk;
counter_preset = counter;
busy_i = busy;
bit_position_i = bit_position;
current_idx_i = current_idx;
case (current_state)
STATE_IDLE: begin
// Start transmission
if (start_frame == 1'b1) begin
next_state = STATE_START;
busy_i = 1'b1;
current_idx_i = { STRAND_PARAM_WIDTH {1'b0} };
bit_position_i = {8 {1'b0} };
end
end
STATE_START: begin
// Perform any one-time initialization
// TODO: does this need to exist?
current_idx_i = { STRAND_PARAM_WIDTH {1'b0} };
bit_position_i = {8 {1'b0} };
next_state = STATE_UNPACK;
end
STATE_UNPACK: begin
// Grab the next pixel word
if (words_to_decode == 1'b1) begin
next_state = STATE_DECODE_1;
end else begin
next_state = STATE_IDLE;
busy_i = 0;
end
// Reset the bit position counter at the beginning of each word
bit_position = {8 {1'b0} };
end
STATE_DECODE_1: begin
// First output phase.
if (ws2811_mode == 1'b1) begin
// WS2811? D <= 1, T <= (bit==1) ? T1H : T0H
if (current_bit == 1'b1) begin
counter_preset = T1H;
end else begin
counter_preset = T0H;
end
strand_data_i = 1'b1;
end else begin
// WS2812? D <= bit, C <= 0, T <= TCLKDIV2
strand_data_i = mem_data[bit_position];
strand_clk_i = 1'b0;
counter_preset = TCLKDIV2;
end
counter_set_i = !counter_running;
if (counter == 0 && counter_running) begin
next_state = STATE_DECODE_2;
end
end
STATE_DECODE_2: begin
// Second output phase.
// WS2811? D <= 0, T <= (bit==1) ? T1L: T0L
// WS2812? C <= 0, T <= TCLKDIV2
if (ws2811_mode == 1'b1) begin
if (mem_data[bit_position] == 1'b1) begin
counter_preset = T1L;
end else begin
counter_preset = T0L;
end
strand_data_i = 1'b0;
end else begin
// Toggle the clock high; data remains the same
strand_data_i = strand_data;
strand_clk_i = 1'b1;
counter_preset = TCLKDIV2;
end
// Advance the bit index
if (counter == 0 && counter_running) begin
if (bit_position < 8'd23) begin
next_state = STATE_DECODE_1;
bit_position_i = bit_position + 1;
end else begin
next_state = STATE_UNPACK;
current_idx_i = current_idx + 1;
end
end
counter_set_i = !counter_running;
end
endcase
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9434 (
// physical interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// delay interface
delay_clk,
// dma interface
adc_clk,
adc_enable,
adc_valid,
adc_data,
adc_dovf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
localparam SERIES7 = 0;
localparam SERIES6 = 1;
parameter PCORE_ID = 0;
parameter PCORE_DEVTYPE = SERIES7;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// physical interface
input adc_clk_in_p;
input adc_clk_in_n;
input [11:0] adc_data_in_p;
input [11:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_valid;
output adc_enable;
output [63:0] adc_data;
input adc_dovf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire mmcm_rst;
wire up_clk;
wire adc_clk;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s;
wire up_wack_s;
wire up_rack_s;
wire [ 1:0] up_status_pn_err_s;
wire [ 1:0] up_status_pn_oos_s;
wire [ 1:0] up_status_or_s;
wire adc_status_s;
wire [12:0] up_dld_s;
wire [64:0] up_dwdata_s;
wire [64:0] up_drdata_s;
wire delay_clk_s;
wire delay_rst;
wire delay_locked_s;
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire [47:0] adc_data_if_s;
wire adc_or_if_s;
// clock/reset assignments
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// single channel always enable
assign adc_enable = 1'b1;
axi_ad9434_if #(
.PCORE_DEVTYPE(PCORE_DEVTYPE),
.PCORE_IODELAY_GROUP(PCORE_IODELAY_GROUP))
i_if(
.adc_clk_in_p(adc_clk_in_p),
.adc_clk_in_n(adc_clk_in_n),
.adc_data_in_p(adc_data_in_p),
.adc_data_in_n(adc_data_in_n),
.adc_or_in_p(adc_or_in_p),
.adc_or_in_n(adc_or_in_n),
.adc_data(adc_data_if_s),
.adc_or(adc_or_if_s),
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_status(adc_status_s),
.up_clk (up_clk),
.up_adc_dld (up_dld_s),
.up_adc_dwdata (up_dwdata_s),
.up_adc_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.mmcm_rst(mmcm_rst),
.up_rstn(up_rstn),
.up_drp_sel(up_drp_sel_s),
.up_drp_wr(up_drp_wr_s),
.up_drp_addr(up_drp_addr_s),
.up_drp_wdata(up_drp_wdata_s),
.up_drp_rdata(up_drp_rdata_s),
.up_drp_ready(up_drp_ready_s),
.up_drp_locked(up_drp_locked_s));
// common processor control
axi_ad9434_core #(.PCORE_ID(PCORE_ID))
i_core (
.adc_clk(adc_clk),
.adc_data(adc_data_if_s),
.adc_or(adc_or_if_s),
.mmcm_rst (mmcm_rst),
.adc_rst (adc_rst),
.adc_status (adc_status_s),
.dma_dvalid (adc_valid),
.dma_data (adc_data),
.dma_dovf (adc_dovf),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_wack (up_wack_s),
.up_raddr (up_raddr_s),
.up_rreq (up_rreq_s),
.up_rack (up_rack_s));
endmodule
|
// ALU implementation
`include "verilog/mips_alu_defines.v"
module alu
(
input wire[31:0] opr_a_alu_i,
input wire[31:0] opr_b_alu_i,
input wire[5:0] op_alu_i,
output wire[31:0] res_alu_o,
output wire z_alu_o,
output wire n_alu_o
);
wire[31:0] res_alu;
wire z_alu;
wire n_alu;
wire v_alu;
wire[31:0] opr_b_negated_alu;
wire cin_alu;
wire[31:0] adder_out_alu;
wire carry_out_alu;
wire[31:0] logical_out_alu;
wire[31:0] shifter_out_alu;
wire comparator_out_alu;
assign res_alu_o = res_alu;
assign z_alu_o = z_alu;
assign n_alu_o = n_alu;
assign opr_b_negated_alu = op_alu_i[0] ? ~opr_b_alu_i : opr_b_alu_i;
assign cin_alu = op_alu_i[0];
assign z_alu = ~|adder_out_alu;
assign n_alu = (v_alu) ? opr_a_alu_i[31] : adder_out_alu[31];
assign res_alu = ((op_alu_i == `ADD_OP) || (op_alu_i == `SUB_OP)) ? adder_out_alu :
((op_alu_i == `SHL_OP) || (op_alu_i == `LSR_OP) || (op_alu_i == `ASR_OP)) ? shifter_out_alu :
((op_alu_i == `OR_OP) || (op_alu_i == `AND_OP) || (op_alu_i == `NOR_OP) || (op_alu_i == `XOR_OP)) ? logical_out_alu :
((op_alu_i == `SLTU_OP)) ? comparator_out_alu :
((op_alu_i == `SLT_OP)) ? {{31{1'b0}}, n_alu}:
31'hxxxx_xxxx;
adder A1 (
.op1 (opr_a_alu_i),
.op2 (opr_b_negated_alu),
.cin (cin_alu),
.sum (adder_out_alu),
.carry (carry_out_alu),
.v_flag (v_alu)
);
shifter S1 (
.op1 (opr_a_alu_i),
.shamt (opr_b_alu_i[5:0]),
.operation (op_alu_i[2:1]),
.res (shifter_out_alu)
);
logical L1 (
.op1 (opr_a_alu_i),
.op2 (opr_b_alu_i),
.operation (op_alu_i[5:3]),
.res (logical_out_alu)
);
comparator C1 (
.op1 (opr_a_alu_i),
.op2 (opr_b_alu_i),
.operation (op_alu_i[5:3]),
.res (comparator_out_alu)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A41O_BEHAVIORAL_PP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_BEHAVIORAL_PP_V |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 12
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "system_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "system_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=12,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=3,C_NUM_MASTER_SLOTS=1,C_AXI_ID_WIDTH=2,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000000000000,C_M_AXI_ADDR_WIDTH=0x0000001d,C_S_AXI_BASE_ID=0x000000020000000100000000,C_S_AXI_THREAD_ID_WIDTH=0x00000\
0000000000000000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000005,C_M_AXI_READ_CONNECTIVITY=0x00000003,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x000000000000000000000000,C_S_AXI_WRITE_ACCEPTANCE=0x000000020000000200000002,C_S_AXI_READ_ACCEPTANCE=0x000000020000000200000002,C_M_AXI_WRITE_ISSUING=0x00000008,C_M_AXI_READ_ISSUING=0x00000008,C_S_AXI_ARB_PRIORITY=0x000000000000000000\
000000,C_M_AXI_SECURE=0x00000000,C_CONNECTIVITY_MODE=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_xbar_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI AWID [1:0] [5:4]" *)
input wire [5 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI AWADDR [31:0] [95:64]" *)
input wire [95 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 S02_AXI AWLEN [7:0] [23:16]" *)
input wire [23 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI AWSIZE [2:0] [8:6]" *)
input wire [8 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI AWBURST [1:0] [5:4]" *)
input wire [5 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWLOCK [0:0] [2:2]" *)
input wire [2 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI AWCACHE [3:0] [11:8]" *)
input wire [11 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI AWPROT [2:0] [8:6]" *)
input wire [8 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI AWQOS [3:0] [11:8]" *)
input wire [11 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64], xilinx.com:interface:aximm:1.0 S02_AXI WDATA [63:0] [191:128]" *)
input wire [191 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8], xilinx.com:interface:aximm:1.0 S02_AXI WSTRB [7:0] [23:16]" *)
input wire [23 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WLAST [0:0] [2:2]" *)
input wire [2 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI BID [1:0] [5:4]" *)
output wire [5 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI BRESP [1:0] [5:4]" *)
output wire [5 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BVALID [0:0] [2:2]" *)
output wire [2 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BREADY [0:0] [2:2]" *)
input wire [2 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI ARID [1:0] [5:4]" *)
input wire [5 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI ARADDR [31:0] [95:64]" *)
input wire [95 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 S02_AXI ARLEN [7:0] [23:16]" *)
input wire [23 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI ARSIZE [2:0] [8:6]" *)
input wire [8 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI ARBURST [1:0] [5:4]" *)
input wire [5 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARLOCK [0:0] [2:2]" *)
input wire [2 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI ARCACHE [3:0] [11:8]" *)
input wire [11 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI ARPROT [2:0] [8:6]" *)
input wire [8 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI ARQOS [3:0] [11:8]" *)
input wire [11 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI RID [1:0] [5:4]" *)
output wire [5 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64], xilinx.com:interface:aximm:1.0 S02_AXI RDATA [63:0] [191:128]" *)
output wire [191 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI RRESP [1:0] [5:4]" *)
output wire [5 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RLAST [0:0] [2:2]" *)
output wire [2 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RVALID [0:0] [2:2]" *)
output wire [2 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RREADY [0:0] [2:2]" *)
input wire [2 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
output wire [1 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
output wire [0 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
input wire [1 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
output wire [1 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
input wire [1 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
input wire [0 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_12_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(3),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(2),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(64'H0000000000000000),
.C_M_AXI_ADDR_WIDTH(32'H0000001d),
.C_S_AXI_BASE_ID(96'H000000020000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(96'H000000000000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000005),
.C_M_AXI_READ_CONNECTIVITY(32'H00000003),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(96'H000000000000000000000000),
.C_S_AXI_WRITE_ACCEPTANCE(96'H000000020000000200000002),
.C_S_AXI_READ_ACCEPTANCE(96'H000000020000000200000002),
.C_M_AXI_WRITE_ISSUING(32'H00000008),
.C_M_AXI_READ_ISSUING(32'H00000008),
.C_S_AXI_ARB_PRIORITY(96'H000000000000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(3'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(6'H00),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(3'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(3'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module scheduler1_multi(clk, reset, wen, enablein, datain, dataout, full, empty, enableout);
parameter data_width = 32;
//parameter data_width1 = 34;
parameter data_width1 = 36;
parameter address_width = 7;
parameter FIFO_depth = 128;
parameter number_mapper = 2;
input clk,reset,wen,enablein;
input [data_width-1:0] datain;
output [data_width1-1:0] dataout;
output full,empty;
output enableout;
reg[address_width-1:0] write_p,read_p;
reg[address_width:0] counter;
reg[data_width-1:0] dataout1;
wire[data_width1-1:0] dataout;
reg [data_width-1:0] memory[FIFO_depth-1:0];
reg[data_width-1:0] keywordnumber,textfilenumber;
reg enableout1;
reg[3:0] routeraddress;
reg wen1;
reg [data_width-1:0] datain1;
reg ren;
reg[5:0]counter2,counter1,counter3,counter4;
reg[3:0] mapper_p;
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
wen1=0;
else
if(wen)
wen1=1;
else
if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
wen1=0;
else
wen1=wen1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
ren=0;
else
if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
ren=1;
else
if(write_p==read_p&&write_p>3)
ren=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
counter1=0;
else
if(ren&&counter1<2)
counter1=counter1+1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
dataout1=0;
else
if(wen1&&(write_p<FIFO_depth-1)&&(enableout1==1))
dataout1=dataout1+1;
else
dataout1=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
routeraddress=0;
else
if(wen1&&(write_p<FIFO_depth-1)&&(enableout1==1))
routeraddress=1;
else
if(ren&&(read_p<write_p)&&(write_p<FIFO_depth-1))
begin
if(mapper_p==1)
routeraddress=4'b1001;
else if(mapper_p==2)
routeraddress=4'b0110;
else if(mapper_p==3)
routeraddress=4;
else if(mapper_p==4)
routeraddress=5;
else if(mapper_p==5)
routeraddress=6;
else if(mapper_p==6)
routeraddress=7;
else if(mapper_p==7)
routeraddress=8;
else if(mapper_p==8)
routeraddress=9;
end
else
routeraddress=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
enableout1=0;
else
if(wen1)
enableout1=1;
else
if(ren&&(read_p<write_p-1))
enableout1=1;
else
enableout1=0;
end
always@(posedge clk,negedge reset)
begin
if(!ren)
mapper_p=0;
else if(ren&&mapper_p<number_mapper)
begin
if(counter4<number_mapper+1)
begin
if(counter3==1)
mapper_p=mapper_p+1;
else
mapper_p=mapper_p;
end
else
mapper_p=mapper_p+1;
end
else
begin
if(counter4<number_mapper+1)
mapper_p=mapper_p;
else
mapper_p=1;
end
end
always@(posedge clk,negedge reset)
begin
if(!ren)
counter4=0;
else if(ren&&(counter3==1)&&(counter4<number_mapper+1))
counter4=counter4+1;
else
counter4=counter4;
end
always@(posedge clk,negedge reset)
begin
if(!ren)
counter3=1;
else if(ren&&counter3<4)
counter3=counter3+1;
else
counter3=1;
end
always@(posedge clk,negedge reset)
begin
if(!ren)
counter2=0;
else if(ren&&counter2<(4*number_mapper))
counter2=counter2+1;
else
counter2=counter2;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
read_p=3;
else if(ren&&(read_p<write_p)&&(read_p<FIFO_depth)&&counter1==2)
begin
if(read_p<7)
read_p<=read_p+1;
else if(read_p==7&&(counter2!=(4*number_mapper)))
read_p=4;
else
read_p=read_p+1;
end
else
read_p=read_p;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
dataout1=0;
else if(ren&&(read_p<=write_p)&&(enableout1==1)&&counter1==2)
dataout1=memory[read_p];
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
write_p=0;
else
if(enablein&&(write_p<FIFO_depth-1))
write_p=write_p+1;
else
write_p=write_p;
end
always@(posedge clk)
begin
if(wen1&&enablein==1)
memory[write_p]=datain;
datain1=datain;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
counter=0;
else if(wen1&&!ren&&(counter!=FIFO_depth))
counter=counter+1;
else if(ren&&!wen1&&(counter!=0))
counter=counter-1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
keywordnumber=0;
else if (write_p>=3)
keywordnumber=memory[2];
else
keywordnumber=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
textfilenumber=0;
else if (write_p>=4)
textfilenumber=memory[3];
else
textfilenumber=0;
end
//*************
reg end_f;
always@(posedge clk or negedge reset)
if(!reset)
end_f <= 0;
else if(datain == 32'hffffffff)
end_f <= 1'b1;
else
end_f <= end_f;
//*************
assign full=(counter==(FIFO_depth-1));
assign empty=(counter==0);
//
//assign dataout[31:0]=dataout1;
//assign dataout[33:32]=routeraddress;
assign dataout[35:4]=dataout1;
assign dataout[3:0]=routeraddress;
//
assign enableout=enableout1;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_pixelq_op_img_data_stream_1_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_pixelq_op_img_data_stream_1_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_pixelq_op_img_data_stream_1_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_pixelq_op_img_data_stream_1_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`include "riscv_defines.v"
module riscv_core (
input clk,
input rstn,
//Instruction memory
output [`REG_W-1:0] imem_addr,
input [`INSTR_W-1:0] imem_rdata,
//Data memory
output [`REG_W-1:0] dmem_addr,
output dmem_cs,
output dmem_rnw,
output [(`DATA_W/8)-1:0] dmem_wmask,
output [`DATA_W-1:0] dmem_wdata,
input [`DATA_W-1:0] dmem_rdata,
//Misc
output stalled
);
localparam OPCODE_IMM = 7'b0010011;
localparam OPCODE_LUI = 7'b0110111;
localparam OPCODE_AUIPC = 7'b0010111;
localparam OPCODE_OP = 7'b0110011;
localparam OPCODE_JAL = 7'b1101111;
localparam OPCODE_JALR = 7'b1100111;
localparam OPCODE_BRANCH = 7'b1100011;
localparam OPCODE_LOAD = 7'b0000011;
localparam OPCODE_STORE = 7'b0100011;
localparam OPCODE_MISC_MEM = 7'b0001111;
localparam OPCODE_SYSTEM = 7'b1110011;
reg [`REG_W-1:0] pc_reg;
reg [`REG_W-1:0] reg_file [0:31];
reg [`REG_W-1:0] pc_nxt;
reg stall_back;
reg take_branch;
reg [`REG_W-1:0] target;
initial begin
stall_back = 0;
take_branch = 0;
end
//Instruction Fetch
assign imem_addr = pc_reg;
always @ (*) begin
if (stall_back) begin
pc_nxt = pc_reg;
end
else if (take_branch) begin
pc_nxt = target;
end
else begin
pc_nxt = pc_reg + 4;
end
end
always @ (posedge clk, negedge rstn) begin
if (rstn == 0) begin
pc_reg <= 'h0;
end
else begin
pc_reg <= pc_nxt;
end
end
wire [`REG_W-1:0] instr;
assign instr = imem_rdata;
//Decode
//Split the instruction into an ALU, mem and branch function
//Reg read
wire [31:0] rsj;
wire [31:0] rsk;
assign rsj = reg_file[rsj_sel];
assign rsk = reg_file[rsk_sel];
wire [4:0] rsj_sel;
wire [4:0] rsk_sel;
wire [4:0] rsd_sel;
assign rsd_sel = instr[11:7];
assign rsj_sel = instr[19:15];
assign rsk_sel = instr[24:20];
endmodule
`ifdef TB
module riscv_core_tb ();
reg clk;
reg rstn;
//Instruction memory
wire [`REG_W-1:0] imem_addr;
reg [`INSTR_W-1:0] imem_rdata;
//Data memory
wire [`REG_W-1:0] dmem_addr;
wire dmem_cs;
wire dmem_rnw;
wire [(`DATA_W/8)-1:0] dmem_wmask;
wire [`DATA_W-1:0] dmem_wdata;
reg [`DATA_W-1:0] dmem_rdata;
//Misc
wire stalled;
riscv_core dut (
.clk (clk),
.rstn (rstn),
.imem_addr (imem_addr),
.imem_rdata (imem_rdata),
.dmem_addr (dmem_addr),
.dmem_cs (dmem_cs),
.dmem_rnw (dmem_rnw),
.dmem_wmask (dmem_wmask),
.dmem_wdata (dmem_wdata),
.dmem_rdata (dmem_rdata),
.stalled (stalled)
);
initial begin
clk = 1;
rstn = 1;
#5 clk = 0;
rstn = 0;
#5 clk = 1;
rstn = 1;
forever begin
#5 clk = ~clk;
end
end
initial
$monitor("imem_addr : %x", imem_addr);
initial begin
$dumpfile("test.vcd");
$dumpvars(0,dut);
end
//reg [31:0] rand;
integer rand;
initial begin
repeat (20) begin
@ (posedge clk);
dut.take_branch = 0;
rand = $random;
if (rand[1:0] == 2'b11) begin
dut.take_branch = 1;
dut.target = rand;
$display("Branching to %x", dut.target);
end
end
$finish();
end
endmodule
`endif
|
`timescale 1ns/1ns
module sigma_delta
(input c_mod, // modulation clock
input mod_bit, // data bit from the modulator
input c, // the clock for the rest of the chip
input invert,
output [15:0] raw_d, // raw ADC word
output raw_dv,
output [15:0] d, // filtered ADC word (dumb for now)
output dv);
wire mod_bit_s; // synchronized modulator bit
sync mod_sync(.in(mod_bit), .clk(c_mod), .out(mod_bit_s));
wire invert_modclk;
sync invert_sync(.in(invert), .clk(c_mod), .out(invert_modclk));
// let's use a decimation ratio of 32 for now. This will give 11.4 ENOB
// and a settling time of 2.4 usec.
localparam W = 16;
localparam DECIM = 32;
wire [W-1:0] i0, i1, i2; // integrators
r #(W) int_0(.c(c_mod), .rst(1'b0), .en(1'b1), .d(i0 + mod_bit_s), .q(i0));
r #(W) int_1(.c(c_mod), .rst(1'b0), .en(1'b1), .d(i0 + i1), .q(i1));
r #(W) int_2(.c(c_mod), .rst(1'b0), .en(1'b1), .d(i1 + i2), .q(i2));
wire dec_match;
wire [7:0] dec_cnt;
r #(8) dec_cnt_r
(.c(c_mod), .rst(dec_match), .en(1'b1), .d(dec_cnt + 1'b1), .q(dec_cnt));
assign dec_match = dec_cnt == DECIM-1; //8'd3; //8'd31; // decimate by 32
wire [W-1:0] decim; // the simplest decimator possible
r #(W) decim_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(i2), .q(decim));
// now the differentiators
wire [W-1:0] d0, d1, d2;
wire [W-1:0] diff_0 = decim - d0;
wire [W-1:0] diff_1 = diff_0 - d1;
wire [W-1:0] diff_2 = diff_1 - d2;
r #(W) d0_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(decim), .q(d0));
r #(W) d1_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(diff_0), .q(d1));
r #(W) d2_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(diff_1), .q(d2));
wire raw_dv_d1;
d1 raw_dv_d1_r(.c(c_mod), .d(dec_match), .q(raw_dv_d1));
// delay things one clock cycle in order to meet timing
wire [15:0] raw_d_modclk; // data word, in the modulation-clock domain
wire raw_dv_modclk;
d1 #(16) raw_d_d1_r(.c(c_mod),
.d(invert_modclk ? 16'd32767 - diff_2 : diff_2),
.q(raw_d_modclk));
d1 raw_dv_d2_r(.c(c_mod), .d(raw_dv_d1), .q(raw_dv_modclk));
// clock it up to the rest of the logic speed
sync #(16) raw_d_s(.in(raw_d_modclk), .clk(c), .out(raw_d));
wire raw_dv_slow; // this signal will be synchronized to "c" but is high too long
sync #(.W(1), .S(3)) raw_dv_s(.in(raw_dv_modclk), .clk(c), .out(raw_dv_slow));
wire raw_dv_slow_d1;
d1 raw_dv_slow_d1_r(.c(c), .d(raw_dv_slow), .q(raw_dv_slow_d1));
assign raw_dv = raw_dv_slow & ~raw_dv_slow_d1; // high for only one cycle
//////////////////////////////////////
// now, implement a dumb placeholder filter. maybe in the future do something
// more sophisticated, but for now just average x32 to make a 19.531 kHz
// stream for feeding PWM
wire [4:0] sample_cnt;
r #(5) sample_cnt_r
(.c(c_mod), .en(raw_dv_modclk), .rst(1'b0),
.d(sample_cnt + 1'b1), .q(sample_cnt));
wire raw_dv_modclk_d1;
d1 raw_dv_modclk_d1_r(.c(c_mod), .d(raw_dv_modclk), .q(raw_dv_modclk_d1));
wire [21:0] accum_d, accum;
wire accum_en, accum_rst;
r #(22) accum_r
(.c(c_mod), .d(accum_d), .rst(accum_rst), .en(raw_dv_modclk), .q(accum));
assign accum_d = accum + {5'h0, raw_d};
assign accum_rst = sample_cnt == 5'h00 & raw_dv_modclk_d1;
wire [21:0] last_accum;
r #(22) last_accum_r
(.c(c_mod), .rst(1'b0), .en(accum_rst), .d(accum), .q(last_accum));
wire [15:0] filtered_modclk = last_accum[20:5]; // in the c_mod domain
wire filtered_dv_modclk;
d1 filtered_dv_d1_r(.c(c_mod), .d(accum_rst), .q(filtered_dv_modclk));
// clock it up to the rest of the logic speed
sync #(16) d_s(.in(filtered_modclk), .clk(c), .out(d));
wire dv_slow; // this signal will be synchronized to "c" but is high too long
sync #(.W(1), .S(3)) dv_s(.in(filtered_dv_modclk), .clk(c), .out(dv_slow));
wire dv_slow_d1;
d1 dv_slow_d1_r(.c(c), .d(dv_slow), .q(dv_slow_d1));
assign dv = dv_slow & ~dv_slow_d1; // high for only one cycle
endmodule
`ifdef test_sigma_delta
module sigma_delta_tb();
wire c, c_mod;
sim_clk #(20) clk_20(c_mod);
sim_clk #(125) clk_125(c);
wire [2:0] hi, lo;
wire [15:0] sd_d;
reg [1:0] all_bits [3999:0];
wire sd_dv;
reg mod_bit;
reg invert;
sigma_delta sd_inst
(.c_mod(c_mod), .c(c), .invert(invert), .mod_bit(mod_bit), .d(sd_d), .dv(sd_dv));
integer i;
initial begin
$readmemh("sigma_delta_test_data.txt", all_bits, 0, 3999);
$dumpfile("sigma_delta.lxt");
$dumpvars();
mod_bit = 1'b0;
invert = 1'b0;
for (i = 0; i < 4000; i = i + 1) begin
wait(c_mod);
wait(~c_mod);
mod_bit = all_bits[i][0];
end
$finish();
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_BLACKBOX_V
`define SKY130_FD_SC_HD__FILL_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 13:10:43 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.v
// Design : fifo_generator_rx_inst
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
empty, rd_data_count, wr_data_count, prog_full, prog_empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[63:0],full,empty,rd_data_count[9:0],wr_data_count[8:0],prog_full,prog_empty" */;
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
output [9:0]rd_data_count;
output [8:0]wr_data_count;
output prog_full;
output prog_empty;
endmodule
|
// ======================================================================
// PwmLedSensor_PPD42.v generated from TopDesign.cysch
// 05/10/2018 at 18:59
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_FAMILY_PSOC6 4
`define CYDEV_CHIP_FAMILY_FM0P 5
`define CYDEV_CHIP_FAMILY_FM3 6
`define CYDEV_CHIP_FAMILY_FM4 7
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_MEMBER_5B 2
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_MEMBER_5A 3
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_4G 4
`define CYDEV_CHIP_REVISION_4G_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4G_ES 17
`define CYDEV_CHIP_REVISION_4G_ES2 33
`define CYDEV_CHIP_MEMBER_4U 5
`define CYDEV_CHIP_REVISION_4U_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4E 6
`define CYDEV_CHIP_REVISION_4E_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0
`define CYDEV_CHIP_MEMBER_4O 7
`define CYDEV_CHIP_REVISION_4O_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4R 8
`define CYDEV_CHIP_REVISION_4R_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4T 9
`define CYDEV_CHIP_REVISION_4T_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4N 10
`define CYDEV_CHIP_REVISION_4N_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4S 11
`define CYDEV_CHIP_REVISION_4S_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4Q 12
`define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4D 13
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4J 14
`define CYDEV_CHIP_REVISION_4J_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4K 15
`define CYDEV_CHIP_REVISION_4K_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4V 16
`define CYDEV_CHIP_REVISION_4V_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4H 17
`define CYDEV_CHIP_REVISION_4H_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4A 18
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4F 19
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4P 20
`define CYDEV_CHIP_REVISION_4P_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4M 21
`define CYDEV_CHIP_REVISION_4M_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4L 22
`define CYDEV_CHIP_REVISION_4L_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4I 23
`define CYDEV_CHIP_REVISION_4I_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_6A 24
`define CYDEV_CHIP_REVISION_6A_ES 17
`define CYDEV_CHIP_REVISION_6A_PRODUCTION 33
`define CYDEV_CHIP_REVISION_6A_NO_UDB 33
`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25
`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26
`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27
`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_FM3 28
`define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_FM4 29
`define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 19
`define CYDEV_CHIP_REVISION_USED 0
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// BLE_v3_40(AutopopulateWhitelist=true, EnableExternalPAcontrol=false, EnableExternalPrepWriteBuff=false, EnableL2capLogicalChannels=true, EnableLinkLayerPrivacy=false, GapConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<CyGapConfiguration xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema">\r\n <DevAddress>00A050000000</DevAddress>\r\n <SiliconGeneratedAddress>true</SiliconGeneratedAddress>\r\n <MtuSize>23</MtuSize>\r\n <MaxTxPayloadSize>27</MaxTxPayloadSize>\r\n <MaxRxPayloadSize>27</MaxRxPayloadSize>\r\n <TxPowerLevel>0</TxPowerLevel>\r\n <TxPowerLevelConnection>0</TxPowerLevelConnection>\r\n <TxPowerLevelAdvScan>0</TxPowerLevelAdvScan>\r\n <SecurityConfig>\r\n <SecurityMode>SECURITY_MODE_1</SecurityMode>\r\n <SecurityLevel>NO_SECURITY</SecurityLevel>\r\n <StrictPairing>false</StrictPairing>\r\n <KeypressNotifications>false</KeypressNotifications>\r\n <IOCapability>DISPLAY</IOCapability>\r\n <PairingMethod>JUST_WORKS</PairingMethod>\r\n <Bonding>BOND</Bonding>\r\n <MaxBondedDevices>4</MaxBondedDevices>\r\n <AutoPopWhitelistBondedDev>true</AutoPopWhitelistBondedDev>\r\n <MaxWhitelistSize>8</MaxWhitelistSize>\r\n <EnableLinkLayerPrivacy>false</EnableLinkLayerPrivacy>\r\n <MaxResolvableDevices>8</MaxResolvableDevices>\r\n <EncryptionKeySize>16</EncryptionKeySize>\r\n </SecurityConfig>\r\n <AdvertisementConfig>\r\n <AdvScanMode>FAST_CONNECTION</AdvScanMode>\r\n <AdvFastScanInterval>\r\n <Minimum>1000</Minimum>\r\n <Maximum>1000</Maximum>\r\n </AdvFastScanInterval>\r\n <AdvReducedScanInterval>\r\n <Minimum>1000</Minimum>\r\n <Maximum>10240</Maximum>\r\n </AdvReducedScanInterval>\r\n <AdvDiscoveryMode>NON_DISCOVERABLE</AdvDiscoveryMode>\r\n <AdvType>NON_CONNECTABLE</AdvType>\r\n <AdvFilterPolicy>SCAN_REQUEST_ANY_CONNECT_REQUEST_ANY</AdvFilterPolicy>\r\n <AdvChannelMap>ALL</AdvChannelMap>\r\n <AdvFastTimeout>0</AdvFastTimeout>\r\n <AdvReducedTimeout>150</AdvReducedTimeout>\r\n <EnableReducedAdvertising>false</EnableReducedAdvertising>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </AdvertisementConfig>\r\n <ScanConfig>\r\n <ScanFastWindow>30</ScanFastWindow>\r\n <ScanFastInterval>30</ScanFastInterval>\r\n <ScanTimeout>30</ScanTimeout>\r\n <ScanReducedWindow>1125</ScanReducedWindow>\r\n <ScanReducedInterval>1280</ScanReducedInterval>\r\n <ScanReducedTimeout>150</ScanReducedTimeout>\r\n <EnableReducedScan>true</EnableReducedScan>\r\n <ScanDiscoveryMode>GENERAL</ScanDiscoveryMode>\r\n <ScanningState>ACTIVE</ScanningState>\r\n <ScanFilterPolicy>ACCEPT_ALL_ADV_PACKETS</ScanFilterPolicy>\r\n <DuplicateFiltering>false</DuplicateFiltering>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </ScanConfig>\r\n <AdvertisementPacket>\r\n <PacketType>ADVERTISEMENT</PacketType>\r\n <Items>\r\n <CyADStructure>\r\n <ADType>1</ADType>\r\n <ADData>04</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>9</ADType>\r\n <ADData>41:69:72:20:42:65:61:63:6F:6E</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>255</ADType>\r\n <ADData>31:01:00:00:00:00:00:00:00:00</ADData>\r\n </CyADStructure>\r\n </Items>\r\n <IncludedServicesServiceUuid />\r\n <IncludedServicesServiceSolicitation />\r\n <IncludedServicesServiceData />\r\n </AdvertisementPacket>\r\n <ScanResponsePacket>\r\n <PacketType>SCAN_RESPONSE</PacketType>\r\n <Items />\r\n <IncludedServicesServiceUuid />\r\n <IncludedServicesServiceSolicitation />\r\n <IncludedServicesServiceData />\r\n </ScanResponsePacket>\r\n</CyGapConfiguration>, HalBaudRate=115200, HalCtsEnable=true, HalCtsPolarity=0, HalRtsEnable=true, HalRtsPolarity=0, HalRtsTriggerLevel=4, HciMode=0, ImportFilePath=, KeypressNotifications=false, L2capMpsSize=23, L2capMtuSize=23, L2capNumChannels=1, L2capNumPsm=1, LLMaxRxPayloadSize=27, LLMaxTxPayloadSize=27, MaxAttrNoOfBuffer=1, MaxBondedDevices=4, MaxResolvableDevices=8, MaxWhitelistSize=8, Mode=0, ProfileConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<Profile xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema" ID="1" DisplayName="Custom" Name="Custom" Type="org.bluetooth.profile.custom">\r\n <CyProfileRole ID="2" DisplayName="Server" Name="Server">\r\n <CyService ID="3" DisplayName="Generic Access" Name="Generic Access" Type="org.bluetooth.service.generic_access" UUID="1800">\r\n <CyCharacteristic ID="4" DisplayName="Device Name" Name="Device Name" Type="org.bluetooth.characteristic.gap.device_name" UUID="2A00">\r\n <Field Name="Name">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>10</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>Air Beacon</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="5" DisplayName="Appearance" Name="Appearance" Type="org.bluetooth.characteristic.gap.appearance" UUID="2A01">\r\n <Field Name="Category">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>ENUM</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="7" DisplayName="Generic Attribute" Name="Generic Attribute" Type="org.bluetooth.service.generic_attribute" UUID="1801">\r\n <CyCharacteristic ID="8" DisplayName="Service Changed" Name="Service Changed" Type="org.bluetooth.characteristic.gatt.service_changed" UUID="2A05">\r\n <CyDescriptor ID="9" DisplayName="Client Characteristic Configuration" Name="Client Characteristic Configuration" Type="org.bluetooth.descriptor.gatt.client_characteristic_configuration" UUID="2902">\r\n <Field Name="Properties">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>3</Maximum>\r\n </Range>\r\n <ValueType>BITFIELD</ValueType>\r\n <Bit>\r\n <Index>0</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Notifications disabled" />\r\n <Enumeration key="1" value="Notifications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <Bit>\r\n <Index>1</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Indications disabled" />\r\n <Enumeration key="1" value="Indications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyDescriptor>\r\n <Field Name="Start of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="End of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="INDICATE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="10" DisplayName="Custom Service" Name="Custom Service" Type="org.bluetooth.service.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyCharacteristic ID="11" DisplayName="Custom Characteristic" Name="Custom Characteristic" Type="org.bluetooth.characteristic.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyDescriptor ID="12" DisplayName="Custom Descriptor" Name="Custom Descriptor" Type="org.bluetooth.descriptor.custom" UUID="0000000000001000800000805F9B34FB">\r\n <Field Name="New field">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="false" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyDescriptor>\r\n <Field Name="New field">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="BROADCAST" Present="false" Mandatory="false" />\r\n <Property Type="READ" Present="false" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITE_WITHOUT_RESPONSE" Present="false" Mandatory="false" />\r\n <Property Type="NOTIFY" Present="false" Mandatory="false" />\r\n <Property Type="INDICATE" Present="false" Mandatory="false" />\r\n <Property Type="AUTHENTICATED_SIGNED_WRITES" Present="false" Mandatory="false" />\r\n <Property Type="RELIABLE_WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITABLE_AUXILIARIES" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>NONE</AccessPermission>\r\n </Permission>\r\n </CyCharacteristic>\r\n <Declaration>PrimarySingleInstance</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <ProfileRoleIndex>0</ProfileRoleIndex>\r\n <RoleType>SERVER</RoleType>\r\n </CyProfileRole>\r\n <GapRole>BROADCASTER</GapRole>\r\n</Profile>, SharingMode=0, StackMode=3, StrictPairing=false, UseDeepSleep=true, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMMENT=, CY_COMPONENT_NAME=BLE_v3_40, CY_CONFIG_TITLE=BLE, CY_CONST_CONFIG=true, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=BLE_v3_40.pdf, CY_FITTER_NAME=BLE, CY_INSTANCE_SHORT_NAME=BLE, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=40, CY_PDL_DRIVER_NAME=, CY_PDL_DRIVER_REQ_VERSION=, CY_PDL_DRIVER_SUBGROUP=, CY_PDL_DRIVER_VARIANT=, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 4.2, INSTANCE_NAME=BLE, )
module BLE_v3_40_0 (
clk,
pa_en);
output clk;
output pa_en;
wire Net_55;
wire Net_60;
wire Net_53;
wire Net_102;
wire Net_101;
wire Net_100;
wire Net_99;
wire Net_98;
wire Net_97;
wire Net_96;
wire Net_95;
wire Net_94;
wire Net_93;
wire Net_92;
wire Net_91;
wire Net_72;
wire Net_71;
wire Net_70;
wire Net_90;
wire Net_89;
wire Net_88;
wire Net_15;
wire Net_14;
cy_m0s8_ble_v1_0 cy_m0s8_ble (
.interrupt(Net_15),
.rf_ext_pa_en(pa_en));
cy_isr_v1_0
#(.int_type(2'b10))
bless_isr
(.int_signal(Net_15));
cy_clock_v1_0
#(.id("34930e12-af9a-4d94-86a4-9071ff746fb7/5ae6fa4d-f41a-4a35-8821-7ce70389cb0c"),
.source_clock_id("9A908CA6-5BB3-4db0-B098-959E5D90882B"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(0))
LFCLK
(.clock_out(Net_53));
assign clk = Net_55 | Net_53;
assign Net_55 = 1'h0;
endmodule
// top
module top ;
wire Net_2582;
wire Net_2581;
electrical Net_2493;
electrical Net_2541;
electrical Net_3701;
electrical Net_3702;
cy_annotation_universal_v1_0 GND_1 (
.connect({
Net_2493
})
);
defparam GND_1.comp_name = "Gnd_v1_0";
defparam GND_1.port_names = "T1";
defparam GND_1.width = 1;
wire [0:0] tmpOE__PWM_IN_net;
wire [0:0] tmpFB_0__PWM_IN_net;
wire [0:0] tmpIO_0__PWM_IN_net;
wire [0:0] tmpINTERRUPT_0__PWM_IN_net;
electrical [0:0] tmpSIOVREF__PWM_IN_net;
cy_psoc3_pins_v1_10
#(.id("8d318d8b-cf7b-4b6b-b02c-ab1c5c49d0ba"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b1),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
PWM_IN
(.oe(tmpOE__PWM_IN_net),
.y({1'b0}),
.fb({tmpFB_0__PWM_IN_net[0:0]}),
.io({tmpIO_0__PWM_IN_net[0:0]}),
.siovref(tmpSIOVREF__PWM_IN_net),
.interrupt({tmpINTERRUPT_0__PWM_IN_net[0:0]}),
.annotation({Net_2541}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__PWM_IN_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
BLE_v3_40_0 BLE (
.clk(Net_2581),
.pa_en(Net_2582));
wire [0:0] tmpOE__STATUS_net;
wire [0:0] tmpFB_0__STATUS_net;
wire [0:0] tmpIO_0__STATUS_net;
wire [0:0] tmpINTERRUPT_0__STATUS_net;
electrical [0:0] tmpSIOVREF__STATUS_net;
cy_psoc3_pins_v1_10
#(.id("e851a3b9-efb8-48be-bbb8-b303b216c393"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
STATUS
(.oe(tmpOE__STATUS_net),
.y({1'b0}),
.fb({tmpFB_0__STATUS_net[0:0]}),
.io({tmpIO_0__STATUS_net[0:0]}),
.siovref(tmpSIOVREF__STATUS_net),
.interrupt({tmpINTERRUPT_0__STATUS_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__STATUS_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_annotation_universal_v1_0 L_1 (
.connect({
Net_2493,
Net_3701
})
);
defparam L_1.comp_name = "Inductor_v1_0";
defparam L_1.port_names = "T1, T2";
defparam L_1.width = 2;
cy_annotation_universal_v1_0 C_1 (
.connect({
Net_3701,
Net_3702
})
);
defparam C_1.comp_name = "Capacitor_v1_0";
defparam C_1.port_names = "T1, T2";
defparam C_1.width = 2;
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Int31 numbers defines indeed a cyclic structure : Z/(2^31)Z *)
(**
Author: Arnaud Spiwack (+ Pierre Letouzey)
*)
Require Import List.
Require Import Min.
Require Export Int31.
Require Import Znumtheory.
Require Import Zgcd_alt.
Require Import Zpow_facts.
Require Import CyclicAxioms.
Require Import Lia.
Local Open Scope nat_scope.
Local Open Scope int31_scope.
Local Hint Resolve Z.lt_gt Z.div_pos : zarith.
Section Basics.
(** * Basic results about [iszero], [shiftl], [shiftr] *)
Lemma iszero_eq0 : forall x, iszero x = true -> x=0.
Proof.
destruct x; simpl; intros.
repeat
match goal with H:(if ?d then _ else _) = true |- _ =>
destruct d; try discriminate
end.
reflexivity.
Qed.
Lemma iszero_not_eq0 : forall x, iszero x = false -> x<>0.
Proof.
intros x H Eq; rewrite Eq in H; simpl in *; discriminate.
Qed.
Lemma sneakl_shiftr : forall x,
x = sneakl (firstr x) (shiftr x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma sneakr_shiftl : forall x,
x = sneakr (firstl x) (shiftl x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma twice_zero : forall x,
twice x = 0 <-> twice_plus_one x = 1.
Proof.
destruct x; simpl in *; split;
intro H; injection H; intros; subst; auto.
Qed.
Lemma twice_or_twice_plus_one : forall x,
x = twice (shiftr x) \/ x = twice_plus_one (shiftr x).
Proof.
intros; case_eq (firstr x); intros.
destruct x; simpl in *; rewrite H; auto.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** * Iterated shift to the right *)
Definition nshiftr x := nat_rect _ x (fun _ => shiftr).
Lemma nshiftr_S :
forall n x, nshiftr x (S n) = shiftr (nshiftr x n).
Proof.
reflexivity.
Qed.
Lemma nshiftr_S_tail :
forall n x, nshiftr x (S n) = nshiftr (shiftr x) n.
Proof.
intros n; elim n; simpl; auto.
intros; now f_equal.
Qed.
Lemma nshiftr_n_0 : forall n, nshiftr 0 n = 0.
Proof.
induction n; simpl; auto.
rewrite IHn; auto.
Qed.
Lemma nshiftr_size : forall x, nshiftr x size = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftr_above_size : forall k x, size<=k ->
nshiftr x k = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftr_size; auto.
simpl; rewrite IHn; auto.
Qed.
(** * Iterated shift to the left *)
Definition nshiftl x := nat_rect _ x (fun _ => shiftl).
Lemma nshiftl_S :
forall n x, nshiftl x (S n) = shiftl (nshiftl x n).
Proof.
reflexivity.
Qed.
Lemma nshiftl_S_tail :
forall n x, nshiftl x (S n) = nshiftl (shiftl x) n.
Proof.
intros n; elim n; simpl; intros; now f_equal.
Qed.
Lemma nshiftl_n_0 : forall n, nshiftl 0 n = 0.
Proof.
induction n; simpl; auto.
rewrite IHn; auto.
Qed.
Lemma nshiftl_size : forall x, nshiftl x size = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftl_above_size : forall k x, size<=k ->
nshiftl x k = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftl_size; auto.
simpl; rewrite IHn; auto.
Qed.
Lemma firstr_firstl :
forall x, firstr x = firstl (nshiftl x (pred size)).
Proof.
destruct x; simpl; auto.
Qed.
Lemma firstl_firstr :
forall x, firstl x = firstr (nshiftr x (pred size)).
Proof.
destruct x; simpl; auto.
Qed.
(** More advanced results about [nshiftr] *)
Lemma nshiftr_predsize_0_firstl : forall x,
nshiftr x (pred size) = 0 -> firstl x = D0.
Proof.
destruct x; compute; intros H; injection H; intros; subst; auto.
Qed.
Lemma nshiftr_0_propagates : forall n p x, n <= p ->
nshiftr x n = 0 -> nshiftr x p = 0.
Proof.
intros.
replace p with ((p-n)+n)%nat by omega.
induction (p-n)%nat.
simpl; auto.
simpl; rewrite IHn0; auto.
Qed.
Lemma nshiftr_0_firstl : forall n x, n < size ->
nshiftr x n = 0 -> firstl x = D0.
Proof.
intros.
apply nshiftr_predsize_0_firstl.
apply nshiftr_0_propagates with n; auto; omega.
Qed.
(** * Some induction principles over [int31] *)
(** Not used for the moment. Are they really useful ? *)
Lemma int31_ind_sneakl : forall P : int31->Prop,
P 0 ->
(forall x d, P x -> P (sneakl d x)) ->
forall x, P x.
Proof.
intros.
assert (forall n, n<=size -> P (nshiftr x (size - n))).
induction n; intros.
rewrite nshiftr_size; auto.
rewrite sneakl_shiftr.
apply H0.
change (P (nshiftr x (S (size - S n)))).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; omega.
change x with (nshiftr x (size-size)); auto.
Qed.
Lemma int31_ind_twice : forall P : int31->Prop,
P 0 ->
(forall x, P x -> P (twice x)) ->
(forall x, P x -> P (twice_plus_one x)) ->
forall x, P x.
Proof.
induction x using int31_ind_sneakl; auto.
destruct d; auto.
Qed.
(** * Some generic results about [recr] *)
Section Recr.
(** [recr] satisfies the fixpoint equation used for its definition. *)
Variable (A:Type)(case0:A)(caserec:digits->int31->A->A).
Lemma recr_aux_eqn : forall n x, iszero x = false ->
recr_aux (S n) A case0 caserec x =
caserec (firstr x) (shiftr x) (recr_aux n A case0 caserec (shiftr x)).
Proof.
intros; simpl; rewrite H; auto.
Qed.
Lemma recr_aux_converges :
forall n p x, n <= size -> n <= p ->
recr_aux n A case0 caserec (nshiftr x (size - n)) =
recr_aux p A case0 caserec (nshiftr x (size - n)).
Proof.
induction n.
simpl minus; intros.
rewrite nshiftr_size; destruct p; simpl; auto.
intros.
destruct p.
inversion H0.
unfold recr_aux; fold recr_aux.
destruct (iszero (nshiftr x (size - S n))); auto.
f_equal.
change (shiftr (nshiftr x (size - S n))) with (nshiftr x (S (size - S n))).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; auto with arith.
Qed.
Lemma recr_eqn : forall x, iszero x = false ->
recr A case0 caserec x =
caserec (firstr x) (shiftr x) (recr A case0 caserec (shiftr x)).
Proof.
intros.
unfold recr.
change x with (nshiftr x (size - size)).
rewrite (recr_aux_converges size (S size)); auto with arith.
rewrite recr_aux_eqn; auto.
Qed.
(** [recr] is usually equivalent to a variant [recrbis]
written without [iszero] check. *)
Fixpoint recrbis_aux (n:nat)(A:Type)(case0:A)(caserec:digits->int31->A->A)
(i:int31) : A :=
match n with
| O => case0
| S next =>
let si := shiftr i in
caserec (firstr i) si (recrbis_aux next A case0 caserec si)
end.
Definition recrbis := recrbis_aux size.
Hypothesis case0_caserec : caserec D0 0 case0 = case0.
Lemma recrbis_aux_equiv : forall n x,
recrbis_aux n A case0 caserec x = recr_aux n A case0 caserec x.
Proof.
induction n; simpl; auto; intros.
case_eq (iszero x); intros; [ | f_equal; auto ].
rewrite (iszero_eq0 _ H); simpl; auto.
replace (recrbis_aux n A case0 caserec 0) with case0; auto.
clear H IHn; induction n; simpl; congruence.
Qed.
Lemma recrbis_equiv : forall x,
recrbis A case0 caserec x = recr A case0 caserec x.
Proof.
intros; apply recrbis_aux_equiv; auto.
Qed.
End Recr.
(** * Incrementation *)
Section Incr.
(** Variant of [incr] via [recrbis] *)
Let Incr (b : digits) (si rec : int31) :=
match b with
| D0 => sneakl D1 si
| D1 => sneakl D0 rec
end.
Definition incrbis_aux n x := recrbis_aux n _ In Incr x.
Lemma incrbis_aux_equiv : forall x, incrbis_aux size x = incr x.
Proof.
unfold incr, recr, incrbis_aux; fold Incr; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [incr] *)
Lemma incr_eqn1 :
forall x, firstr x = D0 -> incr x = twice_plus_one (shiftr x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_eqn2 :
forall x, firstr x = D1 -> incr x = twice (incr (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_twice : forall x, incr (twice x) = twice_plus_one x.
Proof.
intros.
rewrite incr_eqn1; destruct x; simpl; auto.
Qed.
Lemma incr_twice_plus_one_firstl :
forall x, firstl x = D0 -> incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** The previous result is actually true even without the
constraint on [firstl], but this is harder to prove
(see later). *)
End Incr.
(** * Conversion to [Z] : the [phi] function *)
Section Phi.
(** Variant of [phi] via [recrbis] *)
Let Phi := fun b (_:int31) =>
match b with D0 => Z.double | D1 => Z.succ_double end.
Definition phibis_aux n x := recrbis_aux n _ Z0 Phi x.
Lemma phibis_aux_equiv : forall x, phibis_aux size x = phi x.
Proof.
unfold phi, recr, phibis_aux; fold Phi; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [phi] *)
Lemma phi_eqn1 : forall x, firstr x = D0 ->
phi x = Z.double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_eqn2 : forall x, firstr x = D1 ->
phi x = Z.succ_double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_twice_firstl : forall x, firstl x = D0 ->
phi (twice x) = Z.double (phi x).
Proof.
intros.
rewrite phi_eqn1; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
Lemma phi_twice_plus_one_firstl : forall x, firstl x = D0 ->
phi (twice_plus_one x) = Z.succ_double (phi x).
Proof.
intros.
rewrite phi_eqn2; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
End Phi.
(** [phi x] is positive and lower than [2^31] *)
Lemma phibis_aux_pos : forall n x, (0 <= phibis_aux n x)%Z.
Proof.
induction n.
simpl; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr x)).
destruct (firstr x).
specialize IHn with (shiftr x); rewrite Z.double_spec; omega.
specialize IHn with (shiftr x); rewrite Z.succ_double_spec; omega.
Qed.
Lemma phibis_aux_bounded :
forall n x, n <= size ->
(phibis_aux n (nshiftr x (size-n)) < 2 ^ (Z.of_nat n))%Z.
Proof.
induction n.
simpl minus; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr x (size - S n)))).
assert (shiftr (nshiftr x (size - S n)) = nshiftr x (size-n)).
replace (size - n)%nat with (S (size - (S n))) by omega.
simpl; auto.
rewrite H0.
assert (H1 : n <= size) by omega.
specialize (IHn x H1).
set (y:=phibis_aux n (nshiftr x (size - n))) in *.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
case_eq (firstr (nshiftr x (size - S n))); intros.
rewrite Z.double_spec; auto with zarith.
rewrite Z.succ_double_spec; auto with zarith.
Qed.
Lemma phi_nonneg : forall x, (0 <= phi x)%Z.
Proof.
intros.
rewrite <- phibis_aux_equiv.
apply phibis_aux_pos.
Qed.
Hint Resolve phi_nonneg : zarith.
Lemma phi_bounded : forall x, (0 <= phi x < 2 ^ (Z.of_nat size))%Z.
Proof.
intros. split; [auto with zarith|].
rewrite <- phibis_aux_equiv.
change x with (nshiftr x (size-size)).
apply phibis_aux_bounded; auto.
Qed.
Lemma phibis_aux_lowerbound :
forall n x, firstr (nshiftr x n) = D1 ->
(2 ^ Z.of_nat n <= phibis_aux (S n) x)%Z.
Proof.
induction n.
intros.
unfold nshiftr in H; simpl in *.
unfold phibis_aux, recrbis_aux.
rewrite H, Z.succ_double_spec; omega.
intros.
remember (S n) as m.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux m (shiftr x)).
subst m.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
assert (2^(Z.of_nat n) <= phibis_aux (S n) (shiftr x))%Z.
apply IHn.
rewrite <- nshiftr_S_tail; auto.
destruct (firstr x).
change (Z.double (phibis_aux (S n) (shiftr x))) with
(2*(phibis_aux (S n) (shiftr x)))%Z.
omega.
rewrite Z.succ_double_spec; omega.
Qed.
Lemma phi_lowerbound :
forall x, firstl x = D1 -> (2^(Z.of_nat (pred size)) <= phi x)%Z.
Proof.
intros.
generalize (phibis_aux_lowerbound (pred size) x).
rewrite <- firstl_firstr.
change (S (pred size)) with size; auto.
rewrite phibis_aux_equiv; auto.
Qed.
(** * Equivalence modulo [2^n] *)
Section EqShiftL.
(** After killing [n] bits at the left, are the numbers equal ?*)
Definition EqShiftL n x y :=
nshiftl x n = nshiftl y n.
Lemma EqShiftL_zero : forall x y, EqShiftL O x y <-> x = y.
Proof.
unfold EqShiftL; intros; unfold nshiftl; simpl; split; auto.
Qed.
Lemma EqShiftL_size : forall k x y, size<=k -> EqShiftL k x y.
Proof.
red; intros; rewrite 2 nshiftl_above_size; auto.
Qed.
Lemma EqShiftL_le : forall k k' x y, k <= k' ->
EqShiftL k x y -> EqShiftL k' x y.
Proof.
unfold EqShiftL; intros.
replace k' with ((k'-k)+k)%nat by omega.
remember (k'-k)%nat as n.
clear Heqn H k'.
induction n; simpl; auto.
f_equal; auto.
Qed.
Lemma EqShiftL_firstr : forall k x y, k < size ->
EqShiftL k x y -> firstr x = firstr y.
Proof.
intros.
rewrite 2 firstr_firstl.
f_equal.
apply EqShiftL_le with k; auto.
unfold size.
auto with arith.
Qed.
Lemma EqShiftL_twice : forall k x y,
EqShiftL k (twice x) (twice y) <-> EqShiftL (S k) x y.
Proof.
intros; unfold EqShiftL.
rewrite 2 nshiftl_S_tail; split; auto.
Qed.
(** * From int31 to list of digits. *)
(** Lower (=rightmost) bits comes first. *)
Definition i2l := recrbis _ nil (fun d _ rec => d::rec).
Lemma i2l_length : forall x, length (i2l x) = size.
Proof.
intros; reflexivity.
Qed.
Fixpoint lshiftl l x :=
match l with
| nil => x
| d::l => sneakl d (lshiftl l x)
end.
Definition l2i l := lshiftl l On.
Lemma l2i_i2l : forall x, l2i (i2l x) = x.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakr : forall x d,
i2l (sneakr d x) = tail (i2l x) ++ d::nil.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakl : forall x d,
i2l (sneakl d x) = d :: removelast (i2l x).
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_l2i : forall l, length l = size ->
i2l (l2i l) = l.
Proof.
repeat (destruct l as [ |? l]; [intros; discriminate | ]).
destruct l; [ | intros; discriminate].
intros _; compute; auto.
Qed.
Fixpoint cstlist (A:Type)(a:A) n :=
match n with
| O => nil
| S n => a::cstlist _ a n
end.
Lemma i2l_nshiftl : forall n x, n<=size ->
i2l (nshiftl x n) = cstlist _ D0 n ++ firstn (size-n) (i2l x).
Proof.
induction n.
intros.
assert (firstn (size-0) (i2l x) = i2l x).
rewrite <- minus_n_O, <- (i2l_length x).
induction (i2l x); simpl; f_equal; auto.
rewrite H0; clear H0.
reflexivity.
intros.
rewrite nshiftl_S.
unfold shiftl; rewrite i2l_sneakl.
simpl cstlist.
rewrite <- app_comm_cons; f_equal.
rewrite IHn; [ | omega].
rewrite removelast_app.
apply f_equal.
replace (size-n)%nat with (S (size - S n))%nat by omega.
rewrite removelast_firstn; auto.
rewrite i2l_length; omega.
generalize (firstn_length (size-n) (i2l x)).
rewrite i2l_length.
intros H0 H1. rewrite H1 in H0.
rewrite min_l in H0 by omega.
simpl length in H0.
omega.
Qed.
(** [i2l] can be used to define a relation equivalent to [EqShiftL] *)
Lemma EqShiftL_i2l : forall k x y,
EqShiftL k x y <-> firstn (size-k) (i2l x) = firstn (size-k) (i2l y).
Proof.
intros.
destruct (le_lt_dec size k) as [Hle|Hlt].
split; intros.
replace (size-k)%nat with O by omega.
unfold firstn; auto.
apply EqShiftL_size; auto.
unfold EqShiftL.
assert (k <= size) by omega.
split; intros.
assert (i2l (nshiftl x k) = i2l (nshiftl y k)) by (f_equal; auto).
rewrite 2 i2l_nshiftl in H1; auto.
eapply app_inv_head; eauto.
assert (i2l (nshiftl x k) = i2l (nshiftl y k)).
rewrite 2 i2l_nshiftl; auto.
f_equal; auto.
rewrite <- (l2i_i2l (nshiftl x k)), <- (l2i_i2l (nshiftl y k)).
f_equal; auto.
Qed.
(** This equivalence allows proving easily the following delicate
result *)
Lemma EqShiftL_twice_plus_one : forall k x y,
EqShiftL k (twice_plus_one x) (twice_plus_one y) <-> EqShiftL (S k) x y.
Proof.
intros.
destruct (le_lt_dec size k) as [Hle|Hlt].
split; intros; apply EqShiftL_size; auto.
rewrite 2 EqShiftL_i2l.
unfold twice_plus_one.
rewrite 2 i2l_sneakl.
replace (size-k)%nat with (S (size - S k))%nat by omega.
remember (size - S k)%nat as n.
remember (i2l x) as lx.
remember (i2l y) as ly.
simpl.
rewrite 2 firstn_removelast.
split; intros.
injection H; auto.
f_equal; auto.
subst ly n; rewrite i2l_length; omega.
subst lx n; rewrite i2l_length; omega.
Qed.
Lemma EqShiftL_shiftr : forall k x y, EqShiftL k x y ->
EqShiftL (S k) (shiftr x) (shiftr y).
Proof.
intros.
destruct (le_lt_dec size (S k)) as [Hle|Hlt].
apply EqShiftL_size; auto.
case_eq (firstr x); intros.
rewrite <- EqShiftL_twice.
unfold twice; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
rewrite <- EqShiftL_twice_plus_one.
unfold twice_plus_one; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
Qed.
Lemma EqShiftL_incrbis : forall n k x y, n<=size ->
(n+k=S size)%nat ->
EqShiftL k x y ->
EqShiftL k (incrbis_aux n x) (incrbis_aux n y).
Proof.
induction n; simpl; intros.
red; auto.
destruct (eq_nat_dec k size).
subst k; apply EqShiftL_size; auto.
unfold incrbis_aux; simpl;
fold (incrbis_aux n (shiftr x)); fold (incrbis_aux n (shiftr y)).
rewrite (EqShiftL_firstr k x y); auto; try omega.
case_eq (firstr y); intros.
rewrite EqShiftL_twice_plus_one.
apply EqShiftL_shiftr; auto.
rewrite EqShiftL_twice.
apply IHn; try omega.
apply EqShiftL_shiftr; auto.
Qed.
Lemma EqShiftL_incr : forall x y,
EqShiftL 1 x y -> EqShiftL 1 (incr x) (incr y).
Proof.
intros.
rewrite <- 2 incrbis_aux_equiv.
apply EqShiftL_incrbis; auto.
Qed.
End EqShiftL.
(** * More equations about [incr] *)
Lemma incr_twice_plus_one :
forall x, incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto].
apply EqShiftL_incr.
red; destruct x; simpl; auto.
Qed.
Lemma incr_firstr : forall x, firstr (incr x) <> firstr x.
Proof.
intros.
case_eq (firstr x); intros.
rewrite incr_eqn1; auto.
destruct (shiftr x); simpl; discriminate.
rewrite incr_eqn2; auto.
destruct (incr (shiftr x)); simpl; discriminate.
Qed.
Lemma incr_inv : forall x y,
incr x = twice_plus_one y -> x = twice y.
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in *; simpl in *.
change (incr 0) with 1 in H.
symmetry; rewrite twice_zero; auto.
case_eq (firstr x); intros.
rewrite incr_eqn1 in H; auto.
clear H0; destruct x; destruct y; simpl in *.
injection H; intros; subst; auto.
elim (incr_firstr x).
rewrite H1, H; destruct y; simpl; auto.
Qed.
(** * Conversion from [Z] : the [phi_inv] function *)
(** First, recursive equations *)
Lemma phi_inv_double_plus_one : forall z,
phi_inv (Z.succ_double z) = twice_plus_one (phi_inv z).
Proof.
destruct z; simpl; auto.
induction p; simpl.
rewrite 2 incr_twice; auto.
rewrite incr_twice, incr_twice_plus_one.
f_equal.
apply incr_inv; auto.
auto.
Qed.
Lemma phi_inv_double : forall z,
phi_inv (Z.double z) = twice (phi_inv z).
Proof.
destruct z; simpl; auto.
rewrite incr_twice_plus_one; auto.
Qed.
Lemma phi_inv_incr : forall z,
phi_inv (Z.succ z) = incr (phi_inv z).
Proof.
destruct z.
simpl; auto.
simpl; auto.
induction p; simpl; auto.
rewrite <- Pos.add_1_r, IHp, incr_twice_plus_one; auto.
rewrite incr_twice; auto.
simpl; auto.
destruct p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
induction p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
Qed.
(** [phi_inv o inv], the always-exact and easy-to-prove trip :
from int31 to Z and then back to int31. *)
Lemma phi_inv_phi_aux :
forall n x, n <= size ->
phi_inv (phibis_aux n (nshiftr x (size-n))) =
nshiftr x (size-n).
Proof.
induction n.
intros; simpl minus.
rewrite nshiftr_size; auto.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr x (size-S n)))).
assert (shiftr (nshiftr x (size - S n)) = nshiftr x (size-n)).
replace (size - n)%nat with (S (size - (S n))); auto; omega.
rewrite H0.
case_eq (firstr (nshiftr x (size - S n))); intros.
rewrite phi_inv_double.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr x (size - S n)) as y.
destruct y; simpl in H1; rewrite H1; auto.
rewrite phi_inv_double_plus_one.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr x (size - S n)) as y.
destruct y; simpl in H1; rewrite H1; auto.
Qed.
Lemma phi_inv_phi : forall x, phi_inv (phi x) = x.
Proof.
intros.
rewrite <- phibis_aux_equiv.
replace x with (nshiftr x (size - size)) by auto.
apply phi_inv_phi_aux; auto.
Qed.
(** The other composition [phi o phi_inv] is harder to prove correct.
In particular, an overflow can happen, so a modulo is needed.
For the moment, we proceed via several steps, the first one
being a detour to [positive_to_in31]. *)
(** * [positive_to_int31] *)
(** A variant of [p2i] with [twice] and [twice_plus_one] instead of
[2*i] and [2*i+1] *)
Fixpoint p2ibis n p : (N*int31)%type :=
match n with
| O => (Npos p, On)
| S n => match p with
| xO p => let (r,i) := p2ibis n p in (r, twice i)
| xI p => let (r,i) := p2ibis n p in (r, twice_plus_one i)
| xH => (N0, In)
end
end.
Lemma p2ibis_bounded : forall n p,
nshiftr (snd (p2ibis n p)) n = 0.
Proof.
induction n.
simpl; intros; auto.
simpl p2ibis; intros.
destruct p; simpl snd.
specialize IHn with p.
destruct (p2ibis n p). simpl @snd in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n) as [Hle|Hlt].
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ Hlt IHn).
replace (shiftr (twice_plus_one i)) with i; auto.
destruct i; simpl in *. rewrite H; auto.
specialize IHn with p.
destruct (p2ibis n p); simpl @snd in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n) as [Hle|Hlt].
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ Hlt IHn).
replace (shiftr (twice i)) with i; auto.
destruct i; simpl in *; rewrite H; auto.
rewrite nshiftr_S_tail; auto.
replace (shiftr In) with 0; auto.
apply nshiftr_n_0.
Qed.
Local Open Scope Z_scope.
Lemma p2ibis_spec : forall n p, (n<=size)%nat ->
Zpos p = (Z.of_N (fst (p2ibis n p)))*2^(Z.of_nat n) +
phi (snd (p2ibis n p)).
Proof.
induction n; intros.
simpl; rewrite Pos.mul_1_r; auto.
replace (2^(Z.of_nat (S n)))%Z with (2*2^(Z.of_nat n))%Z by
(rewrite <- Z.pow_succ_r, <- Zpos_P_of_succ_nat;
auto with zarith).
rewrite (Z.mul_comm 2).
assert (n<=size)%nat by omega.
destruct p; simpl; [ | | auto];
specialize (IHn p H0);
generalize (p2ibis_bounded n p);
destruct (p2ibis n p) as (r,i); simpl in *; intros.
change (Zpos p~1) with (2*Zpos p + 1)%Z.
rewrite phi_twice_plus_one_firstl, Z.succ_double_spec.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
change (Zpos p~0) with (2*Zpos p)%Z.
rewrite phi_twice_firstl.
change (Z.double (phi i)) with (2*(phi i))%Z.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
Qed.
(** We now prove that this [p2ibis] is related to [phi_inv_positive] *)
Lemma phi_inv_positive_p2ibis : forall n p, (n<=size)%nat ->
EqShiftL (size-n) (phi_inv_positive p) (snd (p2ibis n p)).
Proof.
induction n.
intros.
apply EqShiftL_size; auto.
intros.
simpl p2ibis; destruct p; [ | | red; auto];
specialize IHn with p;
destruct (p2ibis n p); simpl @snd in *; simpl phi_inv_positive;
rewrite ?EqShiftL_twice_plus_one, ?EqShiftL_twice;
replace (S (size - S n))%nat with (size - n)%nat by omega;
apply IHn; omega.
Qed.
(** This gives the expected result about [phi o phi_inv], at least
for the positive case. *)
Lemma phi_phi_inv_positive : forall p,
phi (phi_inv_positive p) = (Zpos p) mod (2^(Z.of_nat size)).
Proof.
intros.
replace (phi_inv_positive p) with (snd (p2ibis size p)).
rewrite (p2ibis_spec size p) by auto.
rewrite Z.add_comm, Z_mod_plus.
symmetry; apply Zmod_small.
apply phi_bounded.
auto with zarith.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size p); auto.
Qed.
(** Moreover, [p2ibis] is also related with [p2i] and hence with
[positive_to_int31]. *)
Lemma double_twice_firstl : forall x, firstl x = D0 ->
(Twon*x = twice x)%int31.
Proof.
intros.
unfold mul31.
rewrite <- Z.double_spec, <- phi_twice_firstl, phi_inv_phi; auto.
Qed.
Lemma double_twice_plus_one_firstl : forall x, firstl x = D0 ->
(Twon*x+In = twice_plus_one x)%int31.
Proof.
intros.
rewrite double_twice_firstl; auto.
unfold add31.
rewrite phi_twice_firstl, <- Z.succ_double_spec,
<- phi_twice_plus_one_firstl, phi_inv_phi; auto.
Qed.
Lemma p2i_p2ibis : forall n p, (n<=size)%nat ->
p2i n p = p2ibis n p.
Proof.
induction n; simpl; auto; intros.
destruct p; auto; specialize IHn with p;
generalize (p2ibis_bounded n p);
rewrite IHn; try omega; destruct (p2ibis n p); simpl; intros;
f_equal; auto.
apply double_twice_plus_one_firstl.
apply (nshiftr_0_firstl n); auto; omega.
apply double_twice_firstl.
apply (nshiftr_0_firstl n); auto; omega.
Qed.
Lemma positive_to_int31_phi_inv_positive : forall p,
snd (positive_to_int31 p) = phi_inv_positive p.
Proof.
intros; unfold positive_to_int31.
rewrite p2i_p2ibis; auto.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size); auto.
Qed.
Lemma positive_to_int31_spec : forall p,
Zpos p = (Z.of_N (fst (positive_to_int31 p)))*2^(Z.of_nat size) +
phi (snd (positive_to_int31 p)).
Proof.
unfold positive_to_int31.
intros; rewrite p2i_p2ibis; auto.
apply p2ibis_spec; auto.
Qed.
(** Thanks to the result about [phi o phi_inv_positive], we can
now establish easily the most general results about
[phi o twice] and so one. *)
Lemma phi_twice : forall x,
phi (twice x) = (Z.double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double.
assert (0 <= Z.double (phi x)).
rewrite Z.double_spec; generalize (phi_bounded x); omega.
destruct (Z.double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_twice_plus_one : forall x,
phi (twice_plus_one x) = (Z.succ_double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double_plus_one.
assert (0 <= Z.succ_double (phi x)).
rewrite Z.succ_double_spec; generalize (phi_bounded x); omega.
destruct (Z.succ_double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_incr : forall x,
phi (incr x) = (Z.succ (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_incr.
assert (0 <= Z.succ (phi x)).
change (Z.succ (phi x)) with ((phi x)+1)%Z;
generalize (phi_bounded x); omega.
destruct (Z.succ (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
(** With the previous results, we can deal with [phi o phi_inv] even
in the negative case *)
Lemma phi_phi_inv_negative :
forall p, phi (incr (complement_negative p)) = (Zneg p) mod 2^(Z.of_nat size).
Proof.
induction p.
simpl complement_negative.
rewrite phi_incr in IHp.
rewrite incr_twice, phi_twice_plus_one.
remember (phi (complement_negative p)) as q.
rewrite Z.succ_double_spec.
replace (2*q+1) with (2*(Z.succ q)-1) by omega.
rewrite <- Zminus_mod_idemp_l, <- Zmult_mod_idemp_r, IHp.
rewrite Zmult_mod_idemp_r, Zminus_mod_idemp_l; auto with zarith.
simpl complement_negative.
rewrite incr_twice_plus_one, phi_twice.
remember (phi (incr (complement_negative p))) as q.
rewrite Z.double_spec, IHp, Zmult_mod_idemp_r; auto with zarith.
simpl; auto.
Qed.
Lemma phi_phi_inv :
forall z, phi (phi_inv z) = z mod 2 ^ (Z.of_nat size).
Proof.
destruct z.
simpl; auto.
apply phi_phi_inv_positive.
apply phi_phi_inv_negative.
Qed.
End Basics.
Instance int31_ops : ZnZ.Ops int31 :=
{
digits := 31%positive; (* number of digits *)
zdigits := 31; (* number of digits *)
to_Z := phi; (* conversion to Z *)
of_pos := positive_to_int31; (* positive -> N*int31 : p => N,i
where p = N*2^31+phi i *)
head0 := head031; (* number of head 0 *)
tail0 := tail031; (* number of tail 0 *)
zero := 0;
one := 1;
minus_one := Tn; (* 2^31 - 1 *)
compare := compare31;
eq0 := fun i => match i ?= 0 with Eq => true | _ => false end;
opp_c := fun i => 0 -c i;
opp := opp31;
opp_carry := fun i => 0-i-1;
succ_c := fun i => i +c 1;
add_c := add31c;
add_carry_c := add31carryc;
succ := fun i => i + 1;
add := add31;
add_carry := fun i j => i + j + 1;
pred_c := fun i => i -c 1;
sub_c := sub31c;
sub_carry_c := sub31carryc;
pred := fun i => i - 1;
sub := sub31;
sub_carry := fun i j => i - j - 1;
mul_c := mul31c;
mul := mul31;
square_c := fun x => x *c x;
div21 := div3121;
div_gt := div31; (* this is supposed to be the special case of
division a/b where a > b *)
div := div31;
modulo_gt := fun i j => let (_,r) := i/j in r;
modulo := fun i j => let (_,r) := i/j in r;
gcd_gt := gcd31;
gcd := gcd31;
add_mul_div := addmuldiv31;
pos_mod := (* modulo 2^p *)
fun p i =>
match p ?= 31 with
| Lt => addmuldiv31 p 0 (addmuldiv31 (31-p) i 0)
| _ => i
end;
is_even :=
fun i => let (_,r) := i/2 in
match r ?= 0 with Eq => true | _ => false end;
sqrt2 := sqrt312;
sqrt := sqrt31;
lor := lor31;
land := land31;
lxor := lxor31
}.
Section Int31_Specs.
Local Open Scope Z_scope.
Notation "[| x |]" := (phi x) (at level 0, x at level 99).
Local Notation wB := (2 ^ (Z.of_nat size)).
Lemma wB_pos : wB > 0.
Proof.
auto with zarith.
Qed.
Notation "[+| c |]" :=
(interp_carry 1 wB phi c) (at level 0, c at level 99).
Notation "[-| c |]" :=
(interp_carry (-1) wB phi c) (at level 0, c at level 99).
Notation "[|| x ||]" :=
(zn2z_to_Z wB phi x) (at level 0, x at level 99).
Lemma spec_zdigits : [| 31 |] = 31.
Proof.
reflexivity.
Qed.
Lemma spec_more_than_1_digit: 1 < 31.
Proof.
auto with zarith.
Qed.
Lemma spec_0 : [| 0 |] = 0.
Proof.
reflexivity.
Qed.
Lemma spec_1 : [| 1 |] = 1.
Proof.
reflexivity.
Qed.
Lemma spec_m1 : [| Tn |] = wB - 1.
Proof.
reflexivity.
Qed.
Lemma spec_compare : forall x y,
(x ?= y)%int31 = ([|x|] ?= [|y|]).
Proof. reflexivity. Qed.
(** Addition *)
Lemma spec_add_c : forall x y, [+|add31c x y|] = [|x|] + [|y|].
Proof.
intros; unfold add31c, add31, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y) mod wB ?= X+Y <> Eq -> [+|C1 (phi_inv (X+Y))|] = X+Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y) (-1) wB).
rewrite Zmod_small; lia.
generalize (Z.compare_eq ((X+Y) mod wB) (X+Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_succ_c : forall x, [+|add31c x 1|] = [|x|] + 1.
Proof.
intros; apply spec_add_c.
Qed.
Lemma spec_add_carry_c : forall x y, [+|add31carryc x y|] = [|x|] + [|y|] + 1.
Proof.
intros.
unfold add31carryc, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y+1) mod wB ?= X+Y+1 <> Eq -> [+|C1 (phi_inv (X+Y+1))|] = X+Y+1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y+1) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y+1) (-1) wB).
rewrite Zmod_small; lia.
generalize (Z.compare_eq ((X+Y+1) mod wB) (X+Y+1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_add : forall x y, [|x+y|] = ([|x|] + [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_add_carry :
forall x y, [|x+y+1|] = ([|x|] + [|y|] + 1) mod wB.
Proof.
unfold add31; intros.
repeat rewrite phi_phi_inv.
apply Zplus_mod_idemp_l.
Qed.
Lemma spec_succ : forall x, [|x+1|] = ([|x|] + 1) mod wB.
Proof.
intros; rewrite <- spec_1; apply spec_add.
Qed.
(** Substraction *)
Lemma spec_sub_c : forall x y, [-|sub31c x y|] = [|x|] - [|y|].
Proof.
unfold sub31c, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y) mod wB ?= X-Y <> Eq -> [-|C1 (phi_inv (X-Y))|] = X-Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y) 0).
rewrite <- (Z_mod_plus_full (X-Y) 1 wB).
rewrite Zmod_small; lia.
contradict H1; apply Zmod_small; lia.
generalize (Z.compare_eq ((X-Y) mod wB) (X-Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub_carry_c : forall x y, [-|sub31carryc x y|] = [|x|] - [|y|] - 1.
Proof.
unfold sub31carryc, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y-1) mod wB ?= X-Y-1 <> Eq -> [-|C1 (phi_inv (X-Y-1))|] = X-Y-1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y-1) 0).
rewrite <- (Z_mod_plus_full (X-Y-1) 1 wB).
rewrite Zmod_small; lia.
contradict H1; apply Zmod_small; lia.
generalize (Z.compare_eq ((X-Y-1) mod wB) (X-Y-1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub : forall x y, [|x-y|] = ([|x|] - [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_sub_carry :
forall x y, [|x-y-1|] = ([|x|] - [|y|] - 1) mod wB.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
apply Zminus_mod_idemp_l.
Qed.
Lemma spec_opp_c : forall x, [-|sub31c 0 x|] = -[|x|].
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_opp : forall x, [|0 - x|] = (-[|x|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_opp_carry : forall x, [|0 - x - 1|] = wB - [|x|] - 1.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
change [|1|] with 1; change [|0|] with 0.
rewrite <- (Z_mod_plus_full (0-[|x|]) 1 wB).
rewrite Zminus_mod_idemp_l.
rewrite Zmod_small; generalize (phi_bounded x); lia.
Qed.
Lemma spec_pred_c : forall x, [-|sub31c x 1|] = [|x|] - 1.
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_pred : forall x, [|x-1|] = ([|x|] - 1) mod wB.
Proof.
intros; apply spec_sub.
Qed.
(** Multiplication *)
Lemma phi2_phi_inv2 : forall x, [||phi_inv2 x||] = x mod (wB^2).
Proof.
assert (forall z, (z / wB) mod wB * wB + z mod wB = z mod wB ^ 2).
intros.
assert ((z/wB) mod wB = z/wB - (z/wB/wB)*wB).
rewrite (Z_div_mod_eq (z/wB) wB wB_pos) at 2; ring.
assert (z mod wB = z - (z/wB)*wB).
rewrite (Z_div_mod_eq z wB wB_pos) at 2; ring.
rewrite H.
rewrite H0 at 1.
ring_simplify.
rewrite Zdiv_Zdiv; auto with zarith.
rewrite (Z_div_mod_eq z (wB*wB)) at 2; auto with zarith.
change (wB*wB) with (wB^2); ring.
unfold phi_inv2.
destruct x; unfold zn2z_to_Z; rewrite ?phi_phi_inv;
change base with wB; auto.
Qed.
Lemma spec_mul_c : forall x y, [|| mul31c x y ||] = [|x|] * [|y|].
Proof.
unfold mul31c; intros.
rewrite phi2_phi_inv2.
apply Zmod_small.
generalize (phi_bounded x)(phi_bounded y); intros.
change (wB^2) with (wB * wB).
auto using Z.mul_lt_mono_nonneg with zarith.
Qed.
Lemma spec_mul : forall x y, [|x*y|] = ([|x|] * [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_square_c : forall x, [|| mul31c x x ||] = [|x|] * [|x|].
Proof.
intros; apply spec_mul_c.
Qed.
(** Division *)
Lemma spec_div21 : forall a1 a2 b,
wB/2 <= [|b|] ->
[|a1|] < [|b|] ->
let (q,r) := div3121 a1 a2 b in
[|a1|] *wB+ [|a2|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div3121; intros.
generalize (phi_bounded a1)(phi_bounded a2)(phi_bounded b); intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod (phi2 a1 a2) [|b|] H4) (Z_div_pos (phi2 a1 a2) [|b|] H4).
unfold Z.div; destruct (Z.div_eucl (phi2 a1 a2) [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
unfold phi2 in *.
change base with wB; change base with wB in H5.
change (Z.pow_pos 2 31) with wB; change (Z.pow_pos 2 31) with wB in H.
rewrite H5, Z.mul_comm.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split.
apply H7; change base with wB; auto with zarith.
apply Z.mul_lt_mono_pos_r with [|b|]; [omega| ].
rewrite Z.mul_comm.
apply Z.le_lt_trans with ([|b|]*z+z0); [omega| ].
rewrite <- H5.
apply Z.le_lt_trans with ([|a1|]*wB+(wB-1)); [omega | ].
replace ([|a1|]*wB+(wB-1)) with (wB*([|a1|]+1)-1) by ring.
assert (wB*([|a1|]+1) <= wB*[|b|]); try omega.
apply Z.mul_le_mono_nonneg; omega.
Qed.
Lemma spec_div : forall a b, 0 < [|b|] ->
let (q,r) := div31 a b in
[|a|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod [|a|] [|b|] H0) (Z_div_pos [|a|] [|b|] H0).
unfold Z.div; destruct (Z.div_eucl [|a|] [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
rewrite H1, Z.mul_comm.
generalize (phi_bounded a)(phi_bounded b); intros.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split; auto with zarith.
apply Z.le_lt_trans with [|a|]; auto with zarith.
rewrite H1.
apply Z.le_trans with ([|b|]*z); try omega.
rewrite <- (Z.mul_1_l z) at 1.
apply Z.mul_le_mono_nonneg; auto with zarith.
Qed.
Lemma spec_mod : forall a b, 0 < [|b|] ->
[|let (_,r) := (a/b)%int31 in r|] = [|a|] mod [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
unfold Z.modulo.
generalize (Z_div_mod [|a|] [|b|] H0).
destruct (Z.div_eucl [|a|] [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
generalize (phi_bounded b); intros.
apply Zmod_small; omega.
Qed.
Lemma phi_gcd : forall i j,
[|gcd31 i j|] = Zgcdn (2*size) [|j|] [|i|].
Proof.
unfold gcd31.
induction (2*size)%nat; intros.
reflexivity.
simpl euler.
unfold compare31.
change [|On|] with 0.
generalize (phi_bounded j)(phi_bounded i); intros.
case_eq [|j|]; intros.
simpl; intros.
generalize (Zabs_spec [|i|]); omega.
simpl. rewrite IHn, H1; f_equal.
rewrite spec_mod, H1; auto.
rewrite H1; compute; auto.
rewrite H1 in H; destruct H as [H _]; compute in H; elim H; auto.
Qed.
Lemma spec_gcd : forall a b, Zis_gcd [|a|] [|b|] [|gcd31 a b|].
Proof.
intros.
rewrite phi_gcd.
apply Zis_gcd_sym.
apply Zgcdn_is_gcd.
unfold Zgcd_bound.
generalize (phi_bounded b).
destruct [|b|].
unfold size; auto with zarith.
intros (_,H).
cut (Pos.size_nat p <= size)%nat; [ omega | rewrite <- Zpower2_Psize; auto].
intros (H,_); compute in H; elim H; auto.
Qed.
Lemma iter_int31_iter_nat : forall A f i a,
iter_int31 i A f a = iter_nat (Z.abs_nat [|i|]) A f a.
Proof.
intros.
unfold iter_int31.
rewrite <- recrbis_equiv; auto; unfold recrbis.
rewrite <- phibis_aux_equiv.
revert i a; induction size.
simpl; auto.
simpl; intros.
case_eq (firstr i); intros H; rewrite 2 IHn;
unfold phibis_aux; simpl; rewrite ?H; fold (phibis_aux n (shiftr i));
generalize (phibis_aux_pos n (shiftr i)); intros;
set (z := phibis_aux n (shiftr i)) in *; clearbody z;
rewrite <- nat_rect_plus.
f_equal.
rewrite Z.double_spec, <- Z.add_diag.
symmetry; apply Zabs2Nat.inj_add; auto with zarith.
change (iter_nat (S (Z.abs_nat z) + (Z.abs_nat z))%nat A f a =
iter_nat (Z.abs_nat (Z.succ_double z)) A f a); f_equal.
rewrite Z.succ_double_spec, <- Z.add_diag.
rewrite Zabs2Nat.inj_add; auto with zarith.
rewrite Zabs2Nat.inj_add; auto with zarith.
change (Z.abs_nat 1) with 1%nat; omega.
Qed.
Fixpoint addmuldiv31_alt n i j :=
match n with
| O => i
| S n => addmuldiv31_alt n (sneakl (firstl j) i) (shiftl j)
end.
Lemma addmuldiv31_equiv : forall p x y,
addmuldiv31 p x y = addmuldiv31_alt (Z.abs_nat [|p|]) x y.
Proof.
intros.
unfold addmuldiv31.
rewrite iter_int31_iter_nat.
set (n:=Z.abs_nat [|p|]); clearbody n; clear p.
revert x y; induction n.
simpl; auto.
intros.
simpl addmuldiv31_alt.
replace (S n) with (n+1)%nat by (rewrite plus_comm; auto).
rewrite nat_rect_plus; simpl; auto.
Qed.
Lemma spec_add_mul_div : forall x y p, [|p|] <= Zpos 31 ->
[| addmuldiv31 p x y |] =
([|x|] * (2 ^ [|p|]) + [|y|] / (2 ^ ((Zpos 31) - [|p|]))) mod wB.
Proof.
intros.
rewrite addmuldiv31_equiv.
assert ([|p|] = Z.of_nat (Z.abs_nat [|p|])).
rewrite Zabs2Nat.id_abs; symmetry; apply Z.abs_eq.
destruct (phi_bounded p); auto.
rewrite H0; rewrite H0 in H; clear H0; rewrite Zabs2Nat.id.
set (n := Z.abs_nat [|p|]) in *; clearbody n.
assert (n <= 31)%nat.
rewrite Nat2Z.inj_le; auto with zarith.
clear p H; revert x y.
induction n.
simpl Z.of_nat; intros.
rewrite Z.mul_1_r.
replace ([|y|] / 2^(31-0)) with 0.
rewrite Z.add_0_r.
symmetry; apply Zmod_small; apply phi_bounded.
symmetry; apply Zdiv_small; apply phi_bounded.
simpl addmuldiv31_alt; intros.
rewrite IHn; [ | omega ].
case_eq (firstl y); intros.
rewrite phi_twice, Z.double_spec.
rewrite phi_twice_firstl; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
f_equal.
f_equal.
ring.
replace (31-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv; auto with zarith.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
rewrite phi_twice_plus_one, Z.succ_double_spec.
rewrite phi_twice; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
rewrite Z.mul_add_distr_r, Z.mul_1_l, <- Z.add_assoc.
f_equal.
f_equal.
ring.
assert ((2*[|y|]) mod wB = 2*[|y|] - wB).
clear - H. symmetry. apply Zmod_unique with 1; [ | ring ].
generalize (phi_lowerbound _ H) (phi_bounded y).
set (wB' := 2^Z.of_nat (pred size)).
replace wB with (2*wB'); [ omega | ].
unfold wB'. rewrite <- Z.pow_succ_r, <- Nat2Z.inj_succ by (auto with zarith).
f_equal.
rewrite H1.
replace wB with (2^(Z.of_nat n)*2^(31-Z.of_nat n)) by
(rewrite <- Zpower_exp; auto with zarith; f_equal; unfold size; ring).
unfold Z.sub; rewrite <- Z.mul_opp_l.
rewrite Z_div_plus; auto with zarith.
ring_simplify.
replace (31+-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv; auto with zarith.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
Qed.
Lemma shift_unshift_mod_2 : forall n p a, 0 <= p <= n ->
((a * 2 ^ (n - p)) mod (2^n) / 2 ^ (n - p)) mod (2^n) =
a mod 2 ^ p.
Proof.
intros.
rewrite Zmod_small.
rewrite Zmod_eq by (auto with zarith).
unfold Z.sub at 1.
rewrite Z_div_plus_full_l
by (cut (0 < 2^(n-p)); auto with zarith).
assert (2^n = 2^(n-p)*2^p).
rewrite <- Zpower_exp by (auto with zarith).
replace (n-p+p) with n; auto with zarith.
rewrite H0.
rewrite <- Zdiv_Zdiv, Z_div_mult by (auto with zarith).
rewrite (Z.mul_comm (2^(n-p))), Z.mul_assoc.
rewrite <- Z.mul_opp_l.
rewrite Z_div_mult by (auto with zarith).
symmetry; apply Zmod_eq; auto with zarith.
remember (a * 2 ^ (n - p)) as b.
destruct (Z_mod_lt b (2^n)); auto with zarith.
split.
apply Z_div_pos; auto with zarith.
apply Zdiv_lt_upper_bound; auto with zarith.
apply Z.lt_le_trans with (2^n); auto with zarith.
rewrite <- (Z.mul_1_r (2^n)) at 1.
apply Z.mul_le_mono_nonneg; auto with zarith.
cut (0 < 2 ^ (n-p)); auto with zarith.
Qed.
Lemma spec_pos_mod : forall w p,
[|ZnZ.pos_mod p w|] = [|w|] mod (2 ^ [|p|]).
Proof.
unfold int31_ops, ZnZ.pos_mod, compare31.
change [|31|] with 31%Z.
assert (forall w p, 31<=p -> [|w|] = [|w|] mod 2^p).
intros.
generalize (phi_bounded w).
symmetry; apply Zmod_small.
split; auto with zarith.
apply Z.lt_le_trans with wB; auto with zarith.
apply Zpower_le_monotone; auto with zarith.
intros.
case_eq ([|p|] ?= 31); intros;
[ apply H; rewrite (Z.compare_eq _ _ H0); auto with zarith | |
apply H; change ([|p|]>31)%Z in H0; auto with zarith ].
change ([|p|]<31) in H0.
rewrite spec_add_mul_div by auto with zarith.
change [|0|] with 0%Z; rewrite Z.mul_0_l, Z.add_0_l.
generalize (phi_bounded p)(phi_bounded w); intros.
assert (31-[|p|]<wB).
apply Z.le_lt_trans with 31%Z; auto with zarith.
compute; auto.
assert ([|31-p|]=31-[|p|]).
unfold sub31; rewrite phi_phi_inv.
change [|31|] with 31%Z.
apply Zmod_small; auto with zarith.
rewrite spec_add_mul_div by (rewrite H4; auto with zarith).
change [|0|] with 0%Z; rewrite Zdiv_0_l, Z.add_0_r.
rewrite H4.
apply shift_unshift_mod_2; simpl; auto with zarith.
Qed.
(** Shift operations *)
Lemma spec_head00: forall x, [|x|] = 0 -> [|head031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl phi_inv.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint head031_alt n x :=
match n with
| O => 0%nat
| S n => match firstl x with
| D0 => S (head031_alt n (shiftl x))
| D1 => 0%nat
end
end.
Lemma head031_equiv :
forall x, [|head031 x|] = Z.of_nat (head031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold head031, recl.
change On with (phi_inv (Z.of_nat (31-size))).
replace (head031_alt size x) with
(head031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recl_aux; fold recl_aux.
unfold head031_alt; fold head031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; omega.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstl x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakr_shiftl x) in H.
rewrite H2 in H.
case_eq (iszero (shiftl x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma phi_nz : forall x, 0 < [|x|] <-> x <> 0%int31.
Proof.
split; intros.
red; intro; subst x; discriminate.
assert ([|x|]<>0%Z).
contradict H.
rewrite <- (phi_inv_phi x); rewrite H; auto.
generalize (phi_bounded x); auto with zarith.
Qed.
Lemma spec_head0 : forall x, 0 < [|x|] ->
wB/ 2 <= 2 ^ ([|head031 x|]) * [|x|] < wB.
Proof.
intros.
rewrite head031_equiv.
assert (nshiftl x size = 0%int31).
apply nshiftl_size.
revert x H H0.
unfold size at 2 5.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl head031_alt.
case_eq (firstl x); intros.
rewrite (Nat2Z.inj_succ (head031_alt n (shiftl x))), Z.pow_succ_r; auto with zarith.
rewrite <- Z.mul_assoc, Z.mul_comm, <- Z.mul_assoc, <-(Z.mul_comm 2).
rewrite <- Z.double_spec, <- (phi_twice_firstl _ H1).
apply IHn.
rewrite phi_nz; rewrite phi_nz in H; contradict H.
change twice with shiftl in H.
rewrite (sneakr_shiftl x), H1, H; auto.
rewrite <- nshiftl_S_tail; auto.
change (2^(Z.of_nat 0)) with 1; rewrite Z.mul_1_l.
generalize (phi_bounded x); unfold size; split; auto with zarith.
change (2^(Z.of_nat 31)/2) with (2^(Z.of_nat (pred size))).
apply phi_lowerbound; auto.
Qed.
Lemma spec_tail00: forall x, [|x|] = 0 -> [|tail031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl phi_inv.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint tail031_alt n x :=
match n with
| O => 0%nat
| S n => match firstr x with
| D0 => S (tail031_alt n (shiftr x))
| D1 => 0%nat
end
end.
Lemma tail031_equiv :
forall x, [|tail031 x|] = Z.of_nat (tail031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold tail031, recr.
change On with (phi_inv (Z.of_nat (31-size))).
replace (tail031_alt size x) with
(tail031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recr_aux; fold recr_aux.
unfold tail031_alt; fold tail031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; omega.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstr x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakl_shiftr x) in H.
rewrite H2 in H.
case_eq (iszero (shiftr x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma spec_tail0 : forall x, 0 < [|x|] ->
exists y, 0 <= y /\ [|x|] = (2 * y + 1) * (2 ^ [|tail031 x|]).
Proof.
intros.
rewrite tail031_equiv.
assert (nshiftr x size = 0%int31).
apply nshiftr_size.
revert x H H0.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl tail031_alt.
case_eq (firstr x); intros.
rewrite (Nat2Z.inj_succ (tail031_alt n (shiftr x))), Z.pow_succ_r; auto with zarith.
destruct (IHn (shiftr x)) as (y & Hy1 & Hy2).
rewrite phi_nz; rewrite phi_nz in H; contradict H.
rewrite (sneakl_shiftr x), H1, H; auto.
rewrite <- nshiftr_S_tail; auto.
exists y; split; auto.
rewrite phi_eqn1; auto.
rewrite Z.double_spec, Hy2; ring.
exists [|shiftr x|].
split.
generalize (phi_bounded (shiftr x)); auto with zarith.
rewrite phi_eqn2; auto.
rewrite Z.succ_double_spec; simpl; ring.
Qed.
(* Sqrt *)
(* Direct transcription of an old proof
of a fortran program in boyer-moore *)
Lemma quotient_by_2 a: a - 1 <= (a/2) + (a/2).
Proof.
case (Z_mod_lt a 2); auto with zarith.
intros H1; rewrite Zmod_eq_full; auto with zarith.
Qed.
Lemma sqrt_main_trick j k: 0 <= j -> 0 <= k ->
(j * k) + j <= ((j + k)/2 + 1) ^ 2.
Proof.
intros Hj; generalize Hj k; pattern j; apply natlike_ind;
auto; clear k j Hj.
intros _ k Hk; repeat rewrite Z.add_0_l.
apply Z.mul_nonneg_nonneg; generalize (Z_div_pos k 2); auto with zarith.
intros j Hj Hrec _ k Hk; pattern k; apply natlike_ind; auto; clear k Hk.
rewrite Z.mul_0_r, Z.add_0_r, Z.add_0_l.
generalize (sqr_pos (Z.succ j / 2)) (quotient_by_2 (Z.succ j));
unfold Z.succ.
rewrite Z.pow_2_r, Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
auto with zarith.
intros k Hk _.
replace ((Z.succ j + Z.succ k) / 2) with ((j + k)/2 + 1).
generalize (Hrec Hj k Hk) (quotient_by_2 (j + k)).
unfold Z.succ; repeat rewrite Z.pow_2_r;
repeat rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
repeat rewrite Z.mul_1_l; repeat rewrite Z.mul_1_r.
auto with zarith.
rewrite Z.add_comm, <- Z_div_plus_full_l; auto with zarith.
apply f_equal2 with (f := Z.div); auto with zarith.
Qed.
Lemma sqrt_main i j: 0 <= i -> 0 < j -> i < ((j + (i/j))/2 + 1) ^ 2.
Proof.
intros Hi Hj.
assert (Hij: 0 <= i/j) by (apply Z_div_pos; auto with zarith).
apply Z.lt_le_trans with (2 := sqrt_main_trick _ _ (Z.lt_le_incl _ _ Hj) Hij).
pattern i at 1; rewrite (Z_div_mod_eq i j); case (Z_mod_lt i j); auto with zarith.
Qed.
Lemma sqrt_init i: 1 < i -> i < (i/2 + 1) ^ 2.
Proof.
intros Hi.
assert (H1: 0 <= i - 2) by auto with zarith.
assert (H2: 1 <= (i / 2) ^ 2); auto with zarith.
replace i with (1* 2 + (i - 2)); auto with zarith.
rewrite Z.pow_2_r, Z_div_plus_full_l; auto with zarith.
generalize (sqr_pos ((i - 2)/ 2)) (Z_div_pos (i - 2) 2).
rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
auto with zarith.
generalize (quotient_by_2 i).
rewrite Z.pow_2_r in H2 |- *;
repeat (rewrite Z.mul_add_distr_r ||
rewrite Z.mul_add_distr_l ||
rewrite Z.mul_1_l || rewrite Z.mul_1_r).
auto with zarith.
Qed.
Lemma sqrt_test_true i j: 0 <= i -> 0 < j -> i/j >= j -> j ^ 2 <= i.
Proof.
intros Hi Hj Hd; rewrite Z.pow_2_r.
apply Z.le_trans with (j * (i/j)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt_test_false i j: 0 <= i -> 0 < j -> i/j < j -> (j + (i/j))/2 < j.
Proof.
intros Hi Hj H; case (Z.le_gt_cases j ((j + (i/j))/2)); auto.
intros H1; contradict H; apply Z.le_ngt.
assert (2 * j <= j + (i/j)); auto with zarith.
apply Z.le_trans with (2 * ((j + (i/j))/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt31_step_def rec i j:
sqrt31_step rec i j =
match (fst (i/j) ?= j)%int31 with
Lt => rec i (fst ((j + fst(i/j))/2))%int31
| _ => j
end.
Proof.
unfold sqrt31_step; case div31; intros.
simpl; case compare31; auto.
Qed.
Lemma div31_phi i j: 0 < [|j|] -> [|fst (i/j)%int31|] = [|i|]/[|j|].
intros Hj; generalize (spec_div i j Hj).
case div31; intros q r; simpl @fst.
intros (H1,H2); apply Zdiv_unique with [|r|]; auto with zarith.
rewrite H1; ring.
Qed.
Lemma sqrt31_step_correct rec i j:
0 < [|i|] -> 0 < [|j|] -> [|i|] < ([|j|] + 1) ^ 2 ->
2 * [|j|] < wB ->
(forall j1 : int31,
0 < [|j1|] < [|j|] -> [|i|] < ([|j1|] + 1) ^ 2 ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|sqrt31_step rec i j|] ^ 2 <= [|i|] < ([|sqrt31_step rec i j|] + 1) ^ 2.
Proof.
assert (Hp2: 0 < [|2|]) by exact (eq_refl Lt).
intros Hi Hj Hij H31 Hrec; rewrite sqrt31_step_def.
rewrite spec_compare, div31_phi; auto.
case Z.compare_spec; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
assert (E : [|(j + fst (i / j)%int31)|] = [|j|] + [|i|] / [|j|]).
{ rewrite spec_add, div31_phi; auto using Z.mod_small with zarith. }
apply Hrec; rewrite !div31_phi, E; auto using sqrt_main with zarith.
split; try apply sqrt_test_false; auto with zarith.
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj.
- replace ([|j|] + [|i|]/[|j|]) with
(1 * 2 + (([|j|] - 2) + [|i|] / [|j|])) by ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= [|i|]/ [|j|]) by auto with zarith.
assert (0 <= ([|j|] - 2 + [|i|] / [|j|]) / [|2|]); auto with zarith.
- rewrite <- Hj, Zdiv_1_r.
replace (1 + [|i|]) with (1 * 2 + ([|i|] - 1)) by ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|i|] - 1) /2) by auto with zarith.
change ([|2|]) with 2; auto with zarith.
Qed.
Lemma iter31_sqrt_correct n rec i j: 0 < [|i|] -> 0 < [|j|] ->
[|i|] < ([|j|] + 1) ^ 2 -> 2 * [|j|] < 2 ^ (Z.of_nat size) ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
[|i|] < ([|j1|] + 1) ^ 2 -> 2 * [|j1|] < 2 ^ (Z.of_nat size) ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|iter31_sqrt n rec i j|] ^ 2 <= [|i|] < ([|iter31_sqrt n rec i j|] + 1) ^ 2.
Proof.
revert rec i j; elim n; unfold iter31_sqrt; fold iter31_sqrt; clear n.
intros rec i j Hi Hj Hij H31 Hrec; apply sqrt31_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Z.pow_0_r; auto with zarith.
intros n Hrec rec i j Hi Hj Hij H31 HHrec.
apply sqrt31_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2 Hj31; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r.
apply Z.le_trans with (2 ^Z.of_nat n + [|j2|]); auto with zarith.
apply Nat2Z.is_nonneg.
Qed.
Lemma spec_sqrt : forall x,
[|sqrt31 x|] ^ 2 <= [|x|] < ([|sqrt31 x|] + 1) ^ 2.
Proof.
intros i; unfold sqrt31.
rewrite spec_compare. case Z.compare_spec; change [|1|] with 1;
intros Hi; auto with zarith.
repeat rewrite Z.pow_2_r; auto with zarith.
apply iter31_sqrt_correct; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
replace ([|i|]) with (1 * 2 + ([|i|] - 2))%Z; try ring.
assert (0 <= ([|i|] - 2)/2)%Z by (apply Z_div_pos; auto with zarith).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply sqrt_init; auto.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Z.le_lt_trans with ([|i|]).
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); auto.
intros j2 H1 H2; contradict H2; apply Z.lt_nge.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Z.le_lt_trans with ([|i|]); auto with zarith.
assert (0 <= [|i|]/2)%Z by (apply Z_div_pos; auto with zarith).
apply Z.le_trans with (2 * ([|i|]/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); unfold size; auto with zarith.
change [|0|] with 0; auto with zarith.
case (phi_bounded i); repeat rewrite Z.pow_2_r; auto with zarith.
Qed.
Lemma sqrt312_step_def rec ih il j:
sqrt312_step rec ih il j =
match (ih ?= j)%int31 with
Eq => j
| Gt => j
| _ =>
match (fst (div3121 ih il j) ?= j)%int31 with
Lt => let m := match j +c fst (div3121 ih il j) with
C0 m1 => fst (m1/2)%int31
| C1 m1 => (fst (m1/2) + v30)%int31
end in rec ih il m
| _ => j
end
end.
Proof.
unfold sqrt312_step; case div3121; intros.
simpl; case compare31; auto.
Qed.
Lemma sqrt312_lower_bound ih il j:
phi2 ih il < ([|j|] + 1) ^ 2 -> [|ih|] <= [|j|].
Proof.
intros H1.
case (phi_bounded j); intros Hbj _.
case (phi_bounded il); intros Hbil _.
case (phi_bounded ih); intros Hbih Hbih1.
assert ([|ih|] < [|j|] + 1); auto with zarith.
apply Z.square_lt_simpl_nonneg; auto with zarith.
rewrite <- ?Z.pow_2_r; apply Z.le_lt_trans with (2 := H1).
apply Z.le_trans with ([|ih|] * wB).
- rewrite ? Z.pow_2_r; auto with zarith.
- unfold phi2. change base with wB; auto with zarith.
Qed.
Lemma div312_phi ih il j: (2^30 <= [|j|] -> [|ih|] < [|j|] ->
[|fst (div3121 ih il j)|] = phi2 ih il/[|j|])%Z.
Proof.
intros Hj Hj1.
generalize (spec_div21 ih il j Hj Hj1).
case div3121; intros q r (Hq, Hr).
apply Zdiv_unique with (phi r); auto with zarith.
simpl @fst; apply eq_trans with (1 := Hq); ring.
Qed.
Lemma sqrt312_step_correct rec ih il j:
2 ^ 29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] < [|j|] -> phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|sqrt312_step rec ih il j|] ^ 2 <= phi2 ih il
< ([|sqrt312_step rec ih il j|] + 1) ^ 2.
Proof.
assert (Hp2: (0 < [|2|])%Z) by exact (eq_refl Lt).
intros Hih Hj Hij Hrec; rewrite sqrt312_step_def.
assert (H1: ([|ih|] <= [|j|])) by (apply sqrt312_lower_bound with il; auto).
case (phi_bounded ih); intros Hih1 _.
case (phi_bounded il); intros Hil1 _.
case (phi_bounded j); intros _ Hj1.
assert (Hp3: (0 < phi2 ih il)).
{ unfold phi2; apply Z.lt_le_trans with ([|ih|] * base); auto with zarith.
apply Z.mul_pos_pos; auto with zarith.
apply Z.lt_le_trans with (2:= Hih); auto with zarith. }
rewrite spec_compare. case Z.compare_spec; intros Hc1.
- split; auto.
apply sqrt_test_true; auto.
+ unfold phi2, base; auto with zarith.
+ unfold phi2; rewrite Hc1.
assert (0 <= [|il|]/[|j|]) by (apply Z_div_pos; auto with zarith).
rewrite Z.mul_comm, Z_div_plus_full_l; auto with zarith.
change base with wB. auto with zarith.
- case (Z.le_gt_cases (2 ^ 30) [|j|]); intros Hjj.
+ rewrite spec_compare; case Z.compare_spec;
rewrite div312_phi; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec.
* assert (Hf1: 0 <= phi2 ih il/ [|j|]) by auto with zarith.
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj;
[ | contradict Hc; apply Z.le_ngt;
rewrite <- Hj, Zdiv_1_r; auto with zarith ].
assert (Hf3: 0 < ([|j|] + phi2 ih il / [|j|]) / 2).
{ replace ([|j|] + phi2 ih il/ [|j|]) with
(1 * 2 + (([|j|] - 2) + phi2 ih il / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|j|] - 2 + phi2 ih il / [|j|]) / 2) ;
auto with zarith. }
assert (Hf4: ([|j|] + phi2 ih il / [|j|]) / 2 < [|j|]).
{ apply sqrt_test_false; auto with zarith. }
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
{ rewrite div31_phi; change [|2|] with 2; auto with zarith.
intros HH; rewrite HH; clear HH; auto with zarith. }
{ rewrite spec_add, div31_phi; change [|2|] with 2; auto.
rewrite Z.mul_1_l; intros HH.
rewrite Z.add_comm, <- Z_div_plus_full_l; auto with zarith.
change (phi v30 * 2) with (2 ^ Z.of_nat size).
rewrite HH, Zmod_small; auto with zarith. }
* replace (phi _) with (([|j|] + (phi2 ih il)/([|j|]))/2);
[ apply sqrt_main; auto with zarith | ].
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
{ rewrite div31_phi; auto with zarith.
intros HH; rewrite HH; auto with zarith. }
{ intros HH; rewrite <- HH.
change (1 * 2 ^ Z.of_nat size) with (phi (v30) * 2).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite Z.add_comm.
rewrite spec_add, Zmod_small.
- rewrite div31_phi; auto.
- split; auto with zarith.
+ case (phi_bounded (fst (r/2)%int31));
case (phi_bounded v30); auto with zarith.
+ rewrite div31_phi; change (phi 2) with 2; auto.
change (2 ^Z.of_nat size) with (base/2 + phi v30).
assert (phi r / 2 < base/2); auto with zarith.
apply Z.mul_lt_mono_pos_r with 2; auto with zarith.
change (base/2 * 2) with base.
apply Z.le_lt_trans with (phi r).
* rewrite Z.mul_comm; apply Z_mult_div_ge; auto with zarith.
* case (phi_bounded r); auto with zarith. }
+ contradict Hij; apply Z.le_ngt.
assert ((1 + [|j|]) <= 2 ^ 30); auto with zarith.
apply Z.le_trans with ((2 ^ 30) * (2 ^ 30)); auto with zarith.
* assert (0 <= 1 + [|j|]); auto with zarith.
apply Z.mul_le_mono_nonneg; auto with zarith.
* change ((2 ^ 30) * (2 ^ 30)) with ((2 ^ 29) * base).
apply Z.le_trans with ([|ih|] * base);
change wB with base in *; auto with zarith.
unfold phi2, base; auto with zarith.
- split; auto.
apply sqrt_test_true; auto.
+ unfold phi2, base; auto with zarith.
+ apply Z.le_ge; apply Z.le_trans with (([|j|] * base)/[|j|]).
* rewrite Z.mul_comm, Z_div_mult; auto with zarith.
* apply Z.ge_le; apply Z_div_ge; auto with zarith.
Qed.
Lemma iter312_sqrt_correct n rec ih il j:
2^29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|iter312_sqrt n rec ih il j|] ^ 2 <= phi2 ih il
< ([|iter312_sqrt n rec ih il j|] + 1) ^ 2.
Proof.
revert rec ih il j; elim n; unfold iter312_sqrt; fold iter312_sqrt; clear n.
intros rec ih il j Hi Hj Hij Hrec; apply sqrt312_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Z.pow_0_r; auto with zarith.
intros n Hrec rec ih il j Hi Hj Hij HHrec.
apply sqrt312_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r.
apply Z.le_trans with (2 ^Z.of_nat n + [|j2|]); auto with zarith.
apply Nat2Z.is_nonneg.
Qed.
(* Avoid expanding [iter312_sqrt] before variables in the context. *)
Strategy 1 [iter312_sqrt].
Lemma spec_sqrt2 : forall x y,
wB/ 4 <= [|x|] ->
let (s,r) := sqrt312 x y in
[||WW x y||] = [|s|] ^ 2 + [+|r|] /\
[+|r|] <= 2 * [|s|].
Proof.
intros ih il Hih; unfold sqrt312.
change [||WW ih il||] with (phi2 ih il).
assert (Hbin: forall s, s * s + 2* s + 1 = (s + 1) ^ 2) by
(intros s; ring).
assert (Hb: 0 <= base) by (red; intros HH; discriminate).
assert (Hi2: phi2 ih il < (phi Tn + 1) ^ 2).
{ change ((phi Tn + 1) ^ 2) with (2^62).
apply Z.le_lt_trans with ((2^31 -1) * base + (2^31 - 1)); auto with zarith.
2: simpl; unfold Z.pow_pos; simpl; auto with zarith.
case (phi_bounded ih); case (phi_bounded il); intros H1 H2 H3 H4.
unfold base, Z.pow, Z.pow_pos in H2,H4; simpl in H2,H4.
unfold phi2. cbn [Z.pow Z.pow_pos Pos.iter]. auto with zarith. }
case (iter312_sqrt_correct 31 (fun _ _ j => j) ih il Tn); auto with zarith.
change [|Tn|] with 2147483647; auto with zarith.
intros j1 _ HH; contradict HH.
apply Z.lt_nge.
change [|Tn|] with 2147483647; auto with zarith.
change (2 ^ Z.of_nat 31) with 2147483648; auto with zarith.
case (phi_bounded j1); auto with zarith.
set (s := iter312_sqrt 31 (fun _ _ j : int31 => j) ih il Tn).
intros Hs1 Hs2.
generalize (spec_mul_c s s); case mul31c.
simpl zn2z_to_Z; intros HH.
assert ([|s|] = 0).
{ symmetry in HH. rewrite Z.mul_eq_0 in HH. destruct HH; auto. }
contradict Hs2; apply Z.le_ngt; rewrite H.
change ((0 + 1) ^ 2) with 1.
apply Z.le_trans with (2 ^ Z.of_nat size / 4 * base).
simpl; auto with zarith.
apply Z.le_trans with ([|ih|] * base); auto with zarith.
unfold phi2; case (phi_bounded il); auto with zarith.
intros ih1 il1.
change [||WW ih1 il1||] with (phi2 ih1 il1).
intros Hihl1.
generalize (spec_sub_c il il1).
case sub31c; intros il2 Hil2.
rewrite spec_compare; case Z.compare_spec.
unfold interp_carry in *.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; ring[Hil2 H1].
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite H1, Hil2; ring.
unfold interp_carry.
intros H1; contradict Hs1.
apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); intros _ H2.
apply Z.lt_le_trans with (([|ih|] + 1) * base + 0).
rewrite Z.mul_add_distr_r, Z.add_0_r; auto with zarith.
case (phi_bounded il1); intros H3 _.
apply Z.add_le_mono; auto with zarith.
unfold interp_carry in *; change (1 * 2 ^ Z.of_nat size) with base.
rewrite Z.pow_2_r, <- Hihl1, Hil2.
intros H1.
rewrite <- Z.le_succ_l, <- Z.add_1_r in H1.
Z.le_elim H1.
contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
case (phi_bounded il); intros Hpil _.
assert (Hl1l: [|il1|] <= [|il|]).
{ case (phi_bounded il2); rewrite Hil2; auto with zarith. }
assert ([|ih1|] * base + 2 * [|s|] + 1 <= [|ih|] * base); auto with zarith.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
case (phi_bounded ih1); intros Hpih1 _; auto with zarith.
apply Z.le_trans with (([|ih1|] + 2) * base); auto with zarith.
rewrite Z.mul_add_distr_r.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
rewrite Hihl1, Hbin; auto.
split.
unfold phi2; rewrite <- H1; ring.
replace (base + ([|il|] - [|il1|])) with (phi2 ih il - ([|s|] * [|s|])).
rewrite <-Hbin in Hs2; auto with zarith.
rewrite <- Hihl1; unfold phi2; rewrite <- H1; ring.
unfold interp_carry in Hil2 |- *.
unfold interp_carry; change (1 * 2 ^ Z.of_nat size) with base.
assert (Hsih: [|ih - 1|] = [|ih|] - 1).
{ rewrite spec_sub, Zmod_small; auto; change [|1|] with 1.
case (phi_bounded ih); intros H1 H2.
generalize Hih; change (2 ^ Z.of_nat size / 4) with 536870912.
split; auto with zarith. }
rewrite spec_compare; case Z.compare_spec.
rewrite Hsih.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; rewrite <-H1.
transitivity ([|ih|] * base + [|il1|] + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2.
rewrite <-H1.
ring_simplify.
transitivity (base + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
rewrite Hsih; intros H1.
assert (He: [|ih|] = [|ih1|]).
{ apply Z.le_antisymm; auto with zarith.
case (Z.le_gt_cases [|ih1|] [|ih|]); auto; intros H2.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); change (2 ^ Z.of_nat size) with base;
intros _ Hpil1.
apply Z.lt_le_trans with (([|ih|] + 1) * base).
rewrite Z.mul_add_distr_r, Z.mul_1_l; auto with zarith.
case (phi_bounded il1); intros Hpil2 _.
apply Z.le_trans with (([|ih1|]) * base); auto with zarith. }
rewrite Z.pow_2_r, <-Hihl1; unfold phi2; rewrite <-He.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2; rewrite He.
assert (phi il - phi il1 < 0); auto with zarith.
rewrite <-Hil2.
case (phi_bounded il2); auto with zarith.
intros H1.
rewrite Z.pow_2_r, <-Hihl1.
assert (H2 : [|ih1|]+2 <= [|ih|]); auto with zarith.
Z.le_elim H2.
contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
assert ([|ih1|] * base + 2 * phi s + 1 <= [|ih|] * base + ([|il|] - [|il1|]));
auto with zarith.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base).
case (phi_bounded il2); intros Hpil2 _.
apply Z.le_trans with ([|ih|] * base + - base); auto with zarith.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
apply Z.le_trans with ([|ih1|] * base + 2 * base); auto with zarith.
assert (Hi: ([|ih1|] + 3) * base <= [|ih|] * base); auto with zarith.
rewrite Z.mul_add_distr_r in Hi; auto with zarith.
rewrite Hihl1, Hbin; auto.
unfold phi2; rewrite <-H2.
split.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
replace (base + [|il2|]) with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite <-H2.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
Qed.
(** [iszero] *)
Lemma spec_eq0 : forall x, ZnZ.eq0 x = true -> [|x|] = 0.
Proof.
clear; unfold ZnZ.eq0, int31_ops.
unfold compare31; intros.
change [|0|] with 0 in H.
apply Z.compare_eq.
now destruct ([|x|] ?= 0).
Qed.
(* Even *)
Lemma spec_is_even : forall x,
if ZnZ.is_even x then [|x|] mod 2 = 0 else [|x|] mod 2 = 1.
Proof.
unfold ZnZ.is_even, int31_ops; intros.
generalize (spec_div x 2).
destruct (x/2)%int31 as (q,r); intros.
unfold compare31.
change [|2|] with 2 in H.
change [|0|] with 0.
destruct H; auto with zarith.
replace ([|x|] mod 2) with [|r|].
destruct H; auto with zarith.
case Z.compare_spec; auto with zarith.
apply Zmod_unique with [|q|]; auto with zarith.
Qed.
(* Bitwise *)
Lemma log2_phi_bounded x : Z.log2 [|x|] < Z.of_nat size.
Proof.
destruct (phi_bounded x) as (H,H').
Z.le_elim H.
- now apply Z.log2_lt_pow2.
- now rewrite <- H.
Qed.
Lemma spec_lor x y : [| ZnZ.lor x y |] = Z.lor [|x|] [|y|].
Proof.
unfold ZnZ.lor,int31_ops. unfold lor31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.lor_nonneg; split; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
rewrite Z.log2_lor; try apply phi_bounded.
apply Z.max_lub_lt; apply log2_phi_bounded.
Qed.
Lemma spec_land x y : [| ZnZ.land x y |] = Z.land [|x|] [|y|].
Proof.
unfold ZnZ.land, int31_ops. unfold land31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.land_nonneg; left; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
eapply Z.le_lt_trans.
apply Z.log2_land; try apply phi_bounded.
apply Z.min_lt_iff; left; apply log2_phi_bounded.
Qed.
Lemma spec_lxor x y : [| ZnZ.lxor x y |] = Z.lxor [|x|] [|y|].
Proof.
unfold ZnZ.lxor, int31_ops. unfold lxor31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.lxor_nonneg; split; intros; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
eapply Z.le_lt_trans.
apply Z.log2_lxor; try apply phi_bounded.
apply Z.max_lub_lt; apply log2_phi_bounded.
Qed.
Global Instance int31_specs : ZnZ.Specs int31_ops := {
spec_to_Z := phi_bounded;
spec_of_pos := positive_to_int31_spec;
spec_zdigits := spec_zdigits;
spec_more_than_1_digit := spec_more_than_1_digit;
spec_0 := spec_0;
spec_1 := spec_1;
spec_m1 := spec_m1;
spec_compare := spec_compare;
spec_eq0 := spec_eq0;
spec_opp_c := spec_opp_c;
spec_opp := spec_opp;
spec_opp_carry := spec_opp_carry;
spec_succ_c := spec_succ_c;
spec_add_c := spec_add_c;
spec_add_carry_c := spec_add_carry_c;
spec_succ := spec_succ;
spec_add := spec_add;
spec_add_carry := spec_add_carry;
spec_pred_c := spec_pred_c;
spec_sub_c := spec_sub_c;
spec_sub_carry_c := spec_sub_carry_c;
spec_pred := spec_pred;
spec_sub := spec_sub;
spec_sub_carry := spec_sub_carry;
spec_mul_c := spec_mul_c;
spec_mul := spec_mul;
spec_square_c := spec_square_c;
spec_div21 := spec_div21;
spec_div_gt := fun a b _ => spec_div a b;
spec_div := spec_div;
spec_modulo_gt := fun a b _ => spec_mod a b;
spec_modulo := spec_mod;
spec_gcd_gt := fun a b _ => spec_gcd a b;
spec_gcd := spec_gcd;
spec_head00 := spec_head00;
spec_head0 := spec_head0;
spec_tail00 := spec_tail00;
spec_tail0 := spec_tail0;
spec_add_mul_div := spec_add_mul_div;
spec_pos_mod := spec_pos_mod;
spec_is_even := spec_is_even;
spec_sqrt2 := spec_sqrt2;
spec_sqrt := spec_sqrt;
spec_lor := spec_lor;
spec_land := spec_land;
spec_lxor := spec_lxor }.
End Int31_Specs.
Module Int31Cyclic <: CyclicType.
Definition t := int31.
Definition ops := int31_ops.
Definition specs := int31_specs.
End Int31Cyclic.
|
`include "senior_defines.vh"
module register_file
#(parameter ctrl_w = `RF_CTRL_WIDTH,
parameter nat_w = `SENIOR_NATIVE_WIDTH)
(
input wire clk_i,
input wire reset_i,
input wire [nat_w-1:0] pass_through_dat_i,
input wire [ctrl_w-1:0] ctrl_i,
input wire [nat_w-1:0] dat_i,
input wire [nat_w-1:0] dm_dat_i,
input wire register_enable_i,
output reg [nat_w-1:0] dat_a_o,
output reg [nat_w-1:0] dat_b_o
);
reg [nat_w-1:0] theRF [31:0];
wire [nat_w-1:0] out_a;
wire [nat_w-1:0] out_b;
// Internal Declarations
always@(posedge clk_i) begin
if(register_enable_i && ctrl_i`RF_WRITE_REG_EN) begin
theRF[ctrl_i`RF_WRITE_REG_SEL] <= dat_i;
end
if(register_enable_i && ctrl_i`RF_WRITE_REG_EN_DM &&
ctrl_i`RF_WRITE_REG_SEL != ctrl_i`RF_WRITE_REG_SEL_DM) begin
theRF[ctrl_i`RF_WRITE_REG_SEL_DM] <= dm_dat_i;
end
end
wire [5:0] ctrl_i_opa;
wire [5:0] ctrl_i_opb;
assign ctrl_i_opa = ctrl_i`RF_OPA;
assign ctrl_i_opb = ctrl_i`RF_OPB;
assign out_a = theRF[ctrl_i_opa[4:0]];
assign out_b = theRF[ctrl_i_opb[4:0]];
// output logic
// mux for operand A
always @(*) begin
case (ctrl_i_opa[5])
1'b0: dat_a_o=out_a;
1'b1: dat_a_o=pass_through_dat_i;
endcase // case(id_rf_opa_sel_i[5])
end
// mux for operand B
always@(*) begin
case (ctrl_i_opb[5])
1'b0: dat_b_o=out_b;
1'b1: dat_b_o=pass_through_dat_i;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_BLACKBOX_V
`define SKY130_FD_SC_HD__TAPVGND2_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_BLACKBOX_V
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// lvt_reg.v: Register-based binary-coded LVT (Live-Value-Table) //
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// Switched SRAM-based Multi-ported RAM; University of British Columbia, 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module lvt_reg
#( parameter MEMD = 16, // memory depth
parameter nRP = 2 , // number of reading ports
parameter nWP = 2 , // number of writing ports
parameter RDWB = 0 , // new data for Read-During-Write
parameter ZERO = 0 , // binary / Initial RAM with zeros (has priority over FILE)
parameter FILE = "" // initialization file, optional
)( input clk , // clock
input [ nWP-1:0] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWP-1:0] WAddr, // write addresses - packed from nWP write ports
input [`log2(MEMD)*nRP-1:0] RAddr, // read addresses - packed from nRP read ports
output [`log2(nWP )*nRP-1:0] RBank); // read bank selector - packed from nRP read ports
localparam ADRW = `log2(MEMD); // address width
localparam LVTW = `log2(nWP ); // required memory width
// Generate Bank ID's to write into LVT
reg [LVTW*nWP-1:0] WData1D ;
wire [LVTW -1:0] WData2D [nWP-1:0];
genvar gi;
generate
for (gi=0;gi<nWP;gi=gi+1) begin: GenerateID
assign WData2D[gi]=gi;
end
endgenerate
// packing/unpacking arrays into 1D/2D/3D structures; see utils.vh for definitions
// pack ID's into 1D array
`ARRINIT;
always @* `ARR2D1D(nWP,LVTW,WData2D,WData1D);
mpram_reg #( .MEMD (MEMD ), // memory depth
.DATW (LVTW ), // data width
.nRP (nRP ), // number of reading ports
.nWP (nWP ), // number of writing ports
.RDWB (RDWB ), // provide new data when Read-During-Write?
.ZERO (ZERO ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (FILE )) // initialization file, optional
mpram_reg_ins ( .clk (clk ), // clock - in
.WEnb (WEnb ), // write enable for each writing port - in : [ nWP-1:0]
.WAddr (WAddr ), // write addresses - packed from nWP write ports - in : [ADRW*nWP-1:0]
.WData (WData1D), // write data - packed from nRP read ports - in : [LVTW*nWP-1:0]
.RAddr (RAddr ), // read addresses - packed from nRP read ports - in : [ADRW*nRP-1:0]
.RData (RBank )); // read data - packed from nRP read ports - out: [LVTW*nRP-1:0]
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:45:59 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_transform_0_0/system_vga_transform_0_0_sim_netlist.v
// Design : system_vga_transform_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_transform_0_0,vga_transform,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_transform,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_transform_0_0
(clk,
enable,
x_addr_in,
y_addr_in,
rot_m00,
rot_m01,
rot_m10,
rot_m11,
t_x,
t_y,
x_addr_out,
y_addr_out);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input enable;
input [9:0]x_addr_in;
input [9:0]y_addr_in;
input [15:0]rot_m00;
input [15:0]rot_m01;
input [15:0]rot_m10;
input [15:0]rot_m11;
input [9:0]t_x;
input [9:0]t_y;
output [9:0]x_addr_out;
output [9:0]y_addr_out;
wire clk;
wire enable;
wire [15:0]rot_m00;
wire [15:0]rot_m01;
wire [15:0]rot_m10;
wire [15:0]rot_m11;
wire [9:0]t_x;
wire [9:0]t_y;
wire [9:0]x_addr_in;
wire [9:0]x_addr_out;
wire [9:0]y_addr_in;
wire [9:0]y_addr_out;
system_vga_transform_0_0_vga_transform U0
(.clk(clk),
.enable(enable),
.rot_m00(rot_m00),
.rot_m01(rot_m01),
.rot_m10(rot_m10),
.rot_m11(rot_m11),
.t_x(t_x),
.t_y(t_y),
.x_addr_in(x_addr_in),
.x_addr_out(x_addr_out),
.y_addr_in(y_addr_in),
.y_addr_out(y_addr_out));
endmodule
(* ORIG_REF_NAME = "vga_transform" *)
module system_vga_transform_0_0_vga_transform
(x_addr_out,
y_addr_out,
rot_m01,
y_addr_in,
rot_m00,
x_addr_in,
clk,
rot_m11,
rot_m10,
enable,
t_x,
t_y);
output [9:0]x_addr_out;
output [9:0]y_addr_out;
input [15:0]rot_m01;
input [9:0]y_addr_in;
input [15:0]rot_m00;
input [9:0]x_addr_in;
input clk;
input [15:0]rot_m11;
input [15:0]rot_m10;
input enable;
input [9:0]t_x;
input [9:0]t_y;
wire clk;
wire enable;
wire [9:0]p_0_in;
wire [23:14]p_1_in;
wire [15:0]rot_m00;
wire [15:0]rot_m01;
wire [15:0]rot_m10;
wire [15:0]rot_m11;
wire [9:0]t_x;
wire [9:0]t_y;
wire [9:0]x_addr_in;
wire [9:0]x_addr_out;
wire [23:14]x_addr_out0;
wire x_addr_out0_carry__0_i_1_n_0;
wire x_addr_out0_carry__0_i_2_n_0;
wire x_addr_out0_carry__0_i_3_n_0;
wire x_addr_out0_carry__0_i_4_n_0;
wire x_addr_out0_carry__0_n_0;
wire x_addr_out0_carry__0_n_1;
wire x_addr_out0_carry__0_n_2;
wire x_addr_out0_carry__0_n_3;
wire x_addr_out0_carry__1_i_1_n_0;
wire x_addr_out0_carry__1_i_2_n_0;
wire x_addr_out0_carry__1_n_3;
wire x_addr_out0_carry_i_1_n_0;
wire x_addr_out0_carry_i_2_n_0;
wire x_addr_out0_carry_i_3_n_0;
wire x_addr_out0_carry_n_0;
wire x_addr_out0_carry_n_1;
wire x_addr_out0_carry_n_2;
wire x_addr_out0_carry_n_3;
wire x_addr_out2_carry__0_i_1_n_0;
wire x_addr_out2_carry__0_i_2_n_0;
wire x_addr_out2_carry__0_i_3_n_0;
wire x_addr_out2_carry__0_i_4_n_0;
wire x_addr_out2_carry__0_n_0;
wire x_addr_out2_carry__0_n_1;
wire x_addr_out2_carry__0_n_2;
wire x_addr_out2_carry__0_n_3;
wire x_addr_out2_carry__1_i_1_n_0;
wire x_addr_out2_carry__1_i_2_n_0;
wire x_addr_out2_carry__1_i_3_n_0;
wire x_addr_out2_carry__1_i_4_n_0;
wire x_addr_out2_carry__1_n_0;
wire x_addr_out2_carry__1_n_1;
wire x_addr_out2_carry__1_n_2;
wire x_addr_out2_carry__1_n_3;
wire x_addr_out2_carry__2_i_1_n_0;
wire x_addr_out2_carry__2_i_2_n_0;
wire x_addr_out2_carry__2_i_3_n_0;
wire x_addr_out2_carry__2_i_4_n_0;
wire x_addr_out2_carry__2_n_0;
wire x_addr_out2_carry__2_n_1;
wire x_addr_out2_carry__2_n_2;
wire x_addr_out2_carry__2_n_3;
wire x_addr_out2_carry__3_i_1_n_0;
wire x_addr_out2_carry__3_i_2_n_0;
wire x_addr_out2_carry__3_i_3_n_0;
wire x_addr_out2_carry__3_i_4_n_0;
wire x_addr_out2_carry__3_n_0;
wire x_addr_out2_carry__3_n_1;
wire x_addr_out2_carry__3_n_2;
wire x_addr_out2_carry__3_n_3;
wire x_addr_out2_carry__4_i_1_n_0;
wire x_addr_out2_carry__4_i_2_n_0;
wire x_addr_out2_carry__4_i_3_n_0;
wire x_addr_out2_carry__4_i_4_n_0;
wire x_addr_out2_carry__4_n_0;
wire x_addr_out2_carry__4_n_1;
wire x_addr_out2_carry__4_n_2;
wire x_addr_out2_carry__4_n_3;
wire x_addr_out2_carry__5_i_1_n_0;
wire x_addr_out2_carry__5_i_2_n_0;
wire x_addr_out2_carry__5_i_3_n_0;
wire x_addr_out2_carry__5_i_4_n_0;
wire x_addr_out2_carry__5_n_0;
wire x_addr_out2_carry__5_n_1;
wire x_addr_out2_carry__5_n_2;
wire x_addr_out2_carry__5_n_3;
wire x_addr_out2_carry__6_i_1_n_0;
wire x_addr_out2_carry__6_i_2_n_0;
wire x_addr_out2_carry__6_i_3_n_0;
wire x_addr_out2_carry__6_i_4_n_0;
wire x_addr_out2_carry__6_n_0;
wire x_addr_out2_carry__6_n_1;
wire x_addr_out2_carry__6_n_2;
wire x_addr_out2_carry__6_n_3;
wire x_addr_out2_carry__7_i_1_n_0;
wire x_addr_out2_carry__7_i_2_n_0;
wire x_addr_out2_carry__7_i_3_n_0;
wire x_addr_out2_carry__7_i_4_n_0;
wire x_addr_out2_carry__7_n_0;
wire x_addr_out2_carry__7_n_1;
wire x_addr_out2_carry__7_n_2;
wire x_addr_out2_carry__7_n_3;
wire x_addr_out2_carry__8_i_1_n_0;
wire x_addr_out2_carry__8_i_2_n_0;
wire x_addr_out2_carry__8_n_3;
wire x_addr_out2_carry_i_1_n_0;
wire x_addr_out2_carry_i_2_n_0;
wire x_addr_out2_carry_i_3_n_0;
wire x_addr_out2_carry_i_4_n_0;
wire x_addr_out2_carry_n_0;
wire x_addr_out2_carry_n_1;
wire x_addr_out2_carry_n_2;
wire x_addr_out2_carry_n_3;
wire x_addr_out3__0_n_100;
wire x_addr_out3__0_n_101;
wire x_addr_out3__0_n_102;
wire x_addr_out3__0_n_103;
wire x_addr_out3__0_n_104;
wire x_addr_out3__0_n_105;
wire x_addr_out3__0_n_58;
wire x_addr_out3__0_n_59;
wire x_addr_out3__0_n_60;
wire x_addr_out3__0_n_61;
wire x_addr_out3__0_n_62;
wire x_addr_out3__0_n_63;
wire x_addr_out3__0_n_64;
wire x_addr_out3__0_n_65;
wire x_addr_out3__0_n_66;
wire x_addr_out3__0_n_67;
wire x_addr_out3__0_n_68;
wire x_addr_out3__0_n_69;
wire x_addr_out3__0_n_70;
wire x_addr_out3__0_n_71;
wire x_addr_out3__0_n_72;
wire x_addr_out3__0_n_73;
wire x_addr_out3__0_n_74;
wire x_addr_out3__0_n_75;
wire x_addr_out3__0_n_76;
wire x_addr_out3__0_n_77;
wire x_addr_out3__0_n_78;
wire x_addr_out3__0_n_79;
wire x_addr_out3__0_n_80;
wire x_addr_out3__0_n_81;
wire x_addr_out3__0_n_82;
wire x_addr_out3__0_n_83;
wire x_addr_out3__0_n_84;
wire x_addr_out3__0_n_85;
wire x_addr_out3__0_n_86;
wire x_addr_out3__0_n_87;
wire x_addr_out3__0_n_88;
wire x_addr_out3__0_n_89;
wire x_addr_out3__0_n_90;
wire x_addr_out3__0_n_91;
wire x_addr_out3__0_n_92;
wire x_addr_out3__0_n_93;
wire x_addr_out3__0_n_94;
wire x_addr_out3__0_n_95;
wire x_addr_out3__0_n_96;
wire x_addr_out3__0_n_97;
wire x_addr_out3__0_n_98;
wire x_addr_out3__0_n_99;
wire x_addr_out3__1_n_100;
wire x_addr_out3__1_n_101;
wire x_addr_out3__1_n_102;
wire x_addr_out3__1_n_103;
wire x_addr_out3__1_n_104;
wire x_addr_out3__1_n_105;
wire x_addr_out3__1_n_106;
wire x_addr_out3__1_n_107;
wire x_addr_out3__1_n_108;
wire x_addr_out3__1_n_109;
wire x_addr_out3__1_n_110;
wire x_addr_out3__1_n_111;
wire x_addr_out3__1_n_112;
wire x_addr_out3__1_n_113;
wire x_addr_out3__1_n_114;
wire x_addr_out3__1_n_115;
wire x_addr_out3__1_n_116;
wire x_addr_out3__1_n_117;
wire x_addr_out3__1_n_118;
wire x_addr_out3__1_n_119;
wire x_addr_out3__1_n_120;
wire x_addr_out3__1_n_121;
wire x_addr_out3__1_n_122;
wire x_addr_out3__1_n_123;
wire x_addr_out3__1_n_124;
wire x_addr_out3__1_n_125;
wire x_addr_out3__1_n_126;
wire x_addr_out3__1_n_127;
wire x_addr_out3__1_n_128;
wire x_addr_out3__1_n_129;
wire x_addr_out3__1_n_130;
wire x_addr_out3__1_n_131;
wire x_addr_out3__1_n_132;
wire x_addr_out3__1_n_133;
wire x_addr_out3__1_n_134;
wire x_addr_out3__1_n_135;
wire x_addr_out3__1_n_136;
wire x_addr_out3__1_n_137;
wire x_addr_out3__1_n_138;
wire x_addr_out3__1_n_139;
wire x_addr_out3__1_n_140;
wire x_addr_out3__1_n_141;
wire x_addr_out3__1_n_142;
wire x_addr_out3__1_n_143;
wire x_addr_out3__1_n_144;
wire x_addr_out3__1_n_145;
wire x_addr_out3__1_n_146;
wire x_addr_out3__1_n_147;
wire x_addr_out3__1_n_148;
wire x_addr_out3__1_n_149;
wire x_addr_out3__1_n_150;
wire x_addr_out3__1_n_151;
wire x_addr_out3__1_n_152;
wire x_addr_out3__1_n_153;
wire x_addr_out3__1_n_58;
wire x_addr_out3__1_n_59;
wire x_addr_out3__1_n_60;
wire x_addr_out3__1_n_61;
wire x_addr_out3__1_n_62;
wire x_addr_out3__1_n_63;
wire x_addr_out3__1_n_64;
wire x_addr_out3__1_n_65;
wire x_addr_out3__1_n_66;
wire x_addr_out3__1_n_67;
wire x_addr_out3__1_n_68;
wire x_addr_out3__1_n_69;
wire x_addr_out3__1_n_70;
wire x_addr_out3__1_n_71;
wire x_addr_out3__1_n_72;
wire x_addr_out3__1_n_73;
wire x_addr_out3__1_n_74;
wire x_addr_out3__1_n_75;
wire x_addr_out3__1_n_76;
wire x_addr_out3__1_n_77;
wire x_addr_out3__1_n_78;
wire x_addr_out3__1_n_79;
wire x_addr_out3__1_n_80;
wire x_addr_out3__1_n_81;
wire x_addr_out3__1_n_82;
wire x_addr_out3__1_n_83;
wire x_addr_out3__1_n_84;
wire x_addr_out3__1_n_85;
wire x_addr_out3__1_n_86;
wire x_addr_out3__1_n_87;
wire x_addr_out3__1_n_88;
wire x_addr_out3__1_n_89;
wire x_addr_out3__1_n_90;
wire x_addr_out3__1_n_91;
wire x_addr_out3__1_n_92;
wire x_addr_out3__1_n_93;
wire x_addr_out3__1_n_94;
wire x_addr_out3__1_n_95;
wire x_addr_out3__1_n_96;
wire x_addr_out3__1_n_97;
wire x_addr_out3__1_n_98;
wire x_addr_out3__1_n_99;
wire x_addr_out3__2_n_100;
wire x_addr_out3__2_n_101;
wire x_addr_out3__2_n_102;
wire x_addr_out3__2_n_103;
wire x_addr_out3__2_n_104;
wire x_addr_out3__2_n_105;
wire x_addr_out3__2_n_58;
wire x_addr_out3__2_n_59;
wire x_addr_out3__2_n_60;
wire x_addr_out3__2_n_61;
wire x_addr_out3__2_n_62;
wire x_addr_out3__2_n_63;
wire x_addr_out3__2_n_64;
wire x_addr_out3__2_n_65;
wire x_addr_out3__2_n_66;
wire x_addr_out3__2_n_67;
wire x_addr_out3__2_n_68;
wire x_addr_out3__2_n_69;
wire x_addr_out3__2_n_70;
wire x_addr_out3__2_n_71;
wire x_addr_out3__2_n_72;
wire x_addr_out3__2_n_73;
wire x_addr_out3__2_n_74;
wire x_addr_out3__2_n_75;
wire x_addr_out3__2_n_76;
wire x_addr_out3__2_n_77;
wire x_addr_out3__2_n_78;
wire x_addr_out3__2_n_79;
wire x_addr_out3__2_n_80;
wire x_addr_out3__2_n_81;
wire x_addr_out3__2_n_82;
wire x_addr_out3__2_n_83;
wire x_addr_out3__2_n_84;
wire x_addr_out3__2_n_85;
wire x_addr_out3__2_n_86;
wire x_addr_out3__2_n_87;
wire x_addr_out3__2_n_88;
wire x_addr_out3__2_n_89;
wire x_addr_out3__2_n_90;
wire x_addr_out3__2_n_91;
wire x_addr_out3__2_n_92;
wire x_addr_out3__2_n_93;
wire x_addr_out3__2_n_94;
wire x_addr_out3__2_n_95;
wire x_addr_out3__2_n_96;
wire x_addr_out3__2_n_97;
wire x_addr_out3__2_n_98;
wire x_addr_out3__2_n_99;
wire x_addr_out3_n_100;
wire x_addr_out3_n_101;
wire x_addr_out3_n_102;
wire x_addr_out3_n_103;
wire x_addr_out3_n_104;
wire x_addr_out3_n_105;
wire x_addr_out3_n_106;
wire x_addr_out3_n_107;
wire x_addr_out3_n_108;
wire x_addr_out3_n_109;
wire x_addr_out3_n_110;
wire x_addr_out3_n_111;
wire x_addr_out3_n_112;
wire x_addr_out3_n_113;
wire x_addr_out3_n_114;
wire x_addr_out3_n_115;
wire x_addr_out3_n_116;
wire x_addr_out3_n_117;
wire x_addr_out3_n_118;
wire x_addr_out3_n_119;
wire x_addr_out3_n_120;
wire x_addr_out3_n_121;
wire x_addr_out3_n_122;
wire x_addr_out3_n_123;
wire x_addr_out3_n_124;
wire x_addr_out3_n_125;
wire x_addr_out3_n_126;
wire x_addr_out3_n_127;
wire x_addr_out3_n_128;
wire x_addr_out3_n_129;
wire x_addr_out3_n_130;
wire x_addr_out3_n_131;
wire x_addr_out3_n_132;
wire x_addr_out3_n_133;
wire x_addr_out3_n_134;
wire x_addr_out3_n_135;
wire x_addr_out3_n_136;
wire x_addr_out3_n_137;
wire x_addr_out3_n_138;
wire x_addr_out3_n_139;
wire x_addr_out3_n_140;
wire x_addr_out3_n_141;
wire x_addr_out3_n_142;
wire x_addr_out3_n_143;
wire x_addr_out3_n_144;
wire x_addr_out3_n_145;
wire x_addr_out3_n_146;
wire x_addr_out3_n_147;
wire x_addr_out3_n_148;
wire x_addr_out3_n_149;
wire x_addr_out3_n_150;
wire x_addr_out3_n_151;
wire x_addr_out3_n_152;
wire x_addr_out3_n_153;
wire x_addr_out3_n_58;
wire x_addr_out3_n_59;
wire x_addr_out3_n_60;
wire x_addr_out3_n_61;
wire x_addr_out3_n_62;
wire x_addr_out3_n_63;
wire x_addr_out3_n_64;
wire x_addr_out3_n_65;
wire x_addr_out3_n_66;
wire x_addr_out3_n_67;
wire x_addr_out3_n_68;
wire x_addr_out3_n_69;
wire x_addr_out3_n_70;
wire x_addr_out3_n_71;
wire x_addr_out3_n_72;
wire x_addr_out3_n_73;
wire x_addr_out3_n_74;
wire x_addr_out3_n_75;
wire x_addr_out3_n_76;
wire x_addr_out3_n_77;
wire x_addr_out3_n_78;
wire x_addr_out3_n_79;
wire x_addr_out3_n_80;
wire x_addr_out3_n_81;
wire x_addr_out3_n_82;
wire x_addr_out3_n_83;
wire x_addr_out3_n_84;
wire x_addr_out3_n_85;
wire x_addr_out3_n_86;
wire x_addr_out3_n_87;
wire x_addr_out3_n_88;
wire x_addr_out3_n_89;
wire x_addr_out3_n_90;
wire x_addr_out3_n_91;
wire x_addr_out3_n_92;
wire x_addr_out3_n_93;
wire x_addr_out3_n_94;
wire x_addr_out3_n_95;
wire x_addr_out3_n_96;
wire x_addr_out3_n_97;
wire x_addr_out3_n_98;
wire x_addr_out3_n_99;
wire \x_addr_out[0]_i_1_n_0 ;
wire \x_addr_out[1]_i_1_n_0 ;
wire \x_addr_out[2]_i_1_n_0 ;
wire \x_addr_out[3]_i_1_n_0 ;
wire \x_addr_out[4]_i_1_n_0 ;
wire \x_addr_out[5]_i_1_n_0 ;
wire \x_addr_out[6]_i_1_n_0 ;
wire \x_addr_out[7]_i_1_n_0 ;
wire \x_addr_out[8]_i_1_n_0 ;
wire \x_addr_out[9]_i_1_n_0 ;
wire [9:0]y_addr_in;
wire [9:0]y_addr_out;
wire y_addr_out0_carry__0_i_1_n_0;
wire y_addr_out0_carry__0_i_2_n_0;
wire y_addr_out0_carry__0_i_3_n_0;
wire y_addr_out0_carry__0_i_4_n_0;
wire y_addr_out0_carry__0_n_0;
wire y_addr_out0_carry__0_n_1;
wire y_addr_out0_carry__0_n_2;
wire y_addr_out0_carry__0_n_3;
wire y_addr_out0_carry__1_i_1_n_0;
wire y_addr_out0_carry__1_i_2_n_0;
wire y_addr_out0_carry__1_n_3;
wire y_addr_out0_carry_i_1_n_0;
wire y_addr_out0_carry_i_2_n_0;
wire y_addr_out0_carry_i_3_n_0;
wire y_addr_out0_carry_i_4_n_0;
wire y_addr_out0_carry_n_0;
wire y_addr_out0_carry_n_1;
wire y_addr_out0_carry_n_2;
wire y_addr_out0_carry_n_3;
wire [37:28]y_addr_out2;
wire y_addr_out2_carry__0_i_1_n_0;
wire y_addr_out2_carry__0_i_2_n_0;
wire y_addr_out2_carry__0_i_3_n_0;
wire y_addr_out2_carry__0_i_4_n_0;
wire y_addr_out2_carry__0_n_0;
wire y_addr_out2_carry__0_n_1;
wire y_addr_out2_carry__0_n_2;
wire y_addr_out2_carry__0_n_3;
wire y_addr_out2_carry__1_i_1_n_0;
wire y_addr_out2_carry__1_i_2_n_0;
wire y_addr_out2_carry__1_i_3_n_0;
wire y_addr_out2_carry__1_i_4_n_0;
wire y_addr_out2_carry__1_n_0;
wire y_addr_out2_carry__1_n_1;
wire y_addr_out2_carry__1_n_2;
wire y_addr_out2_carry__1_n_3;
wire y_addr_out2_carry__2_i_1_n_0;
wire y_addr_out2_carry__2_i_2_n_0;
wire y_addr_out2_carry__2_i_3_n_0;
wire y_addr_out2_carry__2_i_4_n_0;
wire y_addr_out2_carry__2_n_0;
wire y_addr_out2_carry__2_n_1;
wire y_addr_out2_carry__2_n_2;
wire y_addr_out2_carry__2_n_3;
wire y_addr_out2_carry__3_i_1_n_0;
wire y_addr_out2_carry__3_i_2_n_0;
wire y_addr_out2_carry__3_i_3_n_0;
wire y_addr_out2_carry__3_i_4_n_0;
wire y_addr_out2_carry__3_n_0;
wire y_addr_out2_carry__3_n_1;
wire y_addr_out2_carry__3_n_2;
wire y_addr_out2_carry__3_n_3;
wire y_addr_out2_carry__4_i_1_n_0;
wire y_addr_out2_carry__4_i_2_n_0;
wire y_addr_out2_carry__4_i_3_n_0;
wire y_addr_out2_carry__4_i_4_n_0;
wire y_addr_out2_carry__4_n_0;
wire y_addr_out2_carry__4_n_1;
wire y_addr_out2_carry__4_n_2;
wire y_addr_out2_carry__4_n_3;
wire y_addr_out2_carry__5_i_1_n_0;
wire y_addr_out2_carry__5_i_2_n_0;
wire y_addr_out2_carry__5_i_3_n_0;
wire y_addr_out2_carry__5_i_4_n_0;
wire y_addr_out2_carry__5_n_0;
wire y_addr_out2_carry__5_n_1;
wire y_addr_out2_carry__5_n_2;
wire y_addr_out2_carry__5_n_3;
wire y_addr_out2_carry__6_i_1_n_0;
wire y_addr_out2_carry__6_i_2_n_0;
wire y_addr_out2_carry__6_i_3_n_0;
wire y_addr_out2_carry__6_i_4_n_0;
wire y_addr_out2_carry__6_n_0;
wire y_addr_out2_carry__6_n_1;
wire y_addr_out2_carry__6_n_2;
wire y_addr_out2_carry__6_n_3;
wire y_addr_out2_carry__7_i_1_n_0;
wire y_addr_out2_carry__7_i_2_n_0;
wire y_addr_out2_carry__7_i_3_n_0;
wire y_addr_out2_carry__7_i_4_n_0;
wire y_addr_out2_carry__7_n_0;
wire y_addr_out2_carry__7_n_1;
wire y_addr_out2_carry__7_n_2;
wire y_addr_out2_carry__7_n_3;
wire y_addr_out2_carry__8_i_1_n_0;
wire y_addr_out2_carry__8_i_2_n_0;
wire y_addr_out2_carry__8_n_3;
wire y_addr_out2_carry_i_1_n_0;
wire y_addr_out2_carry_i_2_n_0;
wire y_addr_out2_carry_i_3_n_0;
wire y_addr_out2_carry_i_4_n_0;
wire y_addr_out2_carry_n_0;
wire y_addr_out2_carry_n_1;
wire y_addr_out2_carry_n_2;
wire y_addr_out2_carry_n_3;
wire y_addr_out3__0_n_100;
wire y_addr_out3__0_n_101;
wire y_addr_out3__0_n_102;
wire y_addr_out3__0_n_103;
wire y_addr_out3__0_n_104;
wire y_addr_out3__0_n_105;
wire y_addr_out3__0_n_58;
wire y_addr_out3__0_n_59;
wire y_addr_out3__0_n_60;
wire y_addr_out3__0_n_61;
wire y_addr_out3__0_n_62;
wire y_addr_out3__0_n_63;
wire y_addr_out3__0_n_64;
wire y_addr_out3__0_n_65;
wire y_addr_out3__0_n_66;
wire y_addr_out3__0_n_67;
wire y_addr_out3__0_n_68;
wire y_addr_out3__0_n_69;
wire y_addr_out3__0_n_70;
wire y_addr_out3__0_n_71;
wire y_addr_out3__0_n_72;
wire y_addr_out3__0_n_73;
wire y_addr_out3__0_n_74;
wire y_addr_out3__0_n_75;
wire y_addr_out3__0_n_76;
wire y_addr_out3__0_n_77;
wire y_addr_out3__0_n_78;
wire y_addr_out3__0_n_79;
wire y_addr_out3__0_n_80;
wire y_addr_out3__0_n_81;
wire y_addr_out3__0_n_82;
wire y_addr_out3__0_n_83;
wire y_addr_out3__0_n_84;
wire y_addr_out3__0_n_85;
wire y_addr_out3__0_n_86;
wire y_addr_out3__0_n_87;
wire y_addr_out3__0_n_88;
wire y_addr_out3__0_n_89;
wire y_addr_out3__0_n_90;
wire y_addr_out3__0_n_91;
wire y_addr_out3__0_n_92;
wire y_addr_out3__0_n_93;
wire y_addr_out3__0_n_94;
wire y_addr_out3__0_n_95;
wire y_addr_out3__0_n_96;
wire y_addr_out3__0_n_97;
wire y_addr_out3__0_n_98;
wire y_addr_out3__0_n_99;
wire y_addr_out3__1_n_100;
wire y_addr_out3__1_n_101;
wire y_addr_out3__1_n_102;
wire y_addr_out3__1_n_103;
wire y_addr_out3__1_n_104;
wire y_addr_out3__1_n_105;
wire y_addr_out3__1_n_106;
wire y_addr_out3__1_n_107;
wire y_addr_out3__1_n_108;
wire y_addr_out3__1_n_109;
wire y_addr_out3__1_n_110;
wire y_addr_out3__1_n_111;
wire y_addr_out3__1_n_112;
wire y_addr_out3__1_n_113;
wire y_addr_out3__1_n_114;
wire y_addr_out3__1_n_115;
wire y_addr_out3__1_n_116;
wire y_addr_out3__1_n_117;
wire y_addr_out3__1_n_118;
wire y_addr_out3__1_n_119;
wire y_addr_out3__1_n_120;
wire y_addr_out3__1_n_121;
wire y_addr_out3__1_n_122;
wire y_addr_out3__1_n_123;
wire y_addr_out3__1_n_124;
wire y_addr_out3__1_n_125;
wire y_addr_out3__1_n_126;
wire y_addr_out3__1_n_127;
wire y_addr_out3__1_n_128;
wire y_addr_out3__1_n_129;
wire y_addr_out3__1_n_130;
wire y_addr_out3__1_n_131;
wire y_addr_out3__1_n_132;
wire y_addr_out3__1_n_133;
wire y_addr_out3__1_n_134;
wire y_addr_out3__1_n_135;
wire y_addr_out3__1_n_136;
wire y_addr_out3__1_n_137;
wire y_addr_out3__1_n_138;
wire y_addr_out3__1_n_139;
wire y_addr_out3__1_n_140;
wire y_addr_out3__1_n_141;
wire y_addr_out3__1_n_142;
wire y_addr_out3__1_n_143;
wire y_addr_out3__1_n_144;
wire y_addr_out3__1_n_145;
wire y_addr_out3__1_n_146;
wire y_addr_out3__1_n_147;
wire y_addr_out3__1_n_148;
wire y_addr_out3__1_n_149;
wire y_addr_out3__1_n_150;
wire y_addr_out3__1_n_151;
wire y_addr_out3__1_n_152;
wire y_addr_out3__1_n_153;
wire y_addr_out3__1_n_58;
wire y_addr_out3__1_n_59;
wire y_addr_out3__1_n_60;
wire y_addr_out3__1_n_61;
wire y_addr_out3__1_n_62;
wire y_addr_out3__1_n_63;
wire y_addr_out3__1_n_64;
wire y_addr_out3__1_n_65;
wire y_addr_out3__1_n_66;
wire y_addr_out3__1_n_67;
wire y_addr_out3__1_n_68;
wire y_addr_out3__1_n_69;
wire y_addr_out3__1_n_70;
wire y_addr_out3__1_n_71;
wire y_addr_out3__1_n_72;
wire y_addr_out3__1_n_73;
wire y_addr_out3__1_n_74;
wire y_addr_out3__1_n_75;
wire y_addr_out3__1_n_76;
wire y_addr_out3__1_n_77;
wire y_addr_out3__1_n_78;
wire y_addr_out3__1_n_79;
wire y_addr_out3__1_n_80;
wire y_addr_out3__1_n_81;
wire y_addr_out3__1_n_82;
wire y_addr_out3__1_n_83;
wire y_addr_out3__1_n_84;
wire y_addr_out3__1_n_85;
wire y_addr_out3__1_n_86;
wire y_addr_out3__1_n_87;
wire y_addr_out3__1_n_88;
wire y_addr_out3__1_n_89;
wire y_addr_out3__1_n_90;
wire y_addr_out3__1_n_91;
wire y_addr_out3__1_n_92;
wire y_addr_out3__1_n_93;
wire y_addr_out3__1_n_94;
wire y_addr_out3__1_n_95;
wire y_addr_out3__1_n_96;
wire y_addr_out3__1_n_97;
wire y_addr_out3__1_n_98;
wire y_addr_out3__1_n_99;
wire y_addr_out3__2_n_100;
wire y_addr_out3__2_n_101;
wire y_addr_out3__2_n_102;
wire y_addr_out3__2_n_103;
wire y_addr_out3__2_n_104;
wire y_addr_out3__2_n_105;
wire y_addr_out3__2_n_58;
wire y_addr_out3__2_n_59;
wire y_addr_out3__2_n_60;
wire y_addr_out3__2_n_61;
wire y_addr_out3__2_n_62;
wire y_addr_out3__2_n_63;
wire y_addr_out3__2_n_64;
wire y_addr_out3__2_n_65;
wire y_addr_out3__2_n_66;
wire y_addr_out3__2_n_67;
wire y_addr_out3__2_n_68;
wire y_addr_out3__2_n_69;
wire y_addr_out3__2_n_70;
wire y_addr_out3__2_n_71;
wire y_addr_out3__2_n_72;
wire y_addr_out3__2_n_73;
wire y_addr_out3__2_n_74;
wire y_addr_out3__2_n_75;
wire y_addr_out3__2_n_76;
wire y_addr_out3__2_n_77;
wire y_addr_out3__2_n_78;
wire y_addr_out3__2_n_79;
wire y_addr_out3__2_n_80;
wire y_addr_out3__2_n_81;
wire y_addr_out3__2_n_82;
wire y_addr_out3__2_n_83;
wire y_addr_out3__2_n_84;
wire y_addr_out3__2_n_85;
wire y_addr_out3__2_n_86;
wire y_addr_out3__2_n_87;
wire y_addr_out3__2_n_88;
wire y_addr_out3__2_n_89;
wire y_addr_out3__2_n_90;
wire y_addr_out3__2_n_91;
wire y_addr_out3__2_n_92;
wire y_addr_out3__2_n_93;
wire y_addr_out3__2_n_94;
wire y_addr_out3__2_n_95;
wire y_addr_out3__2_n_96;
wire y_addr_out3__2_n_97;
wire y_addr_out3__2_n_98;
wire y_addr_out3__2_n_99;
wire y_addr_out3_n_100;
wire y_addr_out3_n_101;
wire y_addr_out3_n_102;
wire y_addr_out3_n_103;
wire y_addr_out3_n_104;
wire y_addr_out3_n_105;
wire y_addr_out3_n_106;
wire y_addr_out3_n_107;
wire y_addr_out3_n_108;
wire y_addr_out3_n_109;
wire y_addr_out3_n_110;
wire y_addr_out3_n_111;
wire y_addr_out3_n_112;
wire y_addr_out3_n_113;
wire y_addr_out3_n_114;
wire y_addr_out3_n_115;
wire y_addr_out3_n_116;
wire y_addr_out3_n_117;
wire y_addr_out3_n_118;
wire y_addr_out3_n_119;
wire y_addr_out3_n_120;
wire y_addr_out3_n_121;
wire y_addr_out3_n_122;
wire y_addr_out3_n_123;
wire y_addr_out3_n_124;
wire y_addr_out3_n_125;
wire y_addr_out3_n_126;
wire y_addr_out3_n_127;
wire y_addr_out3_n_128;
wire y_addr_out3_n_129;
wire y_addr_out3_n_130;
wire y_addr_out3_n_131;
wire y_addr_out3_n_132;
wire y_addr_out3_n_133;
wire y_addr_out3_n_134;
wire y_addr_out3_n_135;
wire y_addr_out3_n_136;
wire y_addr_out3_n_137;
wire y_addr_out3_n_138;
wire y_addr_out3_n_139;
wire y_addr_out3_n_140;
wire y_addr_out3_n_141;
wire y_addr_out3_n_142;
wire y_addr_out3_n_143;
wire y_addr_out3_n_144;
wire y_addr_out3_n_145;
wire y_addr_out3_n_146;
wire y_addr_out3_n_147;
wire y_addr_out3_n_148;
wire y_addr_out3_n_149;
wire y_addr_out3_n_150;
wire y_addr_out3_n_151;
wire y_addr_out3_n_152;
wire y_addr_out3_n_153;
wire y_addr_out3_n_58;
wire y_addr_out3_n_59;
wire y_addr_out3_n_60;
wire y_addr_out3_n_61;
wire y_addr_out3_n_62;
wire y_addr_out3_n_63;
wire y_addr_out3_n_64;
wire y_addr_out3_n_65;
wire y_addr_out3_n_66;
wire y_addr_out3_n_67;
wire y_addr_out3_n_68;
wire y_addr_out3_n_69;
wire y_addr_out3_n_70;
wire y_addr_out3_n_71;
wire y_addr_out3_n_72;
wire y_addr_out3_n_73;
wire y_addr_out3_n_74;
wire y_addr_out3_n_75;
wire y_addr_out3_n_76;
wire y_addr_out3_n_77;
wire y_addr_out3_n_78;
wire y_addr_out3_n_79;
wire y_addr_out3_n_80;
wire y_addr_out3_n_81;
wire y_addr_out3_n_82;
wire y_addr_out3_n_83;
wire y_addr_out3_n_84;
wire y_addr_out3_n_85;
wire y_addr_out3_n_86;
wire y_addr_out3_n_87;
wire y_addr_out3_n_88;
wire y_addr_out3_n_89;
wire y_addr_out3_n_90;
wire y_addr_out3_n_91;
wire y_addr_out3_n_92;
wire y_addr_out3_n_93;
wire y_addr_out3_n_94;
wire y_addr_out3_n_95;
wire y_addr_out3_n_96;
wire y_addr_out3_n_97;
wire y_addr_out3_n_98;
wire y_addr_out3_n_99;
wire [0:0]NLW_x_addr_out0_carry_O_UNCONNECTED;
wire [3:1]NLW_x_addr_out0_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_x_addr_out0_carry__1_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__0_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__1_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__2_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__3_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__4_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__5_O_UNCONNECTED;
wire [3:1]NLW_x_addr_out2_carry__8_CO_UNCONNECTED;
wire [3:2]NLW_x_addr_out2_carry__8_O_UNCONNECTED;
wire NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3_CARRYOUT_UNCONNECTED;
wire NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3__0_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3__0_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_x_addr_out3__0_PCOUT_UNCONNECTED;
wire NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3__1_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3__1_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED;
wire NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3__2_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3__2_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_x_addr_out3__2_PCOUT_UNCONNECTED;
wire [0:0]NLW_y_addr_out0_carry_O_UNCONNECTED;
wire [3:1]NLW_y_addr_out0_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_y_addr_out0_carry__1_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__0_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__1_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__2_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__3_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__4_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__5_O_UNCONNECTED;
wire [3:1]NLW_y_addr_out2_carry__8_CO_UNCONNECTED;
wire [3:2]NLW_y_addr_out2_carry__8_O_UNCONNECTED;
wire NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3_CARRYOUT_UNCONNECTED;
wire NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3__0_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3__0_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_y_addr_out3__0_PCOUT_UNCONNECTED;
wire NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3__1_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3__1_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED;
wire NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3__2_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3__2_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_y_addr_out3__2_PCOUT_UNCONNECTED;
CARRY4 x_addr_out0_carry
(.CI(1'b0),
.CO({x_addr_out0_carry_n_0,x_addr_out0_carry_n_1,x_addr_out0_carry_n_2,x_addr_out0_carry_n_3}),
.CYINIT(1'b0),
.DI(p_1_in[17:14]),
.O({x_addr_out0[17:15],NLW_x_addr_out0_carry_O_UNCONNECTED[0]}),
.S({x_addr_out0_carry_i_1_n_0,x_addr_out0_carry_i_2_n_0,x_addr_out0_carry_i_3_n_0,x_addr_out0[14]}));
CARRY4 x_addr_out0_carry__0
(.CI(x_addr_out0_carry_n_0),
.CO({x_addr_out0_carry__0_n_0,x_addr_out0_carry__0_n_1,x_addr_out0_carry__0_n_2,x_addr_out0_carry__0_n_3}),
.CYINIT(1'b0),
.DI(p_1_in[21:18]),
.O(x_addr_out0[21:18]),
.S({x_addr_out0_carry__0_i_1_n_0,x_addr_out0_carry__0_i_2_n_0,x_addr_out0_carry__0_i_3_n_0,x_addr_out0_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_1
(.I0(p_1_in[21]),
.I1(t_x[7]),
.O(x_addr_out0_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_2
(.I0(p_1_in[20]),
.I1(t_x[6]),
.O(x_addr_out0_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_3
(.I0(p_1_in[19]),
.I1(t_x[5]),
.O(x_addr_out0_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_4
(.I0(p_1_in[18]),
.I1(t_x[4]),
.O(x_addr_out0_carry__0_i_4_n_0));
CARRY4 x_addr_out0_carry__1
(.CI(x_addr_out0_carry__0_n_0),
.CO({NLW_x_addr_out0_carry__1_CO_UNCONNECTED[3:1],x_addr_out0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,p_1_in[22]}),
.O({NLW_x_addr_out0_carry__1_O_UNCONNECTED[3:2],x_addr_out0[23:22]}),
.S({1'b0,1'b0,x_addr_out0_carry__1_i_1_n_0,x_addr_out0_carry__1_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__1_i_1
(.I0(p_1_in[23]),
.I1(t_x[9]),
.O(x_addr_out0_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__1_i_2
(.I0(p_1_in[22]),
.I1(t_x[8]),
.O(x_addr_out0_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_1
(.I0(p_1_in[17]),
.I1(t_x[3]),
.O(x_addr_out0_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_2
(.I0(p_1_in[16]),
.I1(t_x[2]),
.O(x_addr_out0_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_3
(.I0(p_1_in[15]),
.I1(t_x[1]),
.O(x_addr_out0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_4
(.I0(p_1_in[14]),
.I1(t_x[0]),
.O(x_addr_out0[14]));
CARRY4 x_addr_out2_carry
(.CI(1'b0),
.CO({x_addr_out2_carry_n_0,x_addr_out2_carry_n_1,x_addr_out2_carry_n_2,x_addr_out2_carry_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_102,x_addr_out3__1_n_103,x_addr_out3__1_n_104,x_addr_out3__1_n_105}),
.O(NLW_x_addr_out2_carry_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry_i_1_n_0,x_addr_out2_carry_i_2_n_0,x_addr_out2_carry_i_3_n_0,x_addr_out2_carry_i_4_n_0}));
CARRY4 x_addr_out2_carry__0
(.CI(x_addr_out2_carry_n_0),
.CO({x_addr_out2_carry__0_n_0,x_addr_out2_carry__0_n_1,x_addr_out2_carry__0_n_2,x_addr_out2_carry__0_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_98,x_addr_out3__1_n_99,x_addr_out3__1_n_100,x_addr_out3__1_n_101}),
.O(NLW_x_addr_out2_carry__0_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__0_i_1_n_0,x_addr_out2_carry__0_i_2_n_0,x_addr_out2_carry__0_i_3_n_0,x_addr_out2_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_1
(.I0(x_addr_out3__1_n_98),
.I1(x_addr_out3_n_98),
.O(x_addr_out2_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_2
(.I0(x_addr_out3__1_n_99),
.I1(x_addr_out3_n_99),
.O(x_addr_out2_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_3
(.I0(x_addr_out3__1_n_100),
.I1(x_addr_out3_n_100),
.O(x_addr_out2_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_4
(.I0(x_addr_out3__1_n_101),
.I1(x_addr_out3_n_101),
.O(x_addr_out2_carry__0_i_4_n_0));
CARRY4 x_addr_out2_carry__1
(.CI(x_addr_out2_carry__0_n_0),
.CO({x_addr_out2_carry__1_n_0,x_addr_out2_carry__1_n_1,x_addr_out2_carry__1_n_2,x_addr_out2_carry__1_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_94,x_addr_out3__1_n_95,x_addr_out3__1_n_96,x_addr_out3__1_n_97}),
.O(NLW_x_addr_out2_carry__1_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__1_i_1_n_0,x_addr_out2_carry__1_i_2_n_0,x_addr_out2_carry__1_i_3_n_0,x_addr_out2_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_1
(.I0(x_addr_out3__1_n_94),
.I1(x_addr_out3_n_94),
.O(x_addr_out2_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_2
(.I0(x_addr_out3__1_n_95),
.I1(x_addr_out3_n_95),
.O(x_addr_out2_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_3
(.I0(x_addr_out3__1_n_96),
.I1(x_addr_out3_n_96),
.O(x_addr_out2_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_4
(.I0(x_addr_out3__1_n_97),
.I1(x_addr_out3_n_97),
.O(x_addr_out2_carry__1_i_4_n_0));
CARRY4 x_addr_out2_carry__2
(.CI(x_addr_out2_carry__1_n_0),
.CO({x_addr_out2_carry__2_n_0,x_addr_out2_carry__2_n_1,x_addr_out2_carry__2_n_2,x_addr_out2_carry__2_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_90,x_addr_out3__1_n_91,x_addr_out3__1_n_92,x_addr_out3__1_n_93}),
.O(NLW_x_addr_out2_carry__2_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__2_i_1_n_0,x_addr_out2_carry__2_i_2_n_0,x_addr_out2_carry__2_i_3_n_0,x_addr_out2_carry__2_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_1
(.I0(x_addr_out3__1_n_90),
.I1(x_addr_out3_n_90),
.O(x_addr_out2_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_2
(.I0(x_addr_out3__1_n_91),
.I1(x_addr_out3_n_91),
.O(x_addr_out2_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_3
(.I0(x_addr_out3__1_n_92),
.I1(x_addr_out3_n_92),
.O(x_addr_out2_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_4
(.I0(x_addr_out3__1_n_93),
.I1(x_addr_out3_n_93),
.O(x_addr_out2_carry__2_i_4_n_0));
CARRY4 x_addr_out2_carry__3
(.CI(x_addr_out2_carry__2_n_0),
.CO({x_addr_out2_carry__3_n_0,x_addr_out2_carry__3_n_1,x_addr_out2_carry__3_n_2,x_addr_out2_carry__3_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_103,x_addr_out3__2_n_104,x_addr_out3__2_n_105,x_addr_out3__1_n_89}),
.O(NLW_x_addr_out2_carry__3_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__3_i_1_n_0,x_addr_out2_carry__3_i_2_n_0,x_addr_out2_carry__3_i_3_n_0,x_addr_out2_carry__3_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_1
(.I0(x_addr_out3__2_n_103),
.I1(x_addr_out3__0_n_103),
.O(x_addr_out2_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_2
(.I0(x_addr_out3__2_n_104),
.I1(x_addr_out3__0_n_104),
.O(x_addr_out2_carry__3_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_3
(.I0(x_addr_out3__2_n_105),
.I1(x_addr_out3__0_n_105),
.O(x_addr_out2_carry__3_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_4
(.I0(x_addr_out3__1_n_89),
.I1(x_addr_out3_n_89),
.O(x_addr_out2_carry__3_i_4_n_0));
CARRY4 x_addr_out2_carry__4
(.CI(x_addr_out2_carry__3_n_0),
.CO({x_addr_out2_carry__4_n_0,x_addr_out2_carry__4_n_1,x_addr_out2_carry__4_n_2,x_addr_out2_carry__4_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_99,x_addr_out3__2_n_100,x_addr_out3__2_n_101,x_addr_out3__2_n_102}),
.O(NLW_x_addr_out2_carry__4_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__4_i_1_n_0,x_addr_out2_carry__4_i_2_n_0,x_addr_out2_carry__4_i_3_n_0,x_addr_out2_carry__4_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_1
(.I0(x_addr_out3__2_n_99),
.I1(x_addr_out3__0_n_99),
.O(x_addr_out2_carry__4_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_2
(.I0(x_addr_out3__2_n_100),
.I1(x_addr_out3__0_n_100),
.O(x_addr_out2_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_3
(.I0(x_addr_out3__2_n_101),
.I1(x_addr_out3__0_n_101),
.O(x_addr_out2_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_4
(.I0(x_addr_out3__2_n_102),
.I1(x_addr_out3__0_n_102),
.O(x_addr_out2_carry__4_i_4_n_0));
CARRY4 x_addr_out2_carry__5
(.CI(x_addr_out2_carry__4_n_0),
.CO({x_addr_out2_carry__5_n_0,x_addr_out2_carry__5_n_1,x_addr_out2_carry__5_n_2,x_addr_out2_carry__5_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_95,x_addr_out3__2_n_96,x_addr_out3__2_n_97,x_addr_out3__2_n_98}),
.O(NLW_x_addr_out2_carry__5_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__5_i_1_n_0,x_addr_out2_carry__5_i_2_n_0,x_addr_out2_carry__5_i_3_n_0,x_addr_out2_carry__5_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_1
(.I0(x_addr_out3__2_n_95),
.I1(x_addr_out3__0_n_95),
.O(x_addr_out2_carry__5_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_2
(.I0(x_addr_out3__2_n_96),
.I1(x_addr_out3__0_n_96),
.O(x_addr_out2_carry__5_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_3
(.I0(x_addr_out3__2_n_97),
.I1(x_addr_out3__0_n_97),
.O(x_addr_out2_carry__5_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_4
(.I0(x_addr_out3__2_n_98),
.I1(x_addr_out3__0_n_98),
.O(x_addr_out2_carry__5_i_4_n_0));
CARRY4 x_addr_out2_carry__6
(.CI(x_addr_out2_carry__5_n_0),
.CO({x_addr_out2_carry__6_n_0,x_addr_out2_carry__6_n_1,x_addr_out2_carry__6_n_2,x_addr_out2_carry__6_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_91,x_addr_out3__2_n_92,x_addr_out3__2_n_93,x_addr_out3__2_n_94}),
.O(p_1_in[17:14]),
.S({x_addr_out2_carry__6_i_1_n_0,x_addr_out2_carry__6_i_2_n_0,x_addr_out2_carry__6_i_3_n_0,x_addr_out2_carry__6_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_1
(.I0(x_addr_out3__2_n_91),
.I1(x_addr_out3__0_n_91),
.O(x_addr_out2_carry__6_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_2
(.I0(x_addr_out3__2_n_92),
.I1(x_addr_out3__0_n_92),
.O(x_addr_out2_carry__6_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_3
(.I0(x_addr_out3__2_n_93),
.I1(x_addr_out3__0_n_93),
.O(x_addr_out2_carry__6_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_4
(.I0(x_addr_out3__2_n_94),
.I1(x_addr_out3__0_n_94),
.O(x_addr_out2_carry__6_i_4_n_0));
CARRY4 x_addr_out2_carry__7
(.CI(x_addr_out2_carry__6_n_0),
.CO({x_addr_out2_carry__7_n_0,x_addr_out2_carry__7_n_1,x_addr_out2_carry__7_n_2,x_addr_out2_carry__7_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_87,x_addr_out3__2_n_88,x_addr_out3__2_n_89,x_addr_out3__2_n_90}),
.O(p_1_in[21:18]),
.S({x_addr_out2_carry__7_i_1_n_0,x_addr_out2_carry__7_i_2_n_0,x_addr_out2_carry__7_i_3_n_0,x_addr_out2_carry__7_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_1
(.I0(x_addr_out3__2_n_87),
.I1(x_addr_out3__0_n_87),
.O(x_addr_out2_carry__7_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_2
(.I0(x_addr_out3__2_n_88),
.I1(x_addr_out3__0_n_88),
.O(x_addr_out2_carry__7_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_3
(.I0(x_addr_out3__2_n_89),
.I1(x_addr_out3__0_n_89),
.O(x_addr_out2_carry__7_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_4
(.I0(x_addr_out3__2_n_90),
.I1(x_addr_out3__0_n_90),
.O(x_addr_out2_carry__7_i_4_n_0));
CARRY4 x_addr_out2_carry__8
(.CI(x_addr_out2_carry__7_n_0),
.CO({NLW_x_addr_out2_carry__8_CO_UNCONNECTED[3:1],x_addr_out2_carry__8_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,x_addr_out3__2_n_86}),
.O({NLW_x_addr_out2_carry__8_O_UNCONNECTED[3:2],p_1_in[23:22]}),
.S({1'b0,1'b0,x_addr_out2_carry__8_i_1_n_0,x_addr_out2_carry__8_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__8_i_1
(.I0(x_addr_out3__2_n_85),
.I1(x_addr_out3__0_n_85),
.O(x_addr_out2_carry__8_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__8_i_2
(.I0(x_addr_out3__2_n_86),
.I1(x_addr_out3__0_n_86),
.O(x_addr_out2_carry__8_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_1
(.I0(x_addr_out3__1_n_102),
.I1(x_addr_out3_n_102),
.O(x_addr_out2_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_2
(.I0(x_addr_out3__1_n_103),
.I1(x_addr_out3_n_103),
.O(x_addr_out2_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_3
(.I0(x_addr_out3__1_n_104),
.I1(x_addr_out3_n_104),
.O(x_addr_out2_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_4
(.I0(x_addr_out3__1_n_105),
.I1(x_addr_out3_n_105),
.O(x_addr_out2_carry_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m01[15],rot_m01[15],rot_m01}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3_OVERFLOW_UNCONNECTED),
.P({x_addr_out3_n_58,x_addr_out3_n_59,x_addr_out3_n_60,x_addr_out3_n_61,x_addr_out3_n_62,x_addr_out3_n_63,x_addr_out3_n_64,x_addr_out3_n_65,x_addr_out3_n_66,x_addr_out3_n_67,x_addr_out3_n_68,x_addr_out3_n_69,x_addr_out3_n_70,x_addr_out3_n_71,x_addr_out3_n_72,x_addr_out3_n_73,x_addr_out3_n_74,x_addr_out3_n_75,x_addr_out3_n_76,x_addr_out3_n_77,x_addr_out3_n_78,x_addr_out3_n_79,x_addr_out3_n_80,x_addr_out3_n_81,x_addr_out3_n_82,x_addr_out3_n_83,x_addr_out3_n_84,x_addr_out3_n_85,x_addr_out3_n_86,x_addr_out3_n_87,x_addr_out3_n_88,x_addr_out3_n_89,x_addr_out3_n_90,x_addr_out3_n_91,x_addr_out3_n_92,x_addr_out3_n_93,x_addr_out3_n_94,x_addr_out3_n_95,x_addr_out3_n_96,x_addr_out3_n_97,x_addr_out3_n_98,x_addr_out3_n_99,x_addr_out3_n_100,x_addr_out3_n_101,x_addr_out3_n_102,x_addr_out3_n_103,x_addr_out3_n_104,x_addr_out3_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({x_addr_out3_n_106,x_addr_out3_n_107,x_addr_out3_n_108,x_addr_out3_n_109,x_addr_out3_n_110,x_addr_out3_n_111,x_addr_out3_n_112,x_addr_out3_n_113,x_addr_out3_n_114,x_addr_out3_n_115,x_addr_out3_n_116,x_addr_out3_n_117,x_addr_out3_n_118,x_addr_out3_n_119,x_addr_out3_n_120,x_addr_out3_n_121,x_addr_out3_n_122,x_addr_out3_n_123,x_addr_out3_n_124,x_addr_out3_n_125,x_addr_out3_n_126,x_addr_out3_n_127,x_addr_out3_n_128,x_addr_out3_n_129,x_addr_out3_n_130,x_addr_out3_n_131,x_addr_out3_n_132,x_addr_out3_n_133,x_addr_out3_n_134,x_addr_out3_n_135,x_addr_out3_n_136,x_addr_out3_n_137,x_addr_out3_n_138,x_addr_out3_n_139,x_addr_out3_n_140,x_addr_out3_n_141,x_addr_out3_n_142,x_addr_out3_n_143,x_addr_out3_n_144,x_addr_out3_n_145,x_addr_out3_n_146,x_addr_out3_n_147,x_addr_out3_n_148,x_addr_out3_n_149,x_addr_out3_n_150,x_addr_out3_n_151,x_addr_out3_n_152,x_addr_out3_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3__0
(.A({rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3__0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3__0_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED),
.P({x_addr_out3__0_n_58,x_addr_out3__0_n_59,x_addr_out3__0_n_60,x_addr_out3__0_n_61,x_addr_out3__0_n_62,x_addr_out3__0_n_63,x_addr_out3__0_n_64,x_addr_out3__0_n_65,x_addr_out3__0_n_66,x_addr_out3__0_n_67,x_addr_out3__0_n_68,x_addr_out3__0_n_69,x_addr_out3__0_n_70,x_addr_out3__0_n_71,x_addr_out3__0_n_72,x_addr_out3__0_n_73,x_addr_out3__0_n_74,x_addr_out3__0_n_75,x_addr_out3__0_n_76,x_addr_out3__0_n_77,x_addr_out3__0_n_78,x_addr_out3__0_n_79,x_addr_out3__0_n_80,x_addr_out3__0_n_81,x_addr_out3__0_n_82,x_addr_out3__0_n_83,x_addr_out3__0_n_84,x_addr_out3__0_n_85,x_addr_out3__0_n_86,x_addr_out3__0_n_87,x_addr_out3__0_n_88,x_addr_out3__0_n_89,x_addr_out3__0_n_90,x_addr_out3__0_n_91,x_addr_out3__0_n_92,x_addr_out3__0_n_93,x_addr_out3__0_n_94,x_addr_out3__0_n_95,x_addr_out3__0_n_96,x_addr_out3__0_n_97,x_addr_out3__0_n_98,x_addr_out3__0_n_99,x_addr_out3__0_n_100,x_addr_out3__0_n_101,x_addr_out3__0_n_102,x_addr_out3__0_n_103,x_addr_out3__0_n_104,x_addr_out3__0_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED),
.PCIN({x_addr_out3_n_106,x_addr_out3_n_107,x_addr_out3_n_108,x_addr_out3_n_109,x_addr_out3_n_110,x_addr_out3_n_111,x_addr_out3_n_112,x_addr_out3_n_113,x_addr_out3_n_114,x_addr_out3_n_115,x_addr_out3_n_116,x_addr_out3_n_117,x_addr_out3_n_118,x_addr_out3_n_119,x_addr_out3_n_120,x_addr_out3_n_121,x_addr_out3_n_122,x_addr_out3_n_123,x_addr_out3_n_124,x_addr_out3_n_125,x_addr_out3_n_126,x_addr_out3_n_127,x_addr_out3_n_128,x_addr_out3_n_129,x_addr_out3_n_130,x_addr_out3_n_131,x_addr_out3_n_132,x_addr_out3_n_133,x_addr_out3_n_134,x_addr_out3_n_135,x_addr_out3_n_136,x_addr_out3_n_137,x_addr_out3_n_138,x_addr_out3_n_139,x_addr_out3_n_140,x_addr_out3_n_141,x_addr_out3_n_142,x_addr_out3_n_143,x_addr_out3_n_144,x_addr_out3_n_145,x_addr_out3_n_146,x_addr_out3_n_147,x_addr_out3_n_148,x_addr_out3_n_149,x_addr_out3_n_150,x_addr_out3_n_151,x_addr_out3_n_152,x_addr_out3_n_153}),
.PCOUT(NLW_x_addr_out3__0_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3__1
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3__1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m00[15],rot_m00[15],rot_m00}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3__1_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED),
.P({x_addr_out3__1_n_58,x_addr_out3__1_n_59,x_addr_out3__1_n_60,x_addr_out3__1_n_61,x_addr_out3__1_n_62,x_addr_out3__1_n_63,x_addr_out3__1_n_64,x_addr_out3__1_n_65,x_addr_out3__1_n_66,x_addr_out3__1_n_67,x_addr_out3__1_n_68,x_addr_out3__1_n_69,x_addr_out3__1_n_70,x_addr_out3__1_n_71,x_addr_out3__1_n_72,x_addr_out3__1_n_73,x_addr_out3__1_n_74,x_addr_out3__1_n_75,x_addr_out3__1_n_76,x_addr_out3__1_n_77,x_addr_out3__1_n_78,x_addr_out3__1_n_79,x_addr_out3__1_n_80,x_addr_out3__1_n_81,x_addr_out3__1_n_82,x_addr_out3__1_n_83,x_addr_out3__1_n_84,x_addr_out3__1_n_85,x_addr_out3__1_n_86,x_addr_out3__1_n_87,x_addr_out3__1_n_88,x_addr_out3__1_n_89,x_addr_out3__1_n_90,x_addr_out3__1_n_91,x_addr_out3__1_n_92,x_addr_out3__1_n_93,x_addr_out3__1_n_94,x_addr_out3__1_n_95,x_addr_out3__1_n_96,x_addr_out3__1_n_97,x_addr_out3__1_n_98,x_addr_out3__1_n_99,x_addr_out3__1_n_100,x_addr_out3__1_n_101,x_addr_out3__1_n_102,x_addr_out3__1_n_103,x_addr_out3__1_n_104,x_addr_out3__1_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({x_addr_out3__1_n_106,x_addr_out3__1_n_107,x_addr_out3__1_n_108,x_addr_out3__1_n_109,x_addr_out3__1_n_110,x_addr_out3__1_n_111,x_addr_out3__1_n_112,x_addr_out3__1_n_113,x_addr_out3__1_n_114,x_addr_out3__1_n_115,x_addr_out3__1_n_116,x_addr_out3__1_n_117,x_addr_out3__1_n_118,x_addr_out3__1_n_119,x_addr_out3__1_n_120,x_addr_out3__1_n_121,x_addr_out3__1_n_122,x_addr_out3__1_n_123,x_addr_out3__1_n_124,x_addr_out3__1_n_125,x_addr_out3__1_n_126,x_addr_out3__1_n_127,x_addr_out3__1_n_128,x_addr_out3__1_n_129,x_addr_out3__1_n_130,x_addr_out3__1_n_131,x_addr_out3__1_n_132,x_addr_out3__1_n_133,x_addr_out3__1_n_134,x_addr_out3__1_n_135,x_addr_out3__1_n_136,x_addr_out3__1_n_137,x_addr_out3__1_n_138,x_addr_out3__1_n_139,x_addr_out3__1_n_140,x_addr_out3__1_n_141,x_addr_out3__1_n_142,x_addr_out3__1_n_143,x_addr_out3__1_n_144,x_addr_out3__1_n_145,x_addr_out3__1_n_146,x_addr_out3__1_n_147,x_addr_out3__1_n_148,x_addr_out3__1_n_149,x_addr_out3__1_n_150,x_addr_out3__1_n_151,x_addr_out3__1_n_152,x_addr_out3__1_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3__2
(.A({rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3__2_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3__2_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED),
.P({x_addr_out3__2_n_58,x_addr_out3__2_n_59,x_addr_out3__2_n_60,x_addr_out3__2_n_61,x_addr_out3__2_n_62,x_addr_out3__2_n_63,x_addr_out3__2_n_64,x_addr_out3__2_n_65,x_addr_out3__2_n_66,x_addr_out3__2_n_67,x_addr_out3__2_n_68,x_addr_out3__2_n_69,x_addr_out3__2_n_70,x_addr_out3__2_n_71,x_addr_out3__2_n_72,x_addr_out3__2_n_73,x_addr_out3__2_n_74,x_addr_out3__2_n_75,x_addr_out3__2_n_76,x_addr_out3__2_n_77,x_addr_out3__2_n_78,x_addr_out3__2_n_79,x_addr_out3__2_n_80,x_addr_out3__2_n_81,x_addr_out3__2_n_82,x_addr_out3__2_n_83,x_addr_out3__2_n_84,x_addr_out3__2_n_85,x_addr_out3__2_n_86,x_addr_out3__2_n_87,x_addr_out3__2_n_88,x_addr_out3__2_n_89,x_addr_out3__2_n_90,x_addr_out3__2_n_91,x_addr_out3__2_n_92,x_addr_out3__2_n_93,x_addr_out3__2_n_94,x_addr_out3__2_n_95,x_addr_out3__2_n_96,x_addr_out3__2_n_97,x_addr_out3__2_n_98,x_addr_out3__2_n_99,x_addr_out3__2_n_100,x_addr_out3__2_n_101,x_addr_out3__2_n_102,x_addr_out3__2_n_103,x_addr_out3__2_n_104,x_addr_out3__2_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED),
.PCIN({x_addr_out3__1_n_106,x_addr_out3__1_n_107,x_addr_out3__1_n_108,x_addr_out3__1_n_109,x_addr_out3__1_n_110,x_addr_out3__1_n_111,x_addr_out3__1_n_112,x_addr_out3__1_n_113,x_addr_out3__1_n_114,x_addr_out3__1_n_115,x_addr_out3__1_n_116,x_addr_out3__1_n_117,x_addr_out3__1_n_118,x_addr_out3__1_n_119,x_addr_out3__1_n_120,x_addr_out3__1_n_121,x_addr_out3__1_n_122,x_addr_out3__1_n_123,x_addr_out3__1_n_124,x_addr_out3__1_n_125,x_addr_out3__1_n_126,x_addr_out3__1_n_127,x_addr_out3__1_n_128,x_addr_out3__1_n_129,x_addr_out3__1_n_130,x_addr_out3__1_n_131,x_addr_out3__1_n_132,x_addr_out3__1_n_133,x_addr_out3__1_n_134,x_addr_out3__1_n_135,x_addr_out3__1_n_136,x_addr_out3__1_n_137,x_addr_out3__1_n_138,x_addr_out3__1_n_139,x_addr_out3__1_n_140,x_addr_out3__1_n_141,x_addr_out3__1_n_142,x_addr_out3__1_n_143,x_addr_out3__1_n_144,x_addr_out3__1_n_145,x_addr_out3__1_n_146,x_addr_out3__1_n_147,x_addr_out3__1_n_148,x_addr_out3__1_n_149,x_addr_out3__1_n_150,x_addr_out3__1_n_151,x_addr_out3__1_n_152,x_addr_out3__1_n_153}),
.PCOUT(NLW_x_addr_out3__2_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED));
LUT4 #(
.INIT(16'h66F0))
\x_addr_out[0]_i_1
(.I0(p_1_in[14]),
.I1(t_x[0]),
.I2(x_addr_in[0]),
.I3(enable),
.O(\x_addr_out[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[1]_i_1
(.I0(x_addr_out0[15]),
.I1(x_addr_in[1]),
.I2(enable),
.O(\x_addr_out[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[2]_i_1
(.I0(x_addr_out0[16]),
.I1(x_addr_in[2]),
.I2(enable),
.O(\x_addr_out[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[3]_i_1
(.I0(x_addr_out0[17]),
.I1(x_addr_in[3]),
.I2(enable),
.O(\x_addr_out[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[4]_i_1
(.I0(x_addr_out0[18]),
.I1(x_addr_in[4]),
.I2(enable),
.O(\x_addr_out[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[5]_i_1
(.I0(x_addr_out0[19]),
.I1(x_addr_in[5]),
.I2(enable),
.O(\x_addr_out[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[6]_i_1
(.I0(x_addr_out0[20]),
.I1(x_addr_in[6]),
.I2(enable),
.O(\x_addr_out[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[7]_i_1
(.I0(x_addr_out0[21]),
.I1(x_addr_in[7]),
.I2(enable),
.O(\x_addr_out[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[8]_i_1
(.I0(x_addr_out0[22]),
.I1(x_addr_in[8]),
.I2(enable),
.O(\x_addr_out[8]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\x_addr_out[9]_i_1
(.I0(x_addr_out0[23]),
.I1(x_addr_in[9]),
.I2(enable),
.O(\x_addr_out[9]_i_1_n_0 ));
FDRE \x_addr_out_reg[0]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[0]_i_1_n_0 ),
.Q(x_addr_out[0]),
.R(1'b0));
FDRE \x_addr_out_reg[1]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[1]_i_1_n_0 ),
.Q(x_addr_out[1]),
.R(1'b0));
FDRE \x_addr_out_reg[2]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[2]_i_1_n_0 ),
.Q(x_addr_out[2]),
.R(1'b0));
FDRE \x_addr_out_reg[3]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[3]_i_1_n_0 ),
.Q(x_addr_out[3]),
.R(1'b0));
FDRE \x_addr_out_reg[4]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[4]_i_1_n_0 ),
.Q(x_addr_out[4]),
.R(1'b0));
FDRE \x_addr_out_reg[5]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[5]_i_1_n_0 ),
.Q(x_addr_out[5]),
.R(1'b0));
FDRE \x_addr_out_reg[6]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[6]_i_1_n_0 ),
.Q(x_addr_out[6]),
.R(1'b0));
FDRE \x_addr_out_reg[7]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[7]_i_1_n_0 ),
.Q(x_addr_out[7]),
.R(1'b0));
FDRE \x_addr_out_reg[8]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[8]_i_1_n_0 ),
.Q(x_addr_out[8]),
.R(1'b0));
FDRE \x_addr_out_reg[9]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[9]_i_1_n_0 ),
.Q(x_addr_out[9]),
.R(1'b0));
CARRY4 y_addr_out0_carry
(.CI(1'b0),
.CO({y_addr_out0_carry_n_0,y_addr_out0_carry_n_1,y_addr_out0_carry_n_2,y_addr_out0_carry_n_3}),
.CYINIT(1'b0),
.DI(y_addr_out2[31:28]),
.O({p_0_in[3:1],NLW_y_addr_out0_carry_O_UNCONNECTED[0]}),
.S({y_addr_out0_carry_i_1_n_0,y_addr_out0_carry_i_2_n_0,y_addr_out0_carry_i_3_n_0,y_addr_out0_carry_i_4_n_0}));
CARRY4 y_addr_out0_carry__0
(.CI(y_addr_out0_carry_n_0),
.CO({y_addr_out0_carry__0_n_0,y_addr_out0_carry__0_n_1,y_addr_out0_carry__0_n_2,y_addr_out0_carry__0_n_3}),
.CYINIT(1'b0),
.DI(y_addr_out2[35:32]),
.O(p_0_in[7:4]),
.S({y_addr_out0_carry__0_i_1_n_0,y_addr_out0_carry__0_i_2_n_0,y_addr_out0_carry__0_i_3_n_0,y_addr_out0_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_1
(.I0(y_addr_out2[35]),
.I1(t_y[7]),
.O(y_addr_out0_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_2
(.I0(y_addr_out2[34]),
.I1(t_y[6]),
.O(y_addr_out0_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_3
(.I0(y_addr_out2[33]),
.I1(t_y[5]),
.O(y_addr_out0_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_4
(.I0(y_addr_out2[32]),
.I1(t_y[4]),
.O(y_addr_out0_carry__0_i_4_n_0));
CARRY4 y_addr_out0_carry__1
(.CI(y_addr_out0_carry__0_n_0),
.CO({NLW_y_addr_out0_carry__1_CO_UNCONNECTED[3:1],y_addr_out0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,y_addr_out2[36]}),
.O({NLW_y_addr_out0_carry__1_O_UNCONNECTED[3:2],p_0_in[9:8]}),
.S({1'b0,1'b0,y_addr_out0_carry__1_i_1_n_0,y_addr_out0_carry__1_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__1_i_1
(.I0(y_addr_out2[37]),
.I1(t_y[9]),
.O(y_addr_out0_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__1_i_2
(.I0(y_addr_out2[36]),
.I1(t_y[8]),
.O(y_addr_out0_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_1
(.I0(y_addr_out2[31]),
.I1(t_y[3]),
.O(y_addr_out0_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_2
(.I0(y_addr_out2[30]),
.I1(t_y[2]),
.O(y_addr_out0_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_3
(.I0(y_addr_out2[29]),
.I1(t_y[1]),
.O(y_addr_out0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_4
(.I0(y_addr_out2[28]),
.I1(t_y[0]),
.O(y_addr_out0_carry_i_4_n_0));
CARRY4 y_addr_out2_carry
(.CI(1'b0),
.CO({y_addr_out2_carry_n_0,y_addr_out2_carry_n_1,y_addr_out2_carry_n_2,y_addr_out2_carry_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_102,y_addr_out3__1_n_103,y_addr_out3__1_n_104,y_addr_out3__1_n_105}),
.O(NLW_y_addr_out2_carry_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry_i_1_n_0,y_addr_out2_carry_i_2_n_0,y_addr_out2_carry_i_3_n_0,y_addr_out2_carry_i_4_n_0}));
CARRY4 y_addr_out2_carry__0
(.CI(y_addr_out2_carry_n_0),
.CO({y_addr_out2_carry__0_n_0,y_addr_out2_carry__0_n_1,y_addr_out2_carry__0_n_2,y_addr_out2_carry__0_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_98,y_addr_out3__1_n_99,y_addr_out3__1_n_100,y_addr_out3__1_n_101}),
.O(NLW_y_addr_out2_carry__0_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__0_i_1_n_0,y_addr_out2_carry__0_i_2_n_0,y_addr_out2_carry__0_i_3_n_0,y_addr_out2_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_1
(.I0(y_addr_out3__1_n_98),
.I1(y_addr_out3_n_98),
.O(y_addr_out2_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_2
(.I0(y_addr_out3__1_n_99),
.I1(y_addr_out3_n_99),
.O(y_addr_out2_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_3
(.I0(y_addr_out3__1_n_100),
.I1(y_addr_out3_n_100),
.O(y_addr_out2_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_4
(.I0(y_addr_out3__1_n_101),
.I1(y_addr_out3_n_101),
.O(y_addr_out2_carry__0_i_4_n_0));
CARRY4 y_addr_out2_carry__1
(.CI(y_addr_out2_carry__0_n_0),
.CO({y_addr_out2_carry__1_n_0,y_addr_out2_carry__1_n_1,y_addr_out2_carry__1_n_2,y_addr_out2_carry__1_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_94,y_addr_out3__1_n_95,y_addr_out3__1_n_96,y_addr_out3__1_n_97}),
.O(NLW_y_addr_out2_carry__1_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__1_i_1_n_0,y_addr_out2_carry__1_i_2_n_0,y_addr_out2_carry__1_i_3_n_0,y_addr_out2_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_1
(.I0(y_addr_out3__1_n_94),
.I1(y_addr_out3_n_94),
.O(y_addr_out2_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_2
(.I0(y_addr_out3__1_n_95),
.I1(y_addr_out3_n_95),
.O(y_addr_out2_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_3
(.I0(y_addr_out3__1_n_96),
.I1(y_addr_out3_n_96),
.O(y_addr_out2_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_4
(.I0(y_addr_out3__1_n_97),
.I1(y_addr_out3_n_97),
.O(y_addr_out2_carry__1_i_4_n_0));
CARRY4 y_addr_out2_carry__2
(.CI(y_addr_out2_carry__1_n_0),
.CO({y_addr_out2_carry__2_n_0,y_addr_out2_carry__2_n_1,y_addr_out2_carry__2_n_2,y_addr_out2_carry__2_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_90,y_addr_out3__1_n_91,y_addr_out3__1_n_92,y_addr_out3__1_n_93}),
.O(NLW_y_addr_out2_carry__2_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__2_i_1_n_0,y_addr_out2_carry__2_i_2_n_0,y_addr_out2_carry__2_i_3_n_0,y_addr_out2_carry__2_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_1
(.I0(y_addr_out3__1_n_90),
.I1(y_addr_out3_n_90),
.O(y_addr_out2_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_2
(.I0(y_addr_out3__1_n_91),
.I1(y_addr_out3_n_91),
.O(y_addr_out2_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_3
(.I0(y_addr_out3__1_n_92),
.I1(y_addr_out3_n_92),
.O(y_addr_out2_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_4
(.I0(y_addr_out3__1_n_93),
.I1(y_addr_out3_n_93),
.O(y_addr_out2_carry__2_i_4_n_0));
CARRY4 y_addr_out2_carry__3
(.CI(y_addr_out2_carry__2_n_0),
.CO({y_addr_out2_carry__3_n_0,y_addr_out2_carry__3_n_1,y_addr_out2_carry__3_n_2,y_addr_out2_carry__3_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_103,y_addr_out3__2_n_104,y_addr_out3__2_n_105,y_addr_out3__1_n_89}),
.O(NLW_y_addr_out2_carry__3_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__3_i_1_n_0,y_addr_out2_carry__3_i_2_n_0,y_addr_out2_carry__3_i_3_n_0,y_addr_out2_carry__3_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_1
(.I0(y_addr_out3__2_n_103),
.I1(y_addr_out3__0_n_103),
.O(y_addr_out2_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_2
(.I0(y_addr_out3__2_n_104),
.I1(y_addr_out3__0_n_104),
.O(y_addr_out2_carry__3_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_3
(.I0(y_addr_out3__2_n_105),
.I1(y_addr_out3__0_n_105),
.O(y_addr_out2_carry__3_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_4
(.I0(y_addr_out3__1_n_89),
.I1(y_addr_out3_n_89),
.O(y_addr_out2_carry__3_i_4_n_0));
CARRY4 y_addr_out2_carry__4
(.CI(y_addr_out2_carry__3_n_0),
.CO({y_addr_out2_carry__4_n_0,y_addr_out2_carry__4_n_1,y_addr_out2_carry__4_n_2,y_addr_out2_carry__4_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_99,y_addr_out3__2_n_100,y_addr_out3__2_n_101,y_addr_out3__2_n_102}),
.O(NLW_y_addr_out2_carry__4_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__4_i_1_n_0,y_addr_out2_carry__4_i_2_n_0,y_addr_out2_carry__4_i_3_n_0,y_addr_out2_carry__4_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_1
(.I0(y_addr_out3__2_n_99),
.I1(y_addr_out3__0_n_99),
.O(y_addr_out2_carry__4_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_2
(.I0(y_addr_out3__2_n_100),
.I1(y_addr_out3__0_n_100),
.O(y_addr_out2_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_3
(.I0(y_addr_out3__2_n_101),
.I1(y_addr_out3__0_n_101),
.O(y_addr_out2_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_4
(.I0(y_addr_out3__2_n_102),
.I1(y_addr_out3__0_n_102),
.O(y_addr_out2_carry__4_i_4_n_0));
CARRY4 y_addr_out2_carry__5
(.CI(y_addr_out2_carry__4_n_0),
.CO({y_addr_out2_carry__5_n_0,y_addr_out2_carry__5_n_1,y_addr_out2_carry__5_n_2,y_addr_out2_carry__5_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_95,y_addr_out3__2_n_96,y_addr_out3__2_n_97,y_addr_out3__2_n_98}),
.O(NLW_y_addr_out2_carry__5_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__5_i_1_n_0,y_addr_out2_carry__5_i_2_n_0,y_addr_out2_carry__5_i_3_n_0,y_addr_out2_carry__5_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_1
(.I0(y_addr_out3__2_n_95),
.I1(y_addr_out3__0_n_95),
.O(y_addr_out2_carry__5_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_2
(.I0(y_addr_out3__2_n_96),
.I1(y_addr_out3__0_n_96),
.O(y_addr_out2_carry__5_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_3
(.I0(y_addr_out3__2_n_97),
.I1(y_addr_out3__0_n_97),
.O(y_addr_out2_carry__5_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_4
(.I0(y_addr_out3__2_n_98),
.I1(y_addr_out3__0_n_98),
.O(y_addr_out2_carry__5_i_4_n_0));
CARRY4 y_addr_out2_carry__6
(.CI(y_addr_out2_carry__5_n_0),
.CO({y_addr_out2_carry__6_n_0,y_addr_out2_carry__6_n_1,y_addr_out2_carry__6_n_2,y_addr_out2_carry__6_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_91,y_addr_out3__2_n_92,y_addr_out3__2_n_93,y_addr_out3__2_n_94}),
.O(y_addr_out2[31:28]),
.S({y_addr_out2_carry__6_i_1_n_0,y_addr_out2_carry__6_i_2_n_0,y_addr_out2_carry__6_i_3_n_0,y_addr_out2_carry__6_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_1
(.I0(y_addr_out3__2_n_91),
.I1(y_addr_out3__0_n_91),
.O(y_addr_out2_carry__6_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_2
(.I0(y_addr_out3__2_n_92),
.I1(y_addr_out3__0_n_92),
.O(y_addr_out2_carry__6_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_3
(.I0(y_addr_out3__2_n_93),
.I1(y_addr_out3__0_n_93),
.O(y_addr_out2_carry__6_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_4
(.I0(y_addr_out3__2_n_94),
.I1(y_addr_out3__0_n_94),
.O(y_addr_out2_carry__6_i_4_n_0));
CARRY4 y_addr_out2_carry__7
(.CI(y_addr_out2_carry__6_n_0),
.CO({y_addr_out2_carry__7_n_0,y_addr_out2_carry__7_n_1,y_addr_out2_carry__7_n_2,y_addr_out2_carry__7_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_87,y_addr_out3__2_n_88,y_addr_out3__2_n_89,y_addr_out3__2_n_90}),
.O(y_addr_out2[35:32]),
.S({y_addr_out2_carry__7_i_1_n_0,y_addr_out2_carry__7_i_2_n_0,y_addr_out2_carry__7_i_3_n_0,y_addr_out2_carry__7_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_1
(.I0(y_addr_out3__2_n_87),
.I1(y_addr_out3__0_n_87),
.O(y_addr_out2_carry__7_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_2
(.I0(y_addr_out3__2_n_88),
.I1(y_addr_out3__0_n_88),
.O(y_addr_out2_carry__7_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_3
(.I0(y_addr_out3__2_n_89),
.I1(y_addr_out3__0_n_89),
.O(y_addr_out2_carry__7_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_4
(.I0(y_addr_out3__2_n_90),
.I1(y_addr_out3__0_n_90),
.O(y_addr_out2_carry__7_i_4_n_0));
CARRY4 y_addr_out2_carry__8
(.CI(y_addr_out2_carry__7_n_0),
.CO({NLW_y_addr_out2_carry__8_CO_UNCONNECTED[3:1],y_addr_out2_carry__8_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,y_addr_out3__2_n_86}),
.O({NLW_y_addr_out2_carry__8_O_UNCONNECTED[3:2],y_addr_out2[37:36]}),
.S({1'b0,1'b0,y_addr_out2_carry__8_i_1_n_0,y_addr_out2_carry__8_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__8_i_1
(.I0(y_addr_out3__2_n_85),
.I1(y_addr_out3__0_n_85),
.O(y_addr_out2_carry__8_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__8_i_2
(.I0(y_addr_out3__2_n_86),
.I1(y_addr_out3__0_n_86),
.O(y_addr_out2_carry__8_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_1
(.I0(y_addr_out3__1_n_102),
.I1(y_addr_out3_n_102),
.O(y_addr_out2_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_2
(.I0(y_addr_out3__1_n_103),
.I1(y_addr_out3_n_103),
.O(y_addr_out2_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_3
(.I0(y_addr_out3__1_n_104),
.I1(y_addr_out3_n_104),
.O(y_addr_out2_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_4
(.I0(y_addr_out3__1_n_105),
.I1(y_addr_out3_n_105),
.O(y_addr_out2_carry_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m11[15],rot_m11[15],rot_m11}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3_OVERFLOW_UNCONNECTED),
.P({y_addr_out3_n_58,y_addr_out3_n_59,y_addr_out3_n_60,y_addr_out3_n_61,y_addr_out3_n_62,y_addr_out3_n_63,y_addr_out3_n_64,y_addr_out3_n_65,y_addr_out3_n_66,y_addr_out3_n_67,y_addr_out3_n_68,y_addr_out3_n_69,y_addr_out3_n_70,y_addr_out3_n_71,y_addr_out3_n_72,y_addr_out3_n_73,y_addr_out3_n_74,y_addr_out3_n_75,y_addr_out3_n_76,y_addr_out3_n_77,y_addr_out3_n_78,y_addr_out3_n_79,y_addr_out3_n_80,y_addr_out3_n_81,y_addr_out3_n_82,y_addr_out3_n_83,y_addr_out3_n_84,y_addr_out3_n_85,y_addr_out3_n_86,y_addr_out3_n_87,y_addr_out3_n_88,y_addr_out3_n_89,y_addr_out3_n_90,y_addr_out3_n_91,y_addr_out3_n_92,y_addr_out3_n_93,y_addr_out3_n_94,y_addr_out3_n_95,y_addr_out3_n_96,y_addr_out3_n_97,y_addr_out3_n_98,y_addr_out3_n_99,y_addr_out3_n_100,y_addr_out3_n_101,y_addr_out3_n_102,y_addr_out3_n_103,y_addr_out3_n_104,y_addr_out3_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({y_addr_out3_n_106,y_addr_out3_n_107,y_addr_out3_n_108,y_addr_out3_n_109,y_addr_out3_n_110,y_addr_out3_n_111,y_addr_out3_n_112,y_addr_out3_n_113,y_addr_out3_n_114,y_addr_out3_n_115,y_addr_out3_n_116,y_addr_out3_n_117,y_addr_out3_n_118,y_addr_out3_n_119,y_addr_out3_n_120,y_addr_out3_n_121,y_addr_out3_n_122,y_addr_out3_n_123,y_addr_out3_n_124,y_addr_out3_n_125,y_addr_out3_n_126,y_addr_out3_n_127,y_addr_out3_n_128,y_addr_out3_n_129,y_addr_out3_n_130,y_addr_out3_n_131,y_addr_out3_n_132,y_addr_out3_n_133,y_addr_out3_n_134,y_addr_out3_n_135,y_addr_out3_n_136,y_addr_out3_n_137,y_addr_out3_n_138,y_addr_out3_n_139,y_addr_out3_n_140,y_addr_out3_n_141,y_addr_out3_n_142,y_addr_out3_n_143,y_addr_out3_n_144,y_addr_out3_n_145,y_addr_out3_n_146,y_addr_out3_n_147,y_addr_out3_n_148,y_addr_out3_n_149,y_addr_out3_n_150,y_addr_out3_n_151,y_addr_out3_n_152,y_addr_out3_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3__0
(.A({rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3__0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3__0_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED),
.P({y_addr_out3__0_n_58,y_addr_out3__0_n_59,y_addr_out3__0_n_60,y_addr_out3__0_n_61,y_addr_out3__0_n_62,y_addr_out3__0_n_63,y_addr_out3__0_n_64,y_addr_out3__0_n_65,y_addr_out3__0_n_66,y_addr_out3__0_n_67,y_addr_out3__0_n_68,y_addr_out3__0_n_69,y_addr_out3__0_n_70,y_addr_out3__0_n_71,y_addr_out3__0_n_72,y_addr_out3__0_n_73,y_addr_out3__0_n_74,y_addr_out3__0_n_75,y_addr_out3__0_n_76,y_addr_out3__0_n_77,y_addr_out3__0_n_78,y_addr_out3__0_n_79,y_addr_out3__0_n_80,y_addr_out3__0_n_81,y_addr_out3__0_n_82,y_addr_out3__0_n_83,y_addr_out3__0_n_84,y_addr_out3__0_n_85,y_addr_out3__0_n_86,y_addr_out3__0_n_87,y_addr_out3__0_n_88,y_addr_out3__0_n_89,y_addr_out3__0_n_90,y_addr_out3__0_n_91,y_addr_out3__0_n_92,y_addr_out3__0_n_93,y_addr_out3__0_n_94,y_addr_out3__0_n_95,y_addr_out3__0_n_96,y_addr_out3__0_n_97,y_addr_out3__0_n_98,y_addr_out3__0_n_99,y_addr_out3__0_n_100,y_addr_out3__0_n_101,y_addr_out3__0_n_102,y_addr_out3__0_n_103,y_addr_out3__0_n_104,y_addr_out3__0_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED),
.PCIN({y_addr_out3_n_106,y_addr_out3_n_107,y_addr_out3_n_108,y_addr_out3_n_109,y_addr_out3_n_110,y_addr_out3_n_111,y_addr_out3_n_112,y_addr_out3_n_113,y_addr_out3_n_114,y_addr_out3_n_115,y_addr_out3_n_116,y_addr_out3_n_117,y_addr_out3_n_118,y_addr_out3_n_119,y_addr_out3_n_120,y_addr_out3_n_121,y_addr_out3_n_122,y_addr_out3_n_123,y_addr_out3_n_124,y_addr_out3_n_125,y_addr_out3_n_126,y_addr_out3_n_127,y_addr_out3_n_128,y_addr_out3_n_129,y_addr_out3_n_130,y_addr_out3_n_131,y_addr_out3_n_132,y_addr_out3_n_133,y_addr_out3_n_134,y_addr_out3_n_135,y_addr_out3_n_136,y_addr_out3_n_137,y_addr_out3_n_138,y_addr_out3_n_139,y_addr_out3_n_140,y_addr_out3_n_141,y_addr_out3_n_142,y_addr_out3_n_143,y_addr_out3_n_144,y_addr_out3_n_145,y_addr_out3_n_146,y_addr_out3_n_147,y_addr_out3_n_148,y_addr_out3_n_149,y_addr_out3_n_150,y_addr_out3_n_151,y_addr_out3_n_152,y_addr_out3_n_153}),
.PCOUT(NLW_y_addr_out3__0_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3__1
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3__1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m10[15],rot_m10[15],rot_m10}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3__1_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED),
.P({y_addr_out3__1_n_58,y_addr_out3__1_n_59,y_addr_out3__1_n_60,y_addr_out3__1_n_61,y_addr_out3__1_n_62,y_addr_out3__1_n_63,y_addr_out3__1_n_64,y_addr_out3__1_n_65,y_addr_out3__1_n_66,y_addr_out3__1_n_67,y_addr_out3__1_n_68,y_addr_out3__1_n_69,y_addr_out3__1_n_70,y_addr_out3__1_n_71,y_addr_out3__1_n_72,y_addr_out3__1_n_73,y_addr_out3__1_n_74,y_addr_out3__1_n_75,y_addr_out3__1_n_76,y_addr_out3__1_n_77,y_addr_out3__1_n_78,y_addr_out3__1_n_79,y_addr_out3__1_n_80,y_addr_out3__1_n_81,y_addr_out3__1_n_82,y_addr_out3__1_n_83,y_addr_out3__1_n_84,y_addr_out3__1_n_85,y_addr_out3__1_n_86,y_addr_out3__1_n_87,y_addr_out3__1_n_88,y_addr_out3__1_n_89,y_addr_out3__1_n_90,y_addr_out3__1_n_91,y_addr_out3__1_n_92,y_addr_out3__1_n_93,y_addr_out3__1_n_94,y_addr_out3__1_n_95,y_addr_out3__1_n_96,y_addr_out3__1_n_97,y_addr_out3__1_n_98,y_addr_out3__1_n_99,y_addr_out3__1_n_100,y_addr_out3__1_n_101,y_addr_out3__1_n_102,y_addr_out3__1_n_103,y_addr_out3__1_n_104,y_addr_out3__1_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({y_addr_out3__1_n_106,y_addr_out3__1_n_107,y_addr_out3__1_n_108,y_addr_out3__1_n_109,y_addr_out3__1_n_110,y_addr_out3__1_n_111,y_addr_out3__1_n_112,y_addr_out3__1_n_113,y_addr_out3__1_n_114,y_addr_out3__1_n_115,y_addr_out3__1_n_116,y_addr_out3__1_n_117,y_addr_out3__1_n_118,y_addr_out3__1_n_119,y_addr_out3__1_n_120,y_addr_out3__1_n_121,y_addr_out3__1_n_122,y_addr_out3__1_n_123,y_addr_out3__1_n_124,y_addr_out3__1_n_125,y_addr_out3__1_n_126,y_addr_out3__1_n_127,y_addr_out3__1_n_128,y_addr_out3__1_n_129,y_addr_out3__1_n_130,y_addr_out3__1_n_131,y_addr_out3__1_n_132,y_addr_out3__1_n_133,y_addr_out3__1_n_134,y_addr_out3__1_n_135,y_addr_out3__1_n_136,y_addr_out3__1_n_137,y_addr_out3__1_n_138,y_addr_out3__1_n_139,y_addr_out3__1_n_140,y_addr_out3__1_n_141,y_addr_out3__1_n_142,y_addr_out3__1_n_143,y_addr_out3__1_n_144,y_addr_out3__1_n_145,y_addr_out3__1_n_146,y_addr_out3__1_n_147,y_addr_out3__1_n_148,y_addr_out3__1_n_149,y_addr_out3__1_n_150,y_addr_out3__1_n_151,y_addr_out3__1_n_152,y_addr_out3__1_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3__2
(.A({rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3__2_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3__2_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED),
.P({y_addr_out3__2_n_58,y_addr_out3__2_n_59,y_addr_out3__2_n_60,y_addr_out3__2_n_61,y_addr_out3__2_n_62,y_addr_out3__2_n_63,y_addr_out3__2_n_64,y_addr_out3__2_n_65,y_addr_out3__2_n_66,y_addr_out3__2_n_67,y_addr_out3__2_n_68,y_addr_out3__2_n_69,y_addr_out3__2_n_70,y_addr_out3__2_n_71,y_addr_out3__2_n_72,y_addr_out3__2_n_73,y_addr_out3__2_n_74,y_addr_out3__2_n_75,y_addr_out3__2_n_76,y_addr_out3__2_n_77,y_addr_out3__2_n_78,y_addr_out3__2_n_79,y_addr_out3__2_n_80,y_addr_out3__2_n_81,y_addr_out3__2_n_82,y_addr_out3__2_n_83,y_addr_out3__2_n_84,y_addr_out3__2_n_85,y_addr_out3__2_n_86,y_addr_out3__2_n_87,y_addr_out3__2_n_88,y_addr_out3__2_n_89,y_addr_out3__2_n_90,y_addr_out3__2_n_91,y_addr_out3__2_n_92,y_addr_out3__2_n_93,y_addr_out3__2_n_94,y_addr_out3__2_n_95,y_addr_out3__2_n_96,y_addr_out3__2_n_97,y_addr_out3__2_n_98,y_addr_out3__2_n_99,y_addr_out3__2_n_100,y_addr_out3__2_n_101,y_addr_out3__2_n_102,y_addr_out3__2_n_103,y_addr_out3__2_n_104,y_addr_out3__2_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED),
.PCIN({y_addr_out3__1_n_106,y_addr_out3__1_n_107,y_addr_out3__1_n_108,y_addr_out3__1_n_109,y_addr_out3__1_n_110,y_addr_out3__1_n_111,y_addr_out3__1_n_112,y_addr_out3__1_n_113,y_addr_out3__1_n_114,y_addr_out3__1_n_115,y_addr_out3__1_n_116,y_addr_out3__1_n_117,y_addr_out3__1_n_118,y_addr_out3__1_n_119,y_addr_out3__1_n_120,y_addr_out3__1_n_121,y_addr_out3__1_n_122,y_addr_out3__1_n_123,y_addr_out3__1_n_124,y_addr_out3__1_n_125,y_addr_out3__1_n_126,y_addr_out3__1_n_127,y_addr_out3__1_n_128,y_addr_out3__1_n_129,y_addr_out3__1_n_130,y_addr_out3__1_n_131,y_addr_out3__1_n_132,y_addr_out3__1_n_133,y_addr_out3__1_n_134,y_addr_out3__1_n_135,y_addr_out3__1_n_136,y_addr_out3__1_n_137,y_addr_out3__1_n_138,y_addr_out3__1_n_139,y_addr_out3__1_n_140,y_addr_out3__1_n_141,y_addr_out3__1_n_142,y_addr_out3__1_n_143,y_addr_out3__1_n_144,y_addr_out3__1_n_145,y_addr_out3__1_n_146,y_addr_out3__1_n_147,y_addr_out3__1_n_148,y_addr_out3__1_n_149,y_addr_out3__1_n_150,y_addr_out3__1_n_151,y_addr_out3__1_n_152,y_addr_out3__1_n_153}),
.PCOUT(NLW_y_addr_out3__2_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED));
LUT2 #(
.INIT(4'h6))
\y_addr_out[0]_i_1
(.I0(y_addr_out2[28]),
.I1(t_y[0]),
.O(p_0_in[0]));
FDRE \y_addr_out_reg[0]
(.C(clk),
.CE(enable),
.D(p_0_in[0]),
.Q(y_addr_out[0]),
.R(1'b0));
FDRE \y_addr_out_reg[1]
(.C(clk),
.CE(enable),
.D(p_0_in[1]),
.Q(y_addr_out[1]),
.R(1'b0));
FDRE \y_addr_out_reg[2]
(.C(clk),
.CE(enable),
.D(p_0_in[2]),
.Q(y_addr_out[2]),
.R(1'b0));
FDRE \y_addr_out_reg[3]
(.C(clk),
.CE(enable),
.D(p_0_in[3]),
.Q(y_addr_out[3]),
.R(1'b0));
FDRE \y_addr_out_reg[4]
(.C(clk),
.CE(enable),
.D(p_0_in[4]),
.Q(y_addr_out[4]),
.R(1'b0));
FDRE \y_addr_out_reg[5]
(.C(clk),
.CE(enable),
.D(p_0_in[5]),
.Q(y_addr_out[5]),
.R(1'b0));
FDRE \y_addr_out_reg[6]
(.C(clk),
.CE(enable),
.D(p_0_in[6]),
.Q(y_addr_out[6]),
.R(1'b0));
FDRE \y_addr_out_reg[7]
(.C(clk),
.CE(enable),
.D(p_0_in[7]),
.Q(y_addr_out[7]),
.R(1'b0));
FDRE \y_addr_out_reg[8]
(.C(clk),
.CE(enable),
.D(p_0_in[8]),
.Q(y_addr_out[8]),
.R(1'b0));
FDRE \y_addr_out_reg[9]
(.C(clk),
.CE(enable),
.D(p_0_in[9]),
.Q(y_addr_out[9]),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MAJ3_2_V
`define SKY130_FD_SC_LS__MAJ3_2_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__maj3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__maj3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__MAJ3_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_BEHAVIORAL_V
`define SKY130_FD_SC_LP__OR3B_BEHAVIORAL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or3b (
X ,
A ,
B ,
C_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_BEHAVIORAL_V |
// megafunction wizard: %ROM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cm_rom_final.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cm_rom_final (
aclr,
address_a,
address_b,
clock,
q_a,
q_b);
input aclr;
input [8:0] address_a;
input [8:0] address_b;
input clock;
output [3:0] q_a;
output [3:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire sub_wire2 = 1'h0;
wire [3:0] sub_wire3 = 4'h0;
wire [3:0] q_b = sub_wire0[3:0];
wire [3:0] q_a = sub_wire1[3:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (sub_wire2),
.address_b (address_b),
.data_b (sub_wire3),
.wren_b (sub_wire2),
.aclr0 (aclr),
.address_a (address_a),
.data_a (sub_wire3),
.q_b (sub_wire0),
.q_a (sub_wire1)
// synopsys translate_off
,
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "output_CM_final.mif",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "CLEAR0",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 4,
altsyncram_component.width_b = 4,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "1"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "output_CM_final.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "4"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "output_CM_final.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q_a 0 0 4 0 OUTPUT NODEFVAL "q_a[3..0]"
// Retrieval info: USED_PORT: q_b 0 0 4 0 OUTPUT NODEFVAL "q_b[3..0]"
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 4 0 GND 0 0 4 0
// Retrieval info: CONNECT: @data_b 0 0 4 0 GND 0 0 4 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 4 0 @q_a 0 0 4 0
// Retrieval info: CONNECT: q_b 0 0 4 0 @q_b 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2B_SYMBOL_V
`define SKY130_FD_SC_LS__OR2B_SYMBOL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2B_SYMBOL_V
|
//---------------------------------------------------------------------//
// Name: addrgen.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Generates addresses.
//---------------------------------------------------------------------//
module addrdecode(
clk,
addr_in,
bank0_addr,
bank1_addr,
bank2_addr,
bank3_addr,
sel,
odd
);
input clk;
input [12:0]addr_in;
output [9:0]bank0_addr;
output [9:0]bank1_addr;
output [9:0]bank2_addr;
output [9:0]bank3_addr;
output [1:0]sel;
output odd;
reg [9:0] bank0_addr;
reg [9:0] bank1_addr;
reg [9:0] bank2_addr;
reg [9:0] bank3_addr;
reg [1:0] sel_dlya;
reg [1:0] sel_dlyb;
reg [1:0] sel;
reg odd_dlya;
reg odd_dlyb;
reg odd;
wire [9:0] addr = addr_in[12:3];
wire [9:0] addr_pone = addr_in[12:3] + 1;
// We delay odd and sel by 2 cycle to account for:
// (1) cycle of address decode time.
// (1) cycle of memory access time.
always@(posedge clk) begin
odd_dlya <= addr_in[0];
sel_dlya <= addr_in[2:1];
end
always@(posedge clk) begin
odd_dlyb <= odd_dlya;
sel_dlyb <= sel_dlya;
end
always@(posedge clk) begin
odd <= odd_dlyb;
sel <= sel_dlyb;
end
// Decode the address.
always@(posedge clk) begin
case(addr_in[2:1])
2'b00: begin
bank0_addr <= addr;
bank1_addr <= addr;
bank2_addr <= addr;
bank3_addr <= addr;
end
2'b01: begin
bank0_addr <= addr_pone;
bank1_addr <= addr;
bank2_addr <= addr;
bank3_addr <= addr;
end
2'b10: begin
bank0_addr <= addr_pone;
bank1_addr <= addr_pone;
bank2_addr <= addr;
bank3_addr <= addr;
end
2'b11: begin
bank0_addr <= addr_pone;
bank1_addr <= addr_pone;
bank2_addr <= addr_pone;
bank3_addr <= addr;
end
endcase
end
endmodule
|
(*
Copyright 2014 Cornell University
Copyright 2015 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Website: http://nuprl.org/html/verification/
Authors: Abhishek Anand & Vincent Rahli
*)
Require Import Program.
Require Import Coq.Init.Wf.
Require Export substitution.
Require Export computation1.
(** printing # $\times$ #×# *)
(** printing <=> $\Leftrightarrow$ #⇔# *)
(** Here, we define the lazy computation system of Nuprl. Since
it is a deterministic one, we can define it as a (partial)function.
The computation system of Nuprl is usually specified as a set
of one step reduction rules. So, our main goal here is to define the
[compute_step] function. Since a step of computation may result
in an error, we first lift [NTerm] to add more information
about the result of one step of computation :
[[
Inductive Comput_Result : Set :=
| csuccess : NTerm -> Comput_Result
| cfailure : String.string-> NTerm -> Comput_Result.
]]
For a [NonCanonicalOp], we say that some of its arguments are principal.
Principal arguments are
subterms that have to be evaluated to a canonical form before checking
whether the term itself is a redex or not.
For example, Nuprl's evaluator evaluates the first argument of [NApply]
until it converges (to a $\lambda$ term).
The first argument is principal for all [NonCanonicalOp]s.
For [NCompOp] and [NArithOp], even the second argument is canonical.
We present the one step computation function in the next page.
Although it refers to many other definitions, we describe it first so that
the overall structure of the computation is clear.
It is defined by pattern matching on the supplied [NTerm].
If it was a variable, it results in an error.
If it was an [oterm] with a canonical [Opid], there is nothing more
to be done. Remember that it is a lazy computation system and a term
whose outermost [Opid] is canonical is already in normal form.
If the head [Opid] [ncr] is non-canonical, it does more pattern matching
to futher expose the structure of its [BTerm]s.
In particular, the first [BTerm] is principal and
should have no bound variables and
its [NTerm] should be an [oterm] (and not a variable).
If the [Opid] of that [oterm] is canonical, some interesting action can
be taken. So, there is another (nested) pattern match that invokes
the appropriate function, depending on the head [Opid] ([ncr]).
However, if it was non-canonical, the last clause in the top-level
pattern match gets invoked and it recursively evaluates the first argument
[arg1nt] and (if the recursive calls succeeds,) repackages
the result at the same position with the surroundings
unchanged.
In the nested pattern match, all but the cases for
[NCompOp] and [NArithOp] do not need to invoke recursive calls
of [compute_step]. However, in the cases of [NCompOp] and [NArithOp],
the first two(instead of one) arguments are principal and need to be
evaluated first. Hence, the notations [co] and [ca] also take
[compute_step] as an argument.
% \pagebreak %
*)
(* begin hide *)
Definition shallow_sub {o} (sub : @Sub o) :=
forall t, LIn t (range sub) -> size t = 1.
Lemma range_sub_filter_subset {o} :
forall (sub : @Sub o) l,
subset (range (sub_filter sub l)) (range sub).
Proof.
induction sub; introv; simpl; auto.
destruct a; boolvar; simpl.
- apply subset_cons1; auto.
- apply subset_cons2; auto.
Qed.
Lemma simple_size_lsubst_aux {o} :
forall (t : @NTerm o) sub,
shallow_sub sub
-> size (lsubst_aux t sub) = size t.
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; introv ss; allsimpl; tcsp.
- Case "vterm".
remember (sub_find sub v) as sf; symmetry in Heqsf; destruct sf; allsimpl; auto.
apply sub_find_some in Heqsf.
apply in_sub_eta in Heqsf; repnd.
apply ss in Heqsf; auto.
- Case "oterm".
f_equal; f_equal; allrw map_map; unfold compose.
apply eq_maps; introv i; destruct x as [l t]; simpl.
rw (ind t l); auto.
intros x j.
apply (ss x).
apply range_sub_filter_subset in j; auto.
Qed.
Lemma size_utoken {o} :
forall a, @size o (mk_utoken a) = 1.
Proof. sp. Qed.
Lemma simple_size_subst_aux {o} :
forall (t : @NTerm o) v u,
size u = 1
-> size (subst_aux t v u) = size t.
Proof.
introv e.
unfold subst_aux; apply simple_size_lsubst_aux.
unfold shallow_sub; simpl; introv k; sp; subst; auto.
Qed.
Lemma simple_size_subst {o} :
forall (t : @NTerm o) v u,
size u = 1
-> size (subst t v u) = size t.
Proof.
introv e.
pose proof (unfold_lsubst [(v,u)] t) as h; exrepnd.
unfold subst; rw h0.
rw @simple_size_lsubst_aux.
- apply alpha_eq_preserves_size in h1; auto.
- unfold shallow_sub; simpl; introv k; sp; subst; auto.
Qed.
Definition size_bs {o} (bs : list (@BTerm o)) :=
addl (map size_bterm bs).
(* end hide *)
(* We say that the first argument of any non-canonical term
is a principal argument with respect to computation. It means that
while evaluating a non-canonical term, its priciple argumens
must be first evaluated down to a normal form. *)
Definition compute_step_can {o}
(t : @NTerm o)
(ncr : NonCanonicalOp)
(arg1c : CanonicalOp)
(arg1bts : list BTerm)
(arg1 : NTerm)
(btsr : list BTerm)
(comp : Comput_Result) :=
match ncr with
| NApply => compute_step_apply arg1c t arg1bts btsr
| NEApply => compute_step_eapply btsr t comp arg1 ncr
| NApseq f => compute_step_apseq f arg1c t arg1bts btsr
| NFix => compute_step_fix t arg1 btsr
| NSpread => compute_step_spread arg1c t arg1bts btsr
| NDsup => compute_step_dsup arg1c t arg1bts btsr
| NDecide => compute_step_decide arg1c t arg1bts btsr
| NCbv => compute_step_cbv t arg1 btsr
| NSleep => compute_step_sleep arg1c t arg1bts btsr
| NTUni => compute_step_tuni arg1c t arg1bts btsr
| NMinus => compute_step_minus arg1c t arg1bts btsr
| NFresh => cfailure "fresh has a bound variable" t
| NTryCatch => compute_step_try t arg1 btsr
| NParallel => compute_step_parallel arg1c t arg1bts btsr
| NCompOp op => co btsr t arg1bts arg1c op comp arg1 ncr
| NArithOp op => ca btsr t arg1bts arg1c op comp arg1 ncr
| NCanTest top => compute_step_can_test top arg1c t arg1bts btsr
end.
(*
Function compute_step {o}
(lib : @library o)
(t : @NTerm o)
{measure size t} : Comput_Result :=
match t with
| vterm v => cfailure compute_step_error_not_closed t
| oterm (Can _) _ => csuccess t
| oterm (Mrk _) _ => csuccess t
| oterm (Exc _) _ => csuccess t
| oterm (NCan _) [] => cfailure "no args supplied" t
| oterm (NCan nc) (bterm [] (vterm v) :: bs) => cfailure compute_step_error_not_closed t
| oterm (NCan ncan) (bterm (v::vs) u :: bs) =>
let a := get_fresh_atom lib u in
compute_step_fresh lib ncan t v vs u bs
(@compute_step o lib (subst u v (mk_utoken a)))
a
| oterm (NCan ncr) (bterm [] (oterm (Can arg1c) arg1bts) :: btsr) =>
compute_step_can t ncr arg1c arg1bts (oterm (Can arg1c) arg1bts) btsr
(match btsr with
| bterm _ x :: _ => @compute_step o lib x
| _ => cfailure bad_args t
end)
(* assuming qst arg is always principal *)
(* if the principal argument is an exception, we raise the exception *)
| oterm (NCan ncr) ((bterm [] (oterm (Exc a) arg1bts))::btsr) =>
compute_step_catch ncr a t arg1bts btsr
(* if the principal argument is non-canonical or an abstraction then we compute on that term *)
| oterm (NCan ncr) ((bterm [] arg1nt)::btsr) =>
on_success (@compute_step o lib arg1nt) (fun f => oterm (NCan ncr) (bterm [] f :: btsr))
| oterm (Abs opabs) bs => compute_step_lib lib opabs bs
end.
*)
Definition compute_step_seq_apply {o}
(t : @NTerm o)
(f : ntseq)
(bs : list BTerm) :=
match bs with
| [bterm [] arg] => csuccess (mk_eapply (mk_ntseq f) arg)
| _ => cfailure bad_args t
end.
Definition compute_step_seq_can_test {o}
(t : NTerm)
(bs : list (@BTerm o)) :=
match bs with
| [bterm [] _, bterm [] a] => csuccess a
| _ => cfailure canonical_form_test_not_well_formed t
end.
Definition compute_step_seq {o}
(t : @NTerm o)
(ncr : NonCanonicalOp)
(f : ntseq)
(bs : list (@BTerm o))
(cstep : Comput_Result) :=
match ncr with
| NApply => compute_step_seq_apply t f bs
| NEApply => compute_step_eapply bs t cstep (mk_ntseq f) ncr
| NApseq _ => cfailure bad_args t
| NFix => compute_step_fix t (mk_ntseq f) bs
| NSpread => cfailure bad_args t
| NDsup => cfailure bad_args t
| NDecide => cfailure bad_args t
| NCbv => compute_step_cbv t (mk_ntseq f) bs
| NSleep => cfailure bad_args t
| NTUni => cfailure bad_args t
| NMinus => cfailure bad_args t
| NFresh => cfailure bad_args t
| NTryCatch => compute_step_try t (mk_ntseq f) bs
| NParallel => cfailure bad_args t
| NCompOp _ => cfailure bad_args t
| NArithOp _ => cfailure bad_args t
| NCanTest _ => compute_step_seq_can_test t bs
end.
(*
(**
This generates a very complicated term, we'll do that by hand below in
[compute_step'].
*)
Program Fixpoint compute_step_pf {o}
(lib : @library o)
(t : @NTerm o)
{measure (size t)} : Comput_Result :=
match t with
| vterm v => cfailure compute_step_error_not_closed t
| sterm _ => csuccess t
| oterm (Can _) _ => csuccess t
| oterm Exc _ => csuccess t
| oterm (NCan _) [] => cfailure "no args supplied" t
| oterm (NCan nc) (bterm [] (vterm v) :: bs) => cfailure compute_step_error_not_closed t
| oterm (NCan ncan) (bterm (v::vs) u :: bs) =>
let a := get_fresh_atom u in
compute_step_fresh lib ncan t v vs u bs
(compute_step_pf lib (subst u v (mk_utoken a)))
a
| oterm (NCan ncr) (bterm [] (oterm (Can arg1c) arg1bts as arg1) :: btsr) =>
compute_step_can t ncr arg1c arg1bts arg1 btsr
(match btsr with
| bterm _ x :: _ => compute_step_pf lib x
| _ => cfailure bad_args t
end)
| oterm (NCan ncr) (bterm [] (sterm f) :: btsr) =>
compute_step_seq t ncr f btsr
(match btsr with
| bterm _ x :: _ => compute_step_pf lib x
| _ => cfailure bad_args t
end)
(* assuming qst arg is always principal *)
(* if the principal argument is an exception, we raise the exception *)
| oterm (NCan ncr) ((bterm [] (oterm Exc arg1bts))::btsr) =>
compute_step_catch ncr t arg1bts btsr
(* if the principal argument is non-canonical or an abstraction then we compute on that term *)
| oterm (NCan ncr) ((bterm [] ((oterm _ _) as arg1nt))::btsr) =>
on_success (compute_step_pf lib arg1nt) (fun f => oterm (NCan ncr) (bterm [] f :: btsr))
| oterm (Abs opabs) bs => compute_step_lib lib opabs bs
end.
Obligation 1.
{ simpl; rw @simple_size_subst; auto; omega. }
Qed.
Obligation 2.
{ simpl; omega. }
Qed.
Obligation 4.
{ simpl; omega. }
Qed.
Obligation 6.
{ dands; introv; intro k; inversion k. }
Qed.
Obligation 6.
{ dands; introv; intro k; inversion k. }
Qed.
Obligation 7.
{ dands; introv; intro k; inversion k. }
Qed.
*)
(* begin hide *)
(*
Definition compute_step_pf_unfold {o}
(lib : @library o)
(t : @NTerm o) : Comput_Result :=
match t with
| vterm v => cfailure compute_step_error_not_closed t
| sterm _ => csuccess t
| oterm (Can _) _ => csuccess t
| oterm Exc _ => csuccess t
| oterm (NCan _) [] => cfailure "no args supplied" t
| oterm (NCan nc) (bterm [] (vterm v) :: bs) => cfailure compute_step_error_not_closed t
| oterm (NCan ncan) (bterm (v::vs) u :: bs) =>
let a := get_fresh_atom u in
compute_step_fresh lib ncan t v vs u bs
(compute_step_pf lib (subst u v (mk_utoken a)))
a
| oterm (NCan ncr) (bterm [] (oterm (Can arg1c) arg1bts as arg1) :: btsr) =>
compute_step_can t ncr arg1c arg1bts arg1 btsr
(match btsr with
| bterm _ x :: _ => compute_step_pf lib x
| _ => cfailure bad_args t
end)
(* assuming qst arg is always principal *)
(* if the principal argument is an exception, we raise the exception *)
| oterm (NCan ncr) ((bterm [] (oterm Exc arg1bts))::btsr) =>
compute_step_catch ncr t arg1bts btsr
(* if the principal argument is non-canonical or an abstraction then we compute on that term *)
| oterm (NCan ncr) ((bterm [] arg1nt)::btsr) =>
on_success (compute_step_pf lib arg1nt) (fun f => oterm (NCan ncr) (bterm [] f :: btsr))
| oterm (Abs opabs) bs => compute_step_lib lib opabs bs
end.
*)
(*
Lemma compute_step_pf_eq_unfold {o} :
forall lib (t : @NTerm o),
compute_step_pf lib t = compute_step_pf_unfold lib t.
Proof.
destruct t as [v|op bs]; try reflexivity.
dopid op as [can|ncan|exc|abs] Case; try reflexivity.
Case "NCan".
destruct bs; try reflexivity.
destruct b as [l1 t1].
destruct l1 as [|v vs].
- destruct t1 as [v1|op1 bs1]; try reflexivity.
dopid op1 as [can1|ncan1|exc1|abs1] SCase; try reflexivity.
+ destruct ncan; try reflexivity.
* destruct bs; try reflexivity.
simpl; boolvar; try reflexivity.
{ destruct b.
destruct l; try reflexivity.
- destruct n as [v2|op2 bs2]; try reflexivity.
+ unfold compute_step_pf.
unfold compute_step_pf_func.
unfold Fix_sub.
simpl.
boolvar; simpl; tcsp.
+ dopid op2 as [can2|ncan2|exc2|abs2] SSCas2; try reflexivity.
* unfold compute_step_pf.
unfold compute_step_pf_func.
unfold Fix_sub.
simpl.
boolvar; tcsp.
* unfold on_success.
unfold compute_step_pf at 1.
(*
Check compute_step_func.
Print compute_step_func.
unfold compute_step_func.
unfold Fix_sub.
simpl.
rw F_unfold.
t_fold_fix2.
Opaque Fix_F_sub2.
rw fold_fix2.
simpl.
SearchAbout Fix_F_sub.
*)
Abort.
*)
(** Let's now do that by hand using [Fix] *)
Lemma compute_step'_size1 {o} :
forall ncan v vs (u : @NTerm o) bs a,
size (subst u v (mk_utoken a)) < size (oterm (NCan ncan) (bterm (v::vs) u :: bs)).
Proof.
introv.
rw @simple_size_subst; simpl; try omega.
Qed.
Lemma compute_step'_size2 {o} :
forall ncr arg1c (arg1bts : list (@BTerm o)) l x bs,
size x < size (oterm (NCan ncr) (bterm [] (oterm (Can arg1c) arg1bts) :: bterm l x :: bs)).
Proof.
introv; simpl; omega.
Qed.
Lemma compute_step'_size3 {o} :
forall ncr x (bs : list (@BTerm o)),
size x < size (oterm (NCan ncr) (bterm [] x :: bs)).
Proof.
introv; simpl; omega.
Qed.
Lemma compute_step'_size4 {o} :
forall ncr f l x (bs : list (@BTerm o)),
size x < size (oterm (NCan ncr) (bterm [] (sterm f) :: bterm l x :: bs)).
Proof.
introv; simpl; omega.
Qed.
Definition compute_step {o}
(lib : @library o)
(t : @NTerm o) : Comput_Result :=
@Fix NTerm
(fun a b => lt (size a) (size b))
(measure_wf lt_wf size)
(fun _ => Comput_Result)
(fun t =>
match t with
| vterm v => fun _ => cfailure compute_step_error_not_closed t
| sterm _ => fun _ => csuccess t
| oterm (Can _) _ => fun _ => csuccess t
| oterm Exc _ => fun _ => csuccess t
| oterm (NCan _) [] => fun _ => cfailure "no args supplied" t
| oterm (NCan nc) (bterm [] (vterm v) :: bs) => fun _ => cfailure compute_step_error_not_closed t
| oterm (NCan ncan) (bterm (v::vs) u :: bs) =>
fun F =>
let a := get_fresh_atom u in
compute_step_fresh
lib ncan t v vs u bs
(F (subst u v (mk_utoken a))
(compute_step'_size1 ncan v vs u bs a))
a
| oterm (NCan ncr) (bterm [] (oterm (Can arg1c) arg1bts as arg1) :: btsr) =>
fun F => compute_step_can t ncr arg1c arg1bts arg1 btsr
((match btsr with
| bterm l x :: bs => fun F => F x (compute_step'_size2 ncr arg1c arg1bts l x bs)
| _ => fun _ => cfailure bad_args t
end) F)
| oterm (NCan ncr) (bterm [] (sterm f) :: btsr) =>
fun F => compute_step_seq t ncr f btsr
((match btsr with
| bterm l x :: bs => fun F => F x (compute_step'_size4 ncr f l x bs)
| _ => fun _ => cfailure bad_args t
end) F)
(* assuming qst arg is always principal *)
(* if the principal argument is an exception, we raise the exception *)
| oterm (NCan ncr) ((bterm [] (oterm Exc arg1bts))::btsr) =>
fun _ => compute_step_catch ncr t arg1bts btsr
(* if the principal argument is non-canonical or an abstraction then we compute on that term *)
| oterm (NCan ncr) ((bterm [] (oterm _ _ as arg1nt))::btsr) =>
fun F => on_success (F arg1nt (compute_step'_size3 ncr arg1nt btsr)) (fun f => oterm (NCan ncr) (bterm [] f :: btsr))
| oterm (Abs opabs) bs => fun F => compute_step_lib lib opabs bs
end)
t.
Definition compute_step_unfold {o}
(lib : @library o)
(t : @NTerm o) : Comput_Result :=
match t with
| vterm v => cfailure compute_step_error_not_closed t
| sterm _ => csuccess t
| oterm (Can _) _ => csuccess t
| oterm Exc _ => csuccess t
| oterm (NCan _) [] => cfailure "no args supplied" t
| oterm (NCan nc) (bterm [] (vterm v) :: bs) => cfailure compute_step_error_not_closed t
| oterm (NCan ncan) (bterm (v::vs) u :: bs) =>
let a := get_fresh_atom u in
compute_step_fresh lib ncan t v vs u bs
(compute_step lib (subst u v (mk_utoken a)))
a
| oterm (NCan ncr) (bterm [] (oterm (Can arg1c) arg1bts as arg1) :: btsr) =>
compute_step_can t ncr arg1c arg1bts arg1 btsr
(match btsr with
| bterm _ x :: _ => compute_step lib x
| _ => cfailure bad_args t
end)
| oterm (NCan ncr) (bterm [] (sterm f) :: btsr) =>
compute_step_seq t ncr f btsr
(match btsr with
| bterm _ x :: _ => compute_step lib x
| _ => cfailure bad_args t
end)
(* assuming qst arg is always principal *)
(* if the principal argument is an exception, we raise the exception *)
| oterm (NCan ncr) ((bterm [] (oterm Exc arg1bts))::btsr) =>
compute_step_catch ncr t arg1bts btsr
(* if the principal argument is non-canonical or an abstraction then we compute on that term *)
| oterm (NCan ncr) ((bterm [] arg1nt)::btsr) =>
on_success (compute_step lib arg1nt) (fun f => oterm (NCan ncr) (bterm [] f :: btsr))
| oterm (Abs opabs) bs => compute_step_lib lib opabs bs
end.
Lemma compute_step_eq_unfold {o} :
forall lib (t : @NTerm o),
compute_step lib t = compute_step_unfold lib t.
Proof.
destruct t as [v|f|op bs]; simpl; try reflexivity.
dopid op as [can|ncan|exc|abs] Case; try reflexivity.
destruct bs as [|b bs]; try reflexivity.
destruct b as [l t].
destruct l as [|v vs]; try reflexivity.
- destruct t as [v1|f1|op1 bs1]; try reflexivity.
{ unfold compute_step at 1.
destruct bs; try reflexivity;[].
destruct b.
destruct ncan; try reflexivity;[].
destruct l; try reflexivity;[].
destruct n; try reflexivity;[].
destruct o0; try reflexivity;[].
simpl.
rw Fix_eq; simpl; try reflexivity;[].
introv F.
destruct x as [v'|f'|op bs']; auto;[].
destruct op; auto;[].
destruct bs'; auto;[].
destruct b.
destruct l0.
- destruct n1; auto.
+ destruct bs'; auto.
destruct b; auto.
f_equal; tcsp.
+ destruct o0; try (complete (f_equal; tcsp));[].
destruct bs'; auto.
destruct b.
f_equal; tcsp.
- f_equal; tcsp.
}
dopid op1 as [can1|ncan1|exc1|abs2] SCase; try reflexivity.
+ unfold compute_step at 1.
destruct bs; try reflexivity.
destruct b.
rw Fix_eq; simpl.
* f_equal.
* introv F.
destruct x as [v'|f'|op bs']; auto.
destruct op; auto.
destruct bs'; auto.
destruct b;[].
destruct l0; auto.
{ destruct n1; auto.
{ destruct bs'; auto.
destruct b; auto.
f_equal; tcsp. }
destruct o0; auto; try (complete (f_equal; tcsp)).
destruct bs'; auto.
destruct b; auto.
apply f_equal; tcsp. }
{ f_equal; tcsp. }
+ unfold compute_step at 1.
rw Fix_eq; simpl.
* f_equal.
* introv F.
destruct x as [v'|f'|op bs']; auto.
destruct op; auto.
destruct bs'; auto.
destruct b;[].
destruct l; auto.
{ destruct n0; auto.
{ destruct bs'; auto.
destruct b.
f_equal; tcsp. }
destruct o0; auto; try (complete (f_equal; tcsp)).
destruct bs'; auto.
destruct b; auto.
apply f_equal; tcsp. }
{ f_equal; tcsp. }
- unfold compute_step at 1.
rw Fix_eq; simpl.
+ f_equal.
+ introv F.
destruct x as [v'|f'|op bs']; auto.
destruct op; auto.
destruct bs'; auto.
destruct b;[].
destruct l; auto.
{ destruct n0; auto.
{ destruct bs'; auto.
destruct b.
f_equal; tcsp. }
destruct o0; auto; try (complete (f_equal; tcsp)).
destruct bs'; auto.
destruct b; auto.
apply f_equal; tcsp. }
{ f_equal; tcsp. }
Qed.
(*
(**
Let's define this function another way by adding an extra parameter,
a [nat] that's supposed to be the size of the term
*)
Fixpoint compute_step'_aux {o}
(lib : @library o)
(t : @NTerm o)
(n : nat) : Comput_Result :=
match n with
| 0 => cfailure "" t
| S n =>
match t with
| vterm v => cfailure compute_step_error_not_closed t
| sterm _ => csuccess t
| oterm (Can _) _ => csuccess t
| oterm Exc _ => csuccess t
| oterm (NCan _) [] => cfailure "no args supplied" t
| oterm (NCan nc) (bterm [] (vterm v) :: bs) => cfailure compute_step_error_not_closed t
| oterm (NCan ncan) (bterm (v::vs) u :: bs) =>
let a := get_fresh_atom u in
compute_step_fresh lib ncan t v vs u bs
(compute_step'_aux lib (subst u v (mk_utoken a)) (n - size_bs bs))
a
| oterm (NCan ncr) (bterm [] (oterm (Can arg1c) arg1bts as arg1) :: btsr) =>
compute_step_can t ncr arg1c arg1bts arg1 btsr
(match btsr with
| bterm _ x :: xs => compute_step'_aux lib x (n - (size arg1 + size_bs xs))
| _ => cfailure bad_args t
end)
(* assuming qst arg is always principal *)
(* if the principal argument is an exception, we raise the exception *)
| oterm (NCan ncr) ((bterm [] (oterm Exc arg1bts))::btsr) =>
compute_step_catch ncr t arg1bts btsr
(* if the principal argument is non-canonical or an abstraction then we compute on that term *)
| oterm (NCan ncr) ((bterm [] arg1nt)::btsr) =>
on_success (compute_step'_aux lib arg1nt (n - size_bs btsr)) (fun f => oterm (NCan ncr) (bterm [] f :: btsr))
| oterm (Abs opabs) bs => compute_step_lib lib opabs bs
end
end.
Definition compute_step {o}
(lib : @library o)
(t : @NTerm o) : Comput_Result :=
compute_step_aux lib t (size t).
Definition compute_step_unfold {o}
(lib : @library o)
(t : @NTerm o) : Comput_Result :=
match t with
| vterm v => cfailure compute_step_error_not_closed t
| sterm _ => csuccess t
| oterm (Can _) _ => csuccess t
| oterm Exc _ => csuccess t
| oterm (NCan _) [] => cfailure "no args supplied" t
| oterm (NCan nc) (bterm [] (vterm v) :: bs) => cfailure compute_step_error_not_closed t
| oterm (NCan ncan) (bterm (v::vs) u :: bs) =>
let a := get_fresh_atom u in
compute_step_fresh lib ncan t v vs u bs
(compute_step lib (subst u v (mk_utoken a)))
a
| oterm (NCan ncr) (bterm [] (oterm (Can arg1c) arg1bts as arg1) :: btsr) =>
compute_step_can t ncr arg1c arg1bts arg1 btsr
(match btsr with
| bterm _ x :: xs => compute_step lib x
| _ => cfailure bad_args t
end)
(* assuming qst arg is always principal *)
(* if the principal argument is an exception, we raise the exception *)
| oterm (NCan ncr) ((bterm [] (oterm Exc arg1bts))::btsr) =>
compute_step_catch ncr t arg1bts btsr
(* if the principal argument is non-canonical or an abstraction then we compute on that term *)
| oterm (NCan ncr) ((bterm [] arg1nt)::btsr) =>
on_success (compute_step lib arg1nt) (fun f => oterm (NCan ncr) (bterm [] f :: btsr))
| oterm (Abs opabs) bs => compute_step_lib lib opabs bs
end.
Lemma compute_step_eq_unfold {o} :
forall lib (t : @NTerm o),
compute_step lib t = compute_step_unfold lib t.
Proof.
introv.
destruct t as [v|f|op bs]; try reflexivity.
destruct op; try reflexivity.
destruct bs; try reflexivity.
destruct b.
destruct l; try reflexivity.
- destruct n0; try reflexivity.
{ simpl.
unfold compute_step; simpl.
fold (size_bs bs).
assert (match size_bs bs with
| 0 => S (size_bs bs)
| S l => size_bs bs - l
end
= 1) as e.
{ remember (size_bs bs) as m; clear Heqm.
destruct m; auto.
rw <- minus_Sn_m; auto.
rw minus_diag; auto. }
rw e; clear e.
simpl; auto.
}
assert (match size_bs bs with
| 0 => S (addl (map size_bterm l) + size_bs bs)
| S l0 => addl (map size_bterm l) + size_bs bs - l0
end
= S (addl (map size_bterm l))) as e.
{ remember (size_bs bs) as m; clear Heqm.
destruct m; simpl; try omega. }
destruct o0; try reflexivity.
+ simpl.
unfold compute_step; simpl; auto.
f_equal.
destruct bs; try reflexivity.
destruct b; simpl.
rw plus_permute.
rw <- NPeano.Nat.add_sub_assoc; auto.
rw minus_diag.
rw plus_0_r; auto.
+ simpl.
unfold compute_step; simpl.
unfold on_success; simpl.
allfold (size_bs bs); rw e; simpl; auto.
+ simpl.
unfold compute_step; simpl.
allfold (size_bs bs); rw e; simpl; auto.
- simpl.
unfold compute_step; simpl.
allfold (size_bs bs).
rw <- NPeano.Nat.add_sub_assoc; auto.
rw minus_diag.
rw plus_0_r; auto.
rw @simple_size_subst; simpl; auto.
Qed.
*)
Opaque compute_step.
Tactic Notation "csunf" ident(h) := rewrite @compute_step_eq_unfold in h.
Tactic Notation "csunf" := rewrite @compute_step_eq_unfold.
Lemma compute_step_ncan_ncan {p} :
forall lib nc nc2 bt2 rest,
compute_step lib
(oterm (NCan nc) (bterm [] (oterm (@NCan p nc2) bt2) :: rest))
= match compute_step lib (oterm (NCan nc2) bt2) with
| csuccess f => csuccess (oterm (NCan nc) ((bterm [] f) :: rest))
| cfailure str ts => cfailure str ts
end.
Proof.
introv; csunf; simpl; auto.
Qed.
Lemma compute_step_ncan_abs {p} :
forall lib nc x bt2 rest,
compute_step lib
(oterm (NCan nc) (bterm [] (oterm (@Abs p x) bt2) :: rest))
= match compute_step_lib lib x bt2 with
| csuccess f => csuccess (oterm (NCan nc) ((bterm [] f) :: rest))
| cfailure str ts => cfailure str ts
end.
Proof.
introv; csunf; simpl; auto.
Qed.
Lemma compute_step_try_ncan {p} :
forall lib a nc (bts : list (@BTerm p)) v b,
compute_step lib (mk_try (oterm (NCan nc) bts) a v b)
= match compute_step lib (oterm (NCan nc) bts) with
| csuccess f => csuccess (mk_try f a v b)
| cfailure str ts => cfailure str ts
end.
Proof.
introv; csunf; simpl; auto.
Qed.
Lemma compute_step_try_abs {p} :
forall lib a x (bts : list (@BTerm p)) v b,
compute_step lib (mk_try (oterm (Abs x) bts) a v b)
= match compute_step_lib lib x bts with
| csuccess f => csuccess (mk_try f a v b)
| cfailure str ts => cfailure str ts
end.
Proof.
introv; csunf; simpl; auto.
Qed.
Example comp_test1 {p} :
forall lib,
compute_step lib (mk_apply (mk_lam nvarx (vterm nvarx)) (mk_nat 0))
= csuccess (@mk_nat p 0).
Proof.
reflexivity.
Qed.
Example comp_test2 {p} :
forall lib,
compute_step lib
(mk_apply
(mk_apply (mk_lam nvarx (vterm nvarx)) (mk_lam nvarx (vterm nvarx)))
(mk_nat 0))
= csuccess (mk_apply (mk_lam nvarx (vterm nvarx)) (@mk_nat p 0)).
Proof.
reflexivity.
Qed.
(*
Program Fixpoint div2 (n : nat) {measure n} :
{ x : nat | n = 2 * x \/ n = 2 * x + 1 } :=
match n with
| S (S p) => S (div2 p)
| _ => O
end.
Next Obligation.
destruct (div2 p (div2_obligation_1 (S (S p)) div2 p eq_refl)).
repndors; subst; allsimpl; try omega.
Qed.
Next Obligation.
clear div2.
induction n; try omega.
autodimp IHn hyp; tcsp.
introv k; subst.
pose proof (H (S p)); sp.
repndors; subst; tcsp.
pose proof (H 0); sp.
Qed.
Lemma div2_prop :
forall n, projT1 (div2 n) <= n.
Proof.
induction n; simpl; auto.
destruct n; simpl.
Qed.
*)
Example comp_test_ex_1 {p} :
forall lib,
compute_step lib
(mk_try
(mk_add (mk_nat 1) (mk_nat 1))
(mk_token "")
nvarx
(mk_var nvarx))
= csuccess (mk_try
(mk_nat 2)
(mk_token "")
nvarx
(@mk_var p nvarx)).
Proof.
introv; csunf; simpl; auto.
Qed.
Example comp_test_ex3 {p} :
forall lib,
compute_step lib
(mk_try
(mk_add (mk_nat 1) (mk_exception (mk_token "") mk_zero))
(mk_token "")
nvarx
(mk_var nvarx))
= csuccess (mk_try
(mk_exception (mk_token "") mk_zero)
(mk_token "")
nvarx
(@mk_var p nvarx)).
Proof.
introv; csunf; simpl; auto.
Qed.
Definition maybe_compute_step {o} lib (t : @NTerm o) :=
match compute_step lib t with
| csuccess x => x
| cfailure _ _ => t
end.
Example comp_test_ex4 {p} :
forall lib,
on_success
(compute_step lib
(mk_try
(mk_exception (mk_token "") mk_zero)
(mk_token "")
nvarx
(mk_var nvarx)))
(fun x => maybe_compute_step lib x)
= csuccess (@mk_zero p).
Proof.
introv; csunf; simpl.
unfold maybe_compute_step.
csunf; simpl; unfold co; boolvar; simpl; boolvar; ginv; tcsp.
Qed.
Lemma compute_step_value {p} :
forall lib t, (@isvalue p t) -> compute_step lib t = csuccess t.
Proof.
introv h.
inversion h; subst.
allapply @iscan_implies; repndors; exrepnd; subst; reflexivity.
Qed.
Lemma compute_step_ovalue {p} :
forall lib t, @isovalue p t -> compute_step lib t = csuccess t.
Proof.
introv h.
inversion h; subst.
allapply @iscan_implies; repndors; exrepnd; subst; reflexivity.
Qed.
Definition compute_1step {p} lib (t u : @CTerm p) :=
compute_step lib (get_cterm t) = csuccess (get_cterm u).
(* end hide *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr/sky130_fd_sc_hd__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_hd__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_SYMBOL_V
`define SKY130_FD_SC_LP__EINVP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX4_2_V
`define SKY130_FD_SC_MS__MUX4_2_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux4_2 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux4_2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX4_2_V
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* FIFO-based PL Free Pool
* ============-==========
*
* Serves next free PL id. Tail flits sent on output link replenish free PL pool
*
* One free PL pool per output port
*
*/
module LAG_pl_free_pool (flits_tail, flits_valid,
// Unrestricted free pool
pl_alloc_status, // PL allocation status
pl_allocated, // which PLs were allocated on this cycle?
pl_empty, // is downstream FIFO associated with PL empty?
clk, rst_n);
parameter num_pls_global = 4; // in router
parameter num_pls_local = 4; // at this output port
parameter fifo_free_pool = 0; // organise free pool as FIFO (offer at most one PL per output port per cycle)
// only applicable if fifo_free_pool = 0
parameter only_allocate_pl_when_empty = 0; // only allow a PL to be allocated when it is empty
//-------
input [num_pls_global-1:0] flits_tail;
input [num_pls_global-1:0] flits_valid;
input [num_pls_global-1:0] pl_allocated;
output [num_pls_global-1:0] pl_alloc_status;
input [num_pls_global-1:0] pl_empty;
input clk, rst_n;
logic [num_pls_global-1:0] pl_alloc_status_reg;
pl_t fifo_out;
fifov_flags_t fifo_flags;
logic push;
integer i;
generate
// =============================================================
// Unrestricted PL allocation
// =============================================================
always@(posedge clk) begin
if (!rst_n) begin
for (i=0; i<num_pls_global; i++) begin:forpls2
pl_alloc_status_reg[i] <= (i<num_pls_local);
end
end else begin
for (i=0; i<num_pls_global; i++) begin:forpls
//
// PL consumed, mark PL as allocated
//
if (pl_allocated[i]) pl_alloc_status_reg[i]<=1'b0;
/*if(flits_valid[i])
$stop;
if(flits_tail[i])
$stop;*/
if (flits_valid[i] && flits_tail[i]) begin
//
// Tail flit departs, packets PL is ready to be used again
//
// what about single flit packets - test
assert (!pl_alloc_status_reg[i]);
pl_alloc_status_reg[i]<=1'b1;
end
end //for
end
end // always@ (posedge clk)
if (only_allocate_pl_when_empty) begin
assign pl_alloc_status = pl_alloc_status_reg & pl_empty;
end else begin
assign pl_alloc_status = pl_alloc_status_reg;
end
endgenerate
endmodule // LAG_pl_free_pool
|
//*******************************************************************/
// $File: full_adder.v
// $Date: 2016-03-22
// $Revision: 1.0 $
// $Author: ENCLab
// $State: 1.0 - Initial Release
//*******************************************************************/
// $Change History:
//
// Revision 1.0 ENCLab
// Initial Release
//*******************************************************************/
// $Description
//
// one-bit full adder
//
//*******************************************************************/
`timescale 1 ns / 1 ps
module full_adder
(
//----------------------------------------------------------------
// Input Ports
//----------------------------------------------------------------
input x_in, // one bit input data
input y_in, // one bit input data
input c_in, // one bit carry data
//----------------------------------------------------------------
// Output Ports
//----------------------------------------------------------------
output wire s_out, // sum of two input
output wire c_out // carry of two input
);
//----------------------------------------------------------------
// internal variables declaration
//----------------------------------------------------------------
wire wire_sum0;
wire wire_carry0;
wire wire_carry1;
//----------------------------------------------------------------
// submodule instantiation
//----------------------------------------------------------------
half_adder U0_half_adder (
.x_in ( x_in ),
.y_in ( y_in ),
.s_out ( wire_sum0 ),
.c_out ( wire_carry0 )
);
half_adder U1_half_adder (
.x_in ( wire_sum0 ),
.y_in ( c_in ),
.s_out ( s_out ),
.c_out ( wire_carry1 )
);
//----------------------------------------------------------------
// code for operation start
//----------------------------------------------------------------
// output port
assign c_out = ( wire_carry0 | wire_carry1 );
endmodule |
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_flush O 1 const
// lookup O 131
// RDY_lookup O 1
// RDY_insert O 1
// CLK I 1 clock
// RST_N I 1 reset
// lookup_asid I 16
// lookup_vpn I 27
// insert_asid I 16 reg
// insert_vpn I 27
// insert_pte I 64 reg
// insert_level I 2
// insert_pte_pa I 64 reg
// EN_flush I 1
// EN_insert I 1
//
// Combinational paths from inputs to outputs:
// (lookup_asid, lookup_vpn) -> lookup
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTLB(CLK,
RST_N,
EN_flush,
RDY_flush,
lookup_asid,
lookup_vpn,
lookup,
RDY_lookup,
insert_asid,
insert_vpn,
insert_pte,
insert_level,
insert_pte_pa,
EN_insert,
RDY_insert);
parameter [0 : 0] dmem_not_imem = 1'b0;
input CLK;
input RST_N;
// action method flush
input EN_flush;
output RDY_flush;
// value method lookup
input [15 : 0] lookup_asid;
input [26 : 0] lookup_vpn;
output [130 : 0] lookup;
output RDY_lookup;
// action method insert
input [15 : 0] insert_asid;
input [26 : 0] insert_vpn;
input [63 : 0] insert_pte;
input [1 : 0] insert_level;
input [63 : 0] insert_pte_pa;
input EN_insert;
output RDY_insert;
// signals for module outputs
wire [130 : 0] lookup;
wire RDY_flush, RDY_insert, RDY_lookup;
// register rg_flushing
reg rg_flushing;
wire rg_flushing$D_IN, rg_flushing$EN;
// register tlb0_valids_0
reg tlb0_valids_0;
wire tlb0_valids_0$D_IN, tlb0_valids_0$EN;
// register tlb0_valids_1
reg tlb0_valids_1;
wire tlb0_valids_1$D_IN, tlb0_valids_1$EN;
// register tlb0_valids_10
reg tlb0_valids_10;
wire tlb0_valids_10$D_IN, tlb0_valids_10$EN;
// register tlb0_valids_11
reg tlb0_valids_11;
wire tlb0_valids_11$D_IN, tlb0_valids_11$EN;
// register tlb0_valids_12
reg tlb0_valids_12;
wire tlb0_valids_12$D_IN, tlb0_valids_12$EN;
// register tlb0_valids_13
reg tlb0_valids_13;
wire tlb0_valids_13$D_IN, tlb0_valids_13$EN;
// register tlb0_valids_14
reg tlb0_valids_14;
wire tlb0_valids_14$D_IN, tlb0_valids_14$EN;
// register tlb0_valids_15
reg tlb0_valids_15;
wire tlb0_valids_15$D_IN, tlb0_valids_15$EN;
// register tlb0_valids_2
reg tlb0_valids_2;
wire tlb0_valids_2$D_IN, tlb0_valids_2$EN;
// register tlb0_valids_3
reg tlb0_valids_3;
wire tlb0_valids_3$D_IN, tlb0_valids_3$EN;
// register tlb0_valids_4
reg tlb0_valids_4;
wire tlb0_valids_4$D_IN, tlb0_valids_4$EN;
// register tlb0_valids_5
reg tlb0_valids_5;
wire tlb0_valids_5$D_IN, tlb0_valids_5$EN;
// register tlb0_valids_6
reg tlb0_valids_6;
wire tlb0_valids_6$D_IN, tlb0_valids_6$EN;
// register tlb0_valids_7
reg tlb0_valids_7;
wire tlb0_valids_7$D_IN, tlb0_valids_7$EN;
// register tlb0_valids_8
reg tlb0_valids_8;
wire tlb0_valids_8$D_IN, tlb0_valids_8$EN;
// register tlb0_valids_9
reg tlb0_valids_9;
wire tlb0_valids_9$D_IN, tlb0_valids_9$EN;
// register tlb1_valids_0
reg tlb1_valids_0;
wire tlb1_valids_0$D_IN, tlb1_valids_0$EN;
// register tlb1_valids_1
reg tlb1_valids_1;
wire tlb1_valids_1$D_IN, tlb1_valids_1$EN;
// register tlb1_valids_2
reg tlb1_valids_2;
wire tlb1_valids_2$D_IN, tlb1_valids_2$EN;
// register tlb1_valids_3
reg tlb1_valids_3;
wire tlb1_valids_3$D_IN, tlb1_valids_3$EN;
// register tlb1_valids_4
reg tlb1_valids_4;
wire tlb1_valids_4$D_IN, tlb1_valids_4$EN;
// register tlb1_valids_5
reg tlb1_valids_5;
wire tlb1_valids_5$D_IN, tlb1_valids_5$EN;
// register tlb1_valids_6
reg tlb1_valids_6;
wire tlb1_valids_6$D_IN, tlb1_valids_6$EN;
// register tlb1_valids_7
reg tlb1_valids_7;
wire tlb1_valids_7$D_IN, tlb1_valids_7$EN;
// register tlb2_valids_0
reg tlb2_valids_0;
wire tlb2_valids_0$D_IN, tlb2_valids_0$EN;
// register tlb2_valids_1
reg tlb2_valids_1;
wire tlb2_valids_1$D_IN, tlb2_valids_1$EN;
// register tlb2_valids_2
reg tlb2_valids_2;
wire tlb2_valids_2$D_IN, tlb2_valids_2$EN;
// register tlb2_valids_3
reg tlb2_valids_3;
wire tlb2_valids_3$D_IN, tlb2_valids_3$EN;
// ports of submodule tlb0_entries
wire [166 : 0] tlb0_entries$D_IN, tlb0_entries$D_OUT_1;
wire [3 : 0] tlb0_entries$ADDR_1,
tlb0_entries$ADDR_2,
tlb0_entries$ADDR_3,
tlb0_entries$ADDR_4,
tlb0_entries$ADDR_5,
tlb0_entries$ADDR_IN;
wire tlb0_entries$WE;
// ports of submodule tlb1_entries
wire [158 : 0] tlb1_entries$D_IN, tlb1_entries$D_OUT_1;
wire [2 : 0] tlb1_entries$ADDR_1,
tlb1_entries$ADDR_2,
tlb1_entries$ADDR_3,
tlb1_entries$ADDR_4,
tlb1_entries$ADDR_5,
tlb1_entries$ADDR_IN;
wire tlb1_entries$WE;
// ports of submodule tlb2_entries
wire [150 : 0] tlb2_entries$D_IN, tlb2_entries$D_OUT_1;
wire [1 : 0] tlb2_entries$ADDR_1,
tlb2_entries$ADDR_2,
tlb2_entries$ADDR_3,
tlb2_entries$ADDR_4,
tlb2_entries$ADDR_5,
tlb2_entries$ADDR_IN;
wire tlb2_entries$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_initialize,
CAN_FIRE_flush,
CAN_FIRE_insert,
WILL_FIRE_RL_rl_initialize,
WILL_FIRE_flush,
WILL_FIRE_insert;
// inputs to muxes for submodule ports
wire MUX_tlb0_valids_0$write_1__SEL_1,
MUX_tlb0_valids_1$write_1__SEL_1,
MUX_tlb0_valids_10$write_1__SEL_1,
MUX_tlb0_valids_11$write_1__SEL_1,
MUX_tlb0_valids_12$write_1__SEL_1,
MUX_tlb0_valids_13$write_1__SEL_1,
MUX_tlb0_valids_14$write_1__SEL_1,
MUX_tlb0_valids_15$write_1__SEL_1,
MUX_tlb0_valids_2$write_1__SEL_1,
MUX_tlb0_valids_3$write_1__SEL_1,
MUX_tlb0_valids_4$write_1__SEL_1,
MUX_tlb0_valids_5$write_1__SEL_1,
MUX_tlb0_valids_6$write_1__SEL_1,
MUX_tlb0_valids_7$write_1__SEL_1,
MUX_tlb0_valids_8$write_1__SEL_1,
MUX_tlb0_valids_9$write_1__SEL_1,
MUX_tlb1_valids_0$write_1__SEL_1,
MUX_tlb1_valids_1$write_1__SEL_1,
MUX_tlb1_valids_2$write_1__SEL_1,
MUX_tlb1_valids_3$write_1__SEL_1,
MUX_tlb1_valids_4$write_1__SEL_1,
MUX_tlb1_valids_5$write_1__SEL_1,
MUX_tlb1_valids_6$write_1__SEL_1,
MUX_tlb1_valids_7$write_1__SEL_1,
MUX_tlb2_valids_0$write_1__SEL_1,
MUX_tlb2_valids_1$write_1__SEL_1,
MUX_tlb2_valids_2$write_1__SEL_1,
MUX_tlb2_valids_3$write_1__SEL_1;
// remaining internal signals
reg SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20,
SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d41,
SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb2_v_ETC___d59;
wire [129 : 0] IF_SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_va_ETC___d85,
IF_SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb_ETC___d79,
IF_SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb_ETC___d84;
wire [63 : 0] x__h6482, x__h6502;
wire SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d26,
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d52,
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d70,
SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d47,
SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb2_v_ETC___d65;
// action method flush
assign RDY_flush = 1'd1 ;
assign CAN_FIRE_flush = 1'd1 ;
assign WILL_FIRE_flush = EN_flush ;
// value method lookup
assign lookup =
{ SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d70,
IF_SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_va_ETC___d85 } ;
assign RDY_lookup = !rg_flushing ;
// action method insert
assign RDY_insert = !rg_flushing ;
assign CAN_FIRE_insert = !rg_flushing ;
assign WILL_FIRE_insert = EN_insert ;
// submodule tlb0_entries
RegFile #(.addr_width(32'd4),
.data_width(32'd167),
.lo(4'h0),
.hi(4'd15)) tlb0_entries(.CLK(CLK),
.ADDR_1(tlb0_entries$ADDR_1),
.ADDR_2(tlb0_entries$ADDR_2),
.ADDR_3(tlb0_entries$ADDR_3),
.ADDR_4(tlb0_entries$ADDR_4),
.ADDR_5(tlb0_entries$ADDR_5),
.ADDR_IN(tlb0_entries$ADDR_IN),
.D_IN(tlb0_entries$D_IN),
.WE(tlb0_entries$WE),
.D_OUT_1(tlb0_entries$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule tlb1_entries
RegFile #(.addr_width(32'd3),
.data_width(32'd159),
.lo(3'h0),
.hi(3'd7)) tlb1_entries(.CLK(CLK),
.ADDR_1(tlb1_entries$ADDR_1),
.ADDR_2(tlb1_entries$ADDR_2),
.ADDR_3(tlb1_entries$ADDR_3),
.ADDR_4(tlb1_entries$ADDR_4),
.ADDR_5(tlb1_entries$ADDR_5),
.ADDR_IN(tlb1_entries$ADDR_IN),
.D_IN(tlb1_entries$D_IN),
.WE(tlb1_entries$WE),
.D_OUT_1(tlb1_entries$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule tlb2_entries
RegFile #(.addr_width(32'd2),
.data_width(32'd151),
.lo(2'h0),
.hi(2'd3)) tlb2_entries(.CLK(CLK),
.ADDR_1(tlb2_entries$ADDR_1),
.ADDR_2(tlb2_entries$ADDR_2),
.ADDR_3(tlb2_entries$ADDR_3),
.ADDR_4(tlb2_entries$ADDR_4),
.ADDR_5(tlb2_entries$ADDR_5),
.ADDR_IN(tlb2_entries$ADDR_IN),
.D_IN(tlb2_entries$D_IN),
.WE(tlb2_entries$WE),
.D_OUT_1(tlb2_entries$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// rule RL_rl_initialize
assign CAN_FIRE_RL_rl_initialize = rg_flushing ;
assign WILL_FIRE_RL_rl_initialize = rg_flushing ;
// inputs to muxes for submodule ports
assign MUX_tlb0_valids_0$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd0 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_1$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd1 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_10$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd10 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_11$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd11 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_12$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd12 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_13$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd13 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_14$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd14 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_15$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd15 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_2$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd2 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_3$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd3 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_4$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd4 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_5$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd5 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_6$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd6 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_7$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd7 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_8$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd8 && insert_level == 2'd0 ;
assign MUX_tlb0_valids_9$write_1__SEL_1 =
EN_insert && insert_vpn[3:0] == 4'd9 && insert_level == 2'd0 ;
assign MUX_tlb1_valids_0$write_1__SEL_1 =
EN_insert && insert_vpn[11:9] == 3'd0 && insert_level == 2'd1 ;
assign MUX_tlb1_valids_1$write_1__SEL_1 =
EN_insert && insert_vpn[11:9] == 3'd1 && insert_level == 2'd1 ;
assign MUX_tlb1_valids_2$write_1__SEL_1 =
EN_insert && insert_vpn[11:9] == 3'd2 && insert_level == 2'd1 ;
assign MUX_tlb1_valids_3$write_1__SEL_1 =
EN_insert && insert_vpn[11:9] == 3'd3 && insert_level == 2'd1 ;
assign MUX_tlb1_valids_4$write_1__SEL_1 =
EN_insert && insert_vpn[11:9] == 3'd4 && insert_level == 2'd1 ;
assign MUX_tlb1_valids_5$write_1__SEL_1 =
EN_insert && insert_vpn[11:9] == 3'd5 && insert_level == 2'd1 ;
assign MUX_tlb1_valids_6$write_1__SEL_1 =
EN_insert && insert_vpn[11:9] == 3'd6 && insert_level == 2'd1 ;
assign MUX_tlb1_valids_7$write_1__SEL_1 =
EN_insert && insert_vpn[11:9] == 3'd7 && insert_level == 2'd1 ;
assign MUX_tlb2_valids_0$write_1__SEL_1 =
EN_insert && insert_vpn[19:18] == 2'd0 && insert_level != 2'd0 &&
insert_level != 2'd1 ;
assign MUX_tlb2_valids_1$write_1__SEL_1 =
EN_insert && insert_vpn[19:18] == 2'd1 && insert_level != 2'd0 &&
insert_level != 2'd1 ;
assign MUX_tlb2_valids_2$write_1__SEL_1 =
EN_insert && insert_vpn[19:18] == 2'd2 && insert_level != 2'd0 &&
insert_level != 2'd1 ;
assign MUX_tlb2_valids_3$write_1__SEL_1 =
EN_insert && insert_vpn[19:18] == 2'd3 && insert_level != 2'd0 &&
insert_level != 2'd1 ;
// register rg_flushing
assign rg_flushing$D_IN = EN_flush ;
assign rg_flushing$EN = rg_flushing || EN_flush ;
// register tlb0_valids_0
assign tlb0_valids_0$D_IN = MUX_tlb0_valids_0$write_1__SEL_1 ;
assign tlb0_valids_0$EN =
EN_insert && insert_vpn[3:0] == 4'd0 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_1
assign tlb0_valids_1$D_IN = MUX_tlb0_valids_1$write_1__SEL_1 ;
assign tlb0_valids_1$EN =
EN_insert && insert_vpn[3:0] == 4'd1 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_10
assign tlb0_valids_10$D_IN = MUX_tlb0_valids_10$write_1__SEL_1 ;
assign tlb0_valids_10$EN =
EN_insert && insert_vpn[3:0] == 4'd10 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_11
assign tlb0_valids_11$D_IN = MUX_tlb0_valids_11$write_1__SEL_1 ;
assign tlb0_valids_11$EN =
EN_insert && insert_vpn[3:0] == 4'd11 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_12
assign tlb0_valids_12$D_IN = MUX_tlb0_valids_12$write_1__SEL_1 ;
assign tlb0_valids_12$EN =
EN_insert && insert_vpn[3:0] == 4'd12 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_13
assign tlb0_valids_13$D_IN = MUX_tlb0_valids_13$write_1__SEL_1 ;
assign tlb0_valids_13$EN =
EN_insert && insert_vpn[3:0] == 4'd13 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_14
assign tlb0_valids_14$D_IN = MUX_tlb0_valids_14$write_1__SEL_1 ;
assign tlb0_valids_14$EN =
EN_insert && insert_vpn[3:0] == 4'd14 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_15
assign tlb0_valids_15$D_IN = MUX_tlb0_valids_15$write_1__SEL_1 ;
assign tlb0_valids_15$EN =
EN_insert && insert_vpn[3:0] == 4'd15 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_2
assign tlb0_valids_2$D_IN = MUX_tlb0_valids_2$write_1__SEL_1 ;
assign tlb0_valids_2$EN =
EN_insert && insert_vpn[3:0] == 4'd2 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_3
assign tlb0_valids_3$D_IN = MUX_tlb0_valids_3$write_1__SEL_1 ;
assign tlb0_valids_3$EN =
EN_insert && insert_vpn[3:0] == 4'd3 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_4
assign tlb0_valids_4$D_IN = MUX_tlb0_valids_4$write_1__SEL_1 ;
assign tlb0_valids_4$EN =
EN_insert && insert_vpn[3:0] == 4'd4 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_5
assign tlb0_valids_5$D_IN = MUX_tlb0_valids_5$write_1__SEL_1 ;
assign tlb0_valids_5$EN =
EN_insert && insert_vpn[3:0] == 4'd5 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_6
assign tlb0_valids_6$D_IN = MUX_tlb0_valids_6$write_1__SEL_1 ;
assign tlb0_valids_6$EN =
EN_insert && insert_vpn[3:0] == 4'd6 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_7
assign tlb0_valids_7$D_IN = MUX_tlb0_valids_7$write_1__SEL_1 ;
assign tlb0_valids_7$EN =
EN_insert && insert_vpn[3:0] == 4'd7 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_8
assign tlb0_valids_8$D_IN = MUX_tlb0_valids_8$write_1__SEL_1 ;
assign tlb0_valids_8$EN =
EN_insert && insert_vpn[3:0] == 4'd8 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb0_valids_9
assign tlb0_valids_9$D_IN = MUX_tlb0_valids_9$write_1__SEL_1 ;
assign tlb0_valids_9$EN =
EN_insert && insert_vpn[3:0] == 4'd9 && insert_level == 2'd0 ||
rg_flushing ;
// register tlb1_valids_0
assign tlb1_valids_0$D_IN = MUX_tlb1_valids_0$write_1__SEL_1 ;
assign tlb1_valids_0$EN =
EN_insert && insert_vpn[11:9] == 3'd0 && insert_level == 2'd1 ||
rg_flushing ;
// register tlb1_valids_1
assign tlb1_valids_1$D_IN = MUX_tlb1_valids_1$write_1__SEL_1 ;
assign tlb1_valids_1$EN =
EN_insert && insert_vpn[11:9] == 3'd1 && insert_level == 2'd1 ||
rg_flushing ;
// register tlb1_valids_2
assign tlb1_valids_2$D_IN = MUX_tlb1_valids_2$write_1__SEL_1 ;
assign tlb1_valids_2$EN =
EN_insert && insert_vpn[11:9] == 3'd2 && insert_level == 2'd1 ||
rg_flushing ;
// register tlb1_valids_3
assign tlb1_valids_3$D_IN = MUX_tlb1_valids_3$write_1__SEL_1 ;
assign tlb1_valids_3$EN =
EN_insert && insert_vpn[11:9] == 3'd3 && insert_level == 2'd1 ||
rg_flushing ;
// register tlb1_valids_4
assign tlb1_valids_4$D_IN = MUX_tlb1_valids_4$write_1__SEL_1 ;
assign tlb1_valids_4$EN =
EN_insert && insert_vpn[11:9] == 3'd4 && insert_level == 2'd1 ||
rg_flushing ;
// register tlb1_valids_5
assign tlb1_valids_5$D_IN = MUX_tlb1_valids_5$write_1__SEL_1 ;
assign tlb1_valids_5$EN =
EN_insert && insert_vpn[11:9] == 3'd5 && insert_level == 2'd1 ||
rg_flushing ;
// register tlb1_valids_6
assign tlb1_valids_6$D_IN = MUX_tlb1_valids_6$write_1__SEL_1 ;
assign tlb1_valids_6$EN =
EN_insert && insert_vpn[11:9] == 3'd6 && insert_level == 2'd1 ||
rg_flushing ;
// register tlb1_valids_7
assign tlb1_valids_7$D_IN = MUX_tlb1_valids_7$write_1__SEL_1 ;
assign tlb1_valids_7$EN =
EN_insert && insert_vpn[11:9] == 3'd7 && insert_level == 2'd1 ||
rg_flushing ;
// register tlb2_valids_0
assign tlb2_valids_0$D_IN = MUX_tlb2_valids_0$write_1__SEL_1 ;
assign tlb2_valids_0$EN =
EN_insert && insert_vpn[19:18] == 2'd0 && insert_level != 2'd0 &&
insert_level != 2'd1 ||
rg_flushing ;
// register tlb2_valids_1
assign tlb2_valids_1$D_IN = MUX_tlb2_valids_1$write_1__SEL_1 ;
assign tlb2_valids_1$EN =
EN_insert && insert_vpn[19:18] == 2'd1 && insert_level != 2'd0 &&
insert_level != 2'd1 ||
rg_flushing ;
// register tlb2_valids_2
assign tlb2_valids_2$D_IN = MUX_tlb2_valids_2$write_1__SEL_1 ;
assign tlb2_valids_2$EN =
EN_insert && insert_vpn[19:18] == 2'd2 && insert_level != 2'd0 &&
insert_level != 2'd1 ||
rg_flushing ;
// register tlb2_valids_3
assign tlb2_valids_3$D_IN = MUX_tlb2_valids_3$write_1__SEL_1 ;
assign tlb2_valids_3$EN =
EN_insert && insert_vpn[19:18] == 2'd3 && insert_level != 2'd0 &&
insert_level != 2'd1 ||
rg_flushing ;
// submodule tlb0_entries
assign tlb0_entries$ADDR_1 = lookup_vpn[3:0] ;
assign tlb0_entries$ADDR_2 = 4'h0 ;
assign tlb0_entries$ADDR_3 = 4'h0 ;
assign tlb0_entries$ADDR_4 = 4'h0 ;
assign tlb0_entries$ADDR_5 = 4'h0 ;
assign tlb0_entries$ADDR_IN = insert_vpn[3:0] ;
assign tlb0_entries$D_IN =
{ insert_asid, insert_vpn[26:4], insert_pte, insert_pte_pa } ;
assign tlb0_entries$WE = EN_insert && insert_level == 2'd0 ;
// submodule tlb1_entries
assign tlb1_entries$ADDR_1 = lookup_vpn[11:9] ;
assign tlb1_entries$ADDR_2 = 3'h0 ;
assign tlb1_entries$ADDR_3 = 3'h0 ;
assign tlb1_entries$ADDR_4 = 3'h0 ;
assign tlb1_entries$ADDR_5 = 3'h0 ;
assign tlb1_entries$ADDR_IN = insert_vpn[11:9] ;
assign tlb1_entries$D_IN =
{ insert_asid, insert_vpn[26:12], insert_pte, insert_pte_pa } ;
assign tlb1_entries$WE = EN_insert && insert_level == 2'd1 ;
// submodule tlb2_entries
assign tlb2_entries$ADDR_1 = lookup_vpn[19:18] ;
assign tlb2_entries$ADDR_2 = 2'h0 ;
assign tlb2_entries$ADDR_3 = 2'h0 ;
assign tlb2_entries$ADDR_4 = 2'h0 ;
assign tlb2_entries$ADDR_5 = 2'h0 ;
assign tlb2_entries$ADDR_IN = insert_vpn[19:18] ;
assign tlb2_entries$D_IN =
{ insert_asid, insert_vpn[26:20], insert_pte, insert_pte_pa } ;
assign tlb2_entries$WE =
EN_insert && insert_level != 2'd0 && insert_level != 2'd1 ;
// remaining internal signals
assign IF_SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_va_ETC___d85 =
{ x__h6482, 2'd0, x__h6502 } |
IF_SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb_ETC___d79 |
IF_SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb_ETC___d84 ;
assign IF_SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb_ETC___d79 =
(SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d47 &&
tlb1_entries$D_OUT_1[142:128] == lookup_vpn[26:12]) ?
{ tlb1_entries$D_OUT_1[127:64],
2'd1,
tlb1_entries$D_OUT_1[63:0] } :
130'd0 ;
assign IF_SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb_ETC___d84 =
(SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb2_v_ETC___d65 &&
tlb2_entries$D_OUT_1[134:128] == lookup_vpn[26:20]) ?
{ tlb2_entries$D_OUT_1[127:64],
2'd2,
tlb2_entries$D_OUT_1[63:0] } :
130'd0 ;
assign SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d26 =
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 &&
(tlb0_entries$D_OUT_1[166:151] == lookup_asid ||
tlb0_entries$D_OUT_1[69]) ;
assign SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d52 =
(SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d26 &&
tlb0_entries$D_OUT_1[150:128] == lookup_vpn[26:4]) |
(SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d47 &&
tlb1_entries$D_OUT_1[142:128] == lookup_vpn[26:12]) ;
assign SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d70 =
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d52 |
(SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb2_v_ETC___d65 &&
tlb2_entries$D_OUT_1[134:128] == lookup_vpn[26:20]) ;
assign SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d47 =
SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d41 &&
(tlb1_entries$D_OUT_1[158:143] == lookup_asid ||
tlb1_entries$D_OUT_1[69]) ;
assign SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb2_v_ETC___d65 =
SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb2_v_ETC___d59 &&
(tlb2_entries$D_OUT_1[150:135] == lookup_asid ||
tlb2_entries$D_OUT_1[69]) ;
assign x__h6482 =
(SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d26 &&
tlb0_entries$D_OUT_1[150:128] == lookup_vpn[26:4]) ?
tlb0_entries$D_OUT_1[127:64] :
64'd0 ;
assign x__h6502 =
(SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d26 &&
tlb0_entries$D_OUT_1[150:128] == lookup_vpn[26:4]) ?
tlb0_entries$D_OUT_1[63:0] :
64'd0 ;
always@(lookup_vpn or
tlb0_valids_0 or
tlb0_valids_1 or
tlb0_valids_2 or
tlb0_valids_3 or
tlb0_valids_4 or
tlb0_valids_5 or
tlb0_valids_6 or
tlb0_valids_7 or
tlb0_valids_8 or
tlb0_valids_9 or
tlb0_valids_10 or
tlb0_valids_11 or
tlb0_valids_12 or
tlb0_valids_13 or tlb0_valids_14 or tlb0_valids_15)
begin
case (lookup_vpn[3:0])
4'd0:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_0;
4'd1:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_1;
4'd2:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_2;
4'd3:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_3;
4'd4:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_4;
4'd5:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_5;
4'd6:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_6;
4'd7:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_7;
4'd8:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_8;
4'd9:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_9;
4'd10:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_10;
4'd11:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_11;
4'd12:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_12;
4'd13:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_13;
4'd14:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_14;
4'd15:
SEL_ARR_tlb0_valids_0_tlb0_valids_1_tlb0_valid_ETC___d20 =
tlb0_valids_15;
endcase
end
always@(lookup_vpn or
tlb1_valids_0 or
tlb1_valids_1 or
tlb1_valids_2 or
tlb1_valids_3 or
tlb1_valids_4 or tlb1_valids_5 or tlb1_valids_6 or tlb1_valids_7)
begin
case (lookup_vpn[11:9])
3'd0:
SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d41 =
tlb1_valids_0;
3'd1:
SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d41 =
tlb1_valids_1;
3'd2:
SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d41 =
tlb1_valids_2;
3'd3:
SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d41 =
tlb1_valids_3;
3'd4:
SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d41 =
tlb1_valids_4;
3'd5:
SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d41 =
tlb1_valids_5;
3'd6:
SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d41 =
tlb1_valids_6;
3'd7:
SEL_ARR_tlb1_valids_0_1_tlb1_valids_1_2_tlb1_v_ETC___d41 =
tlb1_valids_7;
endcase
end
always@(lookup_vpn or
tlb2_valids_0 or tlb2_valids_1 or tlb2_valids_2 or tlb2_valids_3)
begin
case (lookup_vpn[19:18])
2'd0:
SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb2_v_ETC___d59 =
tlb2_valids_0;
2'd1:
SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb2_v_ETC___d59 =
tlb2_valids_1;
2'd2:
SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb2_v_ETC___d59 =
tlb2_valids_2;
2'd3:
SEL_ARR_tlb2_valids_0_3_tlb2_valids_1_4_tlb2_v_ETC___d59 =
tlb2_valids_3;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_flushing <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (rg_flushing$EN)
rg_flushing <= `BSV_ASSIGNMENT_DELAY rg_flushing$D_IN;
end
if (tlb0_valids_0$EN)
tlb0_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_0$D_IN;
if (tlb0_valids_1$EN)
tlb0_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_1$D_IN;
if (tlb0_valids_10$EN)
tlb0_valids_10 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_10$D_IN;
if (tlb0_valids_11$EN)
tlb0_valids_11 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_11$D_IN;
if (tlb0_valids_12$EN)
tlb0_valids_12 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_12$D_IN;
if (tlb0_valids_13$EN)
tlb0_valids_13 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_13$D_IN;
if (tlb0_valids_14$EN)
tlb0_valids_14 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_14$D_IN;
if (tlb0_valids_15$EN)
tlb0_valids_15 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_15$D_IN;
if (tlb0_valids_2$EN)
tlb0_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_2$D_IN;
if (tlb0_valids_3$EN)
tlb0_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_3$D_IN;
if (tlb0_valids_4$EN)
tlb0_valids_4 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_4$D_IN;
if (tlb0_valids_5$EN)
tlb0_valids_5 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_5$D_IN;
if (tlb0_valids_6$EN)
tlb0_valids_6 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_6$D_IN;
if (tlb0_valids_7$EN)
tlb0_valids_7 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_7$D_IN;
if (tlb0_valids_8$EN)
tlb0_valids_8 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_8$D_IN;
if (tlb0_valids_9$EN)
tlb0_valids_9 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_9$D_IN;
if (tlb1_valids_0$EN)
tlb1_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_0$D_IN;
if (tlb1_valids_1$EN)
tlb1_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_1$D_IN;
if (tlb1_valids_2$EN)
tlb1_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_2$D_IN;
if (tlb1_valids_3$EN)
tlb1_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_3$D_IN;
if (tlb1_valids_4$EN)
tlb1_valids_4 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_4$D_IN;
if (tlb1_valids_5$EN)
tlb1_valids_5 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_5$D_IN;
if (tlb1_valids_6$EN)
tlb1_valids_6 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_6$D_IN;
if (tlb1_valids_7$EN)
tlb1_valids_7 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_7$D_IN;
if (tlb2_valids_0$EN)
tlb2_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_0$D_IN;
if (tlb2_valids_1$EN)
tlb2_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_1$D_IN;
if (tlb2_valids_2$EN)
tlb2_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_2$D_IN;
if (tlb2_valids_3$EN)
tlb2_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_3$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_flushing = 1'h0;
tlb0_valids_0 = 1'h0;
tlb0_valids_1 = 1'h0;
tlb0_valids_10 = 1'h0;
tlb0_valids_11 = 1'h0;
tlb0_valids_12 = 1'h0;
tlb0_valids_13 = 1'h0;
tlb0_valids_14 = 1'h0;
tlb0_valids_15 = 1'h0;
tlb0_valids_2 = 1'h0;
tlb0_valids_3 = 1'h0;
tlb0_valids_4 = 1'h0;
tlb0_valids_5 = 1'h0;
tlb0_valids_6 = 1'h0;
tlb0_valids_7 = 1'h0;
tlb0_valids_8 = 1'h0;
tlb0_valids_9 = 1'h0;
tlb1_valids_0 = 1'h0;
tlb1_valids_1 = 1'h0;
tlb1_valids_2 = 1'h0;
tlb1_valids_3 = 1'h0;
tlb1_valids_4 = 1'h0;
tlb1_valids_5 = 1'h0;
tlb1_valids_6 = 1'h0;
tlb1_valids_7 = 1'h0;
tlb2_valids_0 = 1'h0;
tlb2_valids_1 = 1'h0;
tlb2_valids_2 = 1'h0;
tlb2_valids_3 = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkTLB
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn transaction asynchronous fifo.
*
*/
module rcn_fifo_async
(
input rst_in,
input clk_in,
input clk_out,
input [68:0] rcn_in,
input push,
output full,
output [68:0] rcn_out,
input pop,
output empty
);
parameter DEPTH = 16; // max 64 (can hold DEPTH-1 before full)
reg [1:0] cross_in;
reg [5:0] head_in;
reg [5:0] head_snapshot;
reg [5:0] tail_in;
reg [1:0] cross_out;
reg [5:0] head_out;
reg [5:0] tail_out;
reg [5:0] tail_snapshot;
always @ (posedge clk_in)
cross_in <= cross_out;
always @ (posedge clk_out or posedge rst_in)
if (rst_in)
cross_out <= 2'b00;
else
case (cross_in)
2'b00: cross_out <= 2'b01;
2'b01: cross_out <= 2'b11;
2'b11: cross_out <= 2'b10;
default: cross_out <= 2'b00;
endcase
wire [5:0] head_in_next = (head_in == (DEPTH - 1)) ? 6'd0 : head_in + 6'd1;
wire fifo_full = (head_in_next == tail_in);
always @ (posedge clk_in or posedge rst_in)
if (rst_in)
begin
head_in <= 6'd0;
head_snapshot <= 6'd0;
tail_in <= 6'd0;
end
else
begin
if (push)
head_in <= head_in_next;
case (cross_in)
2'b01: head_snapshot <= head_in;
2'b10: tail_in <= tail_snapshot;
endcase
end
wire [5:0] tail_out_next = (tail_out == (DEPTH - 1)) ? 6'd0 : tail_out + 6'd1;
wire fifo_empty = (tail_out == head_out);
always @ (posedge clk_out or posedge rst_in)
if (rst_in)
begin
head_out <= 6'd0;
tail_out <= 6'd0;
tail_snapshot <= 6'd0;
end
else
begin
if (pop)
tail_out <= tail_out_next;
case (cross_out)
2'b01: tail_snapshot <= tail_out;
2'b10: head_out <= head_snapshot;
endcase
end
reg [67:0] fifo[(DEPTH - 1):0];
always @ (posedge clk_in)
if (push)
fifo[head_in] <= rcn_in[67:0];
assign full = fifo_full;
assign empty = fifo_empty;
assign rcn_out = {!fifo_empty, fifo[tail_out]};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_sio_macro (
IN,
IN_H,
TIE_LO_ESD,
AMUXBUS_A,
AMUXBUS_B,
PAD,
PAD_A_ESD_0_H,
PAD_A_ESD_1_H,
PAD_A_NOESD_H,
VINREF_DFT,
VOUTREF_DFT,
DFT_REFGEN,
DM0,
DM1,
HLD_H_N,
HLD_H_N_REFGEN,
HLD_OVR,
IBUF_SEL,
IBUF_SEL_REFGEN,
INP_DIS,
ENABLE_H,
ENABLE_VDDA_H,
OE_N,
OUT,
SLOW,
VOH_SEL,
VOHREF,
VREF_SEL,
VREG_EN,
VREG_EN_REFGEN,
VTRIP_SEL,
VTRIP_SEL_REFGEN
);
wire VOUTREF;
wire VINREF;
wire REFLEAK_BIAS;
supply1 vddio;
supply1 vddio_q;
supply1 vdda;
supply1 vccd;
supply1 vswitch;
supply1 vcchib;
supply0 vssd;
supply0 vssio;
supply0 vssio_q;
supply0 vssa;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout VINREF_DFT;
inout VOUTREF_DFT;
input DFT_REFGEN;
input HLD_H_N_REFGEN;
input IBUF_SEL_REFGEN;
input ENABLE_VDDA_H;
input ENABLE_H;
input VOHREF;
input VREG_EN_REFGEN;
input VTRIP_SEL_REFGEN;
output [1:0] TIE_LO_ESD;
output [1:0] IN_H;
output [1:0] IN;
inout [1:0] PAD_A_NOESD_H;
inout [1:0] PAD;
inout [1:0] PAD_A_ESD_1_H;
inout [1:0] PAD_A_ESD_0_H;
input [1:0] SLOW;
input [1:0] VTRIP_SEL;
input [1:0] HLD_H_N;
input [1:0] VREG_EN;
input [2:0] VOH_SEL;
input [1:0] INP_DIS;
input [1:0] HLD_OVR;
input [1:0] OE_N;
input [1:0] VREF_SEL;
input [1:0] IBUF_SEL;
input [2:0] DM0;
input [2:0] DM1;
input [1:0] OUT;
reg notifier_enable_h_refgen,
notifier_vtrip_sel_refgen,
notifier_vreg_en_refgen,
notifier_ibuf_sel_refgen,
notifier_vref_sel,
notifier_vref_sel_int,
notifier_voh_sel,
notifier_dft_refgen;
reg notifier_enable_h_0;
reg notifier_hld_ovr_0;
reg notifier_dm_0;
reg notifier_inp_dis_0;
reg notifier_vtrip_sel_0;
reg notifier_slow_0;
reg notifier_oe_n_0;
reg notifier_out_0;
reg notifier_vreg_en_0;
reg notifier_ibuf_sel_0;
reg notifier_enable_h_1;
reg notifier_hld_ovr_1;
reg notifier_dm_1;
reg notifier_inp_dis_1;
reg notifier_vtrip_sel_1;
reg notifier_slow_1;
reg notifier_oe_n_1;
reg notifier_out_1;
reg notifier_vreg_en_1;
reg notifier_ibuf_sel_1;
wire enable_vdda_h_and_enable_h = ENABLE_VDDA_H==1'b1 && ENABLE_H==1'b1;
sky130_fd_io__top_refgen_new REFGEN (
.VOH_SEL (VOH_SEL[2:0]),
.VREF_SEL (VREF_SEL[1:0]),
.VOHREF (VOHREF),
.VINREF_DFT (VINREF_DFT),
.VOUTREF_DFT (VOUTREF_DFT),
.DFT_REFGEN (DFT_REFGEN),
.AMUXBUS_A (AMUXBUS_A),
.AMUXBUS_B (AMUXBUS_B),
.VOUTREF (VOUTREF),
.VREG_EN (VREG_EN_REFGEN),
.IBUF_SEL (IBUF_SEL_REFGEN),
.VINREF (VINREF),
.VTRIP_SEL (VTRIP_SEL_REFGEN),
.ENABLE_H (ENABLE_H),
.ENABLE_VDDA_H (ENABLE_VDDA_H),
.HLD_H_N (HLD_H_N_REFGEN),
.REFLEAK_BIAS (REFLEAK_BIAS)
);
sky130_fd_io__top_sio SIO_PAIR_1_ (
.PAD (PAD[1]),
.IN_H (IN_H[1]),
.DM (DM1[2:0]),
.HLD_H_N (HLD_H_N[1]),
.PAD_A_ESD_1_H (PAD_A_ESD_1_H[1]),
.PAD_A_ESD_0_H (PAD_A_ESD_0_H[1]),
.ENABLE_H (ENABLE_H),
.OUT (OUT[1]),
.OE_N (OE_N[1]),
.SLOW (SLOW[1]),
.VTRIP_SEL (VTRIP_SEL[1]),
.INP_DIS (INP_DIS[1]),
.TIE_LO_ESD (TIE_LO_ESD[1]),
.IN (IN[1]),
.VINREF (VINREF),
.VOUTREF (VOUTREF),
.REFLEAK_BIAS (REFLEAK_BIAS),
.PAD_A_NOESD_H (PAD_A_NOESD_H[1]),
.VREG_EN (VREG_EN[1]),
.IBUF_SEL (IBUF_SEL[1]),
.HLD_OVR (HLD_OVR[1])
);
sky130_fd_io__top_sio SIO_PAIR_0_ (
.PAD (PAD[0]),
.IN_H (IN_H[0]),
.DM (DM0[2:0]),
.HLD_H_N (HLD_H_N[0]),
.PAD_A_ESD_1_H (PAD_A_ESD_1_H[0]),
.PAD_A_ESD_0_H (PAD_A_ESD_0_H[0]),
.ENABLE_H (ENABLE_H),
.OUT (OUT[0]),
.OE_N (OE_N[0]),
.SLOW (SLOW[0]),
.VTRIP_SEL (VTRIP_SEL[0]),
.INP_DIS (INP_DIS[0]),
.TIE_LO_ESD (TIE_LO_ESD[0]),
.IN (IN[0]),
.VINREF (VINREF),
.VOUTREF (VOUTREF),
.REFLEAK_BIAS (REFLEAK_BIAS),
.PAD_A_NOESD_H (PAD_A_NOESD_H[0]),
.VREG_EN (VREG_EN[0]),
.IBUF_SEL (IBUF_SEL[0]),
.HLD_OVR (HLD_OVR[0])
);
endmodule
|
// nios_system.v
// Generated using ACDS version 14.1 186 at 2016.05.03.15:20:12
`timescale 1 ps / 1 ps
module nios_system (
output wire [31:0] alu_a_export, // alu_a.export
output wire [31:0] alu_b_export, // alu_b.export
input wire alu_carry_out_export, // alu_carry_out.export
output wire [2:0] alu_control_export, // alu_control.export
input wire alu_negative_export, // alu_negative.export
input wire [31:0] alu_out_export, // alu_out.export
input wire alu_overflow_export, // alu_overflow.export
input wire alu_zero_export, // alu_zero.export
input wire clk_clk, // clk.clk
output wire [3:0] hex_0_export, // hex_0.export
output wire [3:0] hex_1_export, // hex_1.export
output wire [3:0] hex_2_export, // hex_2.export
output wire [3:0] hex_3_export, // hex_3.export
output wire [3:0] hex_4_export, // hex_4.export
output wire [3:0] hex_5_export, // hex_5.export
input wire [3:0] keys_export, // keys.export
output wire [9:0] leds_export, // leds.export
output wire [31:0] regfile_data_export, // regfile_data.export
output wire [5:0] regfile_r1sel_export, // regfile_r1sel.export
output wire [5:0] regfile_r2sel_export, // regfile_r2sel.export
input wire [31:0] regfile_reg1_export, // regfile_reg1.export
input wire [31:0] regfile_reg2_export, // regfile_reg2.export
output wire regfile_we_export, // regfile_we.export
output wire [5:0] regfile_wsel_export, // regfile_wsel.export
input wire reset_reset_n, // reset.reset_n
output wire [10:0] sram_addr_export, // sram_addr.export
output wire sram_cs_export, // sram_cs.export
inout wire [15:0] sram_data_in_export, // sram_data_in.export
output wire sram_oe_export, // sram_oe.export
output wire sram_read_write_export, // sram_read_write.export
input wire [9:0] switches_export // switches.export
);
wire [31:0] nios2_qsys_0_data_master_readdata; // mm_interconnect_0:nios2_qsys_0_data_master_readdata -> nios2_qsys_0:d_readdata
wire nios2_qsys_0_data_master_waitrequest; // mm_interconnect_0:nios2_qsys_0_data_master_waitrequest -> nios2_qsys_0:d_waitrequest
wire nios2_qsys_0_data_master_debugaccess; // nios2_qsys_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_qsys_0_data_master_debugaccess
wire [18:0] nios2_qsys_0_data_master_address; // nios2_qsys_0:d_address -> mm_interconnect_0:nios2_qsys_0_data_master_address
wire [3:0] nios2_qsys_0_data_master_byteenable; // nios2_qsys_0:d_byteenable -> mm_interconnect_0:nios2_qsys_0_data_master_byteenable
wire nios2_qsys_0_data_master_read; // nios2_qsys_0:d_read -> mm_interconnect_0:nios2_qsys_0_data_master_read
wire nios2_qsys_0_data_master_write; // nios2_qsys_0:d_write -> mm_interconnect_0:nios2_qsys_0_data_master_write
wire [31:0] nios2_qsys_0_data_master_writedata; // nios2_qsys_0:d_writedata -> mm_interconnect_0:nios2_qsys_0_data_master_writedata
wire [31:0] nios2_qsys_0_instruction_master_readdata; // mm_interconnect_0:nios2_qsys_0_instruction_master_readdata -> nios2_qsys_0:i_readdata
wire nios2_qsys_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_qsys_0_instruction_master_waitrequest -> nios2_qsys_0:i_waitrequest
wire [18:0] nios2_qsys_0_instruction_master_address; // nios2_qsys_0:i_address -> mm_interconnect_0:nios2_qsys_0_instruction_master_address
wire nios2_qsys_0_instruction_master_read; // nios2_qsys_0:i_read -> mm_interconnect_0:nios2_qsys_0_instruction_master_read
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata; // jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest; // jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> jtag_uart_0:av_read_n
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> jtag_uart_0:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
wire [31:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata; // nios2_qsys_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_qsys_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest; // nios2_qsys_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_qsys_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_debugaccess -> nios2_qsys_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_address -> nios2_qsys_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_read -> nios2_qsys_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_byteenable -> nios2_qsys_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_write -> nios2_qsys_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_writedata -> nios2_qsys_0:debug_mem_slave_writedata
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [14:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_leds_s1_chipselect; // mm_interconnect_0:LEDs_s1_chipselect -> LEDs:chipselect
wire [31:0] mm_interconnect_0_leds_s1_readdata; // LEDs:readdata -> mm_interconnect_0:LEDs_s1_readdata
wire [1:0] mm_interconnect_0_leds_s1_address; // mm_interconnect_0:LEDs_s1_address -> LEDs:address
wire mm_interconnect_0_leds_s1_write; // mm_interconnect_0:LEDs_s1_write -> LEDs:write_n
wire [31:0] mm_interconnect_0_leds_s1_writedata; // mm_interconnect_0:LEDs_s1_writedata -> LEDs:writedata
wire [31:0] mm_interconnect_0_switches_s1_readdata; // switches:readdata -> mm_interconnect_0:switches_s1_readdata
wire [1:0] mm_interconnect_0_switches_s1_address; // mm_interconnect_0:switches_s1_address -> switches:address
wire mm_interconnect_0_sram_data_s1_chipselect; // mm_interconnect_0:sram_data_s1_chipselect -> sram_data:chipselect
wire [31:0] mm_interconnect_0_sram_data_s1_readdata; // sram_data:readdata -> mm_interconnect_0:sram_data_s1_readdata
wire [1:0] mm_interconnect_0_sram_data_s1_address; // mm_interconnect_0:sram_data_s1_address -> sram_data:address
wire mm_interconnect_0_sram_data_s1_write; // mm_interconnect_0:sram_data_s1_write -> sram_data:write_n
wire [31:0] mm_interconnect_0_sram_data_s1_writedata; // mm_interconnect_0:sram_data_s1_writedata -> sram_data:writedata
wire mm_interconnect_0_sram_addr_s1_chipselect; // mm_interconnect_0:sram_addr_s1_chipselect -> sram_addr:chipselect
wire [31:0] mm_interconnect_0_sram_addr_s1_readdata; // sram_addr:readdata -> mm_interconnect_0:sram_addr_s1_readdata
wire [1:0] mm_interconnect_0_sram_addr_s1_address; // mm_interconnect_0:sram_addr_s1_address -> sram_addr:address
wire mm_interconnect_0_sram_addr_s1_write; // mm_interconnect_0:sram_addr_s1_write -> sram_addr:write_n
wire [31:0] mm_interconnect_0_sram_addr_s1_writedata; // mm_interconnect_0:sram_addr_s1_writedata -> sram_addr:writedata
wire mm_interconnect_0_sram_read_write_s1_chipselect; // mm_interconnect_0:sram_read_write_s1_chipselect -> sram_read_write:chipselect
wire [31:0] mm_interconnect_0_sram_read_write_s1_readdata; // sram_read_write:readdata -> mm_interconnect_0:sram_read_write_s1_readdata
wire [1:0] mm_interconnect_0_sram_read_write_s1_address; // mm_interconnect_0:sram_read_write_s1_address -> sram_read_write:address
wire mm_interconnect_0_sram_read_write_s1_write; // mm_interconnect_0:sram_read_write_s1_write -> sram_read_write:write_n
wire [31:0] mm_interconnect_0_sram_read_write_s1_writedata; // mm_interconnect_0:sram_read_write_s1_writedata -> sram_read_write:writedata
wire mm_interconnect_0_sram_cs_s1_chipselect; // mm_interconnect_0:sram_cs_s1_chipselect -> sram_cs:chipselect
wire [31:0] mm_interconnect_0_sram_cs_s1_readdata; // sram_cs:readdata -> mm_interconnect_0:sram_cs_s1_readdata
wire [1:0] mm_interconnect_0_sram_cs_s1_address; // mm_interconnect_0:sram_cs_s1_address -> sram_cs:address
wire mm_interconnect_0_sram_cs_s1_write; // mm_interconnect_0:sram_cs_s1_write -> sram_cs:write_n
wire [31:0] mm_interconnect_0_sram_cs_s1_writedata; // mm_interconnect_0:sram_cs_s1_writedata -> sram_cs:writedata
wire mm_interconnect_0_sram_oe_s1_chipselect; // mm_interconnect_0:sram_oe_s1_chipselect -> sram_oe:chipselect
wire [31:0] mm_interconnect_0_sram_oe_s1_readdata; // sram_oe:readdata -> mm_interconnect_0:sram_oe_s1_readdata
wire [1:0] mm_interconnect_0_sram_oe_s1_address; // mm_interconnect_0:sram_oe_s1_address -> sram_oe:address
wire mm_interconnect_0_sram_oe_s1_write; // mm_interconnect_0:sram_oe_s1_write -> sram_oe:write_n
wire [31:0] mm_interconnect_0_sram_oe_s1_writedata; // mm_interconnect_0:sram_oe_s1_writedata -> sram_oe:writedata
wire mm_interconnect_0_regfile_data_s1_chipselect; // mm_interconnect_0:regfile_data_s1_chipselect -> regfile_data:chipselect
wire [31:0] mm_interconnect_0_regfile_data_s1_readdata; // regfile_data:readdata -> mm_interconnect_0:regfile_data_s1_readdata
wire [1:0] mm_interconnect_0_regfile_data_s1_address; // mm_interconnect_0:regfile_data_s1_address -> regfile_data:address
wire mm_interconnect_0_regfile_data_s1_write; // mm_interconnect_0:regfile_data_s1_write -> regfile_data:write_n
wire [31:0] mm_interconnect_0_regfile_data_s1_writedata; // mm_interconnect_0:regfile_data_s1_writedata -> regfile_data:writedata
wire [31:0] mm_interconnect_0_regfile_reg1_s1_readdata; // regfile_reg1:readdata -> mm_interconnect_0:regfile_reg1_s1_readdata
wire [1:0] mm_interconnect_0_regfile_reg1_s1_address; // mm_interconnect_0:regfile_reg1_s1_address -> regfile_reg1:address
wire [31:0] mm_interconnect_0_regfile_reg2_s1_readdata; // regfile_reg2:readdata -> mm_interconnect_0:regfile_reg2_s1_readdata
wire [1:0] mm_interconnect_0_regfile_reg2_s1_address; // mm_interconnect_0:regfile_reg2_s1_address -> regfile_reg2:address
wire mm_interconnect_0_regfile_r1sel_s1_chipselect; // mm_interconnect_0:regfile_r1sel_s1_chipselect -> regfile_r1sel:chipselect
wire [31:0] mm_interconnect_0_regfile_r1sel_s1_readdata; // regfile_r1sel:readdata -> mm_interconnect_0:regfile_r1sel_s1_readdata
wire [1:0] mm_interconnect_0_regfile_r1sel_s1_address; // mm_interconnect_0:regfile_r1sel_s1_address -> regfile_r1sel:address
wire mm_interconnect_0_regfile_r1sel_s1_write; // mm_interconnect_0:regfile_r1sel_s1_write -> regfile_r1sel:write_n
wire [31:0] mm_interconnect_0_regfile_r1sel_s1_writedata; // mm_interconnect_0:regfile_r1sel_s1_writedata -> regfile_r1sel:writedata
wire mm_interconnect_0_regfile_r2sel_s1_chipselect; // mm_interconnect_0:regfile_r2sel_s1_chipselect -> regfile_r2sel:chipselect
wire [31:0] mm_interconnect_0_regfile_r2sel_s1_readdata; // regfile_r2sel:readdata -> mm_interconnect_0:regfile_r2sel_s1_readdata
wire [1:0] mm_interconnect_0_regfile_r2sel_s1_address; // mm_interconnect_0:regfile_r2sel_s1_address -> regfile_r2sel:address
wire mm_interconnect_0_regfile_r2sel_s1_write; // mm_interconnect_0:regfile_r2sel_s1_write -> regfile_r2sel:write_n
wire [31:0] mm_interconnect_0_regfile_r2sel_s1_writedata; // mm_interconnect_0:regfile_r2sel_s1_writedata -> regfile_r2sel:writedata
wire mm_interconnect_0_regfile_wsel_s1_chipselect; // mm_interconnect_0:regfile_wsel_s1_chipselect -> regfile_wsel:chipselect
wire [31:0] mm_interconnect_0_regfile_wsel_s1_readdata; // regfile_wsel:readdata -> mm_interconnect_0:regfile_wsel_s1_readdata
wire [1:0] mm_interconnect_0_regfile_wsel_s1_address; // mm_interconnect_0:regfile_wsel_s1_address -> regfile_wsel:address
wire mm_interconnect_0_regfile_wsel_s1_write; // mm_interconnect_0:regfile_wsel_s1_write -> regfile_wsel:write_n
wire [31:0] mm_interconnect_0_regfile_wsel_s1_writedata; // mm_interconnect_0:regfile_wsel_s1_writedata -> regfile_wsel:writedata
wire mm_interconnect_0_regfile_we_s1_chipselect; // mm_interconnect_0:regfile_we_s1_chipselect -> regfile_we:chipselect
wire [31:0] mm_interconnect_0_regfile_we_s1_readdata; // regfile_we:readdata -> mm_interconnect_0:regfile_we_s1_readdata
wire [1:0] mm_interconnect_0_regfile_we_s1_address; // mm_interconnect_0:regfile_we_s1_address -> regfile_we:address
wire mm_interconnect_0_regfile_we_s1_write; // mm_interconnect_0:regfile_we_s1_write -> regfile_we:write_n
wire [31:0] mm_interconnect_0_regfile_we_s1_writedata; // mm_interconnect_0:regfile_we_s1_writedata -> regfile_we:writedata
wire mm_interconnect_0_hex_0_s1_chipselect; // mm_interconnect_0:hex_0_s1_chipselect -> hex_0:chipselect
wire [31:0] mm_interconnect_0_hex_0_s1_readdata; // hex_0:readdata -> mm_interconnect_0:hex_0_s1_readdata
wire [1:0] mm_interconnect_0_hex_0_s1_address; // mm_interconnect_0:hex_0_s1_address -> hex_0:address
wire mm_interconnect_0_hex_0_s1_write; // mm_interconnect_0:hex_0_s1_write -> hex_0:write_n
wire [31:0] mm_interconnect_0_hex_0_s1_writedata; // mm_interconnect_0:hex_0_s1_writedata -> hex_0:writedata
wire mm_interconnect_0_hex_1_s1_chipselect; // mm_interconnect_0:hex_1_s1_chipselect -> hex_1:chipselect
wire [31:0] mm_interconnect_0_hex_1_s1_readdata; // hex_1:readdata -> mm_interconnect_0:hex_1_s1_readdata
wire [1:0] mm_interconnect_0_hex_1_s1_address; // mm_interconnect_0:hex_1_s1_address -> hex_1:address
wire mm_interconnect_0_hex_1_s1_write; // mm_interconnect_0:hex_1_s1_write -> hex_1:write_n
wire [31:0] mm_interconnect_0_hex_1_s1_writedata; // mm_interconnect_0:hex_1_s1_writedata -> hex_1:writedata
wire mm_interconnect_0_hex_2_s1_chipselect; // mm_interconnect_0:hex_2_s1_chipselect -> hex_2:chipselect
wire [31:0] mm_interconnect_0_hex_2_s1_readdata; // hex_2:readdata -> mm_interconnect_0:hex_2_s1_readdata
wire [1:0] mm_interconnect_0_hex_2_s1_address; // mm_interconnect_0:hex_2_s1_address -> hex_2:address
wire mm_interconnect_0_hex_2_s1_write; // mm_interconnect_0:hex_2_s1_write -> hex_2:write_n
wire [31:0] mm_interconnect_0_hex_2_s1_writedata; // mm_interconnect_0:hex_2_s1_writedata -> hex_2:writedata
wire mm_interconnect_0_hex_3_s1_chipselect; // mm_interconnect_0:hex_3_s1_chipselect -> hex_3:chipselect
wire [31:0] mm_interconnect_0_hex_3_s1_readdata; // hex_3:readdata -> mm_interconnect_0:hex_3_s1_readdata
wire [1:0] mm_interconnect_0_hex_3_s1_address; // mm_interconnect_0:hex_3_s1_address -> hex_3:address
wire mm_interconnect_0_hex_3_s1_write; // mm_interconnect_0:hex_3_s1_write -> hex_3:write_n
wire [31:0] mm_interconnect_0_hex_3_s1_writedata; // mm_interconnect_0:hex_3_s1_writedata -> hex_3:writedata
wire mm_interconnect_0_hex_4_s1_chipselect; // mm_interconnect_0:hex_4_s1_chipselect -> hex_4:chipselect
wire [31:0] mm_interconnect_0_hex_4_s1_readdata; // hex_4:readdata -> mm_interconnect_0:hex_4_s1_readdata
wire [1:0] mm_interconnect_0_hex_4_s1_address; // mm_interconnect_0:hex_4_s1_address -> hex_4:address
wire mm_interconnect_0_hex_4_s1_write; // mm_interconnect_0:hex_4_s1_write -> hex_4:write_n
wire [31:0] mm_interconnect_0_hex_4_s1_writedata; // mm_interconnect_0:hex_4_s1_writedata -> hex_4:writedata
wire mm_interconnect_0_hex_5_s1_chipselect; // mm_interconnect_0:hex_5_s1_chipselect -> hex_5:chipselect
wire [31:0] mm_interconnect_0_hex_5_s1_readdata; // hex_5:readdata -> mm_interconnect_0:hex_5_s1_readdata
wire [1:0] mm_interconnect_0_hex_5_s1_address; // mm_interconnect_0:hex_5_s1_address -> hex_5:address
wire mm_interconnect_0_hex_5_s1_write; // mm_interconnect_0:hex_5_s1_write -> hex_5:write_n
wire [31:0] mm_interconnect_0_hex_5_s1_writedata; // mm_interconnect_0:hex_5_s1_writedata -> hex_5:writedata
wire mm_interconnect_0_alu_a_s1_chipselect; // mm_interconnect_0:alu_a_s1_chipselect -> alu_a:chipselect
wire [31:0] mm_interconnect_0_alu_a_s1_readdata; // alu_a:readdata -> mm_interconnect_0:alu_a_s1_readdata
wire [1:0] mm_interconnect_0_alu_a_s1_address; // mm_interconnect_0:alu_a_s1_address -> alu_a:address
wire mm_interconnect_0_alu_a_s1_write; // mm_interconnect_0:alu_a_s1_write -> alu_a:write_n
wire [31:0] mm_interconnect_0_alu_a_s1_writedata; // mm_interconnect_0:alu_a_s1_writedata -> alu_a:writedata
wire mm_interconnect_0_alu_b_s1_chipselect; // mm_interconnect_0:alu_b_s1_chipselect -> alu_b:chipselect
wire [31:0] mm_interconnect_0_alu_b_s1_readdata; // alu_b:readdata -> mm_interconnect_0:alu_b_s1_readdata
wire [1:0] mm_interconnect_0_alu_b_s1_address; // mm_interconnect_0:alu_b_s1_address -> alu_b:address
wire mm_interconnect_0_alu_b_s1_write; // mm_interconnect_0:alu_b_s1_write -> alu_b:write_n
wire [31:0] mm_interconnect_0_alu_b_s1_writedata; // mm_interconnect_0:alu_b_s1_writedata -> alu_b:writedata
wire mm_interconnect_0_alu_control_s1_chipselect; // mm_interconnect_0:alu_control_s1_chipselect -> alu_control:chipselect
wire [31:0] mm_interconnect_0_alu_control_s1_readdata; // alu_control:readdata -> mm_interconnect_0:alu_control_s1_readdata
wire [1:0] mm_interconnect_0_alu_control_s1_address; // mm_interconnect_0:alu_control_s1_address -> alu_control:address
wire mm_interconnect_0_alu_control_s1_write; // mm_interconnect_0:alu_control_s1_write -> alu_control:write_n
wire [31:0] mm_interconnect_0_alu_control_s1_writedata; // mm_interconnect_0:alu_control_s1_writedata -> alu_control:writedata
wire [31:0] mm_interconnect_0_alu_out_s1_readdata; // alu_out:readdata -> mm_interconnect_0:alu_out_s1_readdata
wire [1:0] mm_interconnect_0_alu_out_s1_address; // mm_interconnect_0:alu_out_s1_address -> alu_out:address
wire [31:0] mm_interconnect_0_alu_zero_s1_readdata; // alu_zero:readdata -> mm_interconnect_0:alu_zero_s1_readdata
wire [1:0] mm_interconnect_0_alu_zero_s1_address; // mm_interconnect_0:alu_zero_s1_address -> alu_zero:address
wire [31:0] mm_interconnect_0_alu_overflow_s1_readdata; // alu_overflow:readdata -> mm_interconnect_0:alu_overflow_s1_readdata
wire [1:0] mm_interconnect_0_alu_overflow_s1_address; // mm_interconnect_0:alu_overflow_s1_address -> alu_overflow:address
wire [31:0] mm_interconnect_0_alu_carry_out_s1_readdata; // alu_carry_out:readdata -> mm_interconnect_0:alu_carry_out_s1_readdata
wire [1:0] mm_interconnect_0_alu_carry_out_s1_address; // mm_interconnect_0:alu_carry_out_s1_address -> alu_carry_out:address
wire [31:0] mm_interconnect_0_alu_negative_s1_readdata; // alu_negative:readdata -> mm_interconnect_0:alu_negative_s1_readdata
wire [1:0] mm_interconnect_0_alu_negative_s1_address; // mm_interconnect_0:alu_negative_s1_address -> alu_negative:address
wire [31:0] mm_interconnect_0_keys_s1_readdata; // keys:readdata -> mm_interconnect_0:keys_s1_readdata
wire [1:0] mm_interconnect_0_keys_s1_address; // mm_interconnect_0:keys_s1_address -> keys:address
wire irq_mapper_receiver0_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
wire [31:0] nios2_qsys_0_irq_irq; // irq_mapper:sender_irq -> nios2_qsys_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDs:reset_n, alu_a:reset_n, alu_b:reset_n, alu_carry_out:reset_n, alu_control:reset_n, alu_negative:reset_n, alu_out:reset_n, alu_overflow:reset_n, alu_zero:reset_n, hex_0:reset_n, hex_1:reset_n, hex_2:reset_n, hex_3:reset_n, hex_4:reset_n, hex_5:reset_n, irq_mapper:reset, jtag_uart_0:rst_n, keys:reset_n, mm_interconnect_0:nios2_qsys_0_reset_reset_bridge_in_reset_reset, nios2_qsys_0:reset_n, onchip_memory2_0:reset, regfile_data:reset_n, regfile_r1sel:reset_n, regfile_r2sel:reset_n, regfile_reg1:reset_n, regfile_reg2:reset_n, regfile_we:reset_n, regfile_wsel:reset_n, rst_translator:in_reset, sram_addr:reset_n, sram_cs:reset_n, sram_data:reset_n, sram_oe:reset_n, sram_read_write:reset_n, switches:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [nios2_qsys_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire nios2_qsys_0_debug_reset_request_reset; // nios2_qsys_0:debug_reset_request -> rst_controller:reset_in1
nios_system_LEDs leds (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_leds_s1_address), // s1.address
.write_n (~mm_interconnect_0_leds_s1_write), // .write_n
.writedata (mm_interconnect_0_leds_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_leds_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_leds_s1_readdata), // .readdata
.out_port (leds_export) // external_connection.export
);
nios_system_alu_a alu_a (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_a_s1_address), // s1.address
.write_n (~mm_interconnect_0_alu_a_s1_write), // .write_n
.writedata (mm_interconnect_0_alu_a_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_alu_a_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_alu_a_s1_readdata), // .readdata
.out_port (alu_a_export) // external_connection.export
);
nios_system_alu_a alu_b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_b_s1_address), // s1.address
.write_n (~mm_interconnect_0_alu_b_s1_write), // .write_n
.writedata (mm_interconnect_0_alu_b_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_alu_b_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_alu_b_s1_readdata), // .readdata
.out_port (alu_b_export) // external_connection.export
);
nios_system_alu_carry_out alu_carry_out (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_carry_out_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_carry_out_s1_readdata), // .readdata
.in_port (alu_carry_out_export) // external_connection.export
);
nios_system_alu_control alu_control (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_control_s1_address), // s1.address
.write_n (~mm_interconnect_0_alu_control_s1_write), // .write_n
.writedata (mm_interconnect_0_alu_control_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_alu_control_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_alu_control_s1_readdata), // .readdata
.out_port (alu_control_export) // external_connection.export
);
nios_system_alu_carry_out alu_negative (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_negative_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_negative_s1_readdata), // .readdata
.in_port (alu_negative_export) // external_connection.export
);
nios_system_alu_out alu_out (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_out_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_out_s1_readdata), // .readdata
.in_port (alu_out_export) // external_connection.export
);
nios_system_alu_carry_out alu_overflow (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_overflow_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_overflow_s1_readdata), // .readdata
.in_port (alu_overflow_export) // external_connection.export
);
nios_system_alu_carry_out alu_zero (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_zero_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_zero_s1_readdata), // .readdata
.in_port (alu_zero_export) // external_connection.export
);
nios_system_hex_0 hex_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_0_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_0_s1_readdata), // .readdata
.out_port (hex_0_export) // external_connection.export
);
nios_system_hex_0 hex_1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_1_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_1_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_1_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_1_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_1_s1_readdata), // .readdata
.out_port (hex_1_export) // external_connection.export
);
nios_system_hex_0 hex_2 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_2_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_2_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_2_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_2_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_2_s1_readdata), // .readdata
.out_port (hex_2_export) // external_connection.export
);
nios_system_hex_0 hex_3 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_3_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_3_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_3_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_3_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_3_s1_readdata), // .readdata
.out_port (hex_3_export) // external_connection.export
);
nios_system_hex_0 hex_4 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_4_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_4_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_4_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_4_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_4_s1_readdata), // .readdata
.out_port (hex_4_export) // external_connection.export
);
nios_system_hex_0 hex_5 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_5_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_5_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_5_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_5_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_5_s1_readdata), // .readdata
.out_port (hex_5_export) // external_connection.export
);
nios_system_jtag_uart_0 jtag_uart_0 (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
nios_system_keys keys (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_keys_s1_address), // s1.address
.readdata (mm_interconnect_0_keys_s1_readdata), // .readdata
.in_port (keys_export) // external_connection.export
);
nios_system_nios2_qsys_0 nios2_qsys_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (nios2_qsys_0_data_master_address), // data_master.address
.d_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.d_read (nios2_qsys_0_data_master_read), // .read
.d_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_qsys_0_data_master_write), // .write
.d_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_qsys_0_instruction_master_address), // instruction_master.address
.i_read (nios2_qsys_0_instruction_master_read), // .read
.i_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.irq (nios2_qsys_0_irq_irq), // irq.irq
.debug_reset_request (nios2_qsys_0_debug_reset_request_reset), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
nios_system_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
nios_system_alu_a regfile_data (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_data_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_data_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_data_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_data_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_data_s1_readdata), // .readdata
.out_port (regfile_data_export) // external_connection.export
);
nios_system_regfile_r1sel regfile_r1sel (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_r1sel_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_r1sel_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_r1sel_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_r1sel_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_r1sel_s1_readdata), // .readdata
.out_port (regfile_r1sel_export) // external_connection.export
);
nios_system_regfile_r1sel regfile_r2sel (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_r2sel_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_r2sel_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_r2sel_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_r2sel_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_r2sel_s1_readdata), // .readdata
.out_port (regfile_r2sel_export) // external_connection.export
);
nios_system_alu_out regfile_reg1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_reg1_s1_address), // s1.address
.readdata (mm_interconnect_0_regfile_reg1_s1_readdata), // .readdata
.in_port (regfile_reg1_export) // external_connection.export
);
nios_system_alu_out regfile_reg2 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_reg2_s1_address), // s1.address
.readdata (mm_interconnect_0_regfile_reg2_s1_readdata), // .readdata
.in_port (regfile_reg2_export) // external_connection.export
);
nios_system_regfile_we regfile_we (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_we_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_we_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_we_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_we_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_we_s1_readdata), // .readdata
.out_port (regfile_we_export) // external_connection.export
);
nios_system_regfile_r1sel regfile_wsel (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_wsel_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_wsel_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_wsel_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_wsel_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_wsel_s1_readdata), // .readdata
.out_port (regfile_wsel_export) // external_connection.export
);
nios_system_sram_addr sram_addr (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_addr_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_addr_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_addr_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_addr_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_addr_s1_readdata), // .readdata
.out_port (sram_addr_export) // external_connection.export
);
nios_system_regfile_we sram_cs (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_cs_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_cs_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_cs_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_cs_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_cs_s1_readdata), // .readdata
.out_port (sram_cs_export) // external_connection.export
);
nios_system_sram_data sram_data (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_data_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_data_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_data_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_data_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_data_s1_readdata), // .readdata
.bidir_port (sram_data_in_export) // external_connection.export
);
nios_system_regfile_we sram_oe (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_oe_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_oe_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_oe_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_oe_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_oe_s1_readdata), // .readdata
.out_port (sram_oe_export) // external_connection.export
);
nios_system_regfile_we sram_read_write (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_read_write_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_read_write_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_read_write_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_read_write_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_read_write_s1_readdata), // .readdata
.out_port (sram_read_write_export) // external_connection.export
);
nios_system_switches switches (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_switches_s1_address), // s1.address
.readdata (mm_interconnect_0_switches_s1_readdata), // .readdata
.in_port (switches_export) // external_connection.export
);
nios_system_mm_interconnect_0 mm_interconnect_0 (
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.nios2_qsys_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_qsys_0_reset_reset_bridge_in_reset.reset
.nios2_qsys_0_data_master_address (nios2_qsys_0_data_master_address), // nios2_qsys_0_data_master.address
.nios2_qsys_0_data_master_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.nios2_qsys_0_data_master_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.nios2_qsys_0_data_master_read (nios2_qsys_0_data_master_read), // .read
.nios2_qsys_0_data_master_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.nios2_qsys_0_data_master_write (nios2_qsys_0_data_master_write), // .write
.nios2_qsys_0_data_master_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.nios2_qsys_0_data_master_debugaccess (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.nios2_qsys_0_instruction_master_address (nios2_qsys_0_instruction_master_address), // nios2_qsys_0_instruction_master.address
.nios2_qsys_0_instruction_master_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.nios2_qsys_0_instruction_master_read (nios2_qsys_0_instruction_master_read), // .read
.nios2_qsys_0_instruction_master_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.alu_a_s1_address (mm_interconnect_0_alu_a_s1_address), // alu_a_s1.address
.alu_a_s1_write (mm_interconnect_0_alu_a_s1_write), // .write
.alu_a_s1_readdata (mm_interconnect_0_alu_a_s1_readdata), // .readdata
.alu_a_s1_writedata (mm_interconnect_0_alu_a_s1_writedata), // .writedata
.alu_a_s1_chipselect (mm_interconnect_0_alu_a_s1_chipselect), // .chipselect
.alu_b_s1_address (mm_interconnect_0_alu_b_s1_address), // alu_b_s1.address
.alu_b_s1_write (mm_interconnect_0_alu_b_s1_write), // .write
.alu_b_s1_readdata (mm_interconnect_0_alu_b_s1_readdata), // .readdata
.alu_b_s1_writedata (mm_interconnect_0_alu_b_s1_writedata), // .writedata
.alu_b_s1_chipselect (mm_interconnect_0_alu_b_s1_chipselect), // .chipselect
.alu_carry_out_s1_address (mm_interconnect_0_alu_carry_out_s1_address), // alu_carry_out_s1.address
.alu_carry_out_s1_readdata (mm_interconnect_0_alu_carry_out_s1_readdata), // .readdata
.alu_control_s1_address (mm_interconnect_0_alu_control_s1_address), // alu_control_s1.address
.alu_control_s1_write (mm_interconnect_0_alu_control_s1_write), // .write
.alu_control_s1_readdata (mm_interconnect_0_alu_control_s1_readdata), // .readdata
.alu_control_s1_writedata (mm_interconnect_0_alu_control_s1_writedata), // .writedata
.alu_control_s1_chipselect (mm_interconnect_0_alu_control_s1_chipselect), // .chipselect
.alu_negative_s1_address (mm_interconnect_0_alu_negative_s1_address), // alu_negative_s1.address
.alu_negative_s1_readdata (mm_interconnect_0_alu_negative_s1_readdata), // .readdata
.alu_out_s1_address (mm_interconnect_0_alu_out_s1_address), // alu_out_s1.address
.alu_out_s1_readdata (mm_interconnect_0_alu_out_s1_readdata), // .readdata
.alu_overflow_s1_address (mm_interconnect_0_alu_overflow_s1_address), // alu_overflow_s1.address
.alu_overflow_s1_readdata (mm_interconnect_0_alu_overflow_s1_readdata), // .readdata
.alu_zero_s1_address (mm_interconnect_0_alu_zero_s1_address), // alu_zero_s1.address
.alu_zero_s1_readdata (mm_interconnect_0_alu_zero_s1_readdata), // .readdata
.hex_0_s1_address (mm_interconnect_0_hex_0_s1_address), // hex_0_s1.address
.hex_0_s1_write (mm_interconnect_0_hex_0_s1_write), // .write
.hex_0_s1_readdata (mm_interconnect_0_hex_0_s1_readdata), // .readdata
.hex_0_s1_writedata (mm_interconnect_0_hex_0_s1_writedata), // .writedata
.hex_0_s1_chipselect (mm_interconnect_0_hex_0_s1_chipselect), // .chipselect
.hex_1_s1_address (mm_interconnect_0_hex_1_s1_address), // hex_1_s1.address
.hex_1_s1_write (mm_interconnect_0_hex_1_s1_write), // .write
.hex_1_s1_readdata (mm_interconnect_0_hex_1_s1_readdata), // .readdata
.hex_1_s1_writedata (mm_interconnect_0_hex_1_s1_writedata), // .writedata
.hex_1_s1_chipselect (mm_interconnect_0_hex_1_s1_chipselect), // .chipselect
.hex_2_s1_address (mm_interconnect_0_hex_2_s1_address), // hex_2_s1.address
.hex_2_s1_write (mm_interconnect_0_hex_2_s1_write), // .write
.hex_2_s1_readdata (mm_interconnect_0_hex_2_s1_readdata), // .readdata
.hex_2_s1_writedata (mm_interconnect_0_hex_2_s1_writedata), // .writedata
.hex_2_s1_chipselect (mm_interconnect_0_hex_2_s1_chipselect), // .chipselect
.hex_3_s1_address (mm_interconnect_0_hex_3_s1_address), // hex_3_s1.address
.hex_3_s1_write (mm_interconnect_0_hex_3_s1_write), // .write
.hex_3_s1_readdata (mm_interconnect_0_hex_3_s1_readdata), // .readdata
.hex_3_s1_writedata (mm_interconnect_0_hex_3_s1_writedata), // .writedata
.hex_3_s1_chipselect (mm_interconnect_0_hex_3_s1_chipselect), // .chipselect
.hex_4_s1_address (mm_interconnect_0_hex_4_s1_address), // hex_4_s1.address
.hex_4_s1_write (mm_interconnect_0_hex_4_s1_write), // .write
.hex_4_s1_readdata (mm_interconnect_0_hex_4_s1_readdata), // .readdata
.hex_4_s1_writedata (mm_interconnect_0_hex_4_s1_writedata), // .writedata
.hex_4_s1_chipselect (mm_interconnect_0_hex_4_s1_chipselect), // .chipselect
.hex_5_s1_address (mm_interconnect_0_hex_5_s1_address), // hex_5_s1.address
.hex_5_s1_write (mm_interconnect_0_hex_5_s1_write), // .write
.hex_5_s1_readdata (mm_interconnect_0_hex_5_s1_readdata), // .readdata
.hex_5_s1_writedata (mm_interconnect_0_hex_5_s1_writedata), // .writedata
.hex_5_s1_chipselect (mm_interconnect_0_hex_5_s1_chipselect), // .chipselect
.jtag_uart_0_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // jtag_uart_0_avalon_jtag_slave.address
.jtag_uart_0_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write
.jtag_uart_0_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read
.jtag_uart_0_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_0_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_0_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.keys_s1_address (mm_interconnect_0_keys_s1_address), // keys_s1.address
.keys_s1_readdata (mm_interconnect_0_keys_s1_readdata), // .readdata
.LEDs_s1_address (mm_interconnect_0_leds_s1_address), // LEDs_s1.address
.LEDs_s1_write (mm_interconnect_0_leds_s1_write), // .write
.LEDs_s1_readdata (mm_interconnect_0_leds_s1_readdata), // .readdata
.LEDs_s1_writedata (mm_interconnect_0_leds_s1_writedata), // .writedata
.LEDs_s1_chipselect (mm_interconnect_0_leds_s1_chipselect), // .chipselect
.nios2_qsys_0_debug_mem_slave_address (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address), // nios2_qsys_0_debug_mem_slave.address
.nios2_qsys_0_debug_mem_slave_write (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write), // .write
.nios2_qsys_0_debug_mem_slave_read (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read), // .read
.nios2_qsys_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata), // .readdata
.nios2_qsys_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata), // .writedata
.nios2_qsys_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable), // .byteenable
.nios2_qsys_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_qsys_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess), // .debugaccess
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.regfile_data_s1_address (mm_interconnect_0_regfile_data_s1_address), // regfile_data_s1.address
.regfile_data_s1_write (mm_interconnect_0_regfile_data_s1_write), // .write
.regfile_data_s1_readdata (mm_interconnect_0_regfile_data_s1_readdata), // .readdata
.regfile_data_s1_writedata (mm_interconnect_0_regfile_data_s1_writedata), // .writedata
.regfile_data_s1_chipselect (mm_interconnect_0_regfile_data_s1_chipselect), // .chipselect
.regfile_r1sel_s1_address (mm_interconnect_0_regfile_r1sel_s1_address), // regfile_r1sel_s1.address
.regfile_r1sel_s1_write (mm_interconnect_0_regfile_r1sel_s1_write), // .write
.regfile_r1sel_s1_readdata (mm_interconnect_0_regfile_r1sel_s1_readdata), // .readdata
.regfile_r1sel_s1_writedata (mm_interconnect_0_regfile_r1sel_s1_writedata), // .writedata
.regfile_r1sel_s1_chipselect (mm_interconnect_0_regfile_r1sel_s1_chipselect), // .chipselect
.regfile_r2sel_s1_address (mm_interconnect_0_regfile_r2sel_s1_address), // regfile_r2sel_s1.address
.regfile_r2sel_s1_write (mm_interconnect_0_regfile_r2sel_s1_write), // .write
.regfile_r2sel_s1_readdata (mm_interconnect_0_regfile_r2sel_s1_readdata), // .readdata
.regfile_r2sel_s1_writedata (mm_interconnect_0_regfile_r2sel_s1_writedata), // .writedata
.regfile_r2sel_s1_chipselect (mm_interconnect_0_regfile_r2sel_s1_chipselect), // .chipselect
.regfile_reg1_s1_address (mm_interconnect_0_regfile_reg1_s1_address), // regfile_reg1_s1.address
.regfile_reg1_s1_readdata (mm_interconnect_0_regfile_reg1_s1_readdata), // .readdata
.regfile_reg2_s1_address (mm_interconnect_0_regfile_reg2_s1_address), // regfile_reg2_s1.address
.regfile_reg2_s1_readdata (mm_interconnect_0_regfile_reg2_s1_readdata), // .readdata
.regfile_we_s1_address (mm_interconnect_0_regfile_we_s1_address), // regfile_we_s1.address
.regfile_we_s1_write (mm_interconnect_0_regfile_we_s1_write), // .write
.regfile_we_s1_readdata (mm_interconnect_0_regfile_we_s1_readdata), // .readdata
.regfile_we_s1_writedata (mm_interconnect_0_regfile_we_s1_writedata), // .writedata
.regfile_we_s1_chipselect (mm_interconnect_0_regfile_we_s1_chipselect), // .chipselect
.regfile_wsel_s1_address (mm_interconnect_0_regfile_wsel_s1_address), // regfile_wsel_s1.address
.regfile_wsel_s1_write (mm_interconnect_0_regfile_wsel_s1_write), // .write
.regfile_wsel_s1_readdata (mm_interconnect_0_regfile_wsel_s1_readdata), // .readdata
.regfile_wsel_s1_writedata (mm_interconnect_0_regfile_wsel_s1_writedata), // .writedata
.regfile_wsel_s1_chipselect (mm_interconnect_0_regfile_wsel_s1_chipselect), // .chipselect
.sram_addr_s1_address (mm_interconnect_0_sram_addr_s1_address), // sram_addr_s1.address
.sram_addr_s1_write (mm_interconnect_0_sram_addr_s1_write), // .write
.sram_addr_s1_readdata (mm_interconnect_0_sram_addr_s1_readdata), // .readdata
.sram_addr_s1_writedata (mm_interconnect_0_sram_addr_s1_writedata), // .writedata
.sram_addr_s1_chipselect (mm_interconnect_0_sram_addr_s1_chipselect), // .chipselect
.sram_cs_s1_address (mm_interconnect_0_sram_cs_s1_address), // sram_cs_s1.address
.sram_cs_s1_write (mm_interconnect_0_sram_cs_s1_write), // .write
.sram_cs_s1_readdata (mm_interconnect_0_sram_cs_s1_readdata), // .readdata
.sram_cs_s1_writedata (mm_interconnect_0_sram_cs_s1_writedata), // .writedata
.sram_cs_s1_chipselect (mm_interconnect_0_sram_cs_s1_chipselect), // .chipselect
.sram_data_s1_address (mm_interconnect_0_sram_data_s1_address), // sram_data_s1.address
.sram_data_s1_write (mm_interconnect_0_sram_data_s1_write), // .write
.sram_data_s1_readdata (mm_interconnect_0_sram_data_s1_readdata), // .readdata
.sram_data_s1_writedata (mm_interconnect_0_sram_data_s1_writedata), // .writedata
.sram_data_s1_chipselect (mm_interconnect_0_sram_data_s1_chipselect), // .chipselect
.sram_oe_s1_address (mm_interconnect_0_sram_oe_s1_address), // sram_oe_s1.address
.sram_oe_s1_write (mm_interconnect_0_sram_oe_s1_write), // .write
.sram_oe_s1_readdata (mm_interconnect_0_sram_oe_s1_readdata), // .readdata
.sram_oe_s1_writedata (mm_interconnect_0_sram_oe_s1_writedata), // .writedata
.sram_oe_s1_chipselect (mm_interconnect_0_sram_oe_s1_chipselect), // .chipselect
.sram_read_write_s1_address (mm_interconnect_0_sram_read_write_s1_address), // sram_read_write_s1.address
.sram_read_write_s1_write (mm_interconnect_0_sram_read_write_s1_write), // .write
.sram_read_write_s1_readdata (mm_interconnect_0_sram_read_write_s1_readdata), // .readdata
.sram_read_write_s1_writedata (mm_interconnect_0_sram_read_write_s1_writedata), // .writedata
.sram_read_write_s1_chipselect (mm_interconnect_0_sram_read_write_s1_chipselect), // .chipselect
.switches_s1_address (mm_interconnect_0_switches_s1_address), // switches_s1.address
.switches_s1_readdata (mm_interconnect_0_switches_s1_readdata) // .readdata
);
nios_system_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (nios2_qsys_0_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (nios2_qsys_0_debug_reset_request_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4x4 crosspoint
*/
module axis_crosspoint_4x4 #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI Stream inputs
*/
input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire input_0_axis_tvalid,
input wire input_0_axis_tlast,
input wire input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire input_1_axis_tvalid,
input wire input_1_axis_tlast,
input wire input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire input_2_axis_tvalid,
input wire input_2_axis_tlast,
input wire input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire input_3_axis_tvalid,
input wire input_3_axis_tlast,
input wire input_3_axis_tuser,
/*
* AXI Stream outputs
*/
output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
output wire output_0_axis_tvalid,
output wire output_0_axis_tlast,
output wire output_0_axis_tuser,
output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
output wire output_1_axis_tvalid,
output wire output_1_axis_tlast,
output wire output_1_axis_tuser,
output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
output wire output_2_axis_tvalid,
output wire output_2_axis_tlast,
output wire output_2_axis_tuser,
output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
output wire output_3_axis_tvalid,
output wire output_3_axis_tlast,
output wire output_3_axis_tuser,
/*
* Control
*/
input wire [1:0] output_0_select,
input wire [1:0] output_1_select,
input wire [1:0] output_2_select,
input wire [1:0] output_3_select
);
reg [DATA_WIDTH-1:0] input_0_axis_tdata_reg = 0;
reg input_0_axis_tvalid_reg = 0;
reg input_0_axis_tlast_reg = 0;
reg input_0_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata_reg = 0;
reg input_1_axis_tvalid_reg = 0;
reg input_1_axis_tlast_reg = 0;
reg input_1_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata_reg = 0;
reg input_2_axis_tvalid_reg = 0;
reg input_2_axis_tlast_reg = 0;
reg input_2_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata_reg = 0;
reg input_3_axis_tvalid_reg = 0;
reg input_3_axis_tlast_reg = 0;
reg input_3_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] output_0_axis_tdata_reg = 0;
reg output_0_axis_tvalid_reg = 0;
reg output_0_axis_tlast_reg = 0;
reg output_0_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] output_1_axis_tdata_reg = 0;
reg output_1_axis_tvalid_reg = 0;
reg output_1_axis_tlast_reg = 0;
reg output_1_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] output_2_axis_tdata_reg = 0;
reg output_2_axis_tvalid_reg = 0;
reg output_2_axis_tlast_reg = 0;
reg output_2_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] output_3_axis_tdata_reg = 0;
reg output_3_axis_tvalid_reg = 0;
reg output_3_axis_tlast_reg = 0;
reg output_3_axis_tuser_reg = 0;
reg [1:0] output_0_select_reg = 0;
reg [1:0] output_1_select_reg = 0;
reg [1:0] output_2_select_reg = 0;
reg [1:0] output_3_select_reg = 0;
assign output_0_axis_tdata = output_0_axis_tdata_reg;
assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
assign output_0_axis_tlast = output_0_axis_tlast_reg;
assign output_0_axis_tuser = output_0_axis_tuser_reg;
assign output_1_axis_tdata = output_1_axis_tdata_reg;
assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
assign output_1_axis_tlast = output_1_axis_tlast_reg;
assign output_1_axis_tuser = output_1_axis_tuser_reg;
assign output_2_axis_tdata = output_2_axis_tdata_reg;
assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
assign output_2_axis_tlast = output_2_axis_tlast_reg;
assign output_2_axis_tuser = output_2_axis_tuser_reg;
assign output_3_axis_tdata = output_3_axis_tdata_reg;
assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
assign output_3_axis_tlast = output_3_axis_tlast_reg;
assign output_3_axis_tuser = output_3_axis_tuser_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
output_0_select_reg <= 0;
output_1_select_reg <= 0;
output_2_select_reg <= 0;
output_3_select_reg <= 0;
input_0_axis_tdata_reg <= 0;
input_0_axis_tvalid_reg <= 0;
input_0_axis_tlast_reg <= 0;
input_0_axis_tuser_reg <= 0;
input_1_axis_tdata_reg <= 0;
input_1_axis_tvalid_reg <= 0;
input_1_axis_tlast_reg <= 0;
input_1_axis_tuser_reg <= 0;
input_2_axis_tdata_reg <= 0;
input_2_axis_tvalid_reg <= 0;
input_2_axis_tlast_reg <= 0;
input_2_axis_tuser_reg <= 0;
input_3_axis_tdata_reg <= 0;
input_3_axis_tvalid_reg <= 0;
input_3_axis_tlast_reg <= 0;
input_3_axis_tuser_reg <= 0;
output_0_axis_tdata_reg <= 0;
output_0_axis_tvalid_reg <= 0;
output_0_axis_tlast_reg <= 0;
output_0_axis_tuser_reg <= 0;
output_1_axis_tdata_reg <= 0;
output_1_axis_tvalid_reg <= 0;
output_1_axis_tlast_reg <= 0;
output_1_axis_tuser_reg <= 0;
output_2_axis_tdata_reg <= 0;
output_2_axis_tvalid_reg <= 0;
output_2_axis_tlast_reg <= 0;
output_2_axis_tuser_reg <= 0;
output_3_axis_tdata_reg <= 0;
output_3_axis_tvalid_reg <= 0;
output_3_axis_tlast_reg <= 0;
output_3_axis_tuser_reg <= 0;
end else begin
input_0_axis_tdata_reg <= input_0_axis_tdata;
input_0_axis_tvalid_reg <= input_0_axis_tvalid;
input_0_axis_tlast_reg <= input_0_axis_tlast;
input_0_axis_tuser_reg <= input_0_axis_tuser;
input_1_axis_tdata_reg <= input_1_axis_tdata;
input_1_axis_tvalid_reg <= input_1_axis_tvalid;
input_1_axis_tlast_reg <= input_1_axis_tlast;
input_1_axis_tuser_reg <= input_1_axis_tuser;
input_2_axis_tdata_reg <= input_2_axis_tdata;
input_2_axis_tvalid_reg <= input_2_axis_tvalid;
input_2_axis_tlast_reg <= input_2_axis_tlast;
input_2_axis_tuser_reg <= input_2_axis_tuser;
input_3_axis_tdata_reg <= input_3_axis_tdata;
input_3_axis_tvalid_reg <= input_3_axis_tvalid;
input_3_axis_tlast_reg <= input_3_axis_tlast;
input_3_axis_tuser_reg <= input_3_axis_tuser;
output_0_select_reg <= output_0_select;
output_1_select_reg <= output_1_select;
output_2_select_reg <= output_2_select;
output_3_select_reg <= output_3_select;
case (output_0_select_reg)
2'd0: begin
output_0_axis_tdata_reg <= input_0_axis_tdata_reg;
output_0_axis_tvalid_reg <= input_0_axis_tvalid_reg;
output_0_axis_tlast_reg <= input_0_axis_tlast_reg;
output_0_axis_tuser_reg <= input_0_axis_tuser_reg;
end
2'd1: begin
output_0_axis_tdata_reg <= input_1_axis_tdata_reg;
output_0_axis_tvalid_reg <= input_1_axis_tvalid_reg;
output_0_axis_tlast_reg <= input_1_axis_tlast_reg;
output_0_axis_tuser_reg <= input_1_axis_tuser_reg;
end
2'd2: begin
output_0_axis_tdata_reg <= input_2_axis_tdata_reg;
output_0_axis_tvalid_reg <= input_2_axis_tvalid_reg;
output_0_axis_tlast_reg <= input_2_axis_tlast_reg;
output_0_axis_tuser_reg <= input_2_axis_tuser_reg;
end
2'd3: begin
output_0_axis_tdata_reg <= input_3_axis_tdata_reg;
output_0_axis_tvalid_reg <= input_3_axis_tvalid_reg;
output_0_axis_tlast_reg <= input_3_axis_tlast_reg;
output_0_axis_tuser_reg <= input_3_axis_tuser_reg;
end
endcase
case (output_1_select_reg)
2'd0: begin
output_1_axis_tdata_reg <= input_0_axis_tdata_reg;
output_1_axis_tvalid_reg <= input_0_axis_tvalid_reg;
output_1_axis_tlast_reg <= input_0_axis_tlast_reg;
output_1_axis_tuser_reg <= input_0_axis_tuser_reg;
end
2'd1: begin
output_1_axis_tdata_reg <= input_1_axis_tdata_reg;
output_1_axis_tvalid_reg <= input_1_axis_tvalid_reg;
output_1_axis_tlast_reg <= input_1_axis_tlast_reg;
output_1_axis_tuser_reg <= input_1_axis_tuser_reg;
end
2'd2: begin
output_1_axis_tdata_reg <= input_2_axis_tdata_reg;
output_1_axis_tvalid_reg <= input_2_axis_tvalid_reg;
output_1_axis_tlast_reg <= input_2_axis_tlast_reg;
output_1_axis_tuser_reg <= input_2_axis_tuser_reg;
end
2'd3: begin
output_1_axis_tdata_reg <= input_3_axis_tdata_reg;
output_1_axis_tvalid_reg <= input_3_axis_tvalid_reg;
output_1_axis_tlast_reg <= input_3_axis_tlast_reg;
output_1_axis_tuser_reg <= input_3_axis_tuser_reg;
end
endcase
case (output_2_select_reg)
2'd0: begin
output_2_axis_tdata_reg <= input_0_axis_tdata_reg;
output_2_axis_tvalid_reg <= input_0_axis_tvalid_reg;
output_2_axis_tlast_reg <= input_0_axis_tlast_reg;
output_2_axis_tuser_reg <= input_0_axis_tuser_reg;
end
2'd1: begin
output_2_axis_tdata_reg <= input_1_axis_tdata_reg;
output_2_axis_tvalid_reg <= input_1_axis_tvalid_reg;
output_2_axis_tlast_reg <= input_1_axis_tlast_reg;
output_2_axis_tuser_reg <= input_1_axis_tuser_reg;
end
2'd2: begin
output_2_axis_tdata_reg <= input_2_axis_tdata_reg;
output_2_axis_tvalid_reg <= input_2_axis_tvalid_reg;
output_2_axis_tlast_reg <= input_2_axis_tlast_reg;
output_2_axis_tuser_reg <= input_2_axis_tuser_reg;
end
2'd3: begin
output_2_axis_tdata_reg <= input_3_axis_tdata_reg;
output_2_axis_tvalid_reg <= input_3_axis_tvalid_reg;
output_2_axis_tlast_reg <= input_3_axis_tlast_reg;
output_2_axis_tuser_reg <= input_3_axis_tuser_reg;
end
endcase
case (output_3_select_reg)
2'd0: begin
output_3_axis_tdata_reg <= input_0_axis_tdata_reg;
output_3_axis_tvalid_reg <= input_0_axis_tvalid_reg;
output_3_axis_tlast_reg <= input_0_axis_tlast_reg;
output_3_axis_tuser_reg <= input_0_axis_tuser_reg;
end
2'd1: begin
output_3_axis_tdata_reg <= input_1_axis_tdata_reg;
output_3_axis_tvalid_reg <= input_1_axis_tvalid_reg;
output_3_axis_tlast_reg <= input_1_axis_tlast_reg;
output_3_axis_tuser_reg <= input_1_axis_tuser_reg;
end
2'd2: begin
output_3_axis_tdata_reg <= input_2_axis_tdata_reg;
output_3_axis_tvalid_reg <= input_2_axis_tvalid_reg;
output_3_axis_tlast_reg <= input_2_axis_tlast_reg;
output_3_axis_tuser_reg <= input_2_axis_tuser_reg;
end
2'd3: begin
output_3_axis_tdata_reg <= input_3_axis_tdata_reg;
output_3_axis_tvalid_reg <= input_3_axis_tvalid_reg;
output_3_axis_tlast_reg <= input_3_axis_tlast_reg;
output_3_axis_tuser_reg <= input_3_axis_tuser_reg;
end
endcase
end
end
endmodule
|
/*
GPR Bank
Reads from Rs, Rt, and Rm.
Writes to Rn.
*/
module RegGPR(
/* verilator lint_off UNUSED */
clock, reset,
regIdRs, regValRs,
regIdRt, regValRt,
regIdRm, regValRm,
regIdRn, regValRn,
regSrVal);
input clock;
input reset;
input[6:0] regIdRs;
input[6:0] regIdRt;
input[6:0] regIdRm;
input[6:0] regIdRn;
output[31:0] regValRs;
output[31:0] regValRt;
output[31:0] regValRm;
input[31:0] regValRn;
input[31:0] regSrVal;
reg regSrRB;
reg[31:0] tRegValRs;
reg[31:0] tRegValRt;
reg[31:0] tRegValRm;
reg[31:0] regGprLA[7:0];
reg[31:0] regGprLB[7:0];
reg[31:0] regGprH[7:0];
assign regValRs = tRegValRs;
assign regValRt = tRegValRt;
assign regValRm = tRegValRm;
always @ (clock)
begin
tRegValRs=0;
tRegValRt=0;
tRegValRm=0;
regSrRB=regSrVal[29];
if(regIdRs[6:3]==4'h0)
begin
tRegValRs=regSrRB?
regGprLB[regIdRs[2:0]]:
regGprLA[regIdRs[2:0]];
end
else if(regIdRs[6:3]==4'h1)
begin
tRegValRs=regGprH[regIdRs[2:0]];
end
else if(regIdRs[6:3]==4'h4)
begin
tRegValRs=regSrRB?
regGprLB[regIdRs[2:0]]:
regGprLA[regIdRs[2:0]];
end
if(regIdRt[6:3]==4'h0)
begin
tRegValRt=regSrRB?
regGprLB[regIdRt[2:0]]:
regGprLA[regIdRt[2:0]];
end
else if(regIdRt[6:3]==4'h1)
begin
tRegValRt=regGprH[regIdRt[2:0]];
end
else if(regIdRt[6:3]==4'h4)
begin
tRegValRt=regSrRB?
regGprLB[regIdRt[2:0]]:
regGprLA[regIdRt[2:0]];
end
if(regIdRm[6:3]==4'h0)
begin
tRegValRm=regSrRB?
regGprLB[regIdRm[2:0]]:
regGprLA[regIdRm[2:0]];
end
else if(regIdRm[6:3]==4'h1)
begin
tRegValRm=regGprH[regIdRm[2:0]];
end
else if(regIdRm[6:3]==4'h4)
begin
tRegValRm=regSrRB?
regGprLB[regIdRm[2:0]]:
regGprLA[regIdRm[2:0]];
end
end
always @ (posedge clock)
begin
if(regIdRn[6:3]==4'h0)
begin
if(regSrRB)
regGprLB[regIdRn[2:0]] <= regValRn;
else
regGprLA[regIdRn[2:0]] <= regValRn;
end
else if(regIdRn[6:3]==4'h1)
begin
regGprH[regIdRn[2:0]] <= regValRn;
end
else if(regIdRn[6:3]==4'h4)
begin
if(regSrRB)
regGprLA[regIdRn[2:0]] <= regValRn;
else
regGprLB[regIdRn[2:0]] <= regValRn;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 15:11:11 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W64_EW11_SW52 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [63:0] Data_MX;
input [63:0] Data_MY;
input [1:0] round_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, n286, n287, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370,
n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381,
n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414,
n415, n416, n417, n418, n419, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551,
n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562,
n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573,
n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584,
n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595,
n596, n597, n598, n599, n600, n601, n602, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n618, n619,
n620, n622, n623, n624, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n695, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, DP_OP_36J35_134_7156_n28,
DP_OP_36J35_134_7156_n27, DP_OP_36J35_134_7156_n26,
DP_OP_36J35_134_7156_n25, DP_OP_36J35_134_7156_n24,
DP_OP_36J35_134_7156_n23, DP_OP_36J35_134_7156_n22,
DP_OP_36J35_134_7156_n21, DP_OP_36J35_134_7156_n20,
DP_OP_36J35_134_7156_n19, DP_OP_36J35_134_7156_n18,
DP_OP_36J35_134_7156_n12, DP_OP_36J35_134_7156_n11,
DP_OP_36J35_134_7156_n10, DP_OP_36J35_134_7156_n9,
DP_OP_36J35_134_7156_n8, DP_OP_36J35_134_7156_n7,
DP_OP_36J35_134_7156_n6, DP_OP_36J35_134_7156_n5,
DP_OP_36J35_134_7156_n4, DP_OP_36J35_134_7156_n3,
DP_OP_36J35_134_7156_n2, DP_OP_36J35_134_7156_n1,
DP_OP_347J35_131_5122_n456, DP_OP_347J35_131_5122_n455,
DP_OP_347J35_131_5122_n449, DP_OP_347J35_131_5122_n448,
DP_OP_347J35_131_5122_n447, DP_OP_347J35_131_5122_n446,
DP_OP_347J35_131_5122_n445, DP_OP_347J35_131_5122_n442,
DP_OP_347J35_131_5122_n441, DP_OP_347J35_131_5122_n440,
DP_OP_347J35_131_5122_n439, DP_OP_347J35_131_5122_n438,
DP_OP_347J35_131_5122_n436, DP_OP_347J35_131_5122_n435,
DP_OP_347J35_131_5122_n434, DP_OP_347J35_131_5122_n422,
DP_OP_347J35_131_5122_n419, DP_OP_347J35_131_5122_n418,
DP_OP_347J35_131_5122_n417, DP_OP_347J35_131_5122_n416,
DP_OP_347J35_131_5122_n415, DP_OP_347J35_131_5122_n414,
DP_OP_347J35_131_5122_n413, DP_OP_347J35_131_5122_n412,
DP_OP_347J35_131_5122_n411, DP_OP_347J35_131_5122_n410,
DP_OP_347J35_131_5122_n409, DP_OP_347J35_131_5122_n408,
DP_OP_347J35_131_5122_n407, DP_OP_347J35_131_5122_n406,
DP_OP_347J35_131_5122_n405, DP_OP_347J35_131_5122_n404,
DP_OP_347J35_131_5122_n403, DP_OP_347J35_131_5122_n402,
DP_OP_347J35_131_5122_n401, DP_OP_347J35_131_5122_n311,
DP_OP_347J35_131_5122_n310, DP_OP_347J35_131_5122_n304,
DP_OP_347J35_131_5122_n303, DP_OP_347J35_131_5122_n302,
DP_OP_347J35_131_5122_n301, DP_OP_347J35_131_5122_n300,
DP_OP_347J35_131_5122_n297, DP_OP_347J35_131_5122_n296,
DP_OP_347J35_131_5122_n295, DP_OP_347J35_131_5122_n294,
DP_OP_347J35_131_5122_n293, DP_OP_347J35_131_5122_n291,
DP_OP_347J35_131_5122_n290, DP_OP_347J35_131_5122_n289,
DP_OP_347J35_131_5122_n277, DP_OP_347J35_131_5122_n274,
DP_OP_347J35_131_5122_n273, DP_OP_347J35_131_5122_n272,
DP_OP_347J35_131_5122_n271, DP_OP_347J35_131_5122_n270,
DP_OP_347J35_131_5122_n269, DP_OP_347J35_131_5122_n268,
DP_OP_347J35_131_5122_n267, DP_OP_347J35_131_5122_n266,
DP_OP_347J35_131_5122_n265, DP_OP_347J35_131_5122_n264,
DP_OP_347J35_131_5122_n263, DP_OP_347J35_131_5122_n262,
DP_OP_347J35_131_5122_n261, DP_OP_347J35_131_5122_n260,
DP_OP_347J35_131_5122_n259, DP_OP_347J35_131_5122_n258,
DP_OP_347J35_131_5122_n257, DP_OP_347J35_131_5122_n256,
DP_OP_347J35_131_5122_n234, DP_OP_347J35_131_5122_n233,
DP_OP_347J35_131_5122_n232, DP_OP_347J35_131_5122_n231,
DP_OP_347J35_131_5122_n230, DP_OP_347J35_131_5122_n229,
DP_OP_347J35_131_5122_n228, DP_OP_347J35_131_5122_n227,
DP_OP_347J35_131_5122_n226, DP_OP_347J35_131_5122_n225,
DP_OP_347J35_131_5122_n224, DP_OP_347J35_131_5122_n223,
DP_OP_347J35_131_5122_n201, DP_OP_347J35_131_5122_n200,
DP_OP_347J35_131_5122_n199, DP_OP_347J35_131_5122_n198,
DP_OP_347J35_131_5122_n192, DP_OP_347J35_131_5122_n191,
DP_OP_347J35_131_5122_n189, DP_OP_347J35_131_5122_n183,
DP_OP_347J35_131_5122_n180, DP_OP_347J35_131_5122_n175,
DP_OP_347J35_131_5122_n174, DP_OP_347J35_131_5122_n173,
DP_OP_347J35_131_5122_n171, DP_OP_347J35_131_5122_n167,
DP_OP_347J35_131_5122_n165, DP_OP_347J35_131_5122_n164,
DP_OP_347J35_131_5122_n160, DP_OP_347J35_131_5122_n158,
DP_OP_347J35_131_5122_n157, DP_OP_347J35_131_5122_n156,
DP_OP_347J35_131_5122_n155, DP_OP_347J35_131_5122_n154,
DP_OP_347J35_131_5122_n153, DP_OP_347J35_131_5122_n151,
DP_OP_347J35_131_5122_n149, DP_OP_347J35_131_5122_n148,
DP_OP_347J35_131_5122_n147, DP_OP_347J35_131_5122_n146,
DP_OP_347J35_131_5122_n145, DP_OP_347J35_131_5122_n144,
DP_OP_347J35_131_5122_n134, DP_OP_347J35_131_5122_n133,
DP_OP_347J35_131_5122_n132, DP_OP_347J35_131_5122_n131,
DP_OP_347J35_131_5122_n130, DP_OP_347J35_131_5122_n129,
DP_OP_347J35_131_5122_n128, DP_OP_347J35_131_5122_n126,
DP_OP_347J35_131_5122_n123, DP_OP_347J35_131_5122_n122,
DP_OP_347J35_131_5122_n121, DP_OP_347J35_131_5122_n120,
DP_OP_347J35_131_5122_n119, DP_OP_347J35_131_5122_n118,
DP_OP_347J35_131_5122_n117, DP_OP_347J35_131_5122_n116,
DP_OP_347J35_131_5122_n115, DP_OP_347J35_131_5122_n114,
DP_OP_347J35_131_5122_n113, DP_OP_347J35_131_5122_n111,
DP_OP_347J35_131_5122_n110, DP_OP_347J35_131_5122_n109,
DP_OP_347J35_131_5122_n108, DP_OP_347J35_131_5122_n107,
DP_OP_347J35_131_5122_n106, DP_OP_347J35_131_5122_n105,
DP_OP_347J35_131_5122_n104, DP_OP_347J35_131_5122_n103,
DP_OP_347J35_131_5122_n102, DP_OP_347J35_131_5122_n101,
DP_OP_347J35_131_5122_n100, DP_OP_347J35_131_5122_n99,
DP_OP_347J35_131_5122_n98, DP_OP_347J35_131_5122_n97,
DP_OP_347J35_131_5122_n96, DP_OP_347J35_131_5122_n95,
DP_OP_347J35_131_5122_n93, DP_OP_347J35_131_5122_n92,
DP_OP_347J35_131_5122_n91, DP_OP_347J35_131_5122_n90,
DP_OP_347J35_131_5122_n89, DP_OP_347J35_131_5122_n88,
DP_OP_347J35_131_5122_n87, DP_OP_347J35_131_5122_n86,
DP_OP_347J35_131_5122_n85, DP_OP_347J35_131_5122_n84,
DP_OP_347J35_131_5122_n82, DP_OP_347J35_131_5122_n81,
DP_OP_347J35_131_5122_n80, DP_OP_347J35_131_5122_n79,
DP_OP_347J35_131_5122_n78, DP_OP_347J35_131_5122_n77,
DP_OP_347J35_131_5122_n76, DP_OP_347J35_131_5122_n75,
DP_OP_347J35_131_5122_n74, DP_OP_347J35_131_5122_n73,
DP_OP_347J35_131_5122_n72, DP_OP_347J35_131_5122_n71,
DP_OP_347J35_131_5122_n70, DP_OP_347J35_131_5122_n69,
DP_OP_347J35_131_5122_n68, DP_OP_347J35_131_5122_n67,
DP_OP_347J35_131_5122_n66, DP_OP_347J35_131_5122_n65,
DP_OP_347J35_131_5122_n64, DP_OP_347J35_131_5122_n63,
DP_OP_347J35_131_5122_n62, DP_OP_347J35_131_5122_n61,
DP_OP_347J35_131_5122_n60, DP_OP_347J35_131_5122_n59,
DP_OP_347J35_131_5122_n58, DP_OP_347J35_131_5122_n57,
DP_OP_347J35_131_5122_n56, DP_OP_347J35_131_5122_n55,
DP_OP_347J35_131_5122_n54, DP_OP_347J35_131_5122_n53,
DP_OP_347J35_131_5122_n52, DP_OP_347J35_131_5122_n51,
DP_OP_347J35_131_5122_n50, DP_OP_347J35_131_5122_n49,
DP_OP_347J35_131_5122_n48, DP_OP_347J35_131_5122_n47,
DP_OP_347J35_131_5122_n46, DP_OP_347J35_131_5122_n45,
DP_OP_347J35_131_5122_n44, DP_OP_347J35_131_5122_n43,
DP_OP_347J35_131_5122_n42, DP_OP_347J35_131_5122_n41,
DP_OP_347J35_131_5122_n40, DP_OP_347J35_131_5122_n39,
DP_OP_347J35_131_5122_n38, DP_OP_347J35_131_5122_n37,
DP_OP_347J35_131_5122_n36, DP_OP_347J35_131_5122_n35,
DP_OP_347J35_131_5122_n34, DP_OP_347J35_131_5122_n33,
DP_OP_347J35_131_5122_n32, DP_OP_347J35_131_5122_n31,
DP_OP_347J35_131_5122_n30, DP_OP_347J35_131_5122_n29,
DP_OP_347J35_131_5122_n28, DP_OP_347J35_131_5122_n27,
DP_OP_347J35_131_5122_n26, DP_OP_347J35_131_5122_n25,
DP_OP_347J35_131_5122_n24, DP_OP_347J35_131_5122_n22,
DP_OP_347J35_131_5122_n21, DP_OP_347J35_131_5122_n20,
DP_OP_338J35_122_4684_n1465, DP_OP_338J35_122_4684_n1464,
DP_OP_338J35_122_4684_n1463, DP_OP_338J35_122_4684_n1462,
DP_OP_338J35_122_4684_n1461, DP_OP_338J35_122_4684_n1460,
DP_OP_338J35_122_4684_n1459, DP_OP_338J35_122_4684_n1458,
DP_OP_338J35_122_4684_n1457, DP_OP_338J35_122_4684_n1456,
DP_OP_338J35_122_4684_n1455, DP_OP_338J35_122_4684_n1454,
DP_OP_338J35_122_4684_n1453, DP_OP_338J35_122_4684_n1452,
DP_OP_338J35_122_4684_n1451, DP_OP_338J35_122_4684_n1450,
DP_OP_338J35_122_4684_n1449, DP_OP_338J35_122_4684_n1308,
DP_OP_338J35_122_4684_n1307, DP_OP_338J35_122_4684_n1306,
DP_OP_338J35_122_4684_n1305, DP_OP_338J35_122_4684_n1304,
DP_OP_338J35_122_4684_n1303, DP_OP_338J35_122_4684_n1302,
DP_OP_338J35_122_4684_n1301, DP_OP_338J35_122_4684_n1300,
DP_OP_338J35_122_4684_n1299, DP_OP_338J35_122_4684_n1298,
DP_OP_338J35_122_4684_n1297, DP_OP_338J35_122_4684_n1295,
DP_OP_338J35_122_4684_n1294, DP_OP_338J35_122_4684_n1293,
DP_OP_338J35_122_4684_n1292, DP_OP_338J35_122_4684_n1291,
DP_OP_338J35_122_4684_n1290, DP_OP_338J35_122_4684_n1289,
DP_OP_338J35_122_4684_n1288, DP_OP_338J35_122_4684_n1286,
DP_OP_338J35_122_4684_n116, DP_OP_338J35_122_4684_n97,
DP_OP_338J35_122_4684_n96, DP_OP_338J35_122_4684_n79,
DP_OP_338J35_122_4684_n78, DP_OP_338J35_122_4684_n63,
DP_OP_338J35_122_4684_n62, DP_OP_338J35_122_4684_n51,
DP_OP_338J35_122_4684_n50, DP_OP_338J35_122_4684_n41,
DP_OP_338J35_122_4684_n40, DP_OP_338J35_122_4684_n35,
DP_OP_338J35_122_4684_n34, DP_OP_338J35_122_4684_n33,
DP_OP_338J35_122_4684_n32, DP_OP_338J35_122_4684_n20,
DP_OP_338J35_122_4684_n19, DP_OP_338J35_122_4684_n18,
DP_OP_338J35_122_4684_n17, DP_OP_338J35_122_4684_n16,
DP_OP_338J35_122_4684_n15, DP_OP_338J35_122_4684_n14,
DP_OP_338J35_122_4684_n13, DP_OP_338J35_122_4684_n12,
DP_OP_338J35_122_4684_n11, DP_OP_338J35_122_4684_n10,
DP_OP_338J35_122_4684_n9, DP_OP_338J35_122_4684_n8,
DP_OP_338J35_122_4684_n7, DP_OP_338J35_122_4684_n6,
DP_OP_338J35_122_4684_n5, DP_OP_338J35_122_4684_n4,
DP_OP_338J35_122_4684_n3, DP_OP_338J35_122_4684_n2,
DP_OP_345J35_129_3436_n116, DP_OP_345J35_129_3436_n97,
DP_OP_345J35_129_3436_n96, DP_OP_345J35_129_3436_n79,
DP_OP_345J35_129_3436_n78, DP_OP_345J35_129_3436_n63,
DP_OP_345J35_129_3436_n62, DP_OP_345J35_129_3436_n51,
DP_OP_345J35_129_3436_n50, DP_OP_345J35_129_3436_n41,
DP_OP_345J35_129_3436_n40, DP_OP_345J35_129_3436_n35,
DP_OP_345J35_129_3436_n34, DP_OP_345J35_129_3436_n33,
DP_OP_345J35_129_3436_n32, DP_OP_345J35_129_3436_n20,
DP_OP_345J35_129_3436_n19, DP_OP_345J35_129_3436_n18,
DP_OP_345J35_129_3436_n17, DP_OP_345J35_129_3436_n16,
DP_OP_345J35_129_3436_n15, DP_OP_345J35_129_3436_n14,
DP_OP_345J35_129_3436_n13, DP_OP_345J35_129_3436_n12,
DP_OP_345J35_129_3436_n11, DP_OP_345J35_129_3436_n10,
DP_OP_345J35_129_3436_n9, DP_OP_345J35_129_3436_n8,
DP_OP_345J35_129_3436_n7, DP_OP_345J35_129_3436_n6,
DP_OP_345J35_129_3436_n5, DP_OP_345J35_129_3436_n4,
DP_OP_345J35_129_3436_n3, DP_OP_345J35_129_3436_n2, add_x_87_n21,
add_x_87_n20, add_x_87_n19, add_x_87_n18, add_x_87_n17, add_x_87_n16,
add_x_87_n15, add_x_87_n14, add_x_87_n13, add_x_87_n12, add_x_87_n11,
add_x_87_n10, add_x_87_n9, add_x_87_n8, add_x_87_n7, add_x_87_n6,
add_x_87_n5, add_x_87_n4, add_x_87_n2, add_x_87_n1,
DP_OP_343J35_127_4270_n857, DP_OP_343J35_127_4270_n853,
DP_OP_346J35_130_4270_n836, DP_OP_346J35_130_4270_n829,
DP_OP_342J35_126_4270_n853, DP_OP_342J35_126_4270_n852,
DP_OP_342J35_126_4270_n774, DP_OP_342J35_126_4270_n772,
DP_OP_342J35_126_4270_n748, DP_OP_342J35_126_4270_n409,
DP_OP_342J35_126_4270_n408, DP_OP_342J35_126_4270_n406,
DP_OP_342J35_126_4270_n404, DP_OP_342J35_126_4270_n402,
DP_OP_342J35_126_4270_n398, DP_OP_342J35_126_4270_n391,
DP_OP_342J35_126_4270_n390, DP_OP_342J35_126_4270_n349,
DP_OP_342J35_126_4270_n348, DP_OP_342J35_126_4270_n347,
DP_OP_342J35_126_4270_n346, DP_OP_342J35_126_4270_n345,
DP_OP_342J35_126_4270_n344, DP_OP_342J35_126_4270_n343,
DP_OP_342J35_126_4270_n342, DP_OP_342J35_126_4270_n341,
DP_OP_342J35_126_4270_n340, DP_OP_342J35_126_4270_n339,
DP_OP_342J35_126_4270_n338, DP_OP_342J35_126_4270_n337,
DP_OP_342J35_126_4270_n336, DP_OP_342J35_126_4270_n335,
DP_OP_342J35_126_4270_n334, DP_OP_342J35_126_4270_n332,
DP_OP_342J35_126_4270_n331, DP_OP_342J35_126_4270_n330,
DP_OP_342J35_126_4270_n329, DP_OP_342J35_126_4270_n328,
DP_OP_342J35_126_4270_n327, DP_OP_342J35_126_4270_n326,
DP_OP_342J35_126_4270_n325, DP_OP_342J35_126_4270_n324,
DP_OP_342J35_126_4270_n323, DP_OP_342J35_126_4270_n322,
DP_OP_342J35_126_4270_n321, DP_OP_342J35_126_4270_n320,
DP_OP_342J35_126_4270_n319, DP_OP_342J35_126_4270_n318,
DP_OP_342J35_126_4270_n314, DP_OP_342J35_126_4270_n313,
DP_OP_342J35_126_4270_n312, DP_OP_342J35_126_4270_n311,
DP_OP_342J35_126_4270_n310, DP_OP_342J35_126_4270_n309,
DP_OP_342J35_126_4270_n307, DP_OP_342J35_126_4270_n306,
DP_OP_342J35_126_4270_n305, DP_OP_342J35_126_4270_n304,
DP_OP_342J35_126_4270_n303, DP_OP_342J35_126_4270_n302,
DP_OP_342J35_126_4270_n301, DP_OP_342J35_126_4270_n300,
DP_OP_342J35_126_4270_n295, DP_OP_342J35_126_4270_n294,
DP_OP_342J35_126_4270_n293, DP_OP_342J35_126_4270_n292,
DP_OP_342J35_126_4270_n289, DP_OP_342J35_126_4270_n288,
DP_OP_342J35_126_4270_n287, DP_OP_342J35_126_4270_n286,
DP_OP_342J35_126_4270_n284, DP_OP_342J35_126_4270_n283,
DP_OP_342J35_126_4270_n282, DP_OP_342J35_126_4270_n281,
DP_OP_342J35_126_4270_n280, DP_OP_342J35_126_4270_n279,
DP_OP_342J35_126_4270_n278, DP_OP_342J35_126_4270_n277,
DP_OP_342J35_126_4270_n276, DP_OP_342J35_126_4270_n275,
DP_OP_342J35_126_4270_n274, DP_OP_342J35_126_4270_n273,
DP_OP_342J35_126_4270_n272, DP_OP_342J35_126_4270_n271,
DP_OP_342J35_126_4270_n270, DP_OP_342J35_126_4270_n269,
DP_OP_342J35_126_4270_n268, DP_OP_342J35_126_4270_n265,
DP_OP_342J35_126_4270_n264, DP_OP_342J35_126_4270_n263,
DP_OP_342J35_126_4270_n262, DP_OP_342J35_126_4270_n261,
DP_OP_342J35_126_4270_n260, DP_OP_342J35_126_4270_n259,
DP_OP_342J35_126_4270_n258, DP_OP_342J35_126_4270_n257,
DP_OP_342J35_126_4270_n256, DP_OP_342J35_126_4270_n255,
DP_OP_342J35_126_4270_n254, DP_OP_342J35_126_4270_n253,
DP_OP_342J35_126_4270_n252, DP_OP_342J35_126_4270_n251,
DP_OP_342J35_126_4270_n250, DP_OP_342J35_126_4270_n249,
DP_OP_342J35_126_4270_n248, DP_OP_342J35_126_4270_n247,
DP_OP_342J35_126_4270_n246, DP_OP_342J35_126_4270_n244,
DP_OP_342J35_126_4270_n243, DP_OP_342J35_126_4270_n242,
DP_OP_342J35_126_4270_n241, DP_OP_342J35_126_4270_n240,
DP_OP_342J35_126_4270_n239, DP_OP_342J35_126_4270_n238,
DP_OP_342J35_126_4270_n237, DP_OP_342J35_126_4270_n236,
DP_OP_342J35_126_4270_n234, DP_OP_342J35_126_4270_n233,
DP_OP_342J35_126_4270_n232, DP_OP_342J35_126_4270_n231,
DP_OP_342J35_126_4270_n230, DP_OP_342J35_126_4270_n229,
DP_OP_342J35_126_4270_n228, DP_OP_342J35_126_4270_n227,
DP_OP_342J35_126_4270_n226, DP_OP_342J35_126_4270_n225,
DP_OP_342J35_126_4270_n224, DP_OP_342J35_126_4270_n223,
DP_OP_342J35_126_4270_n222, DP_OP_342J35_126_4270_n221,
DP_OP_342J35_126_4270_n220, DP_OP_342J35_126_4270_n219,
DP_OP_342J35_126_4270_n218, DP_OP_342J35_126_4270_n217,
DP_OP_342J35_126_4270_n216, DP_OP_342J35_126_4270_n215,
DP_OP_342J35_126_4270_n214, DP_OP_342J35_126_4270_n213,
DP_OP_342J35_126_4270_n212, DP_OP_342J35_126_4270_n211,
DP_OP_342J35_126_4270_n210, DP_OP_342J35_126_4270_n209,
DP_OP_342J35_126_4270_n208, DP_OP_342J35_126_4270_n207,
DP_OP_342J35_126_4270_n206, DP_OP_342J35_126_4270_n205,
DP_OP_342J35_126_4270_n204, DP_OP_342J35_126_4270_n203,
DP_OP_342J35_126_4270_n202, DP_OP_342J35_126_4270_n201,
DP_OP_342J35_126_4270_n200, DP_OP_342J35_126_4270_n199,
DP_OP_342J35_126_4270_n198, DP_OP_342J35_126_4270_n197,
DP_OP_342J35_126_4270_n196, DP_OP_342J35_126_4270_n195,
DP_OP_342J35_126_4270_n194, DP_OP_342J35_126_4270_n193,
DP_OP_342J35_126_4270_n192, DP_OP_342J35_126_4270_n191,
DP_OP_342J35_126_4270_n190, DP_OP_342J35_126_4270_n189,
DP_OP_342J35_126_4270_n188, DP_OP_342J35_126_4270_n187,
DP_OP_342J35_126_4270_n186, DP_OP_342J35_126_4270_n185,
DP_OP_342J35_126_4270_n184, DP_OP_342J35_126_4270_n183,
DP_OP_342J35_126_4270_n182, DP_OP_342J35_126_4270_n181,
DP_OP_342J35_126_4270_n180, DP_OP_342J35_126_4270_n179,
DP_OP_342J35_126_4270_n178, DP_OP_342J35_126_4270_n177,
DP_OP_342J35_126_4270_n176, DP_OP_342J35_126_4270_n175,
DP_OP_342J35_126_4270_n174, DP_OP_342J35_126_4270_n173,
DP_OP_342J35_126_4270_n172, DP_OP_342J35_126_4270_n171,
DP_OP_342J35_126_4270_n170, DP_OP_342J35_126_4270_n169,
DP_OP_342J35_126_4270_n168, DP_OP_342J35_126_4270_n167,
DP_OP_342J35_126_4270_n166, DP_OP_342J35_126_4270_n165,
DP_OP_342J35_126_4270_n164, DP_OP_342J35_126_4270_n163,
DP_OP_342J35_126_4270_n162, DP_OP_342J35_126_4270_n161,
DP_OP_342J35_126_4270_n160, DP_OP_342J35_126_4270_n159,
DP_OP_342J35_126_4270_n158, DP_OP_342J35_126_4270_n157,
DP_OP_342J35_126_4270_n156, DP_OP_342J35_126_4270_n155,
DP_OP_342J35_126_4270_n154, DP_OP_342J35_126_4270_n153,
DP_OP_342J35_126_4270_n152, DP_OP_342J35_126_4270_n151,
DP_OP_342J35_126_4270_n150, DP_OP_342J35_126_4270_n149,
DP_OP_342J35_126_4270_n148, DP_OP_342J35_126_4270_n147,
DP_OP_342J35_126_4270_n146, DP_OP_342J35_126_4270_n145,
DP_OP_342J35_126_4270_n144, DP_OP_342J35_126_4270_n142,
DP_OP_342J35_126_4270_n141, DP_OP_342J35_126_4270_n140,
DP_OP_342J35_126_4270_n139, DP_OP_342J35_126_4270_n138,
DP_OP_342J35_126_4270_n137, DP_OP_342J35_126_4270_n136,
DP_OP_342J35_126_4270_n135, DP_OP_342J35_126_4270_n132,
DP_OP_342J35_126_4270_n130, DP_OP_342J35_126_4270_n129,
DP_OP_342J35_126_4270_n128, DP_OP_344J35_128_4078_n160,
DP_OP_344J35_128_4078_n159, DP_OP_344J35_128_4078_n158,
DP_OP_344J35_128_4078_n157, DP_OP_344J35_128_4078_n156,
DP_OP_344J35_128_4078_n155, DP_OP_344J35_128_4078_n154,
DP_OP_344J35_128_4078_n150, DP_OP_344J35_128_4078_n149,
DP_OP_344J35_128_4078_n148, DP_OP_344J35_128_4078_n147,
DP_OP_344J35_128_4078_n146, DP_OP_344J35_128_4078_n129,
DP_OP_344J35_128_4078_n128, DP_OP_344J35_128_4078_n127,
DP_OP_344J35_128_4078_n126, DP_OP_344J35_128_4078_n125,
DP_OP_344J35_128_4078_n124, DP_OP_344J35_128_4078_n123,
DP_OP_344J35_128_4078_n122, DP_OP_344J35_128_4078_n121,
DP_OP_344J35_128_4078_n120, DP_OP_344J35_128_4078_n116,
DP_OP_344J35_128_4078_n114, DP_OP_344J35_128_4078_n112,
DP_OP_344J35_128_4078_n110, DP_OP_344J35_128_4078_n108,
DP_OP_344J35_128_4078_n103, DP_OP_344J35_128_4078_n101,
DP_OP_344J35_128_4078_n100, DP_OP_344J35_128_4078_n99,
DP_OP_344J35_128_4078_n98, DP_OP_344J35_128_4078_n97,
DP_OP_344J35_128_4078_n96, DP_OP_344J35_128_4078_n95,
DP_OP_344J35_128_4078_n94, DP_OP_344J35_128_4078_n93,
DP_OP_344J35_128_4078_n92, DP_OP_344J35_128_4078_n91,
DP_OP_344J35_128_4078_n90, DP_OP_344J35_128_4078_n89,
DP_OP_344J35_128_4078_n88, DP_OP_344J35_128_4078_n87,
DP_OP_344J35_128_4078_n86, DP_OP_344J35_128_4078_n85,
DP_OP_344J35_128_4078_n84, DP_OP_344J35_128_4078_n83,
DP_OP_344J35_128_4078_n82, DP_OP_344J35_128_4078_n81,
DP_OP_344J35_128_4078_n80, DP_OP_344J35_128_4078_n79,
DP_OP_344J35_128_4078_n78, DP_OP_344J35_128_4078_n77,
DP_OP_344J35_128_4078_n76, DP_OP_344J35_128_4078_n75,
DP_OP_344J35_128_4078_n74, DP_OP_344J35_128_4078_n73,
DP_OP_344J35_128_4078_n72, DP_OP_344J35_128_4078_n71,
DP_OP_344J35_128_4078_n70, DP_OP_344J35_128_4078_n69,
DP_OP_344J35_128_4078_n68, DP_OP_344J35_128_4078_n67,
DP_OP_344J35_128_4078_n66, DP_OP_344J35_128_4078_n65,
DP_OP_344J35_128_4078_n64, DP_OP_344J35_128_4078_n63,
DP_OP_344J35_128_4078_n62, DP_OP_344J35_128_4078_n61,
DP_OP_344J35_128_4078_n60, DP_OP_344J35_128_4078_n59,
DP_OP_344J35_128_4078_n58, DP_OP_344J35_128_4078_n57,
DP_OP_344J35_128_4078_n56, DP_OP_344J35_128_4078_n53,
DP_OP_344J35_128_4078_n52, DP_OP_344J35_128_4078_n49,
DP_OP_344J35_128_4078_n48, DP_OP_344J35_128_4078_n45,
DP_OP_344J35_128_4078_n44, DP_OP_344J35_128_4078_n43,
DP_OP_344J35_128_4078_n41, DP_OP_344J35_128_4078_n40,
DP_OP_344J35_128_4078_n39, DP_OP_344J35_128_4078_n38,
DP_OP_344J35_128_4078_n37, DP_OP_344J35_128_4078_n36,
DP_OP_344J35_128_4078_n35, DP_OP_344J35_128_4078_n34,
DP_OP_344J35_128_4078_n33, DP_OP_344J35_128_4078_n32,
DP_OP_344J35_128_4078_n31, DP_OP_344J35_128_4078_n30,
DP_OP_344J35_128_4078_n29, DP_OP_344J35_128_4078_n12,
DP_OP_344J35_128_4078_n11, DP_OP_344J35_128_4078_n10,
DP_OP_344J35_128_4078_n9, DP_OP_344J35_128_4078_n8,
DP_OP_344J35_128_4078_n7, DP_OP_344J35_128_4078_n6,
DP_OP_344J35_128_4078_n5, DP_OP_344J35_128_4078_n4,
DP_OP_344J35_128_4078_n3, DP_OP_344J35_128_4078_n2,
DP_OP_344J35_128_4078_n1, DP_OP_341J35_125_6458_n468,
DP_OP_341J35_125_6458_n467, DP_OP_341J35_125_6458_n466,
DP_OP_341J35_125_6458_n461, DP_OP_341J35_125_6458_n460,
DP_OP_341J35_125_6458_n459, DP_OP_341J35_125_6458_n458,
DP_OP_341J35_125_6458_n457, DP_OP_341J35_125_6458_n454,
DP_OP_341J35_125_6458_n453, DP_OP_341J35_125_6458_n452,
DP_OP_341J35_125_6458_n451, DP_OP_341J35_125_6458_n450,
DP_OP_341J35_125_6458_n448, DP_OP_341J35_125_6458_n447,
DP_OP_341J35_125_6458_n446, DP_OP_341J35_125_6458_n434,
DP_OP_341J35_125_6458_n431, DP_OP_341J35_125_6458_n430,
DP_OP_341J35_125_6458_n429, DP_OP_341J35_125_6458_n428,
DP_OP_341J35_125_6458_n427, DP_OP_341J35_125_6458_n426,
DP_OP_341J35_125_6458_n425, DP_OP_341J35_125_6458_n424,
DP_OP_341J35_125_6458_n423, DP_OP_341J35_125_6458_n422,
DP_OP_341J35_125_6458_n421, DP_OP_341J35_125_6458_n420,
DP_OP_341J35_125_6458_n419, DP_OP_341J35_125_6458_n418,
DP_OP_341J35_125_6458_n417, DP_OP_341J35_125_6458_n416,
DP_OP_341J35_125_6458_n415, DP_OP_341J35_125_6458_n414,
DP_OP_341J35_125_6458_n413, DP_OP_341J35_125_6458_n311,
DP_OP_341J35_125_6458_n310, DP_OP_341J35_125_6458_n305,
DP_OP_341J35_125_6458_n304, DP_OP_341J35_125_6458_n303,
DP_OP_341J35_125_6458_n302, DP_OP_341J35_125_6458_n301,
DP_OP_341J35_125_6458_n298, DP_OP_341J35_125_6458_n297,
DP_OP_341J35_125_6458_n296, DP_OP_341J35_125_6458_n295,
DP_OP_341J35_125_6458_n294, DP_OP_341J35_125_6458_n291,
DP_OP_341J35_125_6458_n290, DP_OP_341J35_125_6458_n289,
DP_OP_341J35_125_6458_n288, DP_OP_341J35_125_6458_n287,
DP_OP_341J35_125_6458_n276, DP_OP_341J35_125_6458_n273,
DP_OP_341J35_125_6458_n272, DP_OP_341J35_125_6458_n271,
DP_OP_341J35_125_6458_n270, DP_OP_341J35_125_6458_n269,
DP_OP_341J35_125_6458_n268, DP_OP_341J35_125_6458_n267,
DP_OP_341J35_125_6458_n266, DP_OP_341J35_125_6458_n265,
DP_OP_341J35_125_6458_n264, DP_OP_341J35_125_6458_n262,
DP_OP_341J35_125_6458_n261, DP_OP_341J35_125_6458_n260,
DP_OP_341J35_125_6458_n259, DP_OP_341J35_125_6458_n258,
DP_OP_341J35_125_6458_n257, DP_OP_341J35_125_6458_n256,
DP_OP_341J35_125_6458_n234, DP_OP_341J35_125_6458_n203,
DP_OP_341J35_125_6458_n201, DP_OP_341J35_125_6458_n200,
DP_OP_341J35_125_6458_n199, DP_OP_341J35_125_6458_n198,
DP_OP_341J35_125_6458_n194, DP_OP_341J35_125_6458_n193,
DP_OP_341J35_125_6458_n192, DP_OP_341J35_125_6458_n191,
DP_OP_341J35_125_6458_n190, DP_OP_341J35_125_6458_n189,
DP_OP_341J35_125_6458_n185, DP_OP_341J35_125_6458_n184,
DP_OP_341J35_125_6458_n183, DP_OP_341J35_125_6458_n182,
DP_OP_341J35_125_6458_n181, DP_OP_341J35_125_6458_n180,
DP_OP_341J35_125_6458_n176, DP_OP_341J35_125_6458_n175,
DP_OP_341J35_125_6458_n174, DP_OP_341J35_125_6458_n173,
DP_OP_341J35_125_6458_n172, DP_OP_341J35_125_6458_n171,
DP_OP_341J35_125_6458_n168, DP_OP_341J35_125_6458_n167,
DP_OP_341J35_125_6458_n165, DP_OP_341J35_125_6458_n164,
DP_OP_341J35_125_6458_n163, DP_OP_341J35_125_6458_n160,
DP_OP_341J35_125_6458_n159, DP_OP_341J35_125_6458_n158,
DP_OP_341J35_125_6458_n157, DP_OP_341J35_125_6458_n156,
DP_OP_341J35_125_6458_n155, DP_OP_341J35_125_6458_n154,
DP_OP_341J35_125_6458_n153, DP_OP_341J35_125_6458_n152,
DP_OP_341J35_125_6458_n151, DP_OP_341J35_125_6458_n149,
DP_OP_341J35_125_6458_n148, DP_OP_341J35_125_6458_n147,
DP_OP_341J35_125_6458_n146, DP_OP_341J35_125_6458_n144,
DP_OP_341J35_125_6458_n131, DP_OP_341J35_125_6458_n129,
DP_OP_341J35_125_6458_n126, DP_OP_341J35_125_6458_n125,
DP_OP_341J35_125_6458_n123, DP_OP_341J35_125_6458_n122,
DP_OP_341J35_125_6458_n121, DP_OP_341J35_125_6458_n120,
DP_OP_341J35_125_6458_n119, DP_OP_341J35_125_6458_n118,
DP_OP_341J35_125_6458_n117, DP_OP_341J35_125_6458_n116,
DP_OP_341J35_125_6458_n115, DP_OP_341J35_125_6458_n114,
DP_OP_341J35_125_6458_n113, DP_OP_341J35_125_6458_n111,
DP_OP_341J35_125_6458_n110, DP_OP_341J35_125_6458_n109,
DP_OP_341J35_125_6458_n108, DP_OP_341J35_125_6458_n107,
DP_OP_341J35_125_6458_n106, DP_OP_341J35_125_6458_n105,
DP_OP_341J35_125_6458_n104, DP_OP_341J35_125_6458_n103,
DP_OP_341J35_125_6458_n102, DP_OP_341J35_125_6458_n101,
DP_OP_341J35_125_6458_n100, DP_OP_341J35_125_6458_n99,
DP_OP_341J35_125_6458_n98, DP_OP_341J35_125_6458_n97,
DP_OP_341J35_125_6458_n96, DP_OP_341J35_125_6458_n95,
DP_OP_341J35_125_6458_n93, DP_OP_341J35_125_6458_n92,
DP_OP_341J35_125_6458_n91, DP_OP_341J35_125_6458_n90,
DP_OP_341J35_125_6458_n89, DP_OP_341J35_125_6458_n88,
DP_OP_341J35_125_6458_n87, DP_OP_341J35_125_6458_n86,
DP_OP_341J35_125_6458_n85, DP_OP_341J35_125_6458_n84,
DP_OP_341J35_125_6458_n82, DP_OP_341J35_125_6458_n81,
DP_OP_341J35_125_6458_n80, DP_OP_341J35_125_6458_n79,
DP_OP_341J35_125_6458_n78, DP_OP_341J35_125_6458_n77,
DP_OP_341J35_125_6458_n76, DP_OP_341J35_125_6458_n75,
DP_OP_341J35_125_6458_n74, DP_OP_341J35_125_6458_n73,
DP_OP_341J35_125_6458_n72, DP_OP_341J35_125_6458_n69,
DP_OP_341J35_125_6458_n68, DP_OP_341J35_125_6458_n67,
DP_OP_341J35_125_6458_n66, DP_OP_341J35_125_6458_n65,
DP_OP_341J35_125_6458_n64, DP_OP_341J35_125_6458_n63,
DP_OP_341J35_125_6458_n62, DP_OP_341J35_125_6458_n61,
DP_OP_341J35_125_6458_n60, DP_OP_341J35_125_6458_n59,
DP_OP_341J35_125_6458_n58, DP_OP_341J35_125_6458_n57,
DP_OP_341J35_125_6458_n56, DP_OP_341J35_125_6458_n55,
DP_OP_341J35_125_6458_n54, DP_OP_341J35_125_6458_n53,
DP_OP_341J35_125_6458_n52, DP_OP_341J35_125_6458_n51,
DP_OP_341J35_125_6458_n50, DP_OP_341J35_125_6458_n49,
DP_OP_341J35_125_6458_n48, DP_OP_341J35_125_6458_n47,
DP_OP_341J35_125_6458_n46, DP_OP_341J35_125_6458_n45,
DP_OP_341J35_125_6458_n44, DP_OP_341J35_125_6458_n43,
DP_OP_341J35_125_6458_n42, DP_OP_341J35_125_6458_n41,
DP_OP_341J35_125_6458_n40, DP_OP_341J35_125_6458_n39,
DP_OP_341J35_125_6458_n38, DP_OP_341J35_125_6458_n37,
DP_OP_341J35_125_6458_n36, DP_OP_341J35_125_6458_n35,
DP_OP_341J35_125_6458_n34, DP_OP_341J35_125_6458_n33,
DP_OP_341J35_125_6458_n32, DP_OP_341J35_125_6458_n31,
DP_OP_341J35_125_6458_n30, DP_OP_341J35_125_6458_n29,
DP_OP_341J35_125_6458_n28, DP_OP_341J35_125_6458_n27,
DP_OP_341J35_125_6458_n26, DP_OP_341J35_125_6458_n25,
DP_OP_341J35_125_6458_n24, DP_OP_341J35_125_6458_n22,
DP_OP_341J35_125_6458_n21, DP_OP_341J35_125_6458_n20, n728, n729,
n730, n731, n733, n734, n735, n736, n737, n738, n739, n740, n741,
n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752,
n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774,
n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, n785,
n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796,
n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807,
n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818,
n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829,
n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840,
n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851,
n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862,
n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873,
n874, n875, n876, n877, n878, n879, n880, n881, n882, n883, n884,
n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895,
n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, n906,
n907, n908, n909, n910, n911, n912, n913, n914, n915, n916, n917,
n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928,
n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939,
n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950,
n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164,
n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174,
n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594,
n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614,
n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624,
n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634,
n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644,
n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654,
n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664,
n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674,
n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684,
n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694,
n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704,
n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714,
n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724,
n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734,
n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744,
n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754,
n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764,
n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774,
n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784,
n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794,
n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804,
n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814,
n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824,
n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834,
n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844,
n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854,
n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864,
n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874,
n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884,
n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894,
n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904,
n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914,
n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924,
n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934,
n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944,
n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954,
n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964,
n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974,
n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984,
n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994,
n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004,
n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034,
n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044,
n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054,
n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064,
n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074,
n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084,
n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094,
n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204,
n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214,
n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224,
n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234,
n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244,
n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254,
n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264,
n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274,
n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284,
n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294,
n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304,
n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314,
n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324,
n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334,
n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344,
n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354,
n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364,
n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374,
n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384,
n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394,
n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404,
n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414,
n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424,
n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434,
n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444,
n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454,
n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464,
n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474,
n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484,
n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494,
n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504,
n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694,
n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704,
n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714,
n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724,
n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944,
n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954,
n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964,
n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974,
n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984,
n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994,
n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004,
n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014,
n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024,
n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034,
n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044,
n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054,
n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064,
n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074,
n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084,
n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094,
n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104,
n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114,
n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124,
n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134,
n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144,
n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704,
n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754,
n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764,
n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774,
n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784,
n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794,
n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804,
n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814,
n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824,
n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834,
n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844,
n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854,
n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864,
n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874,
n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884,
n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894,
n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904,
n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914,
n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924,
n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934,
n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944,
n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954,
n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964,
n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974,
n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984,
n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994,
n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004,
n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014,
n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024,
n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034,
n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044,
n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054,
n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064,
n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074,
n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084,
n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094,
n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104,
n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114,
n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124,
n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134,
n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144,
n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154,
n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164,
n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174,
n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184,
n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194,
n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204,
n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214,
n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224,
n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234,
n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244,
n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254,
n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264,
n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274,
n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284,
n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294,
n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304,
n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314,
n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324,
n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334,
n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344,
n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354,
n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364,
n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374,
n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384,
n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394,
n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404,
n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414,
n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424,
n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434,
n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444,
n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454,
n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464,
n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474,
n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484,
n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494,
n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504,
n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514,
n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524,
n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534,
n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544,
n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554,
n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564,
n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574,
n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584,
n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594,
n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604,
n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614,
n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624,
n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634,
n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644,
n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654,
n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664,
n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674,
n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684,
n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694,
n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704,
n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714,
n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724,
n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734,
n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744,
n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754,
n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764,
n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774,
n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784,
n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794,
n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804,
n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814,
n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824,
n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834,
n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844,
n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854,
n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864,
n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874,
n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884,
n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894,
n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904,
n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914,
n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924,
n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934,
n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944,
n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954,
n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964,
n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974,
n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984,
n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994,
n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004,
n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014,
n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024,
n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034,
n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044,
n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054,
n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064,
n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074,
n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084,
n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094,
n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104,
n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114,
n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124,
n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134,
n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144,
n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154,
n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164,
n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174,
n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184,
n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194,
n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204,
n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214,
n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224,
n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234,
n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244,
n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254,
n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264,
n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274,
n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284,
n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294,
n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304,
n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314,
n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324,
n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334,
n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344,
n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354,
n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364,
n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374,
n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384,
n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394,
n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404,
n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414,
n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424,
n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434,
n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444,
n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454,
n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464,
n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474,
n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484,
n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494,
n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504,
n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514,
n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524,
n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534,
n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544,
n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554,
n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564,
n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574,
n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584,
n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594,
n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604,
n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614,
n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624,
n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634,
n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644,
n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654,
n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664,
n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674,
n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684,
n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694,
n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704,
n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714,
n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724,
n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734,
n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744,
n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754,
n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764,
n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774,
n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784,
n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794,
n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804,
n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814,
n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824,
n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834,
n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844,
n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854,
n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864,
n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874,
n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884,
n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894,
n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904,
n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914,
n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924,
n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934,
n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944,
n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954,
n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964,
n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974,
n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984,
n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994,
n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004,
n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014,
n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024,
n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034,
n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044,
n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054,
n6055, n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064,
n6065, n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074,
n6075, n6076, n6077, n6078, n6079, n6080, n6082, n6083, n6084, n6085,
n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095,
n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105,
n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115,
n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125,
n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135,
n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145,
n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155,
n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165,
n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175,
n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185,
n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195,
n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205,
n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215,
n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225,
n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235,
n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245,
n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255,
n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265,
n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275,
n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285,
n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295,
n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305,
n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315,
n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325,
n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335,
n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345,
n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355,
n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365,
n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375,
n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385,
n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395,
n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405,
n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415,
n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425,
n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435,
n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445,
n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455,
n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465,
n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474, n6475,
n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484, n6485,
n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494, n6495,
n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504, n6505,
n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514, n6515,
n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524, n6525,
n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534, n6535,
n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544, n6545,
n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554, n6555,
n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564, n6565,
n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574, n6575,
n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584, n6585,
n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595,
n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605,
n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615,
n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625,
n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635,
n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645,
n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655,
n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665,
n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675,
n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685,
n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695,
n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705,
n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715,
n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725,
n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735,
n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745,
n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755,
n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765,
n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775,
n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785,
n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795,
n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805,
n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815,
n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825,
n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835,
n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845,
n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855,
n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865,
n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875,
n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885,
n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895,
n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905,
n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915,
n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925,
n6926, n6927, n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935,
n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945,
n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955,
n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965,
n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975,
n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985,
n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995,
n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005,
n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015,
n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025,
n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035,
n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045,
n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055,
n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065,
n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075,
n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085,
n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095,
n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105,
n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115,
n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125,
n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135,
n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145,
n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155,
n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165,
n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175,
n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185,
n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195,
n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205,
n7206, n7207, n7208, n7209, n7210, n7211, n7212, n7213, n7214, n7215,
n7216, n7217, n7218, n7219, n7220, n7221, n7222, n7223, n7224, n7225,
n7226, n7227, n7228, n7229, n7230, n7231, n7232, n7233, n7234, n7235,
n7236, n7237, n7238, n7239, n7240, n7241, n7242, n7243, n7244, n7245,
n7246, n7247, n7248, n7249, n7250, n7251, n7252, n7253, n7254, n7255,
n7256, n7257, n7258, n7259, n7260, n7261, n7262, n7263, n7264, n7265,
n7266, n7267, n7268, n7269, n7270, n7271, n7272, n7273, n7274, n7275,
n7276, n7277, n7278, n7279, n7280, n7281, n7282, n7283, n7284, n7285,
n7286, n7287, n7288, n7289, n7290, n7291, n7292, n7293, n7294, n7295,
n7296, n7297, n7298, n7299, n7300, n7301, n7302, n7303, n7304, n7305,
n7306, n7307, n7308, n7309, n7310, n7311, n7312, n7313, n7314, n7315,
n7316, n7317, n7318, n7319, n7321, n7322, n7323, n7324, n7325, n7326,
n7327, n7328, n7329, n7330, n7331, n7332, n7333, n7334, n7335, n7336,
n7337, n7338, n7339, n7340, n7341, n7342, n7343, n7344, n7345, n7346,
n7347, n7348, n7349, n7350, n7351, n7352, n7353, n7354, n7355, n7356,
n7357, n7358, n7359, n7360, n7361, n7362, n7363, n7364, n7365, n7366,
n7367, n7368, n7369, n7370, n7371, n7372, n7373, n7374, n7375, n7376,
n7377, n7378, n7379, n7380, n7381, n7382, n7383, n7384, n7385, n7386,
n7387, n7388, n7389, n7390, n7391, n7392, n7393, n7394, n7395, n7396,
n7397, n7398, n7399, n7400, n7401, n7402, n7403, n7404, n7405, n7406,
n7407, n7408, n7409, n7410, n7411, n7412, n7413, n7414, n7415, n7416,
n7417, n7418, n7419, n7420, n7421, n7422, n7423, n7424, n7425, n7426,
n7427, n7428, n7429, n7430, n7431, n7432, n7433, n7434, n7435, n7436,
n7437, n7438, n7439, n7440, n7441, n7442, n7443, n7444, n7445, n7446,
n7447, n7448, n7449, n7450, n7451, n7452, n7453, n7454, n7455, n7456,
n7457, n7458, n7459, n7460, n7461, n7462, n7463, n7464, n7465, n7466,
n7467, n7468, n7469, n7470, n7471, n7472, n7473, n7474, n7475, n7476,
n7477, n7478, n7479, n7480, n7481, n7482, n7483, n7484, n7485, n7486,
n7487, n7488, n7489, n7490, n7491, n7492, n7493, n7494, n7495, n7496,
n7497, n7498, n7499, n7500, n7501, n7502, n7503, n7504, n7505, n7506,
n7507, n7508, n7509, n7510, n7511, n7512, n7513, n7514, n7515, n7516,
n7517, n7518, n7519, n7520, n7521, n7522, n7523, n7524, n7525, n7526,
n7527, n7528, n7529, n7530, n7531, n7532, n7533, n7534, n7535, n7536,
n7537, n7538, n7539, n7540, n7541, n7542, n7543, n7544, n7545, n7546,
n7547, n7548, n7549, n7550, n7551, n7552, n7553, n7554, n7555, n7556,
n7557, n7558, n7559, n7560, n7561, n7562, n7563, n7564, n7565, n7566,
n7567, n7568, n7569, n7570, n7571, n7572, n7573, n7574, n7575, n7576,
n7577, n7578, n7579, n7580, n7581, n7582, n7583, n7584, n7585, n7586,
n7587, n7588, n7589, n7590, n7591, n7592, n7593, n7594, n7595, n7596,
n7597, n7598, n7599, n7600, n7601, n7602, n7603, n7604, n7605, n7606,
n7607, n7608, n7609, n7610, n7611, n7612, n7613, n7614, n7615, n7616,
n7617, n7618, n7619, n7620, n7621, n7622, n7623, n7624, n7625, n7626,
n7627, n7628, n7629, n7630, n7631, n7632, n7633, n7634, n7635, n7636,
n7637, n7638, n7639, n7640, n7641, n7642, n7643, n7644, n7645, n7646,
n7647, n7648, n7649, n7650, n7651, n7652, n7653, n7654, n7655, n7656,
n7657, n7658, n7659, n7660, n7661, n7662, n7663, n7664, n7665, n7666,
n7667, n7668, n7669, n7670, n7671, n7672, n7673, n7674, n7675, n7676,
n7677, n7678, n7679, n7680, n7681, n7682, n7683, n7684, n7685, n7686,
n7687, n7688, n7689, n7690, n7691, n7692, n7693, n7694, n7695, n7696,
n7697, n7698, n7699, n7700, n7701, n7702, n7703, n7704, n7705, n7706,
n7707, n7708, n7709, n7710, n7711, n7712, n7713, n7714, n7715, n7716,
n7717, n7718, n7719, n7720, n7721, n7722, n7723, n7724, n7725, n7726,
n7727, n7728, n7729, n7730, n7731, n7732, n7733, n7734, n7735, n7736,
n7737, n7738, n7739, n7740, n7741, n7742, n7743, n7744, n7745, n7746,
n7747, n7748, n7749, n7750, n7751, n7752, n7753, n7754, n7755, n7756,
n7757, n7758, n7759, n7760, n7761, n7762, n7763, n7764, n7765, n7766,
n7767, n7768, n7769, n7770, n7771, n7772, n7773, n7774, n7775, n7776,
n7777, n7778, n7779, n7780, n7781, n7782, n7783, n7784, n7785, n7786,
n7787, n7788, n7789, n7790, n7791, n7792, n7793, n7794, n7795, n7796,
n7797, n7798, n7799, n7800, n7801, n7802, n7803, n7804, n7805, n7806,
n7807, n7808, n7809, n7810, n7811, n7812, n7813, n7814, n7815, n7816,
n7817, n7818, n7819, n7820, n7821, n7822, n7823, n7824, n7825, n7826,
n7827, n7828, n7829, n7830, n7831, n7832, n7833, n7834, n7835, n7836,
n7837, n7838, n7839, n7840, n7841, n7842, n7843, n7844, n7845, n7846,
n7847, n7848, n7849, n7850, n7851, n7852, n7853, n7854, n7855, n7856,
n7857, n7858, n7859, n7860, n7861, n7862, n7863, n7864, n7865, n7866,
n7867, n7868, n7869, n7870, n7871, n7872, n7873, n7874, n7875, n7876,
n7877, n7878, n7879, n7880, n7881, n7882, n7883, n7884, n7885, n7886,
n7887, n7888, n7889, n7890, n7891, n7892, n7893, n7894, n7895, n7896,
n7897, n7898, n7899, n7900, n7901, n7902, n7903, n7904, n7905, n7906,
n7907, n7908, n7909, n7910, n7911, n7912, n7913, n7914, n7915, n7916,
n7917, n7918, n7919, n7920, n7921, n7922, n7923, n7924, n7925, n7926,
n7927, n7928, n7929, n7930, n7931, n7932, n7933, n7934, n7935, n7936,
n7937, n7938, n7939, n7940, n7941, n7942, n7943, n7944, n7945, n7946,
n7947, n7948, n7949, n7950, n7951, n7952, n7953, n7954, n7955, n7956,
n7957, n7958, n7959, n7960, n7961, n7962, n7963, n7964, n7965, n7966,
n7967, n7968, n7969, n7970, n7971, n7972, n7973, n7974, n7975, n7976,
n7977, n7978, n7979, n7980, n7981, n7982, n7983, n7984, n7985, n7986,
n7987, n7988, n7989, n7990, n7991, n7992, n7993, n7994, n7995, n7996,
n7997, n7998, n7999, n8000, n8001, n8002, n8003, n8004, n8005, n8006,
n8007, n8008, n8009, n8010, n8011, n8012, n8013, n8014, n8015, n8016,
n8017, n8018, n8019, n8020, n8021, n8022, n8023, n8024, n8025, n8026,
n8027, n8028, n8029, n8030, n8031, n8032, n8033, n8034, n8035, n8036,
n8037, n8038, n8039, n8040, n8041, n8042, n8043, n8044, n8045, n8046,
n8047, n8048, n8049, n8050, n8051, n8052, n8053, n8054, n8055, n8056,
n8057, n8058, n8059, n8060, n8061, n8062, n8063, n8064, n8065, n8066,
n8067, n8068, n8069, n8070, n8071, n8072, n8073, n8074, n8075, n8076,
n8077, n8078, n8079, n8080, n8081, n8082, n8083, n8084, n8085, n8086,
n8087, n8088, n8089, n8090, n8091, n8092, n8093, n8094, n8095, n8096,
n8097, n8098, n8099, n8100, n8101, n8102, n8103, n8104, n8105, n8106,
n8107, n8108, n8109, n8110, n8111, n8112, n8113, n8114, n8115, n8116,
n8117, n8118, n8119, n8120, n8121, n8122, n8123, n8124, n8125, n8126,
n8127, n8128, n8129, n8130, n8131, n8132, n8133, n8134, n8135, n8136,
n8137, n8138, n8139, n8140, n8141, n8142, n8143, n8144, n8145, n8146,
n8147, n8148, n8149, n8150, n8151, n8152, n8153, n8154, n8155, n8156,
n8157, n8158, n8159, n8160, n8161, n8162, n8163, n8164, n8165, n8166,
n8167, n8168, n8169, n8170, n8171, n8172, n8173, n8174, n8175, n8176,
n8177, n8178, n8179, n8180, n8181, n8182, n8183, n8184, n8185, n8186,
n8187, n8188, n8189, n8190, n8191, n8192, n8193, n8194, n8195, n8196,
n8197, n8198, n8199, n8200, n8201, n8202, n8203, n8204, n8205, n8206,
n8207, n8208, n8209, n8210, n8211, n8212, n8213, n8214, n8215, n8216,
n8217, n8218, n8219, n8220, n8221, n8222, n8223, n8224, n8225, n8226,
n8227, n8228, n8229, n8230, n8231, n8232, n8233, n8234, n8235, n8236,
n8237, n8238, n8239, n8240, n8241, n8242, n8243, n8244, n8245, n8246,
n8247, n8248, n8249, n8250, n8251, n8252, n8253, n8254, n8255, n8256,
n8257, n8258, n8259, n8260, n8261, n8262, n8263, n8264, n8265, n8266,
n8267, n8268, n8269, n8270, n8271, n8272, n8273, n8274, n8275, n8276,
n8277, n8278, n8279, n8280, n8281, n8282, n8283, n8284, n8285, n8286,
n8287, n8288, n8289, n8290, n8291, n8292, n8293, n8294, n8295, n8296,
n8297, n8298, n8299, n8300, n8301, n8302, n8303, n8304, n8305, n8306,
n8307, n8308, n8309, n8310, n8311, n8312, n8313, n8314, n8315, n8316,
n8317, n8318, n8319, n8320, n8321, n8322, n8323, n8324, n8325, n8326,
n8327, n8328, n8329, n8330, n8331, n8332, n8333, n8334, n8335, n8336,
n8337, n8338, n8339, n8340, n8341, n8342, n8343, n8344, n8345, n8346,
n8347, n8348, n8349, n8350, n8351, n8352, n8353, n8354, n8355, n8356,
n8357, n8358, n8359, n8360, n8361, n8362, n8363, n8364, n8365, n8366,
n8367, n8368, n8369, n8370, n8371, n8372, n8373, n8374, n8375, n8376,
n8377, n8378, n8379, n8380, n8381, n8382, n8383, n8384, n8385, n8386,
n8387, n8388, n8389, n8390, n8391, n8392, n8393, n8394, n8395, n8396,
n8397, n8398, n8399, n8400, n8401, n8402, n8403, n8404, n8405, n8406,
n8407, n8408, n8409, n8410, n8411, n8412, n8413, n8414, n8415, n8416,
n8417, n8418, n8419, n8420, n8421, n8422, n8423, n8424, n8425, n8426,
n8427, n8428, n8429, n8430, n8431, n8432, n8433, n8434, n8435, n8436,
n8437, n8438, n8439, n8440, n8441, n8442, n8443, n8444, n8445, n8446,
n8447, n8448, n8449, n8450, n8451, n8452, n8453, n8454, n8455, n8456,
n8457, n8458, n8459, n8460, n8461, n8462, n8463, n8464, n8465, n8466,
n8467, n8468, n8469, n8470, n8471, n8472, n8473, n8474, n8475, n8476,
n8477, n8478, n8479, n8480, n8481, n8482, n8483, n8484, n8485, n8486,
n8487, n8488, n8489, n8490, n8491, n8492, n8493, n8494, n8495, n8496,
n8497, n8498, n8499, n8500, n8501, n8502, n8503, n8504, n8505, n8506,
n8507, n8508, n8509, n8510, n8511, n8512, n8513, n8514, n8515, n8516,
n8517, n8518, n8519, n8520, n8521, n8522, n8523, n8524, n8525, n8526,
n8527, n8528, n8529, n8530, n8531, n8532, n8533, n8534, n8535, n8536,
n8537, n8538, n8539, n8540, n8541, n8542, n8543, n8544, n8545, n8546,
n8547, n8548, n8549, n8550, n8551, n8552, n8553, n8554, n8555, n8556,
n8557, n8558, n8559, n8560, n8561, n8562, n8563, n8564, n8565, n8566,
n8567, n8568, n8569, n8570, n8571, n8572, n8573, n8574, n8575, n8576,
n8577, n8578, n8579, n8580, n8581, n8582, n8583, n8584, n8585, n8586,
n8587, n8588, n8589, n8590, n8591, n8592, n8593, n8594, n8595, n8596,
n8597, n8598, n8599, n8600, n8601, n8602, n8603, n8604, n8605, n8606,
n8607, n8608, n8609, n8610, n8611, n8612, n8613, n8614, n8615, n8616,
n8617, n8618, n8619, n8620, n8621, n8622, n8623, n8624, n8625, n8626,
n8627, n8628, n8629, n8630, n8631, n8632, n8633, n8634, n8635, n8636,
n8637, n8638, n8639, n8640, n8641, n8642, n8643, n8644, n8645, n8646,
n8647, n8648, n8649, n8650, n8651, n8652, n8653, n8654, n8655, n8656,
n8657, n8658, n8659, n8660, n8661, n8662, n8663, n8664, n8665, n8666,
n8667, n8668, n8669, n8670, n8671, n8672, n8673, n8674, n8675, n8676,
n8677, n8678, n8679, n8680, n8681, n8682, n8683, n8684, n8685, n8686,
n8687, n8688, n8689, n8690, n8691, n8692, n8693, n8694, n8695, n8696,
n8697, n8698, n8699, n8700, n8701, n8702, n8703, n8704, n8705, n8706,
n8707, n8708, n8709, n8710, n8711, n8712, n8713, n8714, n8715, n8716,
n8717, n8718, n8719, n8720, n8721, n8722, n8723, n8724, n8725, n8726,
n8727, n8728, n8729, n8730, n8731, n8732, n8733, n8734, n8735, n8736,
n8737, n8738, n8739, n8740, n8741, n8742, n8743, n8744, n8745, n8746,
n8747, n8748, n8749, n8750, n8751, n8752, n8753, n8754, n8755, n8756,
n8757, n8758, n8759, n8760, n8761, n8762, n8763, n8764, n8765, n8766,
n8767, n8768, n8769, n8770, n8771, n8772, n8773, n8774, n8775, n8776,
n8777, n8778, n8779, n8780, n8781, n8782, n8783, n8784, n8785, n8786,
n8787, n8788, n8789, n8790, n8791, n8792, n8793, n8794, n8795, n8796,
n8797, n8798, n8799, n8800, n8801, n8802, n8803, n8804, n8805, n8806,
n8807, n8808, n8809, n8810, n8811, n8812, n8813, n8814, n8815, n8816,
n8817, n8818, n8819, n8820, n8821, n8822, n8823, n8824, n8825, n8826,
n8827, n8828, n8829, n8830, n8831, n8832, n8833, n8834, n8835, n8836,
n8837, n8838, n8839, n8840, n8841, n8842, n8843, n8844, n8845, n8846,
n8847, n8848, n8849, n8850, n8851, n8852, n8853, n8854, n8855, n8856,
n8857, n8858, n8859, n8860, n8861, n8862, n8863, n8864, n8865, n8866,
n8867, n8868, n8869, n8870, n8871, n8872, n8873, n8874, n8875, n8876,
n8877, n8878, n8879, n8880, n8881, n8882, n8883, n8884, n8885, n8886,
n8887, n8888, n8889, n8890, n8891, n8892, n8893, n8894, n8895, n8896,
n8897, n8898, n8899, n8900, n8901, n8902, n8903, n8904, n8905, n8906,
n8907, n8908, n8909, n8910, n8911, n8912, n8913, n8914, n8915, n8916,
n8917, n8918, n8919, n8920, n8921, n8922, n8923, n8924, n8925, n8926,
n8927, n8928, n8929, n8930, n8931, n8932, n8933, n8934, n8935, n8936,
n8937, n8938, n8939, n8940, n8941, n8942, n8943, n8944, n8945, n8946,
n8947, n8948, n8949, n8950, n8951, n8952, n8953, n8954, n8955, n8956,
n8957, n8958, n8959, n8960, n8961, n8962, n8963, n8964, n8965, n8966,
n8967, n8968, n8969, n8970, n8971, n8972, n8973, n8974, n8975, n8976,
n8977, n8978, n8979, n8980, n8981, n8982, n8983, n8984, n8985, n8986,
n8987, n8988, n8989, n8990, n8991, n8992, n8993, n8994, n8995, n8996,
n8997, n8998, n8999, n9000, n9001, n9002, n9003, n9004, n9005, n9006,
n9007, n9008, n9009, n9010, n9011, n9012, n9013, n9014, n9015, n9016,
n9017, n9018, n9019, n9020, n9021, n9022, n9023, n9024, n9025, n9026,
n9027, n9028, n9029, n9030, n9031, n9032, n9033, n9034, n9035, n9036,
n9037, n9038, n9039, n9040, n9041, n9042, n9043, n9044, n9045, n9046,
n9047, n9048, n9049, n9050, n9051, n9052, n9053, n9054, n9055, n9056,
n9057, n9058, n9059, n9060, n9061, n9062, n9063, n9064, n9065, n9066,
n9067, n9068, n9069, n9070, n9071, n9072, n9073, n9074, n9075, n9076,
n9077, n9078, n9079, n9080, n9081, n9082, n9083, n9084, n9085, n9086,
n9087, n9088, n9089, n9090, n9091, n9092, n9093, n9094, n9095, n9096,
n9097, n9098, n9099, n9100, n9101, n9102, n9103, n9104, n9105, n9106,
n9107, n9108, n9109, n9110, n9111, n9112, n9113, n9114, n9115, n9116,
n9117, n9118, n9119, n9120, n9121, n9122, n9123, n9124, n9125, n9126,
n9127, n9128, n9129, n9130, n9131, n9132, n9133, n9134, n9135, n9136,
n9137, n9138, n9139, n9140, n9141, n9142, n9143, n9144, n9145, n9146,
n9147, n9148, n9149, n9150, n9151, n9152, n9153, n9154, n9155, n9156,
n9157, n9158, n9159, n9160, n9161, n9162, n9163, n9164, n9165, n9166,
n9167, n9168, n9169, n9170, n9171, n9172, n9173, n9174, n9175, n9176,
n9177, n9178, n9179, n9180, n9181, n9182, n9183, n9184, n9185, n9186,
n9187, n9188, n9189, n9190, n9191, n9192, n9193, n9194, n9195, n9196,
n9197, n9198, n9199, n9200, n9201, n9202, n9203, n9204, n9205, n9206,
n9207, n9208, n9209, n9210, n9211, n9212, n9213, n9214, n9215, n9216,
n9217, n9218, n9219, n9220, n9221, n9222, n9223, n9224, n9225, n9226,
n9227, n9228, n9229, n9230, n9231, n9232, n9233, n9234, n9235, n9236,
n9237, n9238, n9239, n9240, n9241, n9242, n9243, n9244, n9245, n9246,
n9247, n9248, n9249, n9250, n9251, n9252, n9253, n9254, n9255, n9256,
n9257, n9258, n9259, n9260, n9261, n9262, n9263, n9264, n9265, n9266,
n9267, n9268, n9269, n9270, n9271, n9272, n9273, n9274, n9275, n9276,
n9277, n9278, n9279, n9280, n9281, n9282, n9283, n9284, n9285, n9286,
n9287, n9288, n9289, n9290, n9291, n9292, n9293, n9294, n9295, n9296,
n9297, n9298, n9299, n9300, n9301, n9302, n9303, n9304, n9305, n9306,
n9307, n9308, n9309, n9310, n9311, n9312, n9313, n9314, n9315, n9316,
n9317, n9318, n9319, n9320, n9321, n9322, n9323, n9324, n9325, n9326,
n9327, n9328, n9329, n9330, n9331, n9332, n9333, n9334, n9335, n9336,
n9337, n9338, n9339, n9340, n9341, n9342, n9343, n9344, n9345, n9346,
n9347, n9348, n9349, n9350, n9351, n9352, n9353, n9354, n9355, n9356,
n9357, n9358, n9359, n9360, n9361, n9362, n9363, n9364, n9365, n9366,
n9367, n9368, n9369, n9370, n9371, n9372, n9373, n9374, n9375, n9376,
n9377, n9378, n9379, n9380, n9381, n9382, n9383, n9384, n9385, n9386,
n9387, n9388, n9389, n9390, n9391, n9392, n9393, n9394, n9395, n9396,
n9397, n9398, n9399, n9400, n9401, n9402, n9403, n9404, n9405, n9406,
n9407, n9408, n9409, n9410, n9411, n9412, n9413, n9414, n9415, n9416,
n9417, n9418, n9419, n9420, n9421, n9422, n9423, n9424, n9425, n9426,
n9427, n9428, n9429, n9430, n9431, n9432, n9433, n9434, n9435, n9436,
n9437, n9438, n9439, n9440, n9441, n9442, n9443, n9444, n9445, n9446,
n9447, n9448, n9449, n9450, n9451, n9452, n9453, n9454, n9455, n9456,
n9457, n9458, n9459, n9460, n9461, n9462, n9463, n9464, n9465, n9466,
n9467, n9468, n9469, n9470, n9471, n9472, n9473, n9474, n9475, n9476,
n9477, n9478, n9479, n9480, n9481, n9482, n9483, n9484, n9485, n9486,
n9487, n9488, n9489, n9490, n9491, n9492, n9493, n9494, n9495, n9496,
n9497, n9498, n9499, n9500, n9501, n9502, n9503, n9504, n9505, n9506,
n9507, n9508, n9509, n9510, n9511, n9512, n9513, n9514, n9515, n9516,
n9517, n9518, n9519, n9520, n9521, n9522, n9523, n9524, n9525, n9526,
n9527, n9528, n9529, n9530, n9531, n9532, n9533, n9534, n9535, n9536,
n9537, n9538, n9539, n9540, n9541, n9542, n9543, n9544, n9545, n9546,
n9547, n9548, n9549, n9550, n9551, n9552, n9553, n9554, n9555, n9556,
n9557, n9558, n9559, n9560, n9561, n9562, n9563, n9564, n9565, n9566,
n9567, n9568, n9569, n9570, n9571, n9572, n9573, n9574, n9575, n9576,
n9577, n9578, n9579, n9580, n9581, n9582, n9583, n9584, n9585, n9586,
n9587, n9588, n9589, n9590, n9591, n9592, n9593, n9594, n9595, n9596,
n9597, n9598, n9599, n9600, n9601, n9602, n9603, n9604, n9605, n9606,
n9607, n9608, n9609, n9611, n9612, n9613, n9614, n9615, n9616, n9617,
n9618, n9619, n9620, n9621, n9622, n9623, n9624, n9625, n9626, n9627,
n9628, n9629, n9630, n9631, n9632, n9633, n9634, n9635, n9636, n9637,
n9638, n9639, n9640, n9641, n9642, n9643, n9644, n9645, n9646, n9647,
n9648, n9649, n9650, n9651, n9652, n9653, n9654, n9656, n9657, n9658,
n9659, n9660, n9661, n9662, n9663, n9664, n9665, n9666, n9667, n9668,
n9670, n9671, n9672, n9673, n9674, n9675, n9676, n9677, n9678, n9679,
n9680, n9681, n9682, n9683, n9684, n9685, n9686, n9687, n9688, n9689,
n9690, n9691, n9692, n9693, n9694, n9695, n9696, n9697, n9698, n9699,
n9700, n9701, n9702, n9703, n9704, n9705, n9706, n9707, n9708, n9709,
n9710, n9711, n9712, n9713, n9714, n9715, n9716, n9717, n9718, n9719,
n9720, n9721, n9722, n9723, n9724, n9725, n9726, n9727, n9728, n9729,
n9730, n9731, n9732, n9733, n9734, n9735, n9736, n9737, n9738, n9739,
n9740, n9741, n9742, n9743, n9744, n9745, n9746, n9747, n9748, n9749,
n9750, n9751, n9752, n9753, n9754, n9755, n9756, n9757, n9758, n9759,
n9760, n9761, n9762, n9763, n9764, n9765, n9766, n9767, n9768, n9769,
n9770, n9771, n9772, n9773, n9774, n9775, n9776, n9777, n9778, n9779,
n9780, n9781, n9782, n9783, n9784, n9785, n9786, n9787, n9788, n9789,
n9790, n9791, n9792, n9793, n9794, n9795, n9796, n9797, n9798, n9799,
n9800, n9801, n9802, n9803, n9804, n9805, n9806, n9807, n9808, n9809,
n9811, n9812, n9813, n9814, n9815, n9816, n9817, n9818, n9819, n9820,
n9821, n9822, n9823, n9824, n9825, n9826, n9827, n9829, n9830, n9831,
n9832, n9833, n9834, n9835, n9836, n9837, n9838, n9839, n9840, n9841,
n9842, n9843, n9844, n9845, n9846, n9847, n9848, n9849, n9850, n9851,
n9852, n9853, n9854, n9855, n9856, n9857, n9858, n9859, n9860, n9861,
n9862, n9863, n9864, n9865, n9866, n9867, n9868, n9869, n9870, n9871,
n9872, n9873, n9874, n9875, n9876, n9877, n9878, n9879, n9880, n9881,
n9882, n9883, n9884, n9885, n9886, n9887, n9888, n9889, n9890, n9891,
n9892, n9893, n9894, n9895, n9896, n9897, n9898, n9899, n9900, n9901,
n9902, n9903, n9904, n9905, n9906, n9907, n9908, n9909, n9910, n9911,
n9912, n9913, n9914, n9915, n9916, n9917, n9918, n9919, n9920, n9921,
n9922, n9923, n9924, n9925, n9926, n9927, n9928, n9929, n9930, n9931,
n9932, n9933, n9934, n9935, n9936, n9937, n9938, n9939, n9940, n9941,
n9942, n9943, n9944, n9945, n9946, n9947, n9948, n9949, n9950, n9951,
n9952, n9953, n9954, n9955, n9956, n9957, n9958, n9959, n9960, n9961,
n9962, n9963, n9964, n9965, n9966, n9967, n9968, n9969, n9970, n9971,
n9972, n9973, n9974, n9975, n9976, n9977, n9978, n9979, n9980, n9981,
n9982, n9983, n9984, n9985, n9986, n9987, n9988, n9989, n9990, n9991,
n9992, n9993, n9994, n9995, n9996, n9997, n9998, n9999, n10000,
n10001, n10002, n10003, n10004, n10005, n10006, n10007, n10008,
n10009, n10010, n10011, n10012, n10013, n10014, n10015, n10016,
n10017, n10018, n10019, n10020, n10021, n10022, n10023, n10024,
n10025, n10026, n10027, n10028, n10029, n10030, n10031, n10032,
n10033, n10034, n10035, n10036, n10037, n10038, n10039, n10040,
n10041, n10042, n10043, n10044, n10045, n10046, n10047, n10048,
n10049, n10050, n10051, n10052, n10053, n10054, n10055, n10056,
n10057, n10058, n10059, n10060, n10061, n10062, n10063, n10064,
n10065, n10066, n10067, n10068, n10069, n10070, n10071, n10072,
n10073, n10074, n10075, n10076, n10077, n10078, n10079, n10080,
n10081, n10082, n10083, n10084, n10085, n10086, n10087, n10088,
n10089, n10090, n10091, n10092, n10093, n10094, n10095, n10096,
n10097, n10098, n10099, n10100, n10101, n10102, n10103, n10104,
n10105, n10106, n10107, n10108, n10109, n10110, n10111, n10112,
n10113, n10114, n10115, n10116, n10117, n10118, n10119, n10120,
n10121, n10122, n10123, n10124, n10125, n10126, n10127, n10128,
n10129, n10130, n10131, n10132, n10133, n10134, n10135, n10136,
n10137, n10138, n10139, n10140, n10141, n10142, n10143, n10144,
n10145, n10146, n10147, n10148, n10149, n10150, n10151, n10152,
n10153, n10154, n10155, n10156, n10157, n10158, n10159, n10160,
n10161, n10162, n10163, n10164, n10165, n10166, n10167, n10168,
n10169, n10170, n10171, n10172, n10173, n10174, n10175, n10176,
n10177, n10178, n10179, n10180, n10181, n10182, n10183, n10184,
n10185, n10186, n10187, n10188, n10189, n10190, n10191, n10192,
n10193, n10194, n10195, n10196, n10197, n10198, n10199, n10200,
n10201, n10202, n10203, n10204, n10205, n10206, n10207, n10208,
n10209, n10210, n10211, n10212, n10213, n10214, n10215, n10216,
n10217, n10218, n10219, n10220, n10221, n10222, n10223, n10224,
n10225, n10226, n10227, n10228, n10229, n10230, n10231, n10232,
n10233, n10234, n10235, n10236, n10237, n10238, n10239, n10240,
n10241, n10242, n10243, n10244, n10245, n10246, n10247, n10248,
n10249, n10250, n10251, n10252, n10253, n10254, n10255, n10256,
n10257, n10258, n10259, n10260, n10261, n10262, n10263, n10264,
n10265, n10266, n10267, n10268, n10269, n10270, n10271, n10272,
n10273, n10274, n10275, n10276, n10277, n10278, n10279, n10280,
n10281, n10282, n10283, n10284, n10285, n10286, n10287, n10288,
n10289, n10290, n10291, n10292, n10293, n10294, n10295, n10296,
n10297, n10298, n10299, n10300, n10301, n10302, n10303, n10304,
n10305, n10306, n10307, n10308, n10309, n10310, n10311, n10312,
n10313, n10314, n10315, n10316, n10317, n10318, n10319, n10320,
n10321, n10322, n10323, n10324, n10325, n10326, n10327, n10328,
n10329, n10330, n10331, n10332, n10333, n10334, n10335, n10336,
n10337, n10338, n10339, n10340, n10341, n10342, n10343, n10344,
n10345, n10346, n10347, n10348, n10349, n10350, n10351, n10352,
n10353, n10354, n10355, n10356, n10357, n10358, n10359, n10360,
n10361, n10362, n10363, n10364, n10365, n10366, n10367, n10368,
n10369, n10370, n10371, n10372, n10373, n10374, n10375, n10376,
n10377, n10378, n10379, n10380, n10381, n10382, n10383, n10384,
n10385, n10386, n10387, n10388, n10389, n10390, n10391, n10392,
n10393, n10394, n10395, n10396, n10397, n10398, n10399, n10400,
n10401, n10402, n10403, n10404, n10405, n10406, n10407, n10408,
n10409, n10410, n10411, n10412, n10413, n10414, n10415, n10416,
n10417, n10418, n10419, n10420, n10421, n10422, n10423, n10424,
n10425, n10426, n10427, n10428, n10429, n10430, n10431, n10432,
n10433, n10434, n10435, n10436, n10437, n10438, n10439, n10440,
n10441, n10442, n10443, n10444, n10445, n10446, n10447, n10448,
n10449, n10450, n10451, n10452, n10453, n10454, n10455, n10456,
n10457, n10458, n10459, n10460, n10461, n10462, n10463, n10464,
n10465, n10466, n10467, n10468, n10469, n10470, n10471, n10472,
n10473, n10474, n10475, n10476, n10477, n10478, n10479, n10480,
n10481, n10482, n10483, n10484, n10485, n10486, n10487, n10488,
n10489, n10490, n10491, n10492, n10493, n10494, n10495, n10496,
n10497, n10498, n10499, n10500, n10501, n10502, n10503, n10504,
n10505, n10506, n10507, n10508, n10509, n10510, n10511, n10512,
n10513, n10514, n10515, n10516, n10517, n10518, n10519, n10520,
n10521, n10522, n10523, n10524, n10525, n10526, n10527, n10528,
n10529, n10530, n10531, n10532, n10533, n10534, n10535, n10536,
n10537, n10538, n10539, n10540, n10541, n10542, n10543, n10544,
n10545, n10546, n10547, n10548, n10549, n10550, n10551, n10552,
n10553, n10554, n10555, n10556, n10557, n10558, n10559, n10560,
n10561, n10562, n10563, n10564, n10565, n10566, n10567, n10568,
n10569, n10570, n10571, n10572, n10573, n10574, n10575, n10576,
n10577, n10578, n10579, n10580, n10581, n10582, n10583, n10584,
n10585, n10586, n10587, n10588, n10589, n10590, n10591, n10592,
n10593, n10594, n10595, n10596, n10597, n10598, n10599, n10600,
n10601, n10602, n10603, n10604, n10605, n10606, n10607, n10608,
n10609, n10610, n10611, n10612, n10613, n10614, n10615, n10616,
n10617, n10618, n10619, n10620, n10621, n10622, n10623, n10624,
n10625, n10626, n10627, n10628, n10629, n10630, n10631, n10632,
n10633, n10634, n10635, n10636, n10637, n10638, n10639, n10640,
n10641, n10642, n10643, n10644, n10645, n10646, n10647, n10648,
n10649, n10650, n10651, n10652, n10653, n10654, n10655, n10656,
n10657, n10658, n10659, n10660, n10661, n10662, n10663, n10664,
n10665, n10666, n10667, n10668, n10669, n10670, n10671, n10672,
n10673, n10674, n10675, n10676, n10677, n10678, n10679, n10680,
n10681, n10682, n10683, n10684, n10685, n10686, n10687, n10688,
n10689, n10690, n10691, n10692, n10693, n10694, n10695, n10696,
n10697, n10698, n10699, n10700, n10701, n10702, n10703, n10704,
n10705, n10706, n10707, n10708, n10709, n10710, n10711, n10712,
n10713, n10714, n10715, n10716, n10717, n10718, n10719, n10720,
n10721, n10722, n10723, n10724, n10725, n10726, n10727, n10728,
n10729, n10730, n10731, n10732, n10733, n10734, n10735, n10736,
n10737, n10738, n10739, n10740, n10741, n10742, n10743, n10744,
n10745, n10746, n10747, n10748, n10749, n10750, n10751, n10752,
n10753, n10754, n10755, n10756, n10757, n10758, n10759, n10760,
n10761, n10762, n10763, n10764, n10765, n10766, n10767, n10768,
n10769, n10770, n10771, n10772, n10773, n10774, n10775, n10776,
n10777, n10778, n10779, n10780, n10781, n10782, n10783, n10784,
n10785, n10786, n10787, n10788, n10789, n10790, n10791, n10792,
n10793, n10794, n10795, n10796, n10797, n10798, n10799, n10800,
n10801, n10802, n10803, n10804, n10805, n10806, n10807, n10808,
n10809, n10810, n10811, n10812, n10813, n10814, n10815, n10816,
n10817, n10818, n10819, n10820, n10821, n10822, n10823, n10825,
n10826, n10827, n10828, n10829, n10830, n10831, n10832, n10833,
n10834, n10835, n10836, n10837, n10838, n10839, n10840, n10841,
n10842, n10843, n10844, n10845, n10846, n10847, n10848, n10849,
n10850, n10851, n10852, n10853, n10854, n10855, n10856, n10857,
n10858, n10859, n10860, n10861, n10862, n10863, n10864, n10865,
n10866, n10867, n10868, n10869, n10870, n10871, n10872, n10873,
n10874, n10875, n10876, n10877, n10878, n10879, n10880, n10881,
n10882, n10883, n10884, n10885, n10886, n10887, n10888, n10889,
n10890, n10891, n10892, n10893, n10894, n10895, n10896, n10897,
n10898, n10899, n10900, n10901, n10902, n10903, n10904, n10905,
n10906, n10907, n10908, n10909, n10910, n10911, n10912, n10913,
n10914, n10915, n10916, n10917, n10918, n10919, n10920, n10921,
n10922, n10923, n10924, n10925, n10926, n10927, n10928, n10929,
n10930, n10931, n10932, n10933, n10934, n10935, n10936, n10937,
n10938, n10939, n10940, n10941, n10942, n10943, n10944, n10945,
n10946, n10947, n10948, n10949, n10950, n10951, n10952, n10953,
n10954, n10955, n10956, n10957, n10958, n10959, n10960, n10961,
n10962, n10963, n10964, n10965, n10966, n10967, n10968, n10969,
n10970, n10971, n10972, n10973, n10974, n10975, n10976, n10977,
n10978, n10979, n10980, n10981, n10982, n10983, n10984, n10985,
n10986, n10987, n10988, n10989, n10990, n10991, n10992, n10993,
n10994, n10995, n10996, n10997, n10998, n11000, n11001, n11002,
n11003, n11004, n11005, n11006, n11007, n11008, n11009, n11010,
n11011, n11012, n11013, n11014, n11015, n11016, n11017, n11018,
n11019, n11020, n11021, n11022, n11023, n11024, n11025, n11026,
n11027, n11028, n11029, n11030, n11031, n11032, n11033, n11034,
n11035, n11036, n11037, n11038, n11039, n11040, n11041, n11042,
n11043, n11044, n11045, n11046, n11047, n11048, n11049, n11050,
n11051, n11052, n11053, n11054, n11055, n11056, n11057, n11058,
n11059, n11060, n11061, n11062, n11063, n11064, n11065, n11066,
n11067, n11068, n11069, n11070, n11071, n11072, n11073, n11074,
n11075, n11076, n11077, n11078, n11079, n11080, n11081, n11082,
n11083, n11084, n11085, n11086, n11087, n11088, n11089, n11090,
n11091, n11092, n11093, n11094, n11095, n11096, n11097, n11098,
n11099, n11100, n11101, n11102, n11103, n11104, n11105, n11106,
n11107, n11108, n11109, n11110, n11111, n11112, n11113, n11114,
n11115, n11116, n11117, n11118, n11119, n11120, n11121, n11122,
n11123, n11124, n11125, n11126, n11127, n11128, n11129, n11130,
n11131, n11132, n11133, n11134, n11135, n11136, n11137, n11138,
n11139, n11140, n11141, n11142, n11143, n11144, n11145, n11146,
n11147, n11148, n11149, n11150, n11151, n11152, n11153, n11154,
n11155, n11156, n11157, n11158, n11159, n11160, n11161, n11162,
n11163, n11164, n11165, n11166, n11167, n11168, n11169, n11170,
n11171, n11172, n11173, n11174, n11175, n11176, n11177, n11178,
n11179, n11180, n11181, n11182, n11183, n11184, n11185, n11186,
n11187, n11188, n11189, n11190, n11191, n11192, n11193, n11194,
n11195, n11196, n11197, n11198, n11199, n11200, n11201, n11202,
n11203, n11204, n11205, n11206, n11207, n11208, n11209, n11210,
n11211, n11212, n11213, n11214, n11215, n11216, n11217, n11218,
n11219, n11220, n11221, n11222, n11223, n11224, n11225, n11226,
n11227, n11228, n11229, n11230, n11231, n11232, n11233, n11234,
n11235, n11236, n11237, n11238, n11239, n11240, n11241, n11242,
n11243, n11244, n11245, n11246, n11247, n11248, n11249;
wire [105:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [63:0] Op_MX;
wire [63:0] Op_MY;
wire [11:0] exp_oper_result;
wire [11:0] S_Oper_A_exp;
wire [52:0] Add_result;
wire [52:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [11:0] Exp_module_Data_S;
wire [27:1] Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B;
wire [29:20] Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle;
wire
[15:1] Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_S_B
;
wire
[13:1] Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right
;
wire
[13:0] Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left
;
wire
[17:10] Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B
;
wire
[12:4] Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left
;
wire
[11:4] Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left
;
wire
[17:10] Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B
;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_63_ ( .D(n715), .CK(clk), .RN(
n11235), .Q(Op_MY[63]) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n661), .CK(clk), .RN(
n11236), .QN(n816) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_50_ ( .D(n529), .CK(clk), .RN(n11231),
.QN(n863) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_49_ ( .D(n530), .CK(clk), .RN(n11231),
.QN(n860) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_48_ ( .D(n531), .CK(clk), .RN(n11231),
.QN(n862) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_47_ ( .D(n532), .CK(clk), .RN(n11231),
.QN(n859) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_45_ ( .D(n534), .CK(clk), .RN(n11231),
.QN(n858) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_44_ ( .D(n535), .CK(clk), .RN(n11231),
.QN(n861) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_43_ ( .D(n536), .CK(clk), .RN(n11231),
.QN(n857) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n566), .CK(clk), .RN(n11234),
.QN(n866) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n568), .CK(clk), .RN(n11234),
.QN(n865) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n570), .CK(clk), .RN(n11234),
.QN(n864) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n579), .CK(clk), .RN(n11240),
.Q(Add_result[0]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_67_ ( .D(n488), .CK(clk), .RN(
n11246), .Q(P_Sgf[67]), .QN(n11206) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_42_ ( .D(n463), .CK(clk), .RN(
n11247), .Q(P_Sgf[42]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_41_ ( .D(n462), .CK(clk), .RN(
n11247), .Q(P_Sgf[41]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_40_ ( .D(n461), .CK(clk), .RN(
n11247), .Q(P_Sgf[40]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_39_ ( .D(n460), .CK(clk), .RN(
n11244), .Q(P_Sgf[39]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_35_ ( .D(n456), .CK(clk), .RN(
n11242), .Q(P_Sgf[35]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_31_ ( .D(n452), .CK(clk), .RN(
n11245), .Q(P_Sgf[31]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_27_ ( .D(n448), .CK(clk), .RN(
n11245), .Q(P_Sgf[27]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_23_ ( .D(n444), .CK(clk), .RN(
n11245), .Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_16_ ( .D(n437), .CK(clk), .RN(
n11246), .Q(P_Sgf[16]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_15_ ( .D(n436), .CK(clk), .RN(
n11246), .Q(P_Sgf[15]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_11_ ( .D(n432), .CK(clk), .RN(
n11246), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_7_ ( .D(n428), .CK(clk), .RN(
n11247), .Q(P_Sgf[7]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_3_ ( .D(n424), .CK(clk), .RN(
n11242), .Q(P_Sgf[3]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n405), .CK(clk), .RN(n11227),
.Q(Exp_module_Overflow_flag_A) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n351),
.CK(clk), .RN(n11226), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n350),
.CK(clk), .RN(n11226), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n349),
.CK(clk), .RN(n11235), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n348),
.CK(clk), .RN(n11226), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n347),
.CK(clk), .RN(n11235), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n346),
.CK(clk), .RN(n11226), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n345),
.CK(clk), .RN(n11231), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n344),
.CK(clk), .RN(n11231), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n343),
.CK(clk), .RN(n11231), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n342),
.CK(clk), .RN(n11231), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n341),
.CK(clk), .RN(n11231), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n340),
.CK(clk), .RN(n11231), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n339),
.CK(clk), .RN(n11231), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n338),
.CK(clk), .RN(n11231), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n337),
.CK(clk), .RN(n11231), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n336),
.CK(clk), .RN(n11231), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n335),
.CK(clk), .RN(n11231), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n334),
.CK(clk), .RN(n11231), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n333),
.CK(clk), .RN(n11232), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n332),
.CK(clk), .RN(n11232), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n331),
.CK(clk), .RN(n11232), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n330),
.CK(clk), .RN(n11232), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n329),
.CK(clk), .RN(n11232), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n328),
.CK(clk), .RN(n11232), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n327),
.CK(clk), .RN(n11232), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n326),
.CK(clk), .RN(n11232), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n325),
.CK(clk), .RN(n11232), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n324),
.CK(clk), .RN(n11232), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n323),
.CK(clk), .RN(n11232), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n322),
.CK(clk), .RN(n11232), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n321),
.CK(clk), .RN(n11233), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n320),
.CK(clk), .RN(n11233), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n319),
.CK(clk), .RN(n11233), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n318),
.CK(clk), .RN(n11233), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n317),
.CK(clk), .RN(n11233), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n316),
.CK(clk), .RN(n11233), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n315),
.CK(clk), .RN(n11233), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n314),
.CK(clk), .RN(n11233), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n313),
.CK(clk), .RN(n11233), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n312),
.CK(clk), .RN(n11233), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n311),
.CK(clk), .RN(n11233), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n310),
.CK(clk), .RN(n11233), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n309),
.CK(clk), .RN(n11234), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n308),
.CK(clk), .RN(n11234), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n307),
.CK(clk), .RN(n11234), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n306),
.CK(clk), .RN(n11234), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n305),
.CK(clk), .RN(n11234), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n304),
.CK(clk), .RN(n11234), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n303),
.CK(clk), .RN(n11234), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n302),
.CK(clk), .RN(n11234), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n301),
.CK(clk), .RN(n11234), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n300),
.CK(clk), .RN(n11234), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n299),
.CK(clk), .RN(n11234), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n298),
.CK(clk), .RN(n11234), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n297),
.CK(clk), .RN(n11235), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n296),
.CK(clk), .RN(n11235), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n295),
.CK(clk), .RN(n11235), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n294),
.CK(clk), .RN(n11235), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n293),
.CK(clk), .RN(n11235), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n292),
.CK(clk), .RN(n11235), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n291),
.CK(clk), .RN(n11235), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n290),
.CK(clk), .RN(n11235), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n289),
.CK(clk), .RN(n11235), .Q(final_result_ieee[62]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n287),
.CK(clk), .RN(n11235), .Q(final_result_ieee[63]), .QN(n11224) );
CMPR32X2TS DP_OP_36J35_134_7156_U13 ( .A(S_Oper_A_exp[0]), .B(n10450), .C(
DP_OP_36J35_134_7156_n28), .CO(DP_OP_36J35_134_7156_n12), .S(
Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_36J35_134_7156_U12 ( .A(DP_OP_36J35_134_7156_n27), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J35_134_7156_n12), .CO(
DP_OP_36J35_134_7156_n11), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J35_134_7156_U11 ( .A(DP_OP_36J35_134_7156_n26), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J35_134_7156_n11), .CO(
DP_OP_36J35_134_7156_n10), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J35_134_7156_U10 ( .A(DP_OP_36J35_134_7156_n25), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J35_134_7156_n10), .CO(
DP_OP_36J35_134_7156_n9), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J35_134_7156_U9 ( .A(DP_OP_36J35_134_7156_n24), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J35_134_7156_n9), .CO(
DP_OP_36J35_134_7156_n8), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J35_134_7156_U8 ( .A(DP_OP_36J35_134_7156_n23), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J35_134_7156_n8), .CO(
DP_OP_36J35_134_7156_n7), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J35_134_7156_U7 ( .A(DP_OP_36J35_134_7156_n22), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J35_134_7156_n7), .CO(
DP_OP_36J35_134_7156_n6), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J35_134_7156_U6 ( .A(DP_OP_36J35_134_7156_n21), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J35_134_7156_n6), .CO(
DP_OP_36J35_134_7156_n5), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J35_134_7156_U5 ( .A(DP_OP_36J35_134_7156_n20), .B(
S_Oper_A_exp[8]), .C(DP_OP_36J35_134_7156_n5), .CO(
DP_OP_36J35_134_7156_n4), .S(Exp_module_Data_S[8]) );
CMPR32X2TS DP_OP_36J35_134_7156_U4 ( .A(DP_OP_36J35_134_7156_n19), .B(
S_Oper_A_exp[9]), .C(DP_OP_36J35_134_7156_n4), .CO(
DP_OP_36J35_134_7156_n3), .S(Exp_module_Data_S[9]) );
CMPR32X2TS DP_OP_36J35_134_7156_U3 ( .A(DP_OP_36J35_134_7156_n18), .B(
S_Oper_A_exp[10]), .C(DP_OP_36J35_134_7156_n3), .CO(
DP_OP_36J35_134_7156_n2), .S(Exp_module_Data_S[10]) );
CMPR32X2TS DP_OP_36J35_134_7156_U2 ( .A(n10450), .B(S_Oper_A_exp[11]), .C(
DP_OP_36J35_134_7156_n2), .CO(DP_OP_36J35_134_7156_n1), .S(
Exp_module_Data_S[11]) );
DFFRX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n581), .CK(clk),
.RN(n11235), .Q(zero_flag), .QN(n11223) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n352), .CK(clk), .RN(n11226),
.Q(underflow_flag), .QN(n11208) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n402), .CK(clk),
.RN(n11230), .Q(Sgf_normalized_result[49]), .QN(n11203) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n400), .CK(clk),
.RN(n11236), .Q(Sgf_normalized_result[47]), .QN(n11202) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n398), .CK(clk),
.RN(n11238), .Q(Sgf_normalized_result[45]), .QN(n11201) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n396), .CK(clk),
.RN(n11229), .Q(Sgf_normalized_result[43]), .QN(n11200) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n418), .CK(clk), .RN(n11227), .Q(
FSM_selector_B[1]), .QN(n11199) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n419), .CK(clk), .RN(n11227), .Q(
FSM_selector_B[0]), .QN(n11198) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n394), .CK(clk),
.RN(n11230), .Q(Sgf_normalized_result[41]), .QN(n11197) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n713), .CK(clk), .RN(n286), .Q(
FS_Module_state_reg[0]), .QN(n11196) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n392), .CK(clk),
.RN(n11237), .Q(Sgf_normalized_result[39]), .QN(n11195) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n390), .CK(clk),
.RN(n11237), .Q(Sgf_normalized_result[37]), .QN(n11194) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n388), .CK(clk),
.RN(n11235), .Q(Sgf_normalized_result[35]), .QN(n11193) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n386), .CK(clk),
.RN(n11237), .Q(Sgf_normalized_result[33]), .QN(n11192) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n384), .CK(clk),
.RN(n11235), .Q(Sgf_normalized_result[31]), .QN(n11191) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n382), .CK(clk),
.RN(n11237), .Q(Sgf_normalized_result[29]), .QN(n11190) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n380), .CK(clk),
.RN(n11238), .Q(Sgf_normalized_result[27]), .QN(n11189) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n378), .CK(clk),
.RN(n11238), .Q(Sgf_normalized_result[25]), .QN(n11188) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n376), .CK(clk),
.RN(n11239), .Q(Sgf_normalized_result[23]), .QN(n11187) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n374), .CK(clk),
.RN(n11229), .Q(Sgf_normalized_result[21]), .QN(n11186) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n372), .CK(clk),
.RN(n11230), .Q(Sgf_normalized_result[19]), .QN(n11185) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n370), .CK(clk),
.RN(n11236), .Q(Sgf_normalized_result[17]), .QN(n11184) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n368), .CK(clk),
.RN(n11226), .Q(Sgf_normalized_result[15]), .QN(n11183) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n366), .CK(clk),
.RN(n11237), .Q(Sgf_normalized_result[13]), .QN(n11182) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n364), .CK(clk),
.RN(n11226), .Q(Sgf_normalized_result[11]), .QN(n11181) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n362), .CK(clk),
.RN(n11237), .Q(Sgf_normalized_result[9]), .QN(n11180) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n360), .CK(clk),
.RN(n11241), .Q(Sgf_normalized_result[7]), .QN(n11179) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n358), .CK(clk),
.RN(n11237), .Q(Sgf_normalized_result[5]), .QN(n11178) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n594), .CK(clk), .RN(
n11226), .Q(Op_MY[12]), .QN(n1104) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n591), .CK(clk), .RN(
n11226), .Q(Op_MY[9]), .QN(n1081) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n593), .CK(clk), .RN(
n11226), .Q(Op_MY[11]), .QN(n910) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n585), .CK(clk), .RN(
n11227), .Q(Op_MY[3]), .QN(n1167) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n582), .CK(clk), .RN(
n11227), .Q(Op_MY[0]), .QN(n1157) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n584), .CK(clk), .RN(
n11227), .Q(Op_MY[2]), .QN(n975) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n586), .CK(clk), .RN(
n11227), .Q(Op_MY[4]), .QN(n976) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n587), .CK(clk), .RN(
n11227), .Q(Op_MY[5]), .QN(n957) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n590), .CK(clk), .RN(
n11226), .Q(Op_MY[8]), .QN(n961) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n592), .CK(clk), .RN(
n11226), .Q(Op_MY[10]), .QN(n965) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n588), .CK(clk), .RN(
n11227), .Q(Op_MY[6]), .QN(n966) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n583), .CK(clk), .RN(
n11227), .Q(Op_MY[1]), .QN(n946) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n589), .CK(clk), .RN(
n11226), .Q(Op_MY[7]), .QN(n1059) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n714), .CK(clk), .RN(n286), .Q(
FS_Module_state_reg[3]), .QN(n11176) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n658), .CK(clk), .RN(
n11237), .Q(Op_MX[12]), .QN(n947) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n647), .CK(clk), .RN(
n11231), .Q(Op_MX[1]), .QN(n948) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n651), .CK(clk), .RN(
n11237), .Q(Op_MX[5]), .QN(n951) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n656), .CK(clk), .RN(
n11237), .Q(Op_MX[10]), .QN(n952) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n649), .CK(clk), .RN(
n11237), .Q(Op_MX[3]), .QN(n953) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n654), .CK(clk), .RN(
n11237), .Q(Op_MX[8]), .QN(n954) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n711), .CK(clk), .RN(n286), .Q(
FS_Module_state_reg[2]), .QN(n11175) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n609), .CK(clk), .RN(
n11241), .Q(Op_MY[27]), .QN(n955) );
CMPR42X1TS DP_OP_347J35_131_5122_U323 ( .A(DP_OP_347J35_131_5122_n436), .B(
DP_OP_347J35_131_5122_n456), .C(DP_OP_347J35_131_5122_n449), .D(
DP_OP_347J35_131_5122_n442), .ICI(DP_OP_347J35_131_5122_n422), .S(
DP_OP_347J35_131_5122_n419), .ICO(DP_OP_347J35_131_5122_n417), .CO(
DP_OP_347J35_131_5122_n418) );
CMPR42X1TS DP_OP_347J35_131_5122_U322 ( .A(DP_OP_347J35_131_5122_n455), .B(
DP_OP_347J35_131_5122_n435), .C(DP_OP_347J35_131_5122_n441), .D(
DP_OP_347J35_131_5122_n448), .ICI(DP_OP_347J35_131_5122_n417), .S(
DP_OP_347J35_131_5122_n416), .ICO(DP_OP_347J35_131_5122_n414), .CO(
DP_OP_347J35_131_5122_n415) );
CMPR42X1TS DP_OP_347J35_131_5122_U320 ( .A(DP_OP_347J35_131_5122_n447), .B(
DP_OP_347J35_131_5122_n440), .C(n954), .D(DP_OP_347J35_131_5122_n413),
.ICI(DP_OP_347J35_131_5122_n414), .S(DP_OP_347J35_131_5122_n411),
.ICO(DP_OP_347J35_131_5122_n409), .CO(DP_OP_347J35_131_5122_n410) );
CMPR42X1TS DP_OP_347J35_131_5122_U318 ( .A(DP_OP_347J35_131_5122_n446), .B(
DP_OP_347J35_131_5122_n412), .C(DP_OP_347J35_131_5122_n439), .D(
DP_OP_347J35_131_5122_n408), .ICI(DP_OP_347J35_131_5122_n409), .S(
DP_OP_347J35_131_5122_n406), .ICO(DP_OP_347J35_131_5122_n404), .CO(
DP_OP_347J35_131_5122_n405) );
CMPR42X1TS DP_OP_347J35_131_5122_U317 ( .A(DP_OP_347J35_131_5122_n407), .B(
DP_OP_347J35_131_5122_n438), .C(DP_OP_347J35_131_5122_n434), .D(
DP_OP_347J35_131_5122_n445), .ICI(DP_OP_347J35_131_5122_n404), .S(
DP_OP_347J35_131_5122_n403), .ICO(DP_OP_347J35_131_5122_n401), .CO(
DP_OP_347J35_131_5122_n402) );
CMPR42X1TS DP_OP_347J35_131_5122_U193 ( .A(DP_OP_347J35_131_5122_n291), .B(
DP_OP_347J35_131_5122_n311), .C(DP_OP_347J35_131_5122_n304), .D(
DP_OP_347J35_131_5122_n297), .ICI(DP_OP_347J35_131_5122_n277), .S(
DP_OP_347J35_131_5122_n274), .ICO(DP_OP_347J35_131_5122_n272), .CO(
DP_OP_347J35_131_5122_n273) );
CMPR42X1TS DP_OP_347J35_131_5122_U192 ( .A(DP_OP_347J35_131_5122_n310), .B(
DP_OP_347J35_131_5122_n290), .C(DP_OP_347J35_131_5122_n296), .D(
DP_OP_347J35_131_5122_n303), .ICI(DP_OP_347J35_131_5122_n272), .S(
DP_OP_347J35_131_5122_n271), .ICO(DP_OP_347J35_131_5122_n269), .CO(
DP_OP_347J35_131_5122_n270) );
CMPR42X1TS DP_OP_347J35_131_5122_U190 ( .A(DP_OP_347J35_131_5122_n302), .B(
DP_OP_347J35_131_5122_n295), .C(n948), .D(DP_OP_347J35_131_5122_n268),
.ICI(DP_OP_347J35_131_5122_n269), .S(DP_OP_347J35_131_5122_n266),
.ICO(DP_OP_347J35_131_5122_n264), .CO(DP_OP_347J35_131_5122_n265) );
CMPR42X1TS DP_OP_347J35_131_5122_U188 ( .A(DP_OP_347J35_131_5122_n301), .B(
DP_OP_347J35_131_5122_n267), .C(DP_OP_347J35_131_5122_n294), .D(
DP_OP_347J35_131_5122_n263), .ICI(DP_OP_347J35_131_5122_n264), .S(
DP_OP_347J35_131_5122_n261), .ICO(DP_OP_347J35_131_5122_n259), .CO(
DP_OP_347J35_131_5122_n260) );
CMPR42X1TS DP_OP_347J35_131_5122_U187 ( .A(DP_OP_347J35_131_5122_n262), .B(
DP_OP_347J35_131_5122_n293), .C(DP_OP_347J35_131_5122_n289), .D(
DP_OP_347J35_131_5122_n300), .ICI(DP_OP_347J35_131_5122_n259), .S(
DP_OP_347J35_131_5122_n258), .ICO(DP_OP_347J35_131_5122_n256), .CO(
DP_OP_347J35_131_5122_n257) );
CMPR42X1TS DP_OP_347J35_131_5122_U58 ( .A(DP_OP_347J35_131_5122_n189), .B(
DP_OP_347J35_131_5122_n234), .C(n6744), .D(DP_OP_347J35_131_5122_n233),
.ICI(DP_OP_347J35_131_5122_n126), .S(DP_OP_347J35_131_5122_n123),
.ICO(DP_OP_347J35_131_5122_n121), .CO(DP_OP_347J35_131_5122_n122) );
CMPR42X1TS DP_OP_347J35_131_5122_U55 ( .A(DP_OP_347J35_131_5122_n120), .B(
DP_OP_347J35_131_5122_n121), .C(n6736), .D(DP_OP_347J35_131_5122_n232),
.ICI(DP_OP_347J35_131_5122_n118), .S(DP_OP_347J35_131_5122_n116),
.ICO(DP_OP_347J35_131_5122_n114), .CO(DP_OP_347J35_131_5122_n115) );
CMPR42X1TS DP_OP_347J35_131_5122_U53 ( .A(DP_OP_347J35_131_5122_n119), .B(
DP_OP_347J35_131_5122_n180), .C(DP_OP_347J35_131_5122_n201), .D(
DP_OP_347J35_131_5122_n173), .ICI(DP_OP_347J35_131_5122_n113), .S(
DP_OP_347J35_131_5122_n111), .ICO(DP_OP_347J35_131_5122_n109), .CO(
DP_OP_347J35_131_5122_n110) );
CMPR42X1TS DP_OP_347J35_131_5122_U52 ( .A(DP_OP_347J35_131_5122_n117), .B(
DP_OP_347J35_131_5122_n114), .C(n6728), .D(DP_OP_347J35_131_5122_n231),
.ICI(DP_OP_347J35_131_5122_n115), .S(DP_OP_347J35_131_5122_n108),
.ICO(DP_OP_347J35_131_5122_n106), .CO(DP_OP_347J35_131_5122_n107) );
CMPR42X1TS DP_OP_347J35_131_5122_U49 ( .A(DP_OP_347J35_131_5122_n105), .B(
DP_OP_347J35_131_5122_n109), .C(DP_OP_347J35_131_5122_n200), .D(
DP_OP_347J35_131_5122_n165), .ICI(DP_OP_347J35_131_5122_n230), .S(
DP_OP_347J35_131_5122_n101), .ICO(DP_OP_347J35_131_5122_n99), .CO(
DP_OP_347J35_131_5122_n100) );
CMPR42X1TS DP_OP_347J35_131_5122_U48 ( .A(DP_OP_347J35_131_5122_n103), .B(
DP_OP_347J35_131_5122_n106), .C(n6722), .D(DP_OP_347J35_131_5122_n110),
.ICI(DP_OP_347J35_131_5122_n107), .S(DP_OP_347J35_131_5122_n98), .ICO(
DP_OP_347J35_131_5122_n96), .CO(DP_OP_347J35_131_5122_n97) );
CMPR42X1TS DP_OP_347J35_131_5122_U46 ( .A(DP_OP_347J35_131_5122_n104), .B(
DP_OP_347J35_131_5122_n171), .C(DP_OP_347J35_131_5122_n192), .D(
DP_OP_347J35_131_5122_n164), .ICI(DP_OP_347J35_131_5122_n95), .S(
DP_OP_347J35_131_5122_n93), .ICO(DP_OP_347J35_131_5122_n91), .CO(
DP_OP_347J35_131_5122_n92) );
CMPR42X1TS DP_OP_347J35_131_5122_U45 ( .A(DP_OP_347J35_131_5122_n102), .B(
DP_OP_347J35_131_5122_n99), .C(DP_OP_347J35_131_5122_n199), .D(
DP_OP_347J35_131_5122_n157), .ICI(DP_OP_347J35_131_5122_n229), .S(
DP_OP_347J35_131_5122_n90), .ICO(DP_OP_347J35_131_5122_n88), .CO(
DP_OP_347J35_131_5122_n89) );
CMPR42X1TS DP_OP_347J35_131_5122_U44 ( .A(DP_OP_347J35_131_5122_n96), .B(
n6714), .C(DP_OP_347J35_131_5122_n100), .D(DP_OP_347J35_131_5122_n93),
.ICI(DP_OP_347J35_131_5122_n97), .S(DP_OP_347J35_131_5122_n87), .ICO(
DP_OP_347J35_131_5122_n85), .CO(DP_OP_347J35_131_5122_n86) );
CMPR42X1TS DP_OP_347J35_131_5122_U41 ( .A(DP_OP_347J35_131_5122_n84), .B(
DP_OP_347J35_131_5122_n91), .C(DP_OP_347J35_131_5122_n198), .D(
DP_OP_347J35_131_5122_n149), .ICI(DP_OP_347J35_131_5122_n88), .S(
DP_OP_347J35_131_5122_n80), .ICO(DP_OP_347J35_131_5122_n78), .CO(
DP_OP_347J35_131_5122_n79) );
CMPR42X1TS DP_OP_347J35_131_5122_U40 ( .A(DP_OP_347J35_131_5122_n191), .B(
DP_OP_347J35_131_5122_n156), .C(DP_OP_347J35_131_5122_n82), .D(
DP_OP_347J35_131_5122_n92), .ICI(DP_OP_347J35_131_5122_n134), .S(
DP_OP_347J35_131_5122_n77), .ICO(DP_OP_347J35_131_5122_n75), .CO(
DP_OP_347J35_131_5122_n76) );
CMPR42X1TS DP_OP_347J35_131_5122_U39 ( .A(DP_OP_347J35_131_5122_n228), .B(
DP_OP_347J35_131_5122_n85), .C(DP_OP_347J35_131_5122_n89), .D(
DP_OP_347J35_131_5122_n80), .ICI(DP_OP_347J35_131_5122_n77), .S(
DP_OP_347J35_131_5122_n74), .ICO(DP_OP_347J35_131_5122_n72), .CO(
DP_OP_347J35_131_5122_n73) );
CMPR42X1TS DP_OP_347J35_131_5122_U36 ( .A(DP_OP_347J35_131_5122_n148), .B(
DP_OP_347J35_131_5122_n183), .C(DP_OP_347J35_131_5122_n155), .D(
DP_OP_347J35_131_5122_n71), .ICI(DP_OP_347J35_131_5122_n75), .S(
DP_OP_347J35_131_5122_n67), .ICO(DP_OP_347J35_131_5122_n65), .CO(
DP_OP_347J35_131_5122_n66) );
CMPR42X1TS DP_OP_347J35_131_5122_U35 ( .A(DP_OP_347J35_131_5122_n81), .B(
DP_OP_347J35_131_5122_n78), .C(DP_OP_347J35_131_5122_n69), .D(
DP_OP_347J35_131_5122_n79), .ICI(DP_OP_347J35_131_5122_n67), .S(
DP_OP_347J35_131_5122_n64), .ICO(DP_OP_347J35_131_5122_n62), .CO(
DP_OP_347J35_131_5122_n63) );
CMPR42X1TS DP_OP_347J35_131_5122_U34 ( .A(DP_OP_347J35_131_5122_n76), .B(
DP_OP_347J35_131_5122_n133), .C(DP_OP_347J35_131_5122_n227), .D(
DP_OP_347J35_131_5122_n72), .ICI(DP_OP_347J35_131_5122_n64), .S(
DP_OP_347J35_131_5122_n61), .ICO(DP_OP_347J35_131_5122_n59), .CO(
DP_OP_347J35_131_5122_n60) );
CMPR42X1TS DP_OP_347J35_131_5122_U32 ( .A(DP_OP_347J35_131_5122_n147), .B(
DP_OP_347J35_131_5122_n70), .C(DP_OP_347J35_131_5122_n175), .D(
DP_OP_347J35_131_5122_n154), .ICI(DP_OP_347J35_131_5122_n58), .S(
DP_OP_347J35_131_5122_n56), .ICO(DP_OP_347J35_131_5122_n54), .CO(
DP_OP_347J35_131_5122_n55) );
CMPR42X1TS DP_OP_347J35_131_5122_U31 ( .A(DP_OP_347J35_131_5122_n68), .B(
DP_OP_347J35_131_5122_n65), .C(DP_OP_347J35_131_5122_n62), .D(
DP_OP_347J35_131_5122_n66), .ICI(DP_OP_347J35_131_5122_n56), .S(
DP_OP_347J35_131_5122_n53), .ICO(DP_OP_347J35_131_5122_n51), .CO(
DP_OP_347J35_131_5122_n52) );
CMPR42X1TS DP_OP_347J35_131_5122_U30 ( .A(DP_OP_347J35_131_5122_n59), .B(
DP_OP_347J35_131_5122_n132), .C(DP_OP_347J35_131_5122_n226), .D(
DP_OP_347J35_131_5122_n63), .ICI(DP_OP_347J35_131_5122_n53), .S(
DP_OP_347J35_131_5122_n50), .ICO(DP_OP_347J35_131_5122_n48), .CO(
DP_OP_347J35_131_5122_n49) );
CMPR42X1TS DP_OP_347J35_131_5122_U29 ( .A(DP_OP_347J35_131_5122_n160), .B(
DP_OP_347J35_131_5122_n174), .C(DP_OP_347J35_131_5122_n146), .D(
DP_OP_347J35_131_5122_n167), .ICI(DP_OP_347J35_131_5122_n153), .S(
DP_OP_347J35_131_5122_n47), .ICO(DP_OP_347J35_131_5122_n45), .CO(
DP_OP_347J35_131_5122_n46) );
CMPR42X1TS DP_OP_347J35_131_5122_U28 ( .A(DP_OP_347J35_131_5122_n57), .B(
DP_OP_347J35_131_5122_n54), .C(DP_OP_347J35_131_5122_n55), .D(
DP_OP_347J35_131_5122_n47), .ICI(DP_OP_347J35_131_5122_n51), .S(
DP_OP_347J35_131_5122_n44), .ICO(DP_OP_347J35_131_5122_n42), .CO(
DP_OP_347J35_131_5122_n43) );
CMPR42X1TS DP_OP_347J35_131_5122_U27 ( .A(DP_OP_347J35_131_5122_n52), .B(
DP_OP_347J35_131_5122_n44), .C(DP_OP_347J35_131_5122_n48), .D(
DP_OP_347J35_131_5122_n131), .ICI(DP_OP_347J35_131_5122_n225), .S(
DP_OP_347J35_131_5122_n41), .ICO(DP_OP_347J35_131_5122_n39), .CO(
DP_OP_347J35_131_5122_n40) );
CMPR42X1TS DP_OP_347J35_131_5122_U25 ( .A(DP_OP_347J35_131_5122_n145), .B(
DP_OP_347J35_131_5122_n45), .C(DP_OP_347J35_131_5122_n38), .D(
DP_OP_347J35_131_5122_n46), .ICI(DP_OP_347J35_131_5122_n42), .S(
DP_OP_347J35_131_5122_n36), .ICO(DP_OP_347J35_131_5122_n34), .CO(
DP_OP_347J35_131_5122_n35) );
CMPR42X1TS DP_OP_347J35_131_5122_U24 ( .A(DP_OP_347J35_131_5122_n43), .B(
DP_OP_347J35_131_5122_n36), .C(DP_OP_347J35_131_5122_n39), .D(
DP_OP_347J35_131_5122_n130), .ICI(DP_OP_347J35_131_5122_n224), .S(
DP_OP_347J35_131_5122_n33), .ICO(DP_OP_347J35_131_5122_n31), .CO(
DP_OP_347J35_131_5122_n32) );
CMPR42X1TS DP_OP_347J35_131_5122_U23 ( .A(DP_OP_347J35_131_5122_n158), .B(
DP_OP_347J35_131_5122_n144), .C(DP_OP_347J35_131_5122_n151), .D(
DP_OP_347J35_131_5122_n37), .ICI(DP_OP_347J35_131_5122_n34), .S(
DP_OP_347J35_131_5122_n30), .ICO(DP_OP_347J35_131_5122_n28), .CO(
DP_OP_347J35_131_5122_n29) );
CMPR42X1TS DP_OP_347J35_131_5122_U22 ( .A(DP_OP_347J35_131_5122_n30), .B(
DP_OP_347J35_131_5122_n35), .C(DP_OP_347J35_131_5122_n31), .D(
DP_OP_347J35_131_5122_n129), .ICI(DP_OP_347J35_131_5122_n223), .S(
DP_OP_347J35_131_5122_n27), .ICO(DP_OP_347J35_131_5122_n25), .CO(
DP_OP_347J35_131_5122_n26) );
CMPR42X1TS DP_OP_347J35_131_5122_U20 ( .A(DP_OP_347J35_131_5122_n24), .B(
DP_OP_347J35_131_5122_n29), .C(DP_OP_347J35_131_5122_n25), .D(
DP_OP_347J35_131_5122_n26), .ICI(DP_OP_347J35_131_5122_n128), .S(
DP_OP_347J35_131_5122_n22), .ICO(DP_OP_347J35_131_5122_n20), .CO(
DP_OP_347J35_131_5122_n21) );
AFCSIHCONX2TS DP_OP_338J35_122_4684_U1047 ( .A(DP_OP_338J35_122_4684_n1465),
.B(DP_OP_338J35_122_4684_n1464), .CS(DP_OP_338J35_122_4684_n1308), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .CO0N(DP_OP_338J35_122_4684_n1307), .CO1N(DP_OP_338J35_122_4684_n1306) );
AFCSHCINX2TS DP_OP_338J35_122_4684_U1046 ( .CI1N(DP_OP_338J35_122_4684_n1306), .B(DP_OP_338J35_122_4684_n1462), .A(DP_OP_338J35_122_4684_n1463), .CI0N(
DP_OP_338J35_122_4684_n1307), .CS(DP_OP_338J35_122_4684_n1308), .CO1(
DP_OP_338J35_122_4684_n1304), .CO0(DP_OP_338J35_122_4684_n1305), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]) );
AFCSIHCONX2TS DP_OP_338J35_122_4684_U1044 ( .A(DP_OP_338J35_122_4684_n1461),
.B(DP_OP_338J35_122_4684_n1460), .CS(DP_OP_338J35_122_4684_n1303), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .CO0N(DP_OP_338J35_122_4684_n1302), .CO1N(DP_OP_338J35_122_4684_n1301) );
AFCSHCINX2TS DP_OP_338J35_122_4684_U1043 ( .CI1N(DP_OP_338J35_122_4684_n1301), .B(DP_OP_338J35_122_4684_n1458), .A(DP_OP_338J35_122_4684_n1459), .CI0N(
DP_OP_338J35_122_4684_n1302), .CS(DP_OP_338J35_122_4684_n1303), .CO1(
DP_OP_338J35_122_4684_n1299), .CO0(DP_OP_338J35_122_4684_n1300), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]) );
AFCSHCONX2TS DP_OP_338J35_122_4684_U1042 ( .B(DP_OP_338J35_122_4684_n1457),
.A(DP_OP_338J35_122_4684_n1456), .CI0(DP_OP_338J35_122_4684_n1300),
.CI1(DP_OP_338J35_122_4684_n1299), .CS(DP_OP_338J35_122_4684_n1303),
.S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .CO0N(DP_OP_338J35_122_4684_n1298), .CO1N(DP_OP_338J35_122_4684_n1297) );
AFCSIHCONX2TS DP_OP_338J35_122_4684_U1040 ( .A(DP_OP_338J35_122_4684_n1455),
.B(DP_OP_338J35_122_4684_n1454), .CS(DP_OP_338J35_122_4684_n1286), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .CO0N(DP_OP_338J35_122_4684_n1295), .CO1N(DP_OP_338J35_122_4684_n1294) );
AFCSHCINX2TS DP_OP_338J35_122_4684_U1039 ( .CI1N(DP_OP_338J35_122_4684_n1294), .B(DP_OP_338J35_122_4684_n1452), .A(DP_OP_338J35_122_4684_n1453), .CI0N(
DP_OP_338J35_122_4684_n1295), .CS(DP_OP_338J35_122_4684_n1286), .CO1(
DP_OP_338J35_122_4684_n1292), .CO0(DP_OP_338J35_122_4684_n1293), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]) );
AFCSHCONX2TS DP_OP_338J35_122_4684_U1038 ( .B(DP_OP_338J35_122_4684_n1450),
.A(DP_OP_338J35_122_4684_n1451), .CI0(DP_OP_338J35_122_4684_n1293),
.CI1(DP_OP_338J35_122_4684_n1292), .CS(DP_OP_338J35_122_4684_n1286),
.S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .CO0N(DP_OP_338J35_122_4684_n1291), .CO1N(DP_OP_338J35_122_4684_n1290) );
AFCSIHCONX2TS DP_OP_338J35_122_4684_U12 ( .A(DP_OP_338J35_122_4684_n116),
.B(DP_OP_338J35_122_4684_n97), .CS(DP_OP_338J35_122_4684_n20), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .CO0N(DP_OP_338J35_122_4684_n19), .CO1N(DP_OP_338J35_122_4684_n18) );
AFCSHCINX2TS DP_OP_338J35_122_4684_U11 ( .CI1N(DP_OP_338J35_122_4684_n18),
.B(DP_OP_338J35_122_4684_n79), .A(DP_OP_338J35_122_4684_n96), .CI0N(
DP_OP_338J35_122_4684_n19), .CS(DP_OP_338J35_122_4684_n20), .CO1(
DP_OP_338J35_122_4684_n16), .CO0(DP_OP_338J35_122_4684_n17), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
AFCSIHCONX2TS DP_OP_338J35_122_4684_U5 ( .A(DP_OP_338J35_122_4684_n35), .B(
DP_OP_338J35_122_4684_n40), .CS(DP_OP_338J35_122_4684_n8), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .CO0N(DP_OP_338J35_122_4684_n7), .CO1N(DP_OP_338J35_122_4684_n6) );
AFCSIHCONX2TS DP_OP_345J35_129_3436_U12 ( .A(DP_OP_345J35_129_3436_n116),
.B(DP_OP_345J35_129_3436_n97), .CS(DP_OP_345J35_129_3436_n20), .S(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[10]),
.CO0N(DP_OP_345J35_129_3436_n19), .CO1N(DP_OP_345J35_129_3436_n18) );
AFCSHCINX2TS DP_OP_345J35_129_3436_U11 ( .CI1N(DP_OP_345J35_129_3436_n18),
.B(DP_OP_345J35_129_3436_n79), .A(DP_OP_345J35_129_3436_n96), .CI0N(
DP_OP_345J35_129_3436_n19), .CS(DP_OP_345J35_129_3436_n20), .CO1(
DP_OP_345J35_129_3436_n16), .CO0(DP_OP_345J35_129_3436_n17), .S(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[11])
);
AFCSIHCONX2TS DP_OP_345J35_129_3436_U9 ( .A(DP_OP_345J35_129_3436_n78), .B(
DP_OP_345J35_129_3436_n63), .CS(DP_OP_345J35_129_3436_n15), .S(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[12]),
.CO0N(DP_OP_345J35_129_3436_n14), .CO1N(DP_OP_345J35_129_3436_n13) );
AFCSHCINX2TS DP_OP_345J35_129_3436_U8 ( .CI1N(DP_OP_345J35_129_3436_n13),
.B(DP_OP_345J35_129_3436_n51), .A(DP_OP_345J35_129_3436_n62), .CI0N(
DP_OP_345J35_129_3436_n14), .CS(DP_OP_345J35_129_3436_n15), .CO1(
DP_OP_345J35_129_3436_n11), .CO0(DP_OP_345J35_129_3436_n12), .S(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[13])
);
AFCSHCONX2TS DP_OP_345J35_129_3436_U7 ( .B(DP_OP_345J35_129_3436_n50), .A(
DP_OP_345J35_129_3436_n41), .CI0(DP_OP_345J35_129_3436_n12), .CI1(
DP_OP_345J35_129_3436_n11), .CS(DP_OP_345J35_129_3436_n15), .S(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[14]),
.CO0N(DP_OP_345J35_129_3436_n10), .CO1N(DP_OP_345J35_129_3436_n9) );
AFCSIHCONX2TS DP_OP_345J35_129_3436_U5 ( .A(DP_OP_345J35_129_3436_n35), .B(
DP_OP_345J35_129_3436_n40), .CS(DP_OP_345J35_129_3436_n8), .S(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[15]),
.CO0N(DP_OP_345J35_129_3436_n7), .CO1N(DP_OP_345J35_129_3436_n6) );
AFCSIHCONX2TS add_x_87_U14 ( .A(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[4]), .B(Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[12]),
.CS(add_x_87_n21), .S(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[20]), .CO0N(
add_x_87_n20), .CO1N(add_x_87_n19) );
AFCSHCINX2TS add_x_87_U13 ( .CI1N(add_x_87_n19), .B(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[13]),
.A(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[5]), .CI0N(add_x_87_n20), .CS(add_x_87_n21), .CO1(add_x_87_n17), .CO0(
add_x_87_n18), .S(Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[21]) );
AFCSIHCONX2TS add_x_87_U11 ( .A(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[6]), .B(Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[14]),
.CS(add_x_87_n16), .S(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[22]), .CO0N(
add_x_87_n15), .CO1N(add_x_87_n14) );
AFCSHCINX2TS add_x_87_U10 ( .CI1N(add_x_87_n14), .B(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[15]),
.A(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[7]), .CI0N(add_x_87_n15), .CS(add_x_87_n16), .CO1(add_x_87_n12), .CO0(
add_x_87_n13), .S(Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[23]) );
AFCSIHCONX2TS add_x_87_U8 ( .A(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[8]), .B(Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[16]),
.CS(add_x_87_n11), .S(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[24]), .CO0N(
add_x_87_n10), .CO1N(add_x_87_n9) );
AFCSHCINX2TS add_x_87_U7 ( .CI1N(add_x_87_n9), .B(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[17]),
.A(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[9]), .CI0N(add_x_87_n10), .CS(add_x_87_n11), .CO1(add_x_87_n7), .CO0(add_x_87_n8),
.S(Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[25]) );
AFCSHCONX2TS add_x_87_U6 ( .B(n1153), .A(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[10]), .CI0(add_x_87_n8), .CI1(add_x_87_n7), .CS(add_x_87_n11), .S(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[26]), .CO0N(
add_x_87_n6), .CO1N(add_x_87_n5) );
AFCSIHCONX2TS DP_OP_344J35_128_4078_U30 ( .A(DP_OP_344J35_128_4078_n116),
.B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[1]), .CS(DP_OP_344J35_128_4078_n40), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[1]), .CO0N(
DP_OP_344J35_128_4078_n39), .CO1N(DP_OP_344J35_128_4078_n38) );
AFCSHCINX2TS DP_OP_344J35_128_4078_U29 ( .CI1N(DP_OP_344J35_128_4078_n38),
.B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[2]), .A(DP_OP_344J35_128_4078_n114), .CI0N(DP_OP_344J35_128_4078_n39), .CS(
DP_OP_344J35_128_4078_n40), .CO1(DP_OP_344J35_128_4078_n36), .CO0(
DP_OP_344J35_128_4078_n37), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[2]) );
AFCSIHCONX2TS DP_OP_344J35_128_4078_U27 ( .A(DP_OP_344J35_128_4078_n112),
.B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[3]), .CS(DP_OP_344J35_128_4078_n35), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[3]), .CO0N(
DP_OP_344J35_128_4078_n34), .CO1N(DP_OP_344J35_128_4078_n33) );
AFCSHCINX2TS DP_OP_344J35_128_4078_U26 ( .CI1N(DP_OP_344J35_128_4078_n33),
.B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[4]), .A(DP_OP_344J35_128_4078_n110), .CI0N(DP_OP_344J35_128_4078_n34), .CS(
DP_OP_344J35_128_4078_n35), .CO1(DP_OP_344J35_128_4078_n31), .CO0(
DP_OP_344J35_128_4078_n32), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[4]) );
AFCSHCONX2TS DP_OP_344J35_128_4078_U25 ( .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[5]), .A(DP_OP_344J35_128_4078_n108), .CI0(DP_OP_344J35_128_4078_n32), .CI1(
DP_OP_344J35_128_4078_n31), .CS(DP_OP_344J35_128_4078_n35), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[5]), .CO0N(
DP_OP_344J35_128_4078_n30), .CO1N(DP_OP_344J35_128_4078_n29) );
AFCSIHCONX2TS DP_OP_344J35_128_4078_U7 ( .A(DP_OP_344J35_128_4078_n58), .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_S_B[15]), .CS(DP_OP_344J35_128_4078_n12), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[22]), .CO0N(
DP_OP_344J35_128_4078_n11), .CO1N(DP_OP_344J35_128_4078_n10) );
AFCSHCINX2TS DP_OP_344J35_128_4078_U6 ( .CI1N(DP_OP_344J35_128_4078_n10),
.B(DP_OP_344J35_128_4078_n57), .A(DP_OP_344J35_128_4078_n53), .CI0N(
DP_OP_344J35_128_4078_n11), .CS(DP_OP_344J35_128_4078_n12), .CO1(
DP_OP_344J35_128_4078_n8), .CO0(DP_OP_344J35_128_4078_n9), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[23]) );
AFCSIHCONX2TS DP_OP_344J35_128_4078_U4 ( .A(DP_OP_344J35_128_4078_n49), .B(
DP_OP_344J35_128_4078_n52), .CS(DP_OP_344J35_128_4078_n1), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[24]), .CO0N(
DP_OP_344J35_128_4078_n7), .CO1N(DP_OP_344J35_128_4078_n6) );
AFCSHCINX2TS DP_OP_344J35_128_4078_U3 ( .CI1N(DP_OP_344J35_128_4078_n6), .B(
DP_OP_344J35_128_4078_n45), .A(DP_OP_344J35_128_4078_n48), .CI0N(
DP_OP_344J35_128_4078_n7), .CS(DP_OP_344J35_128_4078_n1), .CO1(
DP_OP_344J35_128_4078_n4), .CO0(DP_OP_344J35_128_4078_n5), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[25]) );
AFCSHCONX2TS DP_OP_344J35_128_4078_U2 ( .B(DP_OP_344J35_128_4078_n44), .A(
DP_OP_344J35_128_4078_n43), .CI0(DP_OP_344J35_128_4078_n5), .CI1(
DP_OP_344J35_128_4078_n4), .CS(DP_OP_344J35_128_4078_n1), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[26]), .CO0N(
DP_OP_344J35_128_4078_n3), .CO1N(DP_OP_344J35_128_4078_n2) );
AFCSHCINX2TS DP_OP_344J35_128_4078_U1 ( .CI1N(DP_OP_344J35_128_4078_n2), .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[13]), .A(DP_OP_344J35_128_4078_n41), .CI0N(DP_OP_344J35_128_4078_n3), .CS(
DP_OP_344J35_128_4078_n1), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[27]) );
CMPR42X1TS DP_OP_341J35_125_6458_U337 ( .A(DP_OP_341J35_125_6458_n448), .B(
DP_OP_341J35_125_6458_n468), .C(DP_OP_341J35_125_6458_n461), .D(
DP_OP_341J35_125_6458_n454), .ICI(DP_OP_341J35_125_6458_n434), .S(
DP_OP_341J35_125_6458_n431), .ICO(DP_OP_341J35_125_6458_n429), .CO(
DP_OP_341J35_125_6458_n430) );
CMPR42X1TS DP_OP_341J35_125_6458_U336 ( .A(DP_OP_341J35_125_6458_n467), .B(
DP_OP_341J35_125_6458_n447), .C(DP_OP_341J35_125_6458_n453), .D(
DP_OP_341J35_125_6458_n460), .ICI(DP_OP_341J35_125_6458_n429), .S(
DP_OP_341J35_125_6458_n428), .ICO(DP_OP_341J35_125_6458_n426), .CO(
DP_OP_341J35_125_6458_n427) );
CMPR42X1TS DP_OP_341J35_125_6458_U334 ( .A(DP_OP_341J35_125_6458_n459), .B(
DP_OP_341J35_125_6458_n452), .C(DP_OP_341J35_125_6458_n466), .D(
DP_OP_341J35_125_6458_n425), .ICI(DP_OP_341J35_125_6458_n426), .S(
DP_OP_341J35_125_6458_n423), .ICO(DP_OP_341J35_125_6458_n421), .CO(
DP_OP_341J35_125_6458_n422) );
CMPR42X1TS DP_OP_341J35_125_6458_U332 ( .A(DP_OP_341J35_125_6458_n458), .B(
DP_OP_341J35_125_6458_n424), .C(DP_OP_341J35_125_6458_n451), .D(
DP_OP_341J35_125_6458_n420), .ICI(DP_OP_341J35_125_6458_n421), .S(
DP_OP_341J35_125_6458_n418), .ICO(DP_OP_341J35_125_6458_n416), .CO(
DP_OP_341J35_125_6458_n417) );
CMPR42X1TS DP_OP_341J35_125_6458_U331 ( .A(DP_OP_341J35_125_6458_n419), .B(
DP_OP_341J35_125_6458_n450), .C(DP_OP_341J35_125_6458_n446), .D(
DP_OP_341J35_125_6458_n457), .ICI(DP_OP_341J35_125_6458_n416), .S(
DP_OP_341J35_125_6458_n415), .ICO(DP_OP_341J35_125_6458_n413), .CO(
DP_OP_341J35_125_6458_n414) );
CMPR42X1TS DP_OP_341J35_125_6458_U193 ( .A(DP_OP_341J35_125_6458_n305), .B(
DP_OP_341J35_125_6458_n291), .C(DP_OP_341J35_125_6458_n311), .D(
DP_OP_341J35_125_6458_n276), .ICI(DP_OP_341J35_125_6458_n298), .S(
DP_OP_341J35_125_6458_n273), .ICO(DP_OP_341J35_125_6458_n271), .CO(
DP_OP_341J35_125_6458_n272) );
CMPR42X1TS DP_OP_341J35_125_6458_U192 ( .A(DP_OP_341J35_125_6458_n310), .B(
DP_OP_341J35_125_6458_n304), .C(DP_OP_341J35_125_6458_n290), .D(
DP_OP_341J35_125_6458_n297), .ICI(DP_OP_341J35_125_6458_n271), .S(
DP_OP_341J35_125_6458_n270), .ICO(DP_OP_341J35_125_6458_n268), .CO(
DP_OP_341J35_125_6458_n269) );
CMPR42X1TS DP_OP_341J35_125_6458_U190 ( .A(DP_OP_341J35_125_6458_n267), .B(
DP_OP_341J35_125_6458_n303), .C(DP_OP_341J35_125_6458_n289), .D(
DP_OP_341J35_125_6458_n296), .ICI(DP_OP_341J35_125_6458_n268), .S(
DP_OP_341J35_125_6458_n266), .ICO(DP_OP_341J35_125_6458_n264), .CO(
DP_OP_341J35_125_6458_n265) );
CMPR42X1TS DP_OP_341J35_125_6458_U188 ( .A(DP_OP_341J35_125_6458_n267), .B(
DP_OP_341J35_125_6458_n302), .C(DP_OP_341J35_125_6458_n288), .D(
DP_OP_341J35_125_6458_n295), .ICI(DP_OP_341J35_125_6458_n264), .S(
DP_OP_341J35_125_6458_n261), .ICO(DP_OP_341J35_125_6458_n259), .CO(
DP_OP_341J35_125_6458_n260) );
CMPR42X1TS DP_OP_341J35_125_6458_U187 ( .A(DP_OP_341J35_125_6458_n262), .B(
DP_OP_341J35_125_6458_n301), .C(DP_OP_341J35_125_6458_n287), .D(
DP_OP_341J35_125_6458_n294), .ICI(DP_OP_341J35_125_6458_n259), .S(
DP_OP_341J35_125_6458_n258), .ICO(DP_OP_341J35_125_6458_n256), .CO(
DP_OP_341J35_125_6458_n257) );
CMPR42X1TS DP_OP_341J35_125_6458_U58 ( .A(DP_OP_341J35_125_6458_n203), .B(
DP_OP_341J35_125_6458_n189), .C(DP_OP_341J35_125_6458_n126), .D(
DP_OP_341J35_125_6458_n125), .ICI(DP_OP_341J35_125_6458_n234), .S(
DP_OP_341J35_125_6458_n123), .ICO(DP_OP_341J35_125_6458_n121), .CO(
DP_OP_341J35_125_6458_n122) );
CMPR42X1TS DP_OP_341J35_125_6458_U55 ( .A(DP_OP_341J35_125_6458_n181), .B(
DP_OP_341J35_125_6458_n121), .C(DP_OP_341J35_125_6458_n120), .D(
DP_OP_341J35_125_6458_n118), .ICI(DP_OP_341J35_125_6458_n122), .S(
DP_OP_341J35_125_6458_n116), .ICO(DP_OP_341J35_125_6458_n114), .CO(
DP_OP_341J35_125_6458_n115) );
CMPR42X1TS DP_OP_341J35_125_6458_U53 ( .A(DP_OP_341J35_125_6458_n119), .B(
DP_OP_341J35_125_6458_n180), .C(DP_OP_341J35_125_6458_n194), .D(
DP_OP_341J35_125_6458_n113), .ICI(DP_OP_341J35_125_6458_n114), .S(
DP_OP_341J35_125_6458_n111), .ICO(DP_OP_341J35_125_6458_n109), .CO(
DP_OP_341J35_125_6458_n110) );
CMPR42X1TS DP_OP_341J35_125_6458_U52 ( .A(DP_OP_341J35_125_6458_n117), .B(
DP_OP_341J35_125_6458_n201), .C(DP_OP_341J35_125_6458_n173), .D(
DP_OP_341J35_125_6458_n111), .ICI(DP_OP_341J35_125_6458_n115), .S(
DP_OP_341J35_125_6458_n108), .ICO(DP_OP_341J35_125_6458_n106), .CO(
DP_OP_341J35_125_6458_n107) );
CMPR42X1TS DP_OP_341J35_125_6458_U49 ( .A(DP_OP_341J35_125_6458_n193), .B(
DP_OP_341J35_125_6458_n172), .C(DP_OP_341J35_125_6458_n105), .D(
DP_OP_341J35_125_6458_n106), .ICI(DP_OP_341J35_125_6458_n110), .S(
DP_OP_341J35_125_6458_n101), .ICO(DP_OP_341J35_125_6458_n99), .CO(
DP_OP_341J35_125_6458_n100) );
CMPR42X1TS DP_OP_341J35_125_6458_U48 ( .A(DP_OP_341J35_125_6458_n103), .B(
DP_OP_341J35_125_6458_n165), .C(DP_OP_341J35_125_6458_n200), .D(
DP_OP_341J35_125_6458_n101), .ICI(DP_OP_341J35_125_6458_n107), .S(
DP_OP_341J35_125_6458_n98), .ICO(DP_OP_341J35_125_6458_n96), .CO(
DP_OP_341J35_125_6458_n97) );
CMPR42X1TS DP_OP_341J35_125_6458_U46 ( .A(DP_OP_341J35_125_6458_n104), .B(
DP_OP_341J35_125_6458_n171), .C(DP_OP_341J35_125_6458_n185), .D(
DP_OP_341J35_125_6458_n95), .ICI(DP_OP_341J35_125_6458_n99), .S(
DP_OP_341J35_125_6458_n93), .ICO(DP_OP_341J35_125_6458_n91), .CO(
DP_OP_341J35_125_6458_n92) );
CMPR42X1TS DP_OP_341J35_125_6458_U45 ( .A(DP_OP_341J35_125_6458_n102), .B(
DP_OP_341J35_125_6458_n192), .C(DP_OP_341J35_125_6458_n164), .D(
DP_OP_341J35_125_6458_n96), .ICI(DP_OP_341J35_125_6458_n199), .S(
DP_OP_341J35_125_6458_n90), .ICO(DP_OP_341J35_125_6458_n88), .CO(
DP_OP_341J35_125_6458_n89) );
CMPR42X1TS DP_OP_341J35_125_6458_U44 ( .A(DP_OP_341J35_125_6458_n157), .B(
DP_OP_341J35_125_6458_n93), .C(DP_OP_341J35_125_6458_n100), .D(
DP_OP_341J35_125_6458_n90), .ICI(DP_OP_341J35_125_6458_n97), .S(
DP_OP_341J35_125_6458_n87), .ICO(DP_OP_341J35_125_6458_n85), .CO(
DP_OP_341J35_125_6458_n86) );
CMPR42X1TS DP_OP_341J35_125_6458_U41 ( .A(DP_OP_341J35_125_6458_n84), .B(
DP_OP_341J35_125_6458_n184), .C(DP_OP_341J35_125_6458_n163), .D(
DP_OP_341J35_125_6458_n82), .ICI(DP_OP_341J35_125_6458_n156), .S(
DP_OP_341J35_125_6458_n80), .ICO(DP_OP_341J35_125_6458_n78), .CO(
DP_OP_341J35_125_6458_n79) );
CMPR42X1TS DP_OP_341J35_125_6458_U40 ( .A(DP_OP_341J35_125_6458_n92), .B(
DP_OP_341J35_125_6458_n149), .C(DP_OP_341J35_125_6458_n88), .D(
DP_OP_341J35_125_6458_n191), .ICI(DP_OP_341J35_125_6458_n85), .S(
DP_OP_341J35_125_6458_n77), .ICO(DP_OP_341J35_125_6458_n75), .CO(
DP_OP_341J35_125_6458_n76) );
CMPR42X1TS DP_OP_341J35_125_6458_U39 ( .A(DP_OP_341J35_125_6458_n198), .B(
DP_OP_341J35_125_6458_n80), .C(DP_OP_341J35_125_6458_n89), .D(
DP_OP_341J35_125_6458_n77), .ICI(DP_OP_341J35_125_6458_n86), .S(
DP_OP_341J35_125_6458_n74), .ICO(DP_OP_341J35_125_6458_n72), .CO(
DP_OP_341J35_125_6458_n73) );
CMPR42X1TS DP_OP_341J35_125_6458_U36 ( .A(DP_OP_341J35_125_6458_n176), .B(
DP_OP_341J35_125_6458_n81), .C(DP_OP_341J35_125_6458_n190), .D(
DP_OP_341J35_125_6458_n148), .ICI(DP_OP_341J35_125_6458_n69), .S(
DP_OP_341J35_125_6458_n67), .ICO(DP_OP_341J35_125_6458_n65), .CO(
DP_OP_341J35_125_6458_n66) );
CMPR42X1TS DP_OP_341J35_125_6458_U35 ( .A(DP_OP_341J35_125_6458_n78), .B(
DP_OP_341J35_125_6458_n155), .C(DP_OP_341J35_125_6458_n183), .D(
DP_OP_341J35_125_6458_n75), .ICI(DP_OP_341J35_125_6458_n79), .S(
DP_OP_341J35_125_6458_n64), .ICO(DP_OP_341J35_125_6458_n62), .CO(
DP_OP_341J35_125_6458_n63) );
CMPR42X1TS DP_OP_341J35_125_6458_U34 ( .A(DP_OP_341J35_125_6458_n67), .B(
DP_OP_341J35_125_6458_n76), .C(DP_OP_341J35_125_6458_n72), .D(
DP_OP_341J35_125_6458_n64), .ICI(DP_OP_341J35_125_6458_n73), .S(
DP_OP_341J35_125_6458_n61), .ICO(DP_OP_341J35_125_6458_n59), .CO(
DP_OP_341J35_125_6458_n60) );
CMPR42X1TS DP_OP_341J35_125_6458_U32 ( .A(DP_OP_341J35_125_6458_n168), .B(
DP_OP_341J35_125_6458_n147), .C(DP_OP_341J35_125_6458_n182), .D(
DP_OP_341J35_125_6458_n154), .ICI(DP_OP_341J35_125_6458_n68), .S(
DP_OP_341J35_125_6458_n56), .ICO(DP_OP_341J35_125_6458_n54), .CO(
DP_OP_341J35_125_6458_n55) );
CMPR42X1TS DP_OP_341J35_125_6458_U31 ( .A(DP_OP_341J35_125_6458_n175), .B(
DP_OP_341J35_125_6458_n58), .C(DP_OP_341J35_125_6458_n65), .D(
DP_OP_341J35_125_6458_n62), .ICI(DP_OP_341J35_125_6458_n66), .S(
DP_OP_341J35_125_6458_n53), .ICO(DP_OP_341J35_125_6458_n51), .CO(
DP_OP_341J35_125_6458_n52) );
CMPR42X1TS DP_OP_341J35_125_6458_U30 ( .A(DP_OP_341J35_125_6458_n56), .B(
DP_OP_341J35_125_6458_n63), .C(DP_OP_341J35_125_6458_n53), .D(
DP_OP_341J35_125_6458_n59), .ICI(DP_OP_341J35_125_6458_n60), .S(
DP_OP_341J35_125_6458_n50), .ICO(DP_OP_341J35_125_6458_n48), .CO(
DP_OP_341J35_125_6458_n49) );
CMPR42X1TS DP_OP_341J35_125_6458_U29 ( .A(DP_OP_341J35_125_6458_n131), .B(
DP_OP_341J35_125_6458_n160), .C(DP_OP_341J35_125_6458_n146), .D(
DP_OP_341J35_125_6458_n174), .ICI(DP_OP_341J35_125_6458_n153), .S(
DP_OP_341J35_125_6458_n47), .ICO(DP_OP_341J35_125_6458_n45), .CO(
DP_OP_341J35_125_6458_n46) );
CMPR42X1TS DP_OP_341J35_125_6458_U28 ( .A(DP_OP_341J35_125_6458_n167), .B(
DP_OP_341J35_125_6458_n57), .C(DP_OP_341J35_125_6458_n54), .D(
DP_OP_341J35_125_6458_n51), .ICI(DP_OP_341J35_125_6458_n55), .S(
DP_OP_341J35_125_6458_n44), .ICO(DP_OP_341J35_125_6458_n42), .CO(
DP_OP_341J35_125_6458_n43) );
CMPR42X1TS DP_OP_341J35_125_6458_U27 ( .A(DP_OP_341J35_125_6458_n47), .B(
DP_OP_341J35_125_6458_n52), .C(DP_OP_341J35_125_6458_n44), .D(
DP_OP_341J35_125_6458_n48), .ICI(DP_OP_341J35_125_6458_n49), .S(
DP_OP_341J35_125_6458_n41), .ICO(DP_OP_341J35_125_6458_n39), .CO(
DP_OP_341J35_125_6458_n40) );
CMPR42X1TS DP_OP_341J35_125_6458_U25 ( .A(DP_OP_341J35_125_6458_n159), .B(
DP_OP_341J35_125_6458_n152), .C(DP_OP_341J35_125_6458_n45), .D(
DP_OP_341J35_125_6458_n38), .ICI(DP_OP_341J35_125_6458_n42), .S(
DP_OP_341J35_125_6458_n36), .ICO(DP_OP_341J35_125_6458_n34), .CO(
DP_OP_341J35_125_6458_n35) );
CMPR42X1TS DP_OP_341J35_125_6458_U24 ( .A(DP_OP_341J35_125_6458_n46), .B(
DP_OP_341J35_125_6458_n43), .C(DP_OP_341J35_125_6458_n36), .D(
DP_OP_341J35_125_6458_n39), .ICI(DP_OP_341J35_125_6458_n40), .S(
DP_OP_341J35_125_6458_n33), .ICO(DP_OP_341J35_125_6458_n31), .CO(
DP_OP_341J35_125_6458_n32) );
CMPR42X1TS DP_OP_341J35_125_6458_U23 ( .A(DP_OP_341J35_125_6458_n129), .B(
DP_OP_341J35_125_6458_n144), .C(DP_OP_341J35_125_6458_n158), .D(
DP_OP_341J35_125_6458_n151), .ICI(DP_OP_341J35_125_6458_n37), .S(
DP_OP_341J35_125_6458_n30), .ICO(DP_OP_341J35_125_6458_n28), .CO(
DP_OP_341J35_125_6458_n29) );
CMPR42X1TS DP_OP_341J35_125_6458_U22 ( .A(DP_OP_341J35_125_6458_n34), .B(
DP_OP_341J35_125_6458_n30), .C(DP_OP_341J35_125_6458_n35), .D(
DP_OP_341J35_125_6458_n31), .ICI(DP_OP_341J35_125_6458_n32), .S(
DP_OP_341J35_125_6458_n27), .ICO(DP_OP_341J35_125_6458_n25), .CO(
DP_OP_341J35_125_6458_n26) );
CMPR42X1TS DP_OP_341J35_125_6458_U20 ( .A(DP_OP_341J35_125_6458_n28), .B(
DP_OP_341J35_125_6458_n24), .C(DP_OP_341J35_125_6458_n29), .D(
DP_OP_341J35_125_6458_n25), .ICI(DP_OP_341J35_125_6458_n26), .S(
DP_OP_341J35_125_6458_n22), .ICO(DP_OP_341J35_125_6458_n20), .CO(
DP_OP_341J35_125_6458_n21) );
DFFSX4TS Operands_load_reg_XMRegister_Q_reg_50_ ( .D(n937), .CK(clk), .SN(
n754), .Q(DP_OP_342J35_126_4270_n852), .QN(Op_MX[50]) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n712), .CK(clk), .RN(n286), .Q(
n11225), .QN(n11248) );
DFFSX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n941), .CK(clk), .SN(
n11239), .Q(DP_OP_346J35_130_4270_n836), .QN(Op_MY[21]) );
DFFSX4TS Operands_load_reg_XMRegister_Q_reg_48_ ( .D(n936), .CK(clk), .SN(
n11249), .Q(DP_OP_342J35_126_4270_n853), .QN(Op_MX[48]) );
DFFSX1TS Adder_M_Add_Subt_Result_Q_reg_52_ ( .D(n11173), .CK(clk), .SN(
n11240), .QN(Add_result[52]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_102_ ( .D(n778), .CK(clk), .SN(
n286), .QN(P_Sgf[102]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_47_ ( .D(n629), .CK(clk), .RN(
n11230), .Q(Op_MY[47]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n652), .CK(clk), .RN(
n11237), .Q(Op_MX[6]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n655), .CK(clk), .RN(
n11237), .Q(Op_MX[9]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n610), .CK(clk), .RN(
n11241), .Q(Op_MY[28]), .QN(n812) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n611), .CK(clk), .RN(
n11241), .Q(Op_MY[29]), .QN(n813) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n612), .CK(clk), .RN(
n11241), .Q(Op_MY[30]), .QN(n810) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n613), .CK(clk), .RN(
n11226), .Q(Op_MY[31]), .QN(n811) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_32_ ( .D(n614), .CK(clk), .RN(
n11241), .Q(Op_MY[32]), .QN(n733) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n671), .CK(clk), .RN(
n11230), .Q(Op_MX[25]), .QN(n988) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_51_ ( .D(n633), .CK(clk), .RN(
n11228), .Q(Op_MY[51]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n607), .CK(clk), .RN(
n11241), .Q(Op_MY[25]), .QN(n1032) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_48_ ( .D(n630), .CK(clk), .RN(
n11236), .Q(Op_MY[48]), .QN(n1148) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n608), .CK(clk), .RN(
n11241), .Q(Op_MY[26]), .QN(n934) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n672), .CK(clk), .RN(
n11230), .Q(Op_MX[26]), .QN(n774) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n599), .CK(clk), .RN(
n11226), .Q(Op_MY[17]), .QN(n766) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n604), .CK(clk), .RN(
n11239), .Q(Op_MY[22]), .QN(n1026) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n662), .CK(clk), .RN(
n11236), .Q(Op_MX[16]), .QN(n837) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_44_ ( .D(n690), .CK(clk), .RN(
n11234), .Q(Op_MX[44]), .QN(n748) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_38_ ( .D(n620), .CK(clk), .RN(
n11227), .Q(Op_MY[38]), .QN(n738) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_34_ ( .D(n616), .CK(clk), .RN(
n11241), .Q(Op_MY[34]), .QN(n739) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_34_ ( .D(n680), .CK(clk), .RN(
n11238), .Q(Op_MX[34]), .QN(n747) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_33_ ( .D(n615), .CK(clk), .RN(
n11241), .Q(Op_MY[33]), .QN(n740) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n673), .CK(clk), .RN(
n11235), .Q(Op_MX[27]), .QN(n744) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_33_ ( .D(n679), .CK(clk), .RN(
n11238), .Q(Op_MX[33]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n659), .CK(clk), .RN(
n11237), .Q(Op_MX[13]), .QN(n737) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_40_ ( .D(n622), .CK(clk), .RN(
n11227), .Q(Op_MY[40]), .QN(n760) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_44_ ( .D(n626), .CK(clk), .RN(
n11229), .Q(Op_MY[44]), .QN(n762) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_45_ ( .D(n627), .CK(clk), .RN(
n11238), .Q(Op_MY[45]), .QN(n764) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n605), .CK(clk), .RN(
n11239), .Q(Op_MY[23]), .QN(n853) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_50_ ( .D(n632), .CK(clk), .RN(
n11233), .Q(Op_MY[50]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n403), .CK(clk),
.RN(n11229), .Q(Sgf_normalized_result[50]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n389), .CK(clk),
.RN(n11231), .Q(Sgf_normalized_result[36]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n393), .CK(clk),
.RN(n11239), .Q(Sgf_normalized_result[40]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n395), .CK(clk),
.RN(n11238), .Q(Sgf_normalized_result[42]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n397), .CK(clk),
.RN(n11236), .Q(Sgf_normalized_result[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n399), .CK(clk),
.RN(n11230), .Q(Sgf_normalized_result[46]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n401), .CK(clk),
.RN(n11229), .Q(Sgf_normalized_result[48]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n361), .CK(clk),
.RN(n11237), .Q(Sgf_normalized_result[8]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n363), .CK(clk),
.RN(n11236), .Q(Sgf_normalized_result[10]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n365), .CK(clk),
.RN(n11231), .Q(Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n367), .CK(clk),
.RN(n11237), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n369), .CK(clk),
.RN(n11236), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n371), .CK(clk),
.RN(n11239), .Q(Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n373), .CK(clk),
.RN(n11230), .Q(Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n375), .CK(clk),
.RN(n11229), .Q(Sgf_normalized_result[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n377), .CK(clk),
.RN(n11238), .Q(Sgf_normalized_result[24]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n379), .CK(clk),
.RN(n11236), .Q(Sgf_normalized_result[26]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n381), .CK(clk),
.RN(n11235), .Q(Sgf_normalized_result[28]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n383), .CK(clk),
.RN(n11239), .Q(Sgf_normalized_result[30]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n385), .CK(clk),
.RN(n11237), .Q(Sgf_normalized_result[32]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n387), .CK(clk),
.RN(n11235), .Q(Sgf_normalized_result[34]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n391), .CK(clk),
.RN(n11237), .Q(Sgf_normalized_result[38]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_68_ ( .D(n489), .CK(clk), .RN(
n11244), .Q(P_Sgf[68]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_57_ ( .D(n703), .CK(clk), .RN(
n754), .Q(Op_MX[57]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n577), .CK(clk), .RN(n11240),
.Q(Add_result[2]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n578), .CK(clk), .RN(n11240),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n575), .CK(clk), .RN(n11240),
.Q(Add_result[4]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_62_ ( .D(n644), .CK(clk), .RN(
n11240), .Q(Op_MY[62]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n571), .CK(clk), .RN(n11234),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n569), .CK(clk), .RN(n11234),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n567), .CK(clk), .RN(n11234),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n565), .CK(clk), .RN(n11240),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n574), .CK(clk), .RN(n11240),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n572), .CK(clk), .RN(n11240),
.Q(Add_result[7]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_69_ ( .D(n490), .CK(clk), .RN(
n11243), .Q(P_Sgf[69]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_70_ ( .D(n491), .CK(clk), .RN(
n11243), .Q(P_Sgf[70]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_71_ ( .D(n492), .CK(clk), .RN(
n11243), .Q(P_Sgf[71]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_72_ ( .D(n493), .CK(clk), .RN(
n11243), .Q(P_Sgf[72]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_73_ ( .D(n494), .CK(clk), .RN(
n11243), .Q(P_Sgf[73]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_74_ ( .D(n495), .CK(clk), .RN(
n11243), .Q(P_Sgf[74]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_75_ ( .D(n496), .CK(clk), .RN(
n11243), .Q(P_Sgf[75]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_76_ ( .D(n497), .CK(clk), .RN(
n11243), .Q(P_Sgf[76]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_77_ ( .D(n498), .CK(clk), .RN(
n11243), .Q(P_Sgf[77]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_78_ ( .D(n499), .CK(clk), .RN(
n11243), .Q(P_Sgf[78]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_79_ ( .D(n500), .CK(clk), .RN(
n11243), .Q(P_Sgf[79]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_80_ ( .D(n501), .CK(clk), .RN(
n11243), .Q(P_Sgf[80]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_81_ ( .D(n502), .CK(clk), .RN(
n11242), .Q(P_Sgf[81]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_60_ ( .D(n642), .CK(clk), .RN(
n11233), .Q(Op_MY[60]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n576), .CK(clk), .RN(n11240),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n573), .CK(clk), .RN(n11240),
.Q(Add_result[6]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_61_ ( .D(n707), .CK(clk), .RN(
n754), .Q(Op_MX[61]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_10_ ( .D(n407), .CK(clk), .RN(n11228),
.Q(exp_oper_result[10]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n409), .CK(clk), .RN(n11228),
.Q(exp_oper_result[8]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n410), .CK(clk), .RN(n11228),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n411), .CK(clk), .RN(n11228),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n413), .CK(clk), .RN(n11228),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n414), .CK(clk), .RN(n11228),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n415), .CK(clk), .RN(n11228),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n416), .CK(clk), .RN(n11227),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n417), .CK(clk), .RN(n11227),
.Q(exp_oper_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_11_ ( .D(n406), .CK(clk), .RN(n11228),
.Q(exp_oper_result[11]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n596), .CK(clk), .RN(
n11226), .Q(Op_MY[14]), .QN(n1034) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n606), .CK(clk), .RN(
n11229), .Q(Op_MY[24]), .QN(n1109) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_36_ ( .D(n618), .CK(clk), .RN(
n11241), .Q(Op_MY[36]), .QN(n734) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_19_ ( .D(n440), .CK(clk), .RN(
n11246), .Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_48_ ( .D(n469), .CK(clk), .RN(
n11243), .Q(P_Sgf[48]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_52_ ( .D(n473), .CK(clk), .RN(
n11244), .Q(P_Sgf[52]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_44_ ( .D(n465), .CK(clk), .RN(
n11247), .Q(P_Sgf[44]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_61_ ( .D(n482), .CK(clk), .RN(
n11244), .Q(P_Sgf[61]), .QN(n11221) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_63_ ( .D(n484), .CK(clk), .RN(
n11246), .Q(P_Sgf[63]), .QN(n11219) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_65_ ( .D(n486), .CK(clk), .RN(
n11247), .Q(P_Sgf[65]), .QN(n11217) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_0_ ( .D(n421), .CK(clk), .RN(
n11246), .Q(P_Sgf[0]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_4_ ( .D(n425), .CK(clk), .RN(
n11245), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_8_ ( .D(n429), .CK(clk), .RN(
n11247), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_12_ ( .D(n433), .CK(clk), .RN(
n11246), .Q(P_Sgf[12]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_20_ ( .D(n441), .CK(clk), .RN(
n11246), .Q(P_Sgf[20]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_24_ ( .D(n445), .CK(clk), .RN(
n11245), .Q(P_Sgf[24]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_28_ ( .D(n449), .CK(clk), .RN(
n11245), .Q(P_Sgf[28]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_32_ ( .D(n453), .CK(clk), .RN(
n11245), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_36_ ( .D(n457), .CK(clk), .RN(
n11242), .Q(P_Sgf[36]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_63_ ( .D(n645), .CK(clk), .RN(
n11231), .Q(Op_MX[63]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_43_ ( .D(n464), .CK(clk), .RN(
n11247), .Q(P_Sgf[43]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n580), .CK(clk),
.RN(n11228), .Q(Sgf_normalized_result[52]), .QN(n11207) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_49_ ( .D(n631), .CK(clk), .RN(
n754), .Q(Op_MY[49]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n601), .CK(clk), .RN(
n11229), .Q(Op_MY[19]), .QN(n768) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_42_ ( .D(n688), .CK(clk), .RN(
n11249), .Q(Op_MX[42]), .QN(n749) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n663), .CK(clk), .RN(
n11230), .Q(Op_MX[17]), .QN(n746) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_51_ ( .D(n697), .CK(clk), .RN(
n754), .Q(Op_MX[51]), .QN(n1024) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_37_ ( .D(n619), .CK(clk), .RN(
n11227), .Q(Op_MY[37]), .QN(n741) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_41_ ( .D(n687), .CK(clk), .RN(
n11249), .Q(Op_MX[41]), .QN(n750) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n676), .CK(clk), .RN(
n11237), .Q(Op_MX[30]), .QN(n742) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_32_ ( .D(n678), .CK(clk), .RN(
n11239), .Q(Op_MX[32]), .QN(n743) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_40_ ( .D(n686), .CK(clk), .RN(
n11249), .Q(Op_MX[40]), .QN(n751) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_36_ ( .D(n682), .CK(clk), .RN(
n11236), .Q(Op_MX[36]), .QN(n745) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n677), .CK(clk), .RN(
n11226), .Q(Op_MX[31]), .QN(n757) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_38_ ( .D(n684), .CK(clk), .RN(
n11249), .Q(Op_MX[38]), .QN(n809) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n674), .CK(clk), .RN(
n11238), .Q(Op_MX[28]), .QN(n758) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n675), .CK(clk), .RN(
n11235), .Q(Op_MX[29]), .QN(n756) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_45_ ( .D(n691), .CK(clk), .RN(
n11234), .QN(n759) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_58_ ( .D(n704), .CK(clk), .RN(
n11238), .Q(Op_MX[58]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_59_ ( .D(n641), .CK(clk), .RN(
n11228), .Q(Op_MY[59]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_62_ ( .D(n708), .CK(clk), .RN(
n754), .Q(Op_MX[62]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_60_ ( .D(n706), .CK(clk), .RN(
n754), .Q(Op_MX[60]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_54_ ( .D(n636), .CK(clk), .RN(
n754), .Q(Op_MY[54]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_57_ ( .D(n639), .CK(clk), .RN(
n11233), .Q(Op_MY[57]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_53_ ( .D(n699), .CK(clk), .RN(
n754), .Q(Op_MX[53]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_52_ ( .D(n698), .CK(clk), .RN(
n754), .Q(Op_MX[52]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n404), .CK(clk),
.RN(n11249), .Q(Sgf_normalized_result[51]), .QN(n11204) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n354), .CK(clk),
.RN(n11226), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n353), .CK(clk),
.RN(n11235), .Q(Sgf_normalized_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n412), .CK(clk), .RN(n11228),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_9_ ( .D(n408), .CK(clk), .RN(n11228),
.Q(exp_oper_result[9]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_52_ ( .D(n634), .CK(clk), .RN(
n11228), .Q(Op_MY[52]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_61_ ( .D(n643), .CK(clk), .RN(
n11240), .Q(Op_MY[61]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n564), .CK(clk), .RN(n11232),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_41_ ( .D(n538), .CK(clk), .RN(n11236),
.Q(Add_result[41]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_39_ ( .D(n540), .CK(clk), .RN(n11230),
.Q(Add_result[39]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_37_ ( .D(n542), .CK(clk), .RN(n11229),
.Q(Add_result[37]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_35_ ( .D(n544), .CK(clk), .RN(n11239),
.Q(Add_result[35]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_33_ ( .D(n546), .CK(clk), .RN(n11238),
.Q(Add_result[33]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_31_ ( .D(n548), .CK(clk), .RN(n11230),
.Q(Add_result[31]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_29_ ( .D(n550), .CK(clk), .RN(n11229),
.Q(Add_result[29]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_27_ ( .D(n552), .CK(clk), .RN(n11238),
.Q(Add_result[27]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_25_ ( .D(n554), .CK(clk), .RN(n11236),
.Q(Add_result[25]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n556), .CK(clk), .RN(n11239),
.Q(Add_result[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n558), .CK(clk), .RN(n11230),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n560), .CK(clk), .RN(n11240),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n562), .CK(clk), .RN(n11232),
.Q(Add_result[17]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_53_ ( .D(n635), .CK(clk), .RN(
n11228), .Q(Op_MY[53]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_46_ ( .D(n533), .CK(clk), .RN(n11239),
.Q(Add_result[46]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_42_ ( .D(n537), .CK(clk), .RN(n11236),
.Q(Add_result[42]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_40_ ( .D(n539), .CK(clk), .RN(n11239),
.Q(Add_result[40]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_38_ ( .D(n541), .CK(clk), .RN(n11230),
.Q(Add_result[38]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_36_ ( .D(n543), .CK(clk), .RN(n11229),
.Q(Add_result[36]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_34_ ( .D(n545), .CK(clk), .RN(n11238),
.Q(Add_result[34]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_32_ ( .D(n547), .CK(clk), .RN(n11236),
.Q(Add_result[32]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_30_ ( .D(n549), .CK(clk), .RN(n11229),
.Q(Add_result[30]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_28_ ( .D(n551), .CK(clk), .RN(n11238),
.Q(Add_result[28]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_26_ ( .D(n553), .CK(clk), .RN(n11236),
.Q(Add_result[26]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_24_ ( .D(n555), .CK(clk), .RN(n11230),
.Q(Add_result[24]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n557), .CK(clk), .RN(n11229),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n559), .CK(clk), .RN(n11239),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n561), .CK(clk), .RN(n11240),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n563), .CK(clk), .RN(n11232),
.Q(Add_result[16]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_50_ ( .D(n471), .CK(clk), .RN(
n11245), .Q(P_Sgf[50]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_49_ ( .D(n470), .CK(clk), .RN(
n11242), .Q(P_Sgf[49]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_51_ ( .D(n472), .CK(clk), .RN(
n11247), .Q(P_Sgf[51]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_59_ ( .D(n480), .CK(clk), .RN(
n11244), .Q(P_Sgf[59]), .QN(n11209) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_58_ ( .D(n479), .CK(clk), .RN(
n11244), .Q(P_Sgf[58]), .QN(n11210) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_57_ ( .D(n478), .CK(clk), .RN(
n11244), .Q(P_Sgf[57]), .QN(n11211) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_56_ ( .D(n477), .CK(clk), .RN(
n11244), .Q(P_Sgf[56]), .QN(n11212) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_55_ ( .D(n476), .CK(clk), .RN(
n11244), .Q(P_Sgf[55]), .QN(n11213) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_54_ ( .D(n475), .CK(clk), .RN(
n11244), .Q(P_Sgf[54]), .QN(n11214) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_53_ ( .D(n474), .CK(clk), .RN(
n11244), .Q(P_Sgf[53]), .QN(n11215) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_46_ ( .D(n467), .CK(clk), .RN(
n11247), .Q(P_Sgf[46]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_66_ ( .D(n487), .CK(clk), .RN(
n11243), .Q(P_Sgf[66]), .QN(n11216) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_64_ ( .D(n485), .CK(clk), .RN(
n11242), .Q(P_Sgf[64]), .QN(n11218) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_62_ ( .D(n483), .CK(clk), .RN(
n11244), .Q(P_Sgf[62]), .QN(n11220) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_60_ ( .D(n481), .CK(clk), .RN(
n11244), .Q(P_Sgf[60]), .QN(n11222) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_45_ ( .D(n466), .CK(clk), .RN(
n11247), .Q(P_Sgf[45]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_47_ ( .D(n468), .CK(clk), .RN(
n11247), .Q(P_Sgf[47]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_38_ ( .D(n459), .CK(clk), .RN(
n11245), .Q(P_Sgf[38]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_34_ ( .D(n455), .CK(clk), .RN(
n11245), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_30_ ( .D(n451), .CK(clk), .RN(
n11245), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_26_ ( .D(n447), .CK(clk), .RN(
n11245), .Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_22_ ( .D(n443), .CK(clk), .RN(
n11246), .Q(P_Sgf[22]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_18_ ( .D(n439), .CK(clk), .RN(
n11246), .Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_14_ ( .D(n435), .CK(clk), .RN(
n11246), .Q(P_Sgf[14]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_10_ ( .D(n431), .CK(clk), .RN(
n11247), .Q(P_Sgf[10]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_6_ ( .D(n427), .CK(clk), .RN(
n11246), .Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_2_ ( .D(n423), .CK(clk), .RN(
n11247), .Q(P_Sgf[2]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_37_ ( .D(n458), .CK(clk), .RN(
n11244), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_33_ ( .D(n454), .CK(clk), .RN(
n11245), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_29_ ( .D(n450), .CK(clk), .RN(
n11245), .Q(P_Sgf[29]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_25_ ( .D(n446), .CK(clk), .RN(
n11245), .Q(P_Sgf[25]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_21_ ( .D(n442), .CK(clk), .RN(
n11246), .Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_17_ ( .D(n438), .CK(clk), .RN(
n11246), .Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_13_ ( .D(n434), .CK(clk), .RN(
n11246), .Q(P_Sgf[13]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_9_ ( .D(n430), .CK(clk), .RN(
n11247), .Q(P_Sgf[9]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_5_ ( .D(n426), .CK(clk), .RN(
n11244), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_1_ ( .D(n422), .CK(clk), .RN(
n11243), .Q(P_Sgf[1]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_55_ ( .D(n701), .CK(clk), .RN(
n754), .Q(Op_MX[55]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_59_ ( .D(n705), .CK(clk), .RN(
n11226), .Q(Op_MX[59]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_56_ ( .D(n702), .CK(clk), .RN(
n754), .Q(Op_MX[56]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_54_ ( .D(n700), .CK(clk), .RN(
n754), .Q(Op_MX[54]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_56_ ( .D(n638), .CK(clk), .RN(
n754), .Q(Op_MY[56]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_58_ ( .D(n640), .CK(clk), .RN(
n11233), .Q(Op_MY[58]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_55_ ( .D(n637), .CK(clk), .RN(
n754), .Q(Op_MY[55]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n653), .CK(clk), .RN(
n11237), .Q(Op_MX[7]), .QN(n1070) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n670), .CK(clk), .RN(
n11238), .Q(Op_MX[24]), .QN(n773) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n709), .CK(clk), .RN(n11228), .Q(FSM_selector_C), .QN(n11177) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n646), .CK(clk), .RN(
n11231), .Q(Op_MX[0]), .QN(n1087) );
DFFSX1TS Adder_M_Add_Subt_Result_Q_reg_51_ ( .D(n1231), .CK(clk), .SN(n11227), .QN(Add_result[51]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_82_ ( .D(n800), .CK(clk), .SN(
n11242), .QN(P_Sgf[82]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_83_ ( .D(n801), .CK(clk), .SN(
n11242), .QN(P_Sgf[83]) );
DFFSX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n11174), .CK(clk), .SN(
n11240), .QN(FSM_add_overflow_flag) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_104_ ( .D(n791), .CK(clk), .SN(
n11244), .QN(P_Sgf[104]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_85_ ( .D(n796), .CK(clk), .SN(
n11242), .QN(P_Sgf[85]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_86_ ( .D(n795), .CK(clk), .SN(
n11242), .QN(P_Sgf[86]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_96_ ( .D(n794), .CK(clk), .SN(
n286), .QN(P_Sgf[96]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_94_ ( .D(n793), .CK(clk), .SN(
n286), .QN(P_Sgf[94]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_92_ ( .D(n777), .CK(clk), .SN(
n11242), .QN(P_Sgf[92]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_88_ ( .D(n790), .CK(clk), .SN(
n11242), .QN(P_Sgf[88]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_97_ ( .D(n789), .CK(clk), .SN(
n286), .QN(P_Sgf[97]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_95_ ( .D(n788), .CK(clk), .SN(
n286), .QN(P_Sgf[95]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_89_ ( .D(n787), .CK(clk), .SN(
n11242), .QN(P_Sgf[89]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_87_ ( .D(n786), .CK(clk), .SN(
n11242), .QN(P_Sgf[87]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_93_ ( .D(n785), .CK(clk), .SN(
n286), .QN(P_Sgf[93]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_91_ ( .D(n784), .CK(clk), .SN(
n11242), .QN(P_Sgf[91]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_90_ ( .D(n783), .CK(clk), .SN(
n11242), .QN(P_Sgf[90]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_100_ ( .D(n782), .CK(clk), .SN(
n286), .QN(P_Sgf[100]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_98_ ( .D(n792), .CK(clk), .SN(
n286), .QN(P_Sgf[98]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_103_ ( .D(n779), .CK(clk), .SN(
n11245), .QN(P_Sgf[103]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_101_ ( .D(n781), .CK(clk), .SN(
n286), .QN(P_Sgf[101]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_99_ ( .D(n780), .CK(clk), .SN(
n286), .QN(P_Sgf[99]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_105_ ( .D(n776), .CK(clk), .SN(
n11247), .QN(P_Sgf[105]) );
DFFSX1TS Sgf_operation_ODD1_finalreg_Q_reg_84_ ( .D(n1041), .CK(clk), .SN(
n11242), .QN(P_Sgf[84]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n648), .CK(clk), .RN(
n11237), .Q(Op_MX[2]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n355), .CK(clk),
.RN(n11235), .Q(Sgf_normalized_result[2]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n356), .CK(clk),
.RN(n11226), .Q(Sgf_normalized_result[3]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n357), .CK(clk),
.RN(n11235), .Q(Sgf_normalized_result[4]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n359), .CK(clk),
.RN(n11226), .Q(Sgf_normalized_result[6]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n597), .CK(clk), .RN(
n11226), .Q(Op_MY[15]), .QN(n769) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n600), .CK(clk), .RN(
n11226), .Q(Op_MY[18]), .QN(n770) );
CMPR42X1TS DP_OP_344J35_128_4078_U54 ( .A(n9034), .B(
DP_OP_344J35_128_4078_n103), .C(DP_OP_344J35_128_4078_n160), .D(
DP_OP_344J35_128_4078_n101), .ICI(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_S_B[1]),
.S(DP_OP_344J35_128_4078_n100), .ICO(DP_OP_344J35_128_4078_n98), .CO(
DP_OP_344J35_128_4078_n99) );
CMPR42X1TS DP_OP_344J35_128_4078_U53 ( .A(n9032), .B(
DP_OP_344J35_128_4078_n98), .C(DP_OP_344J35_128_4078_n99), .D(
DP_OP_344J35_128_4078_n159), .ICI(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[9]), .S(DP_OP_344J35_128_4078_n97), .ICO(DP_OP_344J35_128_4078_n95), .CO(
DP_OP_344J35_128_4078_n96) );
CMPR42X1TS DP_OP_344J35_128_4078_U49 ( .A(DP_OP_344J35_128_4078_n129), .B(
DP_OP_344J35_128_4078_n86), .C(DP_OP_344J35_128_4078_n87), .D(
DP_OP_344J35_128_4078_n155), .ICI(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[13]), .S(DP_OP_344J35_128_4078_n85), .ICO(DP_OP_344J35_128_4078_n83), .CO(
DP_OP_344J35_128_4078_n84) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_35_ ( .D(n681), .CK(clk), .RN(
n11229), .Q(Op_MX[35]), .QN(n736) );
DFFSX2TS Operands_load_reg_YMRegister_Q_reg_43_ ( .D(n935), .CK(clk), .SN(
n11235), .Q(DP_OP_342J35_126_4270_n748), .QN(Op_MY[43]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n598), .CK(clk), .RN(
n11226), .Q(Op_MY[16]), .QN(n767) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n657), .CK(clk), .RN(
n11237), .Q(Op_MX[11]) );
DFFSX2TS Operands_load_reg_YMRegister_Q_reg_35_ ( .D(n939), .CK(clk), .SN(
n11249), .Q(DP_OP_343J35_127_4270_n857), .QN(Op_MY[35]) );
DFFSX2TS Operands_load_reg_YMRegister_Q_reg_39_ ( .D(n938), .CK(clk), .SN(
n11235), .Q(DP_OP_343J35_127_4270_n853), .QN(Op_MY[39]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_39_ ( .D(n685), .CK(clk), .RN(
n11249), .Q(Op_MX[39]), .QN(n819) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_37_ ( .D(n683), .CK(clk), .RN(
n11239), .Q(Op_MX[37]), .QN(n820) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_41_ ( .D(n623), .CK(clk), .RN(
n11240), .Q(Op_MY[41]), .QN(n761) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_42_ ( .D(n624), .CK(clk), .RN(
n11234), .Q(Op_MY[42]), .QN(n763) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n595), .CK(clk), .RN(
n11226), .Q(Op_MY[13]), .QN(n1049) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n660), .CK(clk), .RN(
n11239), .Q(Op_MX[14]), .QN(n847) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n602), .CK(clk), .RN(
n11230), .Q(Op_MY[20]), .QN(n735) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n650), .CK(clk), .RN(
n11237), .Q(Op_MX[4]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n664), .CK(clk), .RN(
n11238), .Q(Op_MX[18]), .QN(n848) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_43_ ( .D(n689), .CK(clk), .RN(
n11249), .Q(Op_MX[43]), .QN(n838) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n665), .CK(clk), .RN(
n11236), .Q(Op_MX[19]), .QN(n852) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n667), .CK(clk), .RN(
n11230), .Q(Op_MX[21]), .QN(n772) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_49_ ( .D(n695), .CK(clk), .RN(
n11234), .Q(Op_MX[49]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n668), .CK(clk), .RN(
n11249), .Q(Op_MX[22]), .QN(DP_OP_346J35_130_4270_n829) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n669), .CK(clk), .RN(
n11229), .Q(Op_MX[23]), .QN(n771) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n666), .CK(clk), .RN(
n11229), .Q(Op_MX[20]), .QN(n731) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_46_ ( .D(n628), .CK(clk), .RN(
n11239), .Q(Op_MY[46]), .QN(n730) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_46_ ( .D(n692), .CK(clk), .RN(
n11234), .Q(Op_MX[46]), .QN(n729) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_47_ ( .D(n693), .CK(clk), .RN(
n11234), .Q(Op_MX[47]), .QN(n728) );
CMPR42X1TS DP_OP_344J35_128_4078_U52 ( .A(n9030), .B(
DP_OP_344J35_128_4078_n95), .C(DP_OP_344J35_128_4078_n158), .D(
DP_OP_344J35_128_4078_n96), .ICI(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[10]), .S(DP_OP_344J35_128_4078_n94), .ICO(DP_OP_344J35_128_4078_n92), .CO(
DP_OP_344J35_128_4078_n93) );
CMPR42X1TS DP_OP_344J35_128_4078_U51 ( .A(n9028), .B(
DP_OP_344J35_128_4078_n92), .C(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[11]), .D(DP_OP_344J35_128_4078_n93), .ICI(DP_OP_344J35_128_4078_n157), .S(
DP_OP_344J35_128_4078_n91), .ICO(DP_OP_344J35_128_4078_n89), .CO(
DP_OP_344J35_128_4078_n90) );
CMPR42X1TS DP_OP_344J35_128_4078_U50 ( .A(n9026), .B(
DP_OP_344J35_128_4078_n89), .C(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[12]), .D(DP_OP_344J35_128_4078_n90), .ICI(DP_OP_344J35_128_4078_n156), .S(
DP_OP_344J35_128_4078_n88), .ICO(DP_OP_344J35_128_4078_n86), .CO(
DP_OP_344J35_128_4078_n87) );
CMPR42X1TS DP_OP_344J35_128_4078_U46 ( .A(DP_OP_344J35_128_4078_n126), .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[2]), .C(n844), .D(DP_OP_344J35_128_4078_n77), .ICI(DP_OP_344J35_128_4078_n78),
.S(DP_OP_344J35_128_4078_n76), .ICO(DP_OP_344J35_128_4078_n74), .CO(
DP_OP_344J35_128_4078_n75) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n710), .CK(clk), .RN(n754), .Q(FSM_selector_A),
.QN(n11205) );
MXI2X1TS U746 ( .A(P_Sgf[89]), .B(n9460), .S0(n10823), .Y(n787) );
MXI2X1TS U747 ( .A(P_Sgf[97]), .B(n9470), .S0(n10823), .Y(n789) );
MXI2X1TS U748 ( .A(P_Sgf[90]), .B(n9439), .S0(n10823), .Y(n783) );
MXI2X1TS U749 ( .A(P_Sgf[91]), .B(n9444), .S0(n10823), .Y(n784) );
MXI2X1TS U750 ( .A(P_Sgf[93]), .B(n9449), .S0(n10823), .Y(n785) );
NOR2X4TS U751 ( .A(n11061), .B(n11177), .Y(n10507) );
NOR2XLTS U752 ( .A(n909), .B(n942), .Y(n9411) );
CLKINVX6TS U753 ( .A(n10811), .Y(n10877) );
NAND2X1TS U754 ( .A(Sgf_normalized_result[50]), .B(n11163), .Y(n11161) );
NOR2X1TS U755 ( .A(n8810), .B(n9434), .Y(n9423) );
NAND2X1TS U756 ( .A(n9420), .B(n9418), .Y(n9434) );
NOR2X2TS U757 ( .A(n9399), .B(n9398), .Y(n9504) );
NAND2X2TS U758 ( .A(n798), .B(n9400), .Y(n9499) );
OR2X2TS U759 ( .A(n9383), .B(n9382), .Y(n1213) );
NOR2X1TS U760 ( .A(n8822), .B(n9431), .Y(n9418) );
NAND2X1TS U761 ( .A(Sgf_normalized_result[48]), .B(n11154), .Y(n11157) );
NAND2X1TS U762 ( .A(n8780), .B(n9393), .Y(n9114) );
NAND2X1TS U763 ( .A(n9415), .B(n9413), .Y(n9431) );
NOR2X2TS U764 ( .A(n9378), .B(n9377), .Y(n10478) );
INVX2TS U765 ( .A(n9393), .Y(n9391) );
NAND2X1TS U766 ( .A(Sgf_normalized_result[46]), .B(n11150), .Y(n11152) );
NOR2X2TS U767 ( .A(n9372), .B(n9371), .Y(n10468) );
NAND2X2TS U768 ( .A(n9372), .B(n9371), .Y(n10469) );
NAND2X1TS U769 ( .A(n1075), .B(n9379), .Y(n9381) );
INVX2TS U770 ( .A(n9379), .Y(n9113) );
CLKXOR2X2TS U771 ( .A(n9370), .B(n1176), .Y(n9372) );
NOR2X2TS U772 ( .A(n8779), .B(n8778), .Y(n9394) );
NAND2X2TS U773 ( .A(n8779), .B(n8778), .Y(n9393) );
NAND2X1TS U774 ( .A(Sgf_normalized_result[44]), .B(n11146), .Y(n11148) );
NAND2X1TS U775 ( .A(n9110), .B(n9109), .Y(n9374) );
NAND2X2TS U776 ( .A(n9112), .B(n9111), .Y(n9379) );
XNOR2X2TS U777 ( .A(n5629), .B(n993), .Y(n8779) );
OR2X2TS U778 ( .A(n8786), .B(n8785), .Y(n8778) );
NAND2X1TS U779 ( .A(n9108), .B(n9107), .Y(n9368) );
NOR2X1TS U780 ( .A(n9388), .B(n9387), .Y(n5629) );
XNOR2X2TS U781 ( .A(n8786), .B(n8785), .Y(n9111) );
NAND2X1TS U782 ( .A(n9106), .B(n9105), .Y(n9363) );
INVX2TS U783 ( .A(n9317), .Y(n8785) );
NOR2X1TS U784 ( .A(n807), .B(n9477), .Y(n9461) );
NAND2X1TS U785 ( .A(n8781), .B(n8783), .Y(n9387) );
NAND2X1TS U786 ( .A(Sgf_normalized_result[42]), .B(n11142), .Y(n11144) );
OR2X2TS U787 ( .A(n8790), .B(n8789), .Y(n8786) );
INVX2TS U788 ( .A(n9314), .Y(n8789) );
CLKINVX1TS U789 ( .A(n9311), .Y(n8796) );
NOR2X1TS U790 ( .A(n8787), .B(n995), .Y(n8781) );
XNOR2X1TS U791 ( .A(n8758), .B(n9696), .Y(n1229) );
INVX2TS U792 ( .A(n9405), .Y(n8801) );
INVX2TS U793 ( .A(n9425), .Y(n8805) );
CLKINVX1TS U794 ( .A(n10569), .Y(n8806) );
NOR2X2TS U795 ( .A(n9360), .B(n9359), .Y(n10878) );
NOR2X1TS U796 ( .A(n8807), .B(n5628), .Y(n8791) );
INVX2TS U797 ( .A(n9406), .Y(n8810) );
NAND2X1TS U798 ( .A(n9314), .B(n9313), .Y(n10820) );
NAND2X1TS U799 ( .A(n9311), .B(n9310), .Y(n10575) );
NOR2X2TS U800 ( .A(n9355), .B(n9354), .Y(n10864) );
XNOR2X2TS U801 ( .A(n8766), .B(n1050), .Y(n9314) );
OR2X2TS U802 ( .A(n9352), .B(n9351), .Y(n1207) );
OAI21XLTS U803 ( .A0(n8776), .A1(n7028), .B0(n7027), .Y(n7029) );
OAI21X1TS U804 ( .A0(n8776), .A1(n8765), .B0(n8764), .Y(n8766) );
ADDHX1TS U805 ( .A(n9742), .B(n8500), .CO(n8721), .S(n9420) );
XNOR2X2TS U806 ( .A(n7024), .B(n6810), .Y(n9311) );
NAND2XLTS U807 ( .A(n8763), .B(n8762), .Y(n8764) );
NAND2XLTS U808 ( .A(n8763), .B(n7026), .Y(n7027) );
NOR2X2TS U809 ( .A(n9350), .B(n9349), .Y(n10835) );
OAI21XLTS U810 ( .A0(n8776), .A1(n7032), .B0(n7031), .Y(n7034) );
OAI21X1TS U811 ( .A0(n8776), .A1(n1196), .B0(n846), .Y(n8777) );
OAI21X1TS U812 ( .A0(n8776), .A1(n7023), .B0(n7022), .Y(n7024) );
NAND2XLTS U813 ( .A(n8763), .B(n8759), .Y(n7022) );
OAI21X2TS U814 ( .A0(n8841), .A1(n8849), .B0(n8842), .Y(n5626) );
OA21XLTS U815 ( .A0(n8775), .A1(n8774), .B0(n8773), .Y(n846) );
ADDHX1TS U816 ( .A(n9744), .B(n8508), .CO(n8720), .S(n9415) );
ADDHXLTS U817 ( .A(n9745), .B(n8512), .CO(n8508), .S(n9408) );
NAND2X1TS U818 ( .A(n8768), .B(n8771), .Y(n8774) );
NAND2X1TS U819 ( .A(n8772), .B(n8771), .Y(n8773) );
NAND2X1TS U820 ( .A(n5625), .B(n5624), .Y(n8842) );
OAI21X1TS U821 ( .A0(n8717), .A1(n8489), .B0(n8488), .Y(n8512) );
NAND2X1TS U822 ( .A(n9342), .B(n9738), .Y(n10718) );
NAND2XLTS U823 ( .A(n8714), .B(n1016), .Y(n8488) );
NOR2X2TS U824 ( .A(n9342), .B(n9738), .Y(n10717) );
NAND2X1TS U825 ( .A(n8712), .B(n1016), .Y(n8489) );
NAND2X2TS U826 ( .A(n5623), .B(n5622), .Y(n8849) );
OR2X2TS U827 ( .A(n9340), .B(n9739), .Y(n1179) );
NAND2X1TS U828 ( .A(n1161), .B(n5484), .Y(n5485) );
AOI21X2TS U829 ( .A0(n5489), .A1(n808), .B0(n5469), .Y(n5486) );
CLKXOR2X2TS U830 ( .A(n8515), .B(n8514), .Y(n10608) );
NAND2X1TS U831 ( .A(n9340), .B(n9739), .Y(n10729) );
NAND2X1TS U832 ( .A(n9339), .B(n9740), .Y(n10738) );
INVX1TS U833 ( .A(n5487), .Y(n5469) );
NOR2X4TS U834 ( .A(n8769), .B(n8509), .Y(n8761) );
BUFX8TS U835 ( .A(n8515), .Y(n8776) );
OR2X2TS U836 ( .A(n9337), .B(n9336), .Y(n1180) );
NAND2XLTS U837 ( .A(n808), .B(n5487), .Y(n5488) );
NAND2XLTS U838 ( .A(n8519), .B(n8518), .Y(n8520) );
CLKXOR2X2TS U839 ( .A(n8698), .B(n8697), .Y(n1222) );
NOR2X2TS U840 ( .A(n7021), .B(n7020), .Y(n8509) );
NAND2X1TS U841 ( .A(n7021), .B(n7020), .Y(n8770) );
NAND2X1TS U842 ( .A(n9337), .B(n9336), .Y(n10749) );
NAND2X1TS U843 ( .A(n9335), .B(n9334), .Y(n10758) );
NOR2X2TS U844 ( .A(n9335), .B(n9334), .Y(n10757) );
CLKXOR2X2TS U845 ( .A(n8534), .B(n8533), .Y(n10596) );
NOR2X2TS U846 ( .A(n8702), .B(n8703), .Y(n8712) );
OAI21X2TS U847 ( .A0(n8703), .A1(n8701), .B0(n8704), .Y(n8714) );
NAND2X1TS U848 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[26]), .B(
n9749), .Y(n8701) );
NOR2X2TS U849 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[27]), .B(
n9748), .Y(n8703) );
NAND2X1TS U850 ( .A(n8532), .B(n8531), .Y(n8533) );
NAND2X1TS U851 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[27]), .B(
n9748), .Y(n8704) );
AO21XLTS U852 ( .A0(n5454), .A1(n5453), .B0(n5452), .Y(n1129) );
NAND2X2TS U853 ( .A(n5447), .B(n5446), .Y(n5491) );
OAI21X1TS U854 ( .A0(n8694), .A1(n8691), .B0(n8695), .Y(n8468) );
NAND2X1TS U855 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[25]), .B(
n9750), .Y(n8695) );
NAND2X1TS U856 ( .A(n9332), .B(n9331), .Y(n10769) );
NAND2X1TS U857 ( .A(n9330), .B(n9329), .Y(n10778) );
AO21X2TS U858 ( .A0(n996), .A1(n8895), .B0(n5600), .Y(n1112) );
NOR2X2TS U859 ( .A(n9330), .B(n9329), .Y(n10777) );
OR2X2TS U860 ( .A(n5444), .B(n5443), .Y(n958) );
AOI21X1TS U861 ( .A0(n1182), .A1(n10785), .B0(n9328), .Y(n10773) );
NAND2X1TS U862 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[24]), .B(
n9751), .Y(n8691) );
OR2X2TS U863 ( .A(n5599), .B(n5598), .Y(n996) );
CLKXOR2X2TS U864 ( .A(n8680), .B(n962), .Y(n1051) );
OAI2BB1X1TS U865 ( .A0N(n856), .A1N(n1258), .B0(n1259), .Y(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[29]) );
AND2X2TS U866 ( .A(n7006), .B(n825), .Y(n930) );
CLKXOR2X2TS U867 ( .A(n5202), .B(n5201), .Y(n5446) );
NAND2X1TS U868 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[23]), .B(
n9752), .Y(n8684) );
NOR2X1TS U869 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[23]), .B(
n9752), .Y(n8683) );
NAND2X1TS U870 ( .A(n5597), .B(n5596), .Y(n8900) );
NAND2X1TS U871 ( .A(n5599), .B(n5598), .Y(n8894) );
NOR2X1TS U872 ( .A(n6888), .B(n6890), .Y(n7006) );
NAND2XLTS U873 ( .A(n5200), .B(n5449), .Y(n5201) );
NAND2X1TS U874 ( .A(n1080), .B(n8906), .Y(n8908) );
AOI21X2TS U875 ( .A0(n7009), .A1(n825), .B0(n7008), .Y(n7013) );
CMPR32X2TS U876 ( .A(n9699), .B(n9698), .C(n9697), .CO(
DP_OP_344J35_128_4078_n44), .S(DP_OP_344J35_128_4078_n45) );
NOR2X1TS U877 ( .A(n5597), .B(n5596), .Y(n8899) );
NAND2XLTS U878 ( .A(n8914), .B(n8913), .Y(n8916) );
INVX1TS U879 ( .A(n7007), .Y(n7008) );
OAI21X2TS U880 ( .A0(n6995), .A1(n6890), .B0(n6889), .Y(n7009) );
XNOR2X1TS U881 ( .A(n6903), .B(n6902), .Y(n8539) );
CMPR32X2TS U882 ( .A(n9705), .B(n9704), .C(n9703), .CO(
DP_OP_344J35_128_4078_n48), .S(DP_OP_344J35_128_4078_n49) );
NAND2X1TS U883 ( .A(n6837), .B(n6836), .Y(n6995) );
ADDHXLTS U884 ( .A(n9756), .B(n9755), .CO(n9758), .S(n9699) );
NAND2X1TS U885 ( .A(n9319), .B(n9318), .Y(n10812) );
OAI21X1TS U886 ( .A0(n5400), .A1(n5399), .B0(n5398), .Y(n5405) );
NAND2X2TS U887 ( .A(n6893), .B(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[28]), .Y(n7007) );
ADDHXLTS U888 ( .A(n9701), .B(n9700), .CO(n9755), .S(n9705) );
NAND2X1TS U889 ( .A(n5143), .B(n5142), .Y(n5415) );
XOR2X1TS U890 ( .A(add_x_87_n1), .B(n9878), .Y(n6883) );
OR2X2TS U891 ( .A(n5588), .B(n5587), .Y(n1082) );
OR2X2TS U892 ( .A(n6892), .B(n6891), .Y(n6893) );
XNOR2X1TS U893 ( .A(n6892), .B(n6891), .Y(n6884) );
CMPR32X2TS U894 ( .A(n9710), .B(n9709), .C(DP_OP_344J35_128_4078_n56), .CO(
DP_OP_344J35_128_4078_n52), .S(DP_OP_344J35_128_4078_n53) );
OR2X2TS U895 ( .A(Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[26]), .B(
n6839), .Y(n6892) );
NAND2X1TS U896 ( .A(n1050), .B(n6827), .Y(n6901) );
MXI2X1TS U897 ( .A(n1257), .B(n1256), .S0(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[12]), .Y(n1254) );
MX2X1TS U898 ( .A(DP_OP_338J35_122_4684_n3), .B(DP_OP_338J35_122_4684_n2),
.S0(DP_OP_338J35_122_4684_n8), .Y(n1131) );
NAND2X1TS U899 ( .A(n5246), .B(n5245), .Y(n5247) );
ADDFX2TS U900 ( .A(n5160), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[17]), .CI(n5159), .CO(n5185), .S(n5143) );
CMPR32X2TS U901 ( .A(n5134), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(n5133), .CO(n5159), .S(n5119) );
NAND2X1TS U902 ( .A(n1232), .B(n1233), .Y(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[17]) );
CMPR32X2TS U903 ( .A(n6826), .B(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[24]), .C(n6825), .CO(
n6830), .S(n6827) );
OR2X2TS U904 ( .A(n6802), .B(n6801), .Y(n836) );
OAI21X1TS U905 ( .A0(n6916), .A1(n1058), .B0(n6917), .Y(n6914) );
CMPR32X2TS U906 ( .A(n6616), .B(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[22]), .C(n6615), .CO(
n6608), .S(n6807) );
XOR2X1TS U907 ( .A(n7505), .B(n7504), .Y(n9639) );
NAND2X1TS U908 ( .A(n6802), .B(n6801), .Y(n6913) );
CLKMX2X2TS U909 ( .A(add_x_87_n13), .B(add_x_87_n12), .S0(add_x_87_n16), .Y(
add_x_87_n11) );
CLKMX2X2TS U910 ( .A(DP_OP_345J35_129_3436_n3), .B(DP_OP_345J35_129_3436_n2),
.S0(DP_OP_345J35_129_3436_n8), .Y(n1153) );
CMPR32X2TS U911 ( .A(n5089), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .C(n5088), .CO(n4998), .S(n5113) );
NOR2X1TS U912 ( .A(n6800), .B(n6799), .Y(n6916) );
NAND2X1TS U913 ( .A(n6798), .B(n6797), .Y(n6987) );
NAND2X1TS U914 ( .A(n7357), .B(n7356), .Y(n8725) );
OA21XLTS U915 ( .A0(n7374), .A1(n7373), .B0(n7372), .Y(n1219) );
INVX2TS U916 ( .A(n8732), .Y(n7405) );
CMPR32X2TS U917 ( .A(n8979), .B(n8978), .C(n8977), .CO(n8972), .S(n9201) );
CMPR32X2TS U918 ( .A(n8573), .B(n8572), .C(n8571), .CO(n8569), .S(n10631) );
NAND2X1TS U919 ( .A(n7353), .B(n7352), .Y(n7402) );
NAND2X1TS U920 ( .A(n5078), .B(n5077), .Y(n5079) );
NAND2X1TS U921 ( .A(n5059), .B(n5058), .Y(n5264) );
ADDHX1TS U922 ( .A(n10131), .B(n10130), .CO(DP_OP_338J35_122_4684_n32), .S(
DP_OP_338J35_122_4684_n33) );
MXI2X1TS U923 ( .A(n1243), .B(n1154), .S0(DP_OP_345J35_129_3436_n32), .Y(
n1240) );
CMPR32X2TS U924 ( .A(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[11]),
.B(n6601), .C(n6600), .CO(add_x_87_n21), .S(n6636) );
CMPR32X2TS U925 ( .A(n10209), .B(n10208), .C(n10207), .CO(
DP_OP_338J35_122_4684_n40), .S(DP_OP_338J35_122_4684_n41) );
CMPR32X2TS U926 ( .A(n6646), .B(n6645), .C(n6644), .CO(n6637), .S(n6797) );
CMPR32X2TS U927 ( .A(n10161), .B(n10160), .C(n10159), .CO(
DP_OP_338J35_122_4684_n34), .S(DP_OP_338J35_122_4684_n35) );
XOR2X1TS U928 ( .A(n6842), .B(n6841), .Y(n8572) );
XOR2X1TS U929 ( .A(n5011), .B(n5010), .Y(n5038) );
OAI21X2TS U930 ( .A0(n5076), .A1(n5074), .B0(n5077), .Y(n5096) );
NAND2X2TS U931 ( .A(n4991), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n5190) );
CMPR32X2TS U932 ( .A(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[10]),
.B(n6599), .C(n6598), .CO(n6600), .S(n6644) );
CMPR32X2TS U933 ( .A(n6654), .B(n6653), .C(n6652), .CO(n6645), .S(n6794) );
CMPR32X2TS U934 ( .A(n10177), .B(n10176), .C(n10175), .CO(n10159), .S(n10208) );
CMPR32X2TS U935 ( .A(n10151), .B(n10150), .C(n10149), .CO(n10130), .S(n10160) );
NAND2XLTS U936 ( .A(n5055), .B(n5054), .Y(n5056) );
NAND2X1TS U937 ( .A(n7278), .B(n7277), .Y(n7408) );
NAND2X1TS U938 ( .A(n7276), .B(n7275), .Y(n7413) );
NAND2X2TS U939 ( .A(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .B(n4885), .Y(n5077) );
NOR2X2TS U940 ( .A(n4991), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n5188) );
CMPR32X2TS U941 ( .A(n6660), .B(n6659), .C(n6658), .CO(n6653), .S(n6791) );
CMPR32X2TS U942 ( .A(n10158), .B(n10157), .C(n10156), .CO(n10161), .S(n10175) );
CMPR32X2TS U943 ( .A(n6668), .B(n6667), .C(n6666), .CO(n6659), .S(n6789) );
CMPR32X2TS U944 ( .A(n10148), .B(n10147), .C(n10146), .CO(n10149), .S(n10156) );
AFCSIHCONX2TS U945 ( .A(DP_OP_338J35_122_4684_n78), .B(
DP_OP_338J35_122_4684_n63), .CS(DP_OP_338J35_122_4684_n15), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .CO0N(DP_OP_338J35_122_4684_n14), .CO1N(DP_OP_338J35_122_4684_n13) );
NOR2X1TS U946 ( .A(n7245), .B(n7244), .Y(n8475) );
NAND2X1TS U947 ( .A(n7328), .B(n1217), .Y(n7368) );
CMPR32X2TS U948 ( .A(n10276), .B(n10275), .C(n10274), .CO(
DP_OP_338J35_122_4684_n62), .S(DP_OP_338J35_122_4684_n63) );
CMPR32X2TS U949 ( .A(n9923), .B(n9922), .C(n9921), .CO(
DP_OP_345J35_129_3436_n34), .S(DP_OP_345J35_129_3436_n35) );
CMPR32X2TS U950 ( .A(n9970), .B(n9969), .C(n9968), .CO(
DP_OP_345J35_129_3436_n40), .S(DP_OP_345J35_129_3436_n41) );
NOR2X1TS U951 ( .A(n5007), .B(n5005), .Y(n5041) );
CMPR32X2TS U952 ( .A(n5014), .B(n5013), .C(n5012), .CO(n5045), .S(n5037) );
NAND2X1TS U953 ( .A(DP_OP_342J35_126_4270_n136), .B(
DP_OP_342J35_126_4270_n130), .Y(n7331) );
CMPR32X2TS U954 ( .A(n10259), .B(n10258), .C(n10257), .CO(n10256), .S(n10276) );
CMPR32X2TS U955 ( .A(n9937), .B(n9936), .C(n9935), .CO(n9921), .S(n9969) );
CMPR32X2TS U956 ( .A(n9905), .B(n9904), .C(n9903), .CO(n9894), .S(n9922) );
CMPR32X2TS U957 ( .A(n10017), .B(n10016), .C(n10015), .CO(
DP_OP_345J35_129_3436_n50), .S(DP_OP_345J35_129_3436_n51) );
NAND2X1TS U958 ( .A(n8359), .B(n8358), .Y(n8391) );
CMPR32X2TS U959 ( .A(n10273), .B(n10272), .C(n10271), .CO(n10254), .S(n10274) );
ADDFX1TS U960 ( .A(n10180), .B(n10179), .CI(n10178), .CO(n10176), .S(n10217)
);
CMPR32X2TS U961 ( .A(n10065), .B(n10064), .C(n10063), .CO(
DP_OP_345J35_129_3436_n96), .S(DP_OP_345J35_129_3436_n97) );
CMPR32X2TS U962 ( .A(n10307), .B(n10306), .C(n10305), .CO(
DP_OP_338J35_122_4684_n116), .S(n5047) );
CMPR32X2TS U963 ( .A(n10037), .B(n10036), .C(n10035), .CO(
DP_OP_345J35_129_3436_n62), .S(DP_OP_345J35_129_3436_n63) );
CMPR32X2TS U964 ( .A(n10053), .B(n10052), .C(n10051), .CO(
DP_OP_345J35_129_3436_n78), .S(DP_OP_345J35_129_3436_n79) );
CMPR32X2TS U965 ( .A(n2763), .B(n2762), .C(n2761), .CO(n9880), .S(n2817) );
CMPR32X2TS U966 ( .A(n6687), .B(n6686), .C(n6685), .CO(n6681), .S(n6930) );
CMPR32X2TS U967 ( .A(n10155), .B(n10154), .C(n10153), .CO(n10157), .S(n10178) );
CMPR32X2TS U968 ( .A(n10279), .B(n10278), .C(n10277), .CO(n10271), .S(n10292) );
NAND2X1TS U969 ( .A(DP_OP_342J35_126_4270_n157), .B(
DP_OP_342J35_126_4270_n168), .Y(n7261) );
CMPR32X2TS U970 ( .A(n10235), .B(n10234), .C(n10233), .CO(n10216), .S(n10272) );
CMPR32X2TS U971 ( .A(n5382), .B(n5381), .C(n5380), .CO(n4596), .S(n5533) );
CMPR32X2TS U972 ( .A(n7337), .B(n7336), .C(DP_OP_342J35_126_4270_n128), .CO(
n7361), .S(n7313) );
CMPR32X2TS U973 ( .A(n10014), .B(n10013), .C(n10012), .CO(n9968), .S(n10015)
);
CMPR32X2TS U974 ( .A(n9920), .B(n9919), .C(n9918), .CO(n9923), .S(n9935) );
CMPR32X2TS U975 ( .A(n6109), .B(n6108), .C(n6107), .CO(n6110), .S(n6096) );
CMPR32X2TS U976 ( .A(n9908), .B(n9907), .C(n9906), .CO(n9903), .S(n9937) );
NOR2X1TS U977 ( .A(n8179), .B(n8148), .Y(n8359) );
CMPR32X2TS U978 ( .A(n10298), .B(n10297), .C(n10296), .CO(n10303), .S(n10305) );
CMPR32X2TS U979 ( .A(n10263), .B(n10262), .C(n10261), .CO(n10273), .S(n10288) );
CMPR32X2TS U980 ( .A(n2769), .B(n2768), .C(n2767), .CO(n2761), .S(n2823) );
CMPR32X2TS U981 ( .A(n2772), .B(n2771), .C(n2770), .CO(n2763), .S(n2822) );
CMPR32X2TS U982 ( .A(n10062), .B(n10061), .C(n10060), .CO(n10052), .S(n10063) );
CMPR32X2TS U983 ( .A(n9964), .B(n9963), .C(n9962), .CO(n9936), .S(n10013) );
CMPR32X2TS U984 ( .A(n2144), .B(n2143), .C(n2142), .CO(n2135), .S(n5019) );
CMPR32X2TS U985 ( .A(n9643), .B(n9642), .C(n9641), .CO(n7474), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[12]) );
CMPR32X2TS U986 ( .A(n10020), .B(n10019), .C(n10018), .CO(n10017), .S(n10037) );
CMPR32X2TS U987 ( .A(n10034), .B(n10033), .C(n10032), .CO(n10016), .S(n10035) );
CMPR32X2TS U988 ( .A(n2138), .B(n2137), .C(n2136), .CO(n10306), .S(n5013) );
CMPR32X2TS U989 ( .A(n6695), .B(n6694), .C(n6693), .CO(n6686), .S(n6933) );
CMPR32X2TS U990 ( .A(n3015), .B(n3014), .C(n3013), .CO(n3018), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[4]) );
CMPR32X2TS U991 ( .A(n6105), .B(n6104), .C(n6103), .CO(n6111), .S(n6108) );
CMPR32X2TS U992 ( .A(n6077), .B(n6076), .C(n6075), .CO(n6097), .S(n6094) );
CMPR32X2TS U993 ( .A(n10139), .B(n10138), .C(n10137), .CO(n10133), .S(n10154) );
CMPR32X2TS U994 ( .A(n9967), .B(n9966), .C(n9965), .CO(n9970), .S(n10012) );
CMPR32X2TS U995 ( .A(n10050), .B(n10049), .C(n10048), .CO(n10036), .S(n10051) );
NAND2X1TS U996 ( .A(n4951), .B(n4950), .Y(n4977) );
CMPR32X2TS U997 ( .A(n4986), .B(n4985), .C(n4984), .CO(n4987), .S(n4968) );
NAND2X1TS U998 ( .A(n1102), .B(n4847), .Y(n4849) );
NAND2X1TS U999 ( .A(n3865), .B(n3864), .Y(n5250) );
CMPR32X2TS U1000 ( .A(n10047), .B(n10046), .C(n10045), .CO(n10060), .S(
n10067) );
CMPR32X2TS U1001 ( .A(n10229), .B(n10228), .C(n10227), .CO(n10234), .S(
n10262) );
CMPR32X2TS U1002 ( .A(n9917), .B(n9916), .C(n9915), .CO(n9919), .S(n9962) );
CMPR32X2TS U1003 ( .A(n2775), .B(n2774), .C(n2773), .CO(n2768), .S(n2904) );
CMPR32X2TS U1004 ( .A(n6701), .B(n6700), .C(n6699), .CO(n6694), .S(n6936) );
CMPR32X2TS U1005 ( .A(n10232), .B(n10231), .C(n10230), .CO(n10233), .S(
n10261) );
CMPR32X2TS U1006 ( .A(n10040), .B(n10039), .C(n10038), .CO(n10032), .S(
n10053) );
CMPR32X2TS U1007 ( .A(n10056), .B(n10055), .C(n10054), .CO(n10048), .S(
n10065) );
CMPR32X2TS U1008 ( .A(n9998), .B(n9997), .C(n9996), .CO(n10014), .S(n10033)
);
CMPR32X2TS U1009 ( .A(n10024), .B(n10023), .C(n10022), .CO(n10034), .S(
n10049) );
CMPR32X2TS U1010 ( .A(n2778), .B(n2777), .C(n2776), .CO(n2771), .S(n2903) );
CMPR32X2TS U1011 ( .A(n2760), .B(n2759), .C(n2758), .CO(n2766), .S(n2767) );
CMPR32X2TS U1012 ( .A(n4933), .B(n4932), .C(n4931), .CO(n4951), .S(n4917) );
CMPR32X2TS U1013 ( .A(n9530), .B(n7432), .C(n9582), .CO(n7443), .S(n9531) );
CMPR32X2TS U1014 ( .A(n4960), .B(n4959), .C(n4958), .CO(n4969), .S(n4950) );
CMPR32X2TS U1015 ( .A(n7524), .B(n9712), .C(n9711), .CO(
DP_OP_344J35_128_4078_n101), .S(n8412) );
CMPR32X2TS U1016 ( .A(n6051), .B(n6050), .C(n6049), .CO(n6095), .S(n6092) );
CMPR32X2TS U1017 ( .A(n9973), .B(n9972), .C(n9971), .CO(n9967), .S(n10020)
);
CMPR32X2TS U1018 ( .A(n9762), .B(n9761), .C(n9760), .CO(n7336), .S(
DP_OP_342J35_126_4270_n132) );
CMPR32X2TS U1019 ( .A(n6089), .B(n6088), .C(n6087), .CO(n6107), .S(n6076) );
CMPR32X2TS U1020 ( .A(n2150), .B(n2149), .C(n2148), .CO(n2143), .S(n5030) );
CMPR32X2TS U1021 ( .A(n3012), .B(n3011), .C(n3010), .CO(n3013), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[3]) );
CMPR32X2TS U1022 ( .A(n7451), .B(n7450), .C(n7449), .CO(n7476), .S(n9642) );
AOI21X1TS U1023 ( .A0(n5268), .A1(n1063), .B0(n3834), .Y(n5262) );
ADDFX1TS U1024 ( .A(n2132), .B(n2131), .CI(n2130), .CO(n2138), .S(n2139) );
CMPR32X2TS U1025 ( .A(n10266), .B(n10265), .C(n10264), .CO(n10279), .S(
n10295) );
CMPR32X2TS U1026 ( .A(n2104), .B(n2103), .C(n2102), .CO(n10267), .S(n2118)
);
CMPR32X2TS U1027 ( .A(n2117), .B(n2116), .C(n2115), .CO(n2120), .S(n2142) );
CMPR32X2TS U1028 ( .A(n10044), .B(n10043), .C(n10042), .CO(n10038), .S(
n10061) );
CMPR32X2TS U1029 ( .A(n2725), .B(n2724), .C(n2723), .CO(n2727), .S(n2770) );
CMPR32X2TS U1030 ( .A(n10030), .B(n10029), .C(n10028), .CO(n10055), .S(
n10058) );
CMPR32X2TS U1031 ( .A(n9987), .B(n9986), .C(n9985), .CO(n9997), .S(n10023)
);
CMPR32X2TS U1032 ( .A(n2781), .B(n2780), .C(n2779), .CO(n2774), .S(n2916) );
CMPR32X2TS U1033 ( .A(n10238), .B(n10237), .C(n10236), .CO(n10232), .S(
n10266) );
CMPR32X2TS U1034 ( .A(n6577), .B(n6576), .C(n6575), .CO(n6580), .S(n6699) );
CMPR32X2TS U1035 ( .A(n5376), .B(n5375), .C(n5374), .CO(n5288), .S(n5539) );
CMPR32X2TS U1036 ( .A(n10194), .B(n10193), .C(n10192), .CO(n10212), .S(
n10227) );
CMPR32X2TS U1037 ( .A(n2623), .B(n2622), .C(n2621), .CO(n10046), .S(n2765)
);
CMPR32X2TS U1038 ( .A(n6780), .B(n6779), .C(n6778), .CO(n6700), .S(n6939) );
CMPR32X2TS U1039 ( .A(n4949), .B(n4948), .C(n4947), .CO(n4958), .S(n4931) );
CMPR32X2TS U1040 ( .A(n2757), .B(n2756), .C(n2755), .CO(n2759), .S(n2773) );
CMPR32X2TS U1041 ( .A(n1990), .B(n1989), .C(n1988), .CO(n10285), .S(n2137)
);
CMPR32X2TS U1042 ( .A(n10183), .B(n10182), .C(n10181), .CO(n10171), .S(
n10229) );
CMPR32X2TS U1043 ( .A(n10001), .B(n10000), .C(n9999), .CO(n9996), .S(n10040)
);
CMPR32X2TS U1044 ( .A(n10027), .B(n10026), .C(n10025), .CO(n10022), .S(
n10056) );
CMPR32X2TS U1045 ( .A(n2784), .B(n2783), .C(n2782), .CO(n2775), .S(n2915) );
CMPR32X2TS U1046 ( .A(n6074), .B(n6073), .C(n6072), .CO(n6075), .S(n6050) );
CMPR32X2TS U1047 ( .A(n2153), .B(n2152), .C(n2151), .CO(n2148), .S(n3920) );
CMPR32X2TS U1048 ( .A(n6080), .B(n6079), .C(n6078), .CO(n6109), .S(n6087) );
CMPR32X2TS U1049 ( .A(n4967), .B(n4966), .C(n4965), .CO(n4984), .S(n4959) );
CMPR32X2TS U1050 ( .A(n4409), .B(n4408), .C(n4407), .CO(n4458), .S(n5289) );
CMPR32X2TS U1051 ( .A(n6018), .B(n6017), .C(n6016), .CO(n6093), .S(n6091) );
CMPR32X2TS U1052 ( .A(n9932), .B(n9931), .C(n9930), .CO(n9964), .S(n9971) );
CMPR32X2TS U1053 ( .A(n9769), .B(n9768), .C(n9767), .CO(
DP_OP_342J35_126_4270_n141), .S(DP_OP_342J35_126_4270_n142) );
CMPR32X2TS U1054 ( .A(n9901), .B(n9900), .C(n9899), .CO(n9897), .S(n9916) );
CMPR32X2TS U1055 ( .A(n3009), .B(n3008), .C(n3007), .CO(n3011), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[2]) );
NOR2X1TS U1056 ( .A(n10245), .B(n2170), .Y(n2146) );
NAND2X2TS U1057 ( .A(Op_MX[39]), .B(n7477), .Y(n9575) );
CMPR32X2TS U1058 ( .A(n2126), .B(n2125), .C(n2124), .CO(n2117), .S(n2147) );
CMPR32X2TS U1059 ( .A(n9637), .B(n7429), .C(n9538), .CO(n9521), .S(n9539) );
CMPR32X2TS U1060 ( .A(n4412), .B(n4411), .C(n4410), .CO(n4407), .S(n5376) );
CMPR32X2TS U1061 ( .A(n2716), .B(n2715), .C(n2714), .CO(n10028), .S(n2726)
);
CMPR32X2TS U1062 ( .A(n10011), .B(n10010), .C(n10009), .CO(n10042), .S(
n10047) );
CMPR32X2TS U1063 ( .A(n4946), .B(n4945), .C(n4944), .CO(n4965), .S(n4949) );
CMPR32X2TS U1064 ( .A(n1878), .B(n1877), .C(n1876), .CO(n10252), .S(n1990)
);
CMPR32X2TS U1065 ( .A(n5292), .B(n5291), .C(n5290), .CO(n5375), .S(n5544) );
CMPR32X2TS U1066 ( .A(n2787), .B(n2786), .C(n2785), .CO(n2780), .S(n2965) );
CMPR32X2TS U1067 ( .A(n9940), .B(n9939), .C(n9938), .CO(n9931), .S(n9987) );
CMPR32X2TS U1068 ( .A(n9580), .B(n9604), .C(n9540), .CO(n9519), .S(n9541) );
CMPR32X2TS U1069 ( .A(n10202), .B(n10201), .C(n10200), .CO(n10192), .S(
n10236) );
CMPR32X2TS U1070 ( .A(n2754), .B(n2753), .C(n2752), .CO(n2756), .S(n2779) );
CMPR32X2TS U1071 ( .A(n6058), .B(n6057), .C(n6056), .CO(n6088), .S(n6074) );
CMPR32X2TS U1072 ( .A(n2722), .B(n2721), .C(n2720), .CO(n2724), .S(n2776) );
CMPR32X2TS U1073 ( .A(n10008), .B(n10007), .C(n10006), .CO(n10024), .S(
n10043) );
CMPR32X2TS U1074 ( .A(n10142), .B(n10141), .C(n10140), .CO(n10134), .S(
n10183) );
CMPR32X2TS U1075 ( .A(n2091), .B(n2090), .C(n2089), .CO(n2102), .S(n2115) );
CMPR32X2TS U1076 ( .A(n10005), .B(n10004), .C(n10003), .CO(n10044), .S(
n10029) );
CMPR32X2TS U1077 ( .A(n6015), .B(n6014), .C(n6013), .CO(n6090), .S(n5972) );
CMPR32X2TS U1078 ( .A(n9025), .B(n9024), .C(n9023), .CO(n9020), .S(n9085) );
CMPR32X2TS U1079 ( .A(n6021), .B(n6020), .C(n6019), .CO(n6051), .S(n6018) );
CMPR32X2TS U1080 ( .A(n6774), .B(n6773), .C(n6772), .CO(n6779), .S(n6942) );
CMPR32X2TS U1081 ( .A(n3574), .B(n3573), .C(n3572), .CO(n3589), .S(n3570) );
CMPR32X2TS U1082 ( .A(n2156), .B(n2155), .C(n2154), .CO(n2127), .S(n3919) );
CMPR32X2TS U1083 ( .A(n9952), .B(n9951), .C(n9950), .CO(n9973), .S(n9985) );
CMPR32X2TS U1084 ( .A(n9990), .B(n9989), .C(n9988), .CO(n10001), .S(n10027)
);
CMPR32X2TS U1085 ( .A(n2494), .B(n2493), .C(n2492), .CO(n2623), .S(n2760) );
CMPR32X2TS U1086 ( .A(n8754), .B(n9773), .C(n9772), .CO(
DP_OP_342J35_126_4270_n153), .S(DP_OP_342J35_126_4270_n154) );
CMPR32X2TS U1087 ( .A(n6048), .B(n6047), .C(n6046), .CO(n6049), .S(n6016) );
CMPR32X2TS U1088 ( .A(n2159), .B(n2158), .C(n2157), .CO(n2153), .S(n5379) );
CMPR32X2TS U1089 ( .A(n6233), .B(n6086), .C(n6085), .CO(n6103), .S(n6078) );
CMPR32X2TS U1090 ( .A(n4963), .B(n4962), .C(n4961), .CO(n4986), .S(n4967) );
CMPR32X2TS U1091 ( .A(n6054), .B(n6053), .C(n6052), .CO(n6077), .S(n6072) );
CMPR32X2TS U1092 ( .A(n7623), .B(n7622), .C(n7621), .CO(n9713), .S(n8419) );
CMPR32X2TS U1093 ( .A(n10220), .B(n10219), .C(n10218), .CO(n10228), .S(
n10250) );
CMPR32X2TS U1094 ( .A(n9914), .B(n9913), .C(n9912), .CO(n9917), .S(n9930) );
CMPR32X2TS U1095 ( .A(n3622), .B(n3621), .C(n3620), .CO(n3630), .S(n3588) );
CMPR32X2TS U1096 ( .A(n4591), .B(n4590), .C(n4589), .CO(n10152), .S(n10173)
);
CMPR32X2TS U1097 ( .A(n4936), .B(n4935), .C(n4934), .CO(n4960), .S(n4947) );
CMPR32X2TS U1098 ( .A(n2790), .B(n2789), .C(n2788), .CO(n2783), .S(n2964) );
ADDHXLTS U1099 ( .A(n9764), .B(n9763), .CO(n7337), .S(n9769) );
NOR2XLTS U1100 ( .A(n10195), .B(n2170), .Y(n2152) );
NOR2X1TS U1101 ( .A(n3854), .B(n3841), .Y(n3536) );
NAND2X1TS U1102 ( .A(n3833), .B(n3832), .Y(n5267) );
XOR2X1TS U1103 ( .A(n4868), .B(n4319), .Y(n4408) );
CMPR32X2TS U1104 ( .A(n2026), .B(n2025), .C(n2024), .CO(n10226), .S(n2038)
);
CMPR32X2TS U1105 ( .A(n6036), .B(n6035), .C(n6034), .CO(n6073), .S(n6048) );
CMPR32X2TS U1106 ( .A(n9984), .B(n9983), .C(n9982), .CO(n10006), .S(n10011)
);
CMPR32X2TS U1107 ( .A(n4941), .B(n4940), .C(n4939), .CO(n4961), .S(n4945) );
CMPR32X2TS U1108 ( .A(n9981), .B(n9980), .C(n9979), .CO(n9986), .S(n10007)
);
CMPR32X2TS U1109 ( .A(n9958), .B(n9957), .C(n9956), .CO(n9951), .S(n9989) );
CMPR32X2TS U1110 ( .A(n9584), .B(n9608), .C(n9551), .CO(n9540), .S(n9552) );
CMPR32X2TS U1111 ( .A(n2740), .B(n2739), .C(n2738), .CO(n2721), .S(n2782) );
CMPR32X2TS U1112 ( .A(n2445), .B(n2444), .C(n2443), .CO(n2494), .S(n2757) );
CMPR32X2TS U1113 ( .A(n2751), .B(n2750), .C(n2749), .CO(n2753), .S(n2785) );
CMPR32X2TS U1114 ( .A(n6045), .B(n6044), .C(n6043), .CO(n6052), .S(n6020) );
CMPR32X2TS U1115 ( .A(n2678), .B(n2677), .C(n2676), .CO(n10003), .S(n2715)
);
CMPR32X2TS U1116 ( .A(n2697), .B(n2696), .C(n2695), .CO(n2716), .S(n2725) );
CMPR32X2TS U1117 ( .A(n2068), .B(n2067), .C(n2066), .CO(n2087), .S(n2125) );
CMPR32X2TS U1118 ( .A(n2065), .B(n2064), .C(n2063), .CO(n2126), .S(n2154) );
CMPR32X2TS U1119 ( .A(n3625), .B(n3624), .C(n3623), .CO(n3628), .S(n3621) );
CMPR32X2TS U1120 ( .A(n2044), .B(n2043), .C(n2042), .CO(n2090), .S(n2128) );
CMPR32X2TS U1121 ( .A(n6012), .B(n6011), .C(n6010), .CO(n6046), .S(n6015) );
CMPR32X2TS U1122 ( .A(n5992), .B(n5991), .C(n5990), .CO(n6017), .S(n6013) );
CMPR32X2TS U1123 ( .A(n3587), .B(n3586), .C(n3585), .CO(n3620), .S(n3573) );
CMPR32X2TS U1124 ( .A(n10199), .B(n10198), .C(n10197), .CO(n10237), .S(
n10224) );
CMPR32X2TS U1125 ( .A(n2047), .B(n2046), .C(n2045), .CO(n1877), .S(n2089) );
CMPR32X2TS U1126 ( .A(n9037), .B(n6703), .C(n6702), .CO(n6773), .S(n6945) );
CMPR32X2TS U1127 ( .A(n6062), .B(n6061), .C(n6060), .CO(n6079), .S(n6054) );
CMPR32X2TS U1128 ( .A(n6070), .B(n6069), .C(n6068), .CO(n6086), .S(n6058) );
CMPR32X2TS U1129 ( .A(n5300), .B(n5299), .C(n5298), .CO(n5292), .S(n5365) );
CMPR32X2TS U1130 ( .A(n2793), .B(n2792), .C(n2791), .CO(n2786), .S(n2954) );
NAND2X1TS U1131 ( .A(n8108), .B(n8107), .Y(n8191) );
NAND2X1TS U1132 ( .A(n3532), .B(n3531), .Y(n3855) );
CMPR32X2TS U1133 ( .A(n5875), .B(n5874), .C(n5873), .CO(n5971), .S(n5970) );
CMPR32X2TS U1134 ( .A(n9978), .B(n9977), .C(n9976), .CO(n10008), .S(n10004)
);
CMPR32X2TS U1135 ( .A(n10164), .B(n10163), .C(n10162), .CO(n10140), .S(
n10202) );
CMPR32X2TS U1136 ( .A(n2897), .B(n2896), .C(n2895), .CO(n9902), .S(n9933) );
NOR2X1TS U1137 ( .A(DP_OP_342J35_126_4270_n225), .B(
DP_OP_342J35_126_4270_n237), .Y(n7168) );
CMPR32X2TS U1138 ( .A(n9716), .B(n9715), .C(n9714), .CO(n7622), .S(
DP_OP_344J35_128_4078_n108) );
CMPR32X2TS U1139 ( .A(n1996), .B(n1995), .C(n1994), .CO(n10242), .S(n1876)
);
NOR2X1TS U1140 ( .A(n2942), .B(n2940), .Y(n2861) );
INVX2TS U1141 ( .A(n1883), .Y(n10247) );
AOI21X2TS U1142 ( .A0(n4303), .A1(n4376), .B0(n4302), .Y(n4868) );
XNOR2X1TS U1143 ( .A(n3853), .B(n3826), .Y(n3833) );
CMPR32X2TS U1144 ( .A(Op_MY[38]), .B(Op_MY[51]), .C(n2978), .CO(n7434), .S(
n9593) );
CMPR32X2TS U1145 ( .A(n2700), .B(n2699), .C(n2698), .CO(n2697), .S(n2722) );
CMPR32X2TS U1146 ( .A(n2748), .B(n2747), .C(n2746), .CO(n2751), .S(n2791) );
CMPR32X2TS U1147 ( .A(n2032), .B(n2031), .C(n2030), .CO(n2068), .S(n2064) );
CMPR32X2TS U1148 ( .A(n2162), .B(n2161), .C(n2160), .CO(n2112), .S(n5378) );
CMPR32X2TS U1149 ( .A(n2497), .B(n2496), .C(n2495), .CO(n2619), .S(n2492) );
CMPR32X2TS U1150 ( .A(n2743), .B(n2742), .C(n2741), .CO(n2740), .S(n2787) );
CMPR32X2TS U1151 ( .A(n5853), .B(n5852), .C(n5851), .CO(n5990), .S(n5875) );
CMPR32X2TS U1152 ( .A(n5872), .B(n5871), .C(n5870), .CO(n6014), .S(n5873) );
CMPR32X2TS U1153 ( .A(n2111), .B(n2110), .C(n2109), .CO(n2063), .S(n2157) );
CMPR32X2TS U1154 ( .A(n2644), .B(n2643), .C(n2642), .CO(n10005), .S(n2618)
);
CMPR32X2TS U1155 ( .A(n3577), .B(n3576), .C(n3575), .CO(n3622), .S(n3585) );
CMPR32X2TS U1156 ( .A(n6009), .B(n6008), .C(n6007), .CO(n6047), .S(n5991) );
CMPR32X2TS U1157 ( .A(n5963), .B(n5962), .C(n5961), .CO(n5969), .S(n5968) );
CMPR32X2TS U1158 ( .A(n2889), .B(n2888), .C(n2887), .CO(n9934), .S(n9975) );
CMPR32X2TS U1159 ( .A(n9911), .B(n9910), .C(n9909), .CO(n9898), .S(n9940) );
CMPR32X2TS U1160 ( .A(n6695), .B(n9029), .C(n9028), .CO(n9027), .S(n9079) );
CMPR32X2TS U1161 ( .A(n9719), .B(n9718), .C(n9717), .CO(n9715), .S(
DP_OP_344J35_128_4078_n110) );
ADDHXLTS U1162 ( .A(n1887), .B(n1927), .CO(n1883), .S(n1888) );
CMPR32X2TS U1163 ( .A(n9955), .B(n9954), .C(n9953), .CO(n9990), .S(n9983) );
CMPR32X2TS U1164 ( .A(n2665), .B(n2664), .C(n2663), .CO(n9984), .S(n2676) );
CMPR32X2TS U1165 ( .A(n9782), .B(n9781), .C(n9780), .CO(
DP_OP_342J35_126_4270_n193), .S(DP_OP_342J35_126_4270_n194) );
CMPR32X2TS U1166 ( .A(n9943), .B(n9942), .C(n9941), .CO(n9981), .S(n9978) );
CMPR32X2TS U1167 ( .A(n6033), .B(n6032), .C(n6031), .CO(n6056), .S(n6036) );
CMPR32X2TS U1168 ( .A(n5989), .B(n5988), .C(n5987), .CO(n6019), .S(n6010) );
CMPR32X2TS U1169 ( .A(n7494), .B(n2968), .C(DP_OP_341J35_125_6458_n267),
.CO(n9553), .S(n7495) );
CMPR32X2TS U1170 ( .A(n6030), .B(n6029), .C(n6028), .CO(n6057), .S(n6044) );
CMPR32X2TS U1171 ( .A(n7492), .B(n7491), .C(n7490), .CO(n9551), .S(n7493) );
CMPR32X2TS U1172 ( .A(n4443), .B(n4442), .C(n4441), .CO(n10174), .S(n10213)
);
CMPR32X2TS U1173 ( .A(n3584), .B(n3583), .C(n3582), .CO(n3623), .S(n3587) );
CMPR32X2TS U1174 ( .A(n2071), .B(n2070), .C(n2069), .CO(n2067), .S(n2114) );
CMPR32X2TS U1175 ( .A(n3541), .B(n3540), .C(n3539), .CO(n3571), .S(n3533) );
CMPR32X2TS U1176 ( .A(n3810), .B(n3884), .C(n3626), .CO(n3627), .S(n3624) );
CMPR32X2TS U1177 ( .A(n8123), .B(n8122), .C(n8121), .CO(n8124), .S(n8109) );
CMPR32X2TS U1178 ( .A(n2810), .B(n2809), .C(n2808), .CO(n2793), .S(n2947) );
CMPR32X2TS U1179 ( .A(n2796), .B(n2795), .C(n2794), .CO(n2749), .S(n2953) );
CMPR32X2TS U1180 ( .A(n5461), .B(n5460), .C(n5459), .CO(n10120), .S(n10121)
);
INVX2TS U1181 ( .A(n1841), .Y(n10195) );
INVX2TS U1182 ( .A(n1839), .Y(n10196) );
NAND2X1TS U1183 ( .A(n2937), .B(n2939), .Y(n2938) );
NAND2X1TS U1184 ( .A(n4813), .B(n4812), .Y(n5026) );
CMPR32X2TS U1185 ( .A(Op_MY[37]), .B(Op_MY[50]), .C(n2983), .CO(n2978), .S(
n9580) );
CMPR32X2TS U1186 ( .A(n5822), .B(n5821), .C(n5820), .CO(n5992), .S(n5870) );
CMPR32X2TS U1187 ( .A(Op_MX[38]), .B(Op_MX[51]), .C(n2972), .CO(n7477), .S(
n9523) );
CMPR32X2TS U1188 ( .A(n3569), .B(n3568), .C(n3567), .CO(n3572), .S(n3540) );
CMPR32X2TS U1189 ( .A(n5773), .B(n5772), .C(n5771), .CO(n6011), .S(n5872) );
CMPR32X2TS U1190 ( .A(n2710), .B(n2709), .C(n2708), .CO(n2699), .S(n2739) );
CMPR32X2TS U1191 ( .A(n5884), .B(n5883), .C(n5882), .CO(n5871), .S(n5962) );
CMPR32X2TS U1192 ( .A(n2675), .B(n2674), .C(n2673), .CO(n2642), .S(n2695) );
CMPR32X2TS U1193 ( .A(n2612), .B(n2611), .C(n2610), .CO(n9955), .S(n2644) );
CMPR32X2TS U1194 ( .A(n5838), .B(n5837), .C(n5836), .CO(n6008), .S(n5853) );
CMPR32X2TS U1195 ( .A(n5887), .B(n5886), .C(n5885), .CO(n5874), .S(n5961) );
CMPR32X2TS U1196 ( .A(n2077), .B(n2076), .C(n2075), .CO(n2065), .S(n2161) );
CMPR32X2TS U1197 ( .A(n9926), .B(n9925), .C(n9924), .CO(n9909), .S(n9958) );
CMPR32X2TS U1198 ( .A(n6714), .B(n6713), .C(n6712), .CO(n6703), .S(n6764) );
CMPR32X2TS U1199 ( .A(n4915), .B(n4914), .C(n4913), .CO(n4916), .S(n4786) );
CMPR32X2TS U1200 ( .A(n2436), .B(n2435), .C(n2434), .CO(n2497), .S(n2443) );
CMPR32X2TS U1201 ( .A(n5176), .B(n5175), .C(n5174), .CO(n10122), .S(n10123)
);
CMPR32X2TS U1202 ( .A(n8119), .B(n8118), .C(n8117), .CO(n8125), .S(n8122) );
CMPR32X2TS U1203 ( .A(n6701), .B(n9031), .C(n9030), .CO(n9029), .S(n9074) );
NAND2X1TS U1204 ( .A(n3528), .B(n3527), .Y(n3824) );
CMPR32X2TS U1205 ( .A(n2893), .B(n2892), .C(n2891), .CO(n2896), .S(n2889) );
CMPR32X2TS U1206 ( .A(n1984), .B(n1983), .C(n1982), .CO(n2031), .S(n2111) );
CMPR32X2TS U1207 ( .A(n2165), .B(n2164), .C(n2163), .CO(n2160), .S(n5286) );
CMPR32X2TS U1208 ( .A(n2807), .B(n2806), .C(n2805), .CO(n2746), .S(n2948) );
CMPR32X2TS U1209 ( .A(n9787), .B(n9786), .C(n9785), .CO(
DP_OP_342J35_126_4270_n207), .S(DP_OP_342J35_126_4270_n208) );
CMPR32X2TS U1210 ( .A(n4448), .B(n4447), .C(n4446), .CO(n4589), .S(n4442) );
CMPR32X2TS U1211 ( .A(n6006), .B(n6005), .C(n6004), .CO(n6034), .S(n6007) );
CMPR32X2TS U1212 ( .A(n2703), .B(n2702), .C(n2701), .CO(n2743), .S(n2747) );
CMPR32X2TS U1213 ( .A(n5986), .B(n5985), .C(n5984), .CO(n6043), .S(n5988) );
NAND2X1TS U1214 ( .A(n2859), .B(n2858), .Y(n2939) );
CMPR32X2TS U1215 ( .A(n3471), .B(n3470), .C(n3469), .CO(n3534), .S(n3532) );
NAND2X1TS U1216 ( .A(n3530), .B(n3529), .Y(n3683) );
CMPR32X2TS U1217 ( .A(n7122), .B(n7121), .C(n7120), .CO(n9850), .S(n9853) );
CMPR32X2TS U1218 ( .A(n8089), .B(n8088), .C(n8087), .CO(n8110), .S(n8107) );
CMPR32X2TS U1219 ( .A(n7163), .B(n7162), .C(n7161), .CO(n9765), .S(n9851) );
CMPR32X2TS U1220 ( .A(n2886), .B(n2885), .C(n2884), .CO(n9974), .S(n10021)
);
CMPR32X2TS U1221 ( .A(n5966), .B(n5965), .C(n5964), .CO(n5967), .S(n5959) );
CMPR32X2TS U1222 ( .A(n2168), .B(n2167), .C(n2166), .CO(n2109), .S(n5285) );
CMPR32X2TS U1223 ( .A(n3579), .B(n3580), .C(n3578), .CO(n3625), .S(n3577) );
CMPR32X2TS U1224 ( .A(n9722), .B(n9721), .C(n9720), .CO(n9717), .S(
DP_OP_344J35_128_4078_n112) );
CMPR32X2TS U1225 ( .A(n5977), .B(n5976), .C(n5975), .CO(n6144), .S(n6140) );
CMPR32X2TS U1226 ( .A(n6039), .B(n6038), .C(n6037), .CO(n6062), .S(n6033) );
INVX2TS U1227 ( .A(n1846), .Y(n10166) );
ADDHXLTS U1228 ( .A(n2616), .B(n2615), .CO(n2614), .S(n2617) );
INVX4TS U1229 ( .A(n1859), .Y(n10189) );
INVX4TS U1230 ( .A(n1853), .Y(n10191) );
XNOR2X1TS U1231 ( .A(n4809), .B(n4808), .Y(n4813) );
CMPR32X2TS U1232 ( .A(Op_MY[36]), .B(Op_MY[49]), .C(n2982), .CO(n2983), .S(
n9584) );
CMPR32X2TS U1233 ( .A(n1933), .B(n1932), .C(n1931), .CO(n1824), .S(n2020) );
CMPR32X2TS U1234 ( .A(n5869), .B(n5868), .C(n5867), .CO(n5851), .S(n5885) );
CMPR32X2TS U1235 ( .A(n5807), .B(n5806), .C(n5805), .CO(n5989), .S(n5822) );
CMPR32X2TS U1236 ( .A(n2085), .B(n2084), .C(n2083), .CO(n2075), .S(n2163) );
CMPR32X2TS U1237 ( .A(n2671), .B(n2670), .C(n2669), .CO(n2674), .S(n2698) );
CMPR32X2TS U1238 ( .A(n3508), .B(n3507), .C(n3506), .CO(n3539), .S(n3469) );
CMPR32X2TS U1239 ( .A(n2707), .B(n2706), .C(n2705), .CO(n2708), .S(n2741) );
CMPR32X2TS U1240 ( .A(n5856), .B(n5855), .C(n5854), .CO(n5820), .S(n5887) );
CMPR32X2TS U1241 ( .A(n7125), .B(n7124), .C(n7123), .CO(n7162), .S(n7122) );
CMPR32X2TS U1242 ( .A(n2456), .B(n2455), .C(n2454), .CO(n2702), .S(n2806) );
CMPR32X2TS U1243 ( .A(n5913), .B(n5912), .C(n5911), .CO(n5886), .S(n5965) );
CMPR32X2TS U1244 ( .A(n2609), .B(n2608), .C(n2607), .CO(n2663), .S(n2673) );
CMPR32X2TS U1245 ( .A(n5931), .B(n5930), .C(n5929), .CO(n5966), .S(n5956) );
CMPR32X2TS U1246 ( .A(n1880), .B(n1879), .C(n3500), .CO(n1887), .S(n1840) );
CMPR32X2TS U1247 ( .A(n2883), .B(n2882), .C(n2881), .CO(n2887), .S(n2884) );
CMPR32X2TS U1248 ( .A(n8102), .B(n8101), .C(n8100), .CO(n8121), .S(n8088) );
CMPR32X2TS U1249 ( .A(n4895), .B(n4894), .C(n4893), .CO(n4932), .S(n4913) );
CMPR32X2TS U1250 ( .A(n2662), .B(n2661), .C(n2660), .CO(n9942), .S(n2612) );
CMPR32X2TS U1251 ( .A(n5309), .B(n5308), .C(n5307), .CO(n5306), .S(n5357) );
CMPR32X2TS U1252 ( .A(n2875), .B(n2874), .C(n2873), .CO(n10002), .S(n10041)
);
CMPR32X2TS U1253 ( .A(n8065), .B(n8064), .C(n8063), .CO(n8108), .S(n8105) );
CMPR32X2TS U1254 ( .A(n4784), .B(n4783), .C(n4782), .CO(n4785), .S(n4753) );
CMPR32X2TS U1255 ( .A(Op_MY[50]), .B(n8734), .C(n8733), .CO(n9872), .S(n9775) );
CMPR32X2TS U1256 ( .A(n5834), .B(n5833), .C(n5832), .CO(n6006), .S(n5836) );
ADDHXLTS U1257 ( .A(n1847), .B(n1898), .CO(n1846), .S(n1848) );
CMPR32X2TS U1258 ( .A(n3511), .B(n3510), .C(n3509), .CO(n3531), .S(n3530) );
CMPR32X2TS U1259 ( .A(n6780), .B(n9033), .C(n9032), .CO(n9031), .S(n9072) );
CMPR32X2TS U1260 ( .A(n5180), .B(n5179), .C(n5178), .CO(n5460), .S(n5175) );
NAND2X1TS U1261 ( .A(n8104), .B(n8103), .Y(n8335) );
ADDHXLTS U1262 ( .A(n9887), .B(n9886), .CO(n9924), .S(n9943) );
CMPR32X2TS U1263 ( .A(n2183), .B(n2182), .C(n2181), .CO(n2165), .S(n5371) );
CMPR32X2TS U1264 ( .A(n2804), .B(n2803), .C(n2802), .CO(n2805), .S(n2933) );
CMPR32X2TS U1265 ( .A(n5916), .B(n5915), .C(n5914), .CO(n5963), .S(n5964) );
CMPR32X2TS U1266 ( .A(n3544), .B(n3543), .C(n3542), .CO(n3574), .S(n3567) );
CMPR32X2TS U1267 ( .A(n5928), .B(n5927), .C(n5926), .CO(n5958), .S(n5957) );
CMPR32X2TS U1268 ( .A(n3554), .B(n3553), .C(n3552), .CO(n3586), .S(n3569) );
CMPR32X2TS U1269 ( .A(n7113), .B(n7112), .C(n7111), .CO(n9852), .S(n9854) );
CMPR32X2TS U1270 ( .A(n4395), .B(n4394), .C(n4393), .CO(n10214), .S(n10260)
);
CMPR32X2TS U1271 ( .A(n5841), .B(n5840), .C(n5839), .CO(n6139), .S(n6127) );
CMPR32X2TS U1272 ( .A(n6003), .B(n6002), .C(n6001), .CO(n6031), .S(n5984) );
CMPR32X2TS U1273 ( .A(n4892), .B(n4891), .C(n4890), .CO(n4933), .S(n4915) );
CMPR32X2TS U1274 ( .A(n7384), .B(n7383), .C(n7382), .CO(n9774), .S(n9779) );
CMPR32X2TS U1275 ( .A(n9890), .B(n9889), .C(n9888), .CO(n10117), .S(n9882)
);
CMPR32X2TS U1276 ( .A(n6722), .B(n6721), .C(n6720), .CO(n6713), .S(n6762) );
CMPR32X2TS U1277 ( .A(n9725), .B(n9724), .C(n9723), .CO(n9721), .S(
DP_OP_344J35_128_4078_n114) );
NOR2X1TS U1278 ( .A(n3528), .B(n3527), .Y(n3680) );
ADDHXLTS U1279 ( .A(n2432), .B(n2472), .CO(n2431), .S(n2433) );
CMPR32X2TS U1280 ( .A(n1936), .B(n1935), .C(n1934), .CO(n1931), .S(n1981) );
CMPR32X2TS U1281 ( .A(Op_MX[36]), .B(Op_MX[49]), .C(n2980), .CO(n2971), .S(
n9555) );
CMPR32X2TS U1282 ( .A(Op_MY[35]), .B(Op_MY[48]), .C(n2977), .CO(n2982), .S(
n7490) );
CMPR32X2TS U1283 ( .A(n4761), .B(n4760), .C(n4759), .CO(n4914), .S(n4782) );
CMPR32X2TS U1284 ( .A(n9797), .B(n9796), .C(n9795), .CO(
DP_OP_342J35_126_4270_n232), .S(DP_OP_342J35_126_4270_n233) );
CMPR32X2TS U1285 ( .A(n5825), .B(n5824), .C(n5823), .CO(n5838), .S(n5854) );
CMPR32X2TS U1286 ( .A(n3468), .B(n3467), .C(n3466), .CO(n3470), .S(n3509) );
CMPR32X2TS U1287 ( .A(n1967), .B(n1966), .C(n1965), .CO(n1980), .S(n2076) );
CMPR32X2TS U1288 ( .A(n3474), .B(n3473), .C(n3472), .CO(n3541), .S(n3506) );
CMPR32X2TS U1289 ( .A(n4781), .B(n4780), .C(n4779), .CO(n4893), .S(n4784) );
CMPR32X2TS U1290 ( .A(n5919), .B(n5918), .C(n5917), .CO(n5912), .S(n5928) );
CMPR32X2TS U1291 ( .A(n5878), .B(n5877), .C(n5876), .CO(n5869), .S(n5916) );
CMPR32X2TS U1292 ( .A(n5881), .B(n5880), .C(n5879), .CO(n5883), .S(n5915) );
CMPR32X2TS U1293 ( .A(n3490), .B(n3489), .C(n3488), .CO(n3568), .S(n3508) );
CMPR32X2TS U1294 ( .A(n5155), .B(n5154), .C(n5153), .CO(n5174), .S(n5145) );
CMPR32X2TS U1295 ( .A(n3456), .B(n3455), .C(n3454), .CO(n3471), .S(n3511) );
CMPR32X2TS U1296 ( .A(n1843), .B(n1842), .C(n3429), .CO(n1879), .S(n1847) );
CMPR32X2TS U1297 ( .A(n5850), .B(n5849), .C(n5848), .CO(n5771), .S(n5867) );
CMPR32X2TS U1298 ( .A(n8092), .B(n8091), .C(n8090), .CO(n8123), .S(n8100) );
CMPR32X2TS U1299 ( .A(n4713), .B(n4712), .C(n4711), .CO(n4752), .S(n4751) );
CMPR32X2TS U1300 ( .A(n3523), .B(n3522), .C(n3521), .CO(n3529), .S(n3528) );
CMPR32X2TS U1301 ( .A(n1978), .B(n1977), .C(n1976), .CO(n1984), .S(n2084) );
CMPR32X2TS U1302 ( .A(Op_MY[48]), .B(n8736), .C(n8735), .CO(n8752), .S(n8733) );
CMPR32X2TS U1303 ( .A(n5934), .B(n5933), .C(n5932), .CO(n5926), .S(n5953) );
CMPR32X2TS U1304 ( .A(n4317), .B(n4316), .C(n4315), .CO(n10243), .S(n10280)
);
CMPR32X2TS U1305 ( .A(n7110), .B(n7109), .C(n7108), .CO(n9855), .S(n9856) );
CMPR32X2TS U1306 ( .A(n1148), .B(n7379), .C(Op_MY[49]), .CO(n8734), .S(n7383) );
CMPR32X2TS U1307 ( .A(n5716), .B(n5715), .C(n5714), .CO(n5986), .S(n5807) );
CMPR32X2TS U1308 ( .A(n5776), .B(n5775), .C(n5774), .CO(n5839), .S(n6124) );
CMPR32X2TS U1309 ( .A(n2572), .B(n2571), .C(n2570), .CO(n2611), .S(n2609) );
CMPR32X2TS U1310 ( .A(n2569), .B(n2568), .C(n2567), .CO(n2669), .S(n2712) );
CMPR32X2TS U1311 ( .A(n2879), .B(n2878), .C(n2877), .CO(n2892), .S(n2882) );
CMPR32X2TS U1312 ( .A(n2177), .B(n2176), .C(n2175), .CO(n2183), .S(n4424) );
CMPR32X2TS U1313 ( .A(n4403), .B(n4402), .C(n4401), .CO(n4441), .S(n4393) );
CMPR32X2TS U1314 ( .A(n7119), .B(n7118), .C(n7117), .CO(n7120), .S(n7111) );
CMPR32X2TS U1315 ( .A(n2865), .B(n2864), .C(n2863), .CO(n2885), .S(n2873) );
CMPR32X2TS U1316 ( .A(n5744), .B(n5743), .C(n5742), .CO(n5976), .S(n5840) );
CMPR32X2TS U1317 ( .A(n2180), .B(n2179), .C(n2178), .CO(n2083), .S(n5372) );
CMPR32X2TS U1318 ( .A(n4909), .B(n4908), .C(n4907), .CO(n4948), .S(n4895) );
CMPR32X2TS U1319 ( .A(n8086), .B(n8085), .C(n8084), .CO(n8087), .S(n8064) );
CMPR32X2TS U1320 ( .A(n6027), .B(n6026), .C(n6025), .CO(n6228), .S(n6225) );
CMPR32X2TS U1321 ( .A(n3563), .B(n3562), .C(n3561), .CO(n3576), .S(n3553) );
CMPR32X2TS U1322 ( .A(n6065), .B(n6064), .C(n6063), .CO(n6084), .S(n6227) );
CMPR32X2TS U1323 ( .A(n3566), .B(n3565), .C(n3564), .CO(n3575), .S(n3543) );
CMPR32X2TS U1324 ( .A(n5317), .B(n5316), .C(n5315), .CO(n5308), .S(n5355) );
CMPR32X2TS U1325 ( .A(n6728), .B(n6727), .C(n6726), .CO(n6721), .S(n6759) );
CMPR32X2TS U1326 ( .A(n6774), .B(n9035), .C(n9034), .CO(n9033), .S(n9068) );
CMPR32X2TS U1327 ( .A(n7347), .B(n7346), .C(n7345), .CO(n9778), .S(n9784) );
CMPR32X2TS U1328 ( .A(n6877), .B(n6876), .C(n6875), .CO(n9883), .S(n9885) );
ADDHXLTS U1329 ( .A(n2409), .B(n2579), .CO(n2408), .S(n2410) );
XOR2X1TS U1330 ( .A(n839), .B(n2606), .Y(n2442) );
INVX4TS U1331 ( .A(n2427), .Y(n9945) );
CMPR32X2TS U1332 ( .A(n1807), .B(n1806), .C(n1805), .CO(n3905), .S(n3904) );
CMPR32X2TS U1333 ( .A(n3505), .B(n3504), .C(n3503), .CO(n3542), .S(n3473) );
CMPR32X2TS U1334 ( .A(n2011), .B(n2010), .C(n2009), .CO(n5144), .S(n1997) );
CMPR32X2TS U1335 ( .A(n3520), .B(n3519), .C(n3518), .CO(n3510), .S(n3521) );
CMPR32X2TS U1336 ( .A(n4724), .B(n4723), .C(n4722), .CO(n4712), .S(n4725) );
CMPR32X2TS U1337 ( .A(Op_MX[12]), .B(Op_MX[26]), .C(n2428), .CO(n2613), .S(
n2409) );
CMPR32X2TS U1338 ( .A(n2668), .B(n2667), .C(n2666), .CO(n2567), .S(n2705) );
CMPR32X2TS U1339 ( .A(n3453), .B(n3452), .C(n3451), .CO(n3472), .S(n3454) );
CMPR32X2TS U1340 ( .A(n1970), .B(n1969), .C(n1968), .CO(n1965), .S(n2085) );
CMPR32X2TS U1341 ( .A(n4710), .B(n4709), .C(n4708), .CO(n4783), .S(n4711) );
CMPR32X2TS U1342 ( .A(n2827), .B(n2826), .C(n2825), .CO(n2874), .S(n2838) );
CMPR32X2TS U1343 ( .A(n3514), .B(n3513), .C(n3512), .CO(n3466), .S(n3523) );
CMPR32X2TS U1344 ( .A(n4696), .B(n4695), .C(n4694), .CO(n4759), .S(n4713) );
CMPR32X2TS U1345 ( .A(n4775), .B(n4774), .C(n4773), .CO(n4907), .S(n4781) );
CMPR32X2TS U1346 ( .A(n5866), .B(n5865), .C(n5864), .CO(n5881), .S(n5917) );
CMPR32X2TS U1347 ( .A(n5922), .B(n5921), .C(n5920), .CO(n5918), .S(n5934) );
CMPR32X2TS U1348 ( .A(n4778), .B(n4777), .C(n4776), .CO(n4894), .S(n4760) );
CMPR32X2TS U1349 ( .A(n2872), .B(n2871), .C(n2870), .CO(n2881), .S(n2863) );
CMPR32X2TS U1350 ( .A(n8068), .B(n8067), .C(n8066), .CO(n8089), .S(n8085) );
CMPR32X2TS U1351 ( .A(n5757), .B(n5756), .C(n5755), .CO(n5841), .S(n5775) );
CMPR32X2TS U1352 ( .A(n2566), .B(n2565), .C(n2564), .CO(n2570), .S(n2671) );
CMPR32X2TS U1353 ( .A(n4282), .B(n4281), .C(n4280), .CO(n10270), .S(n4301)
);
CMPR32X2TS U1354 ( .A(n6881), .B(n6880), .C(n6879), .CO(n9888), .S(n6877) );
ADDHXLTS U1355 ( .A(n1778), .B(n1897), .CO(n1763), .S(n1779) );
CMPR32X2TS U1356 ( .A(n9037), .B(n9036), .C(n7573), .CO(n9035), .S(n9067) );
CMPR32X2TS U1357 ( .A(n3493), .B(n3492), .C(n3491), .CO(n3544), .S(n3490) );
CMPR32X2TS U1358 ( .A(n5844), .B(n5843), .C(n5842), .CO(n5823), .S(n5877) );
CMPR32X2TS U1359 ( .A(n8032), .B(n8031), .C(n8030), .CO(n8106), .S(n8104) );
CMPR32X2TS U1360 ( .A(n2647), .B(n2646), .C(n2645), .CO(n6869), .S(n6868) );
CMPR32X2TS U1361 ( .A(n9807), .B(n9806), .C(n9805), .CO(
DP_OP_342J35_126_4270_n253), .S(DP_OP_342J35_126_4270_n254) );
CMPR32X2TS U1362 ( .A(n7116), .B(n7115), .C(n7114), .CO(n7123), .S(n7119) );
CMPR32X2TS U1363 ( .A(n5910), .B(n5909), .C(n5908), .CO(n5879), .S(n5930) );
CMPR32X2TS U1364 ( .A(n5925), .B(n5924), .C(n5923), .CO(n5931), .S(n5933) );
CMPR32X2TS U1365 ( .A(n4307), .B(n4306), .C(n4305), .CO(n4394), .S(n4315) );
CMPR32X2TS U1366 ( .A(n6024), .B(n6023), .C(n6022), .CO(n6064), .S(n6027) );
CMPR32X2TS U1367 ( .A(n7101), .B(n7100), .C(n7099), .CO(n7112), .S(n7108) );
CMPR32X2TS U1368 ( .A(n3439), .B(n3438), .C(n3437), .CO(n3507), .S(n3468) );
CMPR32X2TS U1369 ( .A(n4400), .B(n4399), .C(n4398), .CO(n4447), .S(n4402) );
CMPR32X2TS U1370 ( .A(n5787), .B(n5786), .C(n5785), .CO(n5848), .S(n5880) );
CMPR32X2TS U1371 ( .A(n4906), .B(n4905), .C(n4904), .CO(n4944), .S(n4908) );
CMPR32X2TS U1372 ( .A(n8074), .B(n8073), .C(n8072), .CO(n8101), .S(n8086) );
CMPR32X2TS U1373 ( .A(n8099), .B(n8098), .C(n8097), .CO(n8117), .S(n8090) );
CMPR32X2TS U1374 ( .A(n5152), .B(n5151), .C(n5150), .CO(n5178), .S(n5154) );
NOR2X1TS U1375 ( .A(n4565), .B(n4564), .Y(n4744) );
CMPR32X2TS U1376 ( .A(n5828), .B(n5827), .C(n5826), .CO(n5834), .S(n5824) );
CMPR32X2TS U1377 ( .A(n2626), .B(n2625), .C(n2624), .CO(n2858), .S(n2857) );
CMPR32X2TS U1378 ( .A(n7145), .B(n7144), .C(n7143), .CO(n9857), .S(n9858) );
CMPR32X2TS U1379 ( .A(n7151), .B(n7150), .C(n7149), .CO(n9859), .S(n9860) );
CMPR32X2TS U1380 ( .A(n6736), .B(n6735), .C(n6734), .CO(n6726), .S(n6757) );
CMPR32X2TS U1381 ( .A(n1148), .B(n7344), .C(n7343), .CO(n7382), .S(n7345) );
CMPR32X2TS U1382 ( .A(n5981), .B(n5980), .C(n5979), .CO(n6226), .S(n6224) );
CMPR32X2TS U1383 ( .A(n6864), .B(n6863), .C(n6862), .CO(n9884), .S(n6870) );
CMPR32X2TS U1384 ( .A(n7324), .B(n7323), .C(n7322), .CO(n9783), .S(n9873) );
CMPR32X2TS U1385 ( .A(n5712), .B(n5711), .C(n5710), .CO(n5806), .S(n5849) );
CMPR32X2TS U1386 ( .A(n5323), .B(n5322), .C(n5321), .CO(n5317), .S(n5352) );
ADDHXLTS U1387 ( .A(n2555), .B(n2554), .CO(n2660), .S(n2571) );
NOR2X1TS U1388 ( .A(n3776), .B(n3775), .Y(n4427) );
NAND2X1TS U1389 ( .A(n3776), .B(n3775), .Y(n4428) );
NAND2X1TS U1390 ( .A(n8300), .B(n8299), .Y(n8631) );
NAND2X1TS U1391 ( .A(n8301), .B(n914), .Y(n8454) );
NAND2X1TS U1392 ( .A(n3778), .B(n3777), .Y(n4432) );
INVX4TS U1393 ( .A(n2295), .Y(n9961) );
AOI21X1TS U1394 ( .A0(n931), .A1(n2441), .B0(n2440), .Y(n2606) );
CMPR32X2TS U1395 ( .A(n1729), .B(n1728), .C(n1727), .CO(n1807), .S(n3901) );
CMPR32X2TS U1396 ( .A(n4707), .B(n4706), .C(n4705), .CO(n4710), .S(n4722) );
CMPR32X2TS U1397 ( .A(n4269), .B(n4268), .C(n4267), .CO(n4316), .S(n4280) );
CMPR32X2TS U1398 ( .A(n2830), .B(n2829), .C(n2828), .CO(n2864), .S(n2825) );
CMPR32X2TS U1399 ( .A(n1836), .B(n1835), .C(n3347), .CO(n1842), .S(n1778) );
CMPR32X2TS U1400 ( .A(Op_MY[47]), .B(n7319), .C(n7318), .CO(n7346), .S(n7322) );
CMPR32X2TS U1401 ( .A(n1816), .B(n1815), .C(n1814), .CO(n2011), .S(n1813) );
CMPR32X2TS U1402 ( .A(Op_MX[34]), .B(Op_MX[47]), .C(n2976), .CO(n2969), .S(
n9636) );
CMPR32X2TS U1403 ( .A(n4721), .B(n4720), .C(n4719), .CO(n4708), .S(n4726) );
CMPR32X2TS U1404 ( .A(n3417), .B(n3416), .C(n3415), .CO(n3455), .S(n3512) );
CMPR32X2TS U1405 ( .A(n1942), .B(n1941), .C(n1940), .CO(n1939), .S(n1970) );
CMPR32X2TS U1406 ( .A(n1973), .B(n1972), .C(n1971), .CO(n1968), .S(n2180) );
CMPR32X2TS U1407 ( .A(n2008), .B(n2007), .C(n2006), .CO(n5153), .S(n2009) );
CMPR32X2TS U1408 ( .A(n6860), .B(n6859), .C(n6858), .CO(n6876), .S(n6864) );
CMPR32X2TS U1409 ( .A(n2629), .B(n2628), .C(n2627), .CO(n2840), .S(n2624) );
CMPR32X2TS U1410 ( .A(n3450), .B(n3449), .C(n3448), .CO(n3503), .S(n3451) );
CMPR32X2TS U1411 ( .A(n4742), .B(n4741), .C(n4740), .CO(n4727), .S(n4745) );
CMPR32X2TS U1412 ( .A(n2448), .B(n2447), .C(n2446), .CO(n2666), .S(n2748) );
CMPR32X2TS U1413 ( .A(n7098), .B(n7097), .C(n7096), .CO(n7110), .S(n7143) );
CMPR32X2TS U1414 ( .A(n1889), .B(n1796), .C(n1795), .CO(n1832), .S(n1787) );
CMPR32X2TS U1415 ( .A(n4764), .B(n4763), .C(n4762), .CO(n4909), .S(n4773) );
CMPR32X2TS U1416 ( .A(n8062), .B(n8061), .C(n8060), .CO(n8063), .S(n8030) );
CMPR32X2TS U1417 ( .A(n5831), .B(n5830), .C(n5829), .CO(n6223), .S(n6222) );
CMPR32X2TS U1418 ( .A(n2563), .B(n2562), .C(n2561), .CO(n2564), .S(n2569) );
CMPR32X2TS U1419 ( .A(n5779), .B(n5778), .C(n5777), .CO(n5787), .S(n5865) );
CMPR32X2TS U1420 ( .A(n3436), .B(n3435), .C(n3434), .CO(n3672), .S(n3652) );
CMPR32X2TS U1421 ( .A(n8077), .B(n8076), .C(n8075), .CO(n8092), .S(n8074) );
CMPR32X2TS U1422 ( .A(n5802), .B(n5801), .C(n5800), .CO(n5785), .S(n5908) );
CMPR32X2TS U1423 ( .A(n7154), .B(n7153), .C(n7152), .CO(n9861), .S(n9862) );
CMPR32X2TS U1424 ( .A(n3442), .B(n3441), .C(n3440), .CO(n3474), .S(n3437) );
CMPR32X2TS U1425 ( .A(n5907), .B(n5906), .C(n5905), .CO(n5864), .S(n5923) );
ADDHXLTS U1426 ( .A(n1803), .B(n1893), .CO(n1804), .S(n1802) );
CMPR32X2TS U1427 ( .A(n2658), .B(n2657), .C(n2656), .CO(n6863), .S(n2647) );
CMPR32X2TS U1428 ( .A(n4691), .B(n4690), .C(n4689), .CO(n4777), .S(n4696) );
CMPR32X2TS U1429 ( .A(n5999), .B(n5998), .C(n5997), .CO(n6025), .S(n5979) );
CMPR32X2TS U1430 ( .A(n4903), .B(n4902), .C(n4901), .CO(n4939), .S(n4905) );
CMPR32X2TS U1431 ( .A(n4314), .B(n4313), .C(n4312), .CO(n4401), .S(n4305) );
CMPR32X2TS U1432 ( .A(n5863), .B(n5862), .C(n5861), .CO(n5910), .S(n5920) );
CMPR32X2TS U1433 ( .A(n8071), .B(n8070), .C(n8069), .CO(n8102), .S(n8067) );
CMPR32X2TS U1434 ( .A(n7107), .B(n7106), .C(n7105), .CO(n7118), .S(n7101) );
CMPR32X2TS U1435 ( .A(n2869), .B(n2868), .C(n2867), .CO(n2877), .S(n2871) );
CMPR32X2TS U1436 ( .A(n1993), .B(n1992), .C(n1991), .CO(n4300), .S(n4299) );
CMPR32X2TS U1437 ( .A(n4678), .B(n4677), .C(n4676), .CO(n4761), .S(n4709) );
CMPR32X2TS U1438 ( .A(n3219), .B(n3218), .C(n3217), .CO(n3337), .S(n3336) );
CMPR32X2TS U1439 ( .A(n5940), .B(n5939), .C(n5938), .CO(n5924), .S(n6248) );
CMPR32X2TS U1440 ( .A(n6714), .B(n9038), .C(n7623), .CO(n9036), .S(n9058) );
CMPR32X2TS U1441 ( .A(n5847), .B(n5846), .C(n5845), .CO(n5774), .S(n6119) );
CMPR32X2TS U1442 ( .A(n5741), .B(n5740), .C(n5739), .CO(n5743), .S(n5756) );
CMPR32X2TS U1443 ( .A(n5811), .B(n5810), .C(n5809), .CO(n5825), .S(n5786) );
CMPR32X2TS U1444 ( .A(n3477), .B(n3476), .C(n3475), .CO(n3554), .S(n3504) );
CMPR32X2TS U1445 ( .A(n3487), .B(n3486), .C(n3485), .CO(n3676), .S(n3671) );
ADDHXLTS U1446 ( .A(n2560), .B(n2559), .CO(n2572), .S(n2565) );
CMPR32X2TS U1447 ( .A(n6744), .B(n6743), .C(n6742), .CO(n6735), .S(n6751) );
CMPR32X2TS U1448 ( .A(n5937), .B(n5936), .C(n5935), .CO(n5921), .S(n6249) );
CMPR32X2TS U1449 ( .A(n5328), .B(n5327), .C(n5326), .CO(n5323), .S(n5350) );
CMPR32X2TS U1450 ( .A(n3551), .B(n3550), .C(n3549), .CO(n3885), .S(n3675) );
CMPR32X2TS U1451 ( .A(n7299), .B(n7298), .C(n7297), .CO(n9788), .S(n9792) );
CMPR32X2TS U1452 ( .A(n7271), .B(n7270), .C(n7269), .CO(n9791), .S(n9874) );
ADDHXLTS U1453 ( .A(n2465), .B(n2470), .CO(n2464), .S(n2466) );
INVX4TS U1454 ( .A(n1777), .Y(n10246) );
CMPR32X2TS U1455 ( .A(n1831), .B(n1830), .C(n3063), .CO(n1852), .S(n1833) );
CMPR32X2TS U1456 ( .A(n3462), .B(n3461), .C(n3460), .CO(n3467), .S(n3519) );
ADDHXLTS U1457 ( .A(n2400), .B(n2471), .CO(n2399), .S(n2401) );
ADDHXLTS U1458 ( .A(n2304), .B(n2303), .CO(n2305), .S(n2296) );
INVX4TS U1459 ( .A(n2302), .Y(n9991) );
CMPR32X2TS U1460 ( .A(n1819), .B(n1818), .C(n1817), .CO(n2010), .S(n1811) );
ADDFX2TS U1461 ( .A(n4739), .B(n4738), .CI(n4737), .CO(n4748), .S(n4746) );
CMPR32X2TS U1462 ( .A(Op_MY[33]), .B(Op_MY[46]), .C(n7435), .CO(n2974), .S(
n9656) );
CMPR32X2TS U1463 ( .A(n5904), .B(n5903), .C(n5902), .CO(n5905), .S(n5938) );
CMPR32X2TS U1464 ( .A(n4718), .B(n4717), .C(n4716), .CO(n4719), .S(n4740) );
CMPR32X2TS U1465 ( .A(n4687), .B(n4686), .C(n4685), .CO(n4689), .S(n4707) );
CMPR32X2TS U1466 ( .A(n7148), .B(n7147), .C(n7146), .CO(n7096), .S(n7151) );
CMPR32X2TS U1467 ( .A(n4664), .B(n4663), .C(n4662), .CO(n4677), .S(n4705) );
CMPR32X2TS U1468 ( .A(n4733), .B(n4732), .C(n4731), .CO(n4738), .S(n4565) );
CMPR32X2TS U1469 ( .A(Op_MX[11]), .B(n2402), .C(Op_MX[25]), .CO(n2428), .S(
n2400) );
CMPR32X2TS U1470 ( .A(n1799), .B(n1798), .C(n3343), .CO(n1835), .S(n1803) );
CMPR32X2TS U1471 ( .A(n2719), .B(n2718), .C(n2717), .CO(n2730), .S(n2852) );
CMPR32X2TS U1472 ( .A(n1717), .B(n1716), .C(n1715), .CO(n1729), .S(n1760) );
CMPR32X2TS U1473 ( .A(n4736), .B(n4735), .C(n4734), .CO(n4723), .S(n4737) );
CMPR32X2TS U1474 ( .A(n2051), .B(n2050), .C(n2049), .CO(n4281), .S(n1991) );
CMPR32X2TS U1475 ( .A(n4681), .B(n4680), .C(n4679), .CO(n4778), .S(n4678) );
CMPR32X2TS U1476 ( .A(n4767), .B(n4766), .C(n4765), .CO(n4906), .S(n4762) );
CMPR32X2TS U1477 ( .A(n2633), .B(n2632), .C(n2631), .CO(n2826), .S(n2627) );
CMPR32X2TS U1478 ( .A(n5730), .B(n5729), .C(n5728), .CO(n5980), .S(n5829) );
CMPR32X2TS U1479 ( .A(n4730), .B(n4729), .C(n4728), .CO(n4739), .S(n4564) );
CMPR32X2TS U1480 ( .A(n5799), .B(n5798), .C(n5797), .CO(n5845), .S(n6117) );
CMPR32X2TS U1481 ( .A(n1794), .B(n1793), .C(n904), .CO(n1830), .S(n1796) );
CMPR32X2TS U1482 ( .A(n4272), .B(n4271), .C(n4270), .CO(n4306), .S(n4267) );
CMPR32X2TS U1483 ( .A(n3433), .B(n3432), .C(n3431), .CO(n3485), .S(n3434) );
CMPR32X2TS U1484 ( .A(n8035), .B(n8034), .C(n8033), .CO(n8065), .S(n8060) );
CMPR32X2TS U1485 ( .A(n3465), .B(n3464), .C(n3463), .CO(n3518), .S(n3526) );
CMPR32X2TS U1486 ( .A(n1755), .B(n1754), .C(n1753), .CO(n1759), .S(n3896) );
CMPR32X2TS U1487 ( .A(n2364), .B(n2363), .C(n2362), .CO(n2561), .S(n2668) );
CMPR32X2TS U1488 ( .A(n8029), .B(n8028), .C(n8027), .CO(n8103), .S(n7986) );
ADDHXLTS U1489 ( .A(n1871), .B(n1890), .CO(n1872), .S(n1870) );
CMPR32X2TS U1490 ( .A(n5859), .B(n5858), .C(n5857), .CO(n5800), .S(n5922) );
CMPR32X2TS U1491 ( .A(n2655), .B(n2654), .C(n2653), .CO(n6858), .S(n2657) );
CMPR32X2TS U1492 ( .A(n4899), .B(n4898), .C(n4897), .CO(n4937), .S(n4903) );
CMPR32X2TS U1493 ( .A(n5819), .B(n5818), .C(n5817), .CO(n6217), .S(n6216) );
CMPR32X2TS U1494 ( .A(n5760), .B(n5759), .C(n5758), .CO(n5776), .S(n5846) );
CMPR32X2TS U1495 ( .A(n5891), .B(n5890), .C(n5889), .CO(n5862), .S(n5940) );
CMPR32X2TS U1496 ( .A(n2694), .B(n2693), .C(n2692), .CO(n2626), .S(n2729) );
CMPR32X2TS U1497 ( .A(n2837), .B(n2836), .C(n2835), .CO(n2870), .S(n2828) );
CMPR32X2TS U1498 ( .A(n8059), .B(n8058), .C(n8057), .CO(n8084), .S(n8062) );
CMPR32X2TS U1499 ( .A(n5996), .B(n5995), .C(n5994), .CO(n6022), .S(n5999) );
CMPR32X2TS U1500 ( .A(n4311), .B(n4310), .C(n4309), .CO(n4398), .S(n4313) );
CMPR32X2TS U1501 ( .A(n2451), .B(n2450), .C(n2449), .CO(n2447), .S(n2454) );
CMPR32X2TS U1502 ( .A(n7095), .B(n7094), .C(n7093), .CO(n7100), .S(n7097) );
CMPR32X2TS U1503 ( .A(n5944), .B(n5943), .C(n5942), .CO(n5939), .S(n6258) );
ADDHXLTS U1504 ( .A(n5694), .B(n5693), .CO(n5810), .S(n5777) );
CMPR32X2TS U1505 ( .A(n6722), .B(n9039), .C(n9716), .CO(n9038), .S(n9056) );
CMPR32X2TS U1506 ( .A(n3360), .B(n3359), .C(n3358), .CO(n3453), .S(n3417) );
CMPR32X2TS U1507 ( .A(n2003), .B(n2002), .C(n2001), .CO(n5155), .S(n2006) );
CMPR32X2TS U1508 ( .A(n6857), .B(n6856), .C(n6855), .CO(n6879), .S(n6859) );
CMPR32X2TS U1509 ( .A(n3363), .B(n3362), .C(n3361), .CO(n3452), .S(n3416) );
CMPR32X2TS U1510 ( .A(n5709), .B(n5708), .C(n5707), .CO(n6221), .S(n6218) );
CMPR32X2TS U1511 ( .A(n7104), .B(n7103), .C(n7102), .CO(n7114), .S(n7106) );
CMPR32X2TS U1512 ( .A(n4684), .B(n4683), .C(n4682), .CO(n4775), .S(n4691) );
CMPR32X2TS U1513 ( .A(n2558), .B(n2557), .C(n2556), .CO(n6865), .S(n6850) );
CMPR32X2TS U1514 ( .A(n2548), .B(n2547), .C(n2546), .CO(n6867), .S(n6866) );
CMPR32X2TS U1515 ( .A(n3445), .B(n3444), .C(n3443), .CO(n3505), .S(n3440) );
CMPR32X2TS U1516 ( .A(n5338), .B(n5337), .C(n5336), .CO(n5328), .S(n5343) );
NAND2X1TS U1517 ( .A(n2585), .B(n2423), .Y(n2439) );
CMPR32X2TS U1518 ( .A(n3405), .B(n3404), .C(n3403), .CO(n3438), .S(n3461) );
CMPR32X2TS U1519 ( .A(n4701), .B(n4700), .C(n4699), .CO(n4706), .S(n4735) );
CMPR32X2TS U1520 ( .A(n1697), .B(n1696), .C(n1695), .CO(n1726), .S(n3895) );
CMPR32X2TS U1521 ( .A(n2691), .B(n2690), .C(n2689), .CO(n2693), .S(n2717) );
CMPR32X2TS U1522 ( .A(n4704), .B(n4703), .C(n4702), .CO(n4734), .S(n4731) );
CMPR32X2TS U1523 ( .A(n5770), .B(n5769), .C(n5768), .CO(n5758), .S(n5797) );
CMPR32X2TS U1524 ( .A(n4675), .B(n4674), .C(n4673), .CO(n4716), .S(n4729) );
CMPR32X2TS U1525 ( .A(n4658), .B(n4657), .C(n4656), .CO(n4763), .S(n4680) );
CMPR32X2TS U1526 ( .A(n5666), .B(n5665), .C(n5664), .CO(n5708), .S(n5817) );
CMPR32X2TS U1527 ( .A(n7082), .B(n7081), .C(n7080), .CO(n7093), .S(n7148) );
CMPR32X2TS U1528 ( .A(n5736), .B(n5735), .C(n5734), .CO(n5998), .S(n5730) );
CMPR32X2TS U1529 ( .A(n2543), .B(n2542), .C(n2541), .CO(n2548), .S(n2557) );
CMPR32X2TS U1530 ( .A(Op_MX[10]), .B(Op_MX[24]), .C(n2460), .CO(n2402), .S(
n2465) );
CMPR32X2TS U1531 ( .A(n1867), .B(n1866), .C(n3230), .CO(n1798), .S(n1871) );
CMPR32X2TS U1532 ( .A(n3414), .B(n3413), .C(n3412), .CO(n3513), .S(n3463) );
CMPR32X2TS U1533 ( .A(n7994), .B(n7993), .C(n7992), .CO(n8031), .S(n8027) );
CMPR32X2TS U1534 ( .A(n3189), .B(n3188), .C(n3187), .CO(n3515), .S(n3219) );
CMPR32X2TS U1535 ( .A(n7142), .B(n7141), .C(n7140), .CO(n7153), .S(n9865) );
CMPR32X2TS U1536 ( .A(n4661), .B(n4660), .C(n4659), .CO(n4679), .S(n4663) );
CMPR32X2TS U1537 ( .A(n2636), .B(n2635), .C(n2634), .CO(n2829), .S(n2631) );
CMPR32X2TS U1538 ( .A(n2537), .B(n2536), .C(n2535), .CO(n2646), .S(n2547) );
CMPR32X2TS U1539 ( .A(n8048), .B(n8047), .C(n8046), .CO(n8068), .S(n8059) );
CMPR32X2TS U1540 ( .A(n5784), .B(n5783), .C(n5782), .CO(n5859), .S(n5902) );
CMPR32X2TS U1541 ( .A(n2054), .B(n2053), .C(n2052), .CO(n4269), .S(n2050) );
CMPR32X2TS U1542 ( .A(n2080), .B(n2079), .C(n2078), .CO(n1953), .S(n2176) );
CMPR32X2TS U1543 ( .A(n4671), .B(n4670), .C(n4669), .CO(n4664), .S(n4718) );
CMPR32X2TS U1544 ( .A(n7139), .B(n7138), .C(n7137), .CO(n7146), .S(n7154) );
CMPR32X2TS U1545 ( .A(n8056), .B(n8055), .C(n8054), .CO(n8066), .S(n8034) );
CMPR32X2TS U1546 ( .A(n4655), .B(n4654), .C(n4653), .CO(n4681), .S(n4686) );
CMPR32X2TS U1547 ( .A(n7991), .B(n7990), .C(n7989), .CO(n8032), .S(n8029) );
CMPR32X2TS U1548 ( .A(n1944), .B(n3890), .C(n1943), .CO(n1749), .S(n1955) );
CMPR32X2TS U1549 ( .A(n2373), .B(n2372), .C(n2371), .CO(n2362), .S(n2448) );
CMPR32X2TS U1550 ( .A(n2834), .B(n2833), .C(n2832), .CO(n2867), .S(n2835) );
CMPR32X2TS U1551 ( .A(n4105), .B(n4104), .C(n4103), .CO(n4757), .S(n4614) );
CMPR32X2TS U1552 ( .A(n4525), .B(n4524), .C(n4523), .CO(n4733), .S(n4498) );
CMPR32X2TS U1553 ( .A(n5901), .B(n5900), .C(n5899), .CO(n5903), .S(n5942) );
CMPR32X2TS U1554 ( .A(n3402), .B(n3401), .C(n3400), .CO(n3651), .S(n3646) );
CMPR32X2TS U1555 ( .A(n2551), .B(n2550), .C(n2549), .CO(n6849), .S(n6848) );
CMPR32X2TS U1556 ( .A(n5894), .B(n5893), .C(n5892), .CO(n5890), .S(n5944) );
CMPR32X2TS U1557 ( .A(n5749), .B(n5748), .C(n5747), .CO(n5757), .S(n5759) );
CMPR32X2TS U1558 ( .A(n4770), .B(n4769), .C(n4768), .CO(n4897), .S(n4767) );
CMPR32X2TS U1559 ( .A(n5719), .B(n5718), .C(n5717), .CO(n5830), .S(n5707) );
CMPR32X2TS U1560 ( .A(n2459), .B(n2458), .C(n2457), .CO(n2449), .S(n2803) );
CMPR32X2TS U1561 ( .A(n4279), .B(n4278), .C(n4277), .CO(n4312), .S(n4270) );
CMPR32X2TS U1562 ( .A(n2596), .B(n2595), .C(n2594), .CO(n2629), .S(n2692) );
CMPR32X2TS U1563 ( .A(n7863), .B(n7862), .C(n7861), .CO(n7985), .S(n7984) );
CMPR32X2TS U1564 ( .A(n6728), .B(n9040), .C(n9719), .CO(n9039), .S(n9054) );
NAND2X1TS U1565 ( .A(n3731), .B(n3730), .Y(n3802) );
CMPR32X4TS U1566 ( .A(Op_MX[32]), .B(n881), .C(n7431), .CO(n7426), .S(n7432)
);
CMPR32X2TS U1567 ( .A(n5816), .B(n5815), .C(n5814), .CO(n6215), .S(n6214) );
CMPR32X2TS U1568 ( .A(n7092), .B(n7091), .C(n7090), .CO(n7105), .S(n7095) );
CMPR32X2TS U1569 ( .A(n4511), .B(n4510), .C(n4509), .CO(n4912), .S(n4758) );
CMPR32X2TS U1570 ( .A(n2650), .B(n2649), .C(n2648), .CO(n6860), .S(n2653) );
CMPR32X2TS U1571 ( .A(n2108), .B(n2107), .C(n2106), .CO(n2123), .S(n4293) );
CMPR32X2TS U1572 ( .A(n5951), .B(n5950), .C(n5949), .CO(n5943), .S(n6267) );
CMPR32X2TS U1573 ( .A(n5796), .B(n5795), .C(n5794), .CO(n5799), .S(n6114) );
CMPR32X2TS U1574 ( .A(n1784), .B(n1783), .C(n3052), .CO(n1793), .S(n1786) );
NOR2XLTS U1575 ( .A(n1636), .B(n1713), .Y(n1731) );
NAND2X1TS U1576 ( .A(n2576), .B(n2264), .Y(n2424) );
INVX2TS U1577 ( .A(n2615), .Y(n2890) );
NAND2X1TS U1578 ( .A(n7572), .B(n7571), .Y(n8617) );
NAND2X1TS U1579 ( .A(n8236), .B(n8235), .Y(n8615) );
OAI22X1TS U1580 ( .A0(n5182), .A1(n1737), .B0(n1636), .B1(n1949), .Y(n1739)
);
AOI21X1TS U1581 ( .A0(n1030), .A1(n2359), .B0(n2292), .Y(n2300) );
CMPR32X2TS U1582 ( .A(n3186), .B(n3185), .C(n3184), .CO(n3464), .S(n3187) );
CMPR32X2TS U1583 ( .A(Op_MX[9]), .B(Op_MX[23]), .C(n2395), .CO(n2460), .S(
n2356) );
CMPR32X2TS U1584 ( .A(n7838), .B(n7837), .C(n7836), .CO(n7992), .S(n7863) );
CMPR32X2TS U1585 ( .A(n4633), .B(n4632), .C(n4631), .CO(n4701), .S(n4674) );
CMPR32X2TS U1586 ( .A(n7860), .B(n7859), .C(n7858), .CO(n8028), .S(n7861) );
CMPR32X2TS U1587 ( .A(n8004), .B(n8003), .C(n8002), .CO(n8058), .S(n7991) );
CMPR32X2TS U1588 ( .A(n5697), .B(n5696), .C(n5695), .CO(n5664), .S(n5816) );
CMPR32X2TS U1589 ( .A(n2519), .B(n2518), .C(n2517), .CO(n2536), .S(n2541) );
CMPR32X2TS U1590 ( .A(n3222), .B(n3221), .C(n3220), .CO(n3214), .S(n3329) );
CMPR32X2TS U1591 ( .A(n3411), .B(n3410), .C(n3409), .CO(n3514), .S(n3458) );
CMPR32X2TS U1592 ( .A(n2737), .B(n2736), .C(n2735), .CO(n2734), .S(n2846) );
CMPR32X2TS U1593 ( .A(n3332), .B(n3331), .C(n3330), .CO(n3333), .S(n3325) );
CMPR32X2TS U1594 ( .A(n2094), .B(n2093), .C(n2092), .CO(n2108), .S(n4291) );
CMPR32X2TS U1595 ( .A(n2516), .B(n2515), .C(n2514), .CO(n2537), .S(n2542) );
CMPR32X2TS U1596 ( .A(n7132), .B(n7131), .C(n7130), .CO(n7138), .S(n7142) );
CMPR32X2TS U1597 ( .A(n4639), .B(n4638), .C(n4637), .CO(n4699), .S(n4673) );
CMPR32X2TS U1598 ( .A(n4652), .B(n4651), .C(n4650), .CO(n4659), .S(n4669) );
CMPR32X2TS U1599 ( .A(n4636), .B(n4635), .C(n4634), .CO(n4685), .S(n4700) );
CMPR32X2TS U1600 ( .A(n2588), .B(n2587), .C(n2586), .CO(n2595), .S(n2689) );
CMPR32X2TS U1601 ( .A(n4530), .B(n4529), .C(n4528), .CO(n4704), .S(n4523) );
CMPR32X2TS U1602 ( .A(n4536), .B(n4535), .C(n4534), .CO(n4702), .S(n4497) );
CMPR32X2TS U1603 ( .A(n8026), .B(n8025), .C(n8024), .CO(n8033), .S(n7989) );
CMPR32X2TS U1604 ( .A(n3240), .B(n3239), .C(n3238), .CO(n3218), .S(n3327) );
CMPR32X2TS U1605 ( .A(n7977), .B(n7976), .C(n7975), .CO(n7983), .S(n7982) );
CMPR32X2TS U1606 ( .A(n4276), .B(n4275), .C(n4274), .CO(n4309), .S(n4277) );
CMPR32X2TS U1607 ( .A(n2639), .B(n2638), .C(n2637), .CO(n2836), .S(n2634) );
CMPR32X2TS U1608 ( .A(n5767), .B(n5766), .C(n5765), .CO(n5769), .S(n5794) );
CMPR32X2TS U1609 ( .A(n4461), .B(n4460), .C(n4459), .CO(n4525), .S(n4204) );
CMPR32X2TS U1610 ( .A(n4097), .B(n4096), .C(n4095), .CO(n4613), .S(n4693) );
CMPR32X2TS U1611 ( .A(n4623), .B(n4622), .C(n4621), .CO(n4656), .S(n4653) );
CMPR32X2TS U1612 ( .A(n2534), .B(n2533), .C(n2532), .CO(n2656), .S(n2535) );
CMPR32X2TS U1613 ( .A(n5754), .B(n5753), .C(n5752), .CO(n5760), .S(n5768) );
CMPR32X2TS U1614 ( .A(n7077), .B(n7076), .C(n7075), .CO(n7094), .S(n7081) );
CMPR32X2TS U1615 ( .A(n8010), .B(n8009), .C(n8008), .CO(n8061), .S(n7993) );
CMPR32X2TS U1616 ( .A(n2376), .B(n2375), .C(n2374), .CO(n2373), .S(n2451) );
CMPR32X2TS U1617 ( .A(n4101), .B(n4100), .C(n4099), .CO(n4510), .S(n4104) );
CMPR32X2TS U1618 ( .A(n2540), .B(n2539), .C(n2538), .CO(n2558), .S(n2550) );
CMPR32X2TS U1619 ( .A(n5727), .B(n5726), .C(n5725), .CO(n5729), .S(n5718) );
CMPR32X2TS U1620 ( .A(n2599), .B(n2598), .C(n2597), .CO(n2633), .S(n2594) );
CMPR32X2TS U1621 ( .A(n2097), .B(n2096), .C(n2095), .CO(n2101), .S(n2106) );
CMPR32X2TS U1622 ( .A(n6736), .B(n9041), .C(n9722), .CO(n9040), .S(n9052) );
CMPR32X2TS U1623 ( .A(n752), .B(n3370), .C(n3369), .CO(n3435), .S(n3401) );
CMPR32X2TS U1624 ( .A(n8053), .B(n8052), .C(n8051), .CO(n8069), .S(n8055) );
CMPR32X2TS U1625 ( .A(n7135), .B(n7134), .C(n7133), .CO(n7140), .S(n9804) );
CMPR32X2TS U1626 ( .A(n5781), .B(n5780), .C(n6311), .CO(n5784), .S(n5900) );
CMPR32X2TS U1627 ( .A(n5790), .B(n5789), .C(n5788), .CO(n5796), .S(n6321) );
CMPR32X2TS U1628 ( .A(n4612), .B(n4611), .C(n4610), .CO(n4768), .S(n4658) );
CMPR32X2TS U1629 ( .A(n7085), .B(n7084), .C(n7083), .CO(n7080), .S(n7139) );
CMPR32X2TS U1630 ( .A(n2390), .B(n2389), .C(n2388), .CO(n2450), .S(n2458) );
CMPR32X2TS U1631 ( .A(n5896), .B(n5895), .C(n6195), .CO(n5894), .S(n5951) );
INVX2TS U1632 ( .A(n1606), .Y(n2005) );
CMPR32X2TS U1633 ( .A(n3547), .B(n3546), .C(n3545), .CO(n3811), .S(n3787) );
ADDHXLTS U1634 ( .A(n5701), .B(n5700), .CO(n5706), .S(n5783) );
NAND2X1TS U1635 ( .A(n2573), .B(n2293), .Y(n2298) );
CMPR32X2TS U1636 ( .A(n3384), .B(n3383), .C(n3382), .CO(n3403), .S(n3414) );
CMPR32X2TS U1637 ( .A(n1444), .B(n1443), .C(n1442), .CO(
DP_OP_338J35_122_4684_n1449), .S(DP_OP_338J35_122_4684_n1451) );
CMPR32X2TS U1638 ( .A(n2801), .B(n2819), .C(n2800), .CO(n2459), .S(n2925) );
CMPR32X2TS U1639 ( .A(n8039), .B(n8038), .C(n8037), .CO(n8075), .S(n8048) );
CMPR32X2TS U1640 ( .A(n5733), .B(n5732), .C(n5731), .CO(n5994), .S(n5735) );
ADDHXLTS U1641 ( .A(n1880), .B(n3500), .CO(n1714), .S(n1710) );
NOR2X1TS U1642 ( .A(n7959), .B(n7958), .Y(n8291) );
NAND2X1TS U1643 ( .A(n7959), .B(n7958), .Y(n8292) );
NAND2X2TS U1644 ( .A(Op_MX[48]), .B(n728), .Y(n7321) );
NOR2X1TS U1645 ( .A(n2576), .B(n2264), .Y(n2425) );
CMPR32X2TS U1646 ( .A(n3357), .B(n3356), .C(n3355), .CO(n3415), .S(n3412) );
NAND2X2TS U1647 ( .A(n7056), .B(n905), .Y(n7381) );
CMPR32X2TS U1648 ( .A(n1723), .B(n1722), .C(n1721), .CO(n1696), .S(n1746) );
CMPR32X2TS U1649 ( .A(Op_MX[31]), .B(Op_MX[44]), .C(n7427), .CO(n7431), .S(
n9522) );
CMPR32X2TS U1650 ( .A(n1769), .B(n1768), .C(n908), .CO(n1783), .S(n1856) );
CMPR32X2TS U1651 ( .A(Op_MX[5]), .B(Op_MX[12]), .C(n10340), .CO(n6384), .S(
n10341) );
CMPR32X2TS U1652 ( .A(n7878), .B(n7877), .C(n7876), .CO(n7858), .S(n7976) );
CMPR32X2TS U1653 ( .A(n4466), .B(n4465), .C(n4464), .CO(n4530), .S(n4459) );
CMPR32X2TS U1654 ( .A(n3320), .B(n3319), .C(n3318), .CO(n3328), .S(n3330) );
CMPR32X2TS U1655 ( .A(n7731), .B(n7730), .C(n7729), .CO(n7990), .S(n7860) );
CMPR32X2TS U1656 ( .A(n7817), .B(n7816), .C(n7815), .CO(n8010), .S(n7838) );
CMPR32X2TS U1657 ( .A(n7881), .B(n7880), .C(n7879), .CO(n7862), .S(n7975) );
CMPR32X2TS U1658 ( .A(n8023), .B(n8022), .C(n8021), .CO(n8054), .S(n8024) );
CMPR32X2TS U1659 ( .A(n4472), .B(n4471), .C(n4470), .CO(n4528), .S(n4203) );
CMPR32X2TS U1660 ( .A(n3213), .B(n3212), .C(n3211), .CO(n3216), .S(n3238) );
CMPR32X2TS U1661 ( .A(n2684), .B(n2683), .C(n2682), .CO(n2687), .S(n2736) );
CMPR32X2TS U1662 ( .A(n4642), .B(n4641), .C(n4640), .CO(n4671), .S(n4637) );
CMPR32X2TS U1663 ( .A(n4626), .B(n4625), .C(n4624), .CO(n4655), .S(n4636) );
CMPR32X2TS U1664 ( .A(n5674), .B(n5673), .C(n5672), .CO(n5725), .S(n5666) );
CMPR32X2TS U1665 ( .A(n4089), .B(n4088), .C(n4087), .CO(n4105), .S(n4096) );
CMPR32X2TS U1666 ( .A(n1963), .B(n1962), .C(n1961), .CO(n2097), .S(n2093) );
CMPR32X2TS U1667 ( .A(n1720), .B(n1719), .C(n1718), .CO(n1748), .S(n3891) );
CMPR32X2TS U1668 ( .A(n5704), .B(n5703), .C(n5702), .CO(n6213), .S(n6211) );
CMPR32X2TS U1669 ( .A(n2591), .B(n2590), .C(n2589), .CO(n2599), .S(n2586) );
CMPR32X2TS U1670 ( .A(n2512), .B(n2511), .C(n2510), .CO(n2518), .S(n2540) );
CMPR32X2TS U1671 ( .A(n4055), .B(n4054), .C(n4053), .CO(n4692), .S(n4697) );
CMPR32X2TS U1672 ( .A(n2522), .B(n2521), .C(n2520), .CO(n2533), .S(n2519) );
CMPR32X2TS U1673 ( .A(n6744), .B(n9043), .C(n9042), .CO(n9041), .S(n9046) );
CMPR32X2TS U1674 ( .A(n7971), .B(n7970), .C(n7969), .CO(n7972), .S(n7959) );
CMPR32X2TS U1675 ( .A(n3314), .B(n3313), .C(n3312), .CO(n3332), .S(n3310) );
CMPR32X2TS U1676 ( .A(n2681), .B(n2680), .C(n2679), .CO(n2737), .S(n2844) );
CMPR32X2TS U1677 ( .A(n3171), .B(n3170), .C(n3169), .CO(n3409), .S(n3185) );
CMPR32X2TS U1678 ( .A(n3114), .B(n3113), .C(n3112), .CO(n3413), .S(n3184) );
CMPR32X2TS U1679 ( .A(n1441), .B(n1440), .C(n1439), .CO(
DP_OP_338J35_122_4684_n1450), .S(DP_OP_338J35_122_4684_n1453) );
CMPR32X2TS U1680 ( .A(n3183), .B(n3182), .C(n3181), .CO(n3637), .S(n3606) );
CMPR32X2TS U1681 ( .A(n3323), .B(n3322), .C(n3321), .CO(n3324), .S(n3311) );
CMPR32X2TS U1682 ( .A(n4646), .B(n4645), .C(n4644), .CO(n4651), .S(n4633) );
CMPR32X2TS U1683 ( .A(n2074), .B(n2073), .C(n2072), .CO(n2094), .S(n4288) );
CMPR32X2TS U1684 ( .A(n5724), .B(n5723), .C(n5722), .CO(n5734), .S(n5726) );
ADDHXLTS U1685 ( .A(n7079), .B(n7078), .CO(n7076), .S(n7084) );
CMPR32X2TS U1686 ( .A(n7788), .B(n7787), .C(n7786), .CO(n7994), .S(n7859) );
NAND2X1TS U1687 ( .A(n3725), .B(n3724), .Y(n3768) );
CMPR32X2TS U1688 ( .A(n2172), .B(n4851), .C(n2171), .CO(n1950), .S(n4419) );
CMPR32X2TS U1689 ( .A(n3317), .B(n3316), .C(n3315), .CO(n3239), .S(n3331) );
CMPR32X2TS U1690 ( .A(n2500), .B(n2499), .C(n2498), .CO(n2543), .S(n2538) );
CMPR32X2TS U1691 ( .A(n2060), .B(n2059), .C(n2058), .CO(n4278), .S(n2055) );
CMPR32X2TS U1692 ( .A(n1908), .B(n1907), .C(n1906), .CO(n1918), .S(n2095) );
NOR2X1TS U1693 ( .A(Op_MY[49]), .B(Op_MY[42]), .Y(n7310) );
CMPR32X4TS U1694 ( .A(Op_MX[30]), .B(Op_MX[43]), .C(n7428), .CO(n7427), .S(
n7429) );
CMPR32X2TS U1695 ( .A(n7980), .B(n7979), .C(n7978), .CO(n7981), .S(n7973) );
CMPR32X2TS U1696 ( .A(n2602), .B(n2601), .C(n2600), .CO(n2636), .S(n2597) );
CMPR32X2TS U1697 ( .A(n2527), .B(n2526), .C(n2525), .CO(n2658), .S(n2532) );
CMPR32X2TS U1698 ( .A(n8001), .B(n8000), .C(n7999), .CO(n8046), .S(n8003) );
CMPR32X2TS U1699 ( .A(n3408), .B(n3407), .C(n3406), .CO(n3647), .S(n3636) );
CMPR32X2TS U1700 ( .A(n2341), .B(n2340), .C(n2339), .CO(n2549), .S(n6845) );
ADDHXLTS U1701 ( .A(n1843), .B(n3429), .CO(n1683), .S(n1690) );
CMPR32X2TS U1702 ( .A(n3381), .B(n3380), .C(n3379), .CO(n3404), .S(n3410) );
ADDFX1TS U1703 ( .A(n3165), .B(n3164), .CI(n3163), .CO(n3411), .S(n3160) );
CMPR32X2TS U1704 ( .A(n3496), .B(n3495), .C(n3494), .CO(n3788), .S(n3731) );
INVX4TS U1705 ( .A(n1886), .Y(n2105) );
OAI21X1TS U1706 ( .A0(n4355), .A1(n1011), .B0(n4356), .Y(n4325) );
XNOR2X1TS U1707 ( .A(n8258), .B(n8229), .Y(n8236) );
CMPR32X2TS U1708 ( .A(n7841), .B(n7840), .C(n7839), .CO(n7786), .S(n7881) );
CMPR32X2TS U1709 ( .A(Op_MY[5]), .B(Op_MY[12]), .C(n10332), .CO(n6382), .S(
n10333) );
CMPR32X2TS U1710 ( .A(Op_MX[11]), .B(Op_MX[4]), .C(n10328), .CO(n10340), .S(
n10329) );
CMPR32X2TS U1711 ( .A(Op_MY[29]), .B(Op_MY[42]), .C(n7438), .CO(n7437), .S(
n9608) );
CMPR32X2TS U1712 ( .A(n3237), .B(n3236), .C(n3235), .CO(n3240), .S(n3318) );
CMPR32X2TS U1713 ( .A(n3297), .B(n3296), .C(n3295), .CO(n3319), .S(n3322) );
CMPR32X2TS U1714 ( .A(n7968), .B(n7967), .C(n7966), .CO(n7977), .S(n7978) );
CMPR32X2TS U1715 ( .A(n4548), .B(n4547), .C(n4546), .CO(n4632), .S(n4538) );
CMPR32X2TS U1716 ( .A(n4620), .B(n4619), .C(n4618), .CO(n4625), .S(n4646) );
CMPR32X2TS U1717 ( .A(n3137), .B(n3136), .C(n3135), .CO(n3186), .S(n3147) );
CMPR32X2TS U1718 ( .A(Op_MY[12]), .B(Op_MY[26]), .C(n2270), .CO(n2422), .S(
n2293) );
CMPR32X2TS U1719 ( .A(n3294), .B(n3293), .C(n3292), .CO(n3323), .S(n3289) );
CMPR32X2TS U1720 ( .A(n2336), .B(n2335), .C(n2334), .CO(n2339), .S(n2338) );
CMPR32X2TS U1721 ( .A(n3225), .B(n3224), .C(n3223), .CO(n3222), .S(n3320) );
CMPR32X2TS U1722 ( .A(n7766), .B(n7765), .C(n7764), .CO(n7788), .S(n7878) );
CMPR32X2TS U1723 ( .A(n3133), .B(n3132), .C(n3131), .CO(n3159), .S(n3211) );
CMPR32X2TS U1724 ( .A(n7722), .B(n7721), .C(n7720), .CO(n8025), .S(n7729) );
CMPR32X2TS U1725 ( .A(n3140), .B(n3139), .C(n3138), .CO(n3161), .S(n3148) );
CMPR32X2TS U1726 ( .A(n7962), .B(n7961), .C(n7960), .CO(n7980), .S(n7958) );
CMPR32X2TS U1727 ( .A(n4045), .B(n4044), .C(n4043), .CO(n4097), .S(n4054) );
CMPR32X2TS U1728 ( .A(n4617), .B(n4616), .C(n4615), .CO(n4622), .S(n4626) );
CMPR32X2TS U1729 ( .A(n1960), .B(n1959), .C(n1958), .CO(n1963), .S(n2073) );
CMPR32X2TS U1730 ( .A(n1926), .B(n1925), .C(n1924), .CO(n2058), .S(n1920) );
CMPR32X2TS U1731 ( .A(n3300), .B(n3299), .C(n3298), .CO(n3321), .S(n3290) );
CMPR32X2TS U1732 ( .A(n7710), .B(n7709), .C(n7708), .CO(n8002), .S(n7730) );
CMPR32X2TS U1733 ( .A(n3309), .B(n3308), .C(n3307), .CO(n3315), .S(n3312) );
CMPR32X2TS U1734 ( .A(n5669), .B(n5668), .C(n5667), .CO(n5727), .S(n5673) );
CMPR32X2TS U1735 ( .A(n4210), .B(n4209), .C(n4208), .CO(n4464), .S(n4229) );
CMPR32X2TS U1736 ( .A(n7965), .B(n7964), .C(n7963), .CO(n7880), .S(n7979) );
CMPR32X2TS U1737 ( .A(n7857), .B(n7856), .C(n7855), .CO(n7836), .S(n7879) );
CMPR32X2TS U1738 ( .A(n4093), .B(n4092), .C(n4091), .CO(n4100), .S(n4088) );
CMPR32X2TS U1739 ( .A(n2333), .B(n2332), .C(n2331), .CO(n2551), .S(n2340) );
CMPR32X2TS U1740 ( .A(n3180), .B(n3179), .C(n3178), .CO(n3605), .S(n3602) );
CMPR32X2TS U1741 ( .A(n4207), .B(n4206), .C(n4205), .CO(n4470), .S(n4230) );
CMPR32X2TS U1742 ( .A(n1987), .B(n1986), .C(n1985), .CO(n2074), .S(n4285) );
NOR2X1TS U1743 ( .A(n3288), .B(n3287), .Y(n3734) );
CMPR32X2TS U1744 ( .A(n5655), .B(n5654), .C(n5653), .CO(n5672), .S(n5697) );
CMPR32X2TS U1745 ( .A(n5687), .B(n5686), .C(n5685), .CO(n5696), .S(n5704) );
CMPR32X2TS U1746 ( .A(n1912), .B(n1911), .C(n1910), .CO(n1921), .S(n1906) );
CMPR32X2TS U1747 ( .A(n3177), .B(n3176), .C(n3175), .CO(n3406), .S(n3181) );
CMPR32X2TS U1748 ( .A(n3420), .B(n3419), .C(n3418), .CO(n3730), .S(n3727) );
CMPR32X2TS U1749 ( .A(n752), .B(n3372), .C(n3371), .CO(n3400), .S(n3407) );
CMPR32X2TS U1750 ( .A(n1435), .B(n1434), .C(n1433), .CO(
DP_OP_338J35_122_4684_n1452), .S(DP_OP_338J35_122_4684_n1455) );
CMPR32X2TS U1751 ( .A(n1438), .B(n1437), .C(n1436), .CO(n1442), .S(n1440) );
NAND2X1TS U1752 ( .A(n2452), .B(n2290), .Y(n2366) );
CMPR32X2TS U1753 ( .A(n5793), .B(n5792), .C(n5791), .CO(n5702), .S(n6208) );
INVX1TS U1754 ( .A(n4845), .Y(n1945) );
NAND2X1TS U1755 ( .A(n2467), .B(n2291), .Y(n2358) );
CMPR32X2TS U1756 ( .A(n4562), .B(n4561), .C(n4560), .CO(n4640), .S(n4539) );
CMPR32X2TS U1757 ( .A(Op_MX[29]), .B(Op_MX[42]), .C(n7430), .CO(n7428), .S(
n9554) );
CMPR32X2TS U1758 ( .A(n1774), .B(n1773), .C(n3047), .CO(n1768), .S(n1884) );
CMPR32X2TS U1759 ( .A(Op_MY[4]), .B(Op_MY[11]), .C(n10326), .CO(n10332), .S(
n10327) );
CMPR32X2TS U1760 ( .A(Op_MY[11]), .B(Op_MY[25]), .C(n2274), .CO(n2270), .S(
n2291) );
CMPR32X2TS U1761 ( .A(Op_MY[28]), .B(Op_MY[41]), .C(n3004), .CO(n7438), .S(
n7491) );
CMPR32X2TS U1762 ( .A(n7875), .B(n7874), .C(n7873), .CO(n7876), .S(n7966) );
CMPR32X2TS U1763 ( .A(n3270), .B(n3269), .C(n3268), .CO(n3298), .S(n3288) );
CMPR32X2TS U1764 ( .A(n7924), .B(n7923), .C(n7922), .CO(n7969), .S(n7956) );
CMPR32X2TS U1765 ( .A(n7794), .B(n7793), .C(n7792), .CO(n7815), .S(n7839) );
CMPR32X2TS U1766 ( .A(n1904), .B(n1903), .C(n1902), .CO(n1910), .S(n1962) );
CMPR32X2TS U1767 ( .A(n2320), .B(n2319), .C(n2318), .CO(n2331), .S(n2335) );
CMPR32X2TS U1768 ( .A(n3261), .B(n3260), .C(n3259), .CO(n3297), .S(n3294) );
CMPR32X2TS U1769 ( .A(n7866), .B(n7865), .C(n7864), .CO(n7855), .S(n7968) );
CMPR32X2TS U1770 ( .A(n4202), .B(n4201), .C(n4200), .CO(n4466), .S(n4205) );
CMPR32X2TS U1771 ( .A(n7734), .B(n7733), .C(n7732), .CO(n7708), .S(n7766) );
CMPR32X2TS U1772 ( .A(n1432), .B(n1431), .C(n1430), .CO(n1439), .S(n1434) );
CMPR32X2TS U1773 ( .A(n4048), .B(n4047), .C(n4046), .CO(n4089), .S(n4044) );
CMPR32X2TS U1774 ( .A(n3146), .B(n3145), .C(n3144), .CO(n3131), .S(n3223) );
CMPR32X2TS U1775 ( .A(n2254), .B(n2253), .C(n2252), .CO(n2336), .S(n2376) );
CMPR32X2TS U1776 ( .A(n4479), .B(n4478), .C(n4477), .CO(n4562), .S(n4475) );
CMPR32X2TS U1777 ( .A(n7927), .B(n7926), .C(n7925), .CO(n7971), .S(n7955) );
CMPR32X2TS U1778 ( .A(n7728), .B(n7727), .C(n7726), .CO(n8021), .S(n7720) );
CMPR32X2TS U1779 ( .A(n3198), .B(n3197), .C(n3196), .CO(n3213), .S(n3235) );
CMPR32X2TS U1780 ( .A(n3156), .B(n3155), .C(n3154), .CO(n3182), .S(n3178) );
CMPR32X2TS U1781 ( .A(n7791), .B(n7790), .C(n7789), .CO(n7816), .S(n7840) );
CMPR32X2TS U1782 ( .A(n3234), .B(n3233), .C(n3232), .CO(n3236), .S(n3295) );
CMPR32X2TS U1783 ( .A(n1418), .B(n1417), .C(n1416), .CO(
DP_OP_338J35_122_4684_n1454), .S(DP_OP_338J35_122_4684_n1456) );
CMPR32X2TS U1784 ( .A(n7888), .B(n7887), .C(n7886), .CO(n7967), .S(n7970) );
CMPR32X2TS U1785 ( .A(n7921), .B(n7920), .C(n7919), .CO(n7964), .S(n7960) );
CMPR32X2TS U1786 ( .A(n4559), .B(n4558), .C(n4557), .CO(n4642), .S(n4547) );
CMPR32X2TS U1787 ( .A(n4490), .B(n4489), .C(n4488), .CO(n4560), .S(n4474) );
ADDHXLTS U1788 ( .A(n1957), .B(n1956), .CO(n1959), .S(n1987) );
CMPR32X2TS U1789 ( .A(n4213), .B(n4212), .C(n4211), .CO(n4208), .S(n4228) );
NAND2X1TS U1790 ( .A(n8246), .B(n8245), .Y(n8281) );
CMPR32X2TS U1791 ( .A(n2330), .B(n2329), .C(n2328), .CO(n2498), .S(n2332) );
CMPR32X2TS U1792 ( .A(n3210), .B(n3209), .C(n3208), .CO(n3237), .S(n3307) );
CMPR32X2TS U1793 ( .A(n3425), .B(n3424), .C(n3423), .CO(n3546), .S(n3420) );
CMPR32X2TS U1794 ( .A(n3387), .B(n3386), .C(n3385), .CO(n3726), .S(n3725) );
CMPR32X4TS U1795 ( .A(Op_MX[28]), .B(Op_MX[41]), .C(n2967), .CO(n7430), .S(
n2968) );
CMPR32X2TS U1796 ( .A(n3267), .B(n3266), .C(n3265), .CO(n3296), .S(n3292) );
CMPR32X2TS U1797 ( .A(n3303), .B(n3302), .C(n3301), .CO(n3599), .S(n3598) );
CMPR32X2TS U1798 ( .A(n3206), .B(n3205), .C(n3204), .CO(n3601), .S(n3600) );
NOR2X1TS U1799 ( .A(n7954), .B(n7953), .Y(n8262) );
INVX2TS U1800 ( .A(n2471), .Y(n2831) );
CMPR32X2TS U1801 ( .A(n3593), .B(n3272), .C(n3271), .CO(n3300), .S(n3287) );
NAND2X1TS U1802 ( .A(n3063), .B(n1831), .Y(n1633) );
INVX2TS U1803 ( .A(n1865), .Y(n2034) );
CMPR32X2TS U1804 ( .A(n3306), .B(n3305), .C(n3304), .CO(n3313), .S(n3299) );
INVX4TS U1805 ( .A(n1930), .Y(n2170) );
CMPR32X2TS U1806 ( .A(n4198), .B(n4197), .C(n4196), .CO(n4488), .S(n4200) );
CMPR32X2TS U1807 ( .A(Op_MY[3]), .B(Op_MY[10]), .C(n10377), .CO(n10326), .S(
n10378) );
CMPR32X2TS U1808 ( .A(Op_MX[3]), .B(Op_MX[10]), .C(n10330), .CO(n10328), .S(
n10331) );
CMPR32X2TS U1809 ( .A(n7872), .B(n7871), .C(n7870), .CO(n7874), .S(n7886) );
CMPR32X2TS U1810 ( .A(n7823), .B(n7822), .C(n7821), .CO(n7857), .S(n7873) );
CMPR32X2TS U1811 ( .A(n4545), .B(n4544), .C(n4543), .CO(n4618), .S(n4559) );
CMPR32X2TS U1812 ( .A(Op_MY[10]), .B(Op_MY[24]), .C(n2279), .CO(n2274), .S(
n2290) );
CMPR32X2TS U1813 ( .A(n4063), .B(n4062), .C(n4061), .CO(n4081), .S(n4537) );
CMPR32X2TS U1814 ( .A(n7869), .B(n7868), .C(n7867), .CO(n7866), .S(n7888) );
CMPR32X2TS U1815 ( .A(n1421), .B(n1420), .C(n1419), .CO(
DP_OP_338J35_122_4684_n1459), .S(DP_OP_338J35_122_4684_n1460) );
CMPR32X2TS U1816 ( .A(n7918), .B(n7917), .C(n7916), .CO(n7961), .S(n7923) );
CMPR32X2TS U1817 ( .A(n7770), .B(n7769), .C(n7768), .CO(n7841), .S(n7875) );
CMPR32X2TS U1818 ( .A(n3264), .B(n3263), .C(n3262), .CO(n3293), .S(n3268) );
CMPR32X2TS U1819 ( .A(n7930), .B(n7929), .C(n7928), .CO(n7922), .S(n7954) );
CMPR32X2TS U1820 ( .A(n7933), .B(n7932), .C(n7931), .CO(n7924), .S(n7953) );
CMPR32X2TS U1821 ( .A(n7713), .B(n7712), .C(n7711), .CO(n8150), .S(n8142) );
CMPR32X2TS U1822 ( .A(n3395), .B(n3394), .C(n3393), .CO(n3419), .S(n3386) );
ADDHXLTS U1823 ( .A(n2242), .B(n2241), .CO(n2319), .S(n2253) );
CMPR32X2TS U1824 ( .A(n1397), .B(n1396), .C(n1395), .CO(n1433), .S(n1417) );
CMPR32X2TS U1825 ( .A(n4220), .B(n4219), .C(n4218), .CO(n4213), .S(n4225) );
CMPR32X2TS U1826 ( .A(n3697), .B(n3274), .C(n3273), .CO(n3269), .S(n3285) );
CMPR32X2TS U1827 ( .A(n3277), .B(n3276), .C(n3275), .CO(n3272), .S(n3284) );
CMPR32X2TS U1828 ( .A(Op_MX[24]), .B(Op_MX[51]), .C(n1637), .CO(n1671), .S(
n1799) );
CMPR32X2TS U1829 ( .A(n3353), .B(n3352), .C(n3351), .CO(n3724), .S(n3721) );
CMPR32X2TS U1830 ( .A(n4051), .B(n4050), .C(n4049), .CO(n4092), .S(n4047) );
CMPR32X2TS U1831 ( .A(n8045), .B(n8044), .C(n8043), .CO(n8251), .S(n8245) );
CMPR32X2TS U1832 ( .A(n8080), .B(n8079), .C(n8078), .CO(n8289), .S(n8250) );
CMPR32X2TS U1833 ( .A(n1427), .B(n1426), .C(n1425), .CO(n1441), .S(n1430) );
CMPR32X2TS U1834 ( .A(n1424), .B(n1423), .C(n1422), .CO(
DP_OP_338J35_122_4684_n1457), .S(DP_OP_338J35_122_4684_n1458) );
ADDHXLTS U1835 ( .A(n2327), .B(n2326), .CO(n2500), .S(n2328) );
CMPR32X2TS U1836 ( .A(n7885), .B(n7884), .C(n7883), .CO(n7919), .S(n7925) );
CMPR32X2TS U1837 ( .A(n7997), .B(n7996), .C(n7995), .CO(n8161), .S(n8149) );
CMPR32X2TS U1838 ( .A(n3249), .B(n3248), .C(n3247), .CO(n3266), .S(n3271) );
NOR2X1TS U1839 ( .A(n3063), .B(n1831), .Y(n1635) );
AO21XLTS U1840 ( .A0(n2507), .A1(n2506), .B0(n2505), .Y(n826) );
CMPR32X2TS U1841 ( .A(Op_MY[2]), .B(Op_MY[9]), .C(n6405), .CO(n10377), .S(
n6406) );
CMPR32X2TS U1842 ( .A(Op_MX[9]), .B(Op_MX[2]), .C(n10334), .CO(n10330), .S(
n10335) );
CMPR32X2TS U1843 ( .A(n4042), .B(n4041), .C(n4040), .CO(n4025), .S(n4062) );
CMPR32X2TS U1844 ( .A(n4187), .B(n4186), .C(n4185), .CO(n4478), .S(n4196) );
CMPR32X2TS U1845 ( .A(n7914), .B(n7913), .C(n7912), .CO(n7916), .S(n7928) );
CMPR32X2TS U1846 ( .A(n4066), .B(n4065), .C(n4064), .CO(n4063), .S(n4473) );
ADDHXLTS U1847 ( .A(n1770), .B(n752), .CO(n1773), .S(n1928) );
CMPR32X2TS U1848 ( .A(n1415), .B(n1414), .C(n1413), .CO(n1416), .S(n1422) );
CMPR32X2TS U1849 ( .A(n1409), .B(n1408), .C(n1407), .CO(n1424), .S(n1421) );
CMPR32X2TS U1850 ( .A(n8042), .B(n8041), .C(n8040), .CO(n8079), .S(n8045) );
CMPR32X2TS U1851 ( .A(n1412), .B(n1411), .C(n1410), .CO(n1423), .S(n1419) );
CMPR32X2TS U1852 ( .A(n7846), .B(n7845), .C(n7844), .CO(n7869), .S(n7884) );
CMPR32X2TS U1853 ( .A(n7785), .B(n7784), .C(n7783), .CO(n7792), .S(n7821) );
CMPR32X2TS U1854 ( .A(Op_MX[23]), .B(Op_MX[50]), .C(n1647), .CO(n1637), .S(
n1867) );
CMPR32X2TS U1855 ( .A(n4495), .B(n4494), .C(n4493), .CO(n4543), .S(n4479) );
CMPR32X2TS U1856 ( .A(n3395), .B(n3377), .C(n3376), .CO(n3393), .S(n3352) );
CMPR32X2TS U1857 ( .A(n7936), .B(n7935), .C(n7934), .CO(n7929), .S(n7951) );
CMPR32X2TS U1858 ( .A(n7725), .B(n7724), .C(n7723), .CO(n7995), .S(n7712) );
CMPR32X2TS U1859 ( .A(n4004), .B(n4003), .C(n4002), .CO(n4045), .S(n4026) );
CMPR32X2TS U1860 ( .A(n7892), .B(n7891), .C(n7890), .CO(n7883), .S(n7932) );
CMPR32X2TS U1861 ( .A(n7782), .B(n7781), .C(n7780), .CO(n7822), .S(n7871) );
NAND2X1TS U1862 ( .A(n8221), .B(n8220), .Y(n8242) );
NOR2X1TS U1863 ( .A(n8218), .B(n8217), .Y(n8240) );
CMPR32X2TS U1864 ( .A(n1388), .B(n1387), .C(n1386), .CO(n1435), .S(n1395) );
CMPR32X2TS U1865 ( .A(n1380), .B(n1379), .C(n1378), .CO(n1431), .S(n1397) );
ADDHXLTS U1866 ( .A(n3195), .B(n3194), .CO(n3130), .S(n3209) );
INVX6TS U1867 ( .A(n1612), .Y(n1810) );
CMPR32X2TS U1868 ( .A(n7751), .B(n7750), .C(n7749), .CO(n8143), .S(n8139) );
ADDHXLTS U1869 ( .A(n3481), .B(n3500), .CO(n3079), .S(n3083) );
NAND2X1TS U1870 ( .A(n7767), .B(n7824), .Y(n8211) );
INVX4TS U1871 ( .A(n4195), .Y(n4756) );
INVX4TS U1872 ( .A(n1689), .Y(n1948) );
INVX4TS U1873 ( .A(n1605), .Y(n1730) );
NOR2X1TS U1874 ( .A(n4396), .B(n2081), .Y(n1914) );
NAND2X1TS U1875 ( .A(n904), .B(n1794), .Y(n1623) );
CMPR32X2TS U1876 ( .A(n7897), .B(n7896), .C(n7895), .CO(n7870), .S(n7917) );
NOR2X2TS U1877 ( .A(n7767), .B(n7824), .Y(n8213) );
OAI21X1TS U1878 ( .A0(n4354), .A1(n4350), .B0(n4351), .Y(n5319) );
CMPR32X2TS U1879 ( .A(Op_MX[24]), .B(Op_MX[51]), .C(n4164), .CO(n4462), .S(
n4167) );
CMPR32X2TS U1880 ( .A(n4039), .B(n4038), .C(n4037), .CO(n4042), .S(n4065) );
CMPR32X2TS U1881 ( .A(Op_MX[1]), .B(Op_MX[8]), .C(n6399), .CO(n10334), .S(
n6400) );
CMPR32X2TS U1882 ( .A(Op_MY[1]), .B(Op_MY[8]), .C(n6401), .CO(n6405), .S(
n6402) );
CMPR32X2TS U1883 ( .A(n7853), .B(n7852), .C(n7851), .CO(n7896), .S(n7890) );
CMPR32X2TS U1884 ( .A(n3100), .B(n3099), .C(n3098), .CO(n3116), .S(n3105) );
CMPR32X2TS U1885 ( .A(n4069), .B(n4068), .C(n4067), .CO(n4066), .S(n4179) );
CMPR32X2TS U1886 ( .A(n1377), .B(n1376), .C(n1375), .CO(
DP_OP_338J35_122_4684_n1461), .S(DP_OP_338J35_122_4684_n1462) );
CMPR32X2TS U1887 ( .A(n1403), .B(n1402), .C(n1401), .CO(n1414), .S(n1411) );
CMPR32X2TS U1888 ( .A(n4184), .B(n4183), .C(n4182), .CO(n4493), .S(n4187) );
CMPR32X2TS U1889 ( .A(n4001), .B(n4000), .C(n3999), .CO(n4027), .S(n4040) );
CMPR32X2TS U1890 ( .A(n4177), .B(n4176), .C(n4175), .CO(n4171), .S(n4219) );
CMPR32X2TS U1891 ( .A(n1400), .B(n1399), .C(n1398), .CO(n1396), .S(n1415) );
CMPR32X2TS U1892 ( .A(n7820), .B(n7819), .C(n7818), .CO(n8220), .S(n8218) );
CMPR32X2TS U1893 ( .A(n7718), .B(n7717), .C(n7716), .CO(n7711), .S(n7749) );
CMPR32X2TS U1894 ( .A(n1406), .B(n1405), .C(n1404), .CO(n1418), .S(n1413) );
CMPR32X2TS U1895 ( .A(n7737), .B(n7736), .C(n7735), .CO(n8217), .S(n7767) );
CMPR32X2TS U1896 ( .A(n7942), .B(n7941), .C(n7940), .CO(n7934), .S(n7949) );
CMPR32X2TS U1897 ( .A(n8007), .B(n8006), .C(n8005), .CO(n8246), .S(n8221) );
CMPR32X2TS U1898 ( .A(n4007), .B(n4006), .C(n4005), .CO(n4048), .S(n4003) );
CMPR32X2TS U1899 ( .A(n7566), .B(n7565), .C(n7564), .CO(n7824), .S(n7854) );
ADDHXLTS U1900 ( .A(n4492), .B(n4491), .CO(n4542), .S(n4495) );
CMPR32X2TS U1901 ( .A(n7748), .B(n7747), .C(n7746), .CO(n8138), .S(n8137) );
ADDHXLTS U1902 ( .A(n3421), .B(n3429), .CO(n3106), .S(n3107) );
CMPR32X2TS U1903 ( .A(n7552), .B(n7551), .C(n7550), .CO(n7842), .S(n7915) );
CMPR32X2TS U1904 ( .A(n7904), .B(n7903), .C(n7902), .CO(n7891), .S(n7936) );
CMPR32X2TS U1905 ( .A(n7939), .B(n7938), .C(n7937), .CO(n7912), .S(n7950) );
ADDHXLTS U1906 ( .A(n3374), .B(n3343), .CO(n3067), .S(n3072) );
AO21X1TS U1907 ( .A0(n842), .A1(n4485), .B0(n4484), .Y(n765) );
INVX2TS U1908 ( .A(n1894), .Y(n4396) );
NAND2X2TS U1909 ( .A(n3022), .B(n877), .Y(n3499) );
ADDHX1TS U1910 ( .A(Op_MY[26]), .B(n1458), .CO(n1831), .S(n1794) );
CMPR32X2TS U1911 ( .A(Op_MX[23]), .B(Op_MX[50]), .C(n4135), .CO(n4164), .S(
n4138) );
CMPR32X2TS U1912 ( .A(n3043), .B(n3042), .C(n3041), .CO(n3103), .S(n3713) );
CMPR32X2TS U1913 ( .A(n4036), .B(n4035), .C(n4034), .CO(n4039), .S(n4068) );
CMPR32X2TS U1914 ( .A(n7740), .B(n7739), .C(n7738), .CO(n7751), .S(n7748) );
CMPR32X2TS U1915 ( .A(n7797), .B(n7796), .C(n7795), .CO(n7819), .S(n7735) );
CMPR32X2TS U1916 ( .A(n7555), .B(n7554), .C(n7553), .CO(n7736), .S(n7564) );
CMPR32X2TS U1917 ( .A(n7745), .B(n7744), .C(n7743), .CO(n7750), .S(n7746) );
CMPR32X2TS U1918 ( .A(n1368), .B(n1367), .C(n1366), .CO(n1420), .S(n1375) );
CMPR32X2TS U1919 ( .A(n1394), .B(n1393), .C(n1392), .CO(n1404), .S(n1408) );
CMPR32X2TS U1920 ( .A(n7773), .B(n7772), .C(n7771), .CO(n7747), .S(n8134) );
CMPR32X2TS U1921 ( .A(n8325), .B(n7850), .C(n7849), .CO(n7852), .S(n7902) );
CMPR32X2TS U1922 ( .A(n8315), .B(n7907), .C(n7906), .CO(n7939), .S(n7942) );
CMPR32X2TS U1923 ( .A(n4073), .B(n4072), .C(n4071), .CO(n4069), .S(n4174) );
CMPR32X2TS U1924 ( .A(n7835), .B(n7834), .C(n7833), .CO(n8136), .S(n8135) );
CMPR32X2TS U1925 ( .A(Op_MX[22]), .B(Op_MX[49]), .C(n1613), .CO(n1647), .S(
n1627) );
ADDHXLTS U1926 ( .A(Op_MX[9]), .B(Op_MX[23]), .CO(n2231), .S(n2230) );
ADDHXLTS U1927 ( .A(Op_MX[10]), .B(Op_MX[24]), .CO(n2243), .S(n2229) );
CMPR32X2TS U1928 ( .A(n8016), .B(n8015), .C(n8014), .CO(n8043), .S(n8005) );
CMPR32X2TS U1929 ( .A(n7808), .B(n7807), .C(n7806), .CO(n8006), .S(n7818) );
CMPR32X2TS U1930 ( .A(n3998), .B(n3997), .C(n3996), .CO(n4001), .S(n4038) );
CMPR32X2TS U1931 ( .A(n7675), .B(n7674), .C(n7673), .CO(n7713), .S(n7716) );
CMPR32X2TS U1932 ( .A(n1374), .B(n1373), .C(n1372), .CO(n1410), .S(n1377) );
CMPR32X2TS U1933 ( .A(n3982), .B(n3981), .C(n3980), .CO(n4004), .S(n3999) );
ADDHXLTS U1934 ( .A(n4181), .B(n4180), .CO(n4492), .S(n4184) );
CMPR32X2TS U1935 ( .A(n1360), .B(n1359), .C(n1358), .CO(
DP_OP_338J35_122_4684_n1463), .S(DP_OP_338J35_122_4684_n1464) );
ADDHXLTS U1936 ( .A(n7829), .B(n7828), .CO(n7775), .S(n7845) );
OR2X1TS U1937 ( .A(n1462), .B(Op_MY[25]), .Y(n1458) );
ADDHXLTS U1938 ( .A(n4125), .B(n4124), .CO(n4118), .S(n4126) );
INVX2TS U1939 ( .A(n2453), .Y(n2605) );
NAND2X2TS U1940 ( .A(n3483), .B(n3097), .Y(n3555) );
AOI21X2TS U1941 ( .A0(n1144), .A1(n1603), .B0(n1544), .Y(n1610) );
CLKXOR2X2TS U1942 ( .A(n1792), .B(n1791), .Y(n1894) );
NAND2X2TS U1943 ( .A(n3021), .B(n879), .Y(n3346) );
CMPR32X2TS U1944 ( .A(n7805), .B(n7804), .C(n7803), .CO(n7807), .S(n7796) );
CMPR32X2TS U1945 ( .A(n7549), .B(n7548), .C(n7547), .CO(n7553), .S(n7552) );
CMPR32X2TS U1946 ( .A(Op_MX[22]), .B(Op_MX[49]), .C(n4117), .CO(n4135), .S(
n4125) );
CMPR32X2TS U1947 ( .A(n7754), .B(n7753), .C(n7752), .CO(n7743), .S(n7834) );
CMPR32X2TS U1948 ( .A(n1350), .B(n1349), .C(n1348), .CO(n1376), .S(n1358) );
CMPR32X2TS U1949 ( .A(n4156), .B(n4155), .C(n4154), .CO(n4163), .S(n4177) );
CMPR32X2TS U1950 ( .A(n7541), .B(n7540), .C(n7539), .CO(n7843), .S(n7882) );
CMPR32X2TS U1951 ( .A(Op_MX[48]), .B(Op_MX[21]), .C(n1589), .CO(n1613), .S(
n1874) );
NAND2X1TS U1952 ( .A(Op_MY[26]), .B(Op_MY[12]), .Y(n2504) );
CMPR32X2TS U1953 ( .A(n8013), .B(n8012), .C(n8011), .CO(n8040), .S(n8016) );
CMPR32X2TS U1954 ( .A(n7814), .B(n7813), .C(n7812), .CO(n8015), .S(n7808) );
CMPR32X2TS U1955 ( .A(n1357), .B(n1356), .C(n1355), .CO(n1367), .S(n1359) );
CMPR32X2TS U1956 ( .A(n1371), .B(n1370), .C(n1369), .CO(n1412), .S(n1366) );
CMPR32X2TS U1957 ( .A(n2186), .B(n2185), .C(n2184), .CO(
DP_OP_338J35_122_4684_n1465), .S(n4830) );
CMPR32X2TS U1958 ( .A(n7827), .B(n7826), .C(n7825), .CO(n8131), .S(n8130) );
INVX2TS U1959 ( .A(n1890), .Y(n2081) );
CMPR32X2TS U1960 ( .A(n7832), .B(n7831), .C(n7830), .CO(n7833), .S(n8132) );
NAND2X1TS U1961 ( .A(n4334), .B(n4333), .Y(n4335) );
CMPR32X2TS U1962 ( .A(n3035), .B(n3034), .C(n3033), .CO(n3042), .S(n3711) );
CLKXOR2X2TS U1963 ( .A(n2418), .B(n2273), .Y(n2467) );
CMPR32X2TS U1964 ( .A(n7563), .B(n7562), .C(n7561), .CO(n7803), .S(n7554) );
CMPR32X2TS U1965 ( .A(Op_MX[20]), .B(Op_MX[47]), .C(n1556), .CO(n1589), .S(
n1882) );
NAND2X1TS U1966 ( .A(Op_MX[14]), .B(Op_MX[0]), .Y(n2379) );
CMPR32X2TS U1967 ( .A(n7532), .B(n7531), .C(n7530), .CO(n7539), .S(n7889) );
CMPR32X2TS U1968 ( .A(n7538), .B(n7537), .C(n7536), .CO(n7548), .S(n7541) );
CMPR32X2TS U1969 ( .A(n7802), .B(n7801), .C(n7800), .CO(n7812), .S(n7804) );
CMPR32X2TS U1970 ( .A(n1331), .B(n1330), .C(n1329), .CO(n1360), .S(n2184) );
CMPR32X2TS U1971 ( .A(n7761), .B(n7760), .C(n7759), .CO(n7771), .S(n7830) );
CMPR32X2TS U1972 ( .A(n4222), .B(n4810), .C(n4221), .CO(n4154), .S(n4255) );
CMPR32X2TS U1973 ( .A(n7811), .B(n7810), .C(n7809), .CO(n8011), .S(n7813) );
NOR2X2TS U1974 ( .A(n752), .B(n1770), .Y(n1685) );
XNOR2X2TS U1975 ( .A(n1462), .B(Op_MY[25]), .Y(n1784) );
INVX4TS U1976 ( .A(n4134), .Y(n4672) );
CMPR32X2TS U1977 ( .A(Op_MX[46]), .B(Op_MX[19]), .C(n1557), .CO(n1556), .S(
n1838) );
NAND2X1TS U1978 ( .A(Op_MY[25]), .B(Op_MY[11]), .Y(n2309) );
CMPR32X2TS U1979 ( .A(n7546), .B(n7545), .C(n7544), .CO(n7561), .S(n7549) );
CMPR32X2TS U1980 ( .A(n7558), .B(n7557), .C(n7556), .CO(n7805), .S(n7562) );
INVX2TS U1981 ( .A(n4124), .Y(n4077) );
INVX4TS U1982 ( .A(n3341), .Y(n904) );
NAND2X1TS U1983 ( .A(n1614), .B(n1593), .Y(n1673) );
NOR2X1TS U1984 ( .A(n7663), .B(n7677), .Y(n7668) );
AOI21X1TS U1985 ( .A0(n1151), .A1(n3085), .B0(n3045), .Y(n3068) );
CMPR32X2TS U1986 ( .A(Op_MX[18]), .B(n881), .C(n1559), .CO(n1557), .S(n1845)
);
NAND2X1TS U1987 ( .A(Op_MY[36]), .B(Op_MY[29]), .Y(n7701) );
NAND2X1TS U1988 ( .A(Op_MY[21]), .B(Op_MY[7]), .Y(n2437) );
INVX2TS U1989 ( .A(n4148), .Y(n4629) );
INVX4TS U1990 ( .A(n4116), .Y(n4714) );
OAI21X1TS U1991 ( .A0(n7687), .A1(n7690), .B0(n7688), .Y(n7693) );
CMPR32X2TS U1992 ( .A(Op_MY[24]), .B(Op_MY[51]), .C(n4188), .CO(n4480), .S(
n4141) );
NAND2X1TS U1993 ( .A(Op_MY[34]), .B(Op_MY[27]), .Y(n7690) );
NOR2X1TS U1994 ( .A(Op_MY[35]), .B(Op_MY[28]), .Y(n7687) );
CMPR32X2TS U1995 ( .A(Op_MX[44]), .B(Op_MX[17]), .C(n1560), .CO(n1559), .S(
n1762) );
NOR2X1TS U1996 ( .A(n900), .B(n1532), .Y(n1788) );
NOR2X1TS U1997 ( .A(n2199), .B(n1383), .Y(n2187) );
NAND2X1TS U1998 ( .A(n1013), .B(n2272), .Y(n2411) );
AOI21X1TS U1999 ( .A0(n1113), .A1(n2203), .B0(n2202), .Y(n2204) );
CMPR32X2TS U2000 ( .A(Op_MY[48]), .B(Op_MY[21]), .C(n1481), .CO(n1543), .S(
n1535) );
CMPR32X2TS U2001 ( .A(Op_MX[16]), .B(Op_MX[43]), .C(n1564), .CO(n1560), .S(
n1801) );
INVX4TS U2002 ( .A(Op_MX[33]), .Y(n8096) );
INVX2TS U2003 ( .A(n4115), .Y(n4223) );
CMPR32X2TS U2004 ( .A(Op_MY[20]), .B(Op_MY[47]), .C(n1488), .CO(n1481), .S(
n1533) );
CMPR32X2TS U2005 ( .A(Op_MX[42]), .B(n883), .C(n1565), .CO(n1564), .S(n1869)
);
NAND2X1TS U2006 ( .A(Op_MY[17]), .B(Op_MY[3]), .Y(n2271) );
NAND2X1TS U2007 ( .A(Op_MY[18]), .B(Op_MY[4]), .Y(n2267) );
NOR2X1TS U2008 ( .A(Op_MY[17]), .B(Op_MY[3]), .Y(n2266) );
NAND2X1TS U2009 ( .A(Op_MY[19]), .B(Op_MY[5]), .Y(n2261) );
NAND2X1TS U2010 ( .A(Op_MY[16]), .B(Op_MY[2]), .Y(n2276) );
CMPR32X2TS U2011 ( .A(Op_MY[44]), .B(Op_MY[17]), .C(n1502), .CO(n1501), .S(
n1765) );
CMPR32X2TS U2012 ( .A(Op_MY[43]), .B(Op_MY[16]), .C(n1509), .CO(n1502), .S(
n1767) );
OAI21X1TS U2013 ( .A0(n1575), .A1(n1571), .B0(n1572), .Y(n1562) );
INVX2TS U2014 ( .A(n816), .Y(n883) );
NOR2X1TS U2015 ( .A(n1650), .B(n1654), .Y(n1297) );
OAI21X1TS U2016 ( .A0(n1551), .A1(n1585), .B0(n1552), .Y(n1615) );
NOR2X2TS U2017 ( .A(Op_MX[37]), .B(Op_MX[10]), .Y(n1640) );
NAND2X1TS U2018 ( .A(Op_MY[38]), .B(Op_MY[11]), .Y(n1459) );
NAND2X1TS U2019 ( .A(Op_MY[32]), .B(Op_MY[5]), .Y(n1492) );
NOR2X1TS U2020 ( .A(Op_MY[34]), .B(Op_MY[7]), .Y(n1538) );
NOR2XLTS U2021 ( .A(n10191), .B(n10188), .Y(n10182) );
NOR2XLTS U2022 ( .A(n10239), .B(n10244), .Y(n10230) );
ADDHXLTS U2023 ( .A(n10126), .B(n10125), .CO(n10162), .S(n10169) );
INVX2TS U2024 ( .A(n3901), .Y(n1742) );
XOR2X1TS U2025 ( .A(n1631), .B(n802), .Y(n1632) );
NOR2XLTS U2026 ( .A(n3961), .B(n3943), .Y(n3922) );
NOR2XLTS U2027 ( .A(n5948), .B(n731), .Y(n5813) );
NOR2XLTS U2028 ( .A(n4592), .B(n4273), .Y(n4310) );
OR2X1TS U2029 ( .A(n4129), .B(n4128), .Y(n1143) );
INVX4TS U2030 ( .A(n1632), .Y(n2000) );
NOR2XLTS U2031 ( .A(n4688), .B(n4647), .Y(n4185) );
NOR2XLTS U2032 ( .A(n4070), .B(n4102), .Y(n4049) );
XNOR2X1TS U2033 ( .A(n1829), .B(n1828), .Y(n1899) );
NOR2X1TS U2034 ( .A(n2081), .B(n4304), .Y(n1901) );
OAI21XLTS U2035 ( .A0(n4862), .A1(n4861), .B0(n4860), .Y(n4863) );
ADDFX2TS U2036 ( .A(n10283), .B(n10282), .CI(n10281), .CO(n10277), .S(n10300) );
OR2X1TS U2037 ( .A(n3051), .B(n1530), .Y(n1128) );
NOR2XLTS U2038 ( .A(n2509), .B(n737), .Y(n2522) );
AFCSHCINX2TS U2039 ( .CI1N(DP_OP_338J35_122_4684_n13), .B(
DP_OP_338J35_122_4684_n51), .A(DP_OP_338J35_122_4684_n62), .CI0N(
DP_OP_338J35_122_4684_n14), .CS(DP_OP_338J35_122_4684_n15), .CO1(
DP_OP_338J35_122_4684_n11), .CO0(DP_OP_338J35_122_4684_n12), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
NOR2XLTS U2040 ( .A(n4512), .B(n4647), .Y(n3980) );
NOR2XLTS U2041 ( .A(n3258), .B(n805), .Y(n3384) );
NOR2XLTS U2042 ( .A(n1032), .B(n934), .Y(n1364) );
NOR2XLTS U2043 ( .A(n7943), .B(n8096), .Y(n7763) );
NOR2XLTS U2044 ( .A(n4605), .B(n4630), .Y(n4654) );
NOR2XLTS U2045 ( .A(n4943), .B(n4647), .Y(n4631) );
OA21XLTS U2046 ( .A0(n2297), .A1(n2300), .B0(n2298), .Y(n841) );
OAI21X1TS U2047 ( .A0(n2425), .A1(n841), .B0(n2424), .Y(n2441) );
ADDHXLTS U2048 ( .A(n7775), .B(n7774), .CO(n7785), .S(n7781) );
NOR2X1TS U2049 ( .A(n3063), .B(n3097), .Y(n3089) );
NOR2XLTS U2050 ( .A(n1700), .B(n1703), .Y(n1706) );
ADDHXLTS U2051 ( .A(n2553), .B(n2552), .CO(n2559), .S(n2562) );
NOR2XLTS U2052 ( .A(n812), .B(n8096), .Y(n7798) );
NOR2XLTS U2053 ( .A(n4273), .B(n4266), .Y(n1907) );
ADDHXLTS U2054 ( .A(n3366), .B(n3365), .CO(n3449), .S(n3358) );
NOR2XLTS U2055 ( .A(n6083), .B(n5860), .Y(n5985) );
INVX4TS U2056 ( .A(n4147), .Y(n4688) );
OAI21XLTS U2057 ( .A0(n2314), .A1(n2232), .B0(n2235), .Y(n2221) );
NOR2XLTS U2058 ( .A(n849), .B(n9948), .Y(n9939) );
NOR2XLTS U2059 ( .A(n4098), .B(n4052), .Y(n4043) );
OAI21XLTS U2060 ( .A0(n9826), .A1(n9822), .B0(n9823), .Y(n9820) );
NOR2XLTS U2061 ( .A(n810), .B(n757), .Y(n7802) );
ADDFX2TS U2062 ( .A(n3162), .B(n3161), .CI(n3160), .CO(n3459), .S(n3157) );
NOR2XLTS U2063 ( .A(n10239), .B(n4445), .Y(n4590) );
NOR2X1TS U2064 ( .A(n2081), .B(n4266), .Y(n1895) );
NAND2X1TS U2065 ( .A(n1095), .B(n1074), .Y(n1270) );
INVX2TS U2066 ( .A(n1888), .Y(n10245) );
OR2X1TS U2067 ( .A(Op_MY[15]), .B(Op_MY[42]), .Y(n1126) );
ADDFX2TS U2068 ( .A(n10304), .B(n10303), .CI(n10302), .CO(
DP_OP_338J35_122_4684_n96), .S(DP_OP_338J35_122_4684_n97) );
OAI21X2TS U2069 ( .A0(n1788), .A1(n1791), .B0(n1789), .Y(n1828) );
OAI21X1TS U2070 ( .A0(n1539), .A1(n1468), .B0(n1467), .Y(n1471) );
NOR2XLTS U2071 ( .A(DP_OP_346J35_130_4270_n836), .B(n774), .Y(n5746) );
INVX4TS U2072 ( .A(n2442), .Y(n9949) );
INVX2TS U2073 ( .A(n2229), .Y(n2530) );
NOR2XLTS U2074 ( .A(n4649), .B(n4714), .Y(n4211) );
NOR2XLTS U2075 ( .A(n4098), .B(n4030), .Y(n4083) );
NOR2XLTS U2076 ( .A(n2544), .B(n737), .Y(n2650) );
NOR2XLTS U2077 ( .A(n3548), .B(n805), .Y(n3583) );
OAI21XLTS U2078 ( .A0(n4977), .A1(n4976), .B0(n4975), .Y(n4978) );
NAND2X1TS U2079 ( .A(Op_MY[38]), .B(Op_MY[31]), .Y(n7678) );
NOR2XLTS U2080 ( .A(n2194), .B(n774), .Y(n1384) );
INVX4TS U2081 ( .A(n4487), .Y(n4911) );
NAND2X1TS U2082 ( .A(n5199), .B(n5198), .Y(n5449) );
ADDHXLTS U2083 ( .A(n3227), .B(n3226), .CO(n3210), .S(n3261) );
NAND2X1TS U2084 ( .A(n5166), .B(n993), .Y(n5450) );
NOR2XLTS U2085 ( .A(n4098), .B(n4512), .Y(n4511) );
NOR2XLTS U2086 ( .A(n764), .B(n748), .Y(n7116) );
NOR2XLTS U2087 ( .A(n1429), .B(n774), .Y(n1437) );
OAI21XLTS U2088 ( .A0(n2418), .A1(n2411), .B0(n2413), .Y(n2263) );
OR2X4TS U2089 ( .A(n839), .B(n2606), .Y(n849) );
NOR2XLTS U2090 ( .A(n1109), .B(n771), .Y(n5754) );
NOR2XLTS U2091 ( .A(n5190), .B(n5135), .Y(n5136) );
NOR2XLTS U2092 ( .A(n814), .B(n8018), .Y(n8053) );
NOR2X1TS U2093 ( .A(n883), .B(Op_MX[1]), .Y(n2351) );
NOR2XLTS U2094 ( .A(n2513), .B(n2544), .Y(n2334) );
OAI21XLTS U2095 ( .A0(n10075), .A1(n10085), .B0(n10086), .Y(n10076) );
OAI21XLTS U2096 ( .A0(n1704), .A1(n1584), .B0(n1585), .Y(n1549) );
NOR2XLTS U2097 ( .A(n751), .B(n730), .Y(n7077) );
NOR2XLTS U2098 ( .A(n839), .B(n2380), .Y(n2598) );
NAND2X1TS U2099 ( .A(Op_MY[22]), .B(Op_MY[8]), .Y(n2223) );
OR2X1TS U2100 ( .A(Op_MX[17]), .B(Op_MX[3]), .Y(n1021) );
NOR2XLTS U2101 ( .A(n10244), .B(n2174), .Y(n1983) );
OR2X1TS U2102 ( .A(n5059), .B(n5058), .Y(n1135) );
NOR2XLTS U2103 ( .A(n6083), .B(n6040), .Y(n6061) );
NOR2XLTS U2104 ( .A(n743), .B(n811), .Y(n8007) );
INVX4TS U2105 ( .A(n1857), .Y(n2041) );
NOR2XLTS U2106 ( .A(n10246), .B(n2174), .Y(n1978) );
OR2X1TS U2107 ( .A(Op_MX[39]), .B(n7477), .Y(n7444) );
NOR2XLTS U2108 ( .A(DP_OP_343J35_127_4270_n853), .B(n820), .Y(n7724) );
NOR2XLTS U2109 ( .A(n8049), .B(n814), .Y(n8071) );
NOR2XLTS U2110 ( .A(n2199), .B(Op_MX[25]), .Y(n1347) );
NOR2XLTS U2111 ( .A(n736), .B(n741), .Y(n7757) );
INVX4TS U2112 ( .A(n1290), .Y(n2199) );
NOR2XLTS U2113 ( .A(n917), .B(n9830), .Y(n9767) );
NOR2XLTS U2114 ( .A(n9995), .B(n2744), .Y(n2621) );
NOR2XLTS U2115 ( .A(n9829), .B(n763), .Y(n7144) );
NOR2XLTS U2116 ( .A(n9829), .B(n730), .Y(n7161) );
NOR2XLTS U2117 ( .A(n760), .B(n729), .Y(n7082) );
NOR2XLTS U2118 ( .A(n751), .B(n764), .Y(n7085) );
NOR2XLTS U2119 ( .A(n5190), .B(n5187), .Y(n5161) );
INVX2TS U2120 ( .A(n2576), .Y(n2880) );
OAI21XLTS U2121 ( .A0(n2909), .A1(n2921), .B0(n2910), .Y(n2898) );
NOR2XLTS U2122 ( .A(n766), .B(n731), .Y(n5996) );
NOR2XLTS U2123 ( .A(n744), .B(n740), .Y(n7563) );
NAND2X2TS U2124 ( .A(n4600), .B(n4599), .Y(n5022) );
AOI21X1TS U2125 ( .A0(n5266), .A1(n1135), .B0(n5255), .Y(n5258) );
OAI21XLTS U2126 ( .A0(n6174), .A1(n6153), .B0(n6154), .Y(n6098) );
NOR2XLTS U2127 ( .A(n9992), .B(n2799), .Y(n2777) );
NOR2XLTS U2128 ( .A(n2041), .B(n2174), .Y(n1973) );
NOR2XLTS U2129 ( .A(n819), .B(n738), .Y(n7996) );
NOR2X2TS U2130 ( .A(n4749), .B(n4748), .Y(n4797) );
NAND2X1TS U2131 ( .A(n1129), .B(n5468), .Y(n5487) );
NOR2XLTS U2132 ( .A(n917), .B(n9829), .Y(n9760) );
AOI21X1TS U2133 ( .A0(n1008), .A1(n1567), .B0(n1293), .Y(n1575) );
NOR2XLTS U2134 ( .A(add_x_87_n4), .B(n1256), .Y(n1257) );
NOR2X2TS U2135 ( .A(n5429), .B(n5428), .Y(n5495) );
NOR2XLTS U2136 ( .A(n751), .B(DP_OP_342J35_126_4270_n748), .Y(n7126) );
OAI21XLTS U2137 ( .A0(n7376), .A1(n8737), .B0(n8740), .Y(n7377) );
NOR2XLTS U2138 ( .A(n9668), .B(n9663), .Y(n9515) );
NOR2XLTS U2139 ( .A(n750), .B(n764), .Y(n7147) );
NOR2XLTS U2140 ( .A(n760), .B(n748), .Y(n7132) );
NOR2XLTS U2141 ( .A(n9653), .B(n9663), .Y(DP_OP_341J35_125_6458_n154) );
NOR2XLTS U2142 ( .A(n2876), .B(n2630), .Y(n2694) );
NOR2XLTS U2143 ( .A(n9991), .B(n2380), .Y(n2707) );
NOR2XLTS U2144 ( .A(n847), .B(n768), .Y(n5654) );
OAI21XLTS U2145 ( .A0(n3838), .A1(n3854), .B0(n3855), .Y(n3839) );
NAND2X1TS U2146 ( .A(n5023), .B(n5022), .Y(n5025) );
XOR2X1TS U2147 ( .A(n5258), .B(n5257), .Y(n5519) );
AOI21X2TS U2148 ( .A0(n3723), .A1(n3743), .B0(n3722), .Y(n3809) );
NOR2XLTS U2149 ( .A(n746), .B(n768), .Y(n5728) );
OAI21XLTS U2150 ( .A0(n2957), .A1(n2908), .B0(n2907), .Y(n2913) );
OAI21XLTS U2151 ( .A0(n8247), .A1(n8277), .B0(n8281), .Y(n8248) );
OR2X1TS U2152 ( .A(n3589), .B(n3588), .Y(n821) );
OAI21XLTS U2153 ( .A0(n6150), .A1(n6173), .B0(n6174), .Y(n6151) );
OAI21XLTS U2154 ( .A0(n8319), .A1(n8318), .B0(n8317), .Y(n8324) );
AOI21X2TS U2155 ( .A0(n5615), .A1(n958), .B0(n5445), .Y(n5493) );
ADDHXLTS U2156 ( .A(n2378), .B(n2377), .CO(n2374), .S(n2389) );
CLKMX2X2TS U2157 ( .A(DP_OP_345J35_129_3436_n17), .B(
DP_OP_345J35_129_3436_n16), .S0(DP_OP_345J35_129_3436_n20), .Y(
DP_OP_345J35_129_3436_n15) );
MXI2X2TS U2158 ( .A(add_x_87_n6), .B(add_x_87_n5), .S0(add_x_87_n11), .Y(
add_x_87_n1) );
NOR2XLTS U2159 ( .A(n750), .B(n763), .Y(n7133) );
NOR2XLTS U2160 ( .A(n9668), .B(n9666), .Y(n9626) );
OAI21XLTS U2161 ( .A0(n7174), .A1(n7211), .B0(n7212), .Y(n7175) );
NOR2XLTS U2162 ( .A(n5897), .B(n770), .Y(n5695) );
NAND2X1TS U2163 ( .A(n4377), .B(n4382), .Y(n4378) );
CLKMX2X2TS U2164 ( .A(add_x_87_n18), .B(add_x_87_n17), .S0(add_x_87_n21),
.Y(add_x_87_n16) );
NOR2XLTS U2165 ( .A(n847), .B(n770), .Y(n5687) );
NAND2X1TS U2166 ( .A(n1122), .B(n4322), .Y(n4323) );
NOR2XLTS U2167 ( .A(n9388), .B(n8782), .Y(n8784) );
NOR2XLTS U2168 ( .A(n9388), .B(n8787), .Y(n8788) );
OR2X1TS U2169 ( .A(n8116), .B(n8115), .Y(n8126) );
OAI21XLTS U2170 ( .A0(n8166), .A1(n8190), .B0(n8191), .Y(n8167) );
OAI21XLTS U2171 ( .A0(n4983), .A1(n4925), .B0(n4927), .Y(n4920) );
OAI21XLTS U2172 ( .A0(n4822), .A1(n4821), .B0(n4820), .Y(n4827) );
CLKXOR2X2TS U2173 ( .A(n5486), .B(n5485), .Y(n5625) );
ADDHXLTS U2174 ( .A(n2356), .B(n2453), .CO(n2357), .S(n2355) );
OAI2BB1X1TS U2175 ( .A0N(add_x_87_n4), .A1N(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[12]), .B0(n1254), .Y(Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[28]) );
ADDHXLTS U2176 ( .A(n9707), .B(n9706), .CO(n9700), .S(n9710) );
OAI21XLTS U2177 ( .A0(n7232), .A1(n7231), .B0(n7230), .Y(n7237) );
NOR2XLTS U2178 ( .A(n7412), .B(n7407), .Y(n7280) );
NOR2XLTS U2179 ( .A(n9946), .B(n2799), .Y(n2792) );
NOR2XLTS U2180 ( .A(n746), .B(n767), .Y(n5815) );
OAI21XLTS U2181 ( .A0(n3879), .A1(n5438), .B0(n3878), .Y(n3889) );
INVX4TS U2182 ( .A(n3931), .Y(n4647) );
CLKXOR2X2TS U2183 ( .A(n4384), .B(n4378), .Y(n4422) );
MXI2X1TS U2184 ( .A(n929), .B(n1256), .S0(n856), .Y(n1259) );
INVX2TS U2185 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[6]), .Y(n7630) );
NOR2XLTS U2186 ( .A(n9660), .B(n9599), .Y(n3008) );
NOR2X1TS U2187 ( .A(n4816), .B(n4815), .Y(n4853) );
NOR2XLTS U2188 ( .A(n9648), .B(n9625), .Y(n9573) );
NAND2X1TS U2189 ( .A(n5302), .B(n5301), .Y(n5303) );
OR2X1TS U2190 ( .A(n3778), .B(n3777), .Y(n922) );
NAND2X1TS U2191 ( .A(n6884), .B(n6883), .Y(n6889) );
OAI21XLTS U2192 ( .A0(n7358), .A1(n8722), .B0(n8725), .Y(n7359) );
CLKMX2X2TS U2193 ( .A(DP_OP_344J35_128_4078_n9), .B(DP_OP_344J35_128_4078_n8), .S0(DP_OP_344J35_128_4078_n12), .Y(DP_OP_344J35_128_4078_n1) );
AOI21X1TS U2194 ( .A0(n7406), .A1(n7280), .B0(n7279), .Y(n8732) );
NOR2XLTS U2195 ( .A(n9388), .B(n994), .Y(n9390) );
AOI21X2TS U2196 ( .A0(n2861), .A1(n2936), .B0(n2860), .Y(n2957) );
AOI21X1TS U2197 ( .A0(n921), .A1(n968), .B0(n3764), .Y(n4431) );
OAI21XLTS U2198 ( .A0(n2957), .A1(n2956), .B0(n2955), .Y(n2962) );
NOR2XLTS U2199 ( .A(n10428), .B(n10420), .Y(n10308) );
NAND2X1TS U2200 ( .A(n7013), .B(n7012), .Y(n7014) );
OAI21XLTS U2201 ( .A0(n6821), .A1(n6820), .B0(n6819), .Y(n6824) );
NOR2X2TS U2202 ( .A(n9110), .B(n9109), .Y(n9373) );
INVX2TS U2203 ( .A(n10573), .Y(n8803) );
AOI21X2TS U2204 ( .A0(n8865), .A1(n1141), .B0(n5619), .Y(n8859) );
OAI21XLTS U2205 ( .A0(n7416), .A1(n7412), .B0(n7413), .Y(n7411) );
NOR2X1TS U2206 ( .A(n7229), .B(n1230), .Y(n8480) );
OAI21X1TS U2207 ( .A0(n8732), .A1(n8731), .B0(n8730), .Y(n8750) );
NOR2X1TS U2208 ( .A(n6798), .B(n6797), .Y(n6986) );
XNOR2X1TS U2209 ( .A(n8908), .B(n8907), .Y(n9167) );
CLKXOR2X2TS U2210 ( .A(n8873), .B(n8872), .Y(n9149) );
OAI21XLTS U2211 ( .A0(n6820), .A1(n6624), .B0(n6625), .Y(n6621) );
OAI21X1TS U2212 ( .A0(n8614), .A1(n8617), .B0(n8615), .Y(n8620) );
AOI21X2TS U2213 ( .A0(n7015), .A1(n930), .B0(n7014), .Y(n7021) );
NAND2X1TS U2214 ( .A(n8815), .B(n8813), .Y(n8807) );
OAI21XLTS U2215 ( .A0(n5068), .A1(n5067), .B0(n5066), .Y(n5073) );
OAI21X2TS U2216 ( .A0(n10864), .A1(n10859), .B0(n10865), .Y(n9356) );
NOR2XLTS U2217 ( .A(n10403), .B(n10402), .Y(n10381) );
NOR2X1TS U2218 ( .A(n8834), .B(n9428), .Y(n9413) );
NOR2X1TS U2219 ( .A(n1224), .B(n9480), .Y(n9466) );
OA21X1TS U2220 ( .A0(n9395), .A1(n9394), .B0(n9392), .Y(n798) );
NOR2X2TS U2221 ( .A(n9339), .B(n9740), .Y(n10737) );
NAND2X1TS U2222 ( .A(n8763), .B(n7030), .Y(n7031) );
INVX2TS U2223 ( .A(n8769), .Y(n8513) );
NOR2XLTS U2224 ( .A(n6947), .B(n6954), .Y(n6949) );
NAND2X2TS U2225 ( .A(n7019), .B(n7018), .Y(n8775) );
NOR2XLTS U2226 ( .A(n9388), .B(n8807), .Y(n8809) );
NAND2X1TS U2227 ( .A(n6999), .B(n6998), .Y(n8531) );
NAND2X1TS U2228 ( .A(n7003), .B(n7002), .Y(n8518) );
ADDHX1TS U2229 ( .A(n9708), .B(n8747), .CO(n8748), .S(n9425) );
XNOR2X1TS U2230 ( .A(n8682), .B(n959), .Y(n9458) );
OAI21X1TS U2231 ( .A0(n8776), .A1(n8506), .B0(n8505), .Y(n8507) );
OAI21XLTS U2232 ( .A0(n10861), .A1(n10714), .B0(n10713), .Y(n10715) );
OR2X1TS U2233 ( .A(n9321), .B(n9320), .Y(n1175) );
NOR2XLTS U2234 ( .A(n10858), .B(n10774), .Y(n10776) );
AOI21X2TS U2235 ( .A0(n7005), .A1(n8516), .B0(n7004), .Y(n8515) );
OR2X2TS U2236 ( .A(n9343), .B(n9737), .Y(n1178) );
OAI21XLTS U2237 ( .A0(n10861), .A1(n10847), .B0(n10846), .Y(n10848) );
ADDHX1TS U2238 ( .A(n9741), .B(n8721), .CO(n8747), .S(n9406) );
NOR2XLTS U2239 ( .A(n909), .B(n9414), .Y(n9416) );
NOR2XLTS U2240 ( .A(n909), .B(n9457), .Y(n9459) );
NOR2XLTS U2241 ( .A(n909), .B(n9480), .Y(n9481) );
NOR2X1TS U2242 ( .A(n909), .B(n9471), .Y(n9472) );
XNOR2X1TS U2243 ( .A(n8832), .B(n1056), .Y(n9128) );
NOR2X1TS U2244 ( .A(n9388), .B(n8826), .Y(n8828) );
INVX2TS U2245 ( .A(n8840), .Y(n8852) );
CLKINVX2TS U2246 ( .A(n8841), .Y(n8843) );
XOR2X2TS U2247 ( .A(n5494), .B(n5493), .Y(n5621) );
INVX2TS U2248 ( .A(n5490), .Y(n5492) );
MX2X1TS U2249 ( .A(P_Sgf[45]), .B(n10586), .S0(n10611), .Y(n466) );
MX2X1TS U2250 ( .A(P_Sgf[44]), .B(n10582), .S0(n10611), .Y(n465) );
XNOR2X2TS U2251 ( .A(n5453), .B(n5442), .Y(n5443) );
INVX1TS U2252 ( .A(n9413), .Y(n9414) );
XOR2X2TS U2253 ( .A(n5418), .B(n5417), .Y(n5429) );
MX2X1TS U2254 ( .A(P_Sgf[43]), .B(n10610), .S0(n10611), .Y(n464) );
ADDHX1TS U2255 ( .A(n5467), .B(n5466), .CO(n5481), .S(n5199) );
NAND2X1TS U2256 ( .A(n8761), .B(n8762), .Y(n8765) );
NOR2X2TS U2257 ( .A(n5143), .B(n5142), .Y(n5414) );
OAI21XLTS U2258 ( .A0(n9510), .A1(Sgf_normalized_result[52]), .B0(n9495),
.Y(n9493) );
MXI2X1TS U2259 ( .A(n1236), .B(n1130), .S0(DP_OP_338J35_122_4684_n32), .Y(
n1233) );
OAI211XLTS U2260 ( .A0(Sgf_normalized_result[50]), .A1(n11163), .B0(n11162),
.C0(n11161), .Y(n11164) );
NOR2X2TS U2261 ( .A(n6999), .B(n6998), .Y(n8530) );
CLKINVX2TS U2262 ( .A(n8689), .Y(n8693) );
INVX2TS U2263 ( .A(n9456), .Y(n9457) );
NAND2X1TS U2264 ( .A(n1135), .B(n5264), .Y(n5265) );
INVX2TS U2265 ( .A(n8807), .Y(n8797) );
NAND2XLTS U2266 ( .A(n8705), .B(n8704), .Y(n8706) );
INVX3TS U2267 ( .A(n8827), .Y(n4874) );
NAND2XLTS U2268 ( .A(n8714), .B(n9747), .Y(n8522) );
ADDFHX1TS U2269 ( .A(n10212), .B(n10211), .CI(n10210), .CO(n10206), .S(
n10259) );
INVX1TS U2270 ( .A(n8683), .Y(n8685) );
MXI2X1TS U2271 ( .A(n1245), .B(n1244), .S0(DP_OP_345J35_129_3436_n32), .Y(
n1239) );
ADDHX1TS U2272 ( .A(n1809), .B(n1808), .CO(n2013), .S(n1826) );
ADDFX1TS U2273 ( .A(n6594), .B(n1005), .CI(n6593), .CO(n6595), .S(n6658) );
XNOR2X1TS U2274 ( .A(n4883), .B(n978), .Y(n4886) );
NAND2X1TS U2275 ( .A(n4969), .B(n4968), .Y(n4975) );
ADDFX1TS U2276 ( .A(n2823), .B(n2822), .CI(n2821), .CO(n2815), .S(n6592) );
INVX4TS U2277 ( .A(n1797), .Y(n10203) );
ADDHX1TS U2278 ( .A(n6571), .B(n6570), .CO(n6574), .S(n6772) );
INVX1TS U2279 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[7]), .Y(n7517) );
INVX1TS U2280 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[5]), .Y(n7628) );
INVX1TS U2281 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[4]), .Y(n7626) );
INVX1TS U2282 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[3]), .Y(n7624) );
INVX4TS U2283 ( .A(n4556), .Y(n4943) );
OAI22X1TS U2284 ( .A0(n3258), .A1(n3478), .B0(n3279), .B1(n3560), .Y(n3136)
);
INVX2TS U2285 ( .A(n1683), .Y(n5177) );
NAND2X1TS U2286 ( .A(DP_OP_342J35_126_4270_n146), .B(
DP_OP_342J35_126_4270_n156), .Y(n7259) );
OAI21X1TS U2287 ( .A0(n8291), .A1(n8294), .B0(n8292), .Y(n8275) );
XOR2X1TS U2288 ( .A(n2294), .B(n841), .Y(n2295) );
INVX4TS U2289 ( .A(n2361), .Y(n9994) );
NOR2X1TS U2290 ( .A(n2342), .B(n6853), .Y(n2327) );
INVX4TS U2291 ( .A(n826), .Y(n882) );
NOR2X1TS U2292 ( .A(n10408), .B(n10393), .Y(DP_OP_347J35_131_5122_n157) );
NOR2X2TS U2293 ( .A(n8221), .B(n8220), .Y(n8244) );
INVX4TS U2294 ( .A(n3432), .Y(n752) );
NOR2X1TS U2295 ( .A(n10413), .B(n10402), .Y(DP_OP_347J35_131_5122_n164) );
NOR2X1TS U2296 ( .A(n10413), .B(n10393), .Y(DP_OP_347J35_131_5122_n165) );
CLKINVX3TS U2297 ( .A(n10498), .Y(n10965) );
NOR2X1TS U2298 ( .A(n10412), .B(n10427), .Y(n10386) );
INVX4TS U2299 ( .A(n7705), .Y(n7900) );
OR2X1TS U2300 ( .A(n4462), .B(Op_MX[25]), .Y(n4526) );
NOR2X1TS U2301 ( .A(n10407), .B(n10427), .Y(n10382) );
INVX3TS U2302 ( .A(n5680), .Y(n5941) );
NOR2X1TS U2303 ( .A(n10403), .B(n10407), .Y(n10387) );
NOR2X1TS U2304 ( .A(n7943), .B(n8036), .Y(n7829) );
NOR2X1TS U2305 ( .A(n8082), .B(n7943), .Y(n7920) );
INVX2TS U2306 ( .A(n7706), .Y(n8093) );
INVX2TS U2307 ( .A(n2478), .Y(n2482) );
OR2X1TS U2308 ( .A(Op_MX[14]), .B(Op_MX[0]), .Y(n1105) );
XNOR2X1TS U2309 ( .A(n9487), .B(n8917), .Y(n9488) );
XNOR2X1TS U2310 ( .A(n9475), .B(n1222), .Y(n9476) );
XNOR2X1TS U2311 ( .A(n9416), .B(n8830), .Y(n9417) );
XNOR2X1TS U2312 ( .A(n9481), .B(n1224), .Y(n9482) );
NOR2X1TS U2313 ( .A(n909), .B(n8923), .Y(n9487) );
NOR2X1TS U2314 ( .A(n909), .B(n9446), .Y(n9448) );
NOR2X1TS U2315 ( .A(n909), .B(n9424), .Y(n9426) );
NOR2X1TS U2316 ( .A(n909), .B(n9462), .Y(n9464) );
NOR2X1TS U2317 ( .A(n909), .B(n9434), .Y(n9435) );
NOR2X1TS U2318 ( .A(n909), .B(n9428), .Y(n9429) );
NAND2X4TS U2319 ( .A(n9386), .B(n9385), .Y(n10485) );
XOR2X4TS U2320 ( .A(n9114), .B(n9395), .Y(n9386) );
NOR2X4TS U2321 ( .A(n9396), .B(n9391), .Y(n9392) );
OR2X4TS U2322 ( .A(n9112), .B(n9111), .Y(n1075) );
XNOR2X1TS U2323 ( .A(n8809), .B(n5110), .Y(n9116) );
XNOR2X1TS U2324 ( .A(n8821), .B(n829), .Y(n9122) );
XNOR2X2TS U2325 ( .A(n8784), .B(n5142), .Y(n9112) );
NOR2X1TS U2326 ( .A(n9388), .B(n8820), .Y(n8821) );
INVX2TS U2327 ( .A(n8848), .Y(n8850) );
INVX2TS U2328 ( .A(n10729), .Y(n9341) );
OAI21X4TS U2329 ( .A0(n5490), .A1(n5493), .B0(n5491), .Y(n5489) );
INVX2TS U2330 ( .A(n8876), .Y(n5611) );
NOR2X4TS U2331 ( .A(n5447), .B(n5446), .Y(n5490) );
NAND2X2TS U2332 ( .A(n5429), .B(n5428), .Y(n5496) );
ADDHX1TS U2333 ( .A(n5482), .B(n5481), .CO(n5483), .S(n5468) );
NOR2X2TS U2334 ( .A(n5166), .B(n993), .Y(n5448) );
INVX1TS U2335 ( .A(n8763), .Y(n8505) );
XNOR2X1TS U2336 ( .A(n5222), .B(n5221), .Y(n5511) );
ADDFHX2TS U2337 ( .A(n5186), .B(n1131), .CI(n5185), .CO(n5466), .S(n5166) );
NOR2X4TS U2338 ( .A(n7019), .B(n7018), .Y(n8769) );
NAND2X1TS U2339 ( .A(n940), .B(n5220), .Y(n5221) );
INVX2TS U2340 ( .A(n8516), .Y(n8528) );
INVX2TS U2341 ( .A(n9463), .Y(n8853) );
NOR2X2TS U2342 ( .A(n8525), .B(n8517), .Y(n7005) );
AOI21X2TS U2343 ( .A0(n7015), .A1(n930), .B0(n7010), .Y(n7011) );
INVX2TS U2344 ( .A(n5228), .Y(n5248) );
XNOR2X1TS U2345 ( .A(n8711), .B(n8710), .Y(n9463) );
INVX2TS U2346 ( .A(n9442), .Y(n8879) );
AO22XLTS U2347 ( .A0(n11160), .A1(n11159), .B0(n11158), .B1(n876), .Y(n530)
);
INVX2TS U2348 ( .A(n8530), .Y(n8532) );
OAI21X1TS U2349 ( .A0(n8693), .A1(n8692), .B0(n8691), .Y(n8698) );
MXI2X1TS U2350 ( .A(n1238), .B(n1237), .S0(DP_OP_338J35_122_4684_n32), .Y(
n1232) );
INVX2TS U2351 ( .A(n5254), .Y(n5266) );
XOR2X2TS U2352 ( .A(n6895), .B(n6894), .Y(n7003) );
OAI21X1TS U2353 ( .A0(n8717), .A1(n8523), .B0(n8522), .Y(n8524) );
OAI211XLTS U2354 ( .A0(Sgf_normalized_result[48]), .A1(n11154), .B0(n11162),
.C0(n11157), .Y(n11155) );
AO22XLTS U2355 ( .A0(n11160), .A1(n11153), .B0(n11069), .B1(n875), .Y(n532)
);
NAND2X1TS U2356 ( .A(n1136), .B(n5256), .Y(n5257) );
OR2X4TS U2357 ( .A(n5060), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .Y(n1136) );
OR2X4TS U2358 ( .A(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .B(n4886), .Y(n1160) );
NOR2X6TS U2359 ( .A(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .B(n4885), .Y(n5076) );
OR2X4TS U2360 ( .A(n6893), .B(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[28]), .Y(n825) );
AO22XLTS U2361 ( .A0(n11160), .A1(n11149), .B0(n11069), .B1(n874), .Y(n534)
);
XNOR2X1TS U2362 ( .A(n6912), .B(n981), .Y(n8548) );
XNOR2X1TS U2363 ( .A(n6915), .B(n6914), .Y(n8551) );
CLKINVX1TS U2364 ( .A(n8714), .Y(n8708) );
INVX1TS U2365 ( .A(n8692), .Y(n8688) );
OR2X2TS U2366 ( .A(n6805), .B(n6804), .Y(n945) );
INVX1TS U2367 ( .A(n8694), .Y(n8696) );
INVX2TS U2368 ( .A(n4923), .Y(n5067) );
INVX2TS U2369 ( .A(n5189), .Y(n5091) );
XNOR2X1TS U2370 ( .A(n5227), .B(n5226), .Y(n8982) );
XNOR2X1TS U2371 ( .A(n5465), .B(n5464), .Y(n5482) );
XNOR2X1TS U2372 ( .A(n5184), .B(n5183), .Y(n5467) );
NOR2X1TS U2373 ( .A(DP_OP_345J35_129_3436_n4), .B(n1241), .Y(n1243) );
OAI21X1TS U2374 ( .A0(n3916), .A1(n3913), .B0(n3914), .Y(n5127) );
INVX2TS U2375 ( .A(n4792), .Y(n4822) );
XNOR2X1TS U2376 ( .A(n4450), .B(n4449), .Y(n4597) );
XNOR2X1TS U2377 ( .A(n4389), .B(n4388), .Y(n4411) );
INVX2TS U2378 ( .A(n3903), .Y(n1808) );
ADDHX2TS U2379 ( .A(n1742), .B(n1741), .CO(n1809), .S(n1933) );
INVX2TS U2380 ( .A(n3902), .Y(n1932) );
ADDFHX2TS U2381 ( .A(n8985), .B(n8984), .CI(n8983), .CO(n8978), .S(n9204) );
ADDHX1TS U2382 ( .A(n1757), .B(n1756), .CO(n1741), .S(n1935) );
XOR2X1TS U2383 ( .A(n3633), .B(n3632), .Y(n3875) );
XOR2X1TS U2384 ( .A(n3845), .B(n3844), .Y(n3867) );
XOR2X1TS U2385 ( .A(n3858), .B(n3857), .Y(n3865) );
ADDHX1TS U2386 ( .A(n1752), .B(n1751), .CO(n1757), .S(n1938) );
CLKXOR2X2TS U2387 ( .A(n7391), .B(n7390), .Y(n9708) );
CLKXOR2X2TS U2388 ( .A(n8757), .B(n1212), .Y(n9696) );
CLKXOR2X2TS U2389 ( .A(n7401), .B(n7400), .Y(n9742) );
CLKXOR2X2TS U2390 ( .A(n7394), .B(n7393), .Y(n9741) );
ADDFX2TS U2391 ( .A(n2817), .B(n2816), .CI(n2815), .CO(n9879), .S(n6594) );
XNOR2X1TS U2392 ( .A(n8384), .B(n8383), .Y(n9694) );
INVX2TS U2393 ( .A(n9745), .Y(DP_OP_344J35_128_4078_n150) );
ADDFX2TS U2394 ( .A(n10059), .B(n10058), .CI(n10057), .CO(n10064), .S(n10066) );
INVX2TS U2395 ( .A(n3679), .Y(n3853) );
CMPR22X2TS U2396 ( .A(n9895), .B(n9894), .CO(DP_OP_345J35_129_3436_n32), .S(
DP_OP_345J35_129_3436_n33) );
OAI21X1TS U2397 ( .A0(n8381), .A1(n8417), .B0(n8380), .Y(n8384) );
OAI21X1TS U2398 ( .A0(n2957), .A1(n2920), .B0(n2919), .Y(n2924) );
OAI21X1TS U2399 ( .A0(n2941), .A1(n2940), .B0(n2939), .Y(n2946) );
ADDFX2TS U2400 ( .A(n2620), .B(n2619), .CI(n2618), .CO(n10009), .S(n2622) );
AO21X1TS U2401 ( .A0(n3618), .A1(n821), .B0(n3617), .Y(n912) );
CLKAND2X2TS U2402 ( .A(n1246), .B(n1247), .Y(n992) );
INVX1TS U2403 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[8]), .Y(n7515) );
OAI22X1TS U2404 ( .A0(n5177), .A1(n1810), .B0(n5149), .B1(n2000), .Y(n1818)
);
OAI22X1TS U2405 ( .A0(n10247), .A1(n2105), .B0(n10245), .B1(n2041), .Y(n1989) );
OAI22X1TS U2406 ( .A0(n10185), .A1(n2170), .B0(n10187), .B1(n2105), .Y(n2110) );
OAI22X1TS U2407 ( .A0(n5148), .A1(n1730), .B0(n2005), .B1(n1810), .Y(n1716)
);
OAI22X1TS U2408 ( .A0(n10166), .A1(n2170), .B0(n10165), .B1(n2105), .Y(n2113) );
NOR2X2TS U2409 ( .A(n3530), .B(n3529), .Y(n3682) );
OAI22X1TS U2410 ( .A0(n2004), .A1(n1730), .B0(n1823), .B1(n1810), .Y(n1665)
);
OR2X2TS U2411 ( .A(n3571), .B(n3570), .Y(n1162) );
XOR2X1TS U2412 ( .A(n3640), .B(n3639), .Y(n3874) );
ADDFHX1TS U2413 ( .A(n3517), .B(n3516), .CI(n3515), .CO(n3522), .S(n3524) );
XNOR2X1TS U2414 ( .A(n3774), .B(n3773), .Y(n3775) );
XNOR2X1TS U2415 ( .A(n3767), .B(n3766), .Y(n3776) );
CLKAND2X2TS U2416 ( .A(n973), .B(n10118), .Y(n856) );
XOR2X1TS U2417 ( .A(n7232), .B(n7063), .Y(n7229) );
NOR2X1TS U2418 ( .A(n9653), .B(n9667), .Y(n9542) );
XOR2X1TS U2419 ( .A(n7373), .B(n7052), .Y(n7245) );
XOR2X1TS U2420 ( .A(n3850), .B(n3849), .Y(n3866) );
INVX2TS U2421 ( .A(n1854), .Y(n2033) );
XOR2X1TS U2422 ( .A(n3863), .B(n3862), .Y(n3864) );
AOI21X1TS U2423 ( .A0(n1205), .A1(n8625), .B0(n8271), .Y(n8272) );
ADDHX1TS U2424 ( .A(n2344), .B(n2343), .CO(n2552), .S(n2363) );
XOR2X1TS U2425 ( .A(n8295), .B(n8294), .Y(n8300) );
OAI22X1TS U2426 ( .A0(n3364), .A1(n3560), .B0(n3354), .B1(n805), .Y(n3362)
);
NOR2X1TS U2427 ( .A(n9653), .B(n9650), .Y(n9546) );
NOR2X1TS U2428 ( .A(n9662), .B(n9681), .Y(n9679) );
XNOR2X1TS U2429 ( .A(n2426), .B(n2441), .Y(n2427) );
ADDHX1TS U2430 ( .A(n3130), .B(n3129), .CO(n3143), .S(n3145) );
INVX4TS U2431 ( .A(n2970), .Y(n9582) );
NOR2X1TS U2432 ( .A(n3349), .B(n805), .Y(n3366) );
OAI22X1TS U2433 ( .A0(n3364), .A1(n3257), .B0(n3354), .B1(n3350), .Y(n3308)
);
OAI22X1TS U2434 ( .A0(n3548), .A1(n3257), .B0(n3484), .B1(n3350), .Y(n3113)
);
INVX2TS U2435 ( .A(n1870), .Y(n2169) );
CLKXOR2X4TS U2436 ( .A(Op_MX[39]), .B(n7477), .Y(n2970) );
XNOR2X1TS U2437 ( .A(n8298), .B(n8297), .Y(n8299) );
ADDFHX2TS U2438 ( .A(Op_MY[22]), .B(Op_MY[49]), .CI(n1543), .CO(n1478), .S(
n1770) );
XNOR2X1TS U2439 ( .A(n2360), .B(n2359), .Y(n2361) );
INVX2TS U2440 ( .A(n2346), .Y(n2378) );
INVX2TS U2441 ( .A(n8287), .Y(n8258) );
XOR2X1TS U2442 ( .A(n8234), .B(n8233), .Y(n8235) );
OAI21X1TS U2443 ( .A0(n7615), .A1(n7611), .B0(n7612), .Y(n7191) );
OAI22X1TS U2444 ( .A0(n3199), .A1(n879), .B0(n3202), .B1(n3346), .Y(n3302)
);
NOR2X1TS U2445 ( .A(n3059), .B(n3091), .Y(n3061) );
OAI22X1TS U2446 ( .A0(n3102), .A1(n899), .B0(n3040), .B1(n3390), .Y(n3104)
);
INVX2TS U2447 ( .A(n1780), .Y(n1531) );
OAI21X1TS U2448 ( .A0(n8281), .A1(n8280), .B0(n8279), .Y(n8282) );
NAND2X1TS U2449 ( .A(n2265), .B(n2424), .Y(n2294) );
OAI22X1TS U2450 ( .A0(n3392), .A1(n3483), .B0(n3375), .B1(n3555), .Y(n3394)
);
NOR2X1TS U2451 ( .A(n2545), .B(n737), .Y(n2529) );
NOR2X1TS U2452 ( .A(n7187), .B(n7611), .Y(n7156) );
INVX4TS U2453 ( .A(n3345), .Y(n908) );
XOR2X1TS U2454 ( .A(n7251), .B(n7060), .Y(n7244) );
INVX2TS U2455 ( .A(n2296), .Y(n2798) );
OR2X2TS U2456 ( .A(n4120), .B(n4119), .Y(n1037) );
INVX2TS U2457 ( .A(n2585), .Y(n2894) );
INVX2TS U2458 ( .A(n8138), .Y(n7791) );
OAI22X1TS U2459 ( .A0(n8083), .A1(n7908), .B0(n814), .B1(n7909), .Y(n7790)
);
OAI22X1TS U2460 ( .A0(n8050), .A1(n7944), .B0(n8017), .B1(n7905), .Y(n7769)
);
OAI22X1TS U2461 ( .A0(n8017), .A1(n8036), .B0(n7898), .B1(n8081), .Y(n7727)
);
OAI22X1TS U2462 ( .A0(n8049), .A1(n7900), .B0(n7998), .B1(n7898), .Y(n7865)
);
INVX2TS U2463 ( .A(n753), .Y(n3388) );
OAI22X1TS U2464 ( .A0(n8049), .A1(n7898), .B0(n7998), .B1(n8017), .Y(n7765)
);
INVX2TS U2465 ( .A(n2355), .Y(n2797) );
XOR2X1TS U2466 ( .A(n2407), .B(n2406), .Y(n2579) );
INVX4TS U2467 ( .A(n2467), .Y(n2824) );
NOR2X1TS U2468 ( .A(n10419), .B(n10427), .Y(n10390) );
NOR2X1TS U2469 ( .A(n10411), .B(n10402), .Y(n10388) );
OAI21X1TS U2470 ( .A0(n2314), .A1(n2224), .B0(n2223), .Y(n2227) );
NOR2X1TS U2471 ( .A(n10421), .B(n10412), .Y(n10398) );
OAI21X1TS U2472 ( .A0(n1677), .A1(n1640), .B0(n1641), .Y(n1594) );
NOR2X1TS U2473 ( .A(n10412), .B(n10403), .Y(n10380) );
NOR2X1TS U2474 ( .A(n10421), .B(n10407), .Y(n10379) );
INVX2TS U2475 ( .A(n2466), .Y(n9947) );
OAI22X1TS U2476 ( .A0(n7905), .A1(n7910), .B0(n7944), .B1(n7900), .Y(n7913)
);
OAI22X1TS U2477 ( .A0(n8049), .A1(n7910), .B0(n7998), .B1(n7900), .Y(n7887)
);
INVX2TS U2478 ( .A(n8135), .Y(n7868) );
INVX4TS U2479 ( .A(n7429), .Y(n9618) );
NOR2X1TS U2480 ( .A(n2745), .B(n2630), .Y(n2682) );
NAND2X2TS U2481 ( .A(n1699), .B(n1117), .Y(n1303) );
INVX1TS U2482 ( .A(n2365), .Y(n2367) );
AO21X1TS U2483 ( .A0(n7381), .A1(n905), .B0(DP_OP_342J35_126_4270_n852), .Y(
n8735) );
XOR2X1TS U2484 ( .A(n7704), .B(n7703), .Y(n7705) );
AO21X1TS U2485 ( .A0(n7321), .A1(n728), .B0(DP_OP_342J35_126_4270_n853), .Y(
n7344) );
NOR2XLTS U2486 ( .A(n5948), .B(n5835), .Y(n5892) );
OAI21X1TS U2487 ( .A0(n7694), .A1(n7701), .B0(n7695), .Y(n7655) );
OR2X2TS U2488 ( .A(n906), .B(n2474), .Y(n1107) );
INVX2TS U2489 ( .A(n7654), .Y(n8049) );
NOR2X1TS U2490 ( .A(n7694), .B(n7700), .Y(n7656) );
INVX2TS U2491 ( .A(n1475), .Y(n1465) );
NAND2X6TS U2492 ( .A(n1158), .B(n1519), .Y(n1449) );
NOR2X1TS U2493 ( .A(n812), .B(n756), .Y(n7529) );
OR2X2TS U2494 ( .A(Op_MY[48]), .B(Op_MY[41]), .Y(n1145) );
XNOR2X1TS U2495 ( .A(n9438), .B(n806), .Y(n9439) );
OAI21X1TS U2496 ( .A0(n9508), .A1(n9504), .B0(n9505), .Y(n9502) );
CLKMX2X2TS U2497 ( .A(P_Sgf[81]), .B(n10489), .S0(n10897), .Y(n502) );
CLKMX2X2TS U2498 ( .A(P_Sgf[80]), .B(n10477), .S0(n10897), .Y(n501) );
CLKMX2X2TS U2499 ( .A(P_Sgf[79]), .B(n10483), .S0(n10897), .Y(n500) );
CLKMX2X2TS U2500 ( .A(P_Sgf[78]), .B(n10473), .S0(n10897), .Y(n499) );
CLKMX2X2TS U2501 ( .A(P_Sgf[77]), .B(n10467), .S0(n10897), .Y(n498) );
INVX1TS U2502 ( .A(n9498), .Y(n9500) );
CLKMX2X2TS U2503 ( .A(P_Sgf[76]), .B(n10463), .S0(n10897), .Y(n497) );
XNOR2X4TS U2504 ( .A(n9397), .B(n9396), .Y(n9399) );
NAND2X2TS U2505 ( .A(n9383), .B(n9382), .Y(n10474) );
CLKMX2X2TS U2506 ( .A(P_Sgf[75]), .B(n10459), .S0(n10897), .Y(n496) );
CLKMX2X2TS U2507 ( .A(P_Sgf[74]), .B(n10455), .S0(n10897), .Y(n495) );
CLKMX2X2TS U2508 ( .A(P_Sgf[73]), .B(n10898), .S0(n10897), .Y(n494) );
CLKMX2X2TS U2509 ( .A(P_Sgf[71]), .B(n10883), .S0(n10897), .Y(n492) );
CLKMX2X2TS U2510 ( .A(P_Sgf[72]), .B(n10890), .S0(n10897), .Y(n493) );
CLKMX2X2TS U2511 ( .A(P_Sgf[69]), .B(n10853), .S0(n10897), .Y(n490) );
CLKMX2X2TS U2512 ( .A(P_Sgf[70]), .B(n10869), .S0(n10897), .Y(n491) );
AFHCONX2TS U2513 ( .A(n9117), .B(n9116), .CI(n9115), .CON(n9365), .S(n10462)
);
CLKMX2X2TS U2514 ( .A(P_Sgf[68]), .B(n10840), .S0(n10897), .Y(n489) );
CLKMX2X2TS U2515 ( .A(P_Sgf[67]), .B(n10702), .S0(n10782), .Y(n488) );
OAI21X1TS U2516 ( .A0(n10861), .A1(n10860), .B0(n10859), .Y(n10862) );
NOR2X1TS U2517 ( .A(n10858), .B(n10860), .Y(n10863) );
NOR2X1TS U2518 ( .A(n10858), .B(n10847), .Y(n10849) );
CLKMX2X2TS U2519 ( .A(P_Sgf[66]), .B(n10692), .S0(n10782), .Y(n487) );
NOR2X4TS U2520 ( .A(n10864), .B(n10860), .Y(n9357) );
OAI21X1TS U2521 ( .A0(n10861), .A1(n10696), .B0(n10695), .Y(n10697) );
CLKMX2X2TS U2522 ( .A(P_Sgf[65]), .B(n10712), .S0(n10782), .Y(n486) );
OAI21X2TS U2523 ( .A0(n10835), .A1(n10831), .B0(n10836), .Y(n10845) );
OAI21X1TS U2524 ( .A0(n10861), .A1(n10832), .B0(n10831), .Y(n10833) );
NAND2X4TS U2525 ( .A(n1207), .B(n10844), .Y(n10860) );
NOR2X1TS U2526 ( .A(n10858), .B(n10832), .Y(n10834) );
CLKXOR2X2TS U2527 ( .A(n9390), .B(n9389), .Y(n9396) );
NAND2X2TS U2528 ( .A(n9352), .B(n9351), .Y(n10850) );
NOR2X1TS U2529 ( .A(n10858), .B(n10696), .Y(n10698) );
OAI21X1TS U2530 ( .A0(n10861), .A1(n10684), .B0(n10683), .Y(n10685) );
NOR2X1TS U2531 ( .A(n9388), .B(n8814), .Y(n8816) );
NOR2X1TS U2532 ( .A(n9388), .B(n8792), .Y(n8794) );
NOR2X1TS U2533 ( .A(n9388), .B(n8798), .Y(n8800) );
CLKMX2X2TS U2534 ( .A(P_Sgf[64]), .B(n10722), .S0(n10782), .Y(n485) );
BUFX12TS U2535 ( .A(n8836), .Y(n9388) );
XOR2X2TS U2536 ( .A(n8852), .B(n8851), .Y(n9140) );
NOR2X1TS U2537 ( .A(n10858), .B(n10706), .Y(n10708) );
NOR2X1TS U2538 ( .A(n10858), .B(n10684), .Y(n10686) );
OR2X4TS U2539 ( .A(n9347), .B(n9346), .Y(n1177) );
OAI21X1TS U2540 ( .A0(n10861), .A1(n10706), .B0(n10705), .Y(n10707) );
NAND2X2TS U2541 ( .A(n1178), .B(n10703), .Y(n10684) );
NOR2X4TS U2542 ( .A(n9345), .B(n9736), .Y(n10687) );
CLKMX2X2TS U2543 ( .A(P_Sgf[60]), .B(n10762), .S0(n10782), .Y(n481) );
CLKMX2X2TS U2544 ( .A(P_Sgf[59]), .B(n10772), .S0(n10782), .Y(n480) );
NAND2X2TS U2545 ( .A(n9345), .B(n9736), .Y(n10688) );
CLKMX2X2TS U2546 ( .A(P_Sgf[57]), .B(n10793), .S0(n10897), .Y(n478) );
CLKMX2X2TS U2547 ( .A(P_Sgf[58]), .B(n10783), .S0(n10782), .Y(n479) );
CLKMX2X2TS U2548 ( .A(P_Sgf[62]), .B(n10742), .S0(n10782), .Y(n483) );
CLKMX2X2TS U2549 ( .A(P_Sgf[56]), .B(n10803), .S0(n10897), .Y(n477) );
CLKMX2X2TS U2550 ( .A(P_Sgf[55]), .B(n10810), .S0(n10897), .Y(n476) );
CLKMX2X2TS U2551 ( .A(P_Sgf[61]), .B(n10752), .S0(n10782), .Y(n482) );
CLKMX2X2TS U2552 ( .A(P_Sgf[63]), .B(n10732), .S0(n10782), .Y(n484) );
CLKMX2X2TS U2553 ( .A(P_Sgf[53]), .B(n10819), .S0(n10897), .Y(n474) );
XOR2X2TS U2554 ( .A(n8860), .B(n8859), .Y(n9143) );
CLKMX2X2TS U2555 ( .A(P_Sgf[54]), .B(n10816), .S0(n10897), .Y(n475) );
NAND2X2TS U2556 ( .A(n8850), .B(n8849), .Y(n8851) );
NOR2X4TS U2557 ( .A(n5625), .B(n5624), .Y(n8841) );
AOI21X2TS U2558 ( .A0(n1179), .A1(n10724), .B0(n9341), .Y(n10713) );
NOR2X1TS U2559 ( .A(n10858), .B(n10714), .Y(n10716) );
CLKMX2X2TS U2560 ( .A(P_Sgf[52]), .B(n10822), .S0(n10897), .Y(n473) );
OAI21X1TS U2561 ( .A0(n10861), .A1(n10726), .B0(n10725), .Y(n10727) );
OAI21X1TS U2562 ( .A0(n10811), .A1(n10858), .B0(n10861), .Y(n10815) );
NAND2X2TS U2563 ( .A(n1179), .B(n10723), .Y(n10714) );
NOR2X1TS U2564 ( .A(n10858), .B(n10726), .Y(n10728) );
NAND2X2TS U2565 ( .A(n5621), .B(n5620), .Y(n8857) );
CLKMX2X2TS U2566 ( .A(P_Sgf[51]), .B(n10578), .S0(n10611), .Y(n472) );
ADDFHX2TS U2567 ( .A(n8796), .B(n8795), .CI(n1229), .CO(n8790), .S(n9107) );
OAI21X2TS U2568 ( .A0(n10737), .A1(n10733), .B0(n10738), .Y(n10724) );
CLKMX2X2TS U2569 ( .A(P_Sgf[50]), .B(n10574), .S0(n10611), .Y(n471) );
OAI21X1TS U2570 ( .A0(n10861), .A1(n10734), .B0(n10733), .Y(n10735) );
CLKMX2X2TS U2571 ( .A(P_Sgf[49]), .B(n10570), .S0(n10611), .Y(n470) );
NOR2X2TS U2572 ( .A(n5613), .B(n5612), .Y(n8869) );
AOI21X2TS U2573 ( .A0(n1180), .A1(n10744), .B0(n9338), .Y(n10733) );
OAI21X1TS U2574 ( .A0(n10861), .A1(n10746), .B0(n10745), .Y(n10747) );
NAND2X2TS U2575 ( .A(n5492), .B(n5491), .Y(n5494) );
XNOR2X2TS U2576 ( .A(n8890), .B(n1112), .Y(n9158) );
ADDFHX2TS U2577 ( .A(n10573), .B(n10572), .CI(n10571), .CO(n10576), .S(
n10574) );
NOR2X1TS U2578 ( .A(n10858), .B(n10734), .Y(n10736) );
NOR2X2TS U2579 ( .A(n10737), .B(n10734), .Y(n10723) );
CLKMX2X2TS U2580 ( .A(P_Sgf[48]), .B(n10566), .S0(n10611), .Y(n469) );
NAND2X2TS U2581 ( .A(n5610), .B(n5609), .Y(n8876) );
NOR2X1TS U2582 ( .A(n10858), .B(n10746), .Y(n10748) );
NAND2X2TS U2583 ( .A(n1180), .B(n10743), .Y(n10734) );
OR2X2TS U2584 ( .A(n8801), .B(n9489), .Y(n942) );
OAI21X1TS U2585 ( .A0(n10861), .A1(n10754), .B0(n10753), .Y(n10755) );
OAI21X2TS U2586 ( .A0(n10757), .A1(n10753), .B0(n10758), .Y(n10744) );
AFHCINX2TS U2587 ( .CIN(n10563), .B(n10564), .A(n10565), .S(n10566), .CO(
n10567) );
CLKMX2X2TS U2588 ( .A(P_Sgf[47]), .B(n10594), .S0(n10611), .Y(n468) );
OR2X2TS U2589 ( .A(n1129), .B(n5468), .Y(n808) );
NAND2X2TS U2590 ( .A(n5444), .B(n5443), .Y(n5614) );
AOI21X2TS U2591 ( .A0(n1181), .A1(n10764), .B0(n9333), .Y(n10753) );
NOR2X2TS U2592 ( .A(n10757), .B(n10754), .Y(n10743) );
INVX2TS U2593 ( .A(n5495), .Y(n5497) );
NOR2X1TS U2594 ( .A(n10858), .B(n10754), .Y(n10756) );
CLKMX2X2TS U2595 ( .A(P_Sgf[46]), .B(n10590), .S0(n10611), .Y(n467) );
OAI21X1TS U2596 ( .A0(n10861), .A1(n10766), .B0(n10765), .Y(n10767) );
XOR2X2TS U2597 ( .A(n8903), .B(n8902), .Y(n9164) );
NOR2X1TS U2598 ( .A(n10858), .B(n10766), .Y(n10768) );
NAND2X2TS U2599 ( .A(n1181), .B(n10763), .Y(n10754) );
OR2X2TS U2600 ( .A(n5412), .B(n5411), .Y(n963) );
XNOR2X2TS U2601 ( .A(n5405), .B(n5404), .Y(n5412) );
OAI21X1TS U2602 ( .A0(n10861), .A1(n10774), .B0(n10773), .Y(n10775) );
INVX1TS U2603 ( .A(n10861), .Y(n9358) );
OAI21X1TS U2604 ( .A0(n5451), .A1(n5450), .B0(n5449), .Y(n5452) );
INVX2TS U2605 ( .A(n10575), .Y(n9312) );
NAND2X2TS U2606 ( .A(n8901), .B(n8900), .Y(n8903) );
NOR2X1TS U2607 ( .A(n5451), .B(n5448), .Y(n5454) );
OAI21X1TS U2608 ( .A0(n10861), .A1(n10804), .B0(n10812), .Y(n10805) );
NOR2X1TS U2609 ( .A(n10858), .B(n10804), .Y(n10806) );
NOR2X1TS U2610 ( .A(n10858), .B(n10795), .Y(n10797) );
OR2X2TS U2611 ( .A(n9332), .B(n9331), .Y(n1181) );
NOR2X1TS U2612 ( .A(n10858), .B(n10787), .Y(n10789) );
OAI21X1TS U2613 ( .A0(n10861), .A1(n10795), .B0(n10794), .Y(n10796) );
OAI21X1TS U2614 ( .A0(n10861), .A1(n10787), .B0(n10786), .Y(n10788) );
NOR2X2TS U2615 ( .A(n10777), .B(n10774), .Y(n10763) );
NAND2X6TS U2616 ( .A(n9317), .B(n9316), .Y(n10861) );
OAI21X2TS U2617 ( .A0(n10777), .A1(n10773), .B0(n10778), .Y(n10764) );
OR2X2TS U2618 ( .A(n9314), .B(n9313), .Y(n1172) );
OR2X2TS U2619 ( .A(n9311), .B(n9310), .Y(n1171) );
AFHCINX2TS U2620 ( .CIN(n10579), .B(n10580), .A(n10581), .S(n10582), .CO(
n10583) );
INVX3TS U2621 ( .A(n5203), .Y(n5400) );
XNOR2X2TS U2622 ( .A(n8507), .B(n6795), .Y(n10584) );
INVX1TS U2623 ( .A(n9466), .Y(n9467) );
NOR2X1TS U2624 ( .A(n5401), .B(n5399), .Y(n5121) );
AOI21X2TS U2625 ( .A0(n5222), .A1(n940), .B0(n5216), .Y(n5219) );
OAI21X1TS U2626 ( .A0(n5401), .A1(n5398), .B0(n5402), .Y(n5120) );
OAI21X2TS U2627 ( .A0(n8912), .A1(n8915), .B0(n8913), .Y(n8907) );
INVX4TS U2628 ( .A(n5215), .Y(n5222) );
OR2X2TS U2629 ( .A(n5594), .B(n5593), .Y(n1080) );
OR2X2TS U2630 ( .A(n8769), .B(n8774), .Y(n1196) );
XNOR2X2TS U2631 ( .A(n8521), .B(n8520), .Y(n10604) );
CLKINVX2TS U2632 ( .A(n8761), .Y(n8506) );
OR2X2TS U2633 ( .A(n9327), .B(n9326), .Y(n1182) );
XOR2X2TS U2634 ( .A(n8529), .B(n8528), .Y(n10600) );
NAND2X1TS U2635 ( .A(n9327), .B(n9326), .Y(n10790) );
INVX1TS U2636 ( .A(n9461), .Y(n9462) );
NAND2X1TS U2637 ( .A(n9325), .B(n9324), .Y(n10799) );
NAND2X2TS U2638 ( .A(n1175), .B(n10813), .Y(n10795) );
XOR2X2TS U2639 ( .A(n5248), .B(n5247), .Y(n5516) );
CLKXOR2X2TS U2640 ( .A(n7011), .B(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[29]), .Y(n7019) );
INVX1TS U2641 ( .A(n9445), .Y(n9446) );
AOI2BB1X1TS U2642 ( .A0N(n11141), .A1N(FSM_add_overflow_flag), .B0(n9495),
.Y(n9496) );
NAND2X1TS U2643 ( .A(n9321), .B(n9320), .Y(n10807) );
NAND2X2TS U2644 ( .A(n5085), .B(n5084), .Y(n5230) );
OAI21X2TS U2645 ( .A0(n8517), .A1(n8526), .B0(n8518), .Y(n7004) );
XNOR2X2TS U2646 ( .A(n5266), .B(n5265), .Y(n5522) );
INVX2TS U2647 ( .A(n9447), .Y(n8866) );
INVX1TS U2648 ( .A(n9440), .Y(n9441) );
CLKXOR2X2TS U2649 ( .A(n8524), .B(n844), .Y(n1224) );
NOR2X1TS U2650 ( .A(DP_OP_338J35_122_4684_n4), .B(n1234), .Y(n1236) );
NAND2X2TS U2651 ( .A(n5083), .B(n829), .Y(n5245) );
AFHCONX2TS U2652 ( .A(n5529), .B(n5528), .CI(n5527), .CON(n5524), .S(n8933)
);
XOR2X2TS U2653 ( .A(n5393), .B(n5392), .Y(n5527) );
OAI21X1TS U2654 ( .A0(n8717), .A1(n8716), .B0(n8715), .Y(n8719) );
AOI21X2TS U2655 ( .A0(n1136), .A1(n5255), .B0(n5061), .Y(n5062) );
OR2X2TS U2656 ( .A(n6992), .B(n6991), .Y(n1187) );
NOR2X1TS U2657 ( .A(DP_OP_338J35_122_4684_n8), .B(DP_OP_338J35_122_4684_n5),
.Y(n1238) );
NOR2X1TS U2658 ( .A(DP_OP_338J35_122_4684_n8), .B(n1235), .Y(n1237) );
OR2X2TS U2659 ( .A(n9387), .B(n993), .Y(n994) );
AND2X2TS U2660 ( .A(DP_OP_338J35_122_4684_n8), .B(DP_OP_338J35_122_4684_n4),
.Y(n1130) );
XNOR2X2TS U2661 ( .A(n7015), .B(n6997), .Y(n6999) );
XOR2X2TS U2662 ( .A(n6900), .B(n6899), .Y(n6992) );
INVX2TS U2663 ( .A(n5264), .Y(n5255) );
NOR2X1TS U2664 ( .A(DP_OP_338J35_122_4684_n32), .B(DP_OP_338J35_122_4684_n5),
.Y(DP_OP_338J35_122_4684_n3) );
NOR2X1TS U2665 ( .A(DP_OP_338J35_122_4684_n32), .B(DP_OP_338J35_122_4684_n4),
.Y(DP_OP_338J35_122_4684_n2) );
INVX2TS U2666 ( .A(n9458), .Y(n8891) );
NAND2X2TS U2667 ( .A(n5060), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .Y(n5256) );
OAI21X2TS U2668 ( .A0(n8687), .A1(n8683), .B0(n8684), .Y(n8689) );
NAND2X2TS U2669 ( .A(n5038), .B(n5037), .Y(n5270) );
XOR2X2TS U2670 ( .A(n5044), .B(n5043), .Y(n5059) );
INVX1TS U2671 ( .A(n8791), .Y(n8792) );
XOR2X1TS U2672 ( .A(n6908), .B(n6907), .Y(n8542) );
XOR2X2TS U2673 ( .A(n5057), .B(n5056), .Y(n5060) );
XNOR2X2TS U2674 ( .A(n5025), .B(n5024), .Y(n5283) );
NOR2X2TS U2675 ( .A(n1199), .B(n6829), .Y(n6896) );
NAND2X2TS U2676 ( .A(n1199), .B(n6829), .Y(n6897) );
INVX1TS U2677 ( .A(n6890), .Y(n6885) );
NAND2X1TS U2678 ( .A(n980), .B(n6901), .Y(n6903) );
NOR2X2TS U2679 ( .A(n6837), .B(n6836), .Y(n6888) );
ADDFHX2TS U2680 ( .A(n10292), .B(n10291), .CI(n10290), .CO(
DP_OP_338J35_122_4684_n78), .S(DP_OP_338J35_122_4684_n79) );
XNOR2X1TS U2681 ( .A(n8678), .B(n8677), .Y(n9452) );
OAI21X2TS U2682 ( .A0(n5053), .A1(n5049), .B0(n5054), .Y(n4875) );
ADDFHX2TS U2683 ( .A(n5047), .B(n5046), .CI(n5045), .CO(
DP_OP_338J35_122_4684_n20), .S(n5058) );
ADDFHX2TS U2684 ( .A(n6831), .B(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[25]), .CI(n6830),
.CO(n6837), .S(n6829) );
NOR2X2TS U2685 ( .A(n5053), .B(n5048), .Y(n4876) );
OR2X2TS U2686 ( .A(n1050), .B(n6827), .Y(n980) );
INVX1TS U2687 ( .A(n8813), .Y(n8814) );
INVX4TS U2688 ( .A(add_x_87_n1), .Y(n1256) );
OR2X2TS U2689 ( .A(n1192), .B(n6807), .Y(n944) );
NAND2X2TS U2690 ( .A(n824), .B(n5041), .Y(n5048) );
ADDFHX2TS U2691 ( .A(n10301), .B(n10300), .CI(n10299), .CO(n10291), .S(
n10302) );
NAND2X1TS U2692 ( .A(n8696), .B(n8695), .Y(n8697) );
XNOR2X1TS U2693 ( .A(n5141), .B(n5140), .Y(n8783) );
ADDFHX2TS U2694 ( .A(n6609), .B(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[23]), .CI(n6608),
.CO(n6825), .S(n6809) );
OR2X2TS U2695 ( .A(n10128), .B(n10127), .Y(n10131) );
XNOR2X1TS U2696 ( .A(n5094), .B(n5093), .Y(n8799) );
NAND2X1TS U2697 ( .A(n8712), .B(n9747), .Y(n8523) );
INVX1TS U2698 ( .A(n8712), .Y(n8709) );
NAND2X1TS U2699 ( .A(n5033), .B(n5032), .Y(n5281) );
OR2X2TS U2700 ( .A(n5033), .B(n5032), .Y(n1055) );
XNOR2X1TS U2701 ( .A(n5197), .B(n990), .Y(n9389) );
INVX1TS U2702 ( .A(n8702), .Y(n8699) );
XOR2X1TS U2703 ( .A(n6990), .B(n6989), .Y(n8556) );
NAND2X1TS U2704 ( .A(n836), .B(n6913), .Y(n6915) );
OAI21X1TS U2705 ( .A0(n5196), .A1(n5002), .B0(n5001), .Y(n5004) );
OR2X2TS U2706 ( .A(n10133), .B(n10132), .Y(n10128) );
XOR2X2TS U2707 ( .A(n4833), .B(n5067), .Y(n8827) );
INVX1TS U2708 ( .A(n8703), .Y(n8705) );
ADDFHX2TS U2709 ( .A(n4598), .B(n4597), .CI(n4596), .CO(n5024), .S(n5384) );
XNOR2X2TS U2710 ( .A(n4843), .B(n4842), .Y(n1056) );
NOR2X2TS U2711 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[24]), .B(
n9751), .Y(n8692) );
NAND2X1TS U2712 ( .A(n6988), .B(n6987), .Y(n6990) );
OA21X2TS U2713 ( .A0(n6986), .A1(n6989), .B0(n6987), .Y(n1058) );
ADDFHX2TS U2714 ( .A(n2147), .B(n2146), .CI(n2145), .CO(n2140), .S(n5031) );
NAND2X1TS U2715 ( .A(Sgf_normalized_result[40]), .B(n11136), .Y(n11138) );
NAND2X2TS U2716 ( .A(n1239), .B(n1240), .Y(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[17])
);
ADDFHX1TS U2717 ( .A(n10223), .B(n10222), .CI(n10221), .CO(n10249), .S(
n10241) );
ADDFHX2TS U2718 ( .A(n2129), .B(n2128), .CI(n2127), .CO(n2132), .S(n2145) );
NOR2X1TS U2719 ( .A(n5190), .B(n967), .Y(n5191) );
OAI21X1TS U2720 ( .A0(n5480), .A1(n5168), .B0(n5170), .Y(n5158) );
XNOR2X1TS U2721 ( .A(n6924), .B(n6923), .Y(n8563) );
INVX1TS U2722 ( .A(n5105), .Y(n5107) );
ADDFHX1TS U2723 ( .A(n5289), .B(n5288), .CI(n5287), .CO(n4456), .S(n5537) );
NOR2X1TS U2724 ( .A(n5190), .B(n5003), .Y(n4992) );
XNOR2X1TS U2725 ( .A(n3889), .B(n1173), .Y(n8946) );
OAI21X1TS U2726 ( .A0(n3911), .A1(n5122), .B0(n5124), .Y(n3909) );
XNOR2X1TS U2727 ( .A(n5440), .B(n1174), .Y(n8952) );
XNOR2X1TS U2728 ( .A(n5243), .B(n5242), .Y(n8994) );
XNOR2X1TS U2729 ( .A(n5209), .B(n1184), .Y(n8970) );
AOI21X1TS U2730 ( .A0(n926), .A1(n9221), .B0(n9100), .Y(n9215) );
XNOR2X1TS U2731 ( .A(n5548), .B(n5547), .Y(n8975) );
XNOR2X1TS U2732 ( .A(n5410), .B(n964), .Y(n8964) );
OR2X2TS U2733 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[22]), .B(
n9753), .Y(n1216) );
NOR2X2TS U2734 ( .A(n9102), .B(n9101), .Y(n9211) );
NAND2X1TS U2735 ( .A(Sgf_normalized_result[38]), .B(n11132), .Y(n11134) );
OAI21X1TS U2736 ( .A0(n5424), .A1(n5438), .B0(n5423), .Y(n5427) );
OAI21X1TS U2737 ( .A0(n5438), .A1(n5211), .B0(n5210), .Y(n5214) );
ADDFHX2TS U2738 ( .A(n2017), .B(n2016), .CI(n2015), .CO(n10167), .S(n2025)
);
NAND2X1TS U2739 ( .A(n926), .B(n1084), .Y(n9214) );
AOI21X2TS U2740 ( .A0(n5128), .A1(n5127), .B0(n5126), .Y(n5480) );
OR2X2TS U2741 ( .A(n4818), .B(n4817), .Y(n1102) );
NOR2X1TS U2742 ( .A(DP_OP_345J35_129_3436_n8), .B(n1242), .Y(n1244) );
INVX2TS U2743 ( .A(DP_OP_345J35_129_3436_n8), .Y(n1241) );
AND2X2TS U2744 ( .A(DP_OP_345J35_129_3436_n8), .B(DP_OP_345J35_129_3436_n4),
.Y(n1154) );
XNOR2X2TS U2745 ( .A(n4827), .B(n4826), .Y(n4832) );
OAI21X2TS U2746 ( .A0(n4853), .A1(n4856), .B0(n4854), .Y(n4848) );
ADDFHX2TS U2747 ( .A(n2114), .B(n2113), .CI(n2112), .CO(n2124), .S(n2151) );
OR2X2TS U2748 ( .A(n8462), .B(n9754), .Y(n1215) );
NAND2X1TS U2749 ( .A(Sgf_normalized_result[36]), .B(n11128), .Y(n11130) );
XNOR2X2TS U2750 ( .A(n5028), .B(n5027), .Y(n5622) );
OAI21X1TS U2751 ( .A0(n4983), .A1(n4957), .B0(n4956), .Y(n4972) );
OAI21X1TS U2752 ( .A0(n4983), .A1(n4930), .B0(n4929), .Y(n4953) );
NAND2X1TS U2753 ( .A(n8460), .B(n8459), .Y(n8676) );
OR2X2TS U2754 ( .A(n8460), .B(n8459), .Y(n1214) );
OAI21XLTS U2755 ( .A0(n5474), .A1(n5473), .B0(n5472), .Y(n5475) );
OAI21X1TS U2756 ( .A0(n4868), .A1(n4440), .B0(n4439), .Y(n4450) );
XNOR2X1TS U2757 ( .A(n5269), .B(n5268), .Y(n9009) );
ADDHX2TS U2758 ( .A(n4417), .B(n4416), .CO(n4423), .S(n5299) );
OAI21X1TS U2759 ( .A0(n4868), .A1(n4435), .B0(n4437), .Y(n4406) );
ADDFHX2TS U2760 ( .A(n1813), .B(n1812), .CI(n1811), .CO(n1998), .S(n1805) );
OR2X2TS U2761 ( .A(n4813), .B(n4812), .Y(n1133) );
NAND2X1TS U2762 ( .A(n5251), .B(n5250), .Y(n5252) );
XOR2X1TS U2763 ( .A(n5277), .B(n5276), .Y(n9013) );
NAND2X1TS U2764 ( .A(Sgf_normalized_result[34]), .B(n11124), .Y(n11126) );
OAI21X2TS U2765 ( .A0(n3823), .A1(n5273), .B0(n3822), .Y(n5268) );
ADDFHX1TS U2766 ( .A(n6674), .B(n6673), .CI(n6672), .CO(n6667), .S(n6787) );
NAND2X1TS U2767 ( .A(n4387), .B(n4386), .Y(n4388) );
NOR2X1TS U2768 ( .A(n5433), .B(n1184), .Y(n5406) );
NOR2X1TS U2769 ( .A(n5239), .B(n5249), .Y(n3869) );
NAND2X1TS U2770 ( .A(n4318), .B(n4437), .Y(n4319) );
AOI21X1TS U2771 ( .A0(n949), .A1(n5274), .B0(n3821), .Y(n3822) );
NOR2X1TS U2772 ( .A(DP_OP_345J35_129_3436_n32), .B(DP_OP_345J35_129_3436_n5),
.Y(DP_OP_345J35_129_3436_n3) );
NOR2X1TS U2773 ( .A(n5433), .B(n1183), .Y(n3876) );
NOR2X1TS U2774 ( .A(DP_OP_345J35_129_3436_n32), .B(DP_OP_345J35_129_3436_n4),
.Y(DP_OP_345J35_129_3436_n2) );
ADDFHX2TS U2775 ( .A(n1760), .B(n1759), .CI(n1758), .CO(n1743), .S(n3899) );
NOR2X1TS U2776 ( .A(n5433), .B(n5432), .Y(n5434) );
XOR2X1TS U2777 ( .A(n4570), .B(n1132), .Y(n4579) );
NOR2X1TS U2778 ( .A(n5433), .B(n5420), .Y(n5421) );
ADDFHX2TS U2779 ( .A(n1939), .B(n1938), .CI(n1937), .CO(n1936), .S(n1967) );
OAI21XLTS U2780 ( .A0(n5554), .A1(n5562), .B0(n5559), .Y(n5555) );
NOR2X1TS U2781 ( .A(n10191), .B(n2174), .Y(n1995) );
NOR2X1TS U2782 ( .A(n10189), .B(n2174), .Y(n2046) );
NAND2X1TS U2783 ( .A(n949), .B(n5275), .Y(n5276) );
NOR2X1TS U2784 ( .A(n10191), .B(n2033), .Y(n10197) );
NOR2X2TS U2785 ( .A(n3875), .B(n3874), .Y(n5430) );
NAND2X1TS U2786 ( .A(Sgf_normalized_result[32]), .B(n11120), .Y(n11122) );
NOR2X1TS U2787 ( .A(n10191), .B(n10184), .Y(n10220) );
NAND2X2TS U2788 ( .A(n3875), .B(n3874), .Y(n5433) );
NAND2X1TS U2789 ( .A(n1134), .B(n4807), .Y(n4809) );
NOR2X1TS U2790 ( .A(n10191), .B(n10185), .Y(n10144) );
NAND2X1TS U2791 ( .A(n3867), .B(n3866), .Y(n5240) );
ADDFHX2TS U2792 ( .A(n1740), .B(n1739), .CI(n1738), .CO(n1817), .S(n1728) );
NOR2X2TS U2793 ( .A(n3867), .B(n3866), .Y(n5239) );
NAND2X2TS U2794 ( .A(n4749), .B(n4748), .Y(n4798) );
ADDFHX2TS U2795 ( .A(n1726), .B(n1725), .CI(n1724), .CO(n1727), .S(n1758) );
NOR2X2TS U2796 ( .A(n3865), .B(n3864), .Y(n5249) );
NOR2X1TS U2797 ( .A(n10191), .B(n10166), .Y(n10138) );
OR2X2TS U2798 ( .A(n3833), .B(n3832), .Y(n1063) );
ADDFX1TS U2799 ( .A(n1955), .B(n1954), .CI(n1953), .CO(n1969), .S(n1971) );
OR2X2TS U2800 ( .A(n4746), .B(n4745), .Y(n1134) );
ADDFHX2TS U2801 ( .A(n4727), .B(n4726), .CI(n4725), .CO(n4750), .S(n4749) );
AOI21X2TS U2802 ( .A0(n5387), .A1(n920), .B0(n3817), .Y(n5273) );
NOR2X1TS U2803 ( .A(n10186), .B(n2174), .Y(n2066) );
INVX4TS U2804 ( .A(n1834), .Y(n10186) );
XNOR2X1TS U2805 ( .A(n3695), .B(n3694), .Y(n3820) );
NOR2X1TS U2806 ( .A(n10203), .B(n2174), .Y(n2070) );
OAI21X1TS U2807 ( .A0(n9633), .A1(n9575), .B0(n7503), .Y(n7502) );
NAND2X1TS U2808 ( .A(Sgf_normalized_result[30]), .B(n11116), .Y(n11118) );
NOR2X1TS U2809 ( .A(n10239), .B(n10203), .Y(n10235) );
XNOR2X1TS U2810 ( .A(n8410), .B(n8409), .Y(n9727) );
ADDFHX2TS U2811 ( .A(n1667), .B(n1666), .CI(n1665), .CO(n1668), .S(n1695) );
XNOR2X1TS U2812 ( .A(n8404), .B(n8403), .Y(n9726) );
OAI21X1TS U2813 ( .A0(n6820), .A1(n6604), .B0(n6603), .Y(n6607) );
XNOR2X1TS U2814 ( .A(n8374), .B(n1211), .Y(n9693) );
XNOR2X1TS U2815 ( .A(n8425), .B(n8424), .Y(n9729) );
XNOR2X1TS U2816 ( .A(n8394), .B(n8393), .Y(n9695) );
OAI21X1TS U2817 ( .A0(n6642), .A1(n6639), .B0(n6640), .Y(n6635) );
ADDFHX2TS U2818 ( .A(n9018), .B(n9017), .CI(n9016), .CO(n9011), .S(n9096) );
OAI21X2TS U2819 ( .A0(n3679), .A1(n3538), .B0(n3537), .Y(n3619) );
NOR2X1TS U2820 ( .A(n5148), .B(n1636), .Y(n5180) );
NOR2X1TS U2821 ( .A(n5177), .B(n1636), .Y(n5461) );
XNOR2X1TS U2822 ( .A(n7405), .B(n7404), .Y(n9743) );
XNOR2X1TS U2823 ( .A(n8750), .B(n8746), .Y(n9702) );
ADDFHX2TS U2824 ( .A(n1952), .B(n1951), .CI(n1950), .CO(n1954), .S(n2080) );
CMPR22X2TS U2825 ( .A(n1946), .B(n1945), .CO(n1944), .S(n1952) );
NOR2X1TS U2826 ( .A(n10239), .B(n10246), .Y(n10265) );
NOR2X1TS U2827 ( .A(n3837), .B(n3854), .Y(n3840) );
NOR2X2TS U2828 ( .A(n5147), .B(n1713), .Y(n1667) );
INVX4TS U2829 ( .A(n1787), .Y(n10244) );
ADDFHX2TS U2830 ( .A(n8613), .B(n9020), .CI(n9019), .CO(n9017), .S(n9087) );
NAND2X1TS U2831 ( .A(Sgf_normalized_result[28]), .B(n11112), .Y(n11114) );
OR2X1TS U2832 ( .A(n5187), .B(n992), .Y(n967) );
ADDFX1TS U2833 ( .A(n2101), .B(n2100), .CI(n2099), .CO(n1993), .S(n2121) );
AND2X2TS U2834 ( .A(n9746), .B(n8713), .Y(n1016) );
AOI21X2TS U2835 ( .A0(n3340), .A1(n3690), .B0(n3339), .Y(n3679) );
OAI21X2TS U2836 ( .A0(n4431), .A1(n4427), .B0(n4428), .Y(n4433) );
XOR2X1TS U2837 ( .A(n8430), .B(n8429), .Y(n9730) );
XOR2X1TS U2838 ( .A(n7416), .B(n7415), .Y(n9745) );
ADDFHX1TS U2839 ( .A(n2728), .B(n2727), .CI(n2726), .CO(n10057), .S(n2762)
);
XNOR2X1TS U2840 ( .A(n2946), .B(n2945), .Y(n6576) );
OAI21X2TS U2841 ( .A0(n5348), .A1(n5575), .B0(n5347), .Y(n5572) );
NAND2X1TS U2842 ( .A(n3825), .B(n3824), .Y(n3826) );
OAI21X1TS U2843 ( .A0(n6814), .A1(n6340), .B0(n6339), .Y(n6341) );
INVX1TS U2844 ( .A(n9706), .Y(n7513) );
INVX1TS U2845 ( .A(n7020), .Y(n6792) );
ADDFX1TS U2846 ( .A(n1918), .B(n1917), .CI(n1916), .CO(n2051), .S(n2099) );
NAND2X1TS U2847 ( .A(n3536), .B(n3852), .Y(n3538) );
AOI21X1TS U2848 ( .A0(n3851), .A1(n3536), .B0(n3535), .Y(n3537) );
XOR2X1TS U2849 ( .A(n2941), .B(n2938), .Y(n6572) );
NOR2X2TS U2850 ( .A(n2000), .B(n1713), .Y(n1663) );
ADDHX2TS U2851 ( .A(n1694), .B(n1693), .CO(n1664), .S(n1719) );
OA21X4TS U2852 ( .A0(n1635), .A1(n1634), .B0(n1633), .Y(n1636) );
ADDFX1TS U2853 ( .A(n2057), .B(n2056), .CI(n2055), .CO(n4271), .S(n2052) );
AOI21X2TS U2854 ( .A0(n3781), .A1(n927), .B0(n3326), .Y(n3798) );
AOI21X1TS U2855 ( .A0(n6657), .A1(n1190), .B0(n6314), .Y(n6651) );
NAND2X1TS U2856 ( .A(n8379), .B(n8397), .Y(n8381) );
NOR2X1TS U2857 ( .A(n7351), .B(n8722), .Y(n7360) );
NOR2X1TS U2858 ( .A(n2105), .B(n2174), .Y(n2079) );
INVX1TS U2859 ( .A(n9640), .Y(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[13]) );
OR2X2TS U2860 ( .A(n9892), .B(n9891), .Y(n9895) );
NAND2X1TS U2861 ( .A(Sgf_normalized_result[26]), .B(n11108), .Y(n11110) );
NOR2X4TS U2862 ( .A(n1713), .B(n1810), .Y(n1694) );
XOR2X1TS U2863 ( .A(n8435), .B(n8434), .Y(n9731) );
ADDFX1TS U2864 ( .A(n1921), .B(n1920), .CI(n1919), .CO(n2054), .S(n1916) );
OAI21X2TS U2865 ( .A0(n3682), .A1(n3824), .B0(n3683), .Y(n3851) );
OAI21X1TS U2866 ( .A0(n4577), .A1(n4508), .B0(n4507), .Y(n4515) );
ADDFHX1TS U2867 ( .A(n6687), .B(n9027), .CI(n9026), .CO(n9024), .S(n9081) );
ADDFHX2TS U2868 ( .A(n4540), .B(n4539), .CI(n4538), .CO(n4675), .S(n4535) );
NOR2X2TS U2869 ( .A(n3682), .B(n3680), .Y(n3852) );
OAI22X1TS U2870 ( .A0(n10196), .A1(n2170), .B0(n10195), .B1(n2105), .Y(n2129) );
OAI21X1TS U2871 ( .A0(n4248), .A1(n4244), .B0(n4245), .Y(n4243) );
OAI21X1TS U2872 ( .A0(n4577), .A1(n4503), .B0(n4505), .Y(n4108) );
OAI21X1TS U2873 ( .A0(n8401), .A1(n8362), .B0(n8361), .Y(n8363) );
OAI21X1TS U2874 ( .A0(n8726), .A1(n8725), .B0(n8724), .Y(n8727) );
XNOR2X1TS U2875 ( .A(n8441), .B(n8440), .Y(n9732) );
NOR2X1TS U2876 ( .A(n10187), .B(n2170), .Y(n2164) );
NOR2X1TS U2877 ( .A(n5149), .B(n1948), .Y(n1753) );
NOR2X1TS U2878 ( .A(n10165), .B(n2170), .Y(n2158) );
NOR2X1TS U2879 ( .A(n10190), .B(n2170), .Y(n2181) );
OR2X2TS U2880 ( .A(n4937), .B(n1248), .Y(n4963) );
XOR2X1TS U2881 ( .A(n3707), .B(n3706), .Y(n3778) );
NOR2X1TS U2882 ( .A(n2174), .B(n2170), .Y(n4420) );
NOR2X1TS U2883 ( .A(n2170), .B(n2034), .Y(n2171) );
XOR2X1TS U2884 ( .A(n8446), .B(n8445), .Y(n9733) );
XOR2X1TS U2885 ( .A(n4253), .B(n4252), .Y(n4321) );
OR2X2TS U2886 ( .A(n9897), .B(n9896), .Y(n9892) );
NOR2X2TS U2887 ( .A(n3532), .B(n3531), .Y(n3854) );
NOR2X2TS U2888 ( .A(n3534), .B(n3533), .Y(n3841) );
INVX1TS U2889 ( .A(n8729), .Y(n7358) );
NAND2X1TS U2890 ( .A(n3534), .B(n3533), .Y(n3842) );
AOI21X1TS U2891 ( .A0(n8436), .A1(n8334), .B0(n8333), .Y(n8435) );
NOR2XLTS U2892 ( .A(DP_OP_338J35_122_4684_n1290), .B(n1249), .Y(n1251) );
OAI2BB1X1TS U2893 ( .A0N(n4214), .A1N(n4217), .B0(n4173), .Y(n4210) );
OAI21X1TS U2894 ( .A0(n7407), .A1(n7413), .B0(n7408), .Y(n7279) );
OAI21X1TS U2895 ( .A0(n2942), .A1(n2939), .B0(n2943), .Y(n2860) );
OAI21XLTS U2896 ( .A0(n6947), .A1(n6955), .B0(n6952), .Y(n6948) );
NAND2X1TS U2897 ( .A(Sgf_normalized_result[24]), .B(n11104), .Y(n11106) );
XOR2X2TS U2898 ( .A(n1611), .B(n1610), .Y(n1612) );
OAI21X1TS U2899 ( .A0(n8480), .A1(n8483), .B0(n8481), .Y(n8487) );
INVX1TS U2900 ( .A(n9748), .Y(DP_OP_344J35_128_4078_n154) );
OR2X1TS U2901 ( .A(n6313), .B(n6312), .Y(n1190) );
NOR2XLTS U2902 ( .A(DP_OP_338J35_122_4684_n1286), .B(n1250), .Y(n1252) );
NOR2XLTS U2903 ( .A(DP_OP_338J35_122_4684_n1286), .B(
DP_OP_338J35_122_4684_n1291), .Y(n1253) );
OAI21X1TS U2904 ( .A0(n4217), .A1(n4214), .B0(n4215), .Y(n4173) );
OAI21X1TS U2905 ( .A0(n9654), .A1(n9601), .B0(n7474), .Y(n7473) );
OR2X2TS U2906 ( .A(n7242), .B(n7241), .Y(n1048) );
NOR2XLTS U2907 ( .A(DP_OP_338J35_122_4684_n1291), .B(n1248), .Y(
DP_OP_338J35_122_4684_n1289) );
NOR2XLTS U2908 ( .A(DP_OP_338J35_122_4684_n1290), .B(n1248), .Y(
DP_OP_338J35_122_4684_n1288) );
OR2X2TS U2909 ( .A(n9898), .B(n10071), .Y(n9901) );
XNOR2X1TS U2910 ( .A(n3748), .B(n3747), .Y(n3759) );
OAI21X1TS U2911 ( .A0(n6678), .A1(n6675), .B0(n6676), .Y(n6670) );
NOR2X1TS U2912 ( .A(n4592), .B(n2174), .Y(n1917) );
OAI21X1TS U2913 ( .A0(n7374), .A1(n7373), .B0(n7335), .Y(n7338) );
XOR2X1TS U2914 ( .A(n8127), .B(n8146), .Y(n8357) );
ADDFX1TS U2915 ( .A(n2713), .B(n2712), .CI(n2711), .CO(n2445), .S(n2738) );
XNOR2X1TS U2916 ( .A(n10118), .B(n6882), .Y(n9878) );
NOR2X1TS U2917 ( .A(n4444), .B(n4592), .Y(n4591) );
ADDFHX1TS U2918 ( .A(n3216), .B(n3215), .CI(n3214), .CO(n3525), .S(n3217) );
XOR2X1TS U2919 ( .A(n8451), .B(n8450), .Y(n9734) );
NOR2X1TS U2920 ( .A(n9666), .B(n9662), .Y(n9527) );
NOR2X1TS U2921 ( .A(n9664), .B(n9663), .Y(DP_OP_341J35_125_6458_n151) );
NOR2X1TS U2922 ( .A(n6148), .B(n6173), .Y(n6152) );
OAI21X2TS U2923 ( .A0(n1684), .A1(n1685), .B0(n1686), .Y(n1603) );
NOR2X1TS U2924 ( .A(n9662), .B(n9663), .Y(DP_OP_341J35_125_6458_n153) );
ADDHX2TS U2925 ( .A(n1901), .B(n1900), .CO(n1913), .S(n1903) );
NOR2X1TS U2926 ( .A(n4445), .B(n2082), .Y(n2062) );
NOR2X1TS U2927 ( .A(n10074), .B(n10085), .Y(n10077) );
INVX2TS U2928 ( .A(n1909), .Y(n4592) );
NOR2X1TS U2929 ( .A(n9666), .B(n9664), .Y(n9516) );
OAI21X1TS U2930 ( .A0(n3753), .A1(n3749), .B0(n3750), .Y(n3748) );
INVX2TS U2931 ( .A(n8452), .Y(n8634) );
NAND2X1TS U2932 ( .A(Sgf_normalized_result[22]), .B(n11100), .Y(n11102) );
CMPR32X2TS U2933 ( .A(n2840), .B(n2839), .C(n2838), .CO(n10031), .S(n2859)
);
AOI21X1TS U2934 ( .A0(n1046), .A1(n6683), .B0(n6287), .Y(n6678) );
XOR2X1TS U2935 ( .A(n3753), .B(n3752), .Y(n5302) );
ADDFHX2TS U2936 ( .A(n3459), .B(n3458), .CI(n3457), .CO(n3520), .S(n3516) );
OAI21X1TS U2937 ( .A0(n6303), .A1(n6302), .B0(n6301), .Y(n6308) );
NOR2X1TS U2938 ( .A(n4444), .B(n4445), .Y(n4446) );
OAI21X1TS U2939 ( .A0(n10111), .A1(n10107), .B0(n10108), .Y(n10106) );
NOR2X1TS U2940 ( .A(n9668), .B(n9681), .Y(DP_OP_341J35_125_6458_n174) );
OAI21X2TS U2941 ( .A0(n8622), .A1(n8273), .B0(n8272), .Y(n8452) );
NOR2X1TS U2942 ( .A(n4938), .B(n4605), .Y(n4962) );
OAI21XLTS U2943 ( .A0(n3648), .A1(n3660), .B0(n3663), .Y(n3649) );
NOR2X1TS U2944 ( .A(n4444), .B(n4396), .Y(n4403) );
ADDFHX2TS U2945 ( .A(n3149), .B(n3148), .CI(n3147), .CO(n3158), .S(n3221) );
OAI21X1TS U2946 ( .A0(n6688), .A1(n6284), .B0(n6689), .Y(n6683) );
OAI21X1TS U2947 ( .A0(n7373), .A1(n7258), .B0(n7261), .Y(n7248) );
XOR2X1TS U2948 ( .A(n4162), .B(n4157), .Y(n4170) );
NOR2X1TS U2949 ( .A(n4964), .B(n4605), .Y(n4985) );
NOR2X1TS U2950 ( .A(n9668), .B(n9650), .Y(n9525) );
OAI21X1TS U2951 ( .A0(n7306), .A1(n7373), .B0(n7305), .Y(n7315) );
ADDHX1TS U2952 ( .A(n4542), .B(n4541), .CO(n4608), .S(n4544) );
OAI21X1TS U2953 ( .A0(n7368), .A1(n7367), .B0(n7333), .Y(n7334) );
NOR2X1TS U2954 ( .A(n10239), .B(n4396), .Y(n4443) );
NOR2X1TS U2955 ( .A(n4273), .B(n4396), .Y(n2061) );
OAI21X1TS U2956 ( .A0(n7373), .A1(n7263), .B0(n7262), .Y(n7265) );
OAI21X1TS U2957 ( .A0(n7368), .A1(n7367), .B0(n7366), .Y(n7369) );
OAI21X1TS U2958 ( .A0(n7284), .A1(n7373), .B0(n7283), .Y(n7286) );
INVX2TS U2959 ( .A(n1899), .Y(n4445) );
NOR2X1TS U2960 ( .A(n2082), .B(n4396), .Y(n1923) );
NOR2X1TS U2961 ( .A(n9662), .B(n9667), .Y(n9532) );
NAND2X1TS U2962 ( .A(n3746), .B(n3745), .Y(n3747) );
ADDFHX1TS U2963 ( .A(n4027), .B(n4026), .CI(n4025), .CO(n4055), .S(n4082) );
NAND2X1TS U2964 ( .A(Sgf_normalized_result[20]), .B(n11096), .Y(n11098) );
NOR2X1TS U2965 ( .A(n8165), .B(n8190), .Y(n8168) );
NOR2X1TS U2966 ( .A(n849), .B(n9927), .Y(n9957) );
NOR2X1TS U2967 ( .A(n4444), .B(n4304), .Y(n4307) );
OAI21X1TS U2968 ( .A0(n10078), .A1(n10086), .B0(n10079), .Y(n6871) );
XOR2X1TS U2969 ( .A(n4163), .B(n4160), .Y(n4157) );
NAND2X1TS U2970 ( .A(n3288), .B(n3287), .Y(n3735) );
NOR2X1TS U2971 ( .A(n9929), .B(n849), .Y(n9900) );
INVX4TS U2972 ( .A(n1875), .Y(n10239) );
NOR2X1TS U2973 ( .A(n9945), .B(n2380), .Y(n2434) );
OAI21X1TS U2974 ( .A0(n3744), .A1(n3750), .B0(n3745), .Y(n3722) );
OR2X2TS U2975 ( .A(n904), .B(n1794), .Y(n915) );
NOR2X1TS U2976 ( .A(n849), .B(n9944), .Y(n9913) );
OR2X2TS U2977 ( .A(n7227), .B(n7226), .Y(n1218) );
OAI21X1TS U2978 ( .A0(n10102), .A1(n10108), .B0(n10103), .Y(n6851) );
NOR2X1TS U2979 ( .A(n10102), .B(n10107), .Y(n6852) );
OAI21X1TS U2980 ( .A0(n6304), .A1(n6301), .B0(n6305), .Y(n5973) );
NOR2X1TS U2981 ( .A(n849), .B(n2380), .Y(n2664) );
NOR2X1TS U2982 ( .A(n849), .B(n2672), .Y(n9954) );
NOR2X1TS U2983 ( .A(n4444), .B(n2048), .Y(n2049) );
NOR2X1TS U2984 ( .A(n4308), .B(n4304), .Y(n2057) );
NOR2X1TS U2985 ( .A(n6304), .B(n6302), .Y(n5974) );
NOR2X1TS U2986 ( .A(n9660), .B(n9588), .Y(n2996) );
AOI21X1TS U2987 ( .A0(n1065), .A1(n1007), .B0(n3286), .Y(n3737) );
OAI21XLTS U2988 ( .A0(n3611), .A1(n3847), .B0(n3612), .Y(n3603) );
NOR2X2TS U2989 ( .A(n8300), .B(n8299), .Y(n8630) );
NOR2X2TS U2990 ( .A(n3769), .B(n3770), .Y(n3800) );
INVX2TS U2991 ( .A(n1848), .Y(n10165) );
XNOR2X1TS U2992 ( .A(n4339), .B(n4338), .Y(n8928) );
INVX6TS U2993 ( .A(n1889), .Y(n4304) );
OAI21XLTS U2994 ( .A0(n3664), .A1(n3663), .B0(n3662), .Y(n3665) );
NOR2X1TS U2995 ( .A(n4397), .B(n2048), .Y(n2100) );
OAI21X2TS U2996 ( .A0(n7261), .A1(n7260), .B0(n7259), .Y(n7371) );
NAND2X2TS U2997 ( .A(n3052), .B(n1784), .Y(n1629) );
NAND2X1TS U2998 ( .A(n1205), .B(n1083), .Y(n8273) );
OA21X4TS U2999 ( .A0(n4604), .A1(n4603), .B0(n4602), .Y(n4605) );
OAI21X1TS U3000 ( .A0(n7367), .A1(n7302), .B0(n7331), .Y(n7303) );
NOR2X2TS U3001 ( .A(n3052), .B(n1784), .Y(n1628) );
NOR2XLTS U3002 ( .A(n3611), .B(n3846), .Y(n3604) );
OAI21X1TS U3003 ( .A0(n8320), .A1(n8317), .B0(n8321), .Y(n7987) );
NOR2X1TS U3004 ( .A(n9995), .B(n9991), .Y(n9999) );
INVX4TS U3005 ( .A(n3056), .Y(n3478) );
OR2X2TS U3006 ( .A(n8270), .B(n8269), .Y(n1205) );
OAI21X1TS U3007 ( .A0(n8191), .A1(n8169), .B0(n8170), .Y(n8111) );
NOR2X1TS U3008 ( .A(n8320), .B(n8318), .Y(n7988) );
OR2X1TS U3009 ( .A(n9883), .B(n9882), .Y(n1071) );
NOR2X1TS U3010 ( .A(n9662), .B(n9650), .Y(n9535) );
NOR2X2TS U3011 ( .A(n3725), .B(n3724), .Y(n3769) );
INVX3TS U3012 ( .A(n1891), .Y(n4266) );
INVX2TS U3013 ( .A(n1763), .Y(n10185) );
NAND2X1TS U3014 ( .A(Sgf_normalized_result[18]), .B(n11092), .Y(n11094) );
XNOR2X1TS U3015 ( .A(n8276), .B(n8275), .Y(n8301) );
INVX2TS U3016 ( .A(n1779), .Y(n10187) );
INVX2TS U3017 ( .A(n1964), .Y(n2173) );
NOR2X1TS U3018 ( .A(n4308), .B(n2098), .Y(n2092) );
INVX2TS U3019 ( .A(n1905), .Y(n4397) );
NOR2X1TS U3020 ( .A(n9995), .B(n9994), .Y(n10025) );
NOR2X1TS U3021 ( .A(n9994), .B(n2380), .Y(n2446) );
INVX4TS U3022 ( .A(n3096), .Y(n3446) );
NOR2XLTS U3023 ( .A(n3581), .B(n805), .Y(n3626) );
NOR2X1TS U3024 ( .A(n9682), .B(n9681), .Y(n9683) );
NOR2X2TS U3025 ( .A(n8236), .B(n8235), .Y(n8614) );
INVX4TS U3026 ( .A(n3066), .Y(n3560) );
XNOR2X1TS U3027 ( .A(n3055), .B(n3054), .Y(n3056) );
NOR2X2TS U3028 ( .A(n8108), .B(n8107), .Y(n8190) );
INVX2TS U3029 ( .A(n1601), .Y(n5148) );
INVX2TS U3030 ( .A(n1898), .Y(n4308) );
INVX2TS U3031 ( .A(n1804), .Y(n10188) );
OR2X2TS U3032 ( .A(n3047), .B(n1774), .Y(n1144) );
NOR2X1TS U3033 ( .A(n4273), .B(n2098), .Y(n2072) );
NOR2X2TS U3034 ( .A(n3727), .B(n3726), .Y(n3770) );
INVX2TS U3035 ( .A(n1802), .Y(n10190) );
AOI21X1TS U3036 ( .A0(n1138), .A1(n4343), .B0(n3710), .Y(n4354) );
NOR2X1TS U3037 ( .A(n3364), .B(n805), .Y(n3450) );
ADDFHX2TS U3038 ( .A(n3105), .B(n3104), .CI(n3103), .CO(n3166), .S(n3716) );
ADDFHX2TS U3039 ( .A(Op_MY[24]), .B(Op_MY[51]), .CI(n1472), .CO(n1462), .S(
n1769) );
OAI21X1TS U3040 ( .A0(n6349), .A1(n6345), .B0(n6347), .Y(n6147) );
INVX2TS U3041 ( .A(n1915), .Y(n2098) );
INVX2TS U3042 ( .A(n1897), .Y(n4273) );
NOR2X1TS U3043 ( .A(n9995), .B(n2704), .Y(n10030) );
INVX2TS U3044 ( .A(n1872), .Y(n10184) );
NOR2X1TS U3045 ( .A(n2704), .B(n2380), .Y(n2456) );
INVX4TS U3046 ( .A(n3071), .Y(n3350) );
ADDFHX1TS U3047 ( .A(n3117), .B(n3116), .CI(n3115), .CO(n3353), .S(n3168) );
XOR2X1TS U3048 ( .A(n3090), .B(n3065), .Y(n3066) );
NAND2X1TS U3049 ( .A(Sgf_normalized_result[16]), .B(n11088), .Y(n11090) );
XNOR2X1TS U3050 ( .A(n8257), .B(n8256), .Y(n8269) );
OA21XLTS U3051 ( .A0(n7219), .A1(n7222), .B0(n7220), .Y(n1225) );
NOR2X1TS U3052 ( .A(n9995), .B(n2799), .Y(n2758) );
INVX2TS U3053 ( .A(n1646), .Y(n1823) );
ADDFX1TS U3054 ( .A(n2687), .B(n2686), .CI(n2685), .CO(n2691), .S(n2733) );
OAI21XLTS U3055 ( .A0(n6170), .A1(n6166), .B0(n6167), .Y(n6130) );
OR2X2TS U3056 ( .A(DP_OP_342J35_126_4270_n211), .B(
DP_OP_342J35_126_4270_n224), .Y(n1220) );
CLKAND2X2TS U3057 ( .A(n6528), .B(n6527), .Y(n6529) );
INVX2TS U3058 ( .A(n1893), .Y(n2082) );
NOR2X1TS U3059 ( .A(n4074), .B(n4084), .Y(n4071) );
OR2X2TS U3060 ( .A(n1671), .B(Op_MX[25]), .Y(n1698) );
INVX2TS U3061 ( .A(n4136), .Y(n4648) );
NOR2X1TS U3062 ( .A(n4513), .B(n4030), .Y(n4053) );
NOR2X1TS U3063 ( .A(n4090), .B(n4030), .Y(n4041) );
NOR2X1TS U3064 ( .A(n4090), .B(n4084), .Y(n4064) );
NOR2X1TS U3065 ( .A(n4098), .B(n4084), .Y(n4061) );
INVX2TS U3066 ( .A(n4469), .Y(n4900) );
XNOR2X1TS U3067 ( .A(n7569), .B(n7568), .Y(n7572) );
NOR2X1TS U3068 ( .A(n4513), .B(n4102), .Y(n4509) );
OAI21X1TS U3069 ( .A0(n8262), .A1(n8265), .B0(n8263), .Y(n8256) );
ADDFX1TS U3070 ( .A(n2582), .B(n2581), .CI(n2580), .CO(n2588), .S(n2686) );
NOR2X1TS U3071 ( .A(n4077), .B(n4094), .Y(n3974) );
NOR2X1TS U3072 ( .A(n4102), .B(n4077), .Y(n3984) );
NOR2X1TS U3073 ( .A(n2200), .B(n1429), .Y(n1368) );
NOR2X1TS U3074 ( .A(n4074), .B(n4094), .Y(n3983) );
CLKAND2X2TS U3075 ( .A(n888), .B(n889), .Y(n897) );
NOR2X1TS U3076 ( .A(n4512), .B(n4077), .Y(n4007) );
NOR2X1TS U3077 ( .A(n4074), .B(n4102), .Y(n4009) );
NOR2X1TS U3078 ( .A(n2200), .B(n880), .Y(n1407) );
INVX2TS U3079 ( .A(n1660), .Y(n1822) );
NOR2X1TS U3080 ( .A(n2195), .B(n774), .Y(n1394) );
NOR2X1TS U3081 ( .A(n4090), .B(n4052), .Y(n4002) );
NOR2X1TS U3082 ( .A(n4512), .B(n4074), .Y(n4051) );
INVX2TS U3083 ( .A(n1659), .Y(n1947) );
NOR2X1TS U3084 ( .A(n4090), .B(n4094), .Y(n4046) );
NOR2X1TS U3085 ( .A(n4090), .B(n4102), .Y(n4091) );
NOR2X1TS U3086 ( .A(n4098), .B(n4094), .Y(n4087) );
NOR2X1TS U3087 ( .A(n4513), .B(n4052), .Y(n4095) );
NOR2X1TS U3088 ( .A(n4090), .B(n4512), .Y(n4101) );
NOR2X1TS U3089 ( .A(n4098), .B(n4102), .Y(n4099) );
NOR2X1TS U3090 ( .A(n4513), .B(n4094), .Y(n4103) );
OR2X2TS U3091 ( .A(n3081), .B(n1535), .Y(n1146) );
NOR2X1TS U3092 ( .A(n4077), .B(n4052), .Y(n3989) );
NOR2X1TS U3093 ( .A(n4077), .B(n4030), .Y(n4028) );
NOR2X1TS U3094 ( .A(n4074), .B(n4030), .Y(n4034) );
NOR2X1TS U3095 ( .A(n1391), .B(n774), .Y(n1379) );
XNOR2X1TS U3096 ( .A(n3074), .B(n3070), .Y(n3071) );
NOR2X1TS U3097 ( .A(n1390), .B(n774), .Y(n1426) );
INVX4TS U3098 ( .A(n2370), .Y(n2704) );
NOR2X1TS U3099 ( .A(n2200), .B(n1390), .Y(n1348) );
NOR2X1TS U3100 ( .A(n2200), .B(n1391), .Y(n2185) );
INVX2TS U3101 ( .A(n4151), .Y(n4630) );
INVX2TS U3102 ( .A(n4118), .Y(n4627) );
INVX2TS U3103 ( .A(n4139), .Y(n4649) );
INVX4TS U3104 ( .A(n2387), .Y(n2799) );
INVX2TS U3105 ( .A(n4110), .Y(n4772) );
INVX2TS U3106 ( .A(n1864), .Y(n1949) );
INVX2TS U3107 ( .A(n1866), .Y(n1737) );
INVX4TS U3108 ( .A(n2394), .Y(n2744) );
NOR2X1TS U3109 ( .A(n2513), .B(n6854), .Y(n2539) );
NAND2X1TS U3110 ( .A(Sgf_normalized_result[14]), .B(n11084), .Y(n11086) );
OAI21X1TS U3111 ( .A0(n3068), .A1(n3050), .B0(n3049), .Y(n3062) );
OR2X2TS U3112 ( .A(n3097), .B(n1533), .Y(n1029) );
OAI21X1TS U3113 ( .A0(n3059), .A1(n3092), .B0(n3058), .Y(n3060) );
NOR2X1TS U3114 ( .A(n880), .B(n1428), .Y(n1438) );
NOR2X1TS U3115 ( .A(n880), .B(n988), .Y(n1444) );
NOR2X1TS U3116 ( .A(n2199), .B(n774), .Y(n1362) );
INVX2TS U3117 ( .A(n4165), .Y(n4771) );
NAND2X2TS U3118 ( .A(n3501), .B(n3063), .Y(n3557) );
NOR2X1TS U3119 ( .A(n4070), .B(n4512), .Y(n4093) );
NOR2XLTS U3120 ( .A(n6135), .B(n6166), .Y(n6137) );
NOR2X1TS U3121 ( .A(n6854), .B(n737), .Y(n6881) );
OAI21X1TS U3122 ( .A0(n8373), .A1(n8154), .B0(n8156), .Y(n8153) );
NOR2X1TS U3123 ( .A(n4070), .B(n4094), .Y(n4005) );
CLKAND2X2TS U3124 ( .A(n886), .B(n887), .Y(n896) );
XOR2X1TS U3125 ( .A(n8373), .B(n8145), .Y(n8356) );
OAI21X1TS U3126 ( .A0(n8182), .A1(n8181), .B0(n8180), .Y(n8187) );
NOR2X1TS U3127 ( .A(n4070), .B(n4030), .Y(n4037) );
NOR2X1TS U3128 ( .A(n880), .B(n1381), .Y(n1380) );
NOR2X1TS U3129 ( .A(n880), .B(n2190), .Y(n1385) );
NOR2X1TS U3130 ( .A(n4070), .B(n4084), .Y(n4067) );
NOR2X1TS U3131 ( .A(n880), .B(n1382), .Y(n1427) );
INVX2TS U3132 ( .A(n4168), .Y(n4643) );
NOR2X1TS U3133 ( .A(n2342), .B(n737), .Y(n2502) );
INVX4TS U3134 ( .A(DP_OP_341J35_125_6458_n267), .Y(
DP_OP_341J35_125_6458_n262) );
NOR2X1TS U3135 ( .A(n2513), .B(n2652), .Y(n2341) );
NOR2X2TS U3136 ( .A(n8240), .B(n8244), .Y(n8278) );
OAI21X2TS U3137 ( .A0(n8244), .A1(n8243), .B0(n8242), .Y(n8284) );
NAND2X1TS U3138 ( .A(n7954), .B(n7953), .Y(n8263) );
OAI21X1TS U3139 ( .A0(n7187), .A1(n7612), .B0(n7188), .Y(n7155) );
OAI21X1TS U3140 ( .A0(n8213), .A1(n8212), .B0(n8211), .Y(n8214) );
OAI21X1TS U3141 ( .A0(n7212), .A1(n7177), .B0(n7178), .Y(n7157) );
NOR2X1TS U3142 ( .A(n9995), .B(n2688), .Y(n2625) );
NOR2X1TS U3143 ( .A(n2890), .B(n2688), .Y(n2731) );
NOR2X1TS U3144 ( .A(n2890), .B(n839), .Y(n2897) );
NOR2X1TS U3145 ( .A(n2890), .B(n2894), .Y(n2891) );
NOR2X1TS U3146 ( .A(n9995), .B(n2894), .Y(n2895) );
NOR2X1TS U3147 ( .A(n9995), .B(n2880), .Y(n2888) );
OAI22X1TS U3148 ( .A0(n3039), .A1(n878), .B0(n3480), .B1(n3032), .Y(n3037)
);
INVX2TS U3149 ( .A(n2614), .Y(n9993) );
NOR2X1TS U3150 ( .A(n6071), .B(n731), .Y(n6085) );
INVX2TS U3151 ( .A(n2617), .Y(n9992) );
NOR2X1TS U3152 ( .A(n2652), .B(n737), .Y(n6857) );
NOR2X1TS U3153 ( .A(n7375), .B(n8737), .Y(n7378) );
NOR2X1TS U3154 ( .A(n9995), .B(n2862), .Y(n2886) );
NOR2X1TS U3155 ( .A(n2890), .B(n2880), .Y(n2883) );
INVX2TS U3156 ( .A(n904), .Y(n3498) );
NOR2X1TS U3157 ( .A(n2890), .B(n2862), .Y(n2865) );
NOR2X1TS U3158 ( .A(n9995), .B(n2824), .Y(n2875) );
NOR2X1TS U3159 ( .A(n882), .B(n2531), .Y(n2648) );
INVX2TS U3160 ( .A(n3107), .Y(n3484) );
OAI21X1TS U3161 ( .A0(n7316), .A1(n7339), .B0(n7341), .Y(n7327) );
NOR2X1TS U3162 ( .A(n882), .B(n2523), .Y(n2527) );
NOR2X1TS U3163 ( .A(n2513), .B(n882), .Y(n2517) );
INVX4TS U3164 ( .A(n1862), .Y(n2174) );
XOR2X1TS U3165 ( .A(n4019), .B(n4018), .Y(n4531) );
NOR2X1TS U3166 ( .A(n4647), .B(n4052), .Y(n4029) );
NOR2X1TS U3167 ( .A(n4102), .B(n4647), .Y(n3973) );
NOR2X2TS U3168 ( .A(n2513), .B(n2342), .Y(n2819) );
NOR2X1TS U3169 ( .A(n4094), .B(n4647), .Y(n3990) );
XOR2X1TS U3170 ( .A(n4024), .B(n4023), .Y(n4665) );
NOR2X1TS U3171 ( .A(n6055), .B(n6083), .Y(n6089) );
NOR2X1TS U3172 ( .A(n6083), .B(n5945), .Y(n5805) );
NOR2X1TS U3173 ( .A(n9995), .B(n2630), .Y(n2839) );
NOR2X1TS U3174 ( .A(n2890), .B(n2824), .Y(n2827) );
OR2X2TS U3175 ( .A(n4482), .B(n4481), .Y(n843) );
NOR2X1TS U3176 ( .A(n2866), .B(n2880), .Y(n2837) );
NOR2X1TS U3177 ( .A(n2876), .B(n2862), .Y(n2830) );
NOR2X1TS U3178 ( .A(n2831), .B(n2894), .Y(n2834) );
NOR2X1TS U3179 ( .A(n10428), .B(n10411), .Y(DP_OP_347J35_131_5122_n167) );
NOR2X1TS U3180 ( .A(n10408), .B(n10419), .Y(DP_OP_347J35_131_5122_n153) );
NOR2X1TS U3181 ( .A(n10425), .B(n10403), .Y(n10404) );
CLKAND2X2TS U3182 ( .A(n1771), .B(n885), .Y(n894) );
NOR2X1TS U3183 ( .A(n10408), .B(n10412), .Y(DP_OP_347J35_131_5122_n154) );
NAND2X1TS U3184 ( .A(Sgf_normalized_result[12]), .B(n11080), .Y(n11082) );
NOR2X1TS U3185 ( .A(n10425), .B(n10427), .Y(n10416) );
AO21X1TS U3186 ( .A0(n4112), .A1(n933), .B0(n932), .Y(n755) );
CLKAND2X2TS U3187 ( .A(n890), .B(n891), .Y(n898) );
OAI21X1TS U3188 ( .A0(n7580), .A1(n7577), .B0(n7578), .Y(n8215) );
OR2X2TS U3189 ( .A(n4190), .B(n4189), .Y(n842) );
NOR2X1TS U3190 ( .A(n2866), .B(n2688), .Y(n2732) );
NOR2X1TS U3191 ( .A(n2866), .B(n2894), .Y(n2868) );
INVX2TS U3192 ( .A(n9636), .Y(n9634) );
NOR2X1TS U3193 ( .A(n2866), .B(n839), .Y(n2879) );
NOR2X1TS U3194 ( .A(n2876), .B(n2688), .Y(n2719) );
NOR2X1TS U3195 ( .A(n10408), .B(n10423), .Y(n10345) );
NOR2X1TS U3196 ( .A(n10425), .B(n10411), .Y(n10346) );
NOR2X1TS U3197 ( .A(n6041), .B(n731), .Y(n6068) );
NOR2X1TS U3198 ( .A(n10428), .B(n10413), .Y(n10347) );
NOR2X2TS U3199 ( .A(n8246), .B(n8245), .Y(n8277) );
AOI21X2TS U3200 ( .A0(n4112), .A1(n1147), .B0(n1315), .Y(n1285) );
NOR2X1TS U3201 ( .A(n9845), .B(n729), .Y(DP_OP_342J35_126_4270_n294) );
NOR2X1TS U3202 ( .A(n2605), .B(n2862), .Y(n2584) );
NOR2X1TS U3203 ( .A(n2880), .B(n2380), .Y(n2582) );
INVX2TS U3204 ( .A(n2425), .Y(n2265) );
NOR2X1TS U3205 ( .A(n10420), .B(n10425), .Y(n6407) );
NOR2X1TS U3206 ( .A(n2880), .B(n2605), .Y(n2593) );
INVX2TS U3207 ( .A(n2408), .Y(n9929) );
INVX2TS U3208 ( .A(n2305), .Y(n2672) );
NAND2X1TS U3209 ( .A(n931), .B(n2439), .Y(n2426) );
OAI21X1TS U3210 ( .A0(n7266), .A1(n7287), .B0(n7289), .Y(n7274) );
INVX4TS U3211 ( .A(n2222), .Y(n2545) );
NOR2X1TS U3212 ( .A(n2894), .B(n2380), .Y(n2589) );
INVX2TS U3213 ( .A(n2431), .Y(n9960) );
INVX2TS U3214 ( .A(n2433), .Y(n9959) );
INVX4TS U3215 ( .A(n2215), .Y(n2342) );
NOR2X1TS U3216 ( .A(n2866), .B(n2824), .Y(n2596) );
NOR2X2TS U3217 ( .A(n2862), .B(n2380), .Y(n2578) );
NOR2X1TS U3218 ( .A(n2831), .B(n2862), .Y(n2600) );
NOR2X1TS U3219 ( .A(n2894), .B(n2745), .Y(n2641) );
INVX4TS U3220 ( .A(n2316), .Y(n2652) );
NOR2X1TS U3221 ( .A(n10408), .B(n10425), .Y(n10309) );
NOR2X1TS U3222 ( .A(n2831), .B(n2880), .Y(n2639) );
INVX4TS U3223 ( .A(n2240), .Y(n2544) );
NOR2X1TS U3224 ( .A(n2745), .B(n2880), .Y(n2604) );
INVX4TS U3225 ( .A(n2491), .Y(n9995) );
INVX2TS U3226 ( .A(n2410), .Y(n9928) );
NOR2X1TS U3227 ( .A(n2745), .B(n2862), .Y(n2591) );
NOR2X1TS U3228 ( .A(n2894), .B(n2605), .Y(n2602) );
INVX4TS U3229 ( .A(n9821), .Y(n9845) );
INVX2TS U3230 ( .A(n2472), .Y(n2876) );
INVX6TS U3231 ( .A(n2573), .Y(n2862) );
AOI21X1TS U3232 ( .A0(n7583), .A1(n1069), .B0(n7533), .Y(n7580) );
NOR2X1TS U3233 ( .A(n10423), .B(n10403), .Y(n10401) );
NOR2X1TS U3234 ( .A(n2824), .B(n2380), .Y(n2575) );
CLKAND2X2TS U3235 ( .A(Op_MY[14]), .B(n4060), .Y(n892) );
NOR2X1TS U3236 ( .A(n2605), .B(n2824), .Y(n2577) );
INVX2TS U3237 ( .A(n2401), .Y(n9946) );
NOR2X1TS U3238 ( .A(n10423), .B(n10421), .Y(n10409) );
NOR2X1TS U3239 ( .A(n10413), .B(n10407), .Y(n10399) );
NOR2X1TS U3240 ( .A(n10423), .B(n10411), .Y(n10405) );
NOR2X1TS U3241 ( .A(n10413), .B(n10419), .Y(n10406) );
NOR2X1TS U3242 ( .A(n3948), .B(n3935), .Y(n3937) );
XNOR2X1TS U3243 ( .A(n3228), .B(n900), .Y(n3039) );
INVX2TS U3244 ( .A(n2399), .Y(n9944) );
NOR2X1TS U3245 ( .A(n7290), .B(n7287), .Y(n7293) );
OAI21X1TS U3246 ( .A0(n3951), .A1(n3935), .B0(n3934), .Y(n3936) );
OAI21X1TS U3247 ( .A0(n3951), .A1(n3950), .B0(n3949), .Y(n3952) );
OAI21X1TS U3248 ( .A0(n7290), .A1(n7289), .B0(n7288), .Y(n7291) );
NOR2X1TS U3249 ( .A(n3948), .B(n3950), .Y(n3953) );
CMPR32X2TS U3250 ( .A(Op_MY[34]), .B(Op_MY[47]), .C(n2974), .CO(n2977), .S(
n7486) );
NOR2X1TS U3251 ( .A(n10413), .B(n10412), .Y(n10418) );
BUFX4TS U3252 ( .A(n3389), .Y(n899) );
CLKXOR2X2TS U3253 ( .A(n1588), .B(n1587), .Y(n3481) );
NOR2X1TS U3254 ( .A(n2831), .B(n2630), .Y(n2685) );
INVX2TS U3255 ( .A(n2579), .Y(n2866) );
CLKAND2X2TS U3256 ( .A(n1772), .B(n4060), .Y(n893) );
NOR2X1TS U3257 ( .A(n2831), .B(n2688), .Y(n2735) );
OR2X2TS U3258 ( .A(n2585), .B(n2423), .Y(n931) );
CLKXOR2X2TS U3259 ( .A(n1622), .B(n1621), .Y(n3241) );
OAI21X1TS U3260 ( .A0(n8741), .A1(n8740), .B0(n8739), .Y(n8742) );
NOR2X1TS U3261 ( .A(n2745), .B(n2824), .Y(n2580) );
OAI22X1TS U3262 ( .A0(n7898), .A1(n7909), .B0(n7900), .B1(n7908), .Y(n7914)
);
OAI22X1TS U3263 ( .A0(n7905), .A1(n7900), .B0(n7944), .B1(n7898), .Y(n7895)
);
NOR2X1TS U3264 ( .A(n917), .B(n9833), .Y(n9772) );
NOR2X1TS U3265 ( .A(n917), .B(n9839), .Y(DP_OP_342J35_126_4270_n335) );
INVX2TS U3266 ( .A(n2357), .Y(n9927) );
OAI22X1TS U3267 ( .A0(n8017), .A1(n7847), .B0(n7898), .B1(n8018), .Y(n7770)
);
XNOR2X2TS U3268 ( .A(n2421), .B(n2420), .Y(n2585) );
OAI22X1TS U3269 ( .A0(n7898), .A1(n8036), .B0(n7900), .B1(n8081), .Y(n7733)
);
NOR2X1TS U3270 ( .A(n7898), .B(n8096), .Y(n8020) );
XOR2X1TS U3271 ( .A(n2485), .B(n2430), .Y(n2472) );
NOR2X1TS U3272 ( .A(n10411), .B(n10419), .Y(n10410) );
XNOR2X2TS U3273 ( .A(n2263), .B(n2262), .Y(n2576) );
AOI21X1TS U3274 ( .A0(n3954), .A1(n1550), .B0(n1549), .Y(n1555) );
INVX4TS U3275 ( .A(n9827), .Y(n9849) );
AOI21X2TS U3276 ( .A0(n3954), .A1(n3932), .B0(n3933), .Y(n3930) );
NOR2X1TS U3277 ( .A(n8050), .B(n8096), .Y(n8077) );
OAI21X1TS U3278 ( .A0(n2314), .A1(n2237), .B0(n2236), .Y(n2239) );
OAI21X1TS U3279 ( .A0(n2485), .A1(n2484), .B0(n2483), .Y(n2490) );
OR2X2TS U3280 ( .A(n2467), .B(n2291), .Y(n1030) );
NOR2X1TS U3281 ( .A(n10419), .B(n10403), .Y(n10397) );
NOR2X1TS U3282 ( .A(n2605), .B(n2630), .Y(n2574) );
NOR2X1TS U3283 ( .A(n10419), .B(n10421), .Y(n10415) );
NOR2X1TS U3284 ( .A(n5888), .B(n731), .Y(n5983) );
NOR2X1TS U3285 ( .A(n10411), .B(n10412), .Y(n10414) );
NOR2X1TS U3286 ( .A(n8083), .B(n8096), .Y(n8099) );
OAI22X1TS U3287 ( .A0(n7910), .A1(n8036), .B0(n7943), .B1(n8081), .Y(n7774)
);
NOR2X1TS U3288 ( .A(n5941), .B(n731), .Y(n5716) );
NOR2X1TS U3289 ( .A(n8017), .B(n8096), .Y(n8037) );
OR3X4TS U3290 ( .A(underflow_flag), .B(overflow_flag), .C(n11169), .Y(n11171) );
NOR2X1TS U3291 ( .A(n7900), .B(n8096), .Y(n7728) );
OAI21XLTS U3292 ( .A0(DP_OP_341J35_125_6458_n466), .A1(n9670), .B0(n7429),
.Y(DP_OP_341J35_125_6458_n457) );
OAI21X1TS U3293 ( .A0(n1677), .A1(n1676), .B0(n1675), .Y(n1678) );
NOR2X1TS U3294 ( .A(n1673), .B(n1676), .Y(n1679) );
NOR2X1TS U3295 ( .A(n1673), .B(n1640), .Y(n1595) );
INVX2TS U3296 ( .A(n2464), .Y(n9948) );
CLKXOR2X2TS U3297 ( .A(n1487), .B(n1486), .Y(n3097) );
INVX6TS U3298 ( .A(n1548), .Y(n3954) );
NOR2X1TS U3299 ( .A(n9847), .B(n729), .Y(n9780) );
OR2X2TS U3300 ( .A(n8095), .B(n8094), .Y(n8116) );
CLKXOR2X2TS U3301 ( .A(n1563), .B(n1578), .Y(n3374) );
AO21X1TS U3302 ( .A0(n1365), .A1(Op_MY[26]), .B0(n1364), .Y(n932) );
NOR2X1TS U3303 ( .A(n9840), .B(n729), .Y(n9787) );
OR2X2TS U3304 ( .A(n4480), .B(Op_MY[25]), .Y(n4549) );
CLKAND2X2TS U3305 ( .A(Op_MY[14]), .B(n1772), .Y(n895) );
OAI21X1TS U3306 ( .A0(n3955), .A1(n3949), .B0(n3956), .Y(n1306) );
OR2X2TS U3307 ( .A(n2381), .B(n2288), .Y(n1123) );
NOR2X1TS U3308 ( .A(n5946), .B(n731), .Y(n5828) );
AO21X2TS U3309 ( .A0(n2260), .A1(n2212), .B0(n2211), .Y(n1036) );
OAI21X1TS U3310 ( .A0(n4011), .A1(n4015), .B0(n4016), .Y(n1311) );
NOR2X1TS U3311 ( .A(n814), .B(n7905), .Y(n8001) );
NAND2X1TS U3312 ( .A(n1464), .B(n1074), .Y(n1468) );
INVX2TS U3313 ( .A(n2470), .Y(n2745) );
INVX4TS U3314 ( .A(n3120), .Y(n753) );
NOR2X1TS U3315 ( .A(n8093), .B(n814), .Y(n8119) );
INVX4TS U3316 ( .A(n7038), .Y(n9847) );
OR2X4TS U3317 ( .A(n11061), .B(FSM_selector_C), .Y(n10498) );
INVX2TS U3318 ( .A(n1463), .Y(n1539) );
NOR2X1TS U3319 ( .A(n1648), .B(n1650), .Y(n1653) );
CLKXOR2X2TS U3320 ( .A(n1575), .B(n1574), .Y(n3192) );
INVX4TS U3321 ( .A(n7043), .Y(n9840) );
OAI21X1TS U3322 ( .A0(n7681), .A1(n7665), .B0(n7664), .Y(n7666) );
OAI21X1TS U3323 ( .A0(n7310), .A1(n7309), .B0(n7308), .Y(n9815) );
OAI22X1TS U3324 ( .A0(n6354), .A1(n961), .B0(n10383), .B1(n1081), .Y(
DP_OP_347J35_131_5122_n412) );
OAI21X1TS U3325 ( .A0(n7704), .A1(n7700), .B0(n7701), .Y(n7698) );
OAI21X1TS U3326 ( .A0(n3965), .A1(n3964), .B0(n3963), .Y(n3966) );
OAI21X1TS U3327 ( .A0(n7681), .A1(n7677), .B0(n7678), .Y(n7659) );
OAI21X1TS U3328 ( .A0(n3965), .A1(n3943), .B0(n3944), .Y(n3921) );
OAI21X1TS U3329 ( .A0(n2413), .A1(n2210), .B0(n2209), .Y(n2211) );
OAI21X2TS U3330 ( .A0(n2205), .A1(n2284), .B0(n2204), .Y(n2260) );
NOR2X1TS U3331 ( .A(n2452), .B(n2290), .Y(n2365) );
OAI21X1TS U3332 ( .A0(n1340), .A1(n1323), .B0(n1334), .Y(n1316) );
OAI21X2TS U3333 ( .A0(n1473), .A1(n1270), .B0(n1269), .Y(n1271) );
NOR2X1TS U3334 ( .A(n2210), .B(n2411), .Y(n2212) );
NOR2X1TS U3335 ( .A(n3964), .B(n3961), .Y(n3967) );
NOR2X1TS U3336 ( .A(n4010), .B(n4015), .Y(n1312) );
AOI21X2TS U3337 ( .A0(n7693), .A1(n7656), .B0(n7655), .Y(n7681) );
OAI21X1TS U3338 ( .A0(n2351), .A1(n2379), .B0(n2352), .Y(n2463) );
OAI22X2TS U3339 ( .A0(n7055), .A1(n728), .B0(n2966), .B1(n7321), .Y(
DP_OP_342J35_126_4270_n772) );
NOR2X1TS U3340 ( .A(n5897), .B(n767), .Y(n5791) );
NOR2X1TS U3341 ( .A(n9829), .B(n761), .Y(n7149) );
NOR2X1TS U3342 ( .A(n9829), .B(DP_OP_342J35_126_4270_n748), .Y(n7109) );
NOR2X1TS U3343 ( .A(n9829), .B(n764), .Y(n7121) );
NAND2X2TS U3344 ( .A(n999), .B(n1672), .Y(n1300) );
NAND2X1TS U3345 ( .A(n7702), .B(n7701), .Y(n7703) );
NOR2X1TS U3346 ( .A(n5897), .B(n768), .Y(n5665) );
NOR2X1TS U3347 ( .A(n9841), .B(n729), .Y(n9790) );
OAI22X2TS U3348 ( .A0(n2966), .A1(n728), .B0(n7321), .B1(Op_MY[47]), .Y(
DP_OP_342J35_126_4270_n774) );
NOR2X1TS U3349 ( .A(n1333), .B(n1323), .Y(n1317) );
OAI21X1TS U3350 ( .A0(n8753), .A1(Op_MY[47]), .B0(n8754), .Y(n7296) );
XNOR2X2TS U3351 ( .A(n2278), .B(n2277), .Y(n2452) );
NOR2X6TS U3352 ( .A(n10449), .B(n11225), .Y(n10450) );
NOR2X1TS U3353 ( .A(n819), .B(n739), .Y(n7835) );
OR2X2TS U3354 ( .A(n883), .B(Op_MX[42]), .Y(n1118) );
NOR2X1TS U3355 ( .A(n1034), .B(n731), .Y(n5669) );
NOR2X1TS U3356 ( .A(n758), .B(n733), .Y(n7555) );
INVX2TS U3357 ( .A(n2317), .Y(n6853) );
INVX2TS U3358 ( .A(n2230), .Y(n2524) );
NAND2X1TS U3359 ( .A(n1095), .B(n1469), .Y(n1470) );
INVX2TS U3360 ( .A(n2395), .Y(n2523) );
NOR2X1TS U3361 ( .A(n763), .B(n749), .Y(n7087) );
NOR2X1TS U3362 ( .A(n751), .B(n762), .Y(n7086) );
NOR2X1TS U3363 ( .A(n743), .B(n813), .Y(n7737) );
NOR2X1TS U3364 ( .A(n769), .B(n731), .Y(n5724) );
OAI21X1TS U3365 ( .A0(n1524), .A1(n4056), .B0(n4057), .Y(n1273) );
OR2X2TS U3366 ( .A(n5638), .B(n735), .Y(n775) );
NOR2X1TS U3367 ( .A(n809), .B(n738), .Y(n7725) );
INVX2TS U3368 ( .A(n2304), .Y(n2508) );
INVX2TS U3369 ( .A(n1650), .Y(n1620) );
NOR2X1TS U3370 ( .A(n767), .B(n731), .Y(n5731) );
NAND2X4TS U3371 ( .A(n1105), .B(n2379), .Y(n2380) );
NOR2X1TS U3372 ( .A(n758), .B(n740), .Y(n7797) );
NOR2X1TS U3373 ( .A(n743), .B(n810), .Y(n7820) );
NOR2X1TS U3374 ( .A(n819), .B(n741), .Y(n7723) );
NOR2X1TS U3375 ( .A(n743), .B(n740), .Y(n8078) );
NOR2X1TS U3376 ( .A(DP_OP_343J35_127_4270_n853), .B(n747), .Y(n7772) );
NOR2XLTS U3377 ( .A(n1109), .B(n774), .Y(n5744) );
NOR2XLTS U3378 ( .A(n1032), .B(n774), .Y(n5977) );
NOR2X1TS U3379 ( .A(n853), .B(n774), .Y(n5741) );
NOR2X1TS U3380 ( .A(n736), .B(n738), .Y(n7741) );
NOR2X1TS U3381 ( .A(n746), .B(n766), .Y(n5819) );
NOR2X1TS U3382 ( .A(n1026), .B(n774), .Y(n5738) );
NOR2X1TS U3383 ( .A(n761), .B(n749), .Y(n7127) );
CLKAND2X4TS U3384 ( .A(n1260), .B(n10429), .Y(n9512) );
NOR2X1TS U3385 ( .A(n738), .B(n820), .Y(n7675) );
NOR2X1TS U3386 ( .A(n819), .B(n734), .Y(n7717) );
NOR2X1TS U3387 ( .A(n746), .B(n770), .Y(n5717) );
INVX2TS U3388 ( .A(n7683), .Y(n8081) );
NOR2X1TS U3389 ( .A(DP_OP_343J35_127_4270_n853), .B(n745), .Y(n7718) );
NOR2X1TS U3390 ( .A(n743), .B(n955), .Y(n7550) );
OR2X2TS U3391 ( .A(n881), .B(Op_MX[18]), .Y(n827) );
BUFX6TS U3392 ( .A(n11249), .Y(n754) );
INVX2TS U3393 ( .A(n2321), .Y(n6878) );
NOR2X1TS U3394 ( .A(n847), .B(n735), .Y(n5674) );
NOR2X1TS U3395 ( .A(n742), .B(n810), .Y(n7566) );
OAI21X2TS U3396 ( .A0(n1453), .A1(n1459), .B0(n1454), .Y(n1523) );
NOR2X1TS U3397 ( .A(n741), .B(n745), .Y(n7753) );
NOR2X1TS U3398 ( .A(n820), .B(n734), .Y(n7754) );
NOR2X1TS U3399 ( .A(n735), .B(n848), .Y(n6024) );
NAND2X2TS U3400 ( .A(n6359), .B(n6357), .Y(n6358) );
NOR2X1TS U3401 ( .A(n740), .B(n756), .Y(n7809) );
NOR2X1TS U3402 ( .A(n744), .B(n810), .Y(n7528) );
NOR2X1TS U3403 ( .A(n838), .B(n730), .Y(n7117) );
NOR2X1TS U3404 ( .A(n738), .B(n747), .Y(n7758) );
NOR2X1TS U3405 ( .A(n813), .B(n8096), .Y(n7811) );
NOR2X1TS U3406 ( .A(n730), .B(n749), .Y(n7102) );
NOR2X1TS U3407 ( .A(n733), .B(n757), .Y(n8013) );
NOR2X1TS U3408 ( .A(n763), .B(n729), .Y(n7103) );
INVX2TS U3409 ( .A(n9837), .Y(n9839) );
NOR2X1TS U3410 ( .A(n762), .B(n748), .Y(n7104) );
NOR2X1TS U3411 ( .A(n811), .B(n8096), .Y(n8042) );
INVX2TS U3412 ( .A(n7570), .Y(n7909) );
INVX2TS U3413 ( .A(n9793), .Y(n9831) );
NOR2X1TS U3414 ( .A(n762), .B(n729), .Y(n7125) );
NOR2X1TS U3415 ( .A(n762), .B(n749), .Y(n7074) );
INVX2TS U3416 ( .A(n7672), .Y(n7905) );
NOR2X1TS U3417 ( .A(n763), .B(n748), .Y(n7073) );
INVX2TS U3418 ( .A(n7684), .Y(n7944) );
NOR2X1TS U3419 ( .A(n764), .B(n729), .Y(n7163) );
NAND2X2TS U3420 ( .A(n6353), .B(n6351), .Y(n6352) );
NOR2X1TS U3421 ( .A(n761), .B(n729), .Y(n7088) );
NOR2X1TS U3422 ( .A(n741), .B(n747), .Y(n7827) );
INVX2TS U3423 ( .A(n7039), .Y(n9848) );
INVX2TS U3424 ( .A(n9832), .Y(n9834) );
NOR2X1TS U3425 ( .A(n764), .B(n749), .Y(n7089) );
NAND2X2TS U3426 ( .A(n6355), .B(Op_MX[13]), .Y(n6354) );
NAND2X4TS U3427 ( .A(n1027), .B(n7045), .Y(n9841) );
NOR2X1TS U3428 ( .A(DP_OP_342J35_126_4270_n748), .B(n748), .Y(n7092) );
NOR2X1TS U3429 ( .A(n750), .B(n730), .Y(n7098) );
INVX2TS U3430 ( .A(n7676), .Y(n8036) );
NOR2X1TS U3431 ( .A(n2503), .B(n1049), .Y(n2506) );
NOR2X1TS U3432 ( .A(n852), .B(n735), .Y(n6063) );
OR2X2TS U3433 ( .A(n730), .B(n764), .Y(n851) );
NOR2X1TS U3434 ( .A(n2504), .B(n1049), .Y(n2505) );
OAI21X1TS U3435 ( .A0(n7663), .A1(n7678), .B0(n7662), .Y(n7669) );
NOR2X1TS U3436 ( .A(n809), .B(n739), .Y(n7761) );
INVX2TS U3437 ( .A(n7044), .Y(n9846) );
NAND2X2TS U3438 ( .A(n6442), .B(Op_MX[6]), .Y(n6441) );
NOR2X1TS U3439 ( .A(DP_OP_343J35_127_4270_n853), .B(n736), .Y(n7745) );
NOR2X1TS U3440 ( .A(n741), .B(n820), .Y(n7714) );
INVX2TS U3441 ( .A(n9838), .Y(n9842) );
NOR2X1TS U3442 ( .A(n809), .B(n734), .Y(n7715) );
NAND2X2TS U3443 ( .A(n6440), .B(n6438), .Y(n6439) );
NOR2X1TS U3444 ( .A(n738), .B(n745), .Y(n7740) );
NOR2X1TS U3445 ( .A(n733), .B(n756), .Y(n7799) );
INVX4TS U3446 ( .A(n881), .Y(n9829) );
NOR2X1TS U3447 ( .A(n768), .B(n731), .Y(n6065) );
NOR2X1TS U3448 ( .A(n745), .B(n734), .Y(n7759) );
NOR2X1TS U3449 ( .A(n742), .B(n733), .Y(n7806) );
NAND2X2TS U3450 ( .A(n6448), .B(n6446), .Y(n6447) );
NOR2X1TS U3451 ( .A(n750), .B(n762), .Y(n7137) );
NOR2X1TS U3452 ( .A(n1700), .B(n1584), .Y(n1550) );
NOR2X1TS U3453 ( .A(n744), .B(n733), .Y(n7544) );
NOR2X1TS U3454 ( .A(n743), .B(n733), .Y(n8044) );
NOR2X1TS U3455 ( .A(n809), .B(DP_OP_343J35_127_4270_n857), .Y(n7742) );
NOR2X1TS U3456 ( .A(n838), .B(n764), .Y(n7099) );
OR2X2TS U3457 ( .A(Op_MX[17]), .B(Op_MX[44]), .Y(n1111) );
OR2X2TS U3458 ( .A(Op_MY[47]), .B(Op_MY[20]), .Y(n1028) );
NOR2X1TS U3459 ( .A(n838), .B(n762), .Y(n7145) );
OR2X2TS U3460 ( .A(Op_MY[37]), .B(Op_MY[10]), .Y(n1095) );
NOR2X1TS U3461 ( .A(n819), .B(DP_OP_343J35_127_4270_n857), .Y(n7744) );
OR2X2TS U3462 ( .A(Op_MY[33]), .B(Op_MY[6]), .Y(n1076) );
OR2X2TS U3463 ( .A(Op_MY[20]), .B(Op_MY[6]), .Y(n1077) );
OR2X2TS U3464 ( .A(Op_MY[21]), .B(Op_MY[7]), .Y(n1060) );
OR2X2TS U3465 ( .A(Op_MY[19]), .B(Op_MY[46]), .Y(n1120) );
NOR2X1TS U3466 ( .A(DP_OP_343J35_127_4270_n853), .B(n809), .Y(n7997) );
OR2X2TS U3467 ( .A(Op_MX[16]), .B(Op_MX[2]), .Y(n1012) );
NOR2X1TS U3468 ( .A(n1034), .B(n848), .Y(n5656) );
NOR2X1TS U3469 ( .A(n767), .B(n837), .Y(n5657) );
ADDHX2TS U3470 ( .A(Op_MX[40]), .B(Op_MX[27]), .CO(n2967), .S(n9659) );
NOR2XLTS U3471 ( .A(n852), .B(n766), .Y(n5831) );
OR2X2TS U3472 ( .A(Op_MY[51]), .B(Op_MY[24]), .Y(n916) );
NAND2BXLTS U3473 ( .AN(Op_MY[47]), .B(Op_MX[48]), .Y(n7053) );
OR2X2TS U3474 ( .A(Op_MY[18]), .B(Op_MY[4]), .Y(n1013) );
NOR2XLTS U3475 ( .A(n852), .B(n767), .Y(n5709) );
NOR2XLTS U3476 ( .A(n988), .B(n934), .Y(n5975) );
NOR2XLTS U3477 ( .A(n852), .B(n1034), .Y(n5814) );
NOR2XLTS U3478 ( .A(n934), .B(n772), .Y(n5798) );
NOR2X1TS U3479 ( .A(n847), .B(n766), .Y(n5688) );
NOR2X1TS U3480 ( .A(n1109), .B(n773), .Y(n5737) );
NOR2X1TS U3481 ( .A(n769), .B(n837), .Y(n5689) );
NOR2XLTS U3482 ( .A(n934), .B(DP_OP_346J35_130_4270_n829), .Y(n5847) );
NOR2X1TS U3483 ( .A(n853), .B(n773), .Y(n5745) );
NOR2X1TS U3484 ( .A(n1032), .B(DP_OP_346J35_130_4270_n829), .Y(n5770) );
NOR2XLTS U3485 ( .A(n852), .B(n769), .Y(n5818) );
NOR2XLTS U3486 ( .A(n934), .B(n773), .Y(n5742) );
NOR2X1TS U3487 ( .A(n1032), .B(n771), .Y(n5747) );
NOR2XLTS U3488 ( .A(n934), .B(n771), .Y(n5755) );
NOR2X1TS U3489 ( .A(n1032), .B(n773), .Y(n5739) );
ADDHX2TS U3490 ( .A(Op_MY[40]), .B(Op_MY[27]), .CO(n3004), .S(n7487) );
NOR2X1TS U3491 ( .A(n768), .B(n848), .Y(n5995) );
OR2X2TS U3492 ( .A(Op_MY[49]), .B(Op_MY[22]), .Y(n1038) );
NOR2X1TS U3493 ( .A(n820), .B(DP_OP_343J35_127_4270_n857), .Y(n7760) );
OR2X2TS U3494 ( .A(Op_MY[21]), .B(Op_MY[48]), .Y(n1147) );
NOR2XLTS U3495 ( .A(n852), .B(n768), .Y(n6026) );
NOR2X1TS U3496 ( .A(n768), .B(n837), .Y(n5720) );
NOR2X1TS U3497 ( .A(n766), .B(n848), .Y(n5721) );
NOR2X1TS U3498 ( .A(n767), .B(n848), .Y(n5670) );
NOR2X1TS U3499 ( .A(n770), .B(n837), .Y(n5671) );
NOR2XLTS U3500 ( .A(n852), .B(n770), .Y(n5981) );
NOR2X1TS U3501 ( .A(n769), .B(n848), .Y(n5651) );
NOR2X1TS U3502 ( .A(n766), .B(n837), .Y(n5652) );
NOR2X1TS U3503 ( .A(n838), .B(DP_OP_342J35_126_4270_n748), .Y(n7150) );
INVX4TS U3504 ( .A(n759), .Y(n881) );
NOR2X1TS U3505 ( .A(DP_OP_346J35_130_4270_n836), .B(n773), .Y(n5762) );
NOR2X1TS U3506 ( .A(n1026), .B(n771), .Y(n5761) );
XNOR2X1TS U3507 ( .A(Op_MY[51]), .B(Op_MX[48]), .Y(n7267) );
NOR2X1TS U3508 ( .A(n811), .B(n756), .Y(n7558) );
NOR2X2TS U3509 ( .A(Op_MX[32]), .B(Op_MX[5]), .Y(n1700) );
NOR2XLTS U3510 ( .A(n853), .B(DP_OP_346J35_130_4270_n829), .Y(n5788) );
NOR2X1TS U3511 ( .A(n812), .B(n757), .Y(n7542) );
NOR2X1TS U3512 ( .A(Op_MX[21]), .B(Op_MX[7]), .Y(n2486) );
NOR2X1TS U3513 ( .A(n810), .B(n756), .Y(n7543) );
NAND2X1TS U3514 ( .A(Op_MX[40]), .B(Op_MX[13]), .Y(n1707) );
OR2X2TS U3515 ( .A(Op_MX[18]), .B(Op_MX[4]), .Y(n1023) );
OR2X2TS U3516 ( .A(Op_MY[23]), .B(Op_MY[9]), .Y(n1124) );
OR2X2TS U3517 ( .A(Op_MX[40]), .B(Op_MX[13]), .Y(n1117) );
NOR2X1TS U3518 ( .A(n757), .B(n955), .Y(n7535) );
NOR2X1TS U3519 ( .A(n758), .B(n811), .Y(n7547) );
NOR2X1TS U3520 ( .A(n838), .B(n763), .Y(n7152) );
NOR2X1TS U3521 ( .A(n813), .B(n756), .Y(n7534) );
NOR2X1TS U3522 ( .A(n1026), .B(n773), .Y(n5751) );
NOR2X1TS U3523 ( .A(n1109), .B(DP_OP_346J35_130_4270_n829), .Y(n5766) );
NOR2XLTS U3524 ( .A(n1032), .B(n772), .Y(n5795) );
OR2X2TS U3525 ( .A(Op_MX[39]), .B(Op_MX[12]), .Y(n999) );
NOR2X1TS U3526 ( .A(n853), .B(n771), .Y(n5767) );
NOR2X1TS U3527 ( .A(n811), .B(n757), .Y(n7810) );
OR2X2TS U3528 ( .A(Op_MY[16]), .B(Op_MY[43]), .Y(n1114) );
OR2X2TS U3529 ( .A(Op_MY[25]), .B(Op_MY[11]), .Y(n1031) );
CLKINVX6TS U3530 ( .A(rst), .Y(n286) );
OAI22X2TS U3531 ( .A0(n5182), .A1(n2004), .B0(n1636), .B1(n1823), .Y(n2002)
);
OAI21X4TS U3532 ( .A0(n1482), .A1(n1265), .B0(n1264), .Y(n1463) );
INVX4TS U3533 ( .A(n1547), .Y(n5182) );
AFCSHCONX2TS U3534 ( .B(DP_OP_338J35_122_4684_n50), .A(
DP_OP_338J35_122_4684_n41), .CI0(DP_OP_338J35_122_4684_n12), .CI1(
DP_OP_338J35_122_4684_n11), .CS(DP_OP_338J35_122_4684_n15), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .CO0N(DP_OP_338J35_122_4684_n10), .CO1N(DP_OP_338J35_122_4684_n9) );
AOI21X4TS U3535 ( .A0(n1207), .A1(n10845), .B0(n9353), .Y(n10859) );
NAND2X2TS U3536 ( .A(n9347), .B(n9346), .Y(n10699) );
OAI21X2TS U3537 ( .A0(n8899), .A1(n8902), .B0(n8900), .Y(n8895) );
AFHCINX2TS U3538 ( .CIN(n5512), .B(n5513), .A(n5514), .S(n5597), .CO(n5509)
);
XNOR2X1TS U3539 ( .A(n8828), .B(n4874), .Y(n9125) );
ADDFHX4TS U3540 ( .A(n8911), .B(n8910), .CI(n8909), .CO(n8904), .S(n9171) );
ADDFHX4TS U3541 ( .A(n8955), .B(n8954), .CI(n8953), .CO(n8948), .S(n9189) );
XNOR2X4TS U3542 ( .A(n8790), .B(n8789), .Y(n9109) );
NAND2X2TS U3543 ( .A(n1072), .B(n4335), .Y(n4336) );
NOR2X2TS U3544 ( .A(n8841), .B(n8848), .Y(n5627) );
OR2X2TS U3545 ( .A(n4296), .B(n4295), .Y(n1014) );
NOR2X1TS U3546 ( .A(DP_OP_345J35_129_3436_n8), .B(DP_OP_345J35_129_3436_n5),
.Y(n1245) );
OAI22X1TS U3547 ( .A0(n2545), .A1(n2530), .B0(n2509), .B1(n2651), .Y(n2326)
);
AFHCINX4TS U3548 ( .CIN(n5518), .B(n5519), .A(n5520), .S(n5592), .CO(n5515)
);
OAI21X1TS U3549 ( .A0(n8852), .A1(n8848), .B0(n8849), .Y(n8845) );
OR2X4TS U3550 ( .A(n10878), .B(n10873), .Y(n1209) );
NAND2X4TS U3551 ( .A(n10817), .B(n9357), .Y(n10873) );
OAI21X1TS U3552 ( .A0(n3702), .A1(n3698), .B0(n3699), .Y(n3695) );
XNOR2X1TS U3553 ( .A(n3046), .B(n3395), .Y(n3389) );
INVX2TS U3554 ( .A(n3690), .Y(n3702) );
NAND2X1TS U3555 ( .A(n1518), .B(n1517), .Y(n1520) );
NAND2X2TS U3556 ( .A(n1182), .B(n10784), .Y(n10774) );
OAI21X1TS U3557 ( .A0(n5253), .A1(n5249), .B0(n5250), .Y(n5243) );
AOI21X4TS U3558 ( .A0(n824), .A1(n5040), .B0(n4872), .Y(n5049) );
NOR2X2TS U3559 ( .A(n4647), .B(n4672), .Y(n4160) );
INVX2TS U3560 ( .A(n4322), .Y(n4414) );
XNOR2X1TS U3561 ( .A(Op_MX[11]), .B(Op_MX[10]), .Y(n6353) );
NAND2X2TS U3562 ( .A(Op_MX[37]), .B(Op_MX[10]), .Y(n1641) );
INVX2TS U3563 ( .A(n5076), .Y(n5078) );
NOR2X4TS U3564 ( .A(n5085), .B(n5084), .Y(n5229) );
AFHCINX4TS U3565 ( .CIN(n1764), .B(n753), .A(n1765), .S(n1891), .CO(n1781)
);
ADDFHX4TS U3566 ( .A(n8855), .B(n8854), .CI(n8853), .CO(n8846), .S(n9144) );
ADDFHX2TS U3567 ( .A(n6629), .B(n6628), .CI(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[20]), .CO(n6622), .S(
n6801) );
AO21X4TS U3568 ( .A0(n836), .A1(n6914), .B0(n6803), .Y(n981) );
INVX2TS U3569 ( .A(n6913), .Y(n6803) );
OAI21X4TS U3570 ( .A0(n6896), .A1(n6899), .B0(n6897), .Y(n7015) );
AOI21X4TS U3571 ( .A0(n1054), .A1(n5271), .B0(n5039), .Y(n5254) );
NOR2X4TS U3572 ( .A(n4600), .B(n4599), .Y(n5021) );
NOR2X4TS U3573 ( .A(n9498), .B(n9504), .Y(n9402) );
NAND2X2TS U3574 ( .A(n1135), .B(n1136), .Y(n5063) );
NOR2X1TS U3575 ( .A(n2199), .B(n1389), .Y(n1345) );
OAI21X4TS U3576 ( .A0(n9373), .A1(n960), .B0(n9374), .Y(n9380) );
OR2X4TS U3577 ( .A(Op_MY[0]), .B(Op_MY[27]), .Y(n1158) );
NAND2X2TS U3578 ( .A(n1144), .B(n1602), .Y(n1604) );
ADDFHX4TS U3579 ( .A(n10458), .B(n10457), .CI(n10456), .CO(n10460), .S(
n10459) );
ADDFHX4TS U3580 ( .A(n10454), .B(n10453), .CI(n10452), .CO(n10456), .S(
n10455) );
ADDHX1TS U3581 ( .A(n4153), .B(n4152), .CO(n4158), .S(n4155) );
ADDFHX2TS U3582 ( .A(n9025), .B(n6681), .CI(n6680), .CO(n6673), .S(n6784) );
ADDFHX2TS U3583 ( .A(n10569), .B(n10568), .CI(n10567), .CO(n10571), .S(
n10570) );
NOR2X4TS U3584 ( .A(n5076), .B(n5075), .Y(n5095) );
AOI21X2TS U3585 ( .A0(n1014), .A1(n4369), .B0(n4297), .Y(n4374) );
NOR2X2TS U3586 ( .A(Op_MY[28]), .B(Op_MY[1]), .Y(n1516) );
ADDHX1TS U3587 ( .A(n1662), .B(n1661), .CO(n1711), .S(n1697) );
OAI21X4TS U3588 ( .A0(n5389), .A1(n5392), .B0(n5390), .Y(n5271) );
NOR2X1TS U3589 ( .A(n909), .B(n9419), .Y(n9421) );
OR2X2TS U3590 ( .A(n4321), .B(n4320), .Y(n1122) );
AOI21X2TS U3591 ( .A0(n1297), .A1(n1615), .B0(n1296), .Y(n1591) );
OAI21X1TS U3592 ( .A0(n1654), .A1(n1649), .B0(n1655), .Y(n1296) );
MXI2X4TS U3593 ( .A(DP_OP_345J35_129_3436_n10), .B(DP_OP_345J35_129_3436_n9),
.S0(DP_OP_345J35_129_3436_n15), .Y(DP_OP_345J35_129_3436_n8) );
NOR2X2TS U3594 ( .A(n4304), .B(n2174), .Y(n1896) );
INVX2TS U3595 ( .A(n4371), .Y(n4373) );
NAND2X2TS U3596 ( .A(n4373), .B(n4372), .Y(n4375) );
NOR2X2TS U3597 ( .A(n4299), .B(n4298), .Y(n4371) );
NAND2X1TS U3598 ( .A(n5391), .B(n5390), .Y(n5393) );
NAND2X2TS U3599 ( .A(n4321), .B(n4320), .Y(n4322) );
OAI21X1TS U3600 ( .A0(n4162), .A1(n4163), .B0(n4160), .Y(n4161) );
ADDHX1TS U3601 ( .A(n2188), .B(n2187), .CO(n2186), .S(n2192) );
OAI21X2TS U3602 ( .A0(n5007), .A1(n5015), .B0(n5008), .Y(n5040) );
OAI21X2TS U3603 ( .A0(n1491), .A1(n1497), .B0(n1492), .Y(n1483) );
AOI21X2TS U3604 ( .A0(n1483), .A1(n1076), .B0(n1263), .Y(n1264) );
NAND2X2TS U3605 ( .A(n8858), .B(n8857), .Y(n8860) );
MXI2X4TS U3606 ( .A(DP_OP_338J35_122_4684_n10), .B(DP_OP_338J35_122_4684_n9),
.S0(DP_OP_338J35_122_4684_n15), .Y(DP_OP_338J35_122_4684_n8) );
OAI22X2TS U3607 ( .A0(n5147), .A1(n1949), .B0(n2000), .B1(n1737), .Y(n1666)
);
OAI22X2TS U3608 ( .A0(n5147), .A1(n1947), .B0(n1822), .B1(n2000), .Y(n1712)
);
INVX6TS U3609 ( .A(n1626), .Y(n5147) );
AOI21X2TS U3610 ( .A0(n915), .A1(n1624), .B0(n1545), .Y(n1634) );
AOI21X1TS U3611 ( .A0(n1529), .A1(n1460), .B0(n1452), .Y(n1457) );
NAND2X2TS U3612 ( .A(n1484), .B(n1076), .Y(n1265) );
NOR2X4TS U3613 ( .A(n1300), .B(n1590), .Y(n1699) );
ADDHX1TS U3614 ( .A(n4150), .B(n4149), .CO(n4151), .S(n4148) );
ADDFHX2TS U3615 ( .A(n4423), .B(n4422), .CI(n4421), .CO(n4412), .S(n5291) );
AOI21X4TS U3616 ( .A0(n997), .A1(n1112), .B0(n5603), .Y(n8885) );
OAI21X4TS U3617 ( .A0(n10484), .A1(n10487), .B0(n10485), .Y(n9497) );
OAI21X4TS U3618 ( .A0(n8534), .A1(n8530), .B0(n8531), .Y(n8516) );
NAND2X2TS U3619 ( .A(n6898), .B(n6897), .Y(n6900) );
ADDFHX2TS U3620 ( .A(Op_MY[46]), .B(Op_MY[19]), .CI(n1496), .CO(n1488), .S(
n1532) );
ADDFHX2TS U3621 ( .A(Op_MY[42]), .B(Op_MY[15]), .CI(n1515), .CO(n1509), .S(
n1776) );
AOI21X4TS U3622 ( .A0(n5228), .A1(n5087), .B0(n5086), .Y(n5215) );
NAND2X2TS U3623 ( .A(n5506), .B(n5505), .Y(n5508) );
ADDFHX2TS U3624 ( .A(n4172), .B(n4171), .CI(n4170), .CO(n4197), .S(n4217) );
OAI21X2TS U3625 ( .A0(n1516), .A1(n1519), .B0(n1517), .Y(n1503) );
INVX2TS U3626 ( .A(n1503), .Y(n1514) );
OAI21X1TS U3627 ( .A0(n5099), .A1(n5075), .B0(n5074), .Y(n5080) );
CLKXOR2X2TS U3628 ( .A(n8886), .B(n8885), .Y(n9155) );
OR2X2TS U3629 ( .A(n5602), .B(n5601), .Y(n997) );
NOR2X4TS U3630 ( .A(Op_MY[32]), .B(Op_MY[5]), .Y(n1491) );
NAND2X2TS U3631 ( .A(n5605), .B(n5604), .Y(n8883) );
XNOR2X2TS U3632 ( .A(n8845), .B(n8844), .Y(n9137) );
OAI21X2TS U3633 ( .A0(n5215), .A1(n5116), .B0(n5115), .Y(n5203) );
XOR2X4TS U3634 ( .A(n5503), .B(n998), .Y(n5605) );
XNOR2X2TS U3635 ( .A(n5080), .B(n5079), .Y(n5085) );
ADDFHX4TS U3636 ( .A(n8835), .B(n8834), .CI(n8833), .CO(n8829), .S(n9132) );
XOR2X2TS U3637 ( .A(n2932), .B(n2931), .Y(n6570) );
AOI21X2TS U3638 ( .A0(n1068), .A1(n6568), .B0(n2855), .Y(n2931) );
AOI21X4TS U3639 ( .A0(n1075), .A1(n9380), .B0(n9113), .Y(n9395) );
NOR2X2TS U3640 ( .A(n2857), .B(n2856), .Y(n2928) );
AOI21X4TS U3641 ( .A0(n6902), .A1(n980), .B0(n6828), .Y(n6899) );
ADDFHX2TS U3642 ( .A(n2029), .B(n2028), .CI(n2027), .CO(n2088), .S(n2042) );
ADDFHX2TS U3643 ( .A(n2020), .B(n2019), .CI(n2018), .CO(n2037), .S(n2027) );
ADDFHX2TS U3644 ( .A(n1981), .B(n1980), .CI(n1979), .CO(n2018), .S(n2030) );
NAND2X4TS U3645 ( .A(n1177), .B(n10693), .Y(n10832) );
ADDFHX2TS U3646 ( .A(Op_MY[23]), .B(Op_MY[50]), .CI(n1478), .CO(n1472), .S(
n1774) );
AFHCINX4TS U3647 ( .CIN(n10887), .B(n10888), .A(n10889), .S(n10890), .CO(
n10894) );
OAI21X2TS U3648 ( .A0(n5099), .A1(n4889), .B0(n4888), .Y(n5088) );
AOI21X4TS U3649 ( .A0(n5096), .A1(n1160), .B0(n4887), .Y(n4888) );
OAI21X4TS U3650 ( .A0(n4797), .A1(n4800), .B0(n4798), .Y(n4792) );
AOI21X2TS U3651 ( .A0(n1134), .A1(n4808), .B0(n4747), .Y(n4800) );
OA21X4TS U3652 ( .A0(n9367), .A1(n1176), .B0(n9368), .Y(n960) );
OA21X4TS U3653 ( .A0(n9362), .A1(n9365), .B0(n9363), .Y(n1176) );
BUFX20TS U3654 ( .A(n9490), .Y(n909) );
AOI21X4TS U3655 ( .A0(n9497), .A1(n9402), .B0(n9401), .Y(n9490) );
AOI21X4TS U3656 ( .A0(n5607), .A1(n963), .B0(n5413), .Y(n5498) );
OA21X4TS U3657 ( .A0(n5504), .A1(n5507), .B0(n5505), .Y(n998) );
NOR2X2TS U3658 ( .A(n5395), .B(n5394), .Y(n5504) );
OAI21X2TS U3659 ( .A0(n5248), .A1(n5244), .B0(n5245), .Y(n5233) );
NAND2X4TS U3660 ( .A(Op_MY[0]), .B(Op_MY[27]), .Y(n1519) );
ADDFHX2TS U3661 ( .A(n2040), .B(n2039), .CI(n2038), .CO(n10240), .S(n2103)
);
ADDFHX2TS U3662 ( .A(n2037), .B(n2036), .CI(n2035), .CO(n2039), .S(n2086) );
AO21X4TS U3663 ( .A0(n1029), .A1(n1828), .B0(n1534), .Y(n1042) );
OA21X4TS U3664 ( .A0(n1209), .A1(n10811), .B0(n9361), .Y(n10887) );
OA21X4TS U3665 ( .A0(n10878), .A1(n10874), .B0(n10879), .Y(n9361) );
OA21X4TS U3666 ( .A0(n1607), .A1(n1610), .B0(n1608), .Y(n802) );
AOI21X4TS U3667 ( .A0(n1146), .A1(n1042), .B0(n1536), .Y(n1684) );
OAI21X2TS U3668 ( .A0(n5099), .A1(n5098), .B0(n5097), .Y(n5102) );
MX2X4TS U3669 ( .A(DP_OP_338J35_122_4684_n17), .B(DP_OP_338J35_122_4684_n16),
.S0(DP_OP_338J35_122_4684_n20), .Y(DP_OP_338J35_122_4684_n15) );
OAI22X1TS U3670 ( .A0(n1822), .A1(n1810), .B0(n2000), .B1(n1947), .Y(n1662)
);
ADDFHX2TS U3671 ( .A(n1670), .B(n1669), .CI(n1668), .CO(n1738), .S(n1725) );
OAI22X1TS U3672 ( .A0(n2004), .A1(n1810), .B0(n1823), .B1(n2000), .Y(n1670)
);
OAI21X2TS U3673 ( .A0(n4374), .A1(n4371), .B0(n4372), .Y(n4376) );
INVX2TS U3674 ( .A(n10666), .Y(n8888) );
INVX2TS U3675 ( .A(n10584), .Y(n8831) );
NAND2X2TS U3676 ( .A(n6906), .B(n6905), .Y(n6908) );
INVX2TS U3677 ( .A(n6904), .Y(n6906) );
ADDHXLTS U3678 ( .A(n7763), .B(n7762), .CO(n7732), .S(n7783) );
OAI22X1TS U3679 ( .A0(n7900), .A1(n8036), .B0(n7910), .B1(n8081), .Y(n7762)
);
OAI22X1TS U3680 ( .A0(n5148), .A1(n1810), .B0(n2005), .B1(n2000), .Y(n1740)
);
NAND2X1TS U3681 ( .A(n5131), .B(n5170), .Y(n5132) );
INVX2TS U3682 ( .A(n5386), .Y(n3817) );
INVX2TS U3683 ( .A(n9749), .Y(DP_OP_344J35_128_4078_n155) );
INVX2TS U3684 ( .A(n9752), .Y(DP_OP_344J35_128_4078_n158) );
INVX2TS U3685 ( .A(n10641), .Y(n8925) );
INVX2TS U3686 ( .A(n10658), .Y(n8898) );
INVX2TS U3687 ( .A(n10564), .Y(n8812) );
INVX2TS U3688 ( .A(n10608), .Y(n8839) );
AFHCONX2TS U3689 ( .A(n8540), .B(n8539), .CI(n8538), .CON(n8536), .S(n10674)
);
OAI21XLTS U3690 ( .A0(n9263), .A1(n9277), .B0(n9262), .Y(n9264) );
AOI21X1TS U3691 ( .A0(n1137), .A1(n3073), .B0(n3048), .Y(n3049) );
OAI22X1TS U3692 ( .A0(n3349), .A1(n3478), .B0(n3256), .B1(n3560), .Y(n3163)
);
ADDFHX2TS U3693 ( .A(n10289), .B(n10288), .CI(n10287), .CO(n10275), .S(
n10290) );
NOR2X1TS U3694 ( .A(n7910), .B(n8096), .Y(n7734) );
OAI22X1TS U3695 ( .A0(n3447), .A1(n3350), .B0(n3399), .B1(n3398), .Y(n3135)
);
OAI22X1TS U3696 ( .A0(n3118), .A1(n3483), .B0(n3555), .B1(n1570), .Y(n3117)
);
NOR2XLTS U3697 ( .A(n9682), .B(n9651), .Y(n9673) );
OAI21X1TS U3698 ( .A0(n5480), .A1(n5173), .B0(n5172), .Y(n5184) );
INVX2TS U3699 ( .A(n9541), .Y(n9653) );
INVX2TS U3700 ( .A(n7440), .Y(n9664) );
INVX2TS U3701 ( .A(n7495), .Y(n9685) );
INVX2TS U3702 ( .A(n7493), .Y(n9686) );
OAI21X2TS U3703 ( .A0(n5313), .A1(n5310), .B0(n5311), .Y(n3743) );
NAND2X1TS U3704 ( .A(n3788), .B(n3787), .Y(n3801) );
OAI21X1TS U3705 ( .A0(n5239), .A1(n5250), .B0(n5240), .Y(n3868) );
OAI32X1TS U3706 ( .A0(n9592), .A1(n7486), .A2(n9599), .B0(n9597), .B1(n9592),
.Y(n3012) );
INVX2TS U3707 ( .A(n9750), .Y(DP_OP_344J35_128_4078_n156) );
INVX2TS U3708 ( .A(n9753), .Y(DP_OP_344J35_128_4078_n159) );
INVX2TS U3709 ( .A(n10646), .Y(n8919) );
XNOR2X1TS U3710 ( .A(n5578), .B(n5577), .Y(n9008) );
OAI21XLTS U3711 ( .A0(n5576), .A1(n5575), .B0(n5580), .Y(n5577) );
INVX2TS U3712 ( .A(n10674), .Y(n8875) );
INVX2TS U3713 ( .A(n10592), .Y(n8819) );
INVX2TS U3714 ( .A(n10604), .Y(n8847) );
NOR2X4TS U3715 ( .A(n5623), .B(n5622), .Y(n8848) );
INVX2TS U3716 ( .A(n8679), .Y(n8463) );
NAND2X2TS U3717 ( .A(n8884), .B(n8883), .Y(n8886) );
INVX2TS U3718 ( .A(n8882), .Y(n8884) );
INVX2TS U3719 ( .A(n9394), .Y(n8780) );
XNOR2X1TS U3720 ( .A(n6966), .B(n6965), .Y(n8603) );
INVX2TS U3721 ( .A(n10820), .Y(n9315) );
INVX2TS U3722 ( .A(n10474), .Y(n9384) );
NOR2X4TS U3723 ( .A(n9386), .B(n9385), .Y(n10484) );
NAND2X2TS U3724 ( .A(n9378), .B(n9377), .Y(n10479) );
OAI21XLTS U3725 ( .A0(n9248), .A1(n9277), .B0(n9247), .Y(n9249) );
OAI22X1TS U3726 ( .A0(n10247), .A1(n10203), .B0(n10245), .B1(n10186), .Y(
n10210) );
NOR2X1TS U3727 ( .A(n10239), .B(n10186), .Y(n10179) );
OAI22X1TS U3728 ( .A0(n10247), .A1(n10186), .B0(n10245), .B1(n10189), .Y(
n10180) );
OAI22X1TS U3729 ( .A0(n1822), .A1(n1730), .B0(n1947), .B1(n1810), .Y(n1722)
);
OAI22X1TS U3730 ( .A0(n2000), .A1(n1949), .B0(n1810), .B1(n1737), .Y(n1723)
);
OAI22X1TS U3731 ( .A0(n3497), .A1(n3350), .B0(n3427), .B1(n3398), .Y(n3162)
);
OAI22X1TS U3732 ( .A0(n10247), .A1(n10246), .B0(n10245), .B1(n10244), .Y(
n10283) );
OAI22X1TS U3733 ( .A0(n8083), .A1(n7944), .B0(n8050), .B1(n7905), .Y(n7793)
);
OAI22X1TS U3734 ( .A0(n8050), .A1(n7847), .B0(n8017), .B1(n8018), .Y(n7794)
);
OAI22X1TS U3735 ( .A0(n8083), .A1(n7909), .B0(n8050), .B1(n7908), .Y(n7823)
);
OAI21X1TS U3736 ( .A0(n1704), .A1(n1703), .B0(n1702), .Y(n1705) );
ADDFHX2TS U3737 ( .A(n10269), .B(n10268), .CI(n10267), .CO(n10294), .S(
n10298) );
NOR2X1TS U3738 ( .A(n3497), .B(n805), .Y(n3565) );
OAI22X1TS U3739 ( .A0(n5182), .A1(n1949), .B0(n5147), .B1(n1737), .Y(n1715)
);
NOR2X1TS U3740 ( .A(n5182), .B(n1713), .Y(n1717) );
OAI22X1TS U3741 ( .A0(n8093), .A1(n7910), .B0(n8082), .B1(n7900), .Y(n7764)
);
OAI22X1TS U3742 ( .A0(n3497), .A1(n3257), .B0(n3427), .B1(n3350), .Y(n3149)
);
OAI22X1TS U3743 ( .A0(n3497), .A1(n3278), .B0(n3427), .B1(n3257), .Y(n3224)
);
OAI22X1TS U3744 ( .A0(n3364), .A1(n3350), .B0(n3354), .B1(n3398), .Y(n3225)
);
OAI22X1TS U3745 ( .A0(n3258), .A1(n3350), .B0(n3279), .B1(n3398), .Y(n3267)
);
ADDFHX2TS U3746 ( .A(n2120), .B(n2119), .CI(n2118), .CO(n10296), .S(n2134)
);
OAI22X1TS U3747 ( .A0(n3342), .A1(n3346), .B0(n879), .B1(n3345), .Y(n3370)
);
NOR2X1TS U3748 ( .A(n3691), .B(n3698), .Y(n3340) );
OAI21X1TS U3749 ( .A0(n3691), .A1(n3699), .B0(n3692), .Y(n3339) );
ADDFHX2TS U3750 ( .A(n1736), .B(n1735), .CI(n1734), .CO(n1812), .S(n1745) );
OAI22X1TS U3751 ( .A0(n5177), .A1(n1730), .B0(n5149), .B1(n1810), .Y(n1734)
);
OAI22X1TS U3752 ( .A0(n5182), .A1(n1947), .B0(n5147), .B1(n1822), .Y(n1736)
);
NAND2X2TS U3753 ( .A(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .B(n4886), .Y(n5100) );
NOR2X4TS U3754 ( .A(n5119), .B(n995), .Y(n5401) );
NAND2X2TS U3755 ( .A(n5119), .B(n995), .Y(n5402) );
INVX2TS U3756 ( .A(n3680), .Y(n3825) );
BUFX3TS U3757 ( .A(n2973), .Y(n9588) );
ADDHXLTS U3758 ( .A(n10410), .B(n10409), .CO(DP_OP_347J35_131_5122_n70), .S(
DP_OP_347J35_131_5122_n71) );
ADDHX1TS U3759 ( .A(n3038), .B(n3037), .CO(n3099), .S(n3043) );
NOR2XLTS U3760 ( .A(n9664), .B(n9652), .Y(DP_OP_341J35_125_6458_n199) );
INVX2TS U3761 ( .A(n7445), .Y(n9663) );
INVX2TS U3762 ( .A(n9531), .Y(n9667) );
INVX2TS U3763 ( .A(n9520), .Y(n9662) );
INVX2TS U3764 ( .A(n9524), .Y(n9650) );
ADDHXLTS U3765 ( .A(n9690), .B(n9689), .CO(DP_OP_341J35_125_6458_n119), .S(
DP_OP_341J35_125_6458_n120) );
INVX2TS U3766 ( .A(n9539), .Y(n9681) );
INVX2TS U3767 ( .A(n9556), .Y(n9651) );
NAND2X2TS U3768 ( .A(n7432), .B(n7446), .Y(n9601) );
INVX4TS U3769 ( .A(n7432), .Y(n9607) );
BUFX3TS U3770 ( .A(n7447), .Y(n9615) );
OAI21X1TS U3771 ( .A0(n5480), .A1(n5458), .B0(n5457), .Y(n5465) );
INVX2TS U3772 ( .A(n7442), .Y(n9668) );
INVX2TS U3773 ( .A(n7433), .Y(n9666) );
BUFX3TS U3774 ( .A(n2981), .Y(n9599) );
AOI21X1TS U3775 ( .A0(n3806), .A1(n3784), .B0(n3783), .Y(n3785) );
AOI21X1TS U3776 ( .A0(n3806), .A1(n3805), .B0(n3804), .Y(n3807) );
NOR2X1TS U3777 ( .A(n3744), .B(n3749), .Y(n3723) );
NAND2X1TS U3778 ( .A(n3705), .B(n3704), .Y(n3707) );
INVX2TS U3779 ( .A(n3703), .Y(n3705) );
INVX2TS U3780 ( .A(n5436), .Y(n5210) );
NOR2X4TS U3781 ( .A(n5083), .B(n829), .Y(n5244) );
NAND2X1TS U3782 ( .A(n5231), .B(n5230), .Y(n5232) );
CMPR42X1TS U3783 ( .A(DP_OP_344J35_128_4078_n122), .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[6]), .C(DP_OP_344J35_128_4078_n65), .D(DP_OP_344J35_128_4078_n148), .ICI(
DP_OP_344J35_128_4078_n66), .S(DP_OP_344J35_128_4078_n64), .ICO(
DP_OP_344J35_128_4078_n62), .CO(DP_OP_344J35_128_4078_n63) );
INVX2TS U3784 ( .A(n9743), .Y(DP_OP_344J35_128_4078_n148) );
NOR2XLTS U3785 ( .A(n10420), .B(n10393), .Y(DP_OP_347J35_131_5122_n149) );
BUFX3TS U3786 ( .A(n6353), .Y(n10317) );
BUFX3TS U3787 ( .A(n6355), .Y(n10383) );
INVX2TS U3788 ( .A(n6380), .Y(n10408) );
INVX2TS U3789 ( .A(n6383), .Y(n10428) );
INVX2TS U3790 ( .A(n6385), .Y(n10420) );
INVX2TS U3791 ( .A(n6381), .Y(n10425) );
XOR2X1TS U3792 ( .A(n5438), .B(n5237), .Y(n8988) );
OAI21X1TS U3793 ( .A0(n5438), .A1(n5234), .B0(n5235), .Y(n5227) );
INVX2TS U3794 ( .A(n9751), .Y(DP_OP_344J35_128_4078_n157) );
INVX2TS U3795 ( .A(n9754), .Y(DP_OP_344J35_128_4078_n160) );
INVX2TS U3796 ( .A(n9732), .Y(DP_OP_344J35_128_4078_n126) );
NOR2XLTS U3797 ( .A(n10412), .B(n10426), .Y(n10396) );
NOR2XLTS U3798 ( .A(n10421), .B(n10393), .Y(n10394) );
ADDHXLTS U3799 ( .A(n10382), .B(n10381), .CO(DP_OP_347J35_131_5122_n119),
.S(DP_OP_347J35_131_5122_n120) );
INVX2TS U3800 ( .A(n10331), .Y(n10421) );
INVX2TS U3801 ( .A(n10327), .Y(n10419) );
INVX2TS U3802 ( .A(n10329), .Y(n10411) );
NAND2X2TS U3803 ( .A(n1061), .B(n5278), .Y(n5280) );
NOR2X2TS U3804 ( .A(n8301), .B(n914), .Y(n8453) );
INVX2TS U3805 ( .A(n10654), .Y(n8905) );
INVX2TS U3806 ( .A(n8889), .Y(n5603) );
INVX2TS U3807 ( .A(n10633), .Y(n8937) );
INVX2TS U3808 ( .A(n10466), .Y(n8965) );
XNOR2X1TS U3809 ( .A(n5573), .B(n5572), .Y(n9002) );
NAND2X1TS U3810 ( .A(n1096), .B(n5571), .Y(n5573) );
INVX2TS U3811 ( .A(n10588), .Y(n8824) );
NAND2X4TS U3812 ( .A(n5618), .B(n5617), .Y(n8863) );
OAI21X2TS U3813 ( .A0(n8869), .A1(n8872), .B0(n8870), .Y(n8865) );
OR2X6TS U3814 ( .A(n5618), .B(n5617), .Y(n1141) );
NAND2X1TS U3815 ( .A(n1040), .B(n6922), .Y(n6924) );
NAND2X1TS U3816 ( .A(n9369), .B(n9368), .Y(n9370) );
INVX2TS U3817 ( .A(n9367), .Y(n9369) );
NOR2X1TS U3818 ( .A(n9388), .B(n1125), .Y(n8832) );
NOR2X2TS U3819 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[25]), .B(
n9750), .Y(n8694) );
XOR2X1TS U3820 ( .A(n8717), .B(n8700), .Y(n9447) );
NAND2X1TS U3821 ( .A(n8699), .B(n8701), .Y(n8700) );
NAND2X1TS U3822 ( .A(n945), .B(n6911), .Y(n6912) );
NAND2X2TS U3823 ( .A(n8527), .B(n8526), .Y(n8529) );
INVX2TS U3824 ( .A(n8525), .Y(n8527) );
NAND2X1TS U3825 ( .A(n840), .B(n6960), .Y(n6963) );
NAND2X1TS U3826 ( .A(n9364), .B(n9363), .Y(n9366) );
INVX2TS U3827 ( .A(n9362), .Y(n9364) );
NAND2X1TS U3828 ( .A(n8685), .B(n8684), .Y(n8686) );
NAND2X1TS U3829 ( .A(n1215), .B(n8679), .Y(n8680) );
OAI21X1TS U3830 ( .A0(n8717), .A1(n8702), .B0(n8701), .Y(n8707) );
INVX2TS U3831 ( .A(n9497), .Y(n9508) );
NAND2X4TS U3832 ( .A(n9399), .B(n9398), .Y(n9505) );
OAI21XLTS U3833 ( .A0(n9242), .A1(n9277), .B0(n9241), .Y(n9243) );
INVX2TS U3834 ( .A(n10121), .Y(n10142) );
INVX2TS U3835 ( .A(n6865), .Y(n2555) );
INVX2TS U3836 ( .A(n6866), .Y(n2554) );
ADDFX2TS U3837 ( .A(n2014), .B(n2013), .CI(n2012), .CO(n10168), .S(n2017) );
INVX2TS U3838 ( .A(n3906), .Y(n2012) );
INVX2TS U3839 ( .A(n3905), .Y(n2014) );
INVX2TS U3840 ( .A(n5129), .Y(n10126) );
INVX2TS U3841 ( .A(n5130), .Y(n10125) );
INVX2TS U3842 ( .A(n10123), .Y(n10164) );
INVX2TS U3843 ( .A(n10124), .Y(n10163) );
ADDFX2TS U3844 ( .A(n10145), .B(n10144), .CI(n10143), .CO(n10155), .S(n10170) );
OAI22X1TS U3845 ( .A0(n10191), .A1(n10165), .B0(n10189), .B1(n10166), .Y(
n10143) );
ADDHXLTS U3846 ( .A(n2062), .B(n2061), .CO(n4275), .S(n2059) );
INVX2TS U3847 ( .A(DP_OP_338J35_122_4684_n1459), .Y(n4617) );
INVX2TS U3848 ( .A(DP_OP_338J35_122_4684_n1458), .Y(n4616) );
ADDHXLTS U3849 ( .A(n4609), .B(n4608), .CO(n4615), .S(n4619) );
INVX2TS U3850 ( .A(DP_OP_338J35_122_4684_n1461), .Y(n4609) );
ADDHXLTS U3851 ( .A(n4607), .B(n4606), .CO(n4610), .S(n4623) );
INVX2TS U3852 ( .A(DP_OP_338J35_122_4684_n1457), .Y(n4607) );
INVX2TS U3853 ( .A(DP_OP_338J35_122_4684_n1456), .Y(n4606) );
ADDHXLTS U3854 ( .A(n5813), .B(n5812), .CO(n5826), .S(n5809) );
ADDFX2TS U3855 ( .A(n10136), .B(n10135), .CI(n10134), .CO(n10139), .S(n10145) );
INVX2TS U3856 ( .A(n10119), .Y(n10136) );
INVX2TS U3857 ( .A(n10120), .Y(n10135) );
INVX2TS U3858 ( .A(n6868), .Y(n2661) );
INVX2TS U3859 ( .A(n6867), .Y(n2662) );
INVX2TS U3860 ( .A(n6870), .Y(n9886) );
INVX2TS U3861 ( .A(n6869), .Y(n9887) );
OAI22X1TS U3862 ( .A0(n10196), .A1(n10203), .B0(n10195), .B1(n10186), .Y(
n10193) );
OAI22X1TS U3863 ( .A0(n10191), .A1(n10187), .B0(n10189), .B1(n10185), .Y(
n10194) );
ADDFX2TS U3864 ( .A(n10172), .B(n10171), .CI(n10170), .CO(n10153), .S(n10211) );
OAI22X1TS U3865 ( .A0(n10196), .A1(n10186), .B0(n10195), .B1(n10189), .Y(
n10172) );
ADDFX2TS U3866 ( .A(n1826), .B(n1825), .CI(n1824), .CO(n2016), .S(n2023) );
INVX2TS U3867 ( .A(n3904), .Y(n1825) );
ADDHX1TS U3868 ( .A(n1909), .B(n1858), .CO(n1853), .S(n1859) );
OAI22X1TS U3869 ( .A0(n10203), .A1(n10187), .B0(n10185), .B1(n10244), .Y(
n2015) );
ADDFX2TS U3870 ( .A(n10169), .B(n10168), .CI(n10167), .CO(n10200), .S(n10222) );
OAI22X1TS U3871 ( .A0(n10166), .A1(n10203), .B0(n10186), .B1(n10165), .Y(
n10201) );
OAI22X1TS U3872 ( .A0(n10189), .A1(n10187), .B0(n10186), .B1(n10185), .Y(
n10219) );
OAI22X1TS U3873 ( .A0(n10191), .A1(n10190), .B0(n10189), .B1(n10188), .Y(
n10218) );
INVX2TS U3874 ( .A(n6849), .Y(n2560) );
OAI22X1TS U3875 ( .A0(n10247), .A1(n10244), .B0(n10245), .B1(n10203), .Y(
n10231) );
NOR2X1TS U3876 ( .A(n4308), .B(n4396), .Y(n4274) );
NOR2X1TS U3877 ( .A(n4273), .B(n4445), .Y(n4276) );
ADDHXLTS U3878 ( .A(n1923), .B(n1922), .CO(n2060), .S(n1926) );
ADDHX1TS U3879 ( .A(n1664), .B(n1663), .CO(n1661), .S(n1721) );
OAI22X1TS U3880 ( .A0(n4911), .A1(n4649), .B0(n4648), .B1(n4756), .Y(n4624)
);
INVX2TS U3881 ( .A(DP_OP_338J35_122_4684_n1460), .Y(n4620) );
INVX2TS U3882 ( .A(DP_OP_338J35_122_4684_n1455), .Y(n4612) );
INVX2TS U3883 ( .A(DP_OP_338J35_122_4684_n1454), .Y(n4611) );
OAI22X1TS U3884 ( .A0(n9945), .A1(n9946), .B0(n9944), .B1(n9961), .Y(n9941)
);
OAI22X1TS U3885 ( .A0(n6082), .A1(n5946), .B0(n5941), .B1(n6059), .Y(n5827)
);
OAI22X1TS U3886 ( .A0(n10196), .A1(n10189), .B0(n10195), .B1(n10191), .Y(
n10137) );
NOR2X1TS U3887 ( .A(n10196), .B(n10191), .Y(n10132) );
NOR2XLTS U3888 ( .A(n10239), .B(n10189), .Y(n10147) );
OAI22X1TS U3889 ( .A0(n10247), .A1(n10189), .B0(n10245), .B1(n10191), .Y(
n10148) );
INVX2TS U3890 ( .A(DP_OP_338J35_122_4684_n1462), .Y(n4545) );
OAI22X1TS U3891 ( .A0(n9944), .A1(n9994), .B0(n9946), .B1(n9991), .Y(n2607)
);
OAI22X1TS U3892 ( .A0(n9961), .A1(n9947), .B0(n9948), .B1(n9991), .Y(n2608)
);
OAI22X1TS U3893 ( .A0(n9944), .A1(n9991), .B0(n9946), .B1(n9961), .Y(n2610)
);
INVX2TS U3894 ( .A(n9885), .Y(n9925) );
INVX2TS U3895 ( .A(n9884), .Y(n9926) );
ADDHXLTS U3896 ( .A(n1914), .B(n1913), .CO(n1922), .S(n1911) );
OAI22X1TS U3897 ( .A0(n5993), .A1(n5978), .B0(n6040), .B1(n5888), .Y(n5711)
);
INVX2TS U3898 ( .A(n3899), .Y(n1934) );
NAND2X1TS U3899 ( .A(n3097), .B(n1533), .Y(n1827) );
OAI22X1TS U3900 ( .A0(n10188), .A1(n10246), .B0(n10190), .B1(n10244), .Y(
n2019) );
ADDFX2TS U3901 ( .A(n2023), .B(n2022), .CI(n2021), .CO(n2026), .S(n2036) );
OAI22X1TS U3902 ( .A0(n10185), .A1(n10246), .B0(n10187), .B1(n10244), .Y(
n2022) );
OAI22X1TS U3903 ( .A0(n10203), .A1(n10190), .B0(n10188), .B1(n10244), .Y(
n2021) );
OAI22X1TS U3904 ( .A0(n10166), .A1(n10244), .B0(n10165), .B1(n10203), .Y(
n10198) );
OAI22X1TS U3905 ( .A0(n10186), .A1(n10187), .B0(n10203), .B1(n10185), .Y(
n10199) );
OAI22X1TS U3906 ( .A0(n10186), .A1(n10190), .B0(n10203), .B1(n10188), .Y(
n2024) );
OAI22X1TS U3907 ( .A0(n10189), .A1(n10190), .B0(n10186), .B1(n10188), .Y(
n10223) );
OAI22X1TS U3908 ( .A0(n10196), .A1(n10244), .B0(n10195), .B1(n10203), .Y(
n10238) );
ADDFX2TS U3909 ( .A(n10250), .B(n10249), .CI(n10248), .CO(n10263), .S(n10282) );
INVX2TS U3910 ( .A(n6850), .Y(n2566) );
XNOR2X1TS U3911 ( .A(n10133), .B(n10132), .Y(n10158) );
ADDFX2TS U3912 ( .A(n10206), .B(n10205), .CI(n10204), .CO(n10209), .S(n10215) );
INVX2TS U3913 ( .A(n10173), .Y(n10205) );
OAI22X1TS U3914 ( .A0(n3581), .A1(n3257), .B0(n3559), .B1(n3350), .Y(n3380)
);
OAI22X1TS U3915 ( .A0(n3447), .A1(n3446), .B0(n3399), .B1(n3478), .Y(n3379)
);
NAND2X1TS U3916 ( .A(n3051), .B(n1530), .Y(n1780) );
NOR2X1TS U3917 ( .A(n4592), .B(n2081), .Y(n2056) );
NOR2X1TS U3918 ( .A(n4592), .B(n2082), .Y(n4279) );
NOR2X1TS U3919 ( .A(n4308), .B(n4445), .Y(n4311) );
OAI22X1TS U3920 ( .A0(n6082), .A1(n5941), .B0(n6059), .B1(n5888), .Y(n5715)
);
NOR2X1TS U3921 ( .A(n4273), .B(n4304), .Y(n1924) );
NOR2X1TS U3922 ( .A(n4445), .B(n2081), .Y(n1925) );
OAI22X1TS U3923 ( .A0(n3548), .A1(n3398), .B0(n3484), .B1(n3446), .Y(n3359)
);
OAI22X1TS U3924 ( .A0(n3447), .A1(n3478), .B0(n3399), .B1(n3560), .Y(n3360)
);
OAI22X1TS U3925 ( .A0(n3581), .A1(n3398), .B0(n3559), .B1(n3446), .Y(n3445)
);
OAI22X1TS U3926 ( .A0(n3447), .A1(n3560), .B0(n3399), .B1(n805), .Y(n3444)
);
XNOR2X1TS U3927 ( .A(n4480), .B(Op_MY[25]), .Y(n4189) );
NOR2X1TS U3928 ( .A(n4605), .B(n4648), .Y(n4766) );
OAI22X1TS U3929 ( .A0(n4943), .A1(n4771), .B0(n4605), .B1(n4643), .Y(n4765)
);
NOR2X1TS U3930 ( .A(n4605), .B(n4627), .Y(n4657) );
OAI22X1TS U3931 ( .A0(n4900), .A1(n4688), .B0(n4772), .B1(n4756), .Y(n4660)
);
OAI22X1TS U3932 ( .A0(n4943), .A1(n4649), .B0(n4911), .B1(n4648), .Y(n4661)
);
NAND2X1TS U3933 ( .A(n3081), .B(n1535), .Y(n1849) );
INVX2TS U3934 ( .A(n1827), .Y(n1534) );
ADDHXLTS U3935 ( .A(n1799), .B(n3343), .CO(n1645), .S(n1646) );
OAI22X1TS U3936 ( .A0(n4943), .A1(n4628), .B0(n4911), .B1(n4627), .Y(n4635)
);
OAI22X1TS U3937 ( .A0(n4943), .A1(n4630), .B0(n4605), .B1(n4629), .Y(n4634)
);
OAI22X1TS U3938 ( .A0(n4771), .A1(n4688), .B0(n4643), .B1(n4756), .Y(n4652)
);
NOR2X1TS U3939 ( .A(n4605), .B(n4647), .Y(n4650) );
OAI22X1TS U3940 ( .A0(n4771), .A1(n4672), .B0(n4643), .B1(n4688), .Y(n4641)
);
OAI22X1TS U3941 ( .A0(n4648), .A1(n4688), .B0(n4649), .B1(n4756), .Y(n4645)
);
INVX2TS U3942 ( .A(DP_OP_338J35_122_4684_n1453), .Y(n4770) );
INVX2TS U3943 ( .A(DP_OP_338J35_122_4684_n1452), .Y(n4769) );
NOR2X1TS U3944 ( .A(n4605), .B(n4771), .Y(n4902) );
OAI22X1TS U3945 ( .A0(n4900), .A1(n4943), .B0(n4772), .B1(n4605), .Y(n4901)
);
INVX2TS U3946 ( .A(n6847), .Y(n2553) );
ADDHX1TS U3947 ( .A(Op_MY[13]), .B(n2422), .CO(n2423), .S(n2264) );
ADDHXLTS U3948 ( .A(n2641), .B(n2640), .CO(n2833), .S(n2638) );
INVX2TS U3949 ( .A(n6845), .Y(n2343) );
OAI22X1TS U3950 ( .A0(n9945), .A1(n9947), .B0(n9961), .B1(n9948), .Y(n2665)
);
OAI22X1TS U3951 ( .A0(n9929), .A1(n9991), .B0(n9928), .B1(n9961), .Y(n9953)
);
OAI22X1TS U3952 ( .A0(n9949), .A1(n9927), .B0(n849), .B1(n2797), .Y(n9976)
);
OAI22X1TS U3953 ( .A0(n9949), .A1(n9947), .B0(n9945), .B1(n9948), .Y(n9977)
);
OAI22X1TS U3954 ( .A0(n9949), .A1(n9948), .B0(n849), .B1(n9947), .Y(n9979)
);
OAI22X1TS U3955 ( .A0(n9949), .A1(n9946), .B0(n9945), .B1(n9944), .Y(n9980)
);
OAI22X1TS U3956 ( .A0(n9949), .A1(n9944), .B0(n849), .B1(n9946), .Y(n9938)
);
OAI22X1TS U3957 ( .A0(n9929), .A1(n9961), .B0(n9928), .B1(n9945), .Y(n9956)
);
INVX2TS U3958 ( .A(n3062), .Y(n3095) );
ADDHX1TS U3959 ( .A(n3143), .B(n3142), .CO(n3164), .S(n3137) );
ADDHXLTS U3960 ( .A(n3391), .B(n3347), .CO(n3122), .S(n3123) );
OAI22X1TS U3961 ( .A0(n3349), .A1(n3560), .B0(n3256), .B1(n805), .Y(n3383)
);
OAI22X1TS U3962 ( .A0(n3447), .A1(n3398), .B0(n3399), .B1(n3446), .Y(n3169)
);
OAI22X1TS U3963 ( .A0(n3258), .A1(n3560), .B0(n3279), .B1(n805), .Y(n3170)
);
INVX2TS U3964 ( .A(n8136), .Y(n7784) );
NOR2X1TS U3965 ( .A(n10247), .B(n10191), .Y(n10127) );
NOR2XLTS U3966 ( .A(n10239), .B(n10191), .Y(n10151) );
XNOR2X1TS U3967 ( .A(n10128), .B(n10127), .Y(n10150) );
OAI22X1TS U3968 ( .A0(n4648), .A1(n4672), .B0(n4649), .B1(n4688), .Y(n4557)
);
OAI22X1TS U3969 ( .A0(n4756), .A1(n4628), .B0(n4627), .B1(n4688), .Y(n4558)
);
ADDHXLTS U3970 ( .A(Op_MX[26]), .B(n4526), .CO(n4666), .S(n4532) );
ADDHXLTS U3971 ( .A(n2604), .B(n2603), .CO(n2640), .S(n2601) );
ADDHX1TS U3972 ( .A(n2349), .B(n2348), .CO(n2344), .S(n2372) );
INVX2TS U3973 ( .A(n2376), .Y(n2349) );
INVX2TS U3974 ( .A(n2338), .Y(n2348) );
ADDHXLTS U3975 ( .A(n5706), .B(n5705), .CO(n5779), .S(n5857) );
OAI22X1TS U3976 ( .A0(n9945), .A1(n2797), .B0(n9961), .B1(n9927), .Y(n2675)
);
OAI22X1TS U3977 ( .A0(n9929), .A1(n2704), .B0(n9928), .B1(n9994), .Y(n2496)
);
NOR2X1TS U3978 ( .A(n9949), .B(n2380), .Y(n2495) );
OAI22X1TS U3979 ( .A0(n9929), .A1(n9994), .B0(n9928), .B1(n9991), .Y(n2643)
);
OAI22X1TS U3980 ( .A0(n9949), .A1(n9929), .B0(n9928), .B1(n849), .Y(n9912)
);
XNOR2X1TS U3981 ( .A(n9898), .B(n10071), .Y(n9914) );
INVX2TS U3982 ( .A(n9882), .Y(n9911) );
INVX2TS U3983 ( .A(n9883), .Y(n9910) );
INVX2TS U3984 ( .A(n2439), .Y(n2440) );
ADDHXLTS U3985 ( .A(n2529), .B(n2528), .CO(n2655), .S(n2526) );
OAI22X1TS U3986 ( .A0(n2544), .A1(n6853), .B0(n2545), .B1(n6878), .Y(n2528)
);
NOR2X1TS U3987 ( .A(n2082), .B(n4304), .Y(n1912) );
INVX2TS U3988 ( .A(n10213), .Y(n10258) );
ADDFX2TS U3989 ( .A(n10217), .B(n10216), .CI(n10215), .CO(n10207), .S(n10255) );
NOR2X1TS U3990 ( .A(n3923), .B(n3943), .Y(n3960) );
ADDHXLTS U3991 ( .A(n4009), .B(n4008), .CO(n4050), .S(n4006) );
INVX2TS U3992 ( .A(DP_OP_338J35_122_4684_n1464), .Y(n4494) );
INVX2TS U3993 ( .A(n3895), .Y(n1751) );
OAI22X1TS U3994 ( .A0(n10244), .A1(n2169), .B0(n10184), .B1(n10246), .Y(
n1979) );
NOR2X1TS U3995 ( .A(n1596), .B(n1640), .Y(n1672) );
NAND2X1TS U3996 ( .A(n1297), .B(n1616), .Y(n1590) );
AOI21X1TS U3997 ( .A0(n1095), .A1(n1465), .B0(n1268), .Y(n1269) );
INVX2TS U3998 ( .A(n1788), .Y(n1790) );
NAND2X1TS U3999 ( .A(n1029), .B(n1827), .Y(n1829) );
XNOR2X2TS U4000 ( .A(n1850), .B(n1042), .Y(n1909) );
NAND2X1TS U4001 ( .A(n1146), .B(n1849), .Y(n1850) );
OAI22X1TS U4002 ( .A0(n10185), .A1(n2041), .B0(n10187), .B1(n10246), .Y(
n2029) );
OAI22X1TS U4003 ( .A0(n10203), .A1(n2169), .B0(n10244), .B1(n10184), .Y(
n2028) );
OAI22X1TS U4004 ( .A0(n10186), .A1(n2169), .B0(n10203), .B1(n10184), .Y(
n2035) );
OAI22X1TS U4005 ( .A0(n10166), .A1(n10246), .B0(n10165), .B1(n10244), .Y(
n1996) );
OAI22X1TS U4006 ( .A0(n10189), .A1(n2169), .B0(n10186), .B1(n10184), .Y(
n1994) );
OAI22X1TS U4007 ( .A0(n10166), .A1(n2041), .B0(n10165), .B1(n10246), .Y(
n2047) );
OAI22X1TS U4008 ( .A0(n10189), .A1(n2034), .B0(n10186), .B1(n2033), .Y(n2045) );
INVX2TS U4009 ( .A(n3938), .Y(n1304) );
OAI22X1TS U4010 ( .A0(n10191), .A1(n2034), .B0(n10189), .B1(n2033), .Y(n2040) );
ADDFX2TS U4011 ( .A(n10226), .B(n10225), .CI(n10224), .CO(n10248), .S(n10253) );
OAI22X1TS U4012 ( .A0(n10196), .A1(n10246), .B0(n10195), .B1(n10244), .Y(
n10225) );
ADDFX2TS U4013 ( .A(n10242), .B(n10241), .CI(n10240), .CO(n10264), .S(n10268) );
OAI22X1TS U4014 ( .A0(n1822), .A1(n1948), .B0(n1947), .B1(n1730), .Y(n1718)
);
NOR2X2TS U4015 ( .A(n1823), .B(n1948), .Y(n3890) );
NOR2X1TS U4016 ( .A(n3447), .B(n805), .Y(n3476) );
AOI21X1TS U4017 ( .A0(n3062), .A1(n3061), .B0(n3060), .Y(n3090) );
INVX2TS U4018 ( .A(n3106), .Y(n3548) );
ADDHXLTS U4019 ( .A(n5983), .B(n5982), .CO(n6029), .S(n6001) );
OAI22X1TS U4020 ( .A0(n5993), .A1(n6059), .B0(n6082), .B1(n5888), .Y(n5982)
);
ADDHX1TS U4021 ( .A(n1627), .B(n3241), .CO(n1866), .S(n1864) );
INVX2TS U4022 ( .A(n4851), .Y(n1946) );
OAI22X1TS U4023 ( .A0(n2652), .A1(n2530), .B0(n2544), .B1(n2651), .Y(n2520)
);
OAI22X1TS U4024 ( .A0(n2545), .A1(n6853), .B0(n2509), .B1(n6878), .Y(n2521)
);
OAI22X1TS U4025 ( .A0(n9960), .A1(n9991), .B0(n9959), .B1(n9961), .Y(n9988)
);
OAI22X1TS U4026 ( .A0(n9948), .A1(n9994), .B0(n9947), .B1(n9991), .Y(n2670)
);
OAI22X1TS U4027 ( .A0(n9944), .A1(n2704), .B0(n9946), .B1(n9994), .Y(n2435)
);
OAI22X1TS U4028 ( .A0(n9961), .A1(n2797), .B0(n9991), .B1(n9927), .Y(n2436)
);
NOR2X1TS U4029 ( .A(n4142), .B(n4141), .Y(n4193) );
NAND2X1TS U4030 ( .A(n4142), .B(n4141), .Y(n4191) );
AOI21X1TS U4031 ( .A0(n1143), .A1(n972), .B0(n4145), .Y(n4192) );
INVX2TS U4032 ( .A(n4144), .Y(n4145) );
INVX2TS U4033 ( .A(n4830), .Y(n4183) );
NOR2X2TS U4034 ( .A(Op_MY[17]), .B(Op_MY[44]), .Y(n3943) );
ADDHXLTS U4035 ( .A(n3984), .B(n3983), .CO(n4008), .S(n3981) );
NOR2X1TS U4036 ( .A(n3891), .B(n3890), .Y(n4834) );
NAND2X1TS U4037 ( .A(n3891), .B(n3890), .Y(n4835) );
OAI22X1TS U4038 ( .A0(n6071), .A1(n5835), .B0(n6041), .B1(n6000), .Y(n5837)
);
NOR2X1TS U4039 ( .A(n2232), .B(n2234), .Y(n2308) );
OAI21X1TS U4040 ( .A0(n2235), .A1(n2234), .B0(n2233), .Y(n2311) );
OAI22X1TS U4041 ( .A0(n2652), .A1(n6853), .B0(n2544), .B1(n6878), .Y(n2649)
);
ADDHX1TS U4042 ( .A(n1750), .B(n1749), .CO(n1752), .S(n1940) );
INVX2TS U4043 ( .A(n3890), .Y(n1750) );
NOR2X2TS U4044 ( .A(n2005), .B(n1948), .Y(n3892) );
XNOR2X2TS U4045 ( .A(n1782), .B(n1781), .Y(n1889) );
NAND2X1TS U4046 ( .A(n1128), .B(n1780), .Y(n1782) );
NOR2X1TS U4047 ( .A(n4397), .B(n4445), .Y(n4399) );
NOR2X1TS U4048 ( .A(n4592), .B(n4308), .Y(n4400) );
NOR2X1TS U4049 ( .A(n4397), .B(n4266), .Y(n2053) );
NOR2X1TS U4050 ( .A(n4397), .B(n4304), .Y(n4272) );
NOR2X1TS U4051 ( .A(n4397), .B(n4396), .Y(n4314) );
OAI22X1TS U4052 ( .A0(n6071), .A1(n5978), .B0(n6041), .B1(n6040), .Y(n6005)
);
NOR2X1TS U4053 ( .A(n4308), .B(n4266), .Y(n1919) );
AOI21X1TS U4054 ( .A0(n3954), .A1(n1653), .B0(n1652), .Y(n1658) );
ADDHXLTS U4055 ( .A(n8020), .B(n8019), .CO(n8051), .S(n8022) );
INVX2TS U4056 ( .A(n8149), .Y(n8019) );
ADDHXLTS U4057 ( .A(Op_MX[31]), .B(Op_MX[38]), .CO(n7683), .S(n7676) );
NAND2X1TS U4058 ( .A(Op_MY[39]), .B(Op_MY[32]), .Y(n7662) );
OAI22X1TS U4059 ( .A0(n4938), .A1(n4911), .B0(n4896), .B1(n4943), .Y(n4904)
);
INVX2TS U4060 ( .A(n4483), .Y(n4484) );
NAND2X1TS U4061 ( .A(n4190), .B(n4189), .Y(n4483) );
OAI21X1TS U4062 ( .A0(n4193), .A1(n4192), .B0(n4191), .Y(n4485) );
OAI22X1TS U4063 ( .A0(n4900), .A1(n4911), .B0(n4772), .B1(n4943), .Y(n4764)
);
OAI22X1TS U4064 ( .A0(n4900), .A1(n4756), .B0(n4772), .B1(n4911), .Y(n4682)
);
OAI22X1TS U4065 ( .A0(n4943), .A1(n4648), .B0(n4605), .B1(n4649), .Y(n4683)
);
OAI22X1TS U4066 ( .A0(n4943), .A1(n4643), .B0(n4771), .B1(n4911), .Y(n4684)
);
OAI22X1TS U4067 ( .A0(n4938), .A1(n4672), .B0(n4896), .B1(n4688), .Y(n4662)
);
OAI22X1TS U4068 ( .A0(n4943), .A1(n4627), .B0(n4605), .B1(n4628), .Y(n4687)
);
OAI22X1TS U4069 ( .A0(n8083), .A1(n8018), .B0(n814), .B1(n7847), .Y(n8023)
);
INVX2TS U4070 ( .A(n8150), .Y(n8000) );
OAI22X1TS U4071 ( .A0(n8050), .A1(n8036), .B0(n8017), .B1(n8081), .Y(n7999)
);
ADDFX2TS U4072 ( .A(n1748), .B(n1747), .CI(n1746), .CO(n1755), .S(n3893) );
OAI22X1TS U4073 ( .A0(n2004), .A1(n1948), .B0(n1823), .B1(n1730), .Y(n1747)
);
ADDHXLTS U4074 ( .A(n1867), .B(n3230), .CO(n1660), .S(n1659) );
ADDHX1TS U4075 ( .A(n1712), .B(n1711), .CO(n1732), .S(n1669) );
INVX2TS U4076 ( .A(n1849), .Y(n1536) );
NAND2X1TS U4077 ( .A(n1074), .B(n1475), .Y(n1476) );
OAI21X1TS U4078 ( .A0(n1539), .A1(n1474), .B0(n1473), .Y(n1477) );
ADDHX1TS U4079 ( .A(n1821), .B(n1820), .CO(n2008), .S(n1819) );
OAI22X1TS U4080 ( .A0(n5148), .A1(n2000), .B0(n2005), .B1(n5147), .Y(n1820)
);
NOR2X1TS U4081 ( .A(n1636), .B(n1737), .Y(n1821) );
ADDHX1TS U4082 ( .A(n1836), .B(n3347), .CO(n1601), .S(n1606) );
INVX2TS U4083 ( .A(n1645), .Y(n2004) );
ADDHX1TS U4084 ( .A(Op_MX[26]), .B(n1698), .CO(n1880), .S(n1843) );
INVX2TS U4085 ( .A(n8143), .Y(n7721) );
INVX2TS U4086 ( .A(n8142), .Y(n7722) );
OAI22X1TS U4087 ( .A0(n8083), .A1(n7847), .B0(n8050), .B1(n8018), .Y(n7709)
);
OAI22X1TS U4088 ( .A0(n8083), .A1(n7905), .B0(n814), .B1(n7944), .Y(n7710)
);
OAI22X1TS U4089 ( .A0(n4900), .A1(n4672), .B0(n4772), .B1(n4688), .Y(n4670)
);
OAI22X1TS U4090 ( .A0(n4943), .A1(n4629), .B0(n4911), .B1(n4630), .Y(n4639)
);
INVX2TS U4091 ( .A(n9872), .Y(DP_OP_342J35_126_4270_n391) );
OAI21X1TS U4092 ( .A0(n3923), .A1(n3944), .B0(n3924), .Y(n3962) );
AOI21X2TS U4093 ( .A0(n1114), .A1(n3991), .B0(n1277), .Y(n3965) );
NAND2X1TS U4094 ( .A(n3960), .B(n1120), .Y(n1280) );
AOI21X1TS U4095 ( .A0(n843), .A1(n765), .B0(n4554), .Y(n4603) );
INVX2TS U4096 ( .A(n4553), .Y(n4554) );
NAND2X1TS U4097 ( .A(n4551), .B(n4550), .Y(n4602) );
NOR2X1TS U4098 ( .A(n4551), .B(n4550), .Y(n4604) );
ADDHXLTS U4099 ( .A(n4666), .B(n4665), .CO(n4667), .S(n4527) );
INVX2TS U4100 ( .A(n4533), .Y(n4938) );
INVX2TS U4101 ( .A(DP_OP_338J35_122_4684_n1451), .Y(n4899) );
INVX2TS U4102 ( .A(DP_OP_338J35_122_4684_n1450), .Y(n4898) );
NOR2X1TS U4103 ( .A(n4900), .B(n4605), .Y(n4940) );
XNOR2X1TS U4104 ( .A(n4937), .B(n1248), .Y(n4941) );
XOR2X1TS U4105 ( .A(n4555), .B(n4603), .Y(n4556) );
NAND2X1TS U4106 ( .A(n4552), .B(n4602), .Y(n4555) );
INVX2TS U4107 ( .A(n2261), .Y(n2414) );
INVX2TS U4108 ( .A(n2280), .Y(n2203) );
INVX2TS U4109 ( .A(n6848), .Y(n2563) );
NOR2X1TS U4110 ( .A(n839), .B(n2745), .Y(n2832) );
INVX2TS U4111 ( .A(n6846), .Y(n2364) );
OAI21X1TS U4112 ( .A0(n2365), .A1(n2368), .B0(n2366), .Y(n2359) );
NOR2X1TS U4113 ( .A(n2573), .B(n2293), .Y(n2297) );
OAI22X1TS U4114 ( .A0(n5941), .A1(n5978), .B0(n6040), .B1(n5946), .Y(n5778)
);
NAND2X1TS U4115 ( .A(Op_MY[25]), .B(Op_MY[18]), .Y(n5645) );
AOI21X1TS U4116 ( .A0(n5662), .A1(n1108), .B0(n5631), .Y(n5647) );
OAI22X1TS U4117 ( .A0(n9949), .A1(n2797), .B0(n9945), .B1(n9927), .Y(n2677)
);
OAI22X1TS U4118 ( .A0(n9949), .A1(n2672), .B0(n849), .B1(n2798), .Y(n2678)
);
OAI22X1TS U4119 ( .A0(n9960), .A1(n9994), .B0(n9959), .B1(n9991), .Y(n9982)
);
NOR2X2TS U4120 ( .A(Op_MY[24]), .B(Op_MY[10]), .Y(n2234) );
ADDHXLTS U4121 ( .A(n2502), .B(n2501), .CO(n2516), .S(n2510) );
OAI22X1TS U4122 ( .A0(n2509), .A1(n6853), .B0(n2342), .B1(n6878), .Y(n2501)
);
INVX2TS U4123 ( .A(n2243), .Y(n2651) );
OAI22X1TS U4124 ( .A0(n9960), .A1(n9945), .B0(n9959), .B1(n9949), .Y(n9932)
);
OAI22X1TS U4125 ( .A0(n9960), .A1(n9961), .B0(n9959), .B1(n9945), .Y(n9950)
);
NOR2X1TS U4126 ( .A(n3559), .B(n3278), .Y(n3139) );
OAI22X1TS U4127 ( .A0(n3349), .A1(n3446), .B0(n3256), .B1(n3478), .Y(n3138)
);
OAI22X1TS U4128 ( .A0(n3349), .A1(n3398), .B0(n3256), .B1(n3446), .Y(n3144)
);
INVX2TS U4129 ( .A(n3123), .Y(n3427) );
INVX2TS U4130 ( .A(n3122), .Y(n3497) );
NOR2XLTS U4131 ( .A(n3484), .B(n3278), .Y(n3198) );
OAI22X1TS U4132 ( .A0(n3447), .A1(n3257), .B0(n3399), .B1(n3350), .Y(n3196)
);
OAI22X1TS U4133 ( .A0(n3258), .A1(n3446), .B0(n3279), .B1(n3478), .Y(n3197)
);
OAI22X1TS U4134 ( .A0(n3548), .A1(n3278), .B0(n3484), .B1(n3257), .Y(n3133)
);
OAI22X1TS U4135 ( .A0(n3364), .A1(n3398), .B0(n3354), .B1(n3446), .Y(n3132)
);
OAI22X1TS U4136 ( .A0(n6071), .A1(n5898), .B0(n6041), .B1(n5860), .Y(n5855)
);
OAI22X1TS U4137 ( .A0(n6071), .A1(n5945), .B0(n6083), .B1(n5947), .Y(n5856)
);
ADDFX2TS U4138 ( .A(n3159), .B(n3158), .CI(n3157), .CO(n3517), .S(n3215) );
OAI22X1TS U4139 ( .A0(n4911), .A1(n4629), .B0(n4756), .B1(n4630), .Y(n4548)
);
NOR2X1TS U4140 ( .A(n4911), .B(n4647), .Y(n4561) );
ADDHXLTS U4141 ( .A(n4532), .B(n4531), .CO(n4533), .S(n4463) );
INVX2TS U4142 ( .A(n2350), .Y(n2371) );
OAI22X1TS U4143 ( .A0(n9949), .A1(n2798), .B0(n9945), .B1(n2672), .Y(n2696)
);
INVX2TS U4144 ( .A(n3072), .Y(n3399) );
INVX4TS U4145 ( .A(n3078), .Y(n3398) );
XOR2X1TS U4146 ( .A(n3077), .B(n3076), .Y(n3078) );
AOI21X1TS U4147 ( .A0(n3074), .A1(n1052), .B0(n3073), .Y(n3077) );
NAND2X1TS U4148 ( .A(n1137), .B(n3075), .Y(n3076) );
OAI22X1TS U4149 ( .A0(n9960), .A1(n2744), .B0(n9959), .B1(n2704), .Y(n2493)
);
OAI22X1TS U4150 ( .A0(n9960), .A1(n2704), .B0(n9959), .B1(n9994), .Y(n2620)
);
OAI22X1TS U4151 ( .A0(n9993), .A1(n9991), .B0(n9992), .B1(n9961), .Y(n10000)
);
OAI22X1TS U4152 ( .A0(n9960), .A1(n9949), .B0(n9959), .B1(n849), .Y(n9899)
);
NOR2X1TS U4153 ( .A(n9960), .B(n849), .Y(n9896) );
OAI22X1TS U4154 ( .A0(n6854), .A1(n2531), .B0(n882), .B1(n2524), .Y(n2525)
);
OAI22X1TS U4155 ( .A0(n6854), .A1(n2651), .B0(n882), .B1(n2530), .Y(n2654)
);
OAI22X1TS U4156 ( .A0(n6854), .A1(n2530), .B0(n2652), .B1(n2651), .Y(n2534)
);
INVX2TS U4157 ( .A(n2503), .Y(n2323) );
OAI22X1TS U4158 ( .A0(n3349), .A1(n3350), .B0(n3256), .B1(n3398), .Y(n3208)
);
NOR2X1TS U4159 ( .A(n4445), .B(n2174), .Y(n1908) );
ADDHXLTS U4160 ( .A(n3974), .B(n3973), .CO(n3982), .S(n3996) );
ADDFX2TS U4161 ( .A(n10256), .B(n10255), .CI(n10254), .CO(
DP_OP_338J35_122_4684_n50), .S(DP_OP_338J35_122_4684_n51) );
INVX2TS U4162 ( .A(n8134), .Y(n7782) );
NAND2X2TS U4163 ( .A(n1114), .B(n1126), .Y(n3961) );
OAI22X1TS U4164 ( .A0(n4756), .A1(n4629), .B0(n4688), .B1(n4630), .Y(n4489)
);
OAI22X1TS U4165 ( .A0(n4627), .A1(n4672), .B0(n4628), .B1(n4688), .Y(n4490)
);
NOR2X1TS U4166 ( .A(n4756), .B(n4647), .Y(n4477) );
ADDHXLTS U4167 ( .A(n4468), .B(n4467), .CO(n4469), .S(n4110) );
INVX2TS U4168 ( .A(DP_OP_338J35_122_4684_n8), .Y(n1234) );
OAI22X1TS U4169 ( .A0(n6055), .A1(n5888), .B0(n6042), .B1(n5993), .Y(n5821)
);
NOR2X1TS U4170 ( .A(n2082), .B(n4266), .Y(n1902) );
NOR2X1TS U4171 ( .A(n4396), .B(n2174), .Y(n1904) );
ADDHXLTS U4172 ( .A(n5751), .B(n5750), .CO(n5753), .S(n5765) );
ADDHXLTS U4173 ( .A(n1896), .B(n1895), .CO(n1900), .S(n1960) );
INVX2TS U4174 ( .A(n1459), .Y(n1452) );
NAND2X1TS U4175 ( .A(Op_MY[39]), .B(Op_MY[12]), .Y(n1454) );
AOI21X1TS U4176 ( .A0(n1466), .A1(n1074), .B0(n1465), .Y(n1467) );
INVX2TS U4177 ( .A(n1451), .Y(n1460) );
ADDHX1TS U4178 ( .A(n1840), .B(n1905), .CO(n1839), .S(n1841) );
OAI22X1TS U4179 ( .A0(n10185), .A1(n2105), .B0(n10187), .B1(n2041), .Y(n2071) );
OAI22X1TS U4180 ( .A0(n10203), .A1(n2034), .B0(n10244), .B1(n2033), .Y(n2069) );
NOR2X1TS U4181 ( .A(Op_MY[38]), .B(Op_MY[11]), .Y(n1451) );
OAI22X1TS U4182 ( .A0(n10166), .A1(n2105), .B0(n10165), .B1(n2041), .Y(n2043) );
OAI22X1TS U4183 ( .A0(n10186), .A1(n2034), .B0(n10203), .B1(n2033), .Y(n2044) );
NOR2X1TS U4184 ( .A(n4397), .B(n4592), .Y(n4448) );
ADDFX2TS U4185 ( .A(n2088), .B(n2087), .CI(n2086), .CO(n2104), .S(n2116) );
OAI22X1TS U4186 ( .A0(n10196), .A1(n2105), .B0(n10195), .B1(n2041), .Y(n2091) );
NAND2X1TS U4187 ( .A(n1274), .B(n1521), .Y(n1276) );
AOI21X1TS U4188 ( .A0(n1274), .A1(n1523), .B0(n1273), .Y(n1275) );
NOR2X1TS U4189 ( .A(n1525), .B(n4056), .Y(n1274) );
OAI22X1TS U4190 ( .A0(n10196), .A1(n2041), .B0(n10195), .B1(n10246), .Y(
n1878) );
ADDFX2TS U4191 ( .A(n10253), .B(n10252), .CI(n10251), .CO(n10281), .S(n10286) );
NOR2XLTS U4192 ( .A(n10239), .B(n2041), .Y(n10251) );
ADDHX1TS U4193 ( .A(n1692), .B(n1691), .CO(n1720), .S(n4845) );
NOR2X1TS U4194 ( .A(n1713), .B(n1730), .Y(n1691) );
OAI22X1TS U4195 ( .A0(n1737), .A1(n1948), .B0(n1949), .B1(n1730), .Y(n1692)
);
NOR2X1TS U4196 ( .A(n1947), .B(n1948), .Y(n4844) );
ADDFX2TS U4197 ( .A(n10295), .B(n10294), .CI(n10293), .CO(n10287), .S(n10304) );
INVX2TS U4198 ( .A(n3891), .Y(n1943) );
ADDHX1TS U4199 ( .A(n1864), .B(n1863), .CO(n1854), .S(n1865) );
INVX4TS U4200 ( .A(n1863), .Y(n1713) );
INVX2TS U4201 ( .A(n3079), .Y(n3581) );
NOR2X1TS U4202 ( .A(n5993), .B(n731), .Y(n6038) );
NOR2X1TS U4203 ( .A(n6083), .B(n6000), .Y(n6032) );
AOI21X1TS U4204 ( .A0(n3954), .A1(n1639), .B0(n1638), .Y(n1644) );
INVX2TS U4205 ( .A(n1640), .Y(n1642) );
INVX2TS U4206 ( .A(n3281), .Y(n3023) );
INVX2TS U4207 ( .A(n4844), .Y(n1951) );
INVX2TS U4208 ( .A(n2311), .Y(n2236) );
INVX2TS U4209 ( .A(n2308), .Y(n2237) );
OAI22X1TS U4210 ( .A0(n6854), .A1(n2524), .B0(n2652), .B1(n2531), .Y(n2515)
);
OAI22X1TS U4211 ( .A0(n6854), .A1(n2523), .B0(n882), .B1(n2508), .Y(n2514)
);
NOR2XLTS U4212 ( .A(n9995), .B(n9949), .Y(n9907) );
OAI22X1TS U4213 ( .A0(n9993), .A1(n9949), .B0(n9992), .B1(n849), .Y(n9908)
);
INVX2TS U4214 ( .A(n3110), .Y(n3349) );
ADDHXLTS U4215 ( .A(n3192), .B(n3230), .CO(n3108), .S(n3109) );
INVX2TS U4216 ( .A(n2231), .Y(n2531) );
OAI22X1TS U4217 ( .A0(n9993), .A1(n9994), .B0(n9992), .B1(n9991), .Y(n10026)
);
OAI22X1TS U4218 ( .A0(n9929), .A1(n2744), .B0(n9928), .B1(n2704), .Y(n2444)
);
INVX2TS U4219 ( .A(n2345), .Y(n2375) );
ADDHXLTS U4220 ( .A(n2593), .B(n2592), .CO(n2603), .S(n2590) );
ADDHXLTS U4221 ( .A(n7777), .B(n7776), .CO(n7828), .S(n7853) );
INVX2TS U4222 ( .A(n8325), .Y(n7777) );
INVX2TS U4223 ( .A(n8129), .Y(n7776) );
INVX2TS U4224 ( .A(n5127), .Y(n3911) );
INVX2TS U4225 ( .A(n4803), .Y(n4153) );
NAND2X1TS U4226 ( .A(n4120), .B(n4119), .Y(n4130) );
OAI21X1TS U4227 ( .A0(n4223), .A1(n4122), .B0(n4121), .Y(n4132) );
NAND2X1TS U4228 ( .A(n4129), .B(n4128), .Y(n4144) );
AO21X1TS U4229 ( .A0(n1037), .A1(n4132), .B0(n4131), .Y(n972) );
XOR2X1TS U4230 ( .A(n4146), .B(n4192), .Y(n4147) );
NAND2X1TS U4231 ( .A(n4143), .B(n4191), .Y(n4146) );
OAI2BB1X1TS U4232 ( .A0N(n4163), .A1N(n4162), .B0(n4161), .Y(n4186) );
CLKXOR2X2TS U4233 ( .A(n3947), .B(n3946), .Y(n4142) );
AOI21X1TS U4234 ( .A0(n3992), .A1(n3942), .B0(n3941), .Y(n3947) );
INVX2TS U4235 ( .A(n5100), .Y(n4887) );
NAND2X1TS U4236 ( .A(n5095), .B(n1160), .Y(n4889) );
ADDHXLTS U4237 ( .A(n7799), .B(n7798), .CO(n7814), .S(n7800) );
ADDHXLTS U4238 ( .A(Op_MX[29]), .B(Op_MX[36]), .CO(n7686), .S(n7685) );
NAND2X1TS U4239 ( .A(n3893), .B(n3892), .Y(n4879) );
OAI21X1TS U4240 ( .A0(n4834), .A1(n4837), .B0(n4835), .Y(n4880) );
XOR2X1TS U4241 ( .A(n4838), .B(n4837), .Y(n4873) );
XNOR2X2TS U4242 ( .A(n4878), .B(n979), .Y(n4885) );
NOR2X1TS U4243 ( .A(Op_MY[26]), .B(Op_MY[12]), .Y(n2503) );
OAI21X2TS U4244 ( .A0(n2314), .A1(n2313), .B0(n2312), .Y(n2507) );
NAND2X1TS U4245 ( .A(n1031), .B(n2308), .Y(n2313) );
AOI21X1TS U4246 ( .A0(n2311), .A1(n1031), .B0(n2310), .Y(n2312) );
INVX2TS U4247 ( .A(n2309), .Y(n2310) );
ADDHXLTS U4248 ( .A(Op_MX[12]), .B(Op_MX[26]), .CO(n2321), .S(n2317) );
OAI22X1TS U4249 ( .A0(n6854), .A1(n6853), .B0(n2652), .B1(n6878), .Y(n6855)
);
NOR2X1TS U4250 ( .A(n882), .B(n2651), .Y(n6856) );
INVX2TS U4251 ( .A(n3230), .Y(n3344) );
AOI21X1TS U4252 ( .A0(n3954), .A1(n1595), .B0(n1594), .Y(n1600) );
INVX2TS U4253 ( .A(n3343), .Y(n3348) );
INVX2TS U4254 ( .A(n3893), .Y(n1941) );
NOR2X1TS U4255 ( .A(n4444), .B(n4266), .Y(n4268) );
OAI22X1TS U4256 ( .A0(n6055), .A1(n6041), .B0(n6042), .B1(n6071), .Y(n6035)
);
XNOR2X1TS U4257 ( .A(n3343), .B(n908), .Y(n3152) );
ADDHXLTS U4258 ( .A(n3151), .B(n3150), .CO(n3180), .S(n3204) );
OAI22X1TS U4259 ( .A0(n3127), .A1(n3499), .B0(n3126), .B1(n877), .Y(n3150)
);
OAI22X1TS U4260 ( .A0(n3125), .A1(n877), .B0(n3499), .B1(n3498), .Y(n3151)
);
XNOR2X1TS U4261 ( .A(n3347), .B(n908), .Y(n3153) );
NOR2BX1TS U4262 ( .AN(n3281), .B(n3501), .Y(n3156) );
OAI22X1TS U4263 ( .A0(n3124), .A1(n3255), .B0(n3024), .B1(n3280), .Y(n3155)
);
AOI21X1TS U4264 ( .A0(n2463), .A1(n1012), .B0(n2244), .Y(n2397) );
INVX2TS U4265 ( .A(n8160), .Y(n8039) );
INVX2TS U4266 ( .A(n8161), .Y(n8038) );
INVX4TS U4267 ( .A(n7660), .Y(n8050) );
XNOR2X1TS U4268 ( .A(n7659), .B(n7658), .Y(n7660) );
OAI22X1TS U4269 ( .A0(n8083), .A1(n8036), .B0(n8050), .B1(n8081), .Y(n8052)
);
ADDHXLTS U4270 ( .A(Op_MX[39]), .B(Op_MX[32]), .CO(n7706), .S(n7707) );
INVX4TS U4271 ( .A(n7667), .Y(n8083) );
XNOR2X1TS U4272 ( .A(n7666), .B(n740), .Y(n7667) );
INVX2TS U4273 ( .A(n7669), .Y(n7664) );
OAI22X1TS U4274 ( .A0(n4938), .A1(n4943), .B0(n4896), .B1(n4605), .Y(n4946)
);
OAI22X1TS U4275 ( .A0(n4964), .A1(n4911), .B0(n4942), .B1(n4943), .Y(n4935)
);
XNOR2X1TS U4276 ( .A(n4486), .B(n765), .Y(n4487) );
NAND2X1TS U4277 ( .A(n843), .B(n4553), .Y(n4486) );
XNOR2X1TS U4278 ( .A(n4194), .B(n4485), .Y(n4195) );
NAND2X1TS U4279 ( .A(n842), .B(n4483), .Y(n4194) );
OAI22X1TS U4280 ( .A0(n8049), .A1(n8083), .B0(n7998), .B1(n814), .Y(n8047)
);
OAI22X1TS U4281 ( .A0(n8093), .A1(n8017), .B0(n8082), .B1(n8050), .Y(n8056)
);
OAI22X1TS U4282 ( .A0(n4938), .A1(n4756), .B0(n4896), .B1(n4911), .Y(n4774)
);
OAI22X1TS U4283 ( .A0(n4964), .A1(n4688), .B0(n4942), .B1(n4756), .Y(n4776)
);
OAI22X1TS U4284 ( .A0(n4964), .A1(n4672), .B0(n4942), .B1(n4688), .Y(n4676)
);
OAI22X1TS U4285 ( .A0(n4938), .A1(n4688), .B0(n4896), .B1(n4756), .Y(n4690)
);
AOI21X1TS U4286 ( .A0(n4014), .A1(n1312), .B0(n1311), .Y(n4024) );
INVX2TS U4287 ( .A(n8220), .Y(n8009) );
OAI22X1TS U4288 ( .A0(n8093), .A1(n7898), .B0(n8082), .B1(n8017), .Y(n8026)
);
OAI22X1TS U4289 ( .A0(n8049), .A1(n8050), .B0(n7998), .B1(n8083), .Y(n8004)
);
ADDHXLTS U4290 ( .A(Op_MX[22]), .B(Op_MX[49]), .CO(n1291), .S(n1287) );
NOR2X2TS U4291 ( .A(n5181), .B(n1948), .Y(n3898) );
NAND2X1TS U4292 ( .A(n3896), .B(n3895), .Y(n4877) );
AO21XLTS U4293 ( .A0(n1017), .A1(n4880), .B0(n3894), .Y(n979) );
INVX2TS U4294 ( .A(n1684), .Y(n1929) );
OAI22X1TS U4295 ( .A0(n5148), .A1(n1948), .B0(n2005), .B1(n1730), .Y(n1754)
);
ADDFX2TS U4296 ( .A(n1733), .B(n1732), .CI(n1731), .CO(n1814), .S(n1735) );
OAI22X1TS U4297 ( .A0(n2004), .A1(n2000), .B0(n5147), .B1(n1823), .Y(n1733)
);
NAND2X1TS U4298 ( .A(n3047), .B(n1774), .Y(n1602) );
OAI22X1TS U4299 ( .A0(n5177), .A1(n1948), .B0(n5149), .B1(n1730), .Y(n1724)
);
OAI22X1TS U4300 ( .A0(n5182), .A1(n1822), .B0(n1636), .B1(n1947), .Y(n1815)
);
OAI22X1TS U4301 ( .A0(n5182), .A1(n1823), .B0(n2004), .B1(n5147), .Y(n1816)
);
OAI21X1TS U4302 ( .A0(n1628), .A1(n802), .B0(n1629), .Y(n1624) );
NOR2X1TS U4303 ( .A(n1636), .B(n1822), .Y(n2003) );
OAI22X1TS U4304 ( .A0(n5182), .A1(n2005), .B0(n5148), .B1(n5147), .Y(n2001)
);
OAI22X1TS U4305 ( .A0(n5177), .A1(n2000), .B0(n5149), .B1(n5147), .Y(n2007)
);
INVX2TS U4306 ( .A(n1690), .Y(n5149) );
NOR2X1TS U4307 ( .A(n1636), .B(n2004), .Y(n5152) );
OAI22X1TS U4308 ( .A0(n5177), .A1(n5147), .B0(n5149), .B1(n5182), .Y(n5150)
);
OAI22X1TS U4309 ( .A0(n5182), .A1(n5148), .B0(n2005), .B1(n1636), .Y(n5151)
);
INVX2TS U4310 ( .A(n1623), .Y(n1545) );
INVX2TS U4311 ( .A(n8217), .Y(n7787) );
OAI22X1TS U4312 ( .A0(n8093), .A1(n7900), .B0(n8082), .B1(n7898), .Y(n7731)
);
OAI22X1TS U4313 ( .A0(n8049), .A1(n8017), .B0(n7998), .B1(n8050), .Y(n7817)
);
INVX2TS U4314 ( .A(n7824), .Y(n7856) );
INVX2TS U4315 ( .A(n4527), .Y(n4942) );
NOR2X2TS U4316 ( .A(Op_MY[51]), .B(Op_MY[44]), .Y(n9816) );
ADDHX1TS U4317 ( .A(n9777), .B(n9776), .CO(DP_OP_342J35_126_4270_n179), .S(
DP_OP_342J35_126_4270_n180) );
INVX2TS U4318 ( .A(n9774), .Y(n9777) );
INVX2TS U4319 ( .A(n9775), .Y(n9776) );
ADDHXLTS U4320 ( .A(Op_MX[44]), .B(Op_MX[51]), .CO(n9766), .S(n9793) );
INVX2TS U4321 ( .A(n9873), .Y(DP_OP_342J35_126_4270_n398) );
ADDHXLTS U4322 ( .A(n9799), .B(n9798), .CO(DP_OP_342J35_126_4270_n234), .S(
n9795) );
OAI22X1TS U4323 ( .A0(n9840), .A1(n9831), .B0(n9841), .B1(n9830), .Y(n9799)
);
AOI21X2TS U4324 ( .A0(n7312), .A1(n9815), .B0(n7311), .Y(n9813) );
NOR2X1TS U4325 ( .A(n9822), .B(n9816), .Y(n7312) );
ADDHXLTS U4326 ( .A(n7074), .B(n7073), .CO(n7090), .S(n7075) );
INVX2TS U4327 ( .A(n9770), .Y(n9773) );
CMPR42X1TS U4328 ( .A(DP_OP_342J35_126_4270_n391), .B(
DP_OP_342J35_126_4270_n390), .C(DP_OP_342J35_126_4270_n179), .D(
DP_OP_342J35_126_4270_n294), .ICI(DP_OP_342J35_126_4270_n271), .S(
DP_OP_342J35_126_4270_n166), .ICO(DP_OP_342J35_126_4270_n164), .CO(
DP_OP_342J35_126_4270_n165) );
INVX2TS U4329 ( .A(n9871), .Y(DP_OP_342J35_126_4270_n390) );
ADDHXLTS U4330 ( .A(Op_MX[23]), .B(Op_MX[50]), .CO(n1328), .S(n1292) );
ADDHXLTS U4331 ( .A(n1385), .B(n1384), .CO(n1386), .S(n1398) );
OAI22X1TS U4332 ( .A0(n1391), .A1(n1389), .B0(n2194), .B1(n1428), .Y(n1392)
);
OAI22X1TS U4333 ( .A0(n1429), .A1(n2190), .B0(n880), .B1(n2198), .Y(n1393)
);
OAI22X1TS U4334 ( .A0(n1429), .A1(n2189), .B0(n1390), .B1(n1381), .Y(n1402)
);
OAI22X1TS U4335 ( .A0(n1390), .A1(n1383), .B0(n1391), .B1(n1382), .Y(n1403)
);
OAI22X1TS U4336 ( .A0(n1429), .A1(n1383), .B0(n1390), .B1(n1382), .Y(n1399)
);
OAI22X1TS U4337 ( .A0(n1429), .A1(n1381), .B0(n880), .B1(n2189), .Y(n1400)
);
AOI21X2TS U4338 ( .A0(n1038), .A1(n1315), .B0(n1314), .Y(n1340) );
INVX2TS U4339 ( .A(n1313), .Y(n1314) );
NAND2X1TS U4340 ( .A(n1038), .B(n1147), .Y(n1333) );
NOR2X1TS U4341 ( .A(n1280), .B(n3961), .Y(n3976) );
OAI21X1TS U4342 ( .A0(n1280), .A1(n3965), .B0(n1279), .Y(n3975) );
AOI21X1TS U4343 ( .A0(n3962), .A1(n1120), .B0(n1278), .Y(n1279) );
INVX2TS U4344 ( .A(n3968), .Y(n1278) );
ADDHXLTS U4345 ( .A(Op_MX[24]), .B(Op_MX[51]), .CO(n1343), .S(n1327) );
INVX2TS U4346 ( .A(n1365), .Y(n1351) );
INVX2TS U4347 ( .A(n4667), .Y(n4964) );
OAI22X1TS U4348 ( .A0(n4964), .A1(n4943), .B0(n4942), .B1(n4605), .Y(n4966)
);
ADDHXLTS U4349 ( .A(n5671), .B(n5670), .CO(n5723), .S(n5667) );
NAND2X1TS U4350 ( .A(Op_MY[20]), .B(Op_MY[6]), .Y(n2419) );
INVX2TS U4351 ( .A(n2411), .Y(n2412) );
AOI21X1TS U4352 ( .A0(n2415), .A1(n1022), .B0(n2414), .Y(n2416) );
INVX2TS U4353 ( .A(n2413), .Y(n2415) );
AOI21X1TS U4354 ( .A0(n2414), .A1(n1077), .B0(n2208), .Y(n2209) );
INVX2TS U4355 ( .A(n2419), .Y(n2208) );
NAND2X1TS U4356 ( .A(n1113), .B(n2281), .Y(n2205) );
INVX2TS U4357 ( .A(n2276), .Y(n2202) );
ADDHXLTS U4358 ( .A(Op_MX[13]), .B(n2613), .CO(n2616), .S(n2432) );
OAI22X1TS U4359 ( .A0(n9991), .A1(n2797), .B0(n9927), .B1(n9994), .Y(n2568)
);
INVX2TS U4360 ( .A(n2266), .Y(n2272) );
NOR2X1TS U4361 ( .A(n2866), .B(n2862), .Y(n2635) );
INVX2TS U4362 ( .A(n2271), .Y(n2207) );
INVX2TS U4363 ( .A(n2267), .Y(n2206) );
INVX2TS U4364 ( .A(n2260), .Y(n2418) );
NOR2X1TS U4365 ( .A(n839), .B(n2831), .Y(n2869) );
OAI22X1TS U4366 ( .A0(n9927), .A1(n2704), .B0(n2797), .B1(n9994), .Y(n2667)
);
XOR2X1TS U4367 ( .A(n2301), .B(n2300), .Y(n2302) );
INVX2TS U4368 ( .A(n2297), .Y(n2299) );
AOI21X1TS U4369 ( .A0(n1123), .A1(n2392), .B0(n2289), .Y(n2368) );
INVX2TS U4370 ( .A(n2391), .Y(n2289) );
OAI22X1TS U4371 ( .A0(n5993), .A1(n5898), .B0(n5888), .B1(n5860), .Y(n5866)
);
INVX4TS U4372 ( .A(n5642), .Y(n6041) );
XNOR2X1TS U4373 ( .A(n5641), .B(n5640), .Y(n5642) );
OAI22X1TS U4374 ( .A0(n5941), .A1(n5860), .B0(n5888), .B1(n5898), .Y(n5906)
);
INVX4TS U4375 ( .A(n5649), .Y(n5993) );
XOR2X1TS U4376 ( .A(n5648), .B(n5647), .Y(n5649) );
NAND2X1TS U4377 ( .A(n5646), .B(n5645), .Y(n5648) );
OAI22X1TS U4378 ( .A0(n9993), .A1(n2744), .B0(n9992), .B1(n2704), .Y(n2714)
);
OAI22X1TS U4379 ( .A0(n9993), .A1(n2704), .B0(n9992), .B1(n9994), .Y(n10010)
);
NOR2X1TS U4380 ( .A(Op_MY[22]), .B(Op_MY[8]), .Y(n2224) );
NAND2X1TS U4381 ( .A(Op_MY[23]), .B(Op_MY[9]), .Y(n2225) );
INVX2TS U4382 ( .A(n2437), .Y(n2213) );
AOI21X1TS U4383 ( .A0(n1124), .A1(n2218), .B0(n2217), .Y(n2235) );
INVX2TS U4384 ( .A(n2225), .Y(n2217) );
INVX2TS U4385 ( .A(n2223), .Y(n2218) );
NAND2X1TS U4386 ( .A(n1124), .B(n2216), .Y(n2232) );
INVX2TS U4387 ( .A(n2234), .Y(n2219) );
ADDHXLTS U4388 ( .A(Op_MX[11]), .B(Op_MX[25]), .CO(n2337), .S(n2201) );
ADDHXLTS U4389 ( .A(n2307), .B(n2306), .CO(n2333), .S(n2318) );
OAI22X1TS U4390 ( .A0(n2545), .A1(n2524), .B0(n2509), .B1(n2531), .Y(n2306)
);
OAI22X1TS U4391 ( .A0(n2509), .A1(n2530), .B0(n2342), .B1(n2651), .Y(n2307)
);
OAI22X1TS U4392 ( .A0(n2544), .A1(n2524), .B0(n2545), .B1(n2531), .Y(n2329)
);
OAI22X1TS U4393 ( .A0(n2652), .A1(n2508), .B0(n2544), .B1(n2523), .Y(n2330)
);
OAI22X1TS U4394 ( .A0(n6854), .A1(n2508), .B0(n2652), .B1(n2523), .Y(n2499)
);
OAI22X1TS U4395 ( .A0(n2544), .A1(n2530), .B0(n2545), .B1(n2651), .Y(n2511)
);
OAI22X1TS U4396 ( .A0(n2652), .A1(n2524), .B0(n2544), .B1(n2531), .Y(n2512)
);
NOR2XLTS U4397 ( .A(n9995), .B(n9945), .Y(n9963) );
NOR2XLTS U4398 ( .A(n9995), .B(n9961), .Y(n9998) );
OAI22X1TS U4399 ( .A0(n9993), .A1(n9961), .B0(n9992), .B1(n9945), .Y(n9972)
);
ADDHXLTS U4400 ( .A(n3228), .B(n3241), .CO(n3110), .S(n3111) );
NOR2XLTS U4401 ( .A(n3427), .B(n3278), .Y(n3232) );
OAI22X1TS U4402 ( .A0(n3447), .A1(n3278), .B0(n3399), .B1(n3257), .Y(n3233)
);
OAI22X1TS U4403 ( .A0(n3258), .A1(n3398), .B0(n3279), .B1(n3446), .Y(n3234)
);
INVX2TS U4404 ( .A(n3601), .Y(n3212) );
NAND2X1TS U4405 ( .A(Op_MY[33]), .B(Op_MY[6]), .Y(n1485) );
INVX2TS U4406 ( .A(n6120), .Y(n5911) );
OAI22X1TS U4407 ( .A0(n6071), .A1(n5947), .B0(n6041), .B1(n5945), .Y(n5913)
);
INVX2TS U4408 ( .A(n3606), .Y(n3188) );
AOI21X1TS U4409 ( .A0(n3954), .A1(n1619), .B0(n1618), .Y(n1622) );
OAI21X1TS U4410 ( .A0(n1539), .A1(n1538), .B0(n1537), .Y(n1542) );
INVX2TS U4411 ( .A(n4463), .Y(n4896) );
OAI22X1TS U4412 ( .A0(n9993), .A1(n2799), .B0(n9992), .B1(n2744), .Y(n2723)
);
OAI22X1TS U4413 ( .A0(n2544), .A1(n2508), .B0(n2545), .B1(n2523), .Y(n2320)
);
INVX2TS U4414 ( .A(n1704), .Y(n1617) );
NOR2X1TS U4415 ( .A(n3399), .B(n3278), .Y(n3260) );
OAI22X1TS U4416 ( .A0(n3349), .A1(n3257), .B0(n3256), .B1(n3350), .Y(n3259)
);
NOR2X1TS U4417 ( .A(Op_MX[20]), .B(Op_MX[6]), .Y(n2474) );
OA21XLTS U4418 ( .A0(n2486), .A1(n2479), .B0(n2487), .Y(n1106) );
OAI21X2TS U4419 ( .A0(n2247), .A1(n2397), .B0(n2246), .Y(n2429) );
NAND2X1TS U4420 ( .A(n1021), .B(n1023), .Y(n2247) );
AOI21X1TS U4421 ( .A0(n2403), .A1(n1023), .B0(n2245), .Y(n2246) );
INVX2TS U4422 ( .A(n2405), .Y(n2245) );
INVX2TS U4423 ( .A(n2224), .Y(n2216) );
ADDHXLTS U4424 ( .A(n5652), .B(n5651), .CO(n5668), .S(n5655) );
INVX2TS U4425 ( .A(n10002), .Y(n10039) );
INVX2TS U4426 ( .A(n9902), .Y(n9918) );
XNOR2X1TS U4427 ( .A(n9897), .B(n9896), .Y(n9920) );
NOR2X1TS U4428 ( .A(n9993), .B(n849), .Y(n9891) );
NOR2XLTS U4429 ( .A(n9995), .B(n849), .Y(n9905) );
XNOR2X1TS U4430 ( .A(n9892), .B(n9891), .Y(n9904) );
INVX4TS U4431 ( .A(n2325), .Y(n6854) );
XOR2X1TS U4432 ( .A(n2324), .B(n1049), .Y(n2325) );
AOI21X1TS U4433 ( .A0(n2507), .A1(n2323), .B0(n2322), .Y(n2324) );
INVX2TS U4434 ( .A(n2504), .Y(n2322) );
XNOR2X1TS U4435 ( .A(n2507), .B(n2315), .Y(n2316) );
NAND2X1TS U4436 ( .A(n2323), .B(n2504), .Y(n2315) );
NOR2X1TS U4437 ( .A(n4308), .B(n2048), .Y(n2096) );
ADDHX1TS U4438 ( .A(n7560), .B(n7559), .CO(n7801), .S(n7557) );
NOR2X1TS U4439 ( .A(n813), .B(n757), .Y(n7559) );
NOR2X1TS U4440 ( .A(n8096), .B(n955), .Y(n7560) );
NOR2X1TS U4441 ( .A(n4074), .B(n4052), .Y(n3997) );
NAND2X1TS U4442 ( .A(n1159), .B(n4882), .Y(n4883) );
ADDHXLTS U4443 ( .A(n4138), .B(n4137), .CO(n4136), .S(n4139) );
OAI22X1TS U4444 ( .A0(n8050), .A1(n7909), .B0(n8017), .B1(n7908), .Y(n7872)
);
INVX2TS U4445 ( .A(n7707), .Y(n8082) );
CLKXOR2X2TS U4446 ( .A(n3927), .B(n3926), .Y(n4190) );
AOI21X1TS U4447 ( .A0(n3992), .A1(n3922), .B0(n3921), .Y(n3927) );
INVX2TS U4448 ( .A(n3923), .Y(n3925) );
CLKXOR2X2TS U4449 ( .A(n3979), .B(n3978), .Y(n4551) );
AOI21X1TS U4450 ( .A0(n3992), .A1(n3976), .B0(n3975), .Y(n3979) );
CLKXOR2X2TS U4451 ( .A(n3970), .B(n3969), .Y(n4482) );
AOI21X1TS U4452 ( .A0(n3992), .A1(n3967), .B0(n3966), .Y(n3970) );
ADDFX2TS U4453 ( .A(n4476), .B(n4475), .CI(n4474), .CO(n4540), .S(n4471) );
NOR2X1TS U4454 ( .A(n4273), .B(n2048), .Y(n1961) );
ADDHXLTS U4455 ( .A(n5746), .B(n5745), .CO(n5748), .S(n5752) );
ADDHXLTS U4456 ( .A(n5738), .B(n5737), .CO(n5740), .S(n5749) );
NOR2X1TS U4457 ( .A(n2082), .B(n2048), .Y(n1958) );
OAI22X1TS U4458 ( .A0(n10184), .A1(n2041), .B0(n2169), .B1(n10246), .Y(n1966) );
OAI22X1TS U4459 ( .A0(n10244), .A1(n2034), .B0(n10246), .B1(n2033), .Y(n1982) );
NOR2X2TS U4460 ( .A(n10214), .B(n10213), .Y(n4438) );
AOI21X1TS U4461 ( .A0(n1529), .A1(n1521), .B0(n1523), .Y(n1448) );
INVX2TS U4462 ( .A(n1525), .Y(n1446) );
NAND2X1TS U4463 ( .A(n1460), .B(n1459), .Y(n1461) );
AOI21X1TS U4464 ( .A0(n3954), .A1(n1706), .B0(n1705), .Y(n1709) );
AOI21X1TS U4465 ( .A0(n3954), .A1(n1679), .B0(n1678), .Y(n1682) );
AOI21X2TS U4466 ( .A0(n1295), .A1(n1562), .B0(n1294), .Y(n1548) );
OAI21X1TS U4467 ( .A0(n1576), .A1(n1579), .B0(n1580), .Y(n1294) );
NOR2X2TS U4468 ( .A(Op_MY[40]), .B(Op_MY[13]), .Y(n1525) );
NOR2X2TS U4469 ( .A(n1453), .B(n1451), .Y(n1521) );
INVX2TS U4470 ( .A(n1445), .Y(n1529) );
OAI21X2TS U4471 ( .A0(n4438), .A1(n4437), .B0(n4436), .Y(n4865) );
NOR2X2TS U4472 ( .A(n4435), .B(n4438), .Y(n4859) );
NOR2X1TS U4473 ( .A(n10174), .B(n10173), .Y(n4858) );
NAND2X1TS U4474 ( .A(n10152), .B(n10129), .Y(n4860) );
NOR2X2TS U4475 ( .A(n10152), .B(n10129), .Y(n4862) );
AOI21X1TS U4476 ( .A0(n4865), .A1(n4586), .B0(n4585), .Y(n4587) );
NAND2X1TS U4477 ( .A(n4859), .B(n4586), .Y(n4588) );
NAND2X1TS U4478 ( .A(Op_MY[15]), .B(Op_MY[42]), .Y(n4031) );
INVX2TS U4479 ( .A(n3992), .Y(n4033) );
INVX2TS U4480 ( .A(n5624), .Y(n4870) );
OAI21X1TS U4481 ( .A0(n4868), .A1(n4867), .B0(n4866), .Y(n4869) );
NAND2X1TS U4482 ( .A(n4859), .B(n4864), .Y(n4867) );
AOI21X1TS U4483 ( .A0(n4865), .A1(n4864), .B0(n4863), .Y(n4866) );
NOR2X1TS U4484 ( .A(n4858), .B(n4862), .Y(n4864) );
CLKXOR2X2TS U4485 ( .A(n3995), .B(n3994), .Y(n4129) );
INVX2TS U4486 ( .A(n3955), .Y(n3957) );
XOR2X1TS U4487 ( .A(n3988), .B(n3987), .Y(n4467) );
XNOR2X1TS U4488 ( .A(n4014), .B(n3972), .Y(n4166) );
ADDHXLTS U4489 ( .A(n3990), .B(n3989), .CO(n3998), .S(n4036) );
ADDFX2TS U4490 ( .A(n10286), .B(n10285), .CI(n10284), .CO(n10299), .S(n10307) );
NOR2X1TS U4491 ( .A(n4870), .B(n4869), .Y(n5005) );
NOR2X2TS U4492 ( .A(n1713), .B(n1948), .Y(n4851) );
NOR2X2TS U4493 ( .A(n1949), .B(n1948), .Y(n4850) );
INVX4TS U4494 ( .A(n5634), .Y(n6071) );
XOR2X1TS U4495 ( .A(n5633), .B(n735), .Y(n5634) );
AOI21X1TS U4496 ( .A0(n5639), .A1(n5640), .B0(n5632), .Y(n5633) );
OAI22X1TS U4497 ( .A0(n2105), .A1(n2034), .B0(n2170), .B1(n2033), .Y(n2078)
);
NOR2X1TS U4498 ( .A(n10239), .B(n2098), .Y(n1992) );
NOR2XLTS U4499 ( .A(n10239), .B(n2048), .Y(n4282) );
INVX2TS U4500 ( .A(n1892), .Y(n2048) );
XNOR2X1TS U4501 ( .A(n2239), .B(n2238), .Y(n2240) );
NAND2X1TS U4502 ( .A(n1031), .B(n2309), .Y(n2238) );
INVX2TS U4503 ( .A(n9934), .Y(n9965) );
INVX2TS U4504 ( .A(n9933), .Y(n9966) );
OAI22X1TS U4505 ( .A0(n3349), .A1(n3278), .B0(n3256), .B1(n3257), .Y(n3264)
);
OAI22X1TS U4506 ( .A0(n3258), .A1(n3257), .B0(n3279), .B1(n3350), .Y(n3262)
);
INVX2TS U4507 ( .A(n3109), .Y(n3354) );
NOR2X1TS U4508 ( .A(n2342), .B(n2530), .Y(n2242) );
OAI22X1TS U4509 ( .A0(n2509), .A1(n2524), .B0(n2342), .B1(n2531), .Y(n2241)
);
INVX2TS U4510 ( .A(n10041), .Y(n10062) );
INVX2TS U4511 ( .A(n10031), .Y(n10054) );
NAND2X2TS U4512 ( .A(Op_MX[32]), .B(Op_MX[5]), .Y(n1704) );
INVX2TS U4513 ( .A(n1700), .Y(n1614) );
OAI22X1TS U4514 ( .A0(n9960), .A1(n2799), .B0(n9959), .B1(n2744), .Y(n2720)
);
NOR2X2TS U4515 ( .A(Op_MX[19]), .B(Op_MX[5]), .Y(n2473) );
INVX2TS U4516 ( .A(n2474), .Y(n2481) );
INVX2TS U4517 ( .A(n7686), .Y(n8018) );
INVX4TS U4518 ( .A(n7699), .Y(n7898) );
XNOR2X1TS U4519 ( .A(n7698), .B(n7697), .Y(n7699) );
NAND2X1TS U4520 ( .A(n7696), .B(n7695), .Y(n7697) );
INVX4TS U4521 ( .A(n7682), .Y(n8017) );
XOR2X1TS U4522 ( .A(n7681), .B(n7680), .Y(n7682) );
NAND2X1TS U4523 ( .A(n7679), .B(n7678), .Y(n7680) );
INVX2TS U4524 ( .A(n7677), .Y(n7679) );
ADDHXLTS U4525 ( .A(Op_MX[37]), .B(Op_MX[30]), .CO(n7654), .S(n7661) );
AOI21X1TS U4526 ( .A0(n799), .A1(n5216), .B0(n5114), .Y(n5115) );
NAND2X1TS U4527 ( .A(n799), .B(n940), .Y(n5116) );
INVX2TS U4528 ( .A(n5217), .Y(n5114) );
ADDFX2TS U4529 ( .A(n4999), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .CI(n4998), .CO(n5133), .S(n5118) );
XOR2X1TS U4530 ( .A(n3912), .B(n3911), .Y(n4999) );
NAND2X1TS U4531 ( .A(n3910), .B(n5124), .Y(n3912) );
XNOR2X1TS U4532 ( .A(n3909), .B(n3908), .Y(n5134) );
NAND2X1TS U4533 ( .A(n3907), .B(n5123), .Y(n3908) );
ADDFX2TS U4534 ( .A(n4795), .B(n4159), .CI(n4158), .CO(n4182), .S(n4162) );
INVX2TS U4535 ( .A(n4796), .Y(n4159) );
NAND2X1TS U4536 ( .A(n1037), .B(n4130), .Y(n4123) );
XNOR2X1TS U4537 ( .A(n4133), .B(n972), .Y(n4134) );
OAI22X1TS U4538 ( .A0(n4688), .A1(n4629), .B0(n4672), .B1(n4630), .Y(n4198)
);
ADDHXLTS U4539 ( .A(n4167), .B(n4166), .CO(n4165), .S(n4168) );
INVX2TS U4540 ( .A(n4142), .Y(n4052) );
XOR2X1TS U4541 ( .A(n3917), .B(n3916), .Y(n5089) );
NAND2X1TS U4542 ( .A(n3915), .B(n3914), .Y(n3917) );
NOR2X2TS U4543 ( .A(n4513), .B(n4084), .Y(n4698) );
OAI22X1TS U4544 ( .A0(n907), .A1(n4629), .B0(n4714), .B1(n4630), .Y(n4176)
);
NOR2X1TS U4545 ( .A(n810), .B(n8096), .Y(n8012) );
INVX2TS U4546 ( .A(n7693), .Y(n7704) );
INVX2TS U4547 ( .A(n7685), .Y(n7847) );
NAND2X1TS U4548 ( .A(Op_MY[35]), .B(Op_MY[28]), .Y(n7688) );
ADDHXLTS U4549 ( .A(Op_MX[35]), .B(Op_MX[28]), .CO(n7672), .S(n7684) );
NOR2X1TS U4550 ( .A(n4070), .B(n4052), .Y(n4000) );
XNOR2X1TS U4551 ( .A(n4881), .B(n4880), .Y(n4884) );
INVX2TS U4552 ( .A(n5042), .Y(n4872) );
NOR2X2TS U4553 ( .A(n4874), .B(n4873), .Y(n5053) );
NAND2X1TS U4554 ( .A(n4874), .B(n4873), .Y(n5054) );
OAI22X1TS U4555 ( .A0(n6861), .A1(n6854), .B0(n2659), .B1(n882), .Y(n6862)
);
NOR2X2TS U4556 ( .A(n6870), .B(n6869), .Y(n10085) );
OAI22X1TS U4557 ( .A0(n6854), .A1(n6878), .B0(n882), .B1(n6853), .Y(n6880)
);
NOR2X1TS U4558 ( .A(n6861), .B(n882), .Y(n6875) );
ADDHX1TS U4559 ( .A(n3251), .B(n3250), .CO(n3301), .S(n3595) );
OAI22X1TS U4560 ( .A0(n3203), .A1(n3346), .B0(n3202), .B1(n879), .Y(n3250)
);
OAI22X1TS U4561 ( .A0(n3200), .A1(n879), .B0(n3346), .B1(n3345), .Y(n3251)
);
INVX2TS U4562 ( .A(n3347), .Y(n3430) );
AO21XLTS U4563 ( .A0(n3346), .A1(n879), .B0(n3345), .Y(n3433) );
NOR2X1TS U4564 ( .A(n2081), .B(n2048), .Y(n1956) );
NOR2X1TS U4565 ( .A(n4266), .B(n2174), .Y(n1957) );
OAI22X1TS U4566 ( .A0(n10184), .A1(n2105), .B0(n2169), .B1(n2041), .Y(n1976)
);
OAI22X1TS U4567 ( .A0(n10246), .A1(n2034), .B0(n2041), .B1(n2033), .Y(n1977)
);
NOR2XLTS U4568 ( .A(n10239), .B(n4304), .Y(n4395) );
NOR2XLTS U4569 ( .A(n10239), .B(n4266), .Y(n4317) );
NOR2X2TS U4570 ( .A(n10280), .B(n10270), .Y(n4385) );
NOR2X2TS U4571 ( .A(n4301), .B(n4300), .Y(n4383) );
OAI22X1TS U4572 ( .A0(n6055), .A1(n6071), .B0(n6042), .B1(n6083), .Y(n6053)
);
OAI21X1TS U4573 ( .A0(n6200), .A1(n6197), .B0(n6198), .Y(n6192) );
INVX2TS U4574 ( .A(n1927), .Y(n4444) );
OAI21X1TS U4575 ( .A0(n3862), .A1(n3859), .B0(n3860), .Y(n3610) );
OAI22X1TS U4576 ( .A0(n3199), .A1(n3346), .B0(n3152), .B1(n879), .Y(n3206)
);
OAI22X1TS U4577 ( .A0(n3207), .A1(n3255), .B0(n3124), .B1(n3280), .Y(n3205)
);
OAI22X1TS U4578 ( .A0(n3153), .A1(n3346), .B0(n3174), .B1(n879), .Y(n3183)
);
OAI22X1TS U4579 ( .A0(n3153), .A1(n879), .B0(n3152), .B1(n3346), .Y(n3179)
);
INVX2TS U4580 ( .A(n2473), .Y(n2477) );
NAND2X1TS U4581 ( .A(Op_MX[18]), .B(Op_MX[4]), .Y(n2405) );
INVX2TS U4582 ( .A(n2396), .Y(n2403) );
INVX2TS U4583 ( .A(n2397), .Y(n2404) );
ADDHXLTS U4584 ( .A(n2584), .B(n2583), .CO(n2592), .S(n2581) );
ADDHXLTS U4585 ( .A(n7715), .B(n7714), .CO(n7673), .S(n7738) );
OAI22X1TS U4586 ( .A0(n8083), .A1(n8081), .B0(n814), .B1(n8036), .Y(n8076)
);
OAI22X1TS U4587 ( .A0(n8093), .A1(n8050), .B0(n8082), .B1(n8083), .Y(n8070)
);
NOR2X1TS U4588 ( .A(n814), .B(n8081), .Y(n8095) );
NAND2X1TS U4589 ( .A(n7668), .B(Op_MY[33]), .Y(n7671) );
NAND2X1TS U4590 ( .A(n7669), .B(Op_MY[33]), .Y(n7670) );
OAI22X1TS U4591 ( .A0(n8093), .A1(n8083), .B0(n8082), .B1(n814), .Y(n8097)
);
XNOR2X1TS U4592 ( .A(n8095), .B(n8094), .Y(n8098) );
NOR2X1TS U4593 ( .A(n4951), .B(n4950), .Y(n4973) );
OAI22X1TS U4594 ( .A0(n1429), .A1(n2198), .B0(n1390), .B1(n2190), .Y(n1369)
);
OAI22X1TS U4595 ( .A0(n2194), .A1(n1389), .B0(n2195), .B1(n1428), .Y(n1370)
);
OAI22X1TS U4596 ( .A0(n1390), .A1(n2189), .B0(n1391), .B1(n1381), .Y(n1371)
);
ADDHXLTS U4597 ( .A(n1347), .B(n1346), .CO(n1372), .S(n1350) );
OAI22X1TS U4598 ( .A0(n2195), .A1(n1389), .B0(n2199), .B1(n1428), .Y(n1346)
);
ADDHXLTS U4599 ( .A(n1362), .B(n1361), .CO(n1409), .S(n1373) );
OAI22X1TS U4600 ( .A0(n4964), .A1(n4756), .B0(n4942), .B1(n4911), .Y(n4892)
);
ADDHXLTS U4601 ( .A(n7742), .B(n7741), .CO(n7739), .S(n7773) );
ADDHXLTS U4602 ( .A(n7758), .B(n7757), .CO(n7752), .S(n7831) );
ADDHXLTS U4603 ( .A(n1345), .B(n1344), .CO(n1349), .S(n1329) );
OAI22X1TS U4604 ( .A0(n2195), .A1(n1383), .B0(n2199), .B1(n1382), .Y(n1344)
);
INVX2TS U4605 ( .A(n1292), .Y(n1383) );
ADDHX1TS U4606 ( .A(Op_MX[48]), .B(Op_MX[21]), .CO(n4117), .S(n4150) );
INVX2TS U4607 ( .A(n1288), .Y(n1315) );
INVX2TS U4608 ( .A(n1323), .Y(n1332) );
NAND2X1TS U4609 ( .A(Op_MY[50]), .B(Op_MY[23]), .Y(n1334) );
NAND2X1TS U4610 ( .A(n3899), .B(n3898), .Y(n4882) );
XNOR2X1TS U4611 ( .A(n1929), .B(n1688), .Y(n1689) );
NAND2X1TS U4612 ( .A(n1687), .B(n1686), .Y(n1688) );
INVX2TS U4613 ( .A(n1685), .Y(n1687) );
XNOR2X1TS U4614 ( .A(n1604), .B(n1603), .Y(n1605) );
NAND2X1TS U4615 ( .A(n1609), .B(n1608), .Y(n1611) );
NAND2X1TS U4616 ( .A(n1630), .B(n1629), .Y(n1631) );
INVX2TS U4617 ( .A(n1628), .Y(n1630) );
XNOR2X1TS U4618 ( .A(n1625), .B(n1624), .Y(n1626) );
NAND2X1TS U4619 ( .A(n915), .B(n1623), .Y(n1625) );
XOR2X1TS U4620 ( .A(n1546), .B(n1634), .Y(n1547) );
NAND2X1TS U4621 ( .A(n1450), .B(n1633), .Y(n1546) );
INVX2TS U4622 ( .A(n1635), .Y(n1450) );
INVX2TS U4623 ( .A(n1710), .Y(n5181) );
OAI22X1TS U4624 ( .A0(n5177), .A1(n5182), .B0(n5149), .B1(n1636), .Y(n5179)
);
INVX2TS U4625 ( .A(n1714), .Y(n5462) );
ADDFX2TS U4626 ( .A(n5146), .B(n5145), .CI(n5144), .CO(n10124), .S(n5130) );
OAI22X1TS U4627 ( .A0(n5462), .A1(n2000), .B0(n5181), .B1(n5147), .Y(n5146)
);
INVX2TS U4628 ( .A(n8218), .Y(n7837) );
INVX2TS U4629 ( .A(n5477), .Y(n5172) );
XNOR2X1TS U4630 ( .A(n4112), .B(n1289), .Y(n1290) );
NAND2X1TS U4631 ( .A(n1147), .B(n1288), .Y(n1289) );
INVX2TS U4632 ( .A(n7767), .Y(n7877) );
NOR2XLTS U4633 ( .A(n4942), .B(n4714), .Y(n4732) );
INVX2TS U4634 ( .A(n9389), .Y(n5198) );
CMPR42X1TS U4635 ( .A(DP_OP_342J35_126_4270_n326), .B(
DP_OP_342J35_126_4270_n318), .C(DP_OP_342J35_126_4270_n302), .D(
DP_OP_342J35_126_4270_n310), .ICI(DP_OP_342J35_126_4270_n173), .S(
DP_OP_342J35_126_4270_n163), .ICO(DP_OP_342J35_126_4270_n161), .CO(
DP_OP_342J35_126_4270_n162) );
OAI22X1TS U4636 ( .A0(n9844), .A1(n9830), .B0(n9843), .B1(n9831), .Y(
DP_OP_342J35_126_4270_n310) );
OAI22X1TS U4637 ( .A0(n9844), .A1(n881), .B0(n9845), .B1(n9829), .Y(
DP_OP_342J35_126_4270_n302) );
XNOR2X1TS U4638 ( .A(Op_MY[48]), .B(Op_MX[50]), .Y(n7254) );
ADDHXLTS U4639 ( .A(n7089), .B(n7088), .CO(n7107), .S(n7091) );
INVX2TS U4640 ( .A(n9791), .Y(n9797) );
INVX2TS U4641 ( .A(n9792), .Y(n9796) );
ADDHX1TS U4642 ( .A(n9801), .B(n9800), .CO(n9798), .S(
DP_OP_342J35_126_4270_n246) );
NOR2X1TS U4643 ( .A(n9841), .B(n9831), .Y(n9801) );
INVX2TS U4644 ( .A(n9794), .Y(n9800) );
INVX2TS U4645 ( .A(n9816), .Y(n9818) );
ADDHXLTS U4646 ( .A(Op_MX[42]), .B(Op_MX[49]), .CO(n9803), .S(n9802) );
CMPR42X1TS U4647 ( .A(DP_OP_342J35_126_4270_n295), .B(
DP_OP_342J35_126_4270_n180), .C(DP_OP_342J35_126_4270_n303), .D(
DP_OP_342J35_126_4270_n335), .ICI(DP_OP_342J35_126_4270_n190), .S(
DP_OP_342J35_126_4270_n178), .ICO(DP_OP_342J35_126_4270_n176), .CO(
DP_OP_342J35_126_4270_n177) );
OAI22X1TS U4648 ( .A0(n9845), .A1(n881), .B0(n9849), .B1(n9829), .Y(
DP_OP_342J35_126_4270_n303) );
NOR2X1TS U4649 ( .A(n9849), .B(n729), .Y(DP_OP_342J35_126_4270_n295) );
ADDHXLTS U4650 ( .A(n9790), .B(n9789), .CO(DP_OP_342J35_126_4270_n221), .S(
DP_OP_342J35_126_4270_n222) );
INVX2TS U4651 ( .A(n9788), .Y(n9789) );
INVX2TS U4652 ( .A(n9766), .Y(n9830) );
CMPR42X1TS U4653 ( .A(DP_OP_342J35_126_4270_n234), .B(
DP_OP_342J35_126_4270_n398), .C(DP_OP_342J35_126_4270_n314), .D(
DP_OP_342J35_126_4270_n306), .ICI(DP_OP_342J35_126_4270_n346), .S(
DP_OP_342J35_126_4270_n220), .ICO(DP_OP_342J35_126_4270_n218), .CO(
DP_OP_342J35_126_4270_n219) );
OAI22X1TS U4654 ( .A0(n881), .A1(n9840), .B0(n9829), .B1(n9841), .Y(
DP_OP_342J35_126_4270_n306) );
OAI22X1TS U4655 ( .A0(n9847), .A1(n9831), .B0(n9840), .B1(n9830), .Y(
DP_OP_342J35_126_4270_n314) );
OAI22X1TS U4656 ( .A0(n9844), .A1(n9846), .B0(n9843), .B1(n9848), .Y(
DP_OP_342J35_126_4270_n346) );
CMPR42X1TS U4657 ( .A(DP_OP_342J35_126_4270_n222), .B(
DP_OP_342J35_126_4270_n322), .C(DP_OP_342J35_126_4270_n279), .D(
DP_OP_342J35_126_4270_n232), .ICI(DP_OP_342J35_126_4270_n226), .S(
DP_OP_342J35_126_4270_n217), .ICO(DP_OP_342J35_126_4270_n215), .CO(
DP_OP_342J35_126_4270_n216) );
OAI22X1TS U4658 ( .A0(n9849), .A1(n9834), .B0(n9833), .B1(n9847), .Y(
DP_OP_342J35_126_4270_n322) );
INVX2TS U4659 ( .A(n9861), .Y(DP_OP_342J35_126_4270_n279) );
INVX2TS U4660 ( .A(n9783), .Y(n9786) );
INVX2TS U4661 ( .A(n9784), .Y(n9785) );
INVX2TS U4662 ( .A(n9778), .Y(n9782) );
INVX2TS U4663 ( .A(n9779), .Y(n9781) );
INVX4TS U4664 ( .A(n9812), .Y(n9843) );
XNOR2X1TS U4665 ( .A(n9811), .B(n730), .Y(n9812) );
NAND2X1TS U4666 ( .A(n9813), .B(n764), .Y(n9811) );
CMPR42X1TS U4667 ( .A(DP_OP_342J35_126_4270_n304), .B(
DP_OP_342J35_126_4270_n312), .C(DP_OP_342J35_126_4270_n344), .D(
DP_OP_342J35_126_4270_n275), .ICI(DP_OP_342J35_126_4270_n198), .S(
DP_OP_342J35_126_4270_n192), .ICO(DP_OP_342J35_126_4270_n190), .CO(
DP_OP_342J35_126_4270_n191) );
OAI22X1TS U4668 ( .A0(n9845), .A1(n9831), .B0(n9849), .B1(n9830), .Y(
DP_OP_342J35_126_4270_n312) );
OAI22X1TS U4669 ( .A0(n9849), .A1(n881), .B0(n9847), .B1(n9829), .Y(
DP_OP_342J35_126_4270_n304) );
INVX4TS U4670 ( .A(n9814), .Y(n9844) );
XOR2X1TS U4671 ( .A(n9813), .B(Op_MY[45]), .Y(n9814) );
NOR2X1TS U4672 ( .A(DP_OP_342J35_126_4270_n748), .B(n749), .Y(n7079) );
NOR2X1TS U4673 ( .A(n761), .B(n748), .Y(n7078) );
INVX2TS U4674 ( .A(n9765), .Y(n9768) );
CMPR42X1TS U4675 ( .A(DP_OP_342J35_126_4270_n292), .B(
DP_OP_342J35_126_4270_n300), .C(DP_OP_342J35_126_4270_n153), .D(
DP_OP_342J35_126_4270_n142), .ICI(DP_OP_342J35_126_4270_n147), .S(
DP_OP_342J35_126_4270_n140), .ICO(DP_OP_342J35_126_4270_n138), .CO(
DP_OP_342J35_126_4270_n139) );
NOR2X1TS U4676 ( .A(n9843), .B(n729), .Y(DP_OP_342J35_126_4270_n292) );
CMPR42X1TS U4677 ( .A(DP_OP_342J35_126_4270_n309), .B(
DP_OP_342J35_126_4270_n268), .C(DP_OP_342J35_126_4270_n154), .D(
DP_OP_342J35_126_4270_n161), .ICI(DP_OP_342J35_126_4270_n162), .S(
DP_OP_342J35_126_4270_n149), .ICO(DP_OP_342J35_126_4270_n147), .CO(
DP_OP_342J35_126_4270_n148) );
INVX2TS U4678 ( .A(n9850), .Y(DP_OP_342J35_126_4270_n268) );
CMPR42X1TS U4679 ( .A(DP_OP_342J35_126_4270_n269), .B(
DP_OP_342J35_126_4270_n293), .C(DP_OP_342J35_126_4270_n301), .D(
DP_OP_342J35_126_4270_n164), .ICI(DP_OP_342J35_126_4270_n165), .S(
DP_OP_342J35_126_4270_n152), .ICO(DP_OP_342J35_126_4270_n150), .CO(
DP_OP_342J35_126_4270_n151) );
INVX2TS U4680 ( .A(n9851), .Y(DP_OP_342J35_126_4270_n269) );
OAI22X1TS U4681 ( .A0(n9844), .A1(n9829), .B0(n9843), .B1(n881), .Y(
DP_OP_342J35_126_4270_n301) );
NOR2X1TS U4682 ( .A(n9844), .B(n729), .Y(DP_OP_342J35_126_4270_n293) );
CMPR42X1TS U4683 ( .A(DP_OP_342J35_126_4270_n270), .B(
DP_OP_342J35_126_4270_n176), .C(DP_OP_342J35_126_4270_n166), .D(
DP_OP_342J35_126_4270_n177), .ICI(DP_OP_342J35_126_4270_n170), .S(
DP_OP_342J35_126_4270_n160), .ICO(DP_OP_342J35_126_4270_n158), .CO(
DP_OP_342J35_126_4270_n159) );
INVX2TS U4684 ( .A(n9852), .Y(DP_OP_342J35_126_4270_n270) );
INVX2TS U4685 ( .A(n1327), .Y(n1389) );
OAI22X1TS U4686 ( .A0(n1429), .A1(n1382), .B0(n880), .B1(n1383), .Y(n1378)
);
INVX4TS U4687 ( .A(n1342), .Y(n1390) );
XOR2X1TS U4688 ( .A(n1341), .B(Op_MY[25]), .Y(n1342) );
OAI22X1TS U4689 ( .A0(n1429), .A1(n1389), .B0(n1390), .B1(n1428), .Y(n1388)
);
OAI22X1TS U4690 ( .A0(n1391), .A1(Op_MX[25]), .B0(n2194), .B1(n988), .Y(
n1405) );
OAI22X1TS U4691 ( .A0(n1390), .A1(n1389), .B0(n1391), .B1(n1428), .Y(n1406)
);
OAI21X2TS U4692 ( .A0(n1340), .A1(n1339), .B0(n1338), .Y(n1365) );
INVX2TS U4693 ( .A(n1334), .Y(n1337) );
INVX2TS U4694 ( .A(n1335), .Y(n1336) );
NOR2X2TS U4695 ( .A(n1339), .B(n1333), .Y(n1363) );
NAND2X1TS U4696 ( .A(n3976), .B(n1028), .Y(n1283) );
AOI21X1TS U4697 ( .A0(n3975), .A1(n1028), .B0(n1281), .Y(n1282) );
INVX4TS U4698 ( .A(n1354), .Y(n1429) );
XOR2X1TS U4699 ( .A(n1353), .B(n934), .Y(n1354) );
NAND2X1TS U4700 ( .A(n1351), .B(n1032), .Y(n1352) );
NOR2X1TS U4701 ( .A(n4973), .B(n4976), .Y(n4979) );
NOR2X2TS U4702 ( .A(n4925), .B(n4928), .Y(n4974) );
NOR2X1TS U4703 ( .A(Op_MY[15]), .B(Op_MY[1]), .Y(n2275) );
OR2X2TS U4704 ( .A(Op_MY[16]), .B(Op_MY[2]), .Y(n1113) );
NAND2X1TS U4705 ( .A(n883), .B(Op_MX[1]), .Y(n2352) );
NAND2X1TS U4706 ( .A(Op_MY[15]), .B(Op_MY[1]), .Y(n2280) );
INVX2TS U4707 ( .A(n2819), .Y(n2390) );
NAND2X1TS U4708 ( .A(n2381), .B(n2288), .Y(n2391) );
OAI21X1TS U4709 ( .A0(n2285), .A1(n2382), .B0(n2383), .Y(n2392) );
NOR2X1TS U4710 ( .A(n2287), .B(n2286), .Y(n2382) );
INVX2TS U4711 ( .A(n2314), .Y(n2287) );
ADDHXLTS U4712 ( .A(n5721), .B(n5720), .CO(n5736), .S(n5722) );
NOR2X1TS U4713 ( .A(n770), .B(n848), .Y(n5732) );
NOR2XLTS U4714 ( .A(n735), .B(n837), .Y(n5733) );
NAND2X1TS U4715 ( .A(n1077), .B(n2419), .Y(n2420) );
OAI21X1TS U4716 ( .A0(n2418), .A1(n2417), .B0(n2416), .Y(n2421) );
NAND2X1TS U4717 ( .A(n2412), .B(n1022), .Y(n2417) );
NAND2X1TS U4718 ( .A(n1022), .B(n1077), .Y(n2210) );
OAI22X1TS U4719 ( .A0(n9944), .A1(n2744), .B0(n9946), .B1(n2704), .Y(n2711)
);
OAI22X1TS U4720 ( .A0(n9961), .A1(n2798), .B0(n9991), .B1(n2672), .Y(n2713)
);
OAI22X1TS U4721 ( .A0(n9948), .A1(n2704), .B0(n9947), .B1(n9994), .Y(n2710)
);
NOR2X1TS U4722 ( .A(n9961), .B(n2380), .Y(n2709) );
NAND2X1TS U4723 ( .A(n2272), .B(n2271), .Y(n2273) );
NOR2X1TS U4724 ( .A(n2876), .B(n2824), .Y(n2632) );
XNOR2X2TS U4725 ( .A(n2269), .B(n2268), .Y(n2573) );
OAI21X1TS U4726 ( .A0(n2418), .A1(n2266), .B0(n2271), .Y(n2269) );
NAND2X1TS U4727 ( .A(n1022), .B(n2261), .Y(n2262) );
NOR2X1TS U4728 ( .A(n2876), .B(n2880), .Y(n2872) );
NOR2X1TS U4729 ( .A(n2876), .B(n2894), .Y(n2878) );
OAI22X1TS U4730 ( .A0(n9927), .A1(n2744), .B0(n2797), .B1(n2704), .Y(n2701)
);
OAI22X1TS U4731 ( .A0(n9994), .A1(n2798), .B0(n2704), .B1(n2672), .Y(n2703)
);
OAI22X1TS U4732 ( .A0(n9991), .A1(n2798), .B0(n9994), .B1(n2672), .Y(n2706)
);
XOR2X1TS U4733 ( .A(n2369), .B(n2368), .Y(n2370) );
NAND2X1TS U4734 ( .A(n2367), .B(n2366), .Y(n2369) );
OAI22X1TS U4735 ( .A0(n6041), .A1(n5947), .B0(n5993), .B1(n5945), .Y(n5919)
);
OAI22X1TS U4736 ( .A0(n5993), .A1(n5947), .B0(n5888), .B1(n5945), .Y(n5925)
);
INVX2TS U4737 ( .A(n2856), .Y(n2728) );
INVX2TS U4738 ( .A(n2858), .Y(n10045) );
INVX2TS U4739 ( .A(n2859), .Y(n10059) );
INVX4TS U4740 ( .A(n2228), .Y(n2509) );
XNOR2X1TS U4741 ( .A(n2227), .B(n2226), .Y(n2228) );
NAND2X1TS U4742 ( .A(n1124), .B(n2225), .Y(n2226) );
INVX2TS U4743 ( .A(n2337), .Y(n6861) );
XNOR2X1TS U4744 ( .A(n2221), .B(n2220), .Y(n2222) );
INVX2TS U4745 ( .A(n2201), .Y(n2659) );
INVX2TS U4746 ( .A(n10021), .Y(n10050) );
INVX2TS U4747 ( .A(n9975), .Y(n10018) );
INVX2TS U4748 ( .A(n9974), .Y(n10019) );
ADDHXLTS U4749 ( .A(n3282), .B(n3281), .CO(n3044), .S(n3057) );
NAND2X1TS U4750 ( .A(n3081), .B(n3080), .Y(n3082) );
OAI22X1TS U4751 ( .A0(n3375), .A1(n3483), .B0(n3118), .B1(n3555), .Y(n3377)
);
XNOR2X1TS U4752 ( .A(n3481), .B(n753), .Y(n3378) );
XNOR2X1TS U4753 ( .A(n3421), .B(n753), .Y(n3121) );
INVX4TS U4754 ( .A(n3087), .Y(n3257) );
XNOR2X1TS U4755 ( .A(n3086), .B(n3085), .Y(n3087) );
NAND2X1TS U4756 ( .A(n1151), .B(n3084), .Y(n3086) );
INVX2TS U4757 ( .A(n3044), .Y(n3258) );
INVX2TS U4758 ( .A(n3111), .Y(n3256) );
INVX2TS U4759 ( .A(n3600), .Y(n3316) );
INVX2TS U4760 ( .A(n10117), .Y(n10071) );
AOI21X1TS U4761 ( .A0(n10100), .A1(n10077), .B0(n10076), .Y(n10082) );
AOI21X1TS U4762 ( .A0(n10100), .A1(n10084), .B0(n10083), .Y(n10089) );
CLKXOR2X2TS U4763 ( .A(n1539), .B(n1480), .Y(n3081) );
NAND2X1TS U4764 ( .A(n1479), .B(n1537), .Y(n1480) );
ADDFX2TS U4765 ( .A(n3526), .B(n3525), .CI(n3524), .CO(n3527), .S(n3338) );
OAI21X2TS U4766 ( .A0(n3798), .A1(n3794), .B0(n3795), .Y(n3690) );
XNOR2X1TS U4767 ( .A(n5158), .B(n5157), .Y(n5186) );
NAND2X1TS U4768 ( .A(n5156), .B(n5169), .Y(n5157) );
NOR2XLTS U4769 ( .A(n4896), .B(n4714), .Y(n4524) );
INVX2TS U4770 ( .A(n2429), .Y(n2485) );
NAND2X1TS U4771 ( .A(n2477), .B(n2481), .Y(n2484) );
NAND2X1TS U4772 ( .A(Op_MX[21]), .B(Op_MX[7]), .Y(n2487) );
INVX2TS U4773 ( .A(n906), .Y(n2488) );
INVX2TS U4774 ( .A(n2854), .Y(n2769) );
NOR2X2TS U4775 ( .A(n2659), .B(n2342), .Y(n2350) );
AOI21X1TS U4776 ( .A0(n3954), .A1(n1614), .B0(n1617), .Y(n1588) );
XNOR2X2TS U4777 ( .A(n2398), .B(n2404), .Y(n2471) );
NAND2X1TS U4778 ( .A(n1021), .B(n2396), .Y(n2398) );
ADDHXLTS U4779 ( .A(n2578), .B(n2577), .CO(n2583), .S(n2684) );
INVX2TS U4780 ( .A(n2513), .Y(n2303) );
NOR2X1TS U4781 ( .A(n2473), .B(n1107), .Y(n2249) );
OAI21X1TS U4782 ( .A0(n2478), .A1(n1107), .B0(n1106), .Y(n2248) );
XNOR2X1TS U4783 ( .A(n2287), .B(n2214), .Y(n2215) );
NAND2X1TS U4784 ( .A(n2216), .B(n2223), .Y(n2214) );
ADDFX2TS U4785 ( .A(n2766), .B(n2765), .CI(n2764), .CO(n10068), .S(n2816) );
INVX2TS U4786 ( .A(n2857), .Y(n2764) );
OAI22X2TS U4787 ( .A0(n6861), .A1(n2342), .B0(n2659), .B1(n2509), .Y(n6846)
);
OAI22X1TS U4788 ( .A0(n6861), .A1(n2544), .B0(n2659), .B1(n2652), .Y(n2546)
);
OAI22X1TS U4789 ( .A0(n6861), .A1(n2652), .B0(n2659), .B1(n6854), .Y(n2645)
);
NOR2X2TS U4790 ( .A(n6868), .B(n6867), .Y(n10092) );
NOR2X1TS U4791 ( .A(n6866), .B(n6865), .Y(n10090) );
NOR2X1TS U4792 ( .A(n3731), .B(n3730), .Y(n3799) );
NOR2X2TS U4793 ( .A(n4444), .B(n2173), .Y(n4294) );
NOR2X1TS U4794 ( .A(n4397), .B(n2098), .Y(n2107) );
INVX2TS U4795 ( .A(n4190), .Y(n4094) );
INVX2TS U4796 ( .A(n4551), .Y(n4512) );
INVX2TS U4797 ( .A(n4482), .Y(n4102) );
NOR2X1TS U4798 ( .A(n4772), .B(n4714), .Y(n4460) );
AOI21X1TS U4799 ( .A0(n5121), .A1(n5203), .B0(n5120), .Y(n5418) );
ADDHXLTS U4800 ( .A(n5762), .B(n5761), .CO(n5750), .S(n5790) );
NOR2X1TS U4801 ( .A(n6091), .B(n6090), .Y(n6181) );
NOR2X1TS U4802 ( .A(n4292), .B(n4291), .Y(n4359) );
NOR2X2TS U4803 ( .A(n4397), .B(n2173), .Y(n4292) );
NOR2X1TS U4804 ( .A(n3598), .B(n3597), .Y(n3859) );
AOI21X1TS U4805 ( .A0(n3689), .A1(n928), .B0(n3596), .Y(n3862) );
NAND2X1TS U4806 ( .A(n3598), .B(n3597), .Y(n3860) );
OAI22X1TS U4807 ( .A0(n10188), .A1(n2105), .B0(n10190), .B1(n2041), .Y(n2077) );
NOR2X2TS U4808 ( .A(n4308), .B(n2173), .Y(n4289) );
NOR2X2TS U4809 ( .A(n10260), .B(n10243), .Y(n4435) );
NAND2X1TS U4810 ( .A(n10214), .B(n10213), .Y(n4436) );
INVX2TS U4811 ( .A(n3429), .Y(n3502) );
NOR2X1TS U4812 ( .A(n3558), .B(n3557), .Y(n3580) );
OAI21X2TS U4813 ( .A0(n1704), .A1(n1303), .B0(n1302), .Y(n3933) );
AOI21X1TS U4814 ( .A0(n1701), .A1(n1117), .B0(n1301), .Y(n1302) );
NOR2X2TS U4815 ( .A(n1700), .B(n1303), .Y(n3932) );
INVX2TS U4816 ( .A(n4858), .Y(n4586) );
NAND2X1TS U4817 ( .A(n10174), .B(n10173), .Y(n4861) );
XNOR2X2TS U4818 ( .A(n4595), .B(n4594), .Y(n4599) );
OAI21X1TS U4819 ( .A0(n4868), .A1(n4588), .B0(n4587), .Y(n4595) );
AOI21X1TS U4820 ( .A0(n3954), .A1(n3937), .B0(n3936), .Y(n3940) );
CLKXOR2X2TS U4821 ( .A(n4033), .B(n4032), .Y(n4120) );
OAI22X1TS U4822 ( .A0(n10247), .A1(n2170), .B0(n10245), .B1(n2105), .Y(n2144) );
ADDFX2TS U4823 ( .A(n2141), .B(n2140), .CI(n2139), .CO(n2133), .S(n5020) );
NAND2X1TS U4824 ( .A(n4870), .B(n4869), .Y(n5015) );
INVX2TS U4825 ( .A(n4129), .Y(n4030) );
NOR2X2TS U4826 ( .A(n1125), .B(n1094), .Y(n5007) );
INVX2TS U4827 ( .A(n5005), .Y(n5016) );
NAND2X1TS U4828 ( .A(n1125), .B(n1094), .Y(n5008) );
INVX2TS U4829 ( .A(n4137), .Y(n4074) );
ADDHXLTS U4830 ( .A(n4029), .B(n4028), .CO(n4035), .S(n4073) );
ADDHXLTS U4831 ( .A(n7543), .B(n7542), .CO(n7556), .S(n7545) );
INVX2TS U4832 ( .A(n4467), .Y(n4090) );
INVX2TS U4833 ( .A(n4166), .Y(n4070) );
ADDFX2TS U4834 ( .A(n2135), .B(n2134), .CI(n2133), .CO(n5046), .S(n5014) );
NAND2X1TS U4835 ( .A(n1056), .B(n4871), .Y(n5042) );
AOI21X1TS U4836 ( .A0(n5052), .A1(n5051), .B0(n5050), .Y(n5057) );
OAI22X1TS U4837 ( .A0(n2041), .A1(n2034), .B0(n2105), .B1(n2033), .Y(n1972)
);
NAND2X1TS U4838 ( .A(n10280), .B(n10270), .Y(n4386) );
OAI21X1TS U4839 ( .A0(n4384), .A1(n4383), .B0(n4382), .Y(n4389) );
INVX2TS U4840 ( .A(n4850), .Y(n2172) );
INVX2TS U4841 ( .A(n4368), .Y(n4297) );
NAND2X1TS U4842 ( .A(n4299), .B(n4298), .Y(n4372) );
CLKAND2X2TS U4843 ( .A(n1162), .B(n821), .Y(n911) );
OAI22X1TS U4844 ( .A0(n6071), .A1(n6082), .B0(n6083), .B1(n6059), .Y(n6080)
);
NOR2X1TS U4845 ( .A(n6083), .B(n6082), .Y(n6102) );
NOR2X1TS U4846 ( .A(n6083), .B(n731), .Y(n6105) );
XNOR2X1TS U4847 ( .A(n6102), .B(n6292), .Y(n6104) );
NOR2X1TS U4848 ( .A(n3606), .B(n3605), .Y(n3641) );
INVX2TS U4849 ( .A(n4383), .Y(n4377) );
INVX2TS U4850 ( .A(n4376), .Y(n4384) );
NAND2X1TS U4851 ( .A(n4301), .B(n4300), .Y(n4382) );
NOR2X1TS U4852 ( .A(n3593), .B(n3592), .Y(n3827) );
NOR2X2TS U4853 ( .A(n2082), .B(n2173), .Y(n4284) );
ADDHX1TS U4854 ( .A(n1975), .B(n1974), .CO(n1986), .S(n4283) );
NOR2X1TS U4855 ( .A(n2081), .B(n2098), .Y(n1974) );
NOR2X1TS U4856 ( .A(n2174), .B(n2048), .Y(n1975) );
OAI22X1TS U4857 ( .A0(n6861), .A1(n2545), .B0(n2659), .B1(n2544), .Y(n2556)
);
NOR2X2TS U4858 ( .A(n6850), .B(n6849), .Y(n10102) );
NOR2XLTS U4859 ( .A(n3354), .B(n3278), .Y(n3270) );
ADDHXLTS U4860 ( .A(n5657), .B(n5656), .CO(n5653), .S(n5686) );
OAI22X1TS U4861 ( .A0(n2545), .A1(n2508), .B0(n2509), .B1(n2523), .Y(n2254)
);
NAND2X1TS U4862 ( .A(n1614), .B(n1704), .Y(n1558) );
INVX4TS U4863 ( .A(n3396), .Y(n900) );
NOR2X2TS U4864 ( .A(n9902), .B(n9893), .Y(n2909) );
NOR2X2TS U4865 ( .A(n9995), .B(n839), .Y(n9893) );
INVX2TS U4866 ( .A(n2852), .Y(n2778) );
OAI22X1TS U4867 ( .A0(n2704), .A1(n2798), .B0(n2744), .B1(n2672), .Y(n2455)
);
ADDHXLTS U4868 ( .A(Op_MX[22]), .B(n883), .CO(n5635), .S(n5637) );
XNOR2X2TS U4869 ( .A(n2476), .B(n2475), .Y(n2615) );
NAND2X1TS U4870 ( .A(n2481), .B(n2479), .Y(n2475) );
OAI21X1TS U4871 ( .A0(n2485), .A1(n2473), .B0(n2478), .Y(n2476) );
NOR2X1TS U4872 ( .A(n2831), .B(n2824), .Y(n2587) );
OAI22X1TS U4873 ( .A0(n7910), .A1(n7847), .B0(n7943), .B1(n8018), .Y(n7892)
);
NOR2X1TS U4874 ( .A(n740), .B(n757), .Y(n8041) );
OAI22X1TS U4875 ( .A0(n8017), .A1(n7909), .B0(n7898), .B1(n7908), .Y(n7885)
);
INVX2TS U4876 ( .A(n7661), .Y(n7998) );
NOR2X2TS U4877 ( .A(n5118), .B(n5117), .Y(n5399) );
NAND2X1TS U4878 ( .A(n5118), .B(n5117), .Y(n5398) );
OAI22X1TS U4879 ( .A0(n4627), .A1(n4714), .B0(n4628), .B1(n907), .Y(n4215)
);
OAI22X1TS U4880 ( .A0(n4648), .A1(n4714), .B0(n4649), .B1(n907), .Y(n4201)
);
NAND2X1TS U4881 ( .A(n5113), .B(n5112), .Y(n5217) );
INVX2TS U4882 ( .A(n5220), .Y(n5216) );
NOR2X1TS U4883 ( .A(n4715), .B(n4698), .Y(n4249) );
NAND2X1TS U4884 ( .A(n4715), .B(n4698), .Y(n4250) );
AOI21X1TS U4885 ( .A0(n818), .A1(n4325), .B0(n4080), .Y(n4252) );
INVX2TS U4886 ( .A(n4324), .Y(n4080) );
ADDFX2TS U4887 ( .A(n4083), .B(n4082), .CI(n4081), .CO(n4668), .S(n4715) );
NOR2X1TS U4888 ( .A(n4628), .B(n4714), .Y(n4224) );
NAND2X1TS U4889 ( .A(n4112), .B(n4111), .Y(n4121) );
NOR2X1TS U4890 ( .A(n4112), .B(n4111), .Y(n4122) );
NOR2X1TS U4891 ( .A(n742), .B(n740), .Y(n8014) );
INVX2TS U4892 ( .A(n7719), .Y(n7908) );
NOR2XLTS U4893 ( .A(n7943), .B(n7847), .Y(n7904) );
INVX4TS U4894 ( .A(n7692), .Y(n7910) );
XOR2X1TS U4895 ( .A(n7691), .B(n7690), .Y(n7692) );
INVX2TS U4896 ( .A(n4531), .Y(n4098) );
INVX2TS U4897 ( .A(n4665), .Y(n4513) );
NAND2X1TS U4898 ( .A(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .B(n4884), .Y(n5074) );
NOR2X2TS U4899 ( .A(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .B(n4884), .Y(n5075) );
NOR2X1TS U4900 ( .A(n742), .B(n811), .Y(n7795) );
ADDHX1TS U4901 ( .A(n5764), .B(n5763), .CO(n5789), .S(n6311) );
NOR2X2TS U4902 ( .A(n5972), .B(n5971), .Y(n6304) );
NAND2X1TS U4903 ( .A(n5972), .B(n5971), .Y(n6305) );
NOR2X2TS U4904 ( .A(n5970), .B(n5969), .Y(n6302) );
NAND2X1TS U4905 ( .A(n5970), .B(n5969), .Y(n6301) );
AOI21X1TS U4906 ( .A0(n6852), .A1(n10101), .B0(n6851), .Y(n10073) );
NAND2X1TS U4907 ( .A(n6870), .B(n6869), .Y(n10086) );
NOR2X2TS U4908 ( .A(n9885), .B(n9884), .Y(n10078) );
NAND2X1TS U4909 ( .A(n9885), .B(n9884), .Y(n10079) );
NOR2X2TS U4910 ( .A(n10090), .B(n10092), .Y(n10084) );
OAI21X2TS U4911 ( .A0(n10092), .A1(n10097), .B0(n10093), .Y(n10083) );
NOR2X1TS U4912 ( .A(n10085), .B(n10078), .Y(n6872) );
NOR2X1TS U4913 ( .A(n882), .B(n6878), .Y(n9890) );
NOR2X1TS U4914 ( .A(n882), .B(n737), .Y(n9889) );
OR2X1TS U4915 ( .A(n3595), .B(n3594), .Y(n928) );
OAI21X1TS U4916 ( .A0(n3827), .A1(n3830), .B0(n3828), .Y(n3689) );
AOI21X1TS U4917 ( .A0(n3604), .A1(n3610), .B0(n3603), .Y(n3670) );
OAI22X1TS U4918 ( .A0(n3430), .A1(n3557), .B0(n3502), .B1(n3501), .Y(n3486)
);
NOR2X1TS U4919 ( .A(n964), .B(n1184), .Y(n5419) );
NOR2XLTS U4920 ( .A(n2082), .B(n2098), .Y(n1985) );
NOR2X2TS U4921 ( .A(n4273), .B(n2173), .Y(n4286) );
NAND2X1TS U4922 ( .A(n10260), .B(n10243), .Y(n4437) );
NOR2X1TS U4923 ( .A(n4383), .B(n4385), .Y(n4303) );
OAI21X1TS U4924 ( .A0(n4385), .A1(n4382), .B0(n4386), .Y(n4302) );
AOI21X1TS U4925 ( .A0(n5974), .A1(n6192), .B0(n5973), .Y(n6149) );
NAND2X1TS U4926 ( .A(n6095), .B(n6094), .Y(n6174) );
NOR2X2TS U4927 ( .A(n6095), .B(n6094), .Y(n6173) );
OAI21X2TS U4928 ( .A0(n6183), .A1(n6315), .B0(n6184), .Y(n6171) );
NOR2X2TS U4929 ( .A(n6181), .B(n6183), .Y(n6172) );
NOR2X2TS U4930 ( .A(n10239), .B(n2173), .Y(n4295) );
ADDFX2TS U4931 ( .A(n2123), .B(n2122), .CI(n2121), .CO(n4298), .S(n4296) );
NOR2X1TS U4932 ( .A(n4444), .B(n2098), .Y(n2122) );
NOR2X1TS U4933 ( .A(n4294), .B(n4293), .Y(n4364) );
NAND2X1TS U4934 ( .A(n3571), .B(n3570), .Y(n3608) );
NAND2X1TS U4935 ( .A(n3600), .B(n3599), .Y(n3847) );
NAND2X1TS U4936 ( .A(n3589), .B(n3588), .Y(n3616) );
NAND2X1TS U4937 ( .A(n2477), .B(n2478), .Y(n2430) );
NAND2X1TS U4938 ( .A(n1023), .B(n2405), .Y(n2406) );
AOI21X1TS U4939 ( .A0(n2404), .A1(n1021), .B0(n2403), .Y(n2407) );
ADDHXLTS U4940 ( .A(n9680), .B(n9679), .CO(n9543), .S(
DP_OP_341J35_125_6458_n84) );
NOR2XLTS U4941 ( .A(n9653), .B(n9681), .Y(n9671) );
ADDHXLTS U4942 ( .A(n9684), .B(n9683), .CO(DP_OP_341J35_125_6458_n104), .S(
DP_OP_341J35_125_6458_n105) );
NOR2X1TS U4943 ( .A(n809), .B(n741), .Y(n7674) );
OAI22X1TS U4944 ( .A0(n9607), .A1(n9615), .B0(n9613), .B1(n9602), .Y(n7450)
);
INVX2TS U4945 ( .A(n8289), .Y(n8091) );
NOR2X2TS U4946 ( .A(n4969), .B(n4968), .Y(n4976) );
AOI21X1TS U4947 ( .A0(n4980), .A1(n4955), .B0(n4954), .Y(n4956) );
INVX2TS U4948 ( .A(n4977), .Y(n4954) );
NAND2X1TS U4949 ( .A(n4974), .B(n4955), .Y(n4957) );
NOR2X1TS U4950 ( .A(n814), .B(n8096), .Y(n8115) );
XNOR2X1TS U4951 ( .A(n8116), .B(n8115), .Y(n8118) );
INVX2TS U4952 ( .A(n4973), .Y(n4955) );
OAI21X2TS U4953 ( .A0(n4928), .A1(n4927), .B0(n4926), .Y(n4980) );
OAI22X1TS U4954 ( .A0(n2194), .A1(n1383), .B0(n2195), .B1(n1382), .Y(n1356)
);
OAI22X1TS U4955 ( .A0(n1391), .A1(n2189), .B0(n2194), .B1(n1381), .Y(n1355)
);
OAI22X1TS U4956 ( .A0(n1390), .A1(n2198), .B0(n1391), .B1(n2190), .Y(n1357)
);
OAI22X1TS U4957 ( .A0(n1391), .A1(n1383), .B0(n2194), .B1(n1382), .Y(n1374)
);
OAI22X1TS U4958 ( .A0(n2194), .A1(n2189), .B0(n2195), .B1(n1381), .Y(n1330)
);
OAI22X1TS U4959 ( .A0(n1391), .A1(n2198), .B0(n2194), .B1(n2190), .Y(n1331)
);
INVX4TS U4960 ( .A(n1320), .Y(n1391) );
XOR2X1TS U4961 ( .A(n1319), .B(n1318), .Y(n1320) );
NOR2X1TS U4962 ( .A(n8104), .B(n8103), .Y(n8200) );
AOI21X1TS U4963 ( .A0(n7988), .A1(n8311), .B0(n7987), .Y(n8164) );
ADDHX1TS U4964 ( .A(n7756), .B(n7755), .CO(n7832), .S(n8129) );
NOR2X1TS U4965 ( .A(n736), .B(n734), .Y(n7755) );
NOR2X1TS U4966 ( .A(n820), .B(n739), .Y(n7756) );
NOR2X1TS U4967 ( .A(n745), .B(DP_OP_343J35_127_4270_n857), .Y(n7826) );
OAI22X1TS U4968 ( .A0(n2195), .A1(n2189), .B0(n2199), .B1(n1381), .Y(n2188)
);
INVX2TS U4969 ( .A(n4150), .Y(n2198) );
INVX4TS U4970 ( .A(n1286), .Y(n2195) );
XOR2X1TS U4971 ( .A(n1285), .B(n1284), .Y(n1286) );
INVX2TS U4972 ( .A(n4149), .Y(n2200) );
INVX4TS U4973 ( .A(n1326), .Y(n2194) );
XOR2X1TS U4974 ( .A(n1325), .B(n1324), .Y(n1326) );
NAND2X1TS U4975 ( .A(n1332), .B(n1334), .Y(n1324) );
ADDHX1TS U4976 ( .A(n2197), .B(n2196), .CO(n2191), .S(n4803) );
NOR2X1TS U4977 ( .A(n2199), .B(n2189), .Y(n2197) );
OAI22X1TS U4978 ( .A0(n2195), .A1(n2198), .B0(n2199), .B1(n2190), .Y(n2196)
);
NOR2X1TS U4979 ( .A(n2200), .B(n2195), .Y(n4804) );
NOR2X1TS U4980 ( .A(n3902), .B(n3901), .Y(n3913) );
NAND2X1TS U4981 ( .A(n3902), .B(n3901), .Y(n3914) );
AOI21X1TS U4982 ( .A0(n1159), .A1(n978), .B0(n3900), .Y(n3916) );
INVX2TS U4983 ( .A(n4882), .Y(n3900) );
ADDFX2TS U4984 ( .A(n1745), .B(n1744), .CI(n1743), .CO(n3903), .S(n3902) );
OAI22X1TS U4985 ( .A0(n5462), .A1(n1948), .B0(n5181), .B1(n1730), .Y(n1744)
);
OAI22X1TS U4986 ( .A0(n5462), .A1(n1730), .B0(n5181), .B1(n1810), .Y(n1806)
);
ADDFX2TS U4987 ( .A(n1999), .B(n1998), .CI(n1997), .CO(n5129), .S(n3906) );
OAI22X1TS U4988 ( .A0(n5462), .A1(n1810), .B0(n5181), .B1(n2000), .Y(n1999)
);
NAND2X1TS U4989 ( .A(n5130), .B(n5129), .Y(n5170) );
NAND2X1TS U4990 ( .A(n10124), .B(n10123), .Y(n5169) );
OAI22X1TS U4991 ( .A0(n5462), .A1(n5147), .B0(n5181), .B1(n5182), .Y(n5176)
);
OAI22X1TS U4992 ( .A0(n5462), .A1(n5182), .B0(n5181), .B1(n1636), .Y(n5459)
);
NOR2X2TS U4993 ( .A(n5462), .B(n1636), .Y(n10119) );
NOR2X2TS U4994 ( .A(n5130), .B(n5129), .Y(n5168) );
NOR2X2TS U4995 ( .A(n10124), .B(n10123), .Y(n5171) );
NOR2X1TS U4996 ( .A(n10122), .B(n10121), .Y(n5470) );
OAI21X2TS U4997 ( .A0(n8307), .A1(n8304), .B0(n8305), .Y(n8311) );
AOI21X1TS U4998 ( .A0(n5477), .A1(n5456), .B0(n5455), .Y(n5457) );
NAND2X1TS U4999 ( .A(n4746), .B(n4745), .Y(n4807) );
OAI21X1TS U5000 ( .A0(n4744), .A1(n1132), .B0(n4743), .Y(n4808) );
NOR2X1TS U5001 ( .A(n2199), .B(n2198), .Y(n4811) );
NOR2X2TS U5002 ( .A(n2200), .B(n2199), .Y(n4810) );
NAND2X1TS U5003 ( .A(n4565), .B(n4564), .Y(n4743) );
OA21X1TS U5004 ( .A0(n4569), .A1(n4568), .B0(n4567), .Y(n1132) );
OAI21X1TS U5005 ( .A0(n4506), .A1(n4505), .B0(n4504), .Y(n4574) );
NOR2X2TS U5006 ( .A(n5199), .B(n5198), .Y(n5451) );
INVX2TS U5007 ( .A(n5450), .Y(n5167) );
INVX2TS U5008 ( .A(n7337), .Y(n9762) );
NOR2X1TS U5009 ( .A(n917), .B(n729), .Y(n9761) );
XNOR2X1TS U5010 ( .A(Op_MY[49]), .B(Op_MX[50]), .Y(n7268) );
ADDHXLTS U5011 ( .A(n7296), .B(n7295), .CO(n7318), .S(n7299) );
XNOR2X1TS U5012 ( .A(Op_MY[50]), .B(Op_MX[50]), .Y(n7294) );
XNOR2X1TS U5013 ( .A(Op_MY[51]), .B(Op_MX[50]), .Y(n7317) );
NOR2X2TS U5014 ( .A(DP_OP_342J35_126_4270_n136), .B(
DP_OP_342J35_126_4270_n130), .Y(n7302) );
CMPR42X1TS U5015 ( .A(DP_OP_342J35_126_4270_n174), .B(
DP_OP_342J35_126_4270_n163), .C(DP_OP_342J35_126_4270_n171), .D(
DP_OP_342J35_126_4270_n160), .ICI(DP_OP_342J35_126_4270_n167), .S(
DP_OP_342J35_126_4270_n157), .ICO(DP_OP_342J35_126_4270_n155), .CO(
DP_OP_342J35_126_4270_n156) );
OAI22X1TS U5016 ( .A0(n7268), .A1(n905), .B0(n7381), .B1(n7254), .Y(n7269)
);
OAI22X2TS U5017 ( .A0(n7255), .A1(n7321), .B0(n7267), .B1(n728), .Y(n9794)
);
INVX2TS U5018 ( .A(n9876), .Y(DP_OP_342J35_126_4270_n406) );
ADDHX1TS U5019 ( .A(n7253), .B(n7252), .CO(n7270), .S(n9808) );
OAI22X1TS U5020 ( .A0(n7381), .A1(n7058), .B0(n7254), .B1(n905), .Y(n7252)
);
OAI22X1TS U5021 ( .A0(n7381), .A1(DP_OP_342J35_126_4270_n852), .B0(n905),
.B1(n7057), .Y(n7253) );
INVX2TS U5022 ( .A(n9815), .Y(n9826) );
NOR2X2TS U5023 ( .A(Op_MY[50]), .B(Op_MY[43]), .Y(n9822) );
NAND2X1TS U5024 ( .A(Op_MY[50]), .B(Op_MY[43]), .Y(n9823) );
AOI21X1TS U5025 ( .A0(n1145), .A1(n7041), .B0(n7036), .Y(n7309) );
INVX2TS U5026 ( .A(n7040), .Y(n7036) );
ADDHXLTS U5027 ( .A(Op_MX[50]), .B(Op_MX[43]), .CO(n9771), .S(n9832) );
NOR2X1TS U5028 ( .A(n9875), .B(n9808), .Y(n7250) );
AOI21X1TS U5029 ( .A0(n1226), .A1(n7239), .B0(n7054), .Y(n7251) );
NAND2X1TS U5030 ( .A(n9875), .B(n9808), .Y(n7249) );
ADDHXLTS U5031 ( .A(Op_MX[48]), .B(Op_MX[41]), .CO(n9837), .S(n9838) );
NOR2X1TS U5032 ( .A(DP_OP_342J35_126_4270_n748), .B(n729), .Y(n7115) );
CMPR42X1TS U5033 ( .A(DP_OP_342J35_126_4270_n281), .B(
DP_OP_342J35_126_4270_n307), .C(DP_OP_342J35_126_4270_n323), .D(
DP_OP_342J35_126_4270_n331), .ICI(DP_OP_342J35_126_4270_n243), .S(
DP_OP_342J35_126_4270_n231), .ICO(DP_OP_342J35_126_4270_n229), .CO(
DP_OP_342J35_126_4270_n230) );
NOR2X1TS U5034 ( .A(n881), .B(n9841), .Y(DP_OP_342J35_126_4270_n307) );
OAI22X1TS U5035 ( .A0(n9833), .A1(n9840), .B0(n9834), .B1(n9847), .Y(
DP_OP_342J35_126_4270_n323) );
CMPR42X1TS U5036 ( .A(DP_OP_342J35_126_4270_n242), .B(
DP_OP_342J35_126_4270_n280), .C(DP_OP_342J35_126_4270_n233), .D(
DP_OP_342J35_126_4270_n339), .ICI(DP_OP_342J35_126_4270_n347), .S(
DP_OP_342J35_126_4270_n228), .ICO(DP_OP_342J35_126_4270_n226), .CO(
DP_OP_342J35_126_4270_n227) );
OAI22X1TS U5037 ( .A0(n9844), .A1(n9848), .B0(n9845), .B1(n9846), .Y(
DP_OP_342J35_126_4270_n347) );
OAI22X1TS U5038 ( .A0(n9845), .A1(n9842), .B0(n9849), .B1(n9839), .Y(
DP_OP_342J35_126_4270_n339) );
INVX2TS U5039 ( .A(n9862), .Y(DP_OP_342J35_126_4270_n280) );
CMPR42X1TS U5040 ( .A(DP_OP_342J35_126_4270_n255), .B(
DP_OP_342J35_126_4270_n246), .C(DP_OP_342J35_126_4270_n283), .D(
DP_OP_342J35_126_4270_n402), .ICI(DP_OP_342J35_126_4270_n340), .S(
DP_OP_342J35_126_4270_n244), .ICO(DP_OP_342J35_126_4270_n242), .CO(
DP_OP_342J35_126_4270_n243) );
OAI22X1TS U5041 ( .A0(n9849), .A1(n9842), .B0(n9847), .B1(n9839), .Y(
DP_OP_342J35_126_4270_n340) );
INVX2TS U5042 ( .A(n9865), .Y(DP_OP_342J35_126_4270_n283) );
INVX2TS U5043 ( .A(n9771), .Y(n9833) );
XNOR2X1TS U5044 ( .A(n9820), .B(n9819), .Y(n9821) );
INVX2TS U5045 ( .A(n9802), .Y(n9836) );
INVX2TS U5046 ( .A(n9803), .Y(n9835) );
CMPR42X1TS U5047 ( .A(DP_OP_342J35_126_4270_n311), .B(
DP_OP_342J35_126_4270_n272), .C(DP_OP_342J35_126_4270_n187), .D(
DP_OP_342J35_126_4270_n178), .ICI(DP_OP_342J35_126_4270_n191), .S(
DP_OP_342J35_126_4270_n172), .ICO(DP_OP_342J35_126_4270_n170), .CO(
DP_OP_342J35_126_4270_n171) );
OAI22X1TS U5048 ( .A0(n9844), .A1(n9831), .B0(n9845), .B1(n9830), .Y(
DP_OP_342J35_126_4270_n311) );
INVX2TS U5049 ( .A(n9854), .Y(DP_OP_342J35_126_4270_n272) );
CMPR42X1TS U5050 ( .A(DP_OP_342J35_126_4270_n193), .B(
DP_OP_342J35_126_4270_n327), .C(DP_OP_342J35_126_4270_n319), .D(
DP_OP_342J35_126_4270_n273), .ICI(DP_OP_342J35_126_4270_n184), .S(
DP_OP_342J35_126_4270_n175), .ICO(DP_OP_342J35_126_4270_n173), .CO(
DP_OP_342J35_126_4270_n174) );
OAI22X1TS U5051 ( .A0(n9844), .A1(n9833), .B0(n9843), .B1(n9834), .Y(
DP_OP_342J35_126_4270_n319) );
INVX2TS U5052 ( .A(n9855), .Y(DP_OP_342J35_126_4270_n273) );
CMPR42X1TS U5053 ( .A(DP_OP_342J35_126_4270_n330), .B(
DP_OP_342J35_126_4270_n278), .C(DP_OP_342J35_126_4270_n229), .D(
DP_OP_342J35_126_4270_n338), .ICI(DP_OP_342J35_126_4270_n230), .S(
DP_OP_342J35_126_4270_n214), .ICO(DP_OP_342J35_126_4270_n212), .CO(
DP_OP_342J35_126_4270_n213) );
OAI22X1TS U5054 ( .A0(n9844), .A1(n9842), .B0(n9845), .B1(n9839), .Y(
DP_OP_342J35_126_4270_n338) );
OAI22X1TS U5055 ( .A0(n9845), .A1(n9836), .B0(n9849), .B1(n9835), .Y(
DP_OP_342J35_126_4270_n330) );
CMPR42X1TS U5056 ( .A(DP_OP_342J35_126_4270_n221), .B(
DP_OP_342J35_126_4270_n305), .C(DP_OP_342J35_126_4270_n313), .D(
DP_OP_342J35_126_4270_n321), .ICI(DP_OP_342J35_126_4270_n215), .S(
DP_OP_342J35_126_4270_n206), .ICO(DP_OP_342J35_126_4270_n204), .CO(
DP_OP_342J35_126_4270_n205) );
OAI22X1TS U5057 ( .A0(n881), .A1(n9847), .B0(n9829), .B1(n9840), .Y(
DP_OP_342J35_126_4270_n305) );
OAI22X1TS U5058 ( .A0(n9845), .A1(n9834), .B0(n9849), .B1(n9833), .Y(
DP_OP_342J35_126_4270_n321) );
OAI22X1TS U5059 ( .A0(n9849), .A1(n9831), .B0(n9847), .B1(n9830), .Y(
DP_OP_342J35_126_4270_n313) );
CMPR42X1TS U5060 ( .A(DP_OP_342J35_126_4270_n220), .B(
DP_OP_342J35_126_4270_n217), .C(DP_OP_342J35_126_4270_n227), .D(
DP_OP_342J35_126_4270_n223), .ICI(DP_OP_342J35_126_4270_n214), .S(
DP_OP_342J35_126_4270_n211), .ICO(DP_OP_342J35_126_4270_n209), .CO(
DP_OP_342J35_126_4270_n210) );
CMPR42X1TS U5061 ( .A(DP_OP_342J35_126_4270_n277), .B(
DP_OP_342J35_126_4270_n208), .C(DP_OP_342J35_126_4270_n345), .D(
DP_OP_342J35_126_4270_n337), .ICI(DP_OP_342J35_126_4270_n219), .S(
DP_OP_342J35_126_4270_n203), .ICO(DP_OP_342J35_126_4270_n201), .CO(
DP_OP_342J35_126_4270_n202) );
OAI22X1TS U5062 ( .A0(n9844), .A1(n9839), .B0(n9843), .B1(n9842), .Y(
DP_OP_342J35_126_4270_n337) );
INVX2TS U5063 ( .A(n9859), .Y(DP_OP_342J35_126_4270_n277) );
CMPR42X1TS U5064 ( .A(DP_OP_342J35_126_4270_n218), .B(
DP_OP_342J35_126_4270_n276), .C(DP_OP_342J35_126_4270_n329), .D(
DP_OP_342J35_126_4270_n212), .ICI(DP_OP_342J35_126_4270_n216), .S(
DP_OP_342J35_126_4270_n200), .ICO(DP_OP_342J35_126_4270_n198), .CO(
DP_OP_342J35_126_4270_n199) );
OAI22X1TS U5065 ( .A0(n9844), .A1(n9836), .B0(n9845), .B1(n9835), .Y(
DP_OP_342J35_126_4270_n329) );
INVX2TS U5066 ( .A(n9858), .Y(DP_OP_342J35_126_4270_n276) );
CMPR42X1TS U5067 ( .A(DP_OP_342J35_126_4270_n207), .B(
DP_OP_342J35_126_4270_n194), .C(DP_OP_342J35_126_4270_n336), .D(
DP_OP_342J35_126_4270_n328), .ICI(DP_OP_342J35_126_4270_n201), .S(
DP_OP_342J35_126_4270_n189), .ICO(DP_OP_342J35_126_4270_n187), .CO(
DP_OP_342J35_126_4270_n188) );
OAI22X1TS U5068 ( .A0(n9844), .A1(n9835), .B0(n9843), .B1(n9836), .Y(
DP_OP_342J35_126_4270_n328) );
CMPR42X1TS U5069 ( .A(DP_OP_342J35_126_4270_n320), .B(
DP_OP_342J35_126_4270_n204), .C(DP_OP_342J35_126_4270_n274), .D(
DP_OP_342J35_126_4270_n205), .ICI(DP_OP_342J35_126_4270_n192), .S(
DP_OP_342J35_126_4270_n186), .ICO(DP_OP_342J35_126_4270_n184), .CO(
DP_OP_342J35_126_4270_n185) );
INVX2TS U5070 ( .A(n9856), .Y(DP_OP_342J35_126_4270_n274) );
ADDHXLTS U5071 ( .A(n7087), .B(n7086), .CO(n7083), .S(n7131) );
CMPR42X1TS U5072 ( .A(DP_OP_342J35_126_4270_n141), .B(
DP_OP_342J35_126_4270_n132), .C(DP_OP_342J35_126_4270_n138), .D(
DP_OP_342J35_126_4270_n139), .ICI(DP_OP_342J35_126_4270_n135), .S(
DP_OP_342J35_126_4270_n130), .ICO(DP_OP_342J35_126_4270_n128), .CO(
DP_OP_342J35_126_4270_n129) );
NOR2X2TS U5073 ( .A(DP_OP_342J35_126_4270_n145), .B(
DP_OP_342J35_126_4270_n137), .Y(n7329) );
CMPR42X1TS U5074 ( .A(DP_OP_342J35_126_4270_n150), .B(
DP_OP_342J35_126_4270_n151), .C(DP_OP_342J35_126_4270_n140), .D(
DP_OP_342J35_126_4270_n148), .ICI(DP_OP_342J35_126_4270_n144), .S(
DP_OP_342J35_126_4270_n137), .ICO(DP_OP_342J35_126_4270_n135), .CO(
DP_OP_342J35_126_4270_n136) );
CMPR42X1TS U5075 ( .A(DP_OP_342J35_126_4270_n158), .B(
DP_OP_342J35_126_4270_n152), .C(DP_OP_342J35_126_4270_n149), .D(
DP_OP_342J35_126_4270_n159), .ICI(DP_OP_342J35_126_4270_n155), .S(
DP_OP_342J35_126_4270_n146), .ICO(DP_OP_342J35_126_4270_n144), .CO(
DP_OP_342J35_126_4270_n145) );
CLKAND2X2TS U5076 ( .A(n1363), .B(Op_MY[26]), .Y(n933) );
XNOR2X2TS U5077 ( .A(n4988), .B(n4987), .Y(n4991) );
OAI21X1TS U5078 ( .A0(n4983), .A1(n4982), .B0(n4981), .Y(n4988) );
NAND2X1TS U5079 ( .A(n4974), .B(n4979), .Y(n4982) );
AOI21X1TS U5080 ( .A0(n4980), .A1(n4979), .B0(n4978), .Y(n4981) );
NAND2X1TS U5081 ( .A(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(n5135) );
NAND2X1TS U5082 ( .A(n1113), .B(n2276), .Y(n2277) );
XNOR2X2TS U5083 ( .A(n2463), .B(n2462), .Y(n2470) );
NAND2X1TS U5084 ( .A(n1012), .B(n2461), .Y(n2462) );
CLKXOR2X2TS U5085 ( .A(n2354), .B(n2379), .Y(n2453) );
NAND2X1TS U5086 ( .A(n2353), .B(n2352), .Y(n2354) );
CLKXOR2X2TS U5087 ( .A(n2282), .B(n2284), .Y(n2381) );
NAND2X1TS U5088 ( .A(n2281), .B(n2280), .Y(n2282) );
NOR2X1TS U5089 ( .A(n2890), .B(n2630), .Y(n2628) );
NOR2X1TS U5090 ( .A(n2744), .B(n2380), .Y(n2457) );
XNOR2X1TS U5091 ( .A(n2393), .B(n2392), .Y(n2394) );
NAND2X1TS U5092 ( .A(n1123), .B(n2391), .Y(n2393) );
INVX2TS U5093 ( .A(n2382), .Y(n2384) );
NAND2X1TS U5094 ( .A(n2287), .B(n2286), .Y(n2383) );
NOR2X1TS U5095 ( .A(n853), .B(n772), .Y(n6309) );
OAI22X1TS U5096 ( .A0(n9929), .A1(n2799), .B0(n9928), .B1(n2744), .Y(n2754)
);
OAI22X1TS U5097 ( .A0(n9944), .A1(n2799), .B0(n9946), .B1(n2744), .Y(n2750)
);
OAI22X1TS U5098 ( .A0(n9948), .A1(n2744), .B0(n9947), .B1(n2704), .Y(n2742)
);
OAI22X1TS U5099 ( .A0(n6055), .A1(n5948), .B0(n6042), .B1(n5946), .Y(n5927)
);
OAI21XLTS U5100 ( .A0(n6253), .A1(n6242), .B0(n6243), .Y(n6229) );
ADDHX1TS U5101 ( .A(n2251), .B(n2250), .CO(n2252), .S(n2346) );
NOR2X1TS U5102 ( .A(n2342), .B(n2524), .Y(n2251) );
OAI22X1TS U5103 ( .A0(n2509), .A1(n2508), .B0(n2342), .B1(n2523), .Y(n2250)
);
ADDFX2TS U5104 ( .A(n10068), .B(n10067), .CI(n10066), .CO(
DP_OP_345J35_129_3436_n116), .S(n9881) );
OAI21X1TS U5105 ( .A0(n1578), .A1(n1577), .B0(n1576), .Y(n1583) );
OAI21X1TS U5106 ( .A0(n10116), .A1(n10112), .B0(n10113), .Y(n10101) );
OAI22X2TS U5107 ( .A0(n6861), .A1(n2509), .B0(n2659), .B1(n2545), .Y(n6847)
);
INVX2TS U5108 ( .A(n3057), .Y(n3279) );
ADDFX2TS U5109 ( .A(n3168), .B(n3167), .CI(n3166), .CO(n3720), .S(n3719) );
OAI22X1TS U5110 ( .A0(n3121), .A1(n899), .B0(n3102), .B1(n3390), .Y(n3167)
);
NOR2XLTS U5111 ( .A(n3256), .B(n3278), .Y(n3275) );
ADDFX2TS U5112 ( .A(n3329), .B(n3328), .CI(n3327), .CO(n3335), .S(n3334) );
OAI21X2TS U5113 ( .A0(n3770), .A1(n3768), .B0(n3771), .Y(n3806) );
NOR2X1TS U5114 ( .A(n3799), .B(n3803), .Y(n3805) );
INVX2TS U5115 ( .A(n3481), .Y(n3556) );
INVX2TS U5116 ( .A(n900), .Y(n3479) );
AO21XLTS U5117 ( .A0(n3390), .A1(n899), .B0(n3388), .Y(n3424) );
AOI21X1TS U5118 ( .A0(n1189), .A1(n6289), .B0(n5960), .Y(n6200) );
NAND2X1TS U5119 ( .A(n5968), .B(n5967), .Y(n6198) );
NOR2X1TS U5120 ( .A(n5968), .B(n5967), .Y(n6197) );
CLKXOR2X2TS U5121 ( .A(n10072), .B(n10071), .Y(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[12]) );
AOI21X1TS U5122 ( .A0(n10118), .A1(n1071), .B0(n10070), .Y(n10072) );
INVX2TS U5123 ( .A(n9878), .Y(add_x_87_n4) );
NAND2X1TS U5124 ( .A(n5959), .B(n5958), .Y(n6288) );
OR2X1TS U5125 ( .A(n5959), .B(n5958), .Y(n1189) );
OAI21X1TS U5126 ( .A0(n6202), .A1(n6205), .B0(n6203), .Y(n6289) );
NAND2X1TS U5127 ( .A(n6084), .B(n6291), .Y(n6292) );
INVX2TS U5128 ( .A(n8576), .Y(n6839) );
XOR2X1TS U5129 ( .A(n10082), .B(n10081), .Y(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[10]) );
NAND2X1TS U5130 ( .A(n10080), .B(n10079), .Y(n10081) );
XOR2X1TS U5131 ( .A(n10089), .B(n10088), .Y(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[9]) );
NAND2X1TS U5132 ( .A(n10087), .B(n10086), .Y(n10088) );
INVX2TS U5133 ( .A(n8572), .Y(n6891) );
INVX2TS U5134 ( .A(n3930), .Y(n1860) );
CLKINVX3TS U5135 ( .A(n3081), .Y(n3280) );
NOR2X2TS U5136 ( .A(n3338), .B(n3337), .Y(n3691) );
NAND2X1TS U5137 ( .A(n3338), .B(n3337), .Y(n3692) );
NOR2X2TS U5138 ( .A(n3336), .B(n3335), .Y(n3698) );
NAND2X1TS U5139 ( .A(n3336), .B(n3335), .Y(n3699) );
NAND2BXLTS U5140 ( .AN(n3281), .B(n752), .Y(n3254) );
INVX2TS U5141 ( .A(n5448), .Y(n5441) );
OAI21X2TS U5142 ( .A0(n5418), .A1(n5414), .B0(n5415), .Y(n5453) );
NOR2X1TS U5143 ( .A(n4498), .B(n4497), .Y(n4569) );
NAND2X1TS U5144 ( .A(n4498), .B(n4497), .Y(n4567) );
AOI21X1TS U5145 ( .A0(n1045), .A1(n987), .B0(n4501), .Y(n4568) );
NOR2X1TS U5146 ( .A(n4503), .B(n4506), .Y(n4571) );
NAND2X1TS U5147 ( .A(n4912), .B(n4910), .Y(n4572) );
XNOR2X1TS U5148 ( .A(n2490), .B(n2489), .Y(n2491) );
NAND2X1TS U5149 ( .A(n2488), .B(n2487), .Y(n2489) );
INVX2TS U5150 ( .A(n2844), .Y(n2795) );
OAI22X1TS U5151 ( .A0(n9948), .A1(n2799), .B0(n9947), .B1(n2744), .Y(n2796)
);
NAND2X1TS U5152 ( .A(n5953), .B(n5952), .Y(n6234) );
OR2X1TS U5153 ( .A(n5953), .B(n5952), .Y(n1188) );
OAI21XLTS U5154 ( .A0(n6239), .A1(n6252), .B0(n6253), .Y(n6240) );
NOR2XLTS U5155 ( .A(n6238), .B(n6252), .Y(n6241) );
NOR2X1TS U5156 ( .A(n2905), .B(n2909), .Y(n2899) );
NAND2X1TS U5157 ( .A(n2350), .B(n2338), .Y(n6843) );
NOR2BX1TS U5158 ( .AN(n3282), .B(n3483), .Y(n3100) );
OAI22X1TS U5159 ( .A0(n3101), .A1(n878), .B0(n3039), .B1(n3480), .Y(n3098)
);
NAND2X1TS U5160 ( .A(n6866), .B(n6865), .Y(n10097) );
NAND2X1TS U5161 ( .A(n3290), .B(n3289), .Y(n3765) );
OR2X1TS U5162 ( .A(n3290), .B(n3289), .Y(n925) );
OAI21X1TS U5163 ( .A0(n3734), .A1(n3737), .B0(n3735), .Y(n3766) );
ADDHXLTS U5164 ( .A(n2575), .B(n2574), .CO(n2683), .S(n2681) );
INVX2TS U5165 ( .A(n2818), .Y(n2801) );
NOR2X1TS U5166 ( .A(n2799), .B(n2380), .Y(n2800) );
NOR2X2TS U5167 ( .A(n2342), .B(n2508), .Y(n2818) );
NOR2X1TS U5168 ( .A(n6846), .B(n6845), .Y(n10112) );
NAND2X1TS U5169 ( .A(n6846), .B(n6845), .Y(n10113) );
NAND2X1TS U5170 ( .A(n6868), .B(n6867), .Y(n10093) );
INVX2TS U5171 ( .A(n10073), .Y(n10100) );
NOR2X1TS U5172 ( .A(n3311), .B(n3310), .Y(n3703) );
NAND2X1TS U5173 ( .A(n3311), .B(n3310), .Y(n3704) );
AOI21X1TS U5174 ( .A0(n925), .A1(n3766), .B0(n3291), .Y(n3706) );
INVX2TS U5175 ( .A(n3765), .Y(n3291) );
INVX2TS U5176 ( .A(n4364), .Y(n4366) );
NAND2X1TS U5177 ( .A(n4294), .B(n4293), .Y(n4365) );
OA21XLTS U5178 ( .A0(n4359), .A1(n4362), .B0(n4360), .Y(n1078) );
NAND2X1TS U5179 ( .A(n4289), .B(n4288), .Y(n5324) );
AO21X1TS U5180 ( .A0(n1079), .A1(n5330), .B0(n4287), .Y(n983) );
NOR2X2TS U5181 ( .A(n4098), .B(n4223), .Y(n4496) );
OAI22X1TS U5182 ( .A0(n7910), .A1(n7909), .B0(n7908), .B1(n7943), .Y(n7941)
);
XNOR2X1TS U5183 ( .A(n5102), .B(n5101), .Y(n5111) );
NAND2X1TS U5184 ( .A(n1160), .B(n5100), .Y(n5101) );
NOR2X1TS U5185 ( .A(n5244), .B(n5229), .Y(n5087) );
OAI21X1TS U5186 ( .A0(n5229), .A1(n5245), .B0(n5230), .Y(n5086) );
XOR2X1TS U5187 ( .A(n5400), .B(n5205), .Y(n5397) );
NAND2X1TS U5188 ( .A(n5204), .B(n5398), .Y(n5205) );
INVX2TS U5189 ( .A(n5399), .Y(n5204) );
XOR2X1TS U5190 ( .A(n4217), .B(n4216), .Y(n4227) );
XOR2X1TS U5191 ( .A(n4215), .B(n4214), .Y(n4216) );
NOR2X2TS U5192 ( .A(n4758), .B(n4757), .Y(n4506) );
NAND2X1TS U5193 ( .A(n4204), .B(n4203), .Y(n4500) );
OR2X1TS U5194 ( .A(n4204), .B(n4203), .Y(n1045) );
NAND2X1TS U5195 ( .A(n5416), .B(n5415), .Y(n5417) );
INVX2TS U5196 ( .A(n5414), .Y(n5416) );
NAND2X1TS U5197 ( .A(n6091), .B(n6090), .Y(n6315) );
NAND2X1TS U5198 ( .A(n6093), .B(n6092), .Y(n6184) );
NOR2X2TS U5199 ( .A(n6093), .B(n6092), .Y(n6183) );
AOI21X1TS U5200 ( .A0(n815), .A1(n983), .B0(n4290), .Y(n4362) );
NAND2X1TS U5201 ( .A(n4292), .B(n4291), .Y(n4360) );
NAND2X1TS U5202 ( .A(n3856), .B(n3855), .Y(n3857) );
AOI21X1TS U5203 ( .A0(n3853), .A1(n3852), .B0(n3851), .Y(n3858) );
NAND2X1TS U5204 ( .A(n3843), .B(n3842), .Y(n3844) );
AOI21X1TS U5205 ( .A0(n3840), .A1(n3853), .B0(n3839), .Y(n3845) );
NAND2X1TS U5206 ( .A(n5419), .B(n5425), .Y(n5432) );
ADDFX2TS U5207 ( .A(n4458), .B(n4457), .CI(n4456), .CO(n4598), .S(n5381) );
XNOR2X1TS U5208 ( .A(n4406), .B(n4405), .Y(n4457) );
NAND2X1TS U5209 ( .A(n4404), .B(n4436), .Y(n4405) );
AO21XLTS U5210 ( .A0(n3499), .A1(n877), .B0(n3498), .Y(n3551) );
OAI22X1TS U5211 ( .A0(n3502), .A1(n3557), .B0(n3558), .B1(n3501), .Y(n3550)
);
NOR2X1TS U5212 ( .A(n5430), .B(n1183), .Y(n3877) );
XOR2X1TS U5213 ( .A(n4060), .B(n4059), .Y(n4115) );
INVX2TS U5214 ( .A(n5622), .Y(n5033) );
INVX2TS U5215 ( .A(n4120), .Y(n4084) );
XNOR2X1TS U5216 ( .A(n5052), .B(n5017), .Y(n5036) );
NAND2X1TS U5217 ( .A(n5016), .B(n5015), .Y(n5017) );
NOR2X2TS U5218 ( .A(n4074), .B(n4223), .Y(n4178) );
ADDHX1TS U5219 ( .A(n4076), .B(n4075), .CO(n4072), .S(n4169) );
NOR2X1TS U5220 ( .A(n4647), .B(n4030), .Y(n4076) );
NOR2X1TS U5221 ( .A(n4077), .B(n4084), .Y(n4075) );
NAND2X1TS U5222 ( .A(n5009), .B(n5008), .Y(n5010) );
AOI21X1TS U5223 ( .A0(n5052), .A1(n5016), .B0(n5006), .Y(n5011) );
NOR2X2TS U5224 ( .A(n5036), .B(n5035), .Y(n5389) );
NOR2X2TS U5225 ( .A(n4070), .B(n4223), .Y(n4199) );
ADDHXLTS U5226 ( .A(n7535), .B(n7534), .CO(n7546), .S(n7538) );
NOR2X2TS U5227 ( .A(n4090), .B(n4223), .Y(n4109) );
NAND2X1TS U5228 ( .A(n824), .B(n5042), .Y(n5043) );
AOI21X1TS U5229 ( .A0(n5052), .A1(n5041), .B0(n5040), .Y(n5044) );
NOR2XLTS U5230 ( .A(n3642), .B(n3660), .Y(n3650) );
OAI22X1TS U5231 ( .A0(n10184), .A1(n2170), .B0(n2169), .B1(n2105), .Y(n2178)
);
XOR2X1TS U5232 ( .A(n4375), .B(n4374), .Y(n4416) );
AOI21X1TS U5233 ( .A0(n3619), .A1(n911), .B0(n912), .Y(n3633) );
OAI21X2TS U5234 ( .A0(n6149), .A1(n6101), .B0(n6100), .Y(n6165) );
NAND2X1TS U5235 ( .A(n6172), .B(n6099), .Y(n6101) );
AOI21X1TS U5236 ( .A0(n6171), .A1(n6099), .B0(n6098), .Y(n6100) );
NOR2X1TS U5237 ( .A(n6173), .B(n6153), .Y(n6099) );
OR2X1TS U5238 ( .A(n6102), .B(n6292), .Y(n6112) );
NAND2X1TS U5239 ( .A(n3647), .B(n3646), .Y(n3663) );
NOR2XLTS U5240 ( .A(n2169), .B(n2170), .Y(n4426) );
NOR2X1TS U5241 ( .A(n4284), .B(n4283), .Y(n5332) );
NAND2X1TS U5242 ( .A(n4284), .B(n4283), .Y(n5333) );
NAND2X1TS U5243 ( .A(n6850), .B(n6849), .Y(n10103) );
NAND2X1TS U5244 ( .A(n2345), .B(n2376), .Y(n2257) );
AOI21X1TS U5245 ( .A0(n2918), .A1(n2922), .B0(n2906), .Y(n2907) );
NAND2X1TS U5246 ( .A(n2917), .B(n2922), .Y(n2908) );
NAND2X1TS U5247 ( .A(n9902), .B(n9893), .Y(n2910) );
NOR2X1TS U5248 ( .A(n9947), .B(n2799), .Y(n2808) );
OAI22X1TS U5249 ( .A0(n9927), .A1(n2799), .B0(n2797), .B1(n2744), .Y(n2810)
);
INVX4TS U5250 ( .A(n5663), .Y(n5888) );
XNOR2X1TS U5251 ( .A(n5662), .B(n5661), .Y(n5663) );
NOR2X1TS U5252 ( .A(n770), .B(n731), .Y(n6023) );
NOR2X1TS U5253 ( .A(n2866), .B(n2630), .Y(n2690) );
NOR2X1TS U5254 ( .A(n733), .B(n8096), .Y(n8080) );
OAI22X1TS U5255 ( .A0(n8049), .A1(n7943), .B0(n7998), .B1(n7910), .Y(n7926)
);
NAND2X1TS U5256 ( .A(n5403), .B(n5402), .Y(n5404) );
INVX2TS U5257 ( .A(n5401), .Y(n5403) );
NOR2X1TS U5258 ( .A(n4228), .B(n4227), .Y(n4262) );
NOR2X1TS U5259 ( .A(n4643), .B(n4714), .Y(n4206) );
NOR2X2TS U5260 ( .A(n4693), .B(n4692), .Y(n4239) );
NAND2X1TS U5261 ( .A(n4693), .B(n4692), .Y(n4240) );
NOR2X2TS U5262 ( .A(n4614), .B(n4613), .Y(n4503) );
NAND2X1TS U5263 ( .A(n4614), .B(n4613), .Y(n4505) );
XOR2X1TS U5264 ( .A(n5219), .B(n5218), .Y(n5394) );
NAND2X1TS U5265 ( .A(n799), .B(n5217), .Y(n5218) );
NAND2X1TS U5266 ( .A(n4251), .B(n4250), .Y(n4253) );
INVX2TS U5267 ( .A(n4249), .Y(n4251) );
OAI21X1TS U5268 ( .A0(n4252), .A1(n4249), .B0(n4250), .Y(n4238) );
NAND2X1TS U5269 ( .A(n4697), .B(n4668), .Y(n4245) );
NOR2X2TS U5270 ( .A(n4697), .B(n4668), .Y(n4244) );
NOR2X1TS U5271 ( .A(n4225), .B(n4224), .Y(n4257) );
NAND2X1TS U5272 ( .A(n4225), .B(n4224), .Y(n4258) );
NOR2X1TS U5273 ( .A(n4714), .B(n4629), .Y(n4221) );
XNOR2X1TS U5274 ( .A(n4115), .B(n4114), .Y(n4116) );
NAND2X1TS U5275 ( .A(n4113), .B(n4121), .Y(n4114) );
AOI21X1TS U5276 ( .A0(n8216), .A1(n8215), .B0(n8214), .Y(n8287) );
NOR2XLTS U5277 ( .A(n8213), .B(n8210), .Y(n8216) );
OAI22X1TS U5278 ( .A0(n7900), .A1(n7909), .B0(n7910), .B1(n7908), .Y(n7938)
);
OAI22X1TS U5279 ( .A0(n7905), .A1(n7943), .B0(n7944), .B1(n7910), .Y(n7935)
);
NOR2X2TS U5280 ( .A(n4513), .B(n4223), .Y(n4563) );
CLKXOR2X2TS U5281 ( .A(n5099), .B(n5065), .Y(n5083) );
NAND2X1TS U5282 ( .A(n5064), .B(n5074), .Y(n5065) );
INVX2TS U5283 ( .A(n5075), .Y(n5064) );
OAI21X2TS U5284 ( .A0(n5254), .A1(n5063), .B0(n5062), .Y(n5228) );
INVX2TS U5285 ( .A(n5256), .Y(n5061) );
ADDHXLTS U5286 ( .A(Op_MX[34]), .B(Op_MX[27]), .CO(n7719), .S(n7570) );
XNOR2X1TS U5287 ( .A(n6308), .B(n6307), .Y(n6313) );
NAND2X1TS U5288 ( .A(n6306), .B(n6305), .Y(n6307) );
XOR2X1TS U5289 ( .A(n6193), .B(n6303), .Y(n6300) );
NAND2X1TS U5290 ( .A(n6191), .B(n6301), .Y(n6193) );
NOR2X1TS U5291 ( .A(add_x_87_n4), .B(n1255), .Y(add_x_87_n2) );
OAI21X2TS U5292 ( .A0(n10073), .A1(n6874), .B0(n6873), .Y(n10118) );
AOI21X1TS U5293 ( .A0(n10083), .A1(n6872), .B0(n6871), .Y(n6873) );
AND2X2TS U5294 ( .A(add_x_87_n1), .B(add_x_87_n2), .Y(n929) );
NAND2X1TS U5295 ( .A(n4286), .B(n4285), .Y(n5329) );
OR2X1TS U5296 ( .A(n4286), .B(n4285), .Y(n1079) );
OAI21X1TS U5297 ( .A0(n5332), .A1(n5341), .B0(n5333), .Y(n5330) );
XOR2X1TS U5298 ( .A(n3686), .B(n3685), .Y(n3836) );
NAND2X1TS U5299 ( .A(n3684), .B(n3683), .Y(n3685) );
AOI21X1TS U5300 ( .A0(n3853), .A1(n3825), .B0(n3681), .Y(n3686) );
XNOR2X1TS U5301 ( .A(n3689), .B(n3688), .Y(n3835) );
XNOR2X1TS U5302 ( .A(n6165), .B(n6164), .Y(n6333) );
NAND2X1TS U5303 ( .A(n6106), .B(n6163), .Y(n6164) );
XOR2X1TS U5304 ( .A(n6170), .B(n6169), .Y(n6332) );
NAND2X1TS U5305 ( .A(n6163), .B(n6132), .Y(n6133) );
XOR2X1TS U5306 ( .A(n6349), .B(n6142), .Y(n6336) );
NOR2X1TS U5307 ( .A(n3660), .B(n3664), .Y(n3666) );
OAI22X1TS U5308 ( .A0(n10188), .A1(n2170), .B0(n10190), .B1(n2105), .Y(n2168) );
NAND2X1TS U5309 ( .A(n6097), .B(n6096), .Y(n6154) );
NOR2X2TS U5310 ( .A(n6097), .B(n6096), .Y(n6153) );
INVX2TS U5311 ( .A(n6149), .Y(n6318) );
XOR2X1TS U5312 ( .A(n6177), .B(n6176), .Y(n6327) );
NAND2X1TS U5313 ( .A(n6175), .B(n6174), .Y(n6176) );
AOI21X1TS U5314 ( .A0(n6318), .A1(n6172), .B0(n6171), .Y(n6177) );
XNOR2X1TS U5315 ( .A(n6180), .B(n6179), .Y(n6326) );
NAND2X1TS U5316 ( .A(n4296), .B(n4295), .Y(n4368) );
OAI21X1TS U5317 ( .A0(n4364), .A1(n1078), .B0(n4365), .Y(n4369) );
XNOR2X1TS U5318 ( .A(n3619), .B(n3609), .Y(n3871) );
NAND2X1TS U5319 ( .A(n1162), .B(n3608), .Y(n3609) );
XNOR2X1TS U5320 ( .A(n3615), .B(n3614), .Y(n3870) );
OAI21XLTS U5321 ( .A0(n3850), .A1(n3846), .B0(n3847), .Y(n3615) );
XOR2X1TS U5322 ( .A(n3591), .B(n3590), .Y(n3873) );
NAND2X1TS U5323 ( .A(n821), .B(n3616), .Y(n3590) );
AOI21X1TS U5324 ( .A0(n3619), .A1(n1162), .B0(n3618), .Y(n3591) );
XNOR2X1TS U5325 ( .A(n3656), .B(n3607), .Y(n3872) );
NOR2XLTS U5326 ( .A(n9686), .B(n9663), .Y(DP_OP_341J35_125_6458_n156) );
NOR2XLTS U5327 ( .A(n9653), .B(n9651), .Y(n9557) );
NOR2X1TS U5328 ( .A(n5188), .B(n5003), .Y(n4993) );
AOI21X1TS U5329 ( .A0(n5193), .A1(n4993), .B0(n4992), .Y(n4994) );
XNOR2X1TS U5330 ( .A(n5004), .B(n5003), .Y(n8793) );
NAND2X1TS U5331 ( .A(n5189), .B(n5092), .Y(n5002) );
AOI21X1TS U5332 ( .A0(n5193), .A1(n5092), .B0(n5000), .Y(n5001) );
NOR2XLTS U5333 ( .A(n9682), .B(n9685), .Y(n9561) );
NOR2XLTS U5334 ( .A(n9686), .B(n9651), .Y(n9560) );
NOR2XLTS U5335 ( .A(n9653), .B(n9652), .Y(n9559) );
NAND2X1TS U5336 ( .A(n8150), .B(n8149), .Y(n8155) );
INVX2TS U5337 ( .A(n5193), .Y(n5090) );
INVX2TS U5338 ( .A(n5188), .Y(n5092) );
ADDHXLTS U5339 ( .A(n9688), .B(n9687), .CO(n9689), .S(
DP_OP_341J35_125_6458_n125) );
NOR2XLTS U5340 ( .A(n9686), .B(n9685), .Y(n9687) );
INVX2TS U5341 ( .A(n9552), .Y(n9682) );
NAND2X1TS U5342 ( .A(n8143), .B(n8142), .Y(n8156) );
XNOR2X1TS U5343 ( .A(n4972), .B(n4971), .Y(n4990) );
NAND2X1TS U5344 ( .A(n4970), .B(n4975), .Y(n4971) );
INVX2TS U5345 ( .A(n4976), .Y(n4970) );
NOR2XLTS U5346 ( .A(n9686), .B(n9652), .Y(n9564) );
NOR2XLTS U5347 ( .A(n9649), .B(n9685), .Y(n9562) );
OAI21X2TS U5348 ( .A0(n8164), .A1(n8114), .B0(n8113), .Y(n8179) );
NAND2X1TS U5349 ( .A(n8189), .B(n8112), .Y(n8114) );
AOI21X1TS U5350 ( .A0(n8188), .A1(n8112), .B0(n8111), .Y(n8113) );
NOR2X1TS U5351 ( .A(n8190), .B(n8169), .Y(n8112) );
XNOR2X1TS U5352 ( .A(n4953), .B(n4952), .Y(n4989) );
NAND2X1TS U5353 ( .A(n4955), .B(n4977), .Y(n4952) );
INVX2TS U5354 ( .A(n4980), .Y(n4929) );
NAND2X1TS U5355 ( .A(n8110), .B(n8109), .Y(n8170) );
NOR2X2TS U5356 ( .A(n8110), .B(n8109), .Y(n8169) );
NOR2X2TS U5357 ( .A(n4917), .B(n4916), .Y(n4928) );
NOR2X2TS U5358 ( .A(n4786), .B(n4785), .Y(n4925) );
NAND2X1TS U5359 ( .A(n4917), .B(n4916), .Y(n4926) );
NAND2X1TS U5360 ( .A(n4786), .B(n4785), .Y(n4927) );
NOR2X1TS U5361 ( .A(n4823), .B(n4821), .Y(n4755) );
OAI21X1TS U5362 ( .A0(n4823), .A1(n4820), .B0(n4824), .Y(n4754) );
OAI21X2TS U5363 ( .A0(n8202), .A1(n8335), .B0(n8203), .Y(n8188) );
NOR2X2TS U5364 ( .A(n8200), .B(n8202), .Y(n8189) );
NOR2X1TS U5365 ( .A(n8135), .B(n8134), .Y(n8195) );
NAND2X1TS U5366 ( .A(n8135), .B(n8134), .Y(n8196) );
AOI21X1TS U5367 ( .A0(n8208), .A1(n1210), .B0(n8133), .Y(n8198) );
INVX2TS U5368 ( .A(n8335), .Y(n8201) );
NAND2X1TS U5369 ( .A(n8106), .B(n8105), .Y(n8203) );
NOR2X2TS U5370 ( .A(n8106), .B(n8105), .Y(n8202) );
NAND2X1TS U5371 ( .A(n8132), .B(n8131), .Y(n8207) );
OAI21X1TS U5372 ( .A0(n8339), .A1(n8342), .B0(n8340), .Y(n8208) );
NOR2X2TS U5373 ( .A(n4753), .B(n4752), .Y(n4823) );
NAND2X1TS U5374 ( .A(n4753), .B(n4752), .Y(n4824) );
INVX2TS U5375 ( .A(n8200), .Y(n8336) );
INVX2TS U5376 ( .A(n8164), .Y(n8338) );
NOR2X1TS U5377 ( .A(n8130), .B(n8129), .Y(n8339) );
NAND2X1TS U5378 ( .A(n8130), .B(n8129), .Y(n8340) );
NOR2X2TS U5379 ( .A(n4751), .B(n4750), .Y(n4821) );
NAND2X1TS U5380 ( .A(n4751), .B(n4750), .Y(n4820) );
ADDFX2TS U5381 ( .A(n2193), .B(n2192), .CI(n2191), .CO(n4829), .S(n4796) );
OAI22X1TS U5382 ( .A0(n2194), .A1(n2198), .B0(n2195), .B1(n2190), .Y(n2193)
);
NOR2X2TS U5383 ( .A(n2200), .B(n2194), .Y(n4795) );
NOR2X2TS U5384 ( .A(n7986), .B(n7985), .Y(n8320) );
NAND2X1TS U5385 ( .A(n7986), .B(n7985), .Y(n8321) );
ADDHX1TS U5386 ( .A(n7779), .B(n7778), .CO(n7825), .S(n8326) );
NOR2X1TS U5387 ( .A(n745), .B(n739), .Y(n7778) );
NOR2X1TS U5388 ( .A(n734), .B(n747), .Y(n7779) );
NOR2X2TS U5389 ( .A(n736), .B(DP_OP_343J35_127_4270_n857), .Y(n8325) );
NAND2X1TS U5390 ( .A(n8326), .B(n8325), .Y(n8327) );
XOR2X1TS U5391 ( .A(n4801), .B(n4800), .Y(n4816) );
NAND2X1TS U5392 ( .A(n4799), .B(n4798), .Y(n4801) );
NOR2X2TS U5393 ( .A(n3906), .B(n3905), .Y(n5125) );
NOR2X2TS U5394 ( .A(n3904), .B(n3903), .Y(n5122) );
NAND2X1TS U5395 ( .A(n3904), .B(n3903), .Y(n5124) );
NAND2X1TS U5396 ( .A(n3906), .B(n3905), .Y(n5123) );
OAI21X2TS U5397 ( .A0(n5171), .A1(n5170), .B0(n5169), .Y(n5477) );
NAND2X1TS U5398 ( .A(n10122), .B(n10121), .Y(n5473) );
NOR2X2TS U5399 ( .A(n5168), .B(n5171), .Y(n5471) );
NOR2X1TS U5400 ( .A(n5470), .B(n5474), .Y(n5476) );
NOR2X2TS U5401 ( .A(n7984), .B(n7983), .Y(n8318) );
INVX2TS U5402 ( .A(n8311), .Y(n8319) );
NAND2X1TS U5403 ( .A(n7984), .B(n7983), .Y(n8317) );
NOR2X2TS U5404 ( .A(n736), .B(n739), .Y(n8315) );
NOR2X2TS U5405 ( .A(DP_OP_343J35_127_4270_n857), .B(n747), .Y(n8314) );
NAND2X1TS U5406 ( .A(n8315), .B(n8314), .Y(n8316) );
ADDHX1TS U5407 ( .A(n4811), .B(n4810), .CO(n4802), .S(n4812) );
NOR2X1TS U5408 ( .A(n7982), .B(n7981), .Y(n8304) );
AOI21X1TS U5409 ( .A0(n8275), .A1(n1208), .B0(n7974), .Y(n8307) );
INVX2TS U5410 ( .A(n8274), .Y(n7974) );
NAND2X1TS U5411 ( .A(n7982), .B(n7981), .Y(n8305) );
NAND2X1TS U5412 ( .A(n4566), .B(n4743), .Y(n4570) );
OAI21X1TS U5413 ( .A0(n4577), .A1(n4576), .B0(n4575), .Y(n4578) );
NAND2X1TS U5414 ( .A(n4571), .B(n850), .Y(n4576) );
AOI21X1TS U5415 ( .A0(n4574), .A1(n850), .B0(n4573), .Y(n4575) );
AOI21X1TS U5416 ( .A0(n5453), .A1(n5441), .B0(n5167), .Y(n5202) );
INVX2TS U5417 ( .A(n5451), .Y(n5200) );
AOI21X1TS U5418 ( .A0(n7365), .A1(n1217), .B0(n7332), .Y(n7333) );
INVX2TS U5419 ( .A(n7363), .Y(n7332) );
OAI22X1TS U5420 ( .A0(n7267), .A1(n7321), .B0(n728), .B1(Op_MX[48]), .Y(
n7298) );
OAI22X1TS U5421 ( .A0(n7294), .A1(n905), .B0(n7268), .B1(n7381), .Y(n7297)
);
OAI22X1TS U5422 ( .A0(n7294), .A1(n7381), .B0(n7317), .B1(n905), .Y(n7323)
);
OAI21X1TS U5423 ( .A0(n7251), .A1(n7250), .B0(n7249), .Y(n7292) );
NOR2X1TS U5424 ( .A(n7329), .B(n7302), .Y(n7304) );
NAND2X1TS U5425 ( .A(DP_OP_342J35_126_4270_n129), .B(n7313), .Y(n7363) );
AOI21X1TS U5426 ( .A0(n7371), .A1(n7304), .B0(n7303), .Y(n7305) );
AOI21X1TS U5427 ( .A0(n7371), .A1(n7282), .B0(n7281), .Y(n7283) );
INVX2TS U5428 ( .A(n7367), .Y(n7281) );
INVX2TS U5429 ( .A(n7302), .Y(n7328) );
NOR2X2TS U5430 ( .A(DP_OP_342J35_126_4270_n146), .B(
DP_OP_342J35_126_4270_n156), .Y(n7260) );
NOR2X2TS U5431 ( .A(DP_OP_342J35_126_4270_n157), .B(
DP_OP_342J35_126_4270_n168), .Y(n7258) );
INVX2TS U5432 ( .A(n7371), .Y(n7262) );
INVX2TS U5433 ( .A(n7329), .Y(n7282) );
NOR2X2TS U5434 ( .A(n7258), .B(n7260), .Y(n7330) );
NOR2X2TS U5435 ( .A(n9792), .B(n9791), .Y(n7290) );
INVX2TS U5436 ( .A(n7292), .Y(n7266) );
NOR2X2TS U5437 ( .A(n9874), .B(n9794), .Y(n7287) );
NAND2X1TS U5438 ( .A(n9792), .B(n9791), .Y(n7288) );
NAND2X1TS U5439 ( .A(n9874), .B(n9794), .Y(n7289) );
CMPR42X1TS U5440 ( .A(DP_OP_342J35_126_4270_n287), .B(
DP_OP_342J35_126_4270_n406), .C(DP_OP_342J35_126_4270_n334), .D(
DP_OP_342J35_126_4270_n409), .ICI(DP_OP_342J35_126_4270_n286), .S(
DP_OP_342J35_126_4270_n262), .ICO(DP_OP_342J35_126_4270_n260), .CO(
DP_OP_342J35_126_4270_n261) );
NOR2X1TS U5441 ( .A(n9841), .B(n9836), .Y(DP_OP_342J35_126_4270_n334) );
INVX2TS U5442 ( .A(n9868), .Y(DP_OP_342J35_126_4270_n287) );
ADDHX1TS U5443 ( .A(DP_OP_342J35_126_4270_n260), .B(n9809), .CO(
DP_OP_342J35_126_4270_n255), .S(DP_OP_342J35_126_4270_n256) );
INVX2TS U5444 ( .A(n9808), .Y(n9809) );
OAI22X2TS U5445 ( .A0(n7255), .A1(n728), .B0(n7055), .B1(n7321), .Y(n9875)
);
XOR2X1TS U5446 ( .A(n9826), .B(n9825), .Y(n9827) );
NAND2X1TS U5447 ( .A(n9824), .B(n9823), .Y(n9825) );
INVX2TS U5448 ( .A(n9822), .Y(n9824) );
XOR2X1TS U5449 ( .A(n7037), .B(n7309), .Y(n7038) );
NAND2X1TS U5450 ( .A(n7035), .B(n7308), .Y(n7037) );
INVX2TS U5451 ( .A(n7310), .Y(n7035) );
INVX2TS U5452 ( .A(DP_OP_342J35_126_4270_n772), .Y(n9806) );
OAI22X1TS U5453 ( .A0(n9840), .A1(n9836), .B0(n9841), .B1(n9835), .Y(n9807)
);
INVX2TS U5454 ( .A(n9804), .Y(n9805) );
OAI22X1TS U5455 ( .A0(n9847), .A1(n9848), .B0(n9840), .B1(n9846), .Y(n7046)
);
CMPR42X1TS U5456 ( .A(DP_OP_342J35_126_4270_n263), .B(
DP_OP_342J35_126_4270_n772), .C(DP_OP_342J35_126_4270_n342), .D(
DP_OP_342J35_126_4270_n264), .ICI(DP_OP_342J35_126_4270_n262), .S(
DP_OP_342J35_126_4270_n259), .ICO(DP_OP_342J35_126_4270_n257), .CO(
DP_OP_342J35_126_4270_n258) );
OAI22X1TS U5457 ( .A0(n9840), .A1(n9842), .B0(n9839), .B1(n9841), .Y(
DP_OP_342J35_126_4270_n342) );
NAND2X1TS U5458 ( .A(n7051), .B(n7261), .Y(n7052) );
INVX2TS U5459 ( .A(n7258), .Y(n7051) );
NAND2X1TS U5460 ( .A(Op_MY[48]), .B(Op_MY[41]), .Y(n7040) );
INVX2TS U5461 ( .A(n7045), .Y(n7041) );
INVX2TS U5462 ( .A(n9877), .Y(DP_OP_342J35_126_4270_n408) );
ADDHXLTS U5463 ( .A(Op_MX[40]), .B(Op_MX[47]), .CO(n7044), .S(n7039) );
NOR2X1TS U5464 ( .A(n730), .B(n748), .Y(n7124) );
CMPR42X1TS U5465 ( .A(DP_OP_342J35_126_4270_n239), .B(
DP_OP_342J35_126_4270_n240), .C(DP_OP_342J35_126_4270_n236), .D(
DP_OP_342J35_126_4270_n231), .ICI(DP_OP_342J35_126_4270_n228), .S(
DP_OP_342J35_126_4270_n225), .ICO(DP_OP_342J35_126_4270_n223), .CO(
DP_OP_342J35_126_4270_n224) );
CMPR42X1TS U5466 ( .A(DP_OP_342J35_126_4270_n324), .B(
DP_OP_342J35_126_4270_n348), .C(DP_OP_342J35_126_4270_n251), .D(
DP_OP_342J35_126_4270_n244), .ICI(DP_OP_342J35_126_4270_n248), .S(
DP_OP_342J35_126_4270_n238), .ICO(DP_OP_342J35_126_4270_n236), .CO(
DP_OP_342J35_126_4270_n237) );
OAI22X1TS U5467 ( .A0(n9833), .A1(n9841), .B0(n9834), .B1(n9840), .Y(
DP_OP_342J35_126_4270_n324) );
CMPR42X1TS U5468 ( .A(DP_OP_342J35_126_4270_n253), .B(
DP_OP_342J35_126_4270_n282), .C(DP_OP_342J35_126_4270_n332), .D(
DP_OP_342J35_126_4270_n250), .ICI(DP_OP_342J35_126_4270_n247), .S(
DP_OP_342J35_126_4270_n241), .ICO(DP_OP_342J35_126_4270_n239), .CO(
DP_OP_342J35_126_4270_n240) );
OAI22X1TS U5469 ( .A0(n9847), .A1(n9836), .B0(n9840), .B1(n9835), .Y(
DP_OP_342J35_126_4270_n332) );
NOR2X2TS U5470 ( .A(n9858), .B(n9859), .Y(n7187) );
NAND2X1TS U5471 ( .A(n9858), .B(n9859), .Y(n7188) );
NOR2X1TS U5472 ( .A(n9829), .B(n762), .Y(n7113) );
NAND2X1TS U5473 ( .A(n9854), .B(n9855), .Y(n7199) );
NOR2X2TS U5474 ( .A(n9854), .B(n9855), .Y(n7198) );
NAND2X1TS U5475 ( .A(DP_OP_342J35_126_4270_n211), .B(
DP_OP_342J35_126_4270_n224), .Y(n7070) );
OAI21X1TS U5476 ( .A0(n7168), .A1(n1225), .B0(n7169), .Y(n7071) );
CMPR42X1TS U5477 ( .A(DP_OP_342J35_126_4270_n188), .B(
DP_OP_342J35_126_4270_n175), .C(DP_OP_342J35_126_4270_n185), .D(
DP_OP_342J35_126_4270_n181), .ICI(DP_OP_342J35_126_4270_n172), .S(
DP_OP_342J35_126_4270_n169), .ICO(DP_OP_342J35_126_4270_n167), .CO(
DP_OP_342J35_126_4270_n168) );
NOR2X1TS U5478 ( .A(DP_OP_342J35_126_4270_n197), .B(
DP_OP_342J35_126_4270_n210), .Y(n7065) );
NAND2X1TS U5479 ( .A(DP_OP_342J35_126_4270_n197), .B(
DP_OP_342J35_126_4270_n210), .Y(n7066) );
AOI21X1TS U5480 ( .A0(n1220), .A1(n7071), .B0(n7048), .Y(n7068) );
INVX2TS U5481 ( .A(n7070), .Y(n7048) );
CMPR42X1TS U5482 ( .A(DP_OP_342J35_126_4270_n206), .B(
DP_OP_342J35_126_4270_n213), .C(DP_OP_342J35_126_4270_n203), .D(
DP_OP_342J35_126_4270_n209), .ICI(DP_OP_342J35_126_4270_n200), .S(
DP_OP_342J35_126_4270_n197), .ICO(DP_OP_342J35_126_4270_n195), .CO(
DP_OP_342J35_126_4270_n196) );
CMPR42X1TS U5483 ( .A(DP_OP_342J35_126_4270_n202), .B(
DP_OP_342J35_126_4270_n199), .C(DP_OP_342J35_126_4270_n189), .D(
DP_OP_342J35_126_4270_n195), .ICI(DP_OP_342J35_126_4270_n186), .S(
DP_OP_342J35_126_4270_n183), .ICO(DP_OP_342J35_126_4270_n181), .CO(
DP_OP_342J35_126_4270_n182) );
OAI21X2TS U5484 ( .A0(n7068), .A1(n7065), .B0(n7066), .Y(n7061) );
OAI32X1TS U5485 ( .A0(n2970), .A1(n7486), .A2(n9588), .B0(n9586), .B1(n2970),
.Y(n2997) );
ADDHXLTS U5486 ( .A(n2992), .B(n2991), .CO(n3014), .S(n3010) );
INVX4TS U5487 ( .A(n9637), .Y(n9592) );
INVX2TS U5488 ( .A(n7331), .Y(n7365) );
OR2X2TS U5489 ( .A(DP_OP_342J35_126_4270_n129), .B(n7313), .Y(n1217) );
NOR2X2TS U5490 ( .A(n7368), .B(n7329), .Y(n7370) );
NAND2X2TS U5491 ( .A(DP_OP_342J35_126_4270_n145), .B(
DP_OP_342J35_126_4270_n137), .Y(n7367) );
NOR2X1TS U5492 ( .A(n7233), .B(n7231), .Y(n7050) );
OAI21X1TS U5493 ( .A0(n7233), .A1(n7230), .B0(n7234), .Y(n7049) );
NAND2X1TS U5494 ( .A(n7330), .B(n7370), .Y(n7374) );
ADDHXLTS U5495 ( .A(n7127), .B(n7126), .CO(n7130), .S(n7135) );
INVX2TS U5496 ( .A(n7486), .Y(n9660) );
NOR2XLTS U5497 ( .A(n9666), .B(n9686), .Y(DP_OP_341J35_125_6458_n148) );
NOR2X1TS U5498 ( .A(n5188), .B(n967), .Y(n5192) );
CLKMX2X2TS U5499 ( .A(DP_OP_338J35_122_4684_n1305), .B(
DP_OP_338J35_122_4684_n1304), .S0(DP_OP_338J35_122_4684_n1308), .Y(
DP_OP_338J35_122_4684_n1303) );
NOR2X1TS U5500 ( .A(n880), .B(n774), .Y(n1443) );
NAND2X1TS U5501 ( .A(n989), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(n5187) );
CLKAND2X2TS U5502 ( .A(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .B(Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(n989) );
NOR2X1TS U5503 ( .A(n5188), .B(n5135), .Y(n5137) );
INVX2TS U5504 ( .A(n2452), .Y(n2630) );
INVX2TS U5505 ( .A(n2381), .Y(n2688) );
OAI22X1TS U5506 ( .A0(n2744), .A1(n2798), .B0(n2799), .B1(n2672), .Y(n2804)
);
XNOR2X1TS U5507 ( .A(n2386), .B(n2385), .Y(n2387) );
NAND2X1TS U5508 ( .A(n2384), .B(n2383), .Y(n2385) );
NAND2X1TS U5509 ( .A(Op_MY[22]), .B(Op_MY[15]), .Y(n5681) );
NAND2X1TS U5510 ( .A(Op_MY[23]), .B(Op_MY[16]), .Y(n5676) );
NOR2XLTS U5511 ( .A(n5897), .B(n735), .Y(n5719) );
NOR2XLTS U5512 ( .A(n746), .B(n735), .Y(n5997) );
OAI21X2TS U5513 ( .A0(n2958), .A1(n2955), .B0(n2959), .Y(n2918) );
NOR2X2TS U5514 ( .A(n2956), .B(n2958), .Y(n2917) );
NOR2X1TS U5515 ( .A(n9934), .B(n9933), .Y(n2905) );
NOR2XLTS U5516 ( .A(n9959), .B(n2799), .Y(n2781) );
NOR2X2TS U5517 ( .A(n9975), .B(n9974), .Y(n2958) );
NOR2XLTS U5518 ( .A(n9928), .B(n2799), .Y(n2788) );
OAI21X2TS U5519 ( .A0(n2931), .A1(n2928), .B0(n2929), .Y(n2936) );
NOR2X2TS U5520 ( .A(n10041), .B(n10031), .Y(n2942) );
NAND2X1TS U5521 ( .A(n5957), .B(n5956), .Y(n6203) );
AOI21X1TS U5522 ( .A0(n1188), .A1(n5955), .B0(n5954), .Y(n6205) );
NOR2X1TS U5523 ( .A(n5957), .B(n5956), .Y(n6202) );
OAI21X1TS U5524 ( .A0(n6237), .A1(n6232), .B0(n6231), .Y(n6295) );
NOR2X1TS U5525 ( .A(n6252), .B(n6242), .Y(n6230) );
ADDHXLTS U5526 ( .A(n5689), .B(n5688), .CO(n5685), .S(n5793) );
ADDHXLTS U5527 ( .A(Op_MX[21]), .B(Op_MX[14]), .CO(n5713), .S(n5808) );
NOR2X2TS U5528 ( .A(n6848), .B(n6847), .Y(n10107) );
NAND2X1TS U5529 ( .A(n6848), .B(n6847), .Y(n10108) );
NAND2X1TS U5530 ( .A(n3755), .B(n3754), .Y(n3756) );
NOR2X1TS U5531 ( .A(n3279), .B(n3278), .Y(n3757) );
NOR2X2TS U5532 ( .A(n3721), .B(n3720), .Y(n3744) );
NOR2X2TS U5533 ( .A(n3719), .B(n3718), .Y(n3749) );
NAND2X1TS U5534 ( .A(n3721), .B(n3720), .Y(n3745) );
NAND2X1TS U5535 ( .A(n3719), .B(n3718), .Y(n3750) );
NAND2X1TS U5536 ( .A(n3285), .B(n3284), .Y(n3741) );
OR2X1TS U5537 ( .A(n3285), .B(n3284), .Y(n1065) );
OR2X1TS U5538 ( .A(n3757), .B(n3283), .Y(n1007) );
NAND2X1TS U5539 ( .A(n3325), .B(n3324), .Y(n3780) );
OR2X1TS U5540 ( .A(n3325), .B(n3324), .Y(n927) );
OAI21X1TS U5541 ( .A0(n3706), .A1(n3703), .B0(n3704), .Y(n3781) );
NOR2X1TS U5542 ( .A(n3334), .B(n3333), .Y(n3794) );
NAND2X1TS U5543 ( .A(n3334), .B(n3333), .Y(n3795) );
XOR2X1TS U5544 ( .A(n6201), .B(n6200), .Y(n6298) );
NAND2X1TS U5545 ( .A(n6199), .B(n6198), .Y(n6201) );
XNOR2X1TS U5546 ( .A(n6290), .B(n6289), .Y(n6296) );
AO21XLTS U5547 ( .A0(n6295), .A1(n6294), .B0(n6293), .Y(n1166) );
XNOR2X1TS U5548 ( .A(Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[26]),
.B(n6839), .Y(n6836) );
INVX2TS U5549 ( .A(n8579), .Y(n6831) );
NOR2X2TS U5550 ( .A(n6884), .B(n6883), .Y(n6890) );
XOR2X1TS U5551 ( .A(n3702), .B(n3701), .Y(n3819) );
NAND2X1TS U5552 ( .A(n3700), .B(n3699), .Y(n3701) );
INVX2TS U5553 ( .A(n3698), .Y(n3700) );
NAND2X1TS U5554 ( .A(n3693), .B(n3692), .Y(n3694) );
INVX2TS U5555 ( .A(n3691), .Y(n3693) );
NOR2X2TS U5556 ( .A(n2081), .B(n2173), .Y(n5340) );
NOR2X2TS U5557 ( .A(n2174), .B(n2098), .Y(n5339) );
NAND2X1TS U5558 ( .A(n5340), .B(n5339), .Y(n5341) );
NAND2X1TS U5559 ( .A(n7973), .B(n7972), .Y(n8274) );
OR2X1TS U5560 ( .A(n7973), .B(n7972), .Y(n1208) );
NAND2X1TS U5561 ( .A(n5441), .B(n5450), .Y(n5442) );
XOR2X1TS U5562 ( .A(n4502), .B(n4568), .Y(n4517) );
NAND2X1TS U5563 ( .A(n4499), .B(n4567), .Y(n4502) );
XNOR2X1TS U5564 ( .A(n4515), .B(n4514), .Y(n4516) );
NAND2X1TS U5565 ( .A(n850), .B(n4572), .Y(n4514) );
ADDFX2TS U5566 ( .A(n2731), .B(n2730), .CI(n2729), .CO(n2856), .S(n2854) );
XOR2X1TS U5567 ( .A(n6236), .B(n6235), .Y(n6283) );
XOR2X1TS U5568 ( .A(n6246), .B(n6245), .Y(n6282) );
AOI21X1TS U5569 ( .A0(n6273), .A1(n6241), .B0(n6240), .Y(n6246) );
OAI21X1TS U5570 ( .A0(n2957), .A1(n2901), .B0(n2900), .Y(n6591) );
AOI21X1TS U5571 ( .A0(n2918), .A1(n2899), .B0(n2898), .Y(n2900) );
XNOR2X1TS U5572 ( .A(n2256), .B(n986), .Y(n6601) );
OAI22X2TS U5573 ( .A0(n3141), .A1(n1449), .B0(n3134), .B1(n3245), .Y(n3717)
);
XNOR2X1TS U5574 ( .A(n10100), .B(n10099), .Y(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[7]) );
NAND2X1TS U5575 ( .A(n10098), .B(n10097), .Y(n10099) );
NAND2X1TS U5576 ( .A(n3772), .B(n3771), .Y(n3773) );
NAND2X1TS U5577 ( .A(n925), .B(n3765), .Y(n3767) );
NOR2XLTS U5578 ( .A(n2745), .B(n2688), .Y(n2679) );
INVX2TS U5579 ( .A(n6567), .Y(n2855) );
NAND2X1TS U5580 ( .A(n2857), .B(n2856), .Y(n2929) );
NOR2XLTS U5581 ( .A(n2799), .B(n2798), .Y(n2926) );
OAI21X1TS U5582 ( .A0(n6718), .A1(n6715), .B0(n6716), .Y(n6274) );
XOR2X1TS U5583 ( .A(n10116), .B(n10115), .Y(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[4]) );
XOR2X1TS U5584 ( .A(n10096), .B(n10095), .Y(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[8]) );
NAND2X1TS U5585 ( .A(n10094), .B(n10093), .Y(n10095) );
AOI21X1TS U5586 ( .A0(n10100), .A1(n10098), .B0(n10091), .Y(n10096) );
XNOR2X1TS U5587 ( .A(n3733), .B(n3732), .Y(n3777) );
NAND2X1TS U5588 ( .A(n3784), .B(n3802), .Y(n3732) );
OAI21XLTS U5589 ( .A0(n3809), .A1(n3729), .B0(n3728), .Y(n3733) );
INVX2TS U5590 ( .A(n5596), .Y(n5309) );
XOR2X1TS U5591 ( .A(n4367), .B(n1078), .Y(n5307) );
NAND2X1TS U5592 ( .A(n4366), .B(n4365), .Y(n4367) );
INVX2TS U5593 ( .A(n5591), .Y(n5322) );
XNOR2X1TS U5594 ( .A(n5325), .B(n983), .Y(n5351) );
NAND2X1TS U5595 ( .A(n815), .B(n5324), .Y(n5325) );
NOR2X1TS U5596 ( .A(n4496), .B(n4473), .Y(n4355) );
NAND2X1TS U5597 ( .A(n4496), .B(n4473), .Y(n4356) );
OA21XLTS U5598 ( .A0(n4345), .A1(n4348), .B0(n4346), .Y(n1011) );
INVX2TS U5599 ( .A(n5244), .Y(n5246) );
NAND2X1TS U5600 ( .A(n8218), .B(n8217), .Y(n8243) );
NAND2X1TS U5601 ( .A(n7949), .B(n7948), .Y(n8231) );
NOR2X1TS U5602 ( .A(n7949), .B(n7948), .Y(n8230) );
OR2X2TS U5603 ( .A(n5111), .B(n5110), .Y(n940) );
NAND2X1TS U5604 ( .A(n5111), .B(n5110), .Y(n5220) );
NOR2X1TS U5605 ( .A(n5397), .B(n5396), .Y(n5500) );
NAND2X1TS U5606 ( .A(n5397), .B(n5396), .Y(n5501) );
OA21XLTS U5607 ( .A0(n4257), .A1(n4226), .B0(n4258), .Y(n1044) );
INVX2TS U5608 ( .A(n4262), .Y(n4264) );
NAND2X1TS U5609 ( .A(n4228), .B(n4227), .Y(n4263) );
NAND2X1TS U5610 ( .A(n4241), .B(n4240), .Y(n4242) );
OAI21X1TS U5611 ( .A0(n8287), .A1(n8286), .B0(n8285), .Y(n8298) );
NAND2X1TS U5612 ( .A(n8278), .B(n8283), .Y(n8286) );
AOI21X1TS U5613 ( .A0(n8284), .A1(n8283), .B0(n8282), .Y(n8285) );
NOR2X1TS U5614 ( .A(n8277), .B(n8280), .Y(n8283) );
OR2X1TS U5615 ( .A(n8289), .B(n8288), .Y(n1073) );
NAND2X1TS U5616 ( .A(n4758), .B(n4757), .Y(n4504) );
NAND2X1TS U5617 ( .A(n1045), .B(n4500), .Y(n4232) );
AO21X1TS U5618 ( .A0(n1089), .A1(n4236), .B0(n4231), .Y(n987) );
INVX2TS U5619 ( .A(n5606), .Y(n5413) );
XNOR2X1TS U5620 ( .A(n6318), .B(n6317), .Y(n6323) );
NAND2X1TS U5621 ( .A(n6316), .B(n6315), .Y(n6317) );
XOR2X1TS U5622 ( .A(n6187), .B(n6186), .Y(n6325) );
AOI21X1TS U5623 ( .A0(n6318), .A1(n6316), .B0(n6182), .Y(n6187) );
XNOR2X1TS U5624 ( .A(n6190), .B(n6189), .Y(n6324) );
INVX2TS U5625 ( .A(n5593), .Y(n5316) );
NAND2X1TS U5626 ( .A(n4361), .B(n4360), .Y(n4363) );
NOR2X2TS U5627 ( .A(n5355), .B(n5354), .Y(n5554) );
NAND2X1TS U5628 ( .A(n6605), .B(n6822), .Y(n6340) );
NOR2X1TS U5629 ( .A(n6812), .B(n6340), .Y(n6342) );
XNOR2X1TS U5630 ( .A(n3678), .B(n3677), .Y(n1174) );
NOR2X1TS U5631 ( .A(n5430), .B(n5432), .Y(n5435) );
NAND2X1TS U5632 ( .A(n5431), .B(n3877), .Y(n3879) );
XOR2X1TS U5633 ( .A(n3930), .B(n3929), .Y(n3931) );
NOR2X2TS U5634 ( .A(n4077), .B(n4223), .Y(n4330) );
NOR2X2TS U5635 ( .A(n4647), .B(n4084), .Y(n4329) );
NAND2X1TS U5636 ( .A(n4330), .B(n4329), .Y(n4331) );
AOI21X2TS U5637 ( .A0(n5283), .A1(n1055), .B0(n5034), .Y(n5392) );
NAND2X1TS U5638 ( .A(n5036), .B(n5035), .Y(n5390) );
ADDHXLTS U5639 ( .A(n7529), .B(n7528), .CO(n7536), .S(n7532) );
NAND2X1TS U5640 ( .A(n4178), .B(n4169), .Y(n4337) );
OR2X1TS U5641 ( .A(n4178), .B(n4169), .Y(n1018) );
NAND2X1TS U5642 ( .A(n4199), .B(n4174), .Y(n4340) );
OR2X1TS U5643 ( .A(n4199), .B(n4174), .Y(n1015) );
AO21X1TS U5644 ( .A0(n1018), .A1(n4338), .B0(n4078), .Y(n984) );
NOR2X1TS U5645 ( .A(n744), .B(n811), .Y(n7537) );
NOR2X1TS U5646 ( .A(n4109), .B(n4179), .Y(n4345) );
NAND2X1TS U5647 ( .A(n4109), .B(n4179), .Y(n4346) );
AOI21X1TS U5648 ( .A0(n1015), .A1(n984), .B0(n4079), .Y(n4348) );
INVX2TS U5649 ( .A(n6811), .Y(n6605) );
NOR2X1TS U5650 ( .A(n5430), .B(n1184), .Y(n5407) );
NAND2X1TS U5651 ( .A(n6333), .B(n6332), .Y(n6618) );
INVX2TS U5652 ( .A(n5601), .Y(n5300) );
XOR2X1TS U5653 ( .A(n6113), .B(n6131), .Y(n6335) );
AOI21X1TS U5654 ( .A0(n6165), .A1(n6106), .B0(n6110), .Y(n6113) );
INVX2TS U5655 ( .A(n5545), .Y(n5367) );
NAND2X1TS U5656 ( .A(n817), .B(n5550), .Y(n5370) );
OR2X1TS U5657 ( .A(n4332), .B(n4336), .Y(n5337) );
XOR2X1TS U5658 ( .A(n5335), .B(n5341), .Y(n5344) );
NOR2XLTS U5659 ( .A(n5898), .B(n5948), .Y(n5949) );
XNOR2X1TS U5660 ( .A(n10106), .B(n10105), .Y(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[6]) );
NAND2X1TS U5661 ( .A(n10104), .B(n10103), .Y(n10105) );
XOR2X1TS U5662 ( .A(n3809), .B(n3740), .Y(n3762) );
NAND2X1TS U5663 ( .A(n3739), .B(n3768), .Y(n3740) );
XOR2X1TS U5664 ( .A(n3738), .B(n3737), .Y(n3763) );
NAND2X1TS U5665 ( .A(n3736), .B(n3735), .Y(n3738) );
NOR2X1TS U5666 ( .A(n5897), .B(n766), .Y(n5703) );
XNOR2X1TS U5667 ( .A(n2259), .B(n2258), .Y(n6599) );
XNOR2X1TS U5668 ( .A(n2913), .B(n2912), .Y(n6588) );
NAND2X1TS U5669 ( .A(n2911), .B(n2910), .Y(n2912) );
NAND2X1TS U5670 ( .A(n10041), .B(n10031), .Y(n2943) );
OAI22X1TS U5671 ( .A0(n5941), .A1(n5898), .B0(n5946), .B1(n5860), .Y(n5936)
);
NOR2X2TS U5672 ( .A(n6226), .B(n6225), .Y(n6252) );
AOI21X1TS U5673 ( .A0(n1204), .A1(n8226), .B0(n7952), .Y(n8265) );
NAND2X1TS U5674 ( .A(n7956), .B(n7955), .Y(n8255) );
OR2X1TS U5675 ( .A(n7956), .B(n7955), .Y(n1206) );
NAND2X1TS U5676 ( .A(n5412), .B(n5411), .Y(n5606) );
OAI21X2TS U5677 ( .A0(n5500), .A1(n998), .B0(n5501), .Y(n5607) );
OAI21X1TS U5678 ( .A0(n4262), .A1(n1044), .B0(n4263), .Y(n4236) );
NAND2X1TS U5679 ( .A(n4230), .B(n4229), .Y(n4235) );
OR2X1TS U5680 ( .A(n4230), .B(n4229), .Y(n1089) );
AOI21X2TS U5681 ( .A0(n4086), .A1(n4238), .B0(n4085), .Y(n4577) );
NOR2X1TS U5682 ( .A(n4244), .B(n4239), .Y(n4086) );
OAI21X1TS U5683 ( .A0(n4239), .A1(n4245), .B0(n4240), .Y(n4085) );
NAND2X1TS U5684 ( .A(n4233), .B(n4505), .Y(n4234) );
NAND2X1TS U5685 ( .A(n5395), .B(n5394), .Y(n5505) );
INVX2TS U5686 ( .A(n4238), .Y(n4248) );
NAND2X1TS U5687 ( .A(n4246), .B(n4245), .Y(n4247) );
NAND2X1TS U5688 ( .A(n4259), .B(n4258), .Y(n4261) );
INVX2TS U5689 ( .A(n4257), .Y(n4259) );
NOR2XLTS U5690 ( .A(n4647), .B(n4714), .Y(n4256) );
NAND2X1TS U5691 ( .A(n7951), .B(n7950), .Y(n8225) );
OR2X1TS U5692 ( .A(n7951), .B(n7950), .Y(n1204) );
OAI21X1TS U5693 ( .A0(n8230), .A1(n8233), .B0(n8231), .Y(n8226) );
NAND2X1TS U5694 ( .A(n4563), .B(n4537), .Y(n4324) );
NAND2X4TS U5695 ( .A(n1150), .B(n7690), .Y(n7943) );
NAND2X1TS U5696 ( .A(n6313), .B(n6312), .Y(n6655) );
OAI21X1TS U5697 ( .A0(n6661), .A1(n6664), .B0(n6662), .Y(n6657) );
NOR2X1TS U5698 ( .A(n6300), .B(n1186), .Y(n6661) );
NAND2X1TS U5699 ( .A(n6300), .B(n1186), .Y(n6662) );
AOI21X1TS U5700 ( .A0(n1043), .A1(n6670), .B0(n6299), .Y(n6664) );
INVX2TS U5701 ( .A(n5587), .Y(n5327) );
XNOR2X1TS U5702 ( .A(n5331), .B(n5330), .Y(n5349) );
NOR2X2TS U5703 ( .A(n3836), .B(n3835), .Y(n5259) );
NAND2X1TS U5704 ( .A(n3836), .B(n3835), .Y(n5260) );
NOR2X2TS U5705 ( .A(n6333), .B(n6332), .Y(n6617) );
NOR2X1TS U5706 ( .A(n6337), .B(n6336), .Y(n6811) );
NOR2X2TS U5707 ( .A(n6335), .B(n6334), .Y(n6812) );
OAI21X2TS U5708 ( .A0(n6625), .A1(n6617), .B0(n6618), .Y(n6817) );
NOR2X1TS U5709 ( .A(n5430), .B(n5420), .Y(n5422) );
XOR2X1TS U5710 ( .A(n6157), .B(n6156), .Y(n6331) );
AOI21X1TS U5711 ( .A0(n6152), .A1(n6318), .B0(n6151), .Y(n6157) );
XOR2X1TS U5712 ( .A(n6162), .B(n6161), .Y(n6330) );
OAI21X2TS U5713 ( .A0(n6651), .A1(n6647), .B0(n6648), .Y(n6630) );
NOR2X2TS U5714 ( .A(n6327), .B(n6326), .Y(n6631) );
NAND2X1TS U5715 ( .A(n6327), .B(n6326), .Y(n6632) );
NAND2X1TS U5716 ( .A(n822), .B(n1096), .Y(n5561) );
AOI21X1TS U5717 ( .A0(n956), .A1(n5359), .B0(n5358), .Y(n5360) );
AOI21X2TS U5718 ( .A0(n822), .A1(n5568), .B0(n5353), .Y(n5562) );
ADDFX2TS U5719 ( .A(n4323), .B(n5306), .CI(n5305), .CO(n4417), .S(n5364) );
XNOR2X1TS U5720 ( .A(n4370), .B(n4369), .Y(n5305) );
NAND2X1TS U5721 ( .A(n1014), .B(n4368), .Y(n4370) );
NOR2X2TS U5722 ( .A(n3871), .B(n3870), .Y(n5234) );
NAND2X1TS U5723 ( .A(n3871), .B(n3870), .Y(n5235) );
NAND2X1TS U5724 ( .A(n3873), .B(n3872), .Y(n5224) );
NOR2X2TS U5725 ( .A(n3873), .B(n3872), .Y(n5223) );
ADDFX2TS U5726 ( .A(n2734), .B(n2733), .CI(n2732), .CO(n2718), .S(n2850) );
NOR2X1TS U5727 ( .A(n9660), .B(n9634), .Y(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[0]) );
XOR2X1TS U5728 ( .A(n7476), .B(n7475), .Y(n9640) );
INVX2TS U5729 ( .A(n8783), .Y(n5142) );
NOR2X2TS U5730 ( .A(n819), .B(DP_OP_343J35_127_4270_n853), .Y(n8160) );
NAND2X1TS U5731 ( .A(n8392), .B(n8382), .Y(n8362) );
NOR2X1TS U5732 ( .A(n8387), .B(n8362), .Y(n8364) );
OAI21X1TS U5733 ( .A0(n8198), .A1(n8195), .B0(n8196), .Y(n8175) );
NAND2X1TS U5734 ( .A(n8137), .B(n8136), .Y(n8180) );
NAND2X1TS U5735 ( .A(n8139), .B(n8138), .Y(n8184) );
CLKXOR2X2TS U5736 ( .A(n4997), .B(n4996), .Y(n995) );
NAND2X1TS U5737 ( .A(n5189), .B(n4993), .Y(n4995) );
NAND2X1TS U5738 ( .A(n8791), .B(n8793), .Y(n8787) );
INVX2TS U5739 ( .A(n8793), .Y(n5117) );
NAND2X1TS U5740 ( .A(n8808), .B(n8799), .Y(n5628) );
NAND2X1TS U5741 ( .A(n8177), .B(n8147), .Y(n8148) );
XNOR2X1TS U5742 ( .A(n8153), .B(n8152), .Y(n8358) );
NOR2X1TS U5743 ( .A(n8359), .B(n8358), .Y(n8377) );
NAND2X1TS U5744 ( .A(n5092), .B(n5190), .Y(n5093) );
OAI21X2TS U5745 ( .A0(n8406), .A1(n8414), .B0(n8407), .Y(n8398) );
NOR2X2TS U5746 ( .A(n8357), .B(n8356), .Y(n8387) );
AOI21X1TS U5747 ( .A0(n8179), .A1(n8120), .B0(n8124), .Y(n8127) );
NOR2X2TS U5748 ( .A(n4990), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(n5105) );
NAND2X1TS U5749 ( .A(n4990), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(n5106) );
XNOR2X1TS U5750 ( .A(n8179), .B(n8178), .Y(n8355) );
NAND2X1TS U5751 ( .A(n8120), .B(n8177), .Y(n8178) );
XNOR2X1TS U5752 ( .A(n8187), .B(n8186), .Y(n8354) );
NAND2X1TS U5753 ( .A(n4989), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n5103) );
NOR2X2TS U5754 ( .A(n4989), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n5104) );
NOR2XLTS U5755 ( .A(n9649), .B(n9652), .Y(n7616) );
ADDHXLTS U5756 ( .A(n7573), .B(n9713), .CO(DP_OP_344J35_128_4078_n103), .S(
n9712) );
XOR2X1TS U5757 ( .A(n8173), .B(n8172), .Y(n8353) );
NAND2X1TS U5758 ( .A(n8171), .B(n8170), .Y(n8172) );
AOI21X1TS U5759 ( .A0(n8338), .A1(n8168), .B0(n8167), .Y(n8173) );
XOR2X1TS U5760 ( .A(n8176), .B(n8182), .Y(n8352) );
OAI21X2TS U5761 ( .A0(n4843), .A1(n4839), .B0(n4840), .Y(n4923) );
XOR2X1TS U5762 ( .A(n4983), .B(n4788), .Y(n4789) );
NAND2X1TS U5763 ( .A(n4787), .B(n4927), .Y(n4788) );
INVX2TS U5764 ( .A(n4925), .Y(n4787) );
XNOR2X1TS U5765 ( .A(n4920), .B(n4919), .Y(n4921) );
NAND2X1TS U5766 ( .A(n4918), .B(n4926), .Y(n4919) );
INVX2TS U5767 ( .A(n4928), .Y(n4918) );
XOR2X1TS U5768 ( .A(n8194), .B(n8193), .Y(n8349) );
NAND2X1TS U5769 ( .A(n8192), .B(n8191), .Y(n8193) );
AOI21X1TS U5770 ( .A0(n8338), .A1(n8189), .B0(n8188), .Y(n8194) );
INVX2TS U5771 ( .A(n8190), .Y(n8192) );
XOR2X1TS U5772 ( .A(n8199), .B(n8198), .Y(n8348) );
ADDHXLTS U5773 ( .A(n9678), .B(n9677), .CO(DP_OP_341J35_125_6458_n434), .S(
n9567) );
OAI32X1TS U5774 ( .A0(n9607), .A1(n7487), .A2(n9615), .B0(n9613), .B1(n9607),
.Y(n9677) );
OAI21X2TS U5775 ( .A0(n8435), .A1(n8431), .B0(n8432), .Y(n8420) );
XOR2X1TS U5776 ( .A(n8206), .B(n8205), .Y(n8347) );
NAND2X1TS U5777 ( .A(n8204), .B(n8203), .Y(n8205) );
AOI21X1TS U5778 ( .A0(n8338), .A1(n8336), .B0(n8201), .Y(n8206) );
INVX2TS U5779 ( .A(n8202), .Y(n8204) );
XNOR2X1TS U5780 ( .A(n8209), .B(n8208), .Y(n8346) );
NAND2X1TS U5781 ( .A(n1210), .B(n8207), .Y(n8209) );
NAND2X1TS U5782 ( .A(n4825), .B(n4824), .Y(n4826) );
INVX2TS U5783 ( .A(n4823), .Y(n4825) );
NOR2XLTS U5784 ( .A(n9615), .B(n9648), .Y(n7463) );
XNOR2X1TS U5785 ( .A(n8338), .B(n8337), .Y(n8345) );
NAND2X1TS U5786 ( .A(n8336), .B(n8335), .Y(n8337) );
XOR2X1TS U5787 ( .A(n8343), .B(n8342), .Y(n8344) );
XOR2X1TS U5788 ( .A(n4793), .B(n4822), .Y(n4818) );
NAND2X1TS U5789 ( .A(n4791), .B(n4820), .Y(n4793) );
INVX2TS U5790 ( .A(n4821), .Y(n4791) );
XNOR2X1TS U5791 ( .A(n8324), .B(n8323), .Y(n8332) );
NAND2X1TS U5792 ( .A(n8322), .B(n8321), .Y(n8323) );
INVX2TS U5793 ( .A(n8320), .Y(n8322) );
XNOR2X1TS U5794 ( .A(n8329), .B(n8328), .Y(n8331) );
NAND2X1TS U5795 ( .A(n4816), .B(n4815), .Y(n4854) );
AOI21X1TS U5796 ( .A0(n5028), .A1(n1133), .B0(n4814), .Y(n4856) );
INVX2TS U5797 ( .A(n5026), .Y(n4814) );
OAI21X1TS U5798 ( .A0(n5125), .A1(n5124), .B0(n5123), .Y(n5126) );
NOR2X1TS U5799 ( .A(n5122), .B(n5125), .Y(n5128) );
OAI21X1TS U5800 ( .A0(n8451), .A1(n8447), .B0(n8448), .Y(n8436) );
XOR2X1TS U5801 ( .A(n8319), .B(n8313), .Y(n8330) );
NAND2X1TS U5802 ( .A(n8312), .B(n8317), .Y(n8313) );
INVX2TS U5803 ( .A(n8318), .Y(n8312) );
CLKAND2X2TS U5804 ( .A(n1201), .B(n8316), .Y(n1202) );
OAI21X2TS U5805 ( .A0(n4806), .A1(n1140), .B0(n4805), .Y(n5028) );
INVX4TS U5806 ( .A(n2968), .Y(DP_OP_341J35_125_6458_n466) );
NOR2X2TS U5807 ( .A(n747), .B(n739), .Y(n8309) );
XOR2X1TS U5808 ( .A(n8308), .B(n8307), .Y(n8310) );
NAND2X1TS U5809 ( .A(n8306), .B(n8305), .Y(n8308) );
INVX2TS U5810 ( .A(n8304), .Y(n8306) );
NAND2X1TS U5811 ( .A(n4579), .B(n4578), .Y(n4805) );
OA21X1TS U5812 ( .A0(n4583), .A1(n4582), .B0(n4581), .Y(n1140) );
INVX2TS U5813 ( .A(n5614), .Y(n5445) );
XNOR2X1TS U5814 ( .A(n7338), .B(n7361), .Y(n7357) );
AOI21X1TS U5815 ( .A0(n7371), .A1(n7370), .B0(n7334), .Y(n7335) );
XOR2X1TS U5816 ( .A(n7350), .B(n7349), .Y(n7356) );
NAND2X1TS U5817 ( .A(n7348), .B(n8740), .Y(n7349) );
AOI21X1TS U5818 ( .A0(n8745), .A1(n8738), .B0(n8744), .Y(n7350) );
NAND2X1TS U5819 ( .A(n9784), .B(n9783), .Y(n7340) );
NAND2X1TS U5820 ( .A(n9873), .B(n9788), .Y(n7341) );
NAND2X1TS U5821 ( .A(n9779), .B(n9778), .Y(n8740) );
NAND2X1TS U5822 ( .A(n9775), .B(n9774), .Y(n8739) );
NOR2X2TS U5823 ( .A(n9873), .B(n9788), .Y(n7339) );
NOR2X2TS U5824 ( .A(n9784), .B(n9783), .Y(n7342) );
NOR2X2TS U5825 ( .A(n9779), .B(n9778), .Y(n8737) );
AOI21X1TS U5826 ( .A0(n7293), .A1(n7292), .B0(n7291), .Y(n7316) );
XNOR2X1TS U5827 ( .A(n7315), .B(n7314), .Y(n7355) );
NAND2X1TS U5828 ( .A(n1217), .B(n7363), .Y(n7314) );
NAND2X1TS U5829 ( .A(n7330), .B(n7304), .Y(n7306) );
XNOR2X1TS U5830 ( .A(n7327), .B(n7326), .Y(n7354) );
NAND2X1TS U5831 ( .A(n7325), .B(n7340), .Y(n7326) );
XNOR2X1TS U5832 ( .A(n7286), .B(n7285), .Y(n7353) );
NAND2X1TS U5833 ( .A(n7328), .B(n7331), .Y(n7285) );
NAND2X1TS U5834 ( .A(n7330), .B(n7282), .Y(n7284) );
XNOR2X1TS U5835 ( .A(n8745), .B(n7301), .Y(n7352) );
NAND2X1TS U5836 ( .A(n7300), .B(n7341), .Y(n7301) );
NOR2X1TS U5837 ( .A(n7353), .B(n7352), .Y(n7395) );
OAI21X1TS U5838 ( .A0(n8475), .A1(n8478), .B0(n8476), .Y(n7406) );
XNOR2X1TS U5839 ( .A(n7248), .B(n7247), .Y(n7276) );
NAND2X1TS U5840 ( .A(n7246), .B(n7259), .Y(n7247) );
INVX2TS U5841 ( .A(n7260), .Y(n7246) );
XOR2X1TS U5842 ( .A(n7266), .B(n7257), .Y(n7275) );
NAND2X1TS U5843 ( .A(n7256), .B(n7289), .Y(n7257) );
XNOR2X1TS U5844 ( .A(n7265), .B(n7264), .Y(n7278) );
NAND2X1TS U5845 ( .A(n7282), .B(n7367), .Y(n7264) );
INVX2TS U5846 ( .A(n7330), .Y(n7263) );
XNOR2X1TS U5847 ( .A(n7274), .B(n7273), .Y(n7277) );
NAND2X1TS U5848 ( .A(n7272), .B(n7288), .Y(n7273) );
CMPR42X1TS U5849 ( .A(DP_OP_342J35_126_4270_n404), .B(
DP_OP_342J35_126_4270_n256), .C(DP_OP_342J35_126_4270_n257), .D(
DP_OP_342J35_126_4270_n261), .ICI(DP_OP_342J35_126_4270_n341), .S(
DP_OP_342J35_126_4270_n252), .ICO(DP_OP_342J35_126_4270_n250), .CO(
DP_OP_342J35_126_4270_n251) );
OAI22X1TS U5850 ( .A0(n9847), .A1(n9842), .B0(n9840), .B1(n9839), .Y(
DP_OP_342J35_126_4270_n341) );
INVX2TS U5851 ( .A(n9875), .Y(DP_OP_342J35_126_4270_n404) );
CMPR42X1TS U5852 ( .A(DP_OP_342J35_126_4270_n254), .B(
DP_OP_342J35_126_4270_n284), .C(DP_OP_342J35_126_4270_n325), .D(
DP_OP_342J35_126_4270_n349), .ICI(DP_OP_342J35_126_4270_n258), .S(
DP_OP_342J35_126_4270_n249), .ICO(DP_OP_342J35_126_4270_n247), .CO(
DP_OP_342J35_126_4270_n248) );
OAI22X1TS U5853 ( .A0(n9849), .A1(n9848), .B0(n9847), .B1(n9846), .Y(
DP_OP_342J35_126_4270_n349) );
NOR2X1TS U5854 ( .A(DP_OP_342J35_126_4270_n259), .B(n7046), .Y(n7203) );
INVX2TS U5855 ( .A(n7203), .Y(n7205) );
NAND2X1TS U5856 ( .A(DP_OP_342J35_126_4270_n259), .B(n7046), .Y(n7204) );
AOI21X1TS U5857 ( .A0(n7210), .A1(n7197), .B0(n7196), .Y(n7202) );
NAND2X1TS U5858 ( .A(n7200), .B(n7199), .Y(n7201) );
NAND2X1TS U5859 ( .A(n7245), .B(n7244), .Y(n8476) );
AOI21X1TS U5860 ( .A0(n8487), .A1(n1048), .B0(n7243), .Y(n8478) );
INVX2TS U5861 ( .A(n8485), .Y(n7243) );
XNOR2X1TS U5862 ( .A(n7191), .B(n7190), .Y(n7523) );
NAND2X1TS U5863 ( .A(n7189), .B(n7188), .Y(n7190) );
NOR2X1TS U5864 ( .A(n9856), .B(n9857), .Y(n7182) );
NOR2X1TS U5865 ( .A(n9841), .B(n9848), .Y(n7192) );
XNOR2X1TS U5866 ( .A(n7042), .B(n7041), .Y(n7043) );
NAND2X1TS U5867 ( .A(n1145), .B(n7040), .Y(n7042) );
CMPR42X1TS U5868 ( .A(DP_OP_342J35_126_4270_n288), .B(
DP_OP_342J35_126_4270_n774), .C(DP_OP_342J35_126_4270_n408), .D(
DP_OP_342J35_126_4270_n289), .ICI(DP_OP_342J35_126_4270_n343), .S(
DP_OP_342J35_126_4270_n265), .ICO(DP_OP_342J35_126_4270_n263), .CO(
DP_OP_342J35_126_4270_n264) );
NOR2XLTS U5869 ( .A(n9842), .B(n9841), .Y(DP_OP_342J35_126_4270_n343) );
NAND2X1TS U5870 ( .A(n1121), .B(n7633), .Y(n7524) );
OR2X1TS U5871 ( .A(n7523), .B(n7522), .Y(n1121) );
NOR2X2TS U5872 ( .A(n9852), .B(n9853), .Y(n7211) );
INVX2TS U5873 ( .A(n9695), .Y(n9707) );
NOR2X2TS U5874 ( .A(n730), .B(n729), .Y(n7307) );
NAND2X1TS U5875 ( .A(DP_OP_342J35_126_4270_n225), .B(
DP_OP_342J35_126_4270_n237), .Y(n7169) );
NOR2X1TS U5876 ( .A(DP_OP_342J35_126_4270_n238), .B(
DP_OP_342J35_126_4270_n241), .Y(n7219) );
NAND2X1TS U5877 ( .A(DP_OP_342J35_126_4270_n238), .B(
DP_OP_342J35_126_4270_n241), .Y(n7220) );
AOI21X1TS U5878 ( .A0(n7186), .A1(n7156), .B0(n7155), .Y(n7173) );
NAND2X1TS U5879 ( .A(n9852), .B(n9853), .Y(n7212) );
NOR2X2TS U5880 ( .A(n7182), .B(n7198), .Y(n7209) );
OAI21X2TS U5881 ( .A0(n7198), .A1(n7195), .B0(n7199), .Y(n7208) );
NOR2X1TS U5882 ( .A(n7211), .B(n7177), .Y(n7158) );
INVX2TS U5883 ( .A(n9693), .Y(n9756) );
XNOR2X1TS U5884 ( .A(n7072), .B(n7071), .Y(n7224) );
NAND2X1TS U5885 ( .A(n1220), .B(n7070), .Y(n7072) );
AO21X1TS U5886 ( .A0(n7167), .A1(n1091), .B0(n7164), .Y(n1066) );
NOR2X2TS U5887 ( .A(DP_OP_342J35_126_4270_n169), .B(
DP_OP_342J35_126_4270_n182), .Y(n7233) );
NAND2X1TS U5888 ( .A(DP_OP_342J35_126_4270_n169), .B(
DP_OP_342J35_126_4270_n182), .Y(n7234) );
NAND2X1TS U5889 ( .A(DP_OP_342J35_126_4270_n772), .B(n9876), .Y(n7238) );
INVX2TS U5890 ( .A(n7064), .Y(n7239) );
XOR2X1TS U5891 ( .A(n7069), .B(n7068), .Y(n7227) );
NAND2X1TS U5892 ( .A(n7067), .B(n7066), .Y(n7069) );
INVX2TS U5893 ( .A(n7065), .Y(n7067) );
NOR2X2TS U5894 ( .A(DP_OP_342J35_126_4270_n183), .B(
DP_OP_342J35_126_4270_n196), .Y(n7231) );
NAND2X1TS U5895 ( .A(DP_OP_342J35_126_4270_n183), .B(
DP_OP_342J35_126_4270_n196), .Y(n7230) );
INVX2TS U5896 ( .A(n7061), .Y(n7232) );
NAND2X1TS U5897 ( .A(DP_OP_342J35_126_4270_n774), .B(n9877), .Y(n7064) );
OAI21X1TS U5898 ( .A0(n7610), .A1(n7606), .B0(n7607), .Y(n7186) );
NOR2X1TS U5899 ( .A(n750), .B(DP_OP_342J35_126_4270_n748), .Y(n7141) );
AOI21X1TS U5900 ( .A0(n7371), .A1(n7370), .B0(n7369), .Y(n7372) );
XOR2X1TS U5901 ( .A(n7387), .B(n7386), .Y(n7388) );
AOI21X1TS U5902 ( .A0(n7378), .A1(n8745), .B0(n7377), .Y(n7387) );
INVX2TS U5903 ( .A(DP_OP_338J35_122_4684_n1449), .Y(n1248) );
AOI21X1TS U5904 ( .A0(n5193), .A1(n5192), .B0(n5191), .Y(n5194) );
NAND2X1TS U5905 ( .A(n5189), .B(n5192), .Y(n5195) );
MXI2X1TS U5906 ( .A(n1253), .B(n1252), .S0(DP_OP_338J35_122_4684_n1449), .Y(
n1246) );
MXI2X1TS U5907 ( .A(n1251), .B(n991), .S0(DP_OP_338J35_122_4684_n1449), .Y(
n1247) );
NOR2X4TS U5908 ( .A(n5104), .B(n5105), .Y(n5189) );
NOR2X1TS U5909 ( .A(n5188), .B(n5187), .Y(n5162) );
NOR2X1TS U5910 ( .A(n5068), .B(n5069), .Y(n4924) );
OAI21X1TS U5911 ( .A0(n5069), .A1(n5066), .B0(n5070), .Y(n4922) );
NAND2X1TS U5912 ( .A(n5189), .B(n5137), .Y(n5139) );
INVX2TS U5913 ( .A(n10378), .Y(n10412) );
NAND2X2TS U5914 ( .A(Op_MY[14]), .B(Op_MY[0]), .Y(n2284) );
ADDHX1TS U5915 ( .A(n2469), .B(n2468), .CO(n2680), .S(n2841) );
NOR2X1TS U5916 ( .A(n2630), .B(n2380), .Y(n2469) );
NOR2X2TS U5917 ( .A(n2859), .B(n2858), .Y(n2940) );
NOR2XLTS U5918 ( .A(n2797), .B(n2799), .Y(n2935) );
XOR2X1TS U5919 ( .A(n5679), .B(n5678), .Y(n5680) );
INVX2TS U5920 ( .A(n5675), .Y(n5677) );
NOR2X1TS U5921 ( .A(n6222), .B(n6221), .Y(n6260) );
NOR2X2TS U5922 ( .A(n6224), .B(n6223), .Y(n6262) );
AOI21X1TS U5923 ( .A0(n6220), .A1(n6274), .B0(n6219), .Y(n6237) );
NOR2XLTS U5924 ( .A(n6275), .B(n6707), .Y(n6220) );
OAI21XLTS U5925 ( .A0(n6275), .A1(n6708), .B0(n6276), .Y(n6219) );
NAND2X1TS U5926 ( .A(n9934), .B(n9933), .Y(n2921) );
INVX2TS U5927 ( .A(n2905), .Y(n2922) );
NOR2X2TS U5928 ( .A(n10021), .B(n10002), .Y(n2956) );
NAND2X1TS U5929 ( .A(n10021), .B(n10002), .Y(n2955) );
NAND2X1TS U5930 ( .A(n9975), .B(n9974), .Y(n2959) );
XNOR2X1TS U5931 ( .A(n6295), .B(n6233), .Y(n6285) );
OAI22X2TS U5932 ( .A0(n3128), .A1(n1449), .B0(n3193), .B1(n3245), .Y(n3712)
);
ADDHX1TS U5933 ( .A(n3191), .B(n3190), .CO(n3034), .S(n3708) );
OAI22X1TS U5934 ( .A0(n3390), .A1(n3388), .B0(n3027), .B1(n899), .Y(n3191)
);
NAND2BXLTS U5935 ( .AN(n3282), .B(n753), .Y(n3027) );
INVX2TS U5936 ( .A(n5808), .Y(n5947) );
NOR2X2TS U5937 ( .A(DP_OP_346J35_130_4270_n836), .B(n772), .Y(n6297) );
NAND2X1TS U5938 ( .A(n6218), .B(n6217), .Y(n6276) );
NOR2X2TS U5939 ( .A(n6218), .B(n6217), .Y(n6275) );
XOR2X1TS U5940 ( .A(n10111), .B(n10110), .Y(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[5]) );
OR2X1TS U5941 ( .A(n3755), .B(n3754), .Y(n950) );
XNOR2X1TS U5942 ( .A(n3742), .B(n1007), .Y(n3760) );
NAND2X1TS U5943 ( .A(n1065), .B(n3741), .Y(n3742) );
INVX2TS U5944 ( .A(n6901), .Y(n6828) );
XNOR2X1TS U5945 ( .A(n3782), .B(n3781), .Y(n3793) );
NAND2X1TS U5946 ( .A(n927), .B(n3780), .Y(n3782) );
XNOR2X1TS U5947 ( .A(n3791), .B(n3790), .Y(n3792) );
OAI21XLTS U5948 ( .A0(n3809), .A1(n3786), .B0(n3785), .Y(n3791) );
XOR2X1TS U5949 ( .A(n3798), .B(n3797), .Y(n3816) );
NAND2X1TS U5950 ( .A(n3796), .B(n3795), .Y(n3797) );
INVX2TS U5951 ( .A(n3794), .Y(n3796) );
XNOR2X1TS U5952 ( .A(n3814), .B(n3813), .Y(n3815) );
OAI21XLTS U5953 ( .A0(n3809), .A1(n3808), .B0(n3807), .Y(n3814) );
NAND2X1TS U5954 ( .A(n3819), .B(n3818), .Y(n5278) );
OR2X1TS U5955 ( .A(n6298), .B(n6297), .Y(n1043) );
NAND2X1TS U5956 ( .A(n6298), .B(n6297), .Y(n6669) );
NOR2X1TS U5957 ( .A(n6296), .B(n1166), .Y(n6675) );
NAND2X1TS U5958 ( .A(n6296), .B(n1166), .Y(n6676) );
INVX2TS U5959 ( .A(n6888), .Y(n6996) );
NOR2X1TS U5960 ( .A(n2174), .B(n2173), .Y(n5579) );
NAND2X1TS U5961 ( .A(n3820), .B(n1064), .Y(n5275) );
OR2X1TS U5962 ( .A(n3819), .B(n3818), .Y(n1061) );
INVX2TS U5963 ( .A(n5278), .Y(n5274) );
OR2X1TS U5964 ( .A(n3820), .B(n1064), .Y(n949) );
XNOR2X1TS U5965 ( .A(n4332), .B(n4336), .Y(n5342) );
INVX2TS U5966 ( .A(n9659), .Y(n3003) );
NAND2X1TS U5967 ( .A(n1208), .B(n8274), .Y(n8276) );
AO21X1TS U5968 ( .A0(n8298), .A1(n1073), .B0(n8290), .Y(n914) );
OAI21X2TS U5969 ( .A0(n5498), .A1(n5495), .B0(n5496), .Y(n5615) );
NOR2X1TS U5970 ( .A(n4517), .B(n4516), .Y(n4583) );
NAND2X1TS U5971 ( .A(n4517), .B(n4516), .Y(n4581) );
NAND2X1TS U5972 ( .A(n2854), .B(n2853), .Y(n6567) );
OAI21X1TS U5973 ( .A0(n6563), .A1(n1139), .B0(n6564), .Y(n6568) );
OR2X1TS U5974 ( .A(n2854), .B(n2853), .Y(n1068) );
XOR2X1TS U5975 ( .A(n2957), .B(n2951), .Y(n6579) );
NAND2X1TS U5976 ( .A(n2950), .B(n2955), .Y(n2951) );
NOR2X1TS U5977 ( .A(n6283), .B(n6282), .Y(n6688) );
NAND2X1TS U5978 ( .A(n6283), .B(n6282), .Y(n6689) );
INVX2TS U5979 ( .A(n7018), .Y(n6790) );
NOR2X1TS U5980 ( .A(n6214), .B(n6213), .Y(n6715) );
NAND2X1TS U5981 ( .A(n6214), .B(n6213), .Y(n6716) );
AOI21X1TS U5982 ( .A0(n6724), .A1(n1067), .B0(n6212), .Y(n6718) );
ADDFX2TS U5983 ( .A(n6638), .B(n6637), .CI(n6636), .CO(n6628), .S(n6799) );
NAND2X1TS U5984 ( .A(n3717), .B(n3716), .Y(n5311) );
NOR2X1TS U5985 ( .A(n3717), .B(n3716), .Y(n5310) );
INVX2TS U5986 ( .A(n8584), .Y(n6609) );
INVX2TS U5987 ( .A(n10335), .Y(n10403) );
AOI21X1TS U5988 ( .A0(n828), .A1(n6551), .B0(n2843), .Y(n6556) );
NOR2X1TS U5989 ( .A(n2845), .B(n2844), .Y(n6553) );
NAND2X1TS U5990 ( .A(n2845), .B(n2844), .Y(n6554) );
NAND2X1TS U5991 ( .A(n2847), .B(n2846), .Y(n6538) );
OAI21X1TS U5992 ( .A0(n6553), .A1(n6556), .B0(n6554), .Y(n6539) );
ADDHXLTS U5993 ( .A(n6373), .B(n6372), .CO(n6425), .S(n6430) );
NAND2X1TS U5994 ( .A(n2930), .B(n2929), .Y(n2932) );
INVX2TS U5995 ( .A(n2928), .Y(n2930) );
ADDHX1TS U5996 ( .A(n5699), .B(n5698), .CO(n5792), .S(n6737) );
NOR2X1TS U5997 ( .A(n847), .B(n767), .Y(n5698) );
NOR2X1TS U5998 ( .A(n6790), .B(n6789), .Y(n6925) );
NOR2X2TS U5999 ( .A(n6216), .B(n6215), .Y(n6707) );
NAND2X1TS U6000 ( .A(n6216), .B(n6215), .Y(n6708) );
XNOR2X1TS U6001 ( .A(n6635), .B(n6634), .Y(n8498) );
NAND2X1TS U6002 ( .A(n6633), .B(n6632), .Y(n6634) );
NAND2X1TS U6003 ( .A(n5357), .B(n5356), .Y(n5553) );
OR2X1TS U6004 ( .A(n5357), .B(n5356), .Y(n956) );
NOR2X1TS U6005 ( .A(n5554), .B(n5561), .Y(n5556) );
NAND2X1TS U6006 ( .A(n5352), .B(n5351), .Y(n5567) );
NOR2X1TS U6007 ( .A(n743), .B(n812), .Y(n7565) );
CLKXOR2X2TS U6008 ( .A(n4358), .B(n1011), .Y(n5593) );
NAND2X1TS U6009 ( .A(n4357), .B(n4356), .Y(n4358) );
NAND2X1TS U6010 ( .A(n8228), .B(n8243), .Y(n8229) );
NAND2X1TS U6011 ( .A(n5502), .B(n5501), .Y(n5503) );
INVX2TS U6012 ( .A(n5500), .Y(n5502) );
XOR2X1TS U6013 ( .A(n4265), .B(n1044), .Y(n4379) );
XNOR2X1TS U6014 ( .A(n4243), .B(n4242), .Y(n4381) );
NAND2X1TS U6015 ( .A(n4264), .B(n4263), .Y(n4265) );
NAND2X1TS U6016 ( .A(n8293), .B(n8292), .Y(n8295) );
XNOR2X1TS U6017 ( .A(n4108), .B(n4107), .Y(n4521) );
XNOR2X1TS U6018 ( .A(n4232), .B(n987), .Y(n4520) );
NAND2X1TS U6019 ( .A(n4106), .B(n4504), .Y(n4107) );
CLKXOR2X2TS U6020 ( .A(n5499), .B(n5498), .Y(n5613) );
NAND2X1TS U6021 ( .A(n5497), .B(n5496), .Y(n5499) );
NOR2X1TS U6022 ( .A(n6323), .B(n6322), .Y(n6647) );
NAND2X1TS U6023 ( .A(n6323), .B(n6322), .Y(n6648) );
NOR2X2TS U6024 ( .A(n6325), .B(n6324), .Y(n6639) );
NAND2X1TS U6025 ( .A(n6325), .B(n6324), .Y(n6640) );
NAND2X1TS U6026 ( .A(n5355), .B(n5354), .Y(n5559) );
INVX2TS U6027 ( .A(n5554), .Y(n5560) );
NAND2X1TS U6028 ( .A(n5241), .B(n5240), .Y(n5242) );
NAND2X1TS U6029 ( .A(n6338), .B(n6822), .Y(n6339) );
INVX2TS U6030 ( .A(n6815), .Y(n6338) );
NAND2X1TS U6031 ( .A(n6342), .B(n6813), .Y(n6344) );
NOR2X1TS U6032 ( .A(n1050), .B(n8767), .Y(n8771) );
OAI21X1TS U6033 ( .A0(n5439), .A1(n5438), .B0(n5437), .Y(n5440) );
NAND2X1TS U6034 ( .A(n5431), .B(n5435), .Y(n5439) );
XNOR2X1TS U6035 ( .A(n5283), .B(n5282), .Y(n5585) );
NAND2X1TS U6036 ( .A(n1055), .B(n5281), .Y(n5282) );
NAND2X1TS U6037 ( .A(n833), .B(n4331), .Y(n4332) );
NOR2X2TS U6038 ( .A(n742), .B(n955), .Y(n7893) );
NOR2XLTS U6039 ( .A(n758), .B(n813), .Y(n7530) );
NOR2X2TS U6040 ( .A(n742), .B(n812), .Y(n7894) );
NAND2X1TS U6041 ( .A(n1018), .B(n4337), .Y(n4339) );
XNOR2X1TS U6042 ( .A(n5272), .B(n5271), .Y(n5525) );
NAND2X1TS U6043 ( .A(n1054), .B(n5270), .Y(n5272) );
XNOR2X2TS U6044 ( .A(n4341), .B(n984), .Y(n5587) );
NAND2X1TS U6045 ( .A(n1015), .B(n4340), .Y(n4341) );
NOR2X1TS U6046 ( .A(n758), .B(n810), .Y(n7540) );
NOR2X1TS U6047 ( .A(n742), .B(n813), .Y(n7551) );
CLKXOR2X2TS U6048 ( .A(n4349), .B(n4348), .Y(n5591) );
NAND2X1TS U6049 ( .A(n4347), .B(n4346), .Y(n4349) );
XNOR2X1TS U6050 ( .A(n6607), .B(n6606), .Y(n8760) );
NAND2X1TS U6051 ( .A(n6605), .B(n6815), .Y(n6606) );
AOI21X1TS U6052 ( .A0(n6817), .A1(n6612), .B0(n6602), .Y(n6603) );
OAI21X1TS U6053 ( .A0(n5409), .A1(n5438), .B0(n5408), .Y(n5410) );
NAND2X1TS U6054 ( .A(n5431), .B(n5407), .Y(n5409) );
XNOR2X1TS U6055 ( .A(n6621), .B(n6620), .Y(n7033) );
NAND2X1TS U6056 ( .A(n6619), .B(n6618), .Y(n6620) );
NAND2X1TS U6057 ( .A(n5366), .B(n5365), .Y(n5545) );
NOR2X1TS U6058 ( .A(n5304), .B(n5364), .Y(n5546) );
XNOR2X1TS U6059 ( .A(n5214), .B(n5213), .Y(n8976) );
NAND2X1TS U6060 ( .A(n5212), .B(n5433), .Y(n5213) );
NAND2X2TS U6061 ( .A(n6335), .B(n6334), .Y(n6814) );
NAND2X1TS U6062 ( .A(n7033), .B(n7030), .Y(n7025) );
OAI21X1TS U6063 ( .A0(n5208), .A1(n5438), .B0(n5207), .Y(n5209) );
NAND2X1TS U6064 ( .A(n5431), .B(n5212), .Y(n5208) );
OAI21X1TS U6065 ( .A0(n5370), .A1(n5551), .B0(n5369), .Y(n5542) );
AOI21X1TS U6066 ( .A0(n817), .A1(n5368), .B0(n5367), .Y(n5369) );
NAND2X1TS U6067 ( .A(n5344), .B(n5343), .Y(n5574) );
NOR2X1TS U6068 ( .A(n1002), .B(n5342), .Y(n5576) );
NAND2X1TS U6069 ( .A(n1063), .B(n5267), .Y(n5269) );
OR2X1TS U6070 ( .A(n5344), .B(n5343), .Y(n1003) );
NAND2X1TS U6071 ( .A(n6222), .B(n6221), .Y(n6270) );
NAND2X1TS U6072 ( .A(n3763), .B(n3762), .Y(n5293) );
AO21X1TS U6073 ( .A0(n1086), .A1(n5296), .B0(n3761), .Y(n968) );
OR2X1TS U6074 ( .A(n3763), .B(n3762), .Y(n921) );
OAI21X1TS U6075 ( .A0(n6729), .A1(n6732), .B0(n6730), .Y(n6724) );
NAND2X1TS U6076 ( .A(n3714), .B(n3713), .Y(n5318) );
OR2X1TS U6077 ( .A(n3714), .B(n3713), .Y(n918) );
NOR2X2TS U6078 ( .A(n744), .B(n812), .Y(n7899) );
NAND2X1TS U6079 ( .A(n2944), .B(n2943), .Y(n2945) );
NOR2X2TS U6080 ( .A(n6260), .B(n6262), .Y(n6251) );
NAND2X1TS U6081 ( .A(n6226), .B(n6225), .Y(n6253) );
OA21XLTS U6082 ( .A0(n6558), .A1(n6561), .B0(n6559), .Y(n1139) );
NOR2X1TS U6083 ( .A(n2852), .B(n2851), .Y(n6563) );
NAND2X1TS U6084 ( .A(n2852), .B(n2851), .Y(n6564) );
ADDHXLTS U6085 ( .A(n10380), .B(n10379), .CO(DP_OP_347J35_131_5122_n104),
.S(DP_OP_347J35_131_5122_n105) );
INVX2TS U6086 ( .A(n10333), .Y(n10423) );
INVX2TS U6087 ( .A(n10341), .Y(n10413) );
XOR2X1TS U6088 ( .A(n8261), .B(n8260), .Y(n8268) );
AOI21X1TS U6089 ( .A0(n8258), .A1(n8278), .B0(n8284), .Y(n8261) );
XOR2X1TS U6090 ( .A(n8266), .B(n8265), .Y(n8267) );
NAND2X1TS U6091 ( .A(n8264), .B(n8263), .Y(n8266) );
AOI21X2TS U6092 ( .A0(n1088), .A1(n8620), .B0(n8239), .Y(n8622) );
XOR2X1TS U6093 ( .A(n8254), .B(n8253), .Y(n8270) );
AOI21X1TS U6094 ( .A0(n8258), .A1(n8249), .B0(n8248), .Y(n8254) );
NAND2X1TS U6095 ( .A(n1206), .B(n8255), .Y(n8257) );
XNOR2X2TS U6096 ( .A(n5608), .B(n5607), .Y(n5610) );
NAND2X1TS U6097 ( .A(n963), .B(n5606), .Y(n5608) );
XNOR2X1TS U6098 ( .A(n4237), .B(n4236), .Y(n4391) );
NAND2X1TS U6099 ( .A(n1089), .B(n4235), .Y(n4237) );
XOR2X1TS U6100 ( .A(n5508), .B(n5507), .Y(n5602) );
INVX2TS U6101 ( .A(n5504), .Y(n5506) );
XNOR2X1TS U6102 ( .A(n4261), .B(n4260), .Y(n4413) );
XOR2X1TS U6103 ( .A(n8224), .B(n8223), .Y(n8238) );
AOI21X1TS U6104 ( .A0(n8258), .A1(n8228), .B0(n8219), .Y(n8224) );
XNOR2X1TS U6105 ( .A(n8227), .B(n8226), .Y(n8237) );
XNOR2X2TS U6106 ( .A(n4326), .B(n4325), .Y(n5596) );
NAND2X1TS U6107 ( .A(n818), .B(n4324), .Y(n4326) );
XNOR2X1TS U6108 ( .A(n5233), .B(n5232), .Y(n5514) );
OAI21X1TS U6109 ( .A0(n7576), .A1(n8210), .B0(n8212), .Y(n7569) );
NAND2X1TS U6110 ( .A(n7567), .B(n8211), .Y(n7568) );
XNOR2X2TS U6111 ( .A(n6657), .B(n6656), .Y(n7020) );
NAND2X1TS U6112 ( .A(n1190), .B(n6655), .Y(n6656) );
INVX2TS U6113 ( .A(Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[29]),
.Y(n7012) );
CLKXOR2X2TS U6114 ( .A(n6665), .B(n6664), .Y(n7018) );
NAND2X1TS U6115 ( .A(n6663), .B(n6662), .Y(n6665) );
NAND2X1TS U6116 ( .A(n5350), .B(n5349), .Y(n5571) );
OR2X1TS U6117 ( .A(n5350), .B(n5349), .Y(n1096) );
XOR2X1TS U6118 ( .A(n5263), .B(n5262), .Y(n9003) );
NAND2X1TS U6119 ( .A(n5261), .B(n5260), .Y(n5263) );
INVX2TS U6120 ( .A(n5259), .Y(n5261) );
NAND2X1TS U6121 ( .A(n1003), .B(n5581), .Y(n5348) );
AOI21X1TS U6122 ( .A0(n1003), .A1(n5346), .B0(n5345), .Y(n5347) );
XNOR2X2TS U6123 ( .A(n6147), .B(n6146), .Y(n6822) );
NOR2X2TS U6124 ( .A(n6624), .B(n6617), .Y(n6813) );
NOR2X1TS U6125 ( .A(n6812), .B(n6811), .Y(n6818) );
AOI21X1TS U6126 ( .A0(n6818), .A1(n6817), .B0(n6816), .Y(n6819) );
NAND2X1TS U6127 ( .A(n8760), .B(n8759), .Y(n8767) );
XNOR2X1TS U6128 ( .A(n5427), .B(n5426), .Y(n8958) );
NAND2X1TS U6129 ( .A(n5431), .B(n5422), .Y(n5424) );
NAND2X1TS U6130 ( .A(n6331), .B(n6330), .Y(n6625) );
NOR2X2TS U6131 ( .A(n6331), .B(n6330), .Y(n6624) );
OAI21X1TS U6132 ( .A0(n6631), .A1(n6640), .B0(n6632), .Y(n6328) );
NOR2X1TS U6133 ( .A(n6631), .B(n6639), .Y(n6329) );
NAND2X1TS U6134 ( .A(n8498), .B(n8495), .Y(n8490) );
INVX2TS U6135 ( .A(n5546), .Y(n5550) );
AOI21X2TS U6136 ( .A0(n5363), .A1(n5572), .B0(n5362), .Y(n5551) );
NOR2X1TS U6137 ( .A(n5361), .B(n5561), .Y(n5363) );
OAI21X1TS U6138 ( .A0(n5361), .A1(n5562), .B0(n5360), .Y(n5362) );
NAND2X1TS U6139 ( .A(n956), .B(n5560), .Y(n5361) );
NAND2X1TS U6140 ( .A(n5304), .B(n5364), .Y(n5549) );
AOI21X1TS U6141 ( .A0(n831), .A1(n6539), .B0(n2848), .Y(n6561) );
NOR2X1TS U6142 ( .A(n2850), .B(n2849), .Y(n6558) );
NAND2X1TS U6143 ( .A(n2850), .B(n2849), .Y(n6559) );
NAND2BXLTS U6144 ( .AN(Op_MY[7]), .B(Op_MX[12]), .Y(n6365) );
NOR2X2TS U6145 ( .A(n751), .B(n761), .Y(n9869) );
CMPR42X1TS U6146 ( .A(DP_OP_344J35_128_4078_n128), .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[0]), .C(DP_OP_344J35_128_4078_n83), .D(DP_OP_344J35_128_4078_n154), .ICI(
DP_OP_344J35_128_4078_n84), .S(DP_OP_344J35_128_4078_n82), .ICO(
DP_OP_344J35_128_4078_n80), .CO(DP_OP_344J35_128_4078_n81) );
INVX2TS U6147 ( .A(n9734), .Y(DP_OP_344J35_128_4078_n128) );
INVX2TS U6148 ( .A(n8781), .Y(n8782) );
OR2X1TS U6149 ( .A(n8161), .B(n8160), .Y(n1127) );
NAND2X1TS U6150 ( .A(n8364), .B(n8397), .Y(n8366) );
AOI21X1TS U6151 ( .A0(n8364), .A1(n8398), .B0(n8363), .Y(n8365) );
NAND2X1TS U6152 ( .A(n8360), .B(n8382), .Y(n8361) );
INVX2TS U6153 ( .A(n8391), .Y(n8360) );
AOI21X2TS U6154 ( .A0(n8141), .A1(n8175), .B0(n8140), .Y(n8373) );
XNOR2X2TS U6155 ( .A(n8788), .B(n995), .Y(n9110) );
XNOR2X2TS U6156 ( .A(n8163), .B(n8162), .Y(n8382) );
NOR2X1TS U6157 ( .A(n8387), .B(n8377), .Y(n8379) );
AOI21X1TS U6158 ( .A0(n8379), .A1(n8398), .B0(n8378), .Y(n8380) );
XNOR2X1TS U6159 ( .A(n8794), .B(n5117), .Y(n9108) );
INVX2TS U6160 ( .A(n8377), .Y(n8392) );
AOI21X1TS U6161 ( .A0(n8402), .A1(n8398), .B0(n8388), .Y(n8389) );
INVX2TS U6162 ( .A(n8401), .Y(n8388) );
INVX2TS U6163 ( .A(n8799), .Y(n5112) );
INVX2TS U6164 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[2]), .Y(n7518) );
INVX2TS U6165 ( .A(n8387), .Y(n8402) );
NAND2X2TS U6166 ( .A(n8357), .B(n8356), .Y(n8401) );
NOR2X2TS U6167 ( .A(n8413), .B(n8406), .Y(n8397) );
XNOR2X2TS U6168 ( .A(n5109), .B(n5108), .Y(n8808) );
NAND2X1TS U6169 ( .A(n5107), .B(n5106), .Y(n5108) );
NAND2X1TS U6170 ( .A(n8355), .B(n8354), .Y(n8407) );
NOR2X2TS U6171 ( .A(n8355), .B(n8354), .Y(n8406) );
XOR2X1TS U6172 ( .A(n5196), .B(n5082), .Y(n8815) );
NOR2X2TS U6173 ( .A(n8353), .B(n8352), .Y(n8413) );
NAND2X1TS U6174 ( .A(n8353), .B(n8352), .Y(n8414) );
NOR2X1TS U6175 ( .A(n8421), .B(n8426), .Y(n8351) );
OAI21X1TS U6176 ( .A0(n8421), .A1(n8427), .B0(n8422), .Y(n8350) );
NOR2X2TS U6177 ( .A(n4921), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n5069) );
NOR2X2TS U6178 ( .A(n4789), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(n5068) );
NAND2X1TS U6179 ( .A(n4789), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(n5066) );
NAND2X1TS U6180 ( .A(n4921), .B(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n5070) );
NOR2X2TS U6181 ( .A(n8349), .B(n8348), .Y(n8421) );
NAND2X1TS U6182 ( .A(n8349), .B(n8348), .Y(n8422) );
NAND2X1TS U6183 ( .A(n4790), .B(n5066), .Y(n4833) );
INVX2TS U6184 ( .A(n5068), .Y(n4790) );
INVX2TS U6185 ( .A(n8420), .Y(n8429) );
NOR2X2TS U6186 ( .A(n8347), .B(n8346), .Y(n8426) );
NAND2X1TS U6187 ( .A(n8347), .B(n8346), .Y(n8427) );
NOR2X1TS U6188 ( .A(n4832), .B(n4831), .Y(n4839) );
NAND2X1TS U6189 ( .A(n4832), .B(n4831), .Y(n4840) );
AOI21X2TS U6190 ( .A0(n1102), .A1(n4848), .B0(n4819), .Y(n4843) );
INVX2TS U6191 ( .A(n4847), .Y(n4819) );
NOR2X1TS U6192 ( .A(n8345), .B(n8344), .Y(n8431) );
OAI21X1TS U6193 ( .A0(n8437), .A1(n8443), .B0(n8438), .Y(n8333) );
NOR2X1TS U6194 ( .A(n8442), .B(n8437), .Y(n8334) );
NAND2X1TS U6195 ( .A(n8345), .B(n8344), .Y(n8432) );
NAND2X1TS U6196 ( .A(n4818), .B(n4817), .Y(n4847) );
CLKMX2X2TS U6197 ( .A(DP_OP_344J35_128_4078_n37), .B(
DP_OP_344J35_128_4078_n36), .S0(DP_OP_344J35_128_4078_n40), .Y(
DP_OP_344J35_128_4078_n35) );
NOR2X2TS U6198 ( .A(n8332), .B(n8331), .Y(n8437) );
NAND2X1TS U6199 ( .A(n8332), .B(n8331), .Y(n8438) );
CLKXOR2X2TS U6200 ( .A(n4857), .B(n4856), .Y(n5624) );
NAND2X1TS U6201 ( .A(n4855), .B(n4854), .Y(n4857) );
OR2X1TS U6202 ( .A(n7596), .B(n7598), .Y(n9724) );
INVX2TS U6203 ( .A(n8436), .Y(n8446) );
NOR2X2TS U6204 ( .A(n8330), .B(n1202), .Y(n8442) );
NAND2X1TS U6205 ( .A(n8330), .B(n1202), .Y(n8443) );
XNOR2X2TS U6206 ( .A(n5489), .B(n5488), .Y(n5623) );
NAND2X1TS U6207 ( .A(n1133), .B(n5026), .Y(n5027) );
NOR2X1TS U6208 ( .A(n8310), .B(n8309), .Y(n8447) );
AOI21X2TS U6209 ( .A0(n8452), .A1(n8303), .B0(n8302), .Y(n8451) );
OAI21X1TS U6210 ( .A0(n8453), .A1(n8631), .B0(n8454), .Y(n8302) );
NOR2X1TS U6211 ( .A(n8453), .B(n8630), .Y(n8303) );
NAND2X1TS U6212 ( .A(n8310), .B(n8309), .Y(n8448) );
CLKXOR2X2TS U6213 ( .A(n4584), .B(n1140), .Y(n5620) );
NAND2X1TS U6214 ( .A(n4580), .B(n4805), .Y(n4584) );
NAND2X2TS U6215 ( .A(n8753), .B(n1024), .Y(n8754) );
NOR2X1TS U6216 ( .A(Op_MY[51]), .B(n8754), .Y(n8736) );
NOR2X2TS U6217 ( .A(n7357), .B(n7356), .Y(n8722) );
OAI21X2TS U6218 ( .A0(n7397), .A1(n7402), .B0(n7398), .Y(n8729) );
NOR2X2TS U6219 ( .A(n7395), .B(n7397), .Y(n8723) );
OAI21X2TS U6220 ( .A0(n7342), .A1(n7341), .B0(n7340), .Y(n8744) );
NOR2X1TS U6221 ( .A(n8737), .B(n8741), .Y(n8743) );
INVX2TS U6222 ( .A(n7316), .Y(n8745) );
INVX2TS U6223 ( .A(n7402), .Y(n7396) );
NAND2X1TS U6224 ( .A(n7355), .B(n7354), .Y(n7398) );
NOR2X2TS U6225 ( .A(n7355), .B(n7354), .Y(n7397) );
INVX2TS U6226 ( .A(n7395), .Y(n7403) );
NOR2X2TS U6227 ( .A(n7278), .B(n7277), .Y(n7407) );
INVX2TS U6228 ( .A(n7406), .Y(n7416) );
NOR2X2TS U6229 ( .A(n7276), .B(n7275), .Y(n7412) );
OR2X1TS U6230 ( .A(DP_OP_342J35_126_4270_n249), .B(
DP_OP_342J35_126_4270_n252), .Y(n1221) );
NAND2X1TS U6231 ( .A(DP_OP_342J35_126_4270_n249), .B(
DP_OP_342J35_126_4270_n252), .Y(n7216) );
AOI21X1TS U6232 ( .A0(n7210), .A1(n7209), .B0(n7208), .Y(n7215) );
NAND2X1TS U6233 ( .A(n7213), .B(n7212), .Y(n7214) );
OAI21X1TS U6234 ( .A0(n7203), .A1(n7206), .B0(n7204), .Y(n7217) );
CMPR42X1TS U6235 ( .A(DP_OP_344J35_128_4078_n120), .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[8]), .C(DP_OP_344J35_128_4078_n146), .D(DP_OP_344J35_128_4078_n59), .ICI(
DP_OP_344J35_128_4078_n60), .S(DP_OP_344J35_128_4078_n58), .ICO(
DP_OP_344J35_128_4078_n56), .CO(DP_OP_344J35_128_4078_n57) );
INVX2TS U6236 ( .A(n9726), .Y(DP_OP_344J35_128_4078_n120) );
INVX2TS U6237 ( .A(n9741), .Y(DP_OP_344J35_128_4078_n146) );
XOR2X1TS U6238 ( .A(n7207), .B(n7206), .Y(n7423) );
XOR2X1TS U6239 ( .A(n7202), .B(n7201), .Y(n7424) );
NAND2X1TS U6240 ( .A(n7205), .B(n7204), .Y(n7207) );
XOR2X1TS U6241 ( .A(n8479), .B(n8478), .Y(n9746) );
NAND2X1TS U6242 ( .A(n8477), .B(n8476), .Y(n8479) );
INVX2TS U6243 ( .A(n8475), .Y(n8477) );
NAND2X1TS U6244 ( .A(n7523), .B(n7522), .Y(n7633) );
NAND2X1TS U6245 ( .A(n9856), .B(n9857), .Y(n7195) );
INVX2TS U6246 ( .A(n7182), .Y(n7197) );
INVX2TS U6247 ( .A(n7173), .Y(n7210) );
OAI22X1TS U6248 ( .A0(n9840), .A1(n9848), .B0(n9841), .B1(n9846), .Y(n7184)
);
CMPR42X1TS U6249 ( .A(DP_OP_344J35_128_4078_n121), .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[7]), .C(DP_OP_344J35_128_4078_n62), .D(DP_OP_344J35_128_4078_n147), .ICI(
DP_OP_344J35_128_4078_n63), .S(DP_OP_344J35_128_4078_n61), .ICO(
DP_OP_344J35_128_4078_n59), .CO(DP_OP_344J35_128_4078_n60) );
INVX2TS U6250 ( .A(n9727), .Y(DP_OP_344J35_128_4078_n121) );
INVX2TS U6251 ( .A(n9742), .Y(DP_OP_344J35_128_4078_n147) );
NAND2X1TS U6252 ( .A(n9850), .B(n9851), .Y(n7178) );
NAND2X1TS U6253 ( .A(n7221), .B(n7220), .Y(n7223) );
INVX2TS U6254 ( .A(n7219), .Y(n7221) );
NOR2XLTS U6255 ( .A(n7172), .B(n7211), .Y(n7176) );
AOI21X1TS U6256 ( .A0(n1221), .A1(n7217), .B0(n7047), .Y(n7222) );
INVX2TS U6257 ( .A(n7216), .Y(n7047) );
INVX2TS U6258 ( .A(n9708), .Y(n9709) );
OR2X1TS U6259 ( .A(n9765), .B(n7307), .Y(n1091) );
NAND2X1TS U6260 ( .A(n9765), .B(n7307), .Y(n7165) );
NAND2X1TS U6261 ( .A(n7170), .B(n7169), .Y(n7171) );
INVX2TS U6262 ( .A(n7168), .Y(n7170) );
OAI21X1TS U6263 ( .A0(n7160), .A1(n7173), .B0(n7159), .Y(n7167) );
AOI21X1TS U6264 ( .A0(n7208), .A1(n7158), .B0(n7157), .Y(n7159) );
INVX2TS U6265 ( .A(n9702), .Y(n9703) );
INVX2TS U6266 ( .A(n9696), .Y(n9697) );
ADDHX1TS U6267 ( .A(n9758), .B(n9757), .CO(n9759), .S(
DP_OP_344J35_128_4078_n43) );
NAND2X1TS U6268 ( .A(n7224), .B(n1066), .Y(n8470) );
OR2X1TS U6269 ( .A(n7224), .B(n1066), .Y(n1053) );
XNOR2X1TS U6270 ( .A(n7237), .B(n7236), .Y(n7242) );
NAND2X1TS U6271 ( .A(n7235), .B(n7234), .Y(n7236) );
INVX2TS U6272 ( .A(n7233), .Y(n7235) );
XNOR2X1TS U6273 ( .A(n7240), .B(n7239), .Y(n7241) );
NAND2X1TS U6274 ( .A(n1226), .B(n7238), .Y(n7240) );
NAND2X1TS U6275 ( .A(n7227), .B(n7226), .Y(n8473) );
AO21X1TS U6276 ( .A0(n1053), .A1(n8471), .B0(n7225), .Y(n1223) );
INVX2TS U6277 ( .A(n8470), .Y(n7225) );
NAND2X1TS U6278 ( .A(n7062), .B(n7230), .Y(n7063) );
INVX2TS U6279 ( .A(n7231), .Y(n7062) );
CLKAND2X2TS U6280 ( .A(n855), .B(n7064), .Y(n1230) );
NOR2X2TS U6281 ( .A(n9860), .B(n9861), .Y(n7611) );
NAND2X1TS U6282 ( .A(n9860), .B(n9861), .Y(n7612) );
CMPR42X1TS U6283 ( .A(DP_OP_344J35_128_4078_n123), .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[5]), .C(DP_OP_344J35_128_4078_n68), .D(DP_OP_344J35_128_4078_n149), .ICI(
DP_OP_344J35_128_4078_n69), .S(DP_OP_344J35_128_4078_n67), .ICO(
DP_OP_344J35_128_4078_n65), .CO(DP_OP_344J35_128_4078_n66) );
INVX2TS U6284 ( .A(n9729), .Y(DP_OP_344J35_128_4078_n123) );
NOR2X1TS U6285 ( .A(n9862), .B(n9863), .Y(n7606) );
NAND2X1TS U6286 ( .A(n9862), .B(n9863), .Y(n7607) );
CMPR42X1TS U6287 ( .A(DP_OP_344J35_128_4078_n124), .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[4]), .C(DP_OP_344J35_128_4078_n71), .D(DP_OP_344J35_128_4078_n150), .ICI(
DP_OP_344J35_128_4078_n72), .S(DP_OP_344J35_128_4078_n70), .ICO(
DP_OP_344J35_128_4078_n68), .CO(DP_OP_344J35_128_4078_n69) );
INVX2TS U6288 ( .A(n9730), .Y(DP_OP_344J35_128_4078_n124) );
NAND2X1TS U6289 ( .A(n9864), .B(n9865), .Y(n7585) );
CMPR42X1TS U6290 ( .A(DP_OP_344J35_128_4078_n125), .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[3]), .C(DP_OP_344J35_128_4078_n74), .D(n8718), .ICI(DP_OP_344J35_128_4078_n75),
.S(DP_OP_344J35_128_4078_n73), .ICO(DP_OP_344J35_128_4078_n71), .CO(
DP_OP_344J35_128_4078_n72) );
INVX2TS U6291 ( .A(n9731), .Y(DP_OP_344J35_128_4078_n125) );
NAND2X1TS U6292 ( .A(n1219), .B(n7388), .Y(n8724) );
NOR2X2TS U6293 ( .A(n1219), .B(n7388), .Y(n8726) );
NOR2X1TS U6294 ( .A(n9866), .B(n9804), .Y(n7602) );
NAND2X1TS U6295 ( .A(n9866), .B(n9804), .Y(n7603) );
ADDHX1TS U6296 ( .A(n7129), .B(n7128), .CO(n7134), .S(n9868) );
NOR2X1TS U6297 ( .A(n751), .B(n763), .Y(n7129) );
CMPR42X1TS U6298 ( .A(DP_OP_344J35_128_4078_n127), .B(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[1]), .C(DP_OP_344J35_128_4078_n80), .D(n8710), .ICI(DP_OP_344J35_128_4078_n81),
.S(DP_OP_344J35_128_4078_n79), .ICO(DP_OP_344J35_128_4078_n77), .CO(
DP_OP_344J35_128_4078_n78) );
INVX2TS U6299 ( .A(n9733), .Y(DP_OP_344J35_128_4078_n127) );
CLKXOR2X2TS U6300 ( .A(n5165), .B(n992), .Y(n993) );
NAND2X1TS U6301 ( .A(n5189), .B(n5162), .Y(n5164) );
AOI21X1TS U6302 ( .A0(n5193), .A1(n5162), .B0(n5161), .Y(n5163) );
ADDHXLTS U6303 ( .A(Op_MY[7]), .B(Op_MY[0]), .CO(n6401), .S(n6398) );
ADDHXLTS U6304 ( .A(n10387), .B(n10386), .CO(n10389), .S(
DP_OP_347J35_131_5122_n113) );
NAND2X4TS U6305 ( .A(n1035), .B(n2284), .Y(n2285) );
NAND2X1TS U6306 ( .A(n6224), .B(n6223), .Y(n6263) );
INVX2TS U6307 ( .A(n6237), .Y(n6273) );
XNOR2X1TS U6308 ( .A(n2962), .B(n2961), .Y(n6582) );
NAND2X1TS U6309 ( .A(n2960), .B(n2959), .Y(n2961) );
NAND2X1TS U6310 ( .A(n6286), .B(n6285), .Y(n6682) );
INVX2TS U6311 ( .A(n6691), .Y(n6284) );
OR2X1TS U6312 ( .A(n6286), .B(n6285), .Y(n1046) );
AO21XLTS U6313 ( .A0(n6352), .A1(n10317), .B0(n947), .Y(n6390) );
NOR2X1TS U6314 ( .A(n3712), .B(n3711), .Y(n4350) );
NAND2X1TS U6315 ( .A(n3712), .B(n3711), .Y(n4351) );
NAND2X1TS U6316 ( .A(n3709), .B(n3708), .Y(n4342) );
OR2X1TS U6317 ( .A(n3709), .B(n3708), .Y(n1138) );
XNOR2X1TS U6318 ( .A(n6279), .B(n6278), .Y(n6705) );
NAND2X1TS U6319 ( .A(n6277), .B(n6276), .Y(n6278) );
OAI21XLTS U6320 ( .A0(n6711), .A1(n6707), .B0(n6708), .Y(n6279) );
NAND2X1TS U6321 ( .A(n6705), .B(n6704), .Y(n6775) );
ADDFX2TS U6322 ( .A(n6623), .B(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_Q_middle[21]), .CI(n6622),
.CO(n6615), .S(n6804) );
NAND2X1TS U6323 ( .A(n1006), .B(n5303), .Y(n5304) );
NAND2X1TS U6324 ( .A(n3760), .B(n3759), .Y(n5295) );
INVX2TS U6325 ( .A(n5303), .Y(n5296) );
OR2X1TS U6326 ( .A(n3760), .B(n3759), .Y(n1086) );
INVX2TS U6327 ( .A(n6896), .Y(n6898) );
INVX2TS U6328 ( .A(n9736), .Y(n9026) );
AOI21X1TS U6329 ( .A0(n922), .A1(n4433), .B0(n3779), .Y(n4455) );
INVX2TS U6330 ( .A(n4432), .Y(n3779) );
NAND2X1TS U6331 ( .A(n3793), .B(n3792), .Y(n4452) );
NOR2X1TS U6332 ( .A(n3793), .B(n3792), .Y(n4451) );
NAND2X1TS U6333 ( .A(n6996), .B(n6995), .Y(n6997) );
NAND2X1TS U6334 ( .A(n3816), .B(n3815), .Y(n5386) );
OR2X1TS U6335 ( .A(n3816), .B(n3815), .Y(n920) );
OAI21X2TS U6336 ( .A0(n4455), .A1(n4451), .B0(n4452), .Y(n5387) );
XNOR2X2TS U6337 ( .A(n6671), .B(n6670), .Y(n7002) );
NAND2X1TS U6338 ( .A(n1043), .B(n6669), .Y(n6671) );
NAND2X1TS U6339 ( .A(n825), .B(n7007), .Y(n6894) );
AOI21X1TS U6340 ( .A0(n7015), .A1(n7006), .B0(n7009), .Y(n6895) );
CLKXOR2X2TS U6341 ( .A(n6679), .B(n6678), .Y(n7000) );
NAND2X1TS U6342 ( .A(n6677), .B(n6676), .Y(n6679) );
XOR2X1TS U6343 ( .A(n6887), .B(n6886), .Y(n7001) );
AOI21X1TS U6344 ( .A0(n7015), .A1(n6996), .B0(n6838), .Y(n6887) );
NAND2X1TS U6345 ( .A(n6885), .B(n6889), .Y(n6886) );
INVX2TS U6346 ( .A(n6995), .Y(n6838) );
NAND2X1TS U6347 ( .A(n1002), .B(n5342), .Y(n5580) );
NAND2X1TS U6348 ( .A(n1020), .B(n1010), .Y(n9078) );
XNOR2X2TS U6349 ( .A(n5616), .B(n5615), .Y(n5618) );
NAND2X1TS U6350 ( .A(n958), .B(n5614), .Y(n5616) );
CLKXOR2X2TS U6351 ( .A(n4522), .B(n4582), .Y(n5617) );
NAND2X1TS U6352 ( .A(n4518), .B(n4581), .Y(n4522) );
INVX2TS U6353 ( .A(n4583), .Y(n4518) );
NOR2XLTS U6354 ( .A(n10427), .B(n10402), .Y(n10392) );
NOR2XLTS U6355 ( .A(n10407), .B(n10426), .Y(n10391) );
XNOR2X1TS U6356 ( .A(n6569), .B(n6568), .Y(n6702) );
NAND2X1TS U6357 ( .A(n1068), .B(n6567), .Y(n6569) );
AOI21X1TS U6358 ( .A0(n832), .A1(n6767), .B0(n6766), .Y(n6768) );
INVX2TS U6359 ( .A(n6946), .Y(n6766) );
NAND2X1TS U6360 ( .A(n832), .B(n6953), .Y(n6769) );
XNOR2X2TS U6361 ( .A(n6692), .B(n6691), .Y(n6991) );
NAND2X1TS U6362 ( .A(n6690), .B(n6689), .Y(n6692) );
INVX2TS U6363 ( .A(n6925), .Y(n6927) );
NAND2X1TS U6364 ( .A(n6790), .B(n6789), .Y(n6926) );
OA21XLTS U6365 ( .A0(n6981), .A1(n6984), .B0(n6982), .Y(n1047) );
OR2X1TS U6366 ( .A(n9044), .B(n6749), .Y(n9043) );
XOR2X1TS U6367 ( .A(n6719), .B(n6718), .Y(n8555) );
NAND2X1TS U6368 ( .A(n6800), .B(n6799), .Y(n6917) );
NOR2X1TS U6369 ( .A(n6810), .B(n6809), .Y(n6904) );
NAND2X1TS U6370 ( .A(n6810), .B(n6809), .Y(n6905) );
AOI21X2TS U6371 ( .A0(n944), .A1(n985), .B0(n6808), .Y(n6907) );
INVX2TS U6372 ( .A(n6909), .Y(n6808) );
NAND2X1TS U6373 ( .A(n6555), .B(n6554), .Y(n6557) );
XNOR2X1TS U6374 ( .A(n6540), .B(n6539), .Y(n6727) );
NAND2X1TS U6375 ( .A(n831), .B(n6538), .Y(n6540) );
OR2X1TS U6376 ( .A(n6792), .B(n6791), .Y(n1040) );
NAND2X1TS U6377 ( .A(n6792), .B(n6791), .Y(n6922) );
OAI21X1TS U6378 ( .A0(n6925), .A1(n1047), .B0(n6926), .Y(n6923) );
XOR2X1TS U6379 ( .A(n6711), .B(n6710), .Y(n8552) );
NAND2X1TS U6380 ( .A(n6709), .B(n6708), .Y(n6710) );
OAI21X2TS U6381 ( .A0(n6904), .A1(n6907), .B0(n6905), .Y(n6902) );
XNOR2X2TS U6382 ( .A(n4434), .B(n4433), .Y(n9080) );
INVX2TS U6383 ( .A(n8498), .Y(n6800) );
NOR2X2TS U6384 ( .A(n6798), .B(n6795), .Y(n8495) );
INVX2TS U6385 ( .A(n8501), .Y(n6795) );
NOR2X2TS U6386 ( .A(n7854), .B(n7842), .Y(n8210) );
NAND2X1TS U6387 ( .A(n7854), .B(n7842), .Y(n8212) );
NAND2X1TS U6388 ( .A(n5594), .B(n5593), .Y(n8906) );
NAND2X1TS U6389 ( .A(n8268), .B(n8267), .Y(n8623) );
NOR2X2TS U6390 ( .A(n5605), .B(n5604), .Y(n8882) );
NAND2X1TS U6391 ( .A(n5613), .B(n5612), .Y(n8870) );
CLKXOR2X2TS U6392 ( .A(n6651), .B(n6650), .Y(n8501) );
NAND2X1TS U6393 ( .A(n6649), .B(n6648), .Y(n6650) );
INVX2TS U6394 ( .A(n7017), .Y(n6798) );
XOR2X1TS U6395 ( .A(n6643), .B(n6642), .Y(n7017) );
NAND2X1TS U6396 ( .A(n6641), .B(n6640), .Y(n6643) );
CLKXOR2X2TS U6397 ( .A(n6350), .B(n943), .Y(n1199) );
OAI21X1TS U6398 ( .A0(n6344), .A1(n6820), .B0(n6343), .Y(n6350) );
INVX2TS U6399 ( .A(n8770), .Y(n8772) );
NAND2X1TS U6400 ( .A(n7901), .B(n7848), .Y(n7593) );
ADDHX1TS U6401 ( .A(n7526), .B(n7525), .CO(n7531), .S(n7848) );
NOR2X1TS U6402 ( .A(n756), .B(n955), .Y(n7526) );
NOR2X1TS U6403 ( .A(n744), .B(n813), .Y(n7525) );
ADDFX2TS U6404 ( .A(n8931), .B(n8930), .CI(n8929), .CO(n8924), .S(n9180) );
NOR2X1TS U6405 ( .A(n7893), .B(n7889), .Y(n7588) );
NOR2X1TS U6406 ( .A(n10798), .B(n10795), .Y(n10784) );
NAND2X1TS U6407 ( .A(n7882), .B(n7894), .Y(n7582) );
OAI21X1TS U6408 ( .A0(n7588), .A1(n7591), .B0(n7589), .Y(n7583) );
OR2X1TS U6409 ( .A(n7882), .B(n7894), .Y(n1069) );
NOR2X1TS U6410 ( .A(n7915), .B(n7843), .Y(n7577) );
NAND2X1TS U6411 ( .A(n7915), .B(n7843), .Y(n7578) );
AOI21X2TS U6412 ( .A0(n1082), .A1(n5590), .B0(n5589), .Y(n8915) );
NAND2X1TS U6413 ( .A(n5592), .B(n5591), .Y(n8913) );
INVX2TS U6414 ( .A(n10650), .Y(n8911) );
NOR2X2TS U6415 ( .A(n5592), .B(n5591), .Y(n8912) );
INVX2TS U6416 ( .A(n8760), .Y(n6810) );
NOR2X2TS U6417 ( .A(n1192), .B(n7025), .Y(n8759) );
INVX2TS U6418 ( .A(n7033), .Y(n6805) );
NOR2X2TS U6419 ( .A(n6802), .B(n8490), .Y(n7030) );
CLKXOR2X2TS U6420 ( .A(n6614), .B(n6613), .Y(n1192) );
NAND2X1TS U6421 ( .A(n6612), .B(n6814), .Y(n6613) );
OAI21X1TS U6422 ( .A0(n6820), .A1(n6611), .B0(n6610), .Y(n6614) );
XNOR2X1TS U6423 ( .A(n6273), .B(n6272), .Y(n6776) );
NAND2X1TS U6424 ( .A(n1192), .B(n6807), .Y(n6909) );
AO21X1TS U6425 ( .A0(n945), .A1(n981), .B0(n6806), .Y(n985) );
INVX2TS U6426 ( .A(n6911), .Y(n6806) );
AOI21X1TS U6427 ( .A0(n834), .A1(n982), .B0(n6796), .Y(n6989) );
NOR2X1TS U6428 ( .A(n6788), .B(n6787), .Y(n6981) );
NAND2X1TS U6429 ( .A(n6788), .B(n6787), .Y(n6982) );
AOI21X1TS U6430 ( .A0(n845), .A1(n6979), .B0(n6786), .Y(n6984) );
INVX2TS U6431 ( .A(n6978), .Y(n6786) );
AOI21X1TS U6432 ( .A0(n6273), .A1(n6251), .B0(n6250), .Y(n6256) );
XOR2X1TS U6433 ( .A(n6566), .B(n1139), .Y(n6712) );
NAND2X1TS U6434 ( .A(n6565), .B(n6564), .Y(n6566) );
NAND2X1TS U6435 ( .A(n8270), .B(n8269), .Y(n8627) );
INVX2TS U6436 ( .A(n8623), .Y(n8625) );
OR2X1TS U6437 ( .A(n8268), .B(n8267), .Y(n1083) );
NAND2X1TS U6438 ( .A(n5602), .B(n5601), .Y(n8889) );
NAND2X1TS U6439 ( .A(n8238), .B(n8237), .Y(n8619) );
OR2X1TS U6440 ( .A(n8238), .B(n8237), .Y(n1088) );
NAND2X1TS U6441 ( .A(n913), .B(n8617), .Y(n7573) );
OR2X1TS U6442 ( .A(n7572), .B(n7571), .Y(n913) );
INVX2TS U6443 ( .A(n8509), .Y(n8768) );
CLKXOR2X2TS U6444 ( .A(n6824), .B(n6823), .Y(n1050) );
NAND2X1TS U6445 ( .A(n6818), .B(n6813), .Y(n6821) );
INVX2TS U6446 ( .A(n8767), .Y(n8762) );
INVX2TS U6447 ( .A(n7016), .Y(n6802) );
XOR2X1TS U6448 ( .A(n6820), .B(n6627), .Y(n7016) );
NAND2X1TS U6449 ( .A(n5550), .B(n5549), .Y(n5552) );
AOI21X2TS U6450 ( .A0(n840), .A1(n6961), .B0(n6761), .Y(n6955) );
NAND2X1TS U6451 ( .A(n840), .B(n1057), .Y(n6954) );
NAND2X1TS U6452 ( .A(n6560), .B(n6559), .Y(n6562) );
NOR2X2TS U6453 ( .A(n6763), .B(n6762), .Y(n6947) );
NAND2X1TS U6454 ( .A(n1092), .B(n7600), .Y(n7596) );
OAI21X1TS U6455 ( .A0(n8366), .A1(n8417), .B0(n8365), .Y(n8374) );
NOR2X2TS U6456 ( .A(n9108), .B(n9107), .Y(n9367) );
NAND2X1TS U6457 ( .A(n8392), .B(n8391), .Y(n8393) );
OAI21X1TS U6458 ( .A0(n8417), .A1(n8390), .B0(n8389), .Y(n8394) );
NAND2X1TS U6459 ( .A(n8397), .B(n8402), .Y(n8390) );
XNOR2X1TS U6460 ( .A(n8800), .B(n5112), .Y(n9106) );
NAND2X1TS U6461 ( .A(n8797), .B(n8808), .Y(n8798) );
NAND2X1TS U6462 ( .A(n8402), .B(n8401), .Y(n8403) );
OAI21X1TS U6463 ( .A0(n8417), .A1(n8400), .B0(n8399), .Y(n8404) );
INVX2TS U6464 ( .A(n8808), .Y(n5110) );
NAND2X1TS U6465 ( .A(n8408), .B(n8407), .Y(n8409) );
OAI21X1TS U6466 ( .A0(n8417), .A1(n8413), .B0(n8414), .Y(n8410) );
INVX2TS U6467 ( .A(n8815), .Y(n5084) );
NOR2X1TS U6468 ( .A(n8820), .B(n829), .Y(n8813) );
XOR2X1TS U6469 ( .A(n8417), .B(n8416), .Y(n9728) );
NAND2X1TS U6470 ( .A(n8415), .B(n8414), .Y(n8416) );
INVX2TS U6471 ( .A(n8413), .Y(n8415) );
NAND2X1TS U6472 ( .A(n5071), .B(n5070), .Y(n5072) );
NAND2X1TS U6473 ( .A(n8827), .B(n8825), .Y(n8820) );
MXI2X1TS U6474 ( .A(DP_OP_344J35_128_4078_n30), .B(DP_OP_344J35_128_4078_n29), .S0(DP_OP_344J35_128_4078_n35), .Y(n8418) );
NAND2X1TS U6475 ( .A(n8423), .B(n8422), .Y(n8424) );
OAI21X1TS U6476 ( .A0(n8429), .A1(n8426), .B0(n8427), .Y(n8425) );
INVX2TS U6477 ( .A(n8421), .Y(n8423) );
NOR2X1TS U6478 ( .A(n1056), .B(n1125), .Y(n8825) );
NAND2X1TS U6479 ( .A(n8428), .B(n8427), .Y(n8430) );
INVX2TS U6480 ( .A(n8426), .Y(n8428) );
NAND2X1TS U6481 ( .A(n4841), .B(n4840), .Y(n4842) );
INVX2TS U6482 ( .A(n4839), .Y(n4841) );
NAND2X1TS U6483 ( .A(n8433), .B(n8432), .Y(n8434) );
INVX2TS U6484 ( .A(n8431), .Y(n8433) );
INVX2TS U6485 ( .A(n10580), .Y(n8835) );
CLKXOR2X2TS U6486 ( .A(n4849), .B(n4848), .Y(n1125) );
NAND2X1TS U6487 ( .A(n8439), .B(n8438), .Y(n8440) );
OAI21X1TS U6488 ( .A0(n8446), .A1(n8442), .B0(n8443), .Y(n8441) );
INVX2TS U6489 ( .A(n8437), .Y(n8439) );
NAND2X1TS U6490 ( .A(n8444), .B(n8443), .Y(n8445) );
INVX2TS U6491 ( .A(n8442), .Y(n8444) );
NAND2X1TS U6492 ( .A(n8449), .B(n8448), .Y(n8450) );
INVX2TS U6493 ( .A(n8447), .Y(n8449) );
NOR2X2TS U6494 ( .A(n5621), .B(n5620), .Y(n8856) );
INVX2TS U6495 ( .A(n8863), .Y(n5619) );
INVX2TS U6496 ( .A(n10600), .Y(n8855) );
NAND2X1TS U6497 ( .A(n7392), .B(n8725), .Y(n7393) );
AOI21X1TS U6498 ( .A0(n7405), .A1(n8723), .B0(n8729), .Y(n7394) );
INVX2TS U6499 ( .A(n8722), .Y(n7392) );
NAND2X1TS U6500 ( .A(n8723), .B(n8728), .Y(n8731) );
NOR2X1TS U6501 ( .A(n8722), .B(n8726), .Y(n8728) );
AOI21X1TS U6502 ( .A0(n1227), .A1(n8745), .B0(n1228), .Y(n8751) );
AO21XLTS U6503 ( .A0(n8744), .A1(n8743), .B0(n8742), .Y(n1228) );
NAND2X1TS U6504 ( .A(n7399), .B(n7398), .Y(n7400) );
AOI21X1TS U6505 ( .A0(n7405), .A1(n7403), .B0(n7396), .Y(n7401) );
INVX2TS U6506 ( .A(n7397), .Y(n7399) );
NAND2X1TS U6507 ( .A(n7414), .B(n7413), .Y(n7415) );
INVX2TS U6508 ( .A(n7412), .Y(n7414) );
NAND2X1TS U6509 ( .A(n7403), .B(n7402), .Y(n7404) );
XNOR2X2TS U6510 ( .A(n7411), .B(n7410), .Y(n9744) );
NAND2X1TS U6511 ( .A(n7409), .B(n7408), .Y(n7410) );
INVX2TS U6512 ( .A(n7407), .Y(n7409) );
XNOR2X1TS U6513 ( .A(n7218), .B(n7217), .Y(n8465) );
XOR2X1TS U6514 ( .A(n7215), .B(n7214), .Y(n8466) );
NAND2X1TS U6515 ( .A(n1221), .B(n7216), .Y(n7218) );
NAND2X1TS U6516 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[22]), .B(
n9753), .Y(n8681) );
INVX2TS U6517 ( .A(n9746), .Y(n8718) );
NOR2X2TS U6518 ( .A(n8710), .B(n844), .Y(n8713) );
XNOR2X1TS U6519 ( .A(n7210), .B(n7183), .Y(n7635) );
NAND2X1TS U6520 ( .A(n7197), .B(n7195), .Y(n7183) );
XOR2X1TS U6521 ( .A(n7181), .B(n7180), .Y(n7419) );
XOR2X1TS U6522 ( .A(n7223), .B(n7222), .Y(n7417) );
XOR2X1TS U6523 ( .A(n7171), .B(n1225), .Y(n7421) );
INVX2TS U6524 ( .A(n9759), .Y(DP_OP_344J35_128_4078_n41) );
XNOR2X2TS U6525 ( .A(n8474), .B(n1223), .Y(n9748) );
NAND2X1TS U6526 ( .A(n1218), .B(n8473), .Y(n8474) );
XNOR2X2TS U6527 ( .A(n8472), .B(n8471), .Y(n9749) );
NAND2X1TS U6528 ( .A(n1053), .B(n8470), .Y(n8472) );
NAND2X1TS U6529 ( .A(n7242), .B(n7241), .Y(n8485) );
AOI21X1TS U6530 ( .A0(n1218), .A1(n1223), .B0(n7228), .Y(n8483) );
INVX2TS U6531 ( .A(n8473), .Y(n7228) );
NAND2X1TS U6532 ( .A(n7229), .B(n1230), .Y(n8481) );
INVX2TS U6533 ( .A(n9747), .Y(n8710) );
XOR2X1TS U6534 ( .A(n7615), .B(n7614), .Y(n8674) );
NAND2X1TS U6535 ( .A(n7613), .B(n7612), .Y(n7614) );
XOR2X1TS U6536 ( .A(n7610), .B(n7609), .Y(n8671) );
NAND2X1TS U6537 ( .A(n7608), .B(n7607), .Y(n7609) );
NAND2X1TS U6538 ( .A(n7389), .B(n8724), .Y(n7390) );
AOI21X1TS U6539 ( .A0(n7405), .A1(n7360), .B0(n7359), .Y(n7391) );
INVX2TS U6540 ( .A(n8726), .Y(n7389) );
XOR2X1TS U6541 ( .A(n7605), .B(n1098), .Y(n8665) );
NOR2XLTS U6542 ( .A(n10411), .B(n10393), .Y(DP_OP_347J35_131_5122_n173) );
XOR2X1TS U6543 ( .A(n6266), .B(n6265), .Y(n6782) );
AOI21X1TS U6544 ( .A0(n6273), .A1(n6271), .B0(n6261), .Y(n6266) );
XNOR2X2TS U6545 ( .A(n6684), .B(n6683), .Y(n6998) );
NAND2X1TS U6546 ( .A(n1046), .B(n6682), .Y(n6684) );
NAND2X1TS U6547 ( .A(n6795), .B(n6794), .Y(n6920) );
AO21X1TS U6548 ( .A0(n1040), .A1(n6923), .B0(n6793), .Y(n982) );
NAND2X1TS U6549 ( .A(n1165), .B(n6775), .Y(n6706) );
OR2X1TS U6550 ( .A(n6705), .B(n6704), .Y(n1165) );
NAND2X1TS U6551 ( .A(n6805), .B(n6804), .Y(n6911) );
NAND2X1TS U6552 ( .A(n6992), .B(n6991), .Y(n8535) );
AOI21X2TS U6553 ( .A0(n1187), .A1(n6994), .B0(n6993), .Y(n8534) );
INVX2TS U6554 ( .A(n8535), .Y(n6993) );
INVX2TS U6555 ( .A(n8536), .Y(n6994) );
XNOR2X2TS U6556 ( .A(n5388), .B(n5387), .Y(n9084) );
NAND2X1TS U6557 ( .A(n920), .B(n5386), .Y(n5388) );
AOI21X2TS U6558 ( .A0(n924), .A1(n9246), .B0(n9083), .Y(n9238) );
NOR2X2TS U6559 ( .A(n9085), .B(n9084), .Y(n9228) );
NOR2X1TS U6560 ( .A(n9228), .B(n9237), .Y(n9230) );
NOR2X2TS U6561 ( .A(n7003), .B(n7002), .Y(n8517) );
NAND2X2TS U6562 ( .A(n7001), .B(n7000), .Y(n8526) );
NOR2X2TS U6563 ( .A(n7001), .B(n7000), .Y(n8525) );
XNOR2X1TS U6564 ( .A(n5583), .B(n5582), .Y(n9014) );
NOR2X2TS U6565 ( .A(n9078), .B(n9268), .Y(n9251) );
NAND2X1TS U6566 ( .A(n1085), .B(n9236), .Y(n9091) );
NAND2X1TS U6567 ( .A(n924), .B(n923), .Y(n9237) );
OAI21XLTS U6568 ( .A0(n9091), .A1(n9238), .B0(n9090), .Y(n9092) );
AOI21X1TS U6569 ( .A0(n1085), .A1(n9089), .B0(n9088), .Y(n9090) );
OAI21X2TS U6570 ( .A0(n9078), .A1(n9267), .B0(n9077), .Y(n9252) );
AOI21X1TS U6571 ( .A0(n1020), .A1(n9260), .B0(n9076), .Y(n9077) );
XNOR2X2TS U6572 ( .A(n8457), .B(n8456), .Y(n9735) );
NAND2X1TS U6573 ( .A(n8455), .B(n8454), .Y(n8456) );
OAI21X1TS U6574 ( .A0(n8634), .A1(n8630), .B0(n8631), .Y(n8457) );
NAND2BXLTS U6575 ( .AN(Op_MY[0]), .B(Op_MX[5]), .Y(n6454) );
XOR2X1TS U6576 ( .A(n6473), .B(n6472), .Y(n10336) );
NAND2X1TS U6577 ( .A(n6758), .B(n6757), .Y(n6964) );
AOI21X1TS U6578 ( .A0(n6771), .A1(n6965), .B0(n6770), .Y(n6944) );
NOR2XLTS U6579 ( .A(n6769), .B(n6954), .Y(n6771) );
OAI21XLTS U6580 ( .A0(n6769), .A1(n6955), .B0(n6768), .Y(n6770) );
XOR2X1TS U6581 ( .A(n6919), .B(n1058), .Y(n8554) );
NAND2X1TS U6582 ( .A(n6918), .B(n6917), .Y(n6919) );
INVX2TS U6583 ( .A(n6916), .Y(n6918) );
NAND2X1TS U6584 ( .A(n9075), .B(n9074), .Y(n9258) );
OR2X1TS U6585 ( .A(n9075), .B(n9074), .Y(n1020) );
OR2X1TS U6586 ( .A(n6758), .B(n6757), .Y(n1057) );
NAND2X1TS U6587 ( .A(n6760), .B(n6759), .Y(n6960) );
NAND2X1TS U6588 ( .A(n9080), .B(n9079), .Y(n9255) );
XNOR2X2TS U6589 ( .A(n8499), .B(n6800), .Y(n10592) );
OAI21X1TS U6590 ( .A0(n8776), .A1(n8497), .B0(n8496), .Y(n8499) );
NAND2X1TS U6591 ( .A(n8761), .B(n8495), .Y(n8497) );
AOI21X1TS U6592 ( .A0(n9104), .A1(n9226), .B0(n9103), .Y(n9208) );
NOR2XLTS U6593 ( .A(n9211), .B(n9214), .Y(n9104) );
OAI21XLTS U6594 ( .A0(n9211), .A1(n9215), .B0(n9212), .Y(n9103) );
CLKXOR2X2TS U6595 ( .A(n8618), .B(n8617), .Y(n9740) );
NAND2X1TS U6596 ( .A(n8616), .B(n8615), .Y(n8618) );
XNOR2X1TS U6597 ( .A(n8896), .B(n8895), .Y(n9161) );
NAND2X1TS U6598 ( .A(n996), .B(n8894), .Y(n8896) );
XNOR2X2TS U6599 ( .A(n8626), .B(n8624), .Y(n9738) );
NAND2X1TS U6600 ( .A(n1083), .B(n8623), .Y(n8624) );
CLKXOR2X2TS U6601 ( .A(n8634), .B(n8633), .Y(n9736) );
NAND2X1TS U6602 ( .A(n8632), .B(n8631), .Y(n8633) );
XNOR2X2TS U6603 ( .A(n8504), .B(n6798), .Y(n10588) );
OAI21X1TS U6604 ( .A0(n8776), .A1(n8503), .B0(n8502), .Y(n8504) );
NAND2X1TS U6605 ( .A(n8761), .B(n8501), .Y(n8503) );
NOR2X2TS U6606 ( .A(n9319), .B(n9318), .Y(n10804) );
AOI21X1TS U6607 ( .A0(n1175), .A1(n9323), .B0(n9322), .Y(n10794) );
INVX2TS U6608 ( .A(n10812), .Y(n9323) );
INVX2TS U6609 ( .A(n10807), .Y(n9322) );
NOR2X2TS U6610 ( .A(n9325), .B(n9324), .Y(n10798) );
XOR2X1TS U6611 ( .A(n8922), .B(n8921), .Y(n9173) );
NAND2X1TS U6612 ( .A(n1082), .B(n8920), .Y(n8922) );
NAND2X1TS U6613 ( .A(n8761), .B(n8759), .Y(n7023) );
XNOR2X2TS U6614 ( .A(n7034), .B(n6805), .Y(n10569) );
NAND2X1TS U6615 ( .A(n8761), .B(n7030), .Y(n7032) );
XNOR2X2TS U6616 ( .A(n7029), .B(n1192), .Y(n10573) );
NAND2X1TS U6617 ( .A(n8761), .B(n7026), .Y(n7028) );
NAND2X1TS U6618 ( .A(n8513), .B(n8775), .Y(n8514) );
INVX2TS U6619 ( .A(n9224), .Y(n9221) );
NAND2X1TS U6620 ( .A(n9099), .B(n9098), .Y(n9220) );
OR2X1TS U6621 ( .A(n9099), .B(n9098), .Y(n926) );
XNOR2X1TS U6622 ( .A(n6910), .B(n985), .Y(n8545) );
NAND2X1TS U6623 ( .A(n944), .B(n6909), .Y(n6910) );
NAND2X1TS U6624 ( .A(n1090), .B(n9276), .Y(n9268) );
NAND2X1TS U6625 ( .A(n9073), .B(n9072), .Y(n9266) );
XOR2X1TS U6626 ( .A(n6985), .B(n6984), .Y(n8568) );
NAND2X1TS U6627 ( .A(n6983), .B(n6982), .Y(n6985) );
NAND2X1TS U6628 ( .A(n6765), .B(n6764), .Y(n6946) );
CLKXOR2X2TS U6629 ( .A(n8629), .B(n8628), .Y(n9737) );
NAND2X1TS U6630 ( .A(n1205), .B(n8627), .Y(n8628) );
AOI21X1TS U6631 ( .A0(n8626), .A1(n1083), .B0(n8625), .Y(n8629) );
XNOR2X1TS U6632 ( .A(n8878), .B(n8877), .Y(n9152) );
NAND2X1TS U6633 ( .A(n1142), .B(n8876), .Y(n8877) );
XNOR2X2TS U6634 ( .A(n8621), .B(n8620), .Y(n9739) );
NAND2X1TS U6635 ( .A(n1088), .B(n8619), .Y(n8621) );
XNOR2X2TS U6636 ( .A(n8511), .B(n8510), .Y(n10580) );
NAND2X1TS U6637 ( .A(n8768), .B(n8770), .Y(n8510) );
OAI21X1TS U6638 ( .A0(n8776), .A1(n8769), .B0(n8775), .Y(n8511) );
NAND2X1TS U6639 ( .A(n9102), .B(n9101), .Y(n9212) );
XNOR2X2TS U6640 ( .A(n8494), .B(n6802), .Y(n10564) );
OAI21X1TS U6641 ( .A0(n8776), .A1(n8493), .B0(n8492), .Y(n8494) );
NAND2X1TS U6642 ( .A(n8761), .B(n8491), .Y(n8493) );
NAND2X1TS U6643 ( .A(n6763), .B(n6762), .Y(n6952) );
INVX2TS U6644 ( .A(n6947), .Y(n6953) );
AOI21X1TS U6645 ( .A0(n974), .A1(n6754), .B0(n6753), .Y(n6755) );
CLKXOR2X2TS U6646 ( .A(n9376), .B(n960), .Y(n9378) );
NAND2X1TS U6647 ( .A(n9375), .B(n9374), .Y(n9376) );
INVX2TS U6648 ( .A(n9373), .Y(n9375) );
NOR2X1TS U6649 ( .A(n9106), .B(n9105), .Y(n9362) );
XNOR2X1TS U6650 ( .A(n8816), .B(n5084), .Y(n9119) );
NAND2X1TS U6651 ( .A(n8843), .B(n8842), .Y(n8844) );
INVX2TS U6652 ( .A(n10844), .Y(n10847) );
NAND2X1TS U6653 ( .A(n8750), .B(n8749), .Y(n8757) );
XOR2XLTS U6654 ( .A(n9770), .B(n9763), .Y(n8755) );
ADDHXLTS U6655 ( .A(n9743), .B(n8720), .CO(n8500), .S(n9407) );
AOI21X2TS U6656 ( .A0(n1216), .A1(n959), .B0(n8464), .Y(n8687) );
INVX2TS U6657 ( .A(n8681), .Y(n8464) );
NAND2X1TS U6658 ( .A(n1216), .B(n8681), .Y(n8682) );
XNOR2X1TS U6659 ( .A(n8719), .B(n8718), .Y(n9468) );
NAND2X1TS U6660 ( .A(n8712), .B(n8713), .Y(n8716) );
NAND2X1TS U6661 ( .A(n8714), .B(n8713), .Y(n8715) );
NAND2X1TS U6662 ( .A(n8462), .B(n9754), .Y(n8679) );
AO21X1TS U6663 ( .A0(n1214), .A1(n8677), .B0(n8461), .Y(n962) );
NAND2X1TS U6664 ( .A(n1214), .B(n8676), .Y(n8678) );
CLKXOR2X2TS U6665 ( .A(n8690), .B(n8693), .Y(n9442) );
NAND2X1TS U6666 ( .A(n8688), .B(n8691), .Y(n8690) );
NOR2X2TS U6667 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[26]), .B(
n9749), .Y(n8702) );
NAND2X1TS U6668 ( .A(n1048), .B(n8485), .Y(n8486) );
CLKXOR2X2TS U6669 ( .A(n8484), .B(n8483), .Y(n9747) );
NAND2X1TS U6670 ( .A(n8482), .B(n8481), .Y(n8484) );
INVX2TS U6671 ( .A(n8480), .Y(n8482) );
NOR2X1TS U6672 ( .A(n8692), .B(n8694), .Y(n8469) );
OAI21X1TS U6673 ( .A0(n8717), .A1(n8709), .B0(n8708), .Y(n8711) );
ADDHXLTS U6674 ( .A(n9702), .B(n8748), .CO(n8758), .S(n9405) );
NOR2X4TS U6675 ( .A(n798), .B(n9400), .Y(n9498) );
ADDHXLTS U6676 ( .A(n6462), .B(n6461), .CO(n6536), .S(n6543) );
NAND2X1TS U6677 ( .A(n8611), .B(n8610), .Y(n8612) );
OR2X1TS U6678 ( .A(n6752), .B(n6751), .Y(n974) );
ADDHX1TS U6679 ( .A(n10354), .B(n6494), .CO(n6493), .S(n8584) );
NAND2X1TS U6680 ( .A(n6785), .B(n6784), .Y(n6978) );
XNOR2X1TS U6681 ( .A(n6921), .B(n982), .Y(n8560) );
NAND2X1TS U6682 ( .A(n834), .B(n6920), .Y(n6921) );
NAND2X1TS U6683 ( .A(n9067), .B(n9066), .Y(n9275) );
NOR2X1TS U6684 ( .A(n9067), .B(n9066), .Y(n9272) );
OR2X1TS U6685 ( .A(n9069), .B(n9068), .Y(n1090) );
CLKXOR2X2TS U6686 ( .A(n8537), .B(n8536), .Y(n10678) );
NAND2X1TS U6687 ( .A(n1187), .B(n8535), .Y(n8537) );
NAND2X1TS U6688 ( .A(n9082), .B(n9081), .Y(n9245) );
OR2X1TS U6689 ( .A(n9082), .B(n9081), .Y(n924) );
NAND2X1TS U6690 ( .A(n9085), .B(n9084), .Y(n9235) );
OR2X1TS U6691 ( .A(n9087), .B(n9086), .Y(n1085) );
OAI21XLTS U6692 ( .A0(n9228), .A1(n9238), .B0(n9235), .Y(n9229) );
OAI21X1TS U6693 ( .A0(n8528), .A1(n8525), .B0(n8526), .Y(n8521) );
INVX2TS U6694 ( .A(n8517), .Y(n8519) );
NAND2X1TS U6695 ( .A(n9097), .B(n9096), .Y(n9224) );
OR2X1TS U6696 ( .A(n9097), .B(n9096), .Y(n1084) );
OAI21X2TS U6697 ( .A0(n9095), .A1(n9277), .B0(n9094), .Y(n9226) );
NAND2X1TS U6698 ( .A(n9093), .B(n9251), .Y(n9095) );
AOI21X1TS U6699 ( .A0(n9093), .A1(n9252), .B0(n9092), .Y(n9094) );
NOR2X1TS U6700 ( .A(n9091), .B(n9237), .Y(n9093) );
XNOR2X1TS U6701 ( .A(n8865), .B(n8864), .Y(n9146) );
NAND2X1TS U6702 ( .A(n1141), .B(n8863), .Y(n8864) );
NAND2X1TS U6703 ( .A(n1168), .B(n8612), .Y(n8613) );
OR2X1TS U6704 ( .A(n8611), .B(n8610), .Y(n1168) );
OAI21XLTS U6705 ( .A0(n9254), .A1(n9277), .B0(n9253), .Y(n9257) );
INVX2TS U6706 ( .A(n10858), .Y(n10817) );
NAND2X1TS U6707 ( .A(n9343), .B(n9737), .Y(n10709) );
NAND2X1TS U6708 ( .A(n6953), .B(n6952), .Y(n6959) );
AOI21X1TS U6709 ( .A0(n6957), .A1(n6965), .B0(n6956), .Y(n6958) );
INVX2TS U6710 ( .A(n10874), .Y(n10875) );
NAND2X1TS U6711 ( .A(n9360), .B(n9359), .Y(n10879) );
NAND2X1TS U6712 ( .A(n9355), .B(n9354), .Y(n10865) );
NAND2X1TS U6713 ( .A(n11065), .B(n11178), .Y(n11067) );
AOI21X2TS U6714 ( .A0(Sgf_normalized_result[3]), .A1(
Sgf_normalized_result[2]), .B0(Sgf_normalized_result[4]), .Y(n11065)
);
NAND2X1TS U6715 ( .A(n9350), .B(n9349), .Y(n10836) );
NAND2X1TS U6716 ( .A(n9468), .B(n9466), .Y(n9428) );
NAND2X1TS U6717 ( .A(n9458), .B(n9456), .Y(n9437) );
NOR2X1TS U6718 ( .A(n806), .B(n9437), .Y(n9440) );
NOR2X1TS U6719 ( .A(n1222), .B(n9474), .Y(n9445) );
NOR2X1TS U6720 ( .A(n8909), .B(n9483), .Y(n9450) );
NOR2X1TS U6721 ( .A(n1051), .B(n9471), .Y(n9456) );
INVX2TS U6722 ( .A(n9468), .Y(n8837) );
NAND2X1TS U6723 ( .A(n9452), .B(n9450), .Y(n9471) );
NAND2X1TS U6724 ( .A(n9442), .B(n9440), .Y(n9474) );
NAND2X1TS U6725 ( .A(n9447), .B(n9445), .Y(n9477) );
NAND2X1TS U6726 ( .A(n9463), .B(n9461), .Y(n9480) );
NAND2X1TS U6727 ( .A(n9486), .B(n9410), .Y(n9483) );
NAND2X1TS U6728 ( .A(n9425), .B(n9423), .Y(n9489) );
BUFX6TS U6729 ( .A(n10555), .Y(n10823) );
NAND4XLTS U6730 ( .A(n11037), .B(n11036), .C(n11035), .D(n11034), .Y(n11053)
);
NAND4XLTS U6731 ( .A(n11025), .B(n11024), .C(n11023), .D(n11022), .Y(n11031)
);
XNOR2X1TS U6732 ( .A(n6980), .B(n6979), .Y(n8571) );
NAND2X1TS U6733 ( .A(n845), .B(n6978), .Y(n6980) );
NAND2X1TS U6734 ( .A(n10631), .B(n10630), .Y(n10632) );
OAI21XLTS U6735 ( .A0(n9272), .A1(n9277), .B0(n9275), .Y(n9273) );
OAI21XLTS U6736 ( .A0(n9232), .A1(n9277), .B0(n9231), .Y(n9233) );
XOR2X1TS U6737 ( .A(n10761), .B(n10760), .Y(n10762) );
AOI21X1TS U6738 ( .A0(n10877), .A1(n10756), .B0(n10755), .Y(n10761) );
XOR2X1TS U6739 ( .A(n10741), .B(n10740), .Y(n10742) );
AOI21X1TS U6740 ( .A0(n10877), .A1(n10736), .B0(n10735), .Y(n10741) );
XOR2X1TS U6741 ( .A(n10721), .B(n10720), .Y(n10722) );
NAND2X1TS U6742 ( .A(n10719), .B(n10718), .Y(n10720) );
AOI21X1TS U6743 ( .A0(n10877), .A1(n10716), .B0(n10715), .Y(n10721) );
XOR2X1TS U6744 ( .A(n10691), .B(n10690), .Y(n10692) );
NAND2X1TS U6745 ( .A(n10689), .B(n10688), .Y(n10690) );
AOI21X1TS U6746 ( .A0(n10877), .A1(n10686), .B0(n10685), .Y(n10691) );
XNOR2X1TS U6747 ( .A(n10877), .B(n10818), .Y(n10819) );
NAND2X1TS U6748 ( .A(n10817), .B(n10861), .Y(n10818) );
XOR2X1TS U6749 ( .A(n10809), .B(n10808), .Y(n10810) );
AOI21X1TS U6750 ( .A0(n10877), .A1(n10806), .B0(n10805), .Y(n10809) );
XOR2X1TS U6751 ( .A(n10802), .B(n10801), .Y(n10803) );
AOI21X1TS U6752 ( .A0(n10877), .A1(n10797), .B0(n10796), .Y(n10802) );
XOR2X1TS U6753 ( .A(n10792), .B(n10791), .Y(n10793) );
AOI21X1TS U6754 ( .A0(n10877), .A1(n10789), .B0(n10788), .Y(n10792) );
AOI21X1TS U6755 ( .A0(n10877), .A1(n10776), .B0(n10775), .Y(n10781) );
XOR2X1TS U6756 ( .A(n10771), .B(n10770), .Y(n10772) );
AOI21X1TS U6757 ( .A0(n10877), .A1(n10768), .B0(n10767), .Y(n10771) );
XNOR2X1TS U6758 ( .A(n10577), .B(n10576), .Y(n10578) );
NAND2X1TS U6759 ( .A(n1171), .B(n10575), .Y(n10577) );
AO22XLTS U6760 ( .A0(n11141), .A1(n11091), .B0(n11139), .B1(Add_result[17]),
.Y(n562) );
AO22XLTS U6761 ( .A0(n11141), .A1(n11095), .B0(n11139), .B1(Add_result[19]),
.Y(n560) );
AO22XLTS U6762 ( .A0(n11141), .A1(n11099), .B0(n11139), .B1(Add_result[21]),
.Y(n558) );
AO22XLTS U6763 ( .A0(n11141), .A1(n11103), .B0(n11139), .B1(Add_result[23]),
.Y(n556) );
AO22XLTS U6764 ( .A0(n11162), .A1(n11107), .B0(n11139), .B1(Add_result[25]),
.Y(n554) );
AO22XLTS U6765 ( .A0(n11141), .A1(n11111), .B0(n11139), .B1(Add_result[27]),
.Y(n552) );
AO22XLTS U6766 ( .A0(n11160), .A1(n11115), .B0(n11139), .B1(Add_result[29]),
.Y(n550) );
AO22XLTS U6767 ( .A0(n11160), .A1(n11119), .B0(n11139), .B1(Add_result[31]),
.Y(n548) );
AO22XLTS U6768 ( .A0(n11162), .A1(n11123), .B0(n11139), .B1(Add_result[33]),
.Y(n546) );
AO22XLTS U6769 ( .A0(n11160), .A1(n11127), .B0(n11158), .B1(Add_result[35]),
.Y(n544) );
AO22XLTS U6770 ( .A0(n11162), .A1(n11131), .B0(n11158), .B1(Add_result[37]),
.Y(n542) );
AO22XLTS U6771 ( .A0(n11162), .A1(n11135), .B0(n11158), .B1(Add_result[39]),
.Y(n540) );
AO22XLTS U6772 ( .A0(n11141), .A1(n11140), .B0(n11139), .B1(Add_result[41]),
.Y(n538) );
AO22XLTS U6773 ( .A0(n11141), .A1(n11087), .B0(n11139), .B1(Add_result[15]),
.Y(n564) );
AO22XLTS U6774 ( .A0(n9512), .A1(Data_MX[63]), .B0(n10554), .B1(Op_MX[63]),
.Y(n645) );
XOR2X1TS U6775 ( .A(n10711), .B(n10710), .Y(n10712) );
NAND2X1TS U6776 ( .A(n1178), .B(n10709), .Y(n10710) );
AOI21X1TS U6777 ( .A0(n10877), .A1(n10708), .B0(n10707), .Y(n10711) );
XOR2X1TS U6778 ( .A(n10731), .B(n10730), .Y(n10732) );
NAND2X1TS U6779 ( .A(n1179), .B(n10729), .Y(n10730) );
XOR2X1TS U6780 ( .A(n10751), .B(n10750), .Y(n10752) );
AOI21X1TS U6781 ( .A0(n10877), .A1(n10748), .B0(n10747), .Y(n10751) );
XNOR2X1TS U6782 ( .A(n10821), .B(n1191), .Y(n10822) );
NAND2X1TS U6783 ( .A(n1172), .B(n10820), .Y(n10821) );
NAND2X1TS U6784 ( .A(n10486), .B(n10485), .Y(n10488) );
INVX2TS U6785 ( .A(n10484), .Y(n10486) );
NAND2X1TS U6786 ( .A(n1213), .B(n10474), .Y(n10476) );
XOR2X1TS U6787 ( .A(n10482), .B(n10481), .Y(n10483) );
NAND2X1TS U6788 ( .A(n10480), .B(n10479), .Y(n10482) );
INVX2TS U6789 ( .A(n10478), .Y(n10480) );
NAND2X1TS U6790 ( .A(n10470), .B(n10469), .Y(n10472) );
INVX2TS U6791 ( .A(n10468), .Y(n10470) );
XOR2X1TS U6792 ( .A(n10882), .B(n10881), .Y(n10883) );
NAND2X1TS U6793 ( .A(n10880), .B(n10879), .Y(n10881) );
AOI21X1TS U6794 ( .A0(n10877), .A1(n10876), .B0(n10875), .Y(n10882) );
XOR2X1TS U6795 ( .A(n10868), .B(n10867), .Y(n10869) );
NAND2X1TS U6796 ( .A(n10866), .B(n10865), .Y(n10867) );
AOI21X1TS U6797 ( .A0(n10877), .A1(n10863), .B0(n10862), .Y(n10868) );
XOR2X1TS U6798 ( .A(n10852), .B(n10851), .Y(n10853) );
AO22XLTS U6799 ( .A0(n11141), .A1(n11071), .B0(n11139), .B1(Add_result[7]),
.Y(n572) );
AO22XLTS U6800 ( .A0(n11141), .A1(n11066), .B0(n11139), .B1(Add_result[5]),
.Y(n574) );
XOR2X1TS U6801 ( .A(n10839), .B(n10838), .Y(n10840) );
NAND2X1TS U6802 ( .A(n10837), .B(n10836), .Y(n10838) );
AOI21X1TS U6803 ( .A0(n10877), .A1(n10834), .B0(n10833), .Y(n10839) );
XNOR2X1TS U6804 ( .A(n9435), .B(n8810), .Y(n9436) );
INVX2TS U6805 ( .A(n9494), .Y(n11173) );
MXI2X1TS U6806 ( .A(P_Sgf[84]), .B(n9404), .S0(n10823), .Y(n1041) );
XNOR2X1TS U6807 ( .A(n9411), .B(n1229), .Y(n9412) );
XNOR2X1TS U6808 ( .A(n9421), .B(n8818), .Y(n9422) );
XNOR2X1TS U6809 ( .A(n9426), .B(n8805), .Y(n9427) );
XNOR2X1TS U6810 ( .A(n9429), .B(n8834), .Y(n9430) );
XNOR2X1TS U6811 ( .A(n9432), .B(n8822), .Y(n9433) );
NOR2XLTS U6812 ( .A(n909), .B(n9431), .Y(n9432) );
NOR2XLTS U6813 ( .A(n909), .B(n9437), .Y(n9438) );
XNOR2X1TS U6814 ( .A(n9443), .B(n8879), .Y(n9444) );
NOR2XLTS U6815 ( .A(n909), .B(n9441), .Y(n9443) );
XNOR2X1TS U6816 ( .A(n9448), .B(n8866), .Y(n9449) );
XNOR2X1TS U6817 ( .A(n9454), .B(n9453), .Y(n9455) );
NOR2XLTS U6818 ( .A(n909), .B(n9451), .Y(n9454) );
XNOR2X1TS U6819 ( .A(n9459), .B(n8891), .Y(n9460) );
XNOR2X1TS U6820 ( .A(n9464), .B(n8853), .Y(n9465) );
XNOR2X1TS U6821 ( .A(n9469), .B(n8837), .Y(n9470) );
NOR2XLTS U6822 ( .A(n909), .B(n9467), .Y(n9469) );
XNOR2X1TS U6823 ( .A(n9472), .B(n1051), .Y(n9473) );
NOR2XLTS U6824 ( .A(n909), .B(n9474), .Y(n9475) );
XNOR2X1TS U6825 ( .A(n9478), .B(n807), .Y(n9479) );
NOR2XLTS U6826 ( .A(n909), .B(n9477), .Y(n9478) );
XNOR2X1TS U6827 ( .A(n9484), .B(n8909), .Y(n9485) );
NOR2XLTS U6828 ( .A(n909), .B(n9483), .Y(n9484) );
XNOR2X1TS U6829 ( .A(n9491), .B(n8801), .Y(n9492) );
NOR2XLTS U6830 ( .A(n909), .B(n9489), .Y(n9491) );
INVX2TS U6831 ( .A(n9496), .Y(n11174) );
XNOR2X1TS U6832 ( .A(n9502), .B(n9501), .Y(n9503) );
NAND2X1TS U6833 ( .A(n9500), .B(n9499), .Y(n9501) );
XOR2X1TS U6834 ( .A(n9508), .B(n9507), .Y(n9509) );
NAND2X1TS U6835 ( .A(n9506), .B(n9505), .Y(n9507) );
INVX2TS U6836 ( .A(n9504), .Y(n9506) );
AOI21X1TS U6837 ( .A0(Add_result[51]), .A1(n11139), .B0(n9511), .Y(n1231) );
NAND4XLTS U6838 ( .A(n11017), .B(n11016), .C(n11015), .D(n11014), .Y(n11033)
);
XOR2X1TS U6839 ( .A(n10701), .B(n10700), .Y(n10702) );
NAND2X1TS U6840 ( .A(n1177), .B(n10699), .Y(n10700) );
AOI21X1TS U6841 ( .A0(n10877), .A1(n10698), .B0(n10697), .Y(n10701) );
AO22XLTS U6842 ( .A0(n11141), .A1(n11075), .B0(n11139), .B1(n867), .Y(n570)
);
AO22XLTS U6843 ( .A0(n11141), .A1(n11079), .B0(n11139), .B1(n868), .Y(n568)
);
AO22XLTS U6844 ( .A0(n11141), .A1(n11083), .B0(n11139), .B1(n869), .Y(n566)
);
AO22XLTS U6845 ( .A0(n11162), .A1(n11145), .B0(n11069), .B1(n873), .Y(n536)
);
NOR2X1TS U6846 ( .A(n760), .B(n751), .Y(n8656) );
MXI2X1TS U6847 ( .A(P_Sgf[105]), .B(n9412), .S0(n10823), .Y(n776) );
MXI2X1TS U6848 ( .A(P_Sgf[92]), .B(n9476), .S0(n10823), .Y(n777) );
MXI2X1TS U6849 ( .A(P_Sgf[102]), .B(n9436), .S0(n10782), .Y(n778) );
MXI2X1TS U6850 ( .A(P_Sgf[103]), .B(n9427), .S0(n10782), .Y(n779) );
MXI2X1TS U6851 ( .A(P_Sgf[99]), .B(n9417), .S0(n10823), .Y(n780) );
MXI2X1TS U6852 ( .A(P_Sgf[101]), .B(n9422), .S0(n10823), .Y(n781) );
MXI2X1TS U6853 ( .A(P_Sgf[100]), .B(n9433), .S0(n10823), .Y(n782) );
MXI2X1TS U6854 ( .A(P_Sgf[87]), .B(n9455), .S0(n10823), .Y(n786) );
MXI2X1TS U6855 ( .A(P_Sgf[95]), .B(n9465), .S0(n10823), .Y(n788) );
MXI2X1TS U6856 ( .A(P_Sgf[88]), .B(n9473), .S0(n10823), .Y(n790) );
MXI2X1TS U6857 ( .A(P_Sgf[104]), .B(n9492), .S0(n10782), .Y(n791) );
MXI2X1TS U6858 ( .A(P_Sgf[98]), .B(n9430), .S0(n10823), .Y(n792) );
MXI2X1TS U6859 ( .A(P_Sgf[94]), .B(n9479), .S0(n10823), .Y(n793) );
MXI2X1TS U6860 ( .A(P_Sgf[96]), .B(n9482), .S0(n10823), .Y(n794) );
MXI2X1TS U6861 ( .A(P_Sgf[86]), .B(n9485), .S0(n10823), .Y(n795) );
MXI2X1TS U6862 ( .A(P_Sgf[85]), .B(n9488), .S0(n10823), .Y(n796) );
XOR2X1TS U6863 ( .A(n3051), .B(n753), .Y(n797) );
XOR2X1TS U6864 ( .A(n1508), .B(n1507), .Y(n3120) );
OR2X2TS U6865 ( .A(n5113), .B(n5112), .Y(n799) );
MXI2X1TS U6866 ( .A(P_Sgf[82]), .B(n9509), .S0(n10897), .Y(n800) );
MXI2X1TS U6867 ( .A(P_Sgf[83]), .B(n9503), .S0(n10823), .Y(n801) );
XOR2X1TS U6868 ( .A(n3253), .B(n3047), .Y(n803) );
XOR2X1TS U6869 ( .A(n3052), .B(n3201), .Y(n804) );
OA21X4TS U6870 ( .A0(n3090), .A1(n3089), .B0(n3088), .Y(n805) );
XNOR2X2TS U6871 ( .A(n8687), .B(n8686), .Y(n806) );
CLKXOR2X2TS U6872 ( .A(n8707), .B(n8706), .Y(n807) );
OA21X4TS U6873 ( .A0(n7671), .A1(n7681), .B0(n7670), .Y(n814) );
OR2X1TS U6874 ( .A(n4289), .B(n4288), .Y(n815) );
OR2X1TS U6875 ( .A(n5366), .B(n5365), .Y(n817) );
OR2X1TS U6876 ( .A(n4563), .B(n4537), .Y(n818) );
OR2X2TS U6877 ( .A(n5352), .B(n5351), .Y(n822) );
OR2X1TS U6878 ( .A(n9864), .B(n9865), .Y(n823) );
OR2X2TS U6879 ( .A(n1056), .B(n4871), .Y(n824) );
OR2X1TS U6880 ( .A(n2842), .B(n2841), .Y(n828) );
CLKXOR2X2TS U6881 ( .A(n5073), .B(n5072), .Y(n829) );
OR2X1TS U6882 ( .A(n6441), .B(n966), .Y(n830) );
OR2X1TS U6883 ( .A(n2847), .B(n2846), .Y(n831) );
OR2X2TS U6884 ( .A(n6765), .B(n6764), .Y(n832) );
OR2X1TS U6885 ( .A(n4330), .B(n4329), .Y(n833) );
OR2X1TS U6886 ( .A(n6795), .B(n6794), .Y(n834) );
OR2X1TS U6887 ( .A(n3630), .B(n3629), .Y(n835) );
CLKXOR2X4TS U6888 ( .A(n1036), .B(n2438), .Y(n839) );
OR2X2TS U6889 ( .A(n6760), .B(n6759), .Y(n840) );
CLKXOR2X2TS U6890 ( .A(n8487), .B(n8486), .Y(n844) );
OR2X1TS U6891 ( .A(n6785), .B(n6784), .Y(n845) );
OR2X1TS U6892 ( .A(n4912), .B(n4910), .Y(n850) );
INVX2TS U6893 ( .A(n9407), .Y(n8822) );
INVX2TS U6894 ( .A(n9420), .Y(n8818) );
OR2X1TS U6895 ( .A(n5636), .B(n735), .Y(n854) );
INVX2TS U6896 ( .A(n9415), .Y(n8830) );
NOR2X1TS U6897 ( .A(n847), .B(n1034), .Y(n8570) );
OR2X1TS U6898 ( .A(DP_OP_342J35_126_4270_n774), .B(n9877), .Y(n855) );
NOR2X1TS U6899 ( .A(n735), .B(n731), .Y(n6291) );
NOR2X2TS U6900 ( .A(n744), .B(n955), .Y(n9318) );
INVX2TS U6901 ( .A(n9410), .Y(n8923) );
INVX2TS U6902 ( .A(n9486), .Y(n8917) );
INVX2TS U6903 ( .A(n864), .Y(n867) );
INVX2TS U6904 ( .A(n865), .Y(n868) );
INVX2TS U6905 ( .A(n866), .Y(n869) );
OR2X4TS U6906 ( .A(FSM_selector_B[1]), .B(n11198), .Y(n10549) );
INVX2TS U6907 ( .A(n7489), .Y(n9652) );
INVX2TS U6908 ( .A(n7488), .Y(n9649) );
NAND2X1TS U6909 ( .A(Op_MY[18]), .B(Op_MY[45]), .Y(n3924) );
XNOR2X1TS U6910 ( .A(n3391), .B(n753), .Y(n3102) );
INVX2TS U6911 ( .A(n6118), .Y(n5929) );
NOR2X2TS U6912 ( .A(n988), .B(n1026), .Y(n6118) );
INVX2TS U6913 ( .A(n6746), .Y(n5950) );
NOR2X2TS U6914 ( .A(n5897), .B(n1034), .Y(n6746) );
NOR2X2TS U6915 ( .A(n988), .B(n853), .Y(n6120) );
XNOR2X2TS U6916 ( .A(n3481), .B(n3243), .Y(n3141) );
INVX2TS U6917 ( .A(n3243), .Y(n3425) );
NOR2X2TS U6918 ( .A(n11183), .B(n11086), .Y(n11088) );
NOR2X2TS U6919 ( .A(n11184), .B(n11090), .Y(n11092) );
NOR2X2TS U6920 ( .A(n11185), .B(n11094), .Y(n11096) );
NOR2X2TS U6921 ( .A(n11186), .B(n11098), .Y(n11100) );
NOR2X2TS U6922 ( .A(n11187), .B(n11102), .Y(n11104) );
NOR2X2TS U6923 ( .A(n11188), .B(n11106), .Y(n11108) );
NOR2X2TS U6924 ( .A(n11189), .B(n11110), .Y(n11112) );
NOR2X2TS U6925 ( .A(n11190), .B(n11114), .Y(n11116) );
NOR2X2TS U6926 ( .A(n11191), .B(n11118), .Y(n11120) );
NOR2X2TS U6927 ( .A(n11192), .B(n11122), .Y(n11124) );
NOR2X2TS U6928 ( .A(n11193), .B(n11126), .Y(n11128) );
NOR2X2TS U6929 ( .A(n11194), .B(n11130), .Y(n11132) );
XNOR2X1TS U6930 ( .A(n10815), .B(n10814), .Y(n10816) );
NOR4X1TS U6931 ( .A(Op_MX[20]), .B(Op_MX[18]), .C(Op_MX[42]), .D(Op_MX[16]),
.Y(n11042) );
NOR4X1TS U6932 ( .A(Op_MY[45]), .B(Op_MY[44]), .C(Op_MY[43]), .D(Op_MY[42]),
.Y(n11026) );
NOR4X1TS U6933 ( .A(Op_MY[38]), .B(Op_MY[30]), .C(Op_MY[29]), .D(Op_MY[28]),
.Y(n11027) );
NOR4X1TS U6934 ( .A(Op_MX[12]), .B(Op_MX[11]), .C(Op_MX[10]), .D(Op_MX[27]),
.Y(n11039) );
NOR4X1TS U6935 ( .A(Op_MY[37]), .B(Op_MY[36]), .C(Op_MY[35]), .D(Op_MY[34]),
.Y(n11028) );
NOR4X1TS U6936 ( .A(Op_MX[14]), .B(Op_MX[3]), .C(Op_MX[1]), .D(Op_MX[39]),
.Y(n11041) );
NOR4X1TS U6937 ( .A(Op_MY[7]), .B(Op_MY[33]), .C(Op_MY[32]), .D(Op_MY[31]),
.Y(n11021) );
NOR4X1TS U6938 ( .A(Op_MY[20]), .B(Op_MY[40]), .C(Op_MY[39]), .D(Op_MY[27]),
.Y(n11029) );
NOR4X1TS U6939 ( .A(Op_MX[24]), .B(Op_MX[22]), .C(Op_MX[43]), .D(Op_MX[41]),
.Y(n11034) );
NOR4X1TS U6940 ( .A(Op_MY[25]), .B(Op_MY[24]), .C(Op_MY[23]), .D(Op_MY[21]),
.Y(n11023) );
NOR4X1TS U6941 ( .A(Op_MY[19]), .B(Op_MY[18]), .C(Op_MY[17]), .D(Op_MY[16]),
.Y(n11024) );
NOR4X1TS U6942 ( .A(Op_MY[26]), .B(Op_MY[15]), .C(Op_MY[14]), .D(Op_MY[41]),
.Y(n11025) );
NOR2X2TS U6943 ( .A(n847), .B(n769), .Y(n6745) );
NOR2X2TS U6944 ( .A(n988), .B(DP_OP_346J35_130_4270_n836), .Y(n6115) );
NOR2X2TS U6945 ( .A(n5897), .B(n769), .Y(n6738) );
INVX2TS U6946 ( .A(n8570), .Y(n6976) );
INVX2TS U6947 ( .A(DP_OP_345J35_129_3436_n5), .Y(n1242) );
AFCSHCINX2TS U6948 ( .CI1N(DP_OP_345J35_129_3436_n6), .B(
DP_OP_345J35_129_3436_n34), .A(DP_OP_345J35_129_3436_n33), .CI0N(
DP_OP_345J35_129_3436_n7), .CS(DP_OP_345J35_129_3436_n8), .CO1(
DP_OP_345J35_129_3436_n4), .CO0(DP_OP_345J35_129_3436_n5), .S(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_S_B[16])
);
INVX2TS U6949 ( .A(DP_OP_338J35_122_4684_n5), .Y(n1235) );
AFCSHCINX2TS U6950 ( .CI1N(DP_OP_338J35_122_4684_n6), .B(
DP_OP_338J35_122_4684_n34), .A(DP_OP_338J35_122_4684_n33), .CI0N(
DP_OP_338J35_122_4684_n7), .CS(DP_OP_338J35_122_4684_n8), .CO1(
DP_OP_338J35_122_4684_n4), .CO0(DP_OP_338J35_122_4684_n5), .S(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_middle_RECURSIVE_ODD1_S_B[16]) );
OR2X1TS U6951 ( .A(n6211), .B(n6210), .Y(n1067) );
NOR2X2TS U6952 ( .A(n746), .B(n769), .Y(n6210) );
NAND2X1TS U6953 ( .A(n916), .B(n1335), .Y(n1318) );
NAND2X1TS U6954 ( .A(n1332), .B(n916), .Y(n1339) );
AOI21X1TS U6955 ( .A0(n916), .A1(n1337), .B0(n1336), .Y(n1338) );
OAI21X1TS U6956 ( .A0(n9816), .A1(n9823), .B0(n9817), .Y(n7311) );
NAND2X1TS U6957 ( .A(n9818), .B(n9817), .Y(n9819) );
NAND2X1TS U6958 ( .A(Op_MY[51]), .B(Op_MY[44]), .Y(n9817) );
INVX2TS U6959 ( .A(n5638), .Y(n5632) );
NAND2X1TS U6960 ( .A(Op_MY[26]), .B(Op_MY[19]), .Y(n5638) );
INVX2TS U6961 ( .A(n5690), .Y(n6059) );
INVX2TS U6962 ( .A(n5658), .Y(n5978) );
OAI22X1TS U6963 ( .A0(n7317), .A1(n7381), .B0(n905), .B1(Op_MX[50]), .Y(
n7347) );
OAI22X1TS U6964 ( .A0(n7381), .A1(Op_MX[50]), .B0(n905), .B1(
DP_OP_342J35_126_4270_n852), .Y(n7379) );
XOR2X1TS U6965 ( .A(Op_MX[50]), .B(Op_MX[49]), .Y(n7056) );
ADDHX1TS U6966 ( .A(n9022), .B(n9021), .CO(n9015), .S(n9086) );
XNOR2X2TS U6967 ( .A(n5280), .B(n5279), .Y(n9021) );
ADDHX1TS U6968 ( .A(n6467), .B(n6466), .CO(n6544), .S(n10557) );
NAND2X1TS U6969 ( .A(n1013), .B(n2267), .Y(n2268) );
AOI21X2TS U6970 ( .A0(n1013), .A1(n2207), .B0(n2206), .Y(n2413) );
OAI22X1TS U6971 ( .A0(n8754), .A1(Op_MY[47]), .B0(n8753), .B1(Op_MY[48]),
.Y(n7295) );
NOR2BX1TS U6972 ( .AN(Op_MY[47]), .B(n8753), .Y(n7271) );
NOR2BX2TS U6973 ( .AN(Op_MY[47]), .B(n728), .Y(n7226) );
NOR2BX2TS U6974 ( .AN(Op_MY[47]), .B(n905), .Y(n9876) );
NAND2X1TS U6975 ( .A(Op_MY[47]), .B(Op_MY[40]), .Y(n7045) );
INVX2TS U6976 ( .A(n861), .Y(n870) );
INVX2TS U6977 ( .A(n862), .Y(n871) );
INVX2TS U6978 ( .A(n863), .Y(n872) );
INVX2TS U6979 ( .A(n5636), .Y(n5639) );
NOR2X1TS U6980 ( .A(Op_MY[26]), .B(Op_MY[19]), .Y(n5636) );
NOR3XLTS U6981 ( .A(Op_MY[13]), .B(Op_MY[22]), .C(Op_MY[53]), .Y(n11022) );
INVX2TS U6982 ( .A(n857), .Y(n873) );
INVX2TS U6983 ( .A(n858), .Y(n874) );
INVX2TS U6984 ( .A(n859), .Y(n875) );
INVX2TS U6985 ( .A(n860), .Y(n876) );
NOR4X1TS U6986 ( .A(Op_MY[50]), .B(Op_MY[51]), .C(Op_MY[52]), .D(Op_MY[61]),
.Y(n11016) );
NOR2X2TS U6987 ( .A(n11204), .B(n11161), .Y(n9510) );
NOR3XLTS U6988 ( .A(Op_MX[33]), .B(Op_MX[53]), .C(Op_MX[52]), .Y(n11046) );
INVX3TS U6989 ( .A(n804), .Y(n877) );
INVX3TS U6990 ( .A(n797), .Y(n878) );
NOR4X1TS U6991 ( .A(Op_MX[19]), .B(Op_MX[17]), .C(Op_MX[48]), .D(Op_MX[62]),
.Y(n11047) );
NOR4X1TS U6992 ( .A(Op_MX[61]), .B(Op_MX[60]), .C(Op_MX[59]), .D(Op_MX[58]),
.Y(n11048) );
NAND2X1TS U6993 ( .A(n4482), .B(n4481), .Y(n4553) );
ADDHX1TS U6994 ( .A(Op_MY[26]), .B(n4549), .CO(n4550), .S(n4481) );
INVX2TS U6995 ( .A(n5644), .Y(n5646) );
NOR2X1TS U6996 ( .A(Op_MY[25]), .B(Op_MY[18]), .Y(n5644) );
INVX2TS U6997 ( .A(n3943), .Y(n3945) );
NOR2X4TS U6998 ( .A(Op_MY[39]), .B(n7434), .Y(n9633) );
INVX3TS U6999 ( .A(n803), .Y(n879) );
INVX4TS U7000 ( .A(n755), .Y(n880) );
NOR2X2TS U7001 ( .A(Op_MX[34]), .B(Op_MX[7]), .Y(n1551) );
NAND2X1TS U7002 ( .A(n1446), .B(n1524), .Y(n1447) );
OAI21X1TS U7003 ( .A0(n1526), .A1(n1525), .B0(n1524), .Y(n1527) );
NAND2X1TS U7004 ( .A(Op_MY[40]), .B(Op_MY[13]), .Y(n1524) );
OAI32X1TS U7005 ( .A0(n9618), .A1(n7487), .A2(n9625), .B0(n9623), .B1(n9618),
.Y(n9570) );
NOR4X1TS U7006 ( .A(Op_MX[46]), .B(Op_MX[31]), .C(Op_MX[29]), .D(Op_MX[44]),
.Y(n11043) );
NOR4X1TS U7007 ( .A(Op_MX[26]), .B(Op_MX[51]), .C(Op_MX[49]), .D(Op_MX[28]),
.Y(n11035) );
NOR2X2TS U7008 ( .A(Op_MX[38]), .B(Op_MX[11]), .Y(n1596) );
NAND2X1TS U7009 ( .A(Op_MX[38]), .B(Op_MX[11]), .Y(n1597) );
NOR4X1TS U7010 ( .A(Op_MX[38]), .B(Op_MX[37]), .C(Op_MX[36]), .D(Op_MX[35]),
.Y(n11044) );
NOR4X1TS U7011 ( .A(Op_MX[13]), .B(Op_MX[0]), .C(Op_MX[47]), .D(Op_MX[40]),
.Y(n11038) );
NOR4X1TS U7012 ( .A(Op_MY[46]), .B(Op_MY[47]), .C(Op_MY[48]), .D(Op_MY[49]),
.Y(n11017) );
NOR4X1TS U7013 ( .A(Op_MX[25]), .B(Op_MX[21]), .C(Op_MX[50]), .D(Op_MX[32]),
.Y(n11036) );
NAND2X1TS U7014 ( .A(Op_MX[30]), .B(Op_MX[3]), .Y(n1576) );
NOR4X1TS U7015 ( .A(Op_MX[23]), .B(n883), .C(n881), .D(Op_MX[30]), .Y(n11037) );
NOR2X2TS U7016 ( .A(Op_MX[41]), .B(Op_MX[14]), .Y(n3935) );
NAND2X1TS U7017 ( .A(Op_MY[37]), .B(Op_MY[30]), .Y(n7695) );
NAND2X1TS U7018 ( .A(Op_MX[20]), .B(Op_MX[6]), .Y(n2479) );
NOR2X1TS U7019 ( .A(Op_MX[47]), .B(Op_MX[20]), .Y(n4020) );
NAND2X1TS U7020 ( .A(Op_MX[17]), .B(Op_MX[3]), .Y(n2396) );
XOR2X1TS U7021 ( .A(Op_MX[11]), .B(Op_MX[12]), .Y(n6351) );
OR2X2TS U7022 ( .A(Op_MY[19]), .B(Op_MY[5]), .Y(n1022) );
XNOR2X2TS U7023 ( .A(Op_MY[49]), .B(Op_MX[48]), .Y(n7055) );
NAND2X1TS U7024 ( .A(Op_MY[49]), .B(Op_MY[42]), .Y(n7308) );
AOI32X1TS U7025 ( .A0(n11061), .A1(n11060), .A2(n11059), .B0(n11207), .B1(
n11058), .Y(n580) );
NOR4X1TS U7026 ( .A(P_Sgf[19]), .B(P_Sgf[17]), .C(P_Sgf[18]), .D(P_Sgf[16]),
.Y(n10432) );
NOR4X1TS U7027 ( .A(Op_MX[9]), .B(Op_MX[8]), .C(Op_MX[7]), .D(Op_MX[5]), .Y(
n11040) );
AOI21X1TS U7028 ( .A0(n10877), .A1(n10728), .B0(n10727), .Y(n10731) );
NOR2X2TS U7029 ( .A(Op_MX[43]), .B(Op_MX[16]), .Y(n3955) );
BUFX8TS U7030 ( .A(n754), .Y(n11226) );
NOR2X2TS U7031 ( .A(Op_MX[19]), .B(Op_MX[46]), .Y(n4015) );
OAI21X1TS U7032 ( .A0(n5196), .A1(n5195), .B0(n5194), .Y(n5197) );
OAI21X1TS U7033 ( .A0(n5196), .A1(n5164), .B0(n5163), .Y(n5165) );
OAI21X1TS U7034 ( .A0(n5196), .A1(n5139), .B0(n5138), .Y(n5141) );
OAI21X1TS U7035 ( .A0(n5196), .A1(n4995), .B0(n4994), .Y(n4997) );
OAI21X1TS U7036 ( .A0(n5196), .A1(n5091), .B0(n5090), .Y(n5094) );
OAI21X1TS U7037 ( .A0(n5196), .A1(n5104), .B0(n5103), .Y(n5109) );
INVX2TS U7038 ( .A(n6125), .Y(n5868) );
NOR2X2TS U7039 ( .A(n988), .B(n1109), .Y(n6125) );
NOR2X1TS U7040 ( .A(n6209), .B(n6208), .Y(n6729) );
INVX2TS U7041 ( .A(n6209), .Y(n5904) );
NOR2X2TS U7042 ( .A(n746), .B(n1034), .Y(n6209) );
NAND2X1TS U7043 ( .A(n2299), .B(n2298), .Y(n2301) );
NAND2X1TS U7044 ( .A(n6337), .B(n6336), .Y(n6815) );
NAND2X1TS U7045 ( .A(n1030), .B(n2358), .Y(n2360) );
INVX2TS U7046 ( .A(n2358), .Y(n2292) );
NOR2X1TS U7047 ( .A(Op_MY[23]), .B(Op_MY[16]), .Y(n5675) );
NAND2X1TS U7048 ( .A(n896), .B(n897), .Y(n1964) );
NAND2X1TS U7049 ( .A(n884), .B(n898), .Y(n1775) );
INVX2TS U7050 ( .A(n1772), .Y(n885) );
NAND2X1TS U7051 ( .A(n885), .B(n892), .Y(n886) );
NAND2X1TS U7052 ( .A(n1034), .B(n893), .Y(n887) );
NAND2X1TS U7053 ( .A(n1034), .B(n894), .Y(n888) );
NAND2X1TS U7054 ( .A(n1771), .B(n895), .Y(n889) );
NAND2X1TS U7055 ( .A(n4060), .B(n885), .Y(n890) );
NAND2X1TS U7056 ( .A(n4060), .B(n1034), .Y(n891) );
NAND2X1TS U7057 ( .A(n885), .B(n1034), .Y(n884) );
INVX2TS U7058 ( .A(n4060), .Y(n1771) );
OAI22X1TS U7059 ( .A0(n3378), .A1(n899), .B0(n3121), .B1(n3390), .Y(n3351)
);
OAI22X1TS U7060 ( .A0(n3036), .A1(n899), .B0(n3029), .B1(n3390), .Y(n3033)
);
OAI22X1TS U7061 ( .A0(n3029), .A1(n899), .B0(n3390), .B1(n3028), .Y(n3190)
);
XNOR2X1TS U7062 ( .A(n1495), .B(n1494), .Y(n3396) );
NAND2X1TS U7063 ( .A(n900), .B(n1532), .Y(n1789) );
OAI21X1TS U7064 ( .A0(n2284), .A1(n2275), .B0(n2280), .Y(n2278) );
INVX2TS U7065 ( .A(n2275), .Y(n2281) );
NAND2X1TS U7066 ( .A(n8763), .B(n8491), .Y(n8492) );
NAND2X1TS U7067 ( .A(n8763), .B(n8495), .Y(n8496) );
NAND2X1TS U7068 ( .A(n8763), .B(n8501), .Y(n8502) );
OAI211XLTS U7069 ( .A0(Sgf_normalized_result[46]), .A1(n11150), .B0(n11162),
.C0(n11152), .Y(n11151) );
OAI211XLTS U7070 ( .A0(Sgf_normalized_result[44]), .A1(n11146), .B0(n11162),
.C0(n11148), .Y(n11147) );
OAI211XLTS U7071 ( .A0(Sgf_normalized_result[42]), .A1(n11142), .B0(n11162),
.C0(n11144), .Y(n11143) );
OAI211XLTS U7072 ( .A0(Sgf_normalized_result[40]), .A1(n11136), .B0(n11162),
.C0(n11138), .Y(n11137) );
OAI211XLTS U7073 ( .A0(Sgf_normalized_result[36]), .A1(n11128), .B0(n11160),
.C0(n11130), .Y(n11129) );
NAND2X4TS U7074 ( .A(n901), .B(n902), .Y(n6083) );
INVX2TS U7075 ( .A(n5640), .Y(n903) );
NAND2X1TS U7076 ( .A(n775), .B(n903), .Y(n901) );
NAND2X1TS U7077 ( .A(n775), .B(n854), .Y(n902) );
OAI21X2TS U7078 ( .A0(n5647), .A1(n5644), .B0(n5645), .Y(n5640) );
XNOR2X1TS U7079 ( .A(n1457), .B(n1456), .Y(n3341) );
NAND2X1TS U7080 ( .A(n904), .B(n900), .Y(n3058) );
NOR2X2TS U7081 ( .A(n904), .B(n900), .Y(n3059) );
OAI22X1TS U7082 ( .A0(n9843), .A1(n9829), .B0(n917), .B1(n881), .Y(
DP_OP_342J35_126_4270_n300) );
NOR2X1TS U7083 ( .A(n917), .B(n9835), .Y(DP_OP_342J35_126_4270_n326) );
OAI22X1TS U7084 ( .A0(n9843), .A1(n9833), .B0(n917), .B1(n9834), .Y(
DP_OP_342J35_126_4270_n318) );
NOR2X1TS U7085 ( .A(n917), .B(n9846), .Y(DP_OP_342J35_126_4270_n344) );
OAI22X1TS U7086 ( .A0(n9843), .A1(n9835), .B0(n917), .B1(n9836), .Y(
DP_OP_342J35_126_4270_n327) );
OAI22X1TS U7087 ( .A0(n9843), .A1(n9839), .B0(n917), .B1(n9842), .Y(
DP_OP_342J35_126_4270_n336) );
OAI22X1TS U7088 ( .A0(n9843), .A1(n9846), .B0(n917), .B1(n9848), .Y(
DP_OP_342J35_126_4270_n345) );
XOR2X1TS U7089 ( .A(Op_MX[49]), .B(Op_MX[48]), .Y(n7380) );
INVX4TS U7090 ( .A(n7380), .Y(n905) );
NOR2X2TS U7091 ( .A(n2513), .B(n2545), .Y(n2345) );
NOR2X2TS U7092 ( .A(n2513), .B(n2509), .Y(n2347) );
NOR2X1TS U7093 ( .A(Op_MX[21]), .B(Op_MX[7]), .Y(n906) );
BUFX4TS U7094 ( .A(n1149), .Y(n907) );
OAI22X1TS U7095 ( .A0(n4672), .A1(n4629), .B0(n907), .B1(n4630), .Y(n4172)
);
XOR2X1TS U7096 ( .A(n4123), .B(n4132), .Y(n1149) );
NOR2X2TS U7097 ( .A(Op_MY[50]), .B(Op_MY[23]), .Y(n1323) );
XNOR2X1TS U7098 ( .A(n3374), .B(n753), .Y(n3040) );
XNOR2X1TS U7099 ( .A(n3192), .B(n753), .Y(n3036) );
NOR2X2TS U7100 ( .A(Op_MY[18]), .B(Op_MY[45]), .Y(n3923) );
NAND2X1TS U7101 ( .A(n752), .B(n1770), .Y(n1686) );
INVX2TS U7102 ( .A(n3253), .Y(n3432) );
OR2X1TS U7103 ( .A(n3253), .B(n3243), .Y(n1151) );
NAND2X1TS U7104 ( .A(n3253), .B(n3243), .Y(n3084) );
NOR2X1TS U7105 ( .A(n760), .B(n749), .Y(n7128) );
NAND2X1TS U7106 ( .A(n908), .B(n1769), .Y(n1608) );
NOR2X1TS U7107 ( .A(n908), .B(n1769), .Y(n1607) );
XNOR2X1TS U7108 ( .A(n3500), .B(n908), .Y(n3342) );
INVX2TS U7109 ( .A(n3201), .Y(n3345) );
OR2X1TS U7110 ( .A(n3201), .B(n753), .Y(n1137) );
NAND2X1TS U7111 ( .A(n3201), .B(n753), .Y(n3075) );
XOR2X1TS U7112 ( .A(n909), .B(n8923), .Y(n9404) );
NOR4X1TS U7113 ( .A(Op_MX[6]), .B(Op_MX[4]), .C(Op_MX[2]), .D(Op_MX[34]),
.Y(n11045) );
NAND2X1TS U7114 ( .A(Op_MY[34]), .B(Op_MY[7]), .Y(n1537) );
NAND2X2TS U7115 ( .A(Op_MX[19]), .B(Op_MX[5]), .Y(n2478) );
ADDHX1TS U7116 ( .A(Op_MY[8]), .B(Op_MY[22]), .CO(n2283), .S(n2286) );
NAND2X1TS U7117 ( .A(Op_MY[49]), .B(Op_MY[22]), .Y(n1313) );
NAND2X1TS U7118 ( .A(Op_MY[17]), .B(Op_MY[44]), .Y(n3944) );
ADDHXLTS U7119 ( .A(Op_MX[16]), .B(Op_MX[23]), .CO(n5650), .S(n5643) );
ADDHXLTS U7120 ( .A(Op_MX[26]), .B(Op_MX[19]), .CO(n5692), .S(n5690) );
ADDHXLTS U7121 ( .A(Op_MX[24]), .B(Op_MX[17]), .CO(n5659), .S(n5658) );
ADDHX1TS U7122 ( .A(Op_MY[48]), .B(Op_MY[21]), .CO(n4127), .S(n4111) );
INVX2TS U7123 ( .A(n1607), .Y(n1609) );
NOR2X2TS U7124 ( .A(Op_MY[37]), .B(Op_MY[30]), .Y(n7694) );
NAND2X1TS U7125 ( .A(Op_MY[37]), .B(Op_MY[10]), .Y(n1469) );
INVX2TS U7126 ( .A(n5612), .Y(n4409) );
NAND2X1TS U7127 ( .A(n1207), .B(n10850), .Y(n10851) );
INVX2TS U7128 ( .A(n5021), .Y(n5023) );
XOR2XLTS U7129 ( .A(n10488), .B(n10487), .Y(n10489) );
INVX2TS U7130 ( .A(n10864), .Y(n10866) );
XNOR2X1TS U7131 ( .A(n10476), .B(n10475), .Y(n10477) );
NAND2X1TS U7132 ( .A(Op_MX[31]), .B(Op_MX[4]), .Y(n1580) );
NOR2X2TS U7133 ( .A(Op_MX[31]), .B(Op_MX[4]), .Y(n1579) );
OAI22X1TS U7134 ( .A0(n4648), .A1(n907), .B0(n4649), .B1(n4672), .Y(n4476)
);
OAI22X1TS U7135 ( .A0(n4771), .A1(n4714), .B0(n4643), .B1(n907), .Y(n4465)
);
OAI22X1TS U7136 ( .A0(n4627), .A1(n907), .B0(n4628), .B1(n4672), .Y(n4202)
);
NOR2X2TS U7137 ( .A(Op_MY[36]), .B(Op_MY[29]), .Y(n7700) );
NAND2X1TS U7138 ( .A(Op_MY[36]), .B(Op_MY[9]), .Y(n1475) );
OR2X2TS U7139 ( .A(Op_MY[36]), .B(Op_MY[9]), .Y(n1074) );
OAI22X1TS U7140 ( .A0(n2195), .A1(Op_MX[25]), .B0(n2199), .B1(n988), .Y(
n1361) );
ADDFHX2TS U7141 ( .A(n10896), .B(n10895), .CI(n10894), .CO(n10452), .S(
n10898) );
NAND2X1TS U7142 ( .A(Op_MX[29]), .B(Op_MX[2]), .Y(n1572) );
NOR2X1TS U7143 ( .A(Op_MX[29]), .B(Op_MX[2]), .Y(n1571) );
NAND2X1TS U7144 ( .A(Op_MX[43]), .B(Op_MX[16]), .Y(n3956) );
NAND2X1TS U7145 ( .A(n883), .B(Op_MX[42]), .Y(n3938) );
NOR2X2TS U7146 ( .A(Op_MY[38]), .B(Op_MY[31]), .Y(n7677) );
INVX2TS U7147 ( .A(n10596), .Y(n8862) );
INVX2TS U7148 ( .A(n10678), .Y(n8868) );
XOR2X2TS U7149 ( .A(n8916), .B(n8915), .Y(n9170) );
NAND2X1TS U7150 ( .A(Op_MX[34]), .B(Op_MX[7]), .Y(n1552) );
INVX2TS U7151 ( .A(n4122), .Y(n4113) );
INVX2TS U7152 ( .A(n8921), .Y(n5590) );
INVX2TS U7153 ( .A(n3960), .Y(n3964) );
NAND2X1TS U7154 ( .A(Op_MX[41]), .B(Op_MX[14]), .Y(n3934) );
ADDHXLTS U7155 ( .A(Op_MX[14]), .B(Op_MX[41]), .CO(n1565), .S(n1861) );
XOR2XLTS U7156 ( .A(n10472), .B(n10471), .Y(n10473) );
AOI21X1TS U7157 ( .A0(n4112), .A1(n1363), .B0(n1352), .Y(n1353) );
AOI21X1TS U7158 ( .A0(n4112), .A1(n1363), .B0(n1365), .Y(n1341) );
AOI21X1TS U7159 ( .A0(n4112), .A1(n1322), .B0(n1321), .Y(n1325) );
AOI21X1TS U7160 ( .A0(n4112), .A1(n1317), .B0(n1316), .Y(n1319) );
OAI22X1TS U7161 ( .A0(n4964), .A1(n4714), .B0(n4942), .B1(n907), .Y(n4742)
);
OAI22X1TS U7162 ( .A0(n4938), .A1(n907), .B0(n4896), .B1(n4672), .Y(n4717)
);
OAI22X1TS U7163 ( .A0(n4964), .A1(n907), .B0(n4942), .B1(n4672), .Y(n4720)
);
OAI22X1TS U7164 ( .A0(n4900), .A1(n907), .B0(n4772), .B1(n4672), .Y(n4638)
);
OAI22X1TS U7165 ( .A0(n4938), .A1(n4714), .B0(n4896), .B1(n907), .Y(n4703)
);
OAI22X1TS U7166 ( .A0(n4771), .A1(n907), .B0(n4643), .B1(n4672), .Y(n4546)
);
OAI22X1TS U7167 ( .A0(n4900), .A1(n4714), .B0(n4772), .B1(n907), .Y(n4529)
);
OAI211XLTS U7168 ( .A0(n10498), .A1(n11211), .B0(n10509), .C0(n10508), .Y(
n357) );
NAND2X1TS U7169 ( .A(Op_MY[14]), .B(Op_MY[41]), .Y(n4057) );
NOR2X2TS U7170 ( .A(Op_MY[14]), .B(Op_MY[41]), .Y(n4056) );
ADDHX1TS U7171 ( .A(n3080), .B(Op_MY[41]), .CO(n1515), .S(n1772) );
OAI211XLTS U7172 ( .A0(n10498), .A1(n11212), .B0(n10506), .C0(n10505), .Y(
n356) );
ADDHXLTS U7173 ( .A(Op_MX[18]), .B(Op_MX[25]), .CO(n5803), .S(n5804) );
XNOR2X1TS U7174 ( .A(n4462), .B(Op_MX[25]), .Y(n4468) );
XNOR2X2TS U7175 ( .A(n1671), .B(Op_MX[25]), .Y(n1836) );
OAI22X1TS U7176 ( .A0(n1429), .A1(n988), .B0(n880), .B1(Op_MX[25]), .Y(n1436) );
OAI22X1TS U7177 ( .A0(n1429), .A1(Op_MX[25]), .B0(n1390), .B1(n988), .Y(
n1432) );
OAI22X1TS U7178 ( .A0(n1390), .A1(Op_MX[25]), .B0(n1391), .B1(n988), .Y(
n1387) );
OAI22X1TS U7179 ( .A0(n2194), .A1(Op_MX[25]), .B0(n2195), .B1(n988), .Y(
n1401) );
CMPR32X2TS U7180 ( .A(Op_MY[45]), .B(Op_MY[18]), .C(n1501), .CO(n1496), .S(
n1530) );
CMPR32X2TS U7181 ( .A(Op_MY[23]), .B(Op_MY[50]), .C(n4140), .CO(n4188), .S(
n4128) );
CMPR32X2TS U7182 ( .A(Op_MY[9]), .B(Op_MY[23]), .C(n2283), .CO(n2279), .S(
n2288) );
CMPR32X2TS U7183 ( .A(n8753), .B(Op_MY[51]), .C(n8752), .CO(n9770), .S(n9871) );
OAI22X1TS U7184 ( .A0(Op_MY[50]), .A1(n8754), .B0(Op_MY[51]), .B1(n8753),
.Y(n7384) );
NAND2X1TS U7185 ( .A(Op_MY[51]), .B(Op_MY[24]), .Y(n1335) );
OAI211XLTS U7186 ( .A0(n10498), .A1(n11213), .B0(n10513), .C0(n10512), .Y(
n355) );
OAI22X1TS U7187 ( .A0(Op_MY[50]), .A1(n8753), .B0(Op_MY[49]), .B1(n8754),
.Y(n7343) );
OAI22X1TS U7188 ( .A0(Op_MY[49]), .A1(n8753), .B0(n8754), .B1(Op_MY[48]),
.Y(n7324) );
CMPR32X2TS U7189 ( .A(Op_MY[22]), .B(Op_MY[49]), .C(n4127), .CO(n4140), .S(
n4119) );
INVX2TS U7190 ( .A(n9740), .Y(n9034) );
OA21X4TS U7191 ( .A0(n9813), .A1(n730), .B0(n851), .Y(n917) );
OR2X1TS U7192 ( .A(n9059), .B(n9058), .Y(n919) );
OR2X2TS U7193 ( .A(n9080), .B(n9079), .Y(n923) );
MXI2X1TS U7194 ( .A(Data_MY[43]), .B(Op_MY[43]), .S0(n11006), .Y(n935) );
MXI2X1TS U7195 ( .A(Data_MX[48]), .B(Op_MX[48]), .S0(n10552), .Y(n936) );
MXI2X1TS U7196 ( .A(Data_MX[50]), .B(Op_MX[50]), .S0(n10552), .Y(n937) );
MXI2X1TS U7197 ( .A(Data_MY[39]), .B(Op_MY[39]), .S0(n10554), .Y(n938) );
MXI2X1TS U7198 ( .A(Data_MY[35]), .B(Op_MY[35]), .S0(n10554), .Y(n939) );
MXI2X1TS U7199 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(n10682), .Y(n941) );
OA21XLTS U7200 ( .A0(n6349), .A1(n1198), .B0(n1197), .Y(n943) );
AO21X4TS U7201 ( .A0(n1215), .A1(n962), .B0(n8463), .Y(n959) );
XNOR2X1TS U7202 ( .A(n3655), .B(n3654), .Y(n964) );
AO21XLTS U7203 ( .A0(n3882), .A1(n1163), .B0(n3881), .Y(n969) );
CLKAND2X2TS U7204 ( .A(n1152), .B(n1163), .Y(n970) );
OR2X1TS U7205 ( .A(n9725), .B(n9046), .Y(n971) );
CLKAND2X2TS U7206 ( .A(n1071), .B(n10117), .Y(n973) );
OR2X1TS U7207 ( .A(n3081), .B(n3080), .Y(n977) );
AO21X1TS U7208 ( .A0(n1019), .A1(n979), .B0(n3897), .Y(n978) );
AO21XLTS U7209 ( .A0(n2259), .A1(n1155), .B0(n2255), .Y(n986) );
MXI2X1TS U7210 ( .A(DP_OP_338J35_122_4684_n1289), .B(
DP_OP_338J35_122_4684_n1288), .S0(DP_OP_338J35_122_4684_n1286), .Y(
n990) );
CLKAND2X2TS U7211 ( .A(DP_OP_338J35_122_4684_n1286), .B(
DP_OP_338J35_122_4684_n1290), .Y(n991) );
OR2X1TS U7212 ( .A(n9052), .B(n9051), .Y(n1000) );
OR2X1TS U7213 ( .A(n5340), .B(n5339), .Y(n1001) );
CLKAND2X2TS U7214 ( .A(n1001), .B(n5341), .Y(n1002) );
OR2X1TS U7215 ( .A(n2819), .B(n2818), .Y(n1004) );
CLKAND2X2TS U7216 ( .A(n1004), .B(n2820), .Y(n1005) );
ADDHX1TS U7217 ( .A(n6112), .B(n6111), .CO(n6131), .S(n6106) );
ADDHX1TS U7218 ( .A(n8126), .B(n8125), .CO(n8146), .S(n8120) );
OR2X1TS U7219 ( .A(n5302), .B(n5301), .Y(n1006) );
OR2X1TS U7220 ( .A(Op_MX[28]), .B(Op_MX[1]), .Y(n1008) );
OR2X1TS U7221 ( .A(n9054), .B(n9053), .Y(n1009) );
OR2X2TS U7222 ( .A(n9073), .B(n9072), .Y(n1010) );
OR2X1TS U7223 ( .A(n3893), .B(n3892), .Y(n1017) );
OR2X1TS U7224 ( .A(n3896), .B(n3895), .Y(n1019) );
INVX2TS U7225 ( .A(n7573), .Y(n9336) );
OR2X1TS U7226 ( .A(Op_MY[22]), .B(Op_MY[15]), .Y(n1025) );
INVX2TS U7227 ( .A(n8754), .Y(n9763) );
OR2X1TS U7228 ( .A(Op_MY[47]), .B(Op_MY[40]), .Y(n1027) );
OR2X1TS U7229 ( .A(Op_MY[21]), .B(Op_MY[14]), .Y(n1033) );
OR2X1TS U7230 ( .A(Op_MY[14]), .B(Op_MY[0]), .Y(n1035) );
INVX2TS U7231 ( .A(n2285), .Y(n2386) );
OR2X1TS U7232 ( .A(n6354), .B(n1049), .Y(n1039) );
INVX2TS U7233 ( .A(n9326), .Y(n9722) );
INVX2TS U7234 ( .A(n5304), .Y(n9066) );
INVX2TS U7235 ( .A(n9331), .Y(n9716) );
OR2X2TS U7236 ( .A(n3047), .B(n3046), .Y(n1052) );
INVX2TS U7237 ( .A(n9334), .Y(n7623) );
OR2X4TS U7238 ( .A(n5038), .B(n5037), .Y(n1054) );
INVX2TS U7239 ( .A(n9738), .Y(n9030) );
INVX2TS U7240 ( .A(n8613), .Y(n10618) );
OR2X1TS U7241 ( .A(n3697), .B(n3696), .Y(n1062) );
CLKAND2X2TS U7242 ( .A(n1062), .B(n3830), .Y(n1064) );
OR2X1TS U7243 ( .A(n4334), .B(n4333), .Y(n1072) );
INVX2TS U7244 ( .A(n4336), .Y(n9044) );
INVX2TS U7245 ( .A(n9329), .Y(n9719) );
NOR2BX1TS U7246 ( .AN(n3282), .B(n1449), .Y(n9309) );
INVX2TS U7247 ( .A(n9309), .Y(n3754) );
INVX2TS U7248 ( .A(n9737), .Y(n9028) );
NOR2X1TS U7249 ( .A(n4647), .B(n4223), .Y(n8940) );
INVX2TS U7250 ( .A(n8940), .Y(n4254) );
INVX2TS U7251 ( .A(n8124), .Y(n8177) );
INVX2TS U7252 ( .A(n6110), .Y(n6163) );
OR2X1TS U7253 ( .A(n9870), .B(n9869), .Y(n1092) );
OR2X1TS U7254 ( .A(n4851), .B(n4850), .Y(n1093) );
CLKAND2X2TS U7255 ( .A(n1093), .B(n4852), .Y(n1094) );
INVX2TS U7256 ( .A(n7596), .Y(n8659) );
OR2X1TS U7257 ( .A(n9867), .B(n9868), .Y(n1097) );
CLKAND2X2TS U7258 ( .A(n7599), .B(n7600), .Y(n1098) );
OR2X1TS U7259 ( .A(n6738), .B(n6737), .Y(n1099) );
OR2X1TS U7260 ( .A(n6548), .B(n6547), .Y(n1100) );
CLKAND2X2TS U7261 ( .A(n1100), .B(n6549), .Y(n1101) );
OR2X1TS U7262 ( .A(n6746), .B(n6745), .Y(n1103) );
INVX2TS U7263 ( .A(n6748), .Y(n8567) );
NAND2X1TS U7264 ( .A(n1103), .B(n6747), .Y(n6748) );
OR2X1TS U7265 ( .A(Op_MY[24]), .B(Op_MY[17]), .Y(n1108) );
OR2X1TS U7266 ( .A(n3811), .B(n3810), .Y(n1110) );
INVX2TS U7267 ( .A(n4332), .Y(n8934) );
OR2X1TS U7268 ( .A(n7901), .B(n7848), .Y(n1115) );
OR2X1TS U7269 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(n1116) );
NAND2X1TS U7270 ( .A(n1116), .B(n1569), .Y(n1570) );
OR2X1TS U7271 ( .A(n7911), .B(n7899), .Y(n1119) );
INVX2TS U7272 ( .A(n7598), .Y(n9320) );
NAND2X2TS U7273 ( .A(n1119), .B(n7597), .Y(n7598) );
INVX2TS U7274 ( .A(n7524), .Y(n8459) );
INVX2TS U7275 ( .A(n4323), .Y(n5598) );
OR2X4TS U7276 ( .A(n5610), .B(n5609), .Y(n1142) );
OR2X1TS U7277 ( .A(Op_MY[34]), .B(Op_MY[27]), .Y(n1150) );
OR2X1TS U7278 ( .A(n3672), .B(n3671), .Y(n1152) );
OR2X1TS U7279 ( .A(n2345), .B(n2376), .Y(n1155) );
OR2X1TS U7280 ( .A(n2350), .B(n2338), .Y(n1156) );
NOR2BX1TS U7281 ( .AN(Op_MY[0]), .B(n1087), .Y(n10556) );
INVX2TS U7282 ( .A(n10557), .Y(n6749) );
INVX2TS U7283 ( .A(n10558), .Y(n6744) );
INVX2TS U7284 ( .A(n1449), .Y(n3080) );
OR2X1TS U7285 ( .A(n3899), .B(n3898), .Y(n1159) );
OA21XLTS U7286 ( .A0(n5480), .A1(n5479), .B0(n5478), .Y(n1161) );
OR2X1TS U7287 ( .A(n3676), .B(n3675), .Y(n1163) );
OR2X1TS U7288 ( .A(n3885), .B(n3884), .Y(n1164) );
INVX2TS U7289 ( .A(n6706), .Y(n8549) );
INVX2TS U7290 ( .A(n10559), .Y(n6736) );
INVX2TS U7291 ( .A(n10560), .Y(n6728) );
INVX2TS U7292 ( .A(n10561), .Y(n6722) );
INVX2TS U7293 ( .A(n10562), .Y(n6714) );
INVX2TS U7294 ( .A(n6529), .Y(n9037) );
INVX2TS U7295 ( .A(n10612), .Y(n6774) );
INVX2TS U7296 ( .A(n10613), .Y(n6780) );
INVX2TS U7297 ( .A(n10614), .Y(n6701) );
INVX2TS U7298 ( .A(n10615), .Y(n6695) );
INVX2TS U7299 ( .A(n10616), .Y(n6687) );
OR2X1TS U7300 ( .A(n10631), .B(n10630), .Y(n1169) );
CLKAND2X2TS U7301 ( .A(n1169), .B(n10632), .Y(n1170) );
XNOR2X1TS U7302 ( .A(n3888), .B(n3887), .Y(n1173) );
OR2X1TS U7303 ( .A(n5432), .B(n1174), .Y(n1183) );
XNOR2X2TS U7304 ( .A(n3659), .B(n3658), .Y(n1184) );
BUFX6TS U7305 ( .A(n11165), .Y(n11168) );
BUFX4TS U7306 ( .A(n11165), .Y(n11169) );
INVX4TS U7307 ( .A(n11172), .Y(n11165) );
OR2X1TS U7308 ( .A(n6195), .B(n6194), .Y(n1185) );
CLKAND2X2TS U7309 ( .A(n1185), .B(n6196), .Y(n1186) );
BUFX4TS U7310 ( .A(n11069), .Y(n11158) );
BUFX6TS U7311 ( .A(n11158), .Y(n11139) );
AO21X4TS U7312 ( .A0(n1171), .A1(n10576), .B0(n9312), .Y(n1191) );
OR2X1TS U7313 ( .A(n6115), .B(n6114), .Y(n1193) );
OR2X1TS U7314 ( .A(n6118), .B(n6117), .Y(n1194) );
OR2X1TS U7315 ( .A(n6120), .B(n6119), .Y(n1195) );
OA21XLTS U7316 ( .A0(n6348), .A1(n6347), .B0(n6346), .Y(n1197) );
OR2X1TS U7317 ( .A(n6345), .B(n6348), .Y(n1198) );
OR2X2TS U7318 ( .A(Op_MY[35]), .B(Op_MY[8]), .Y(n1200) );
OR2X1TS U7319 ( .A(n8315), .B(n8314), .Y(n1201) );
OR2X1TS U7320 ( .A(n8326), .B(n8325), .Y(n1203) );
OR2X1TS U7321 ( .A(n8132), .B(n8131), .Y(n1210) );
OA21XLTS U7322 ( .A0(n8373), .A1(n8372), .B0(n8371), .Y(n1211) );
XNOR2X1TS U7323 ( .A(n8756), .B(n8755), .Y(n1212) );
INVX2TS U7324 ( .A(n9452), .Y(n9453) );
OR2X1TS U7325 ( .A(DP_OP_342J35_126_4270_n772), .B(n9876), .Y(n1226) );
CLKAND2X2TS U7326 ( .A(n8738), .B(n8743), .Y(n1227) );
BUFX6TS U7327 ( .A(n754), .Y(n11237) );
BUFX4TS U7328 ( .A(n11232), .Y(n11240) );
NAND2X4TS U7329 ( .A(n11009), .B(n10429), .Y(n11249) );
BUFX4TS U7330 ( .A(n11241), .Y(n11238) );
BUFX4TS U7331 ( .A(n11241), .Y(n11239) );
BUFX4TS U7332 ( .A(n11241), .Y(n11230) );
BUFX4TS U7333 ( .A(n11241), .Y(n11229) );
BUFX4TS U7334 ( .A(n11241), .Y(n11236) );
BUFX4TS U7335 ( .A(n11249), .Y(n11241) );
INVX6TS U7336 ( .A(n9512), .Y(n11006) );
INVX6TS U7337 ( .A(n9512), .Y(n10681) );
INVX2TS U7338 ( .A(n10122), .Y(n10141) );
OAI22X1TS U7339 ( .A0(n10189), .A1(n10165), .B0(n10166), .B1(n10186), .Y(
n10181) );
INVX2TS U7340 ( .A(n1602), .Y(n1544) );
OAI22X1TS U7341 ( .A0(n10191), .A1(n2169), .B0(n10189), .B1(n10184), .Y(
n10221) );
INVX2TS U7342 ( .A(n3962), .Y(n3963) );
OAI22X1TS U7343 ( .A0(n4911), .A1(n4628), .B0(n4756), .B1(n4627), .Y(n4644)
);
OAI22X1TS U7344 ( .A0(n4771), .A1(n4756), .B0(n4643), .B1(n4911), .Y(n4621)
);
INVX2TS U7345 ( .A(n3716), .Y(n3142) );
NAND2X1TS U7346 ( .A(n1790), .B(n1789), .Y(n1792) );
OAI22X1TS U7347 ( .A0(n10247), .A1(n2041), .B0(n10245), .B1(n10246), .Y(
n10269) );
NAND2X1TS U7348 ( .A(n3945), .B(n3944), .Y(n3946) );
INVX2TS U7349 ( .A(n5171), .Y(n5156) );
INVX2TS U7350 ( .A(n1473), .Y(n1466) );
INVX2TS U7351 ( .A(n10270), .Y(n10293) );
INVX2TS U7352 ( .A(n4020), .Y(n4022) );
XOR2X1TS U7353 ( .A(n5480), .B(n5132), .Y(n5160) );
INVX2TS U7354 ( .A(n7361), .Y(n7362) );
INVX2TS U7355 ( .A(n9857), .Y(DP_OP_342J35_126_4270_n275) );
INVX2TS U7356 ( .A(n9860), .Y(DP_OP_342J35_126_4270_n278) );
NAND2X1TS U7357 ( .A(n2219), .B(n2233), .Y(n2220) );
INVX2TS U7358 ( .A(n3709), .Y(n3226) );
INVX2TS U7359 ( .A(n3083), .Y(n3559) );
INVX2TS U7360 ( .A(n1648), .Y(n1619) );
NAND2X1TS U7361 ( .A(n1117), .B(n1707), .Y(n1708) );
INVX2TS U7362 ( .A(n1596), .Y(n1598) );
NOR2X1TS U7363 ( .A(n4647), .B(n907), .Y(n4175) );
OAI22X1TS U7364 ( .A0(n7898), .A1(n7847), .B0(n7900), .B1(n8018), .Y(n7780)
);
NAND2X1TS U7365 ( .A(n5456), .B(n5473), .Y(n5183) );
NOR2X1TS U7366 ( .A(n814), .B(n7908), .Y(n7726) );
NOR2X2TS U7367 ( .A(Op_MY[39]), .B(Op_MY[32]), .Y(n7663) );
NAND2X1TS U7368 ( .A(n7363), .B(n7362), .Y(n7364) );
OAI22X1TS U7369 ( .A0(n9844), .A1(n9834), .B0(n9845), .B1(n9833), .Y(
DP_OP_342J35_126_4270_n320) );
OAI22X1TS U7370 ( .A0(n9843), .A1(n9830), .B0(n917), .B1(n9831), .Y(
DP_OP_342J35_126_4270_n309) );
OAI22X1TS U7371 ( .A0(n9849), .A1(n9836), .B0(n9847), .B1(n9835), .Y(
DP_OP_342J35_126_4270_n331) );
NOR2X1TS U7372 ( .A(n839), .B(n2605), .Y(n2637) );
OAI22X1TS U7373 ( .A0(n9949), .A1(n9928), .B0(n9929), .B1(n9945), .Y(n9952)
);
NOR2X2TS U7374 ( .A(Op_MX[33]), .B(Op_MX[6]), .Y(n1584) );
INVX2TS U7375 ( .A(n3637), .Y(n3465) );
OAI22X1TS U7376 ( .A0(n3497), .A1(n3560), .B0(n3427), .B1(n805), .Y(n3491)
);
NAND2X1TS U7377 ( .A(n1455), .B(n1454), .Y(n1456) );
NOR2X2TS U7378 ( .A(Op_MY[39]), .B(Op_MY[12]), .Y(n1453) );
INVX2TS U7379 ( .A(n8131), .Y(n7846) );
OAI22X1TS U7380 ( .A0(n8017), .A1(n7944), .B0(n7905), .B1(n7898), .Y(n7867)
);
NAND2X1TS U7381 ( .A(n5463), .B(n5472), .Y(n5464) );
INVX2TS U7382 ( .A(n4692), .Y(n4695) );
AOI21X1TS U7383 ( .A0(n7365), .A1(n1217), .B0(n7364), .Y(n7366) );
OAI22X1TS U7384 ( .A0(n9845), .A1(n9848), .B0(n9849), .B1(n9846), .Y(
DP_OP_342J35_126_4270_n348) );
OAI22X1TS U7385 ( .A0(n9945), .A1(n2798), .B0(n9961), .B1(n2672), .Y(n2700)
);
OAI22X1TS U7386 ( .A0(n3426), .A1(n878), .B0(n3397), .B1(n3480), .Y(n3418)
);
OAI22X1TS U7387 ( .A0(n9993), .A1(n9945), .B0(n9992), .B1(n9949), .Y(n9915)
);
INVX2TS U7388 ( .A(n3652), .Y(n3456) );
OAI22X1TS U7389 ( .A0(n3025), .A1(n877), .B0(n3126), .B1(n3499), .Y(n3154)
);
INVX2TS U7390 ( .A(n6228), .Y(n6069) );
OAI22X1TS U7391 ( .A0(n10188), .A1(n2041), .B0(n10190), .B1(n10246), .Y(
n2032) );
INVX2TS U7392 ( .A(n3896), .Y(n1937) );
INVX2TS U7393 ( .A(n4294), .Y(n2149) );
INVX2TS U7394 ( .A(n5015), .Y(n5006) );
INVX2TS U7395 ( .A(n8250), .Y(n8073) );
INVX2TS U7396 ( .A(n7238), .Y(n7054) );
AOI21X1TS U7397 ( .A0(n2482), .A1(n2481), .B0(n2480), .Y(n2483) );
INVX2TS U7398 ( .A(n2917), .Y(n2920) );
XNOR2X1TS U7399 ( .A(n900), .B(n3282), .Y(n3032) );
XNOR2X1TS U7400 ( .A(n3192), .B(n900), .Y(n3101) );
NAND2X1TS U7401 ( .A(n9883), .B(n9882), .Y(n10069) );
INVX2TS U7402 ( .A(n5692), .Y(n6082) );
INVX2TS U7403 ( .A(n4807), .Y(n4747) );
AOI21X1TS U7404 ( .A0(n5193), .A1(n5137), .B0(n5136), .Y(n5138) );
INVX2TS U7405 ( .A(n9694), .Y(n9701) );
INVX2TS U7406 ( .A(n2347), .Y(n2377) );
NOR2X1TS U7407 ( .A(n2876), .B(n839), .Y(n2893) );
NAND2X1TS U7408 ( .A(n2922), .B(n2921), .Y(n2923) );
INVX2TS U7409 ( .A(n10107), .Y(n10109) );
INVX2TS U7410 ( .A(n3770), .Y(n3772) );
NAND2X1TS U7411 ( .A(n3800), .B(n3805), .Y(n3808) );
NAND2X1TS U7412 ( .A(n1071), .B(n10069), .Y(n6882) );
INVX2TS U7413 ( .A(n8928), .Y(n5336) );
NAND2X1TS U7414 ( .A(n3595), .B(n3594), .Y(n3687) );
OAI21X1TS U7415 ( .A0(n3841), .A1(n3855), .B0(n3842), .Y(n3535) );
INVX2TS U7416 ( .A(n5483), .Y(n5484) );
NAND2X1TS U7417 ( .A(n7385), .B(n8739), .Y(n7386) );
INVX2TS U7418 ( .A(n9728), .Y(DP_OP_344J35_128_4078_n122) );
ADDHX1TS U7419 ( .A(Op_MX[8]), .B(Op_MX[22]), .CO(n2395), .S(n2304) );
XNOR2X1TS U7420 ( .A(n2924), .B(n2923), .Y(n6585) );
INVX2TS U7421 ( .A(n10101), .Y(n10111) );
OAI21X1TS U7422 ( .A0(n3809), .A1(n3769), .B0(n3768), .Y(n3774) );
INVX2TS U7423 ( .A(n5650), .Y(n6000) );
NAND2X1TS U7424 ( .A(n3606), .B(n3605), .Y(n3644) );
INVX2TS U7425 ( .A(n4284), .Y(n2182) );
INVX2TS U7426 ( .A(n4285), .Y(n2167) );
NAND2X1TS U7427 ( .A(n1164), .B(n3886), .Y(n3887) );
NOR2XLTS U7428 ( .A(n9664), .B(n9685), .Y(DP_OP_341J35_125_6458_n191) );
XNOR2X1TS U7429 ( .A(n7167), .B(n7166), .Y(n7422) );
NAND2X1TS U7430 ( .A(n3613), .B(n3612), .Y(n3614) );
AOI21X1TS U7431 ( .A0(n6180), .A1(n1194), .B0(n6159), .Y(n6162) );
INVX2TS U7432 ( .A(n3660), .Y(n3657) );
INVX2TS U7433 ( .A(n5620), .Y(n5383) );
AOI21X1TS U7434 ( .A0(n6342), .A1(n6817), .B0(n6341), .Y(n6343) );
NAND2X1TS U7435 ( .A(n8259), .B(n8281), .Y(n8260) );
INVX2TS U7436 ( .A(n8183), .Y(n8185) );
INVX2TS U7437 ( .A(n8157), .Y(n8151) );
INVX2TS U7438 ( .A(n9744), .Y(DP_OP_344J35_128_4078_n149) );
AOI21X1TS U7439 ( .A0(n8729), .A1(n8728), .B0(n8727), .Y(n8730) );
INVX2TS U7440 ( .A(n2846), .Y(n2790) );
INVX2TS U7441 ( .A(n8607), .Y(n6668) );
INVX2TS U7442 ( .A(n8599), .Y(n6646) );
INVX2TS U7443 ( .A(n8581), .Y(n6826) );
INVX2TS U7444 ( .A(n7013), .Y(n7010) );
INVX2TS U7445 ( .A(n9059), .Y(n5356) );
INVX2TS U7446 ( .A(n5425), .Y(n5426) );
INVX2TS U7447 ( .A(n9009), .Y(n5526) );
INVX2TS U7448 ( .A(n8869), .Y(n8871) );
INVX2TS U7449 ( .A(n8665), .Y(n9720) );
INVX2TS U7450 ( .A(n9739), .Y(n9032) );
INVX2TS U7451 ( .A(n6297), .Y(n6281) );
INVX2TS U7452 ( .A(n10617), .Y(n9025) );
INVX2TS U7453 ( .A(n6631), .Y(n6633) );
INVX2TS U7454 ( .A(n5431), .Y(n5211) );
INVX2TS U7455 ( .A(n6812), .Y(n6612) );
NOR2X1TS U7456 ( .A(n9648), .B(n3003), .Y(n8458) );
NAND2X1TS U7457 ( .A(n5081), .B(n5103), .Y(n5082) );
ADDHXLTS U7458 ( .A(n10398), .B(n10397), .CO(n10400), .S(
DP_OP_347J35_131_5122_n95) );
INVX2TS U7459 ( .A(n8555), .Y(n6763) );
NAND2X1TS U7460 ( .A(n1009), .B(n1000), .Y(n9287) );
INVX2TS U7461 ( .A(n9238), .Y(n9239) );
INVX2TS U7462 ( .A(n9408), .Y(n8834) );
INVX2TS U7463 ( .A(n9423), .Y(n9424) );
INVX2TS U7464 ( .A(n6955), .Y(n6956) );
NAND2X1TS U7465 ( .A(n971), .B(n9306), .Y(n9050) );
INVX2TS U7466 ( .A(n9287), .Y(n9290) );
NAND2X1TS U7467 ( .A(n9240), .B(n9251), .Y(n9242) );
XOR2X1TS U7468 ( .A(n8836), .B(n1125), .Y(n9131) );
OAI21XLTS U7469 ( .A0(FSM_selector_B[0]), .A1(n10550), .B0(n10549), .Y(
n10551) );
OAI21XLTS U7470 ( .A0(n6969), .A1(n6968), .B0(n6972), .Y(n6970) );
INVX2TS U7471 ( .A(n8543), .Y(n6938) );
NAND2X1TS U7472 ( .A(n9286), .B(n9285), .Y(n9292) );
OAI21XLTS U7473 ( .A0(n9268), .A1(n9277), .B0(n9267), .Y(n9269) );
NAND2X1TS U7474 ( .A(n926), .B(n9220), .Y(n9223) );
INVX2TS U7475 ( .A(n10798), .Y(n10800) );
INVX2TS U7476 ( .A(n10878), .Y(n10880) );
INVX6TS U7477 ( .A(n10854), .Y(n10992) );
XOR2X1TS U7478 ( .A(n9296), .B(n9295), .Y(n10647) );
NAND2X1TS U7479 ( .A(n10739), .B(n10738), .Y(n10740) );
AOI21X1TS U7480 ( .A0(n10877), .A1(n10849), .B0(n10848), .Y(n10852) );
XOR2X1TS U7481 ( .A(n9366), .B(n9365), .Y(n10464) );
OAI211XLTS U7482 ( .A0(n10854), .A1(n11206), .B0(n10842), .C0(n10841), .Y(
n10843) );
BUFX3TS U7483 ( .A(n10921), .Y(n10947) );
BUFX3TS U7484 ( .A(n10921), .Y(n11005) );
BUFX6TS U7485 ( .A(n10555), .Y(n10643) );
XOR2X1TS U7486 ( .A(n10781), .B(n10780), .Y(n10783) );
OAI211XLTS U7487 ( .A0(Sgf_normalized_result[3]), .A1(
Sgf_normalized_result[2]), .B0(n11162), .C0(n11062), .Y(n11063) );
OAI211XLTS U7488 ( .A0(Sgf_normalized_result[8]), .A1(n11072), .B0(n11162),
.C0(n11074), .Y(n11073) );
OAI211XLTS U7489 ( .A0(Sgf_normalized_result[22]), .A1(n11100), .B0(n11160),
.C0(n11102), .Y(n11101) );
OAI211XLTS U7490 ( .A0(Sgf_normalized_result[38]), .A1(n11132), .B0(n11162),
.C0(n11134), .Y(n11133) );
BUFX3TS U7491 ( .A(n11158), .Y(n11156) );
INVX4TS U7492 ( .A(n9512), .Y(n10552) );
OAI211XLTS U7493 ( .A0(n10498), .A1(n11209), .B0(n10511), .C0(n10510), .Y(
n359) );
OR2X1TS U7494 ( .A(exp_oper_result[11]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
INVX2TS U7495 ( .A(DP_OP_338J35_122_4684_n1286), .Y(n1249) );
INVX2TS U7496 ( .A(DP_OP_338J35_122_4684_n1291), .Y(n1250) );
INVX2TS U7497 ( .A(
Sgf_operation_ODD1_right_RECURSIVE_ODD1_middle_RECURSIVE_ODD1_Q_left[12]), .Y(n1255) );
INVX2TS U7498 ( .A(add_x_87_n2), .Y(n1258) );
NOR2XLTS U7499 ( .A(n11196), .B(FS_Module_state_reg[2]), .Y(n1260) );
NOR2X2TS U7500 ( .A(FS_Module_state_reg[3]), .B(n11225), .Y(n10429) );
NAND2X1TS U7501 ( .A(Op_MY[28]), .B(Op_MY[1]), .Y(n1517) );
NOR2X2TS U7502 ( .A(Op_MY[30]), .B(Op_MY[3]), .Y(n1504) );
NOR2X2TS U7503 ( .A(Op_MY[29]), .B(Op_MY[2]), .Y(n1510) );
NOR2X1TS U7504 ( .A(n1504), .B(n1510), .Y(n1262) );
NAND2X1TS U7505 ( .A(Op_MY[29]), .B(Op_MY[2]), .Y(n1511) );
NAND2X1TS U7506 ( .A(Op_MY[30]), .B(Op_MY[3]), .Y(n1505) );
OAI21X1TS U7507 ( .A0(n1504), .A1(n1511), .B0(n1505), .Y(n1261) );
AOI21X2TS U7508 ( .A0(n1503), .A1(n1262), .B0(n1261), .Y(n1482) );
NOR2X1TS U7509 ( .A(Op_MY[31]), .B(Op_MY[4]), .Y(n1489) );
NOR2X1TS U7510 ( .A(n1491), .B(n1489), .Y(n1484) );
NAND2X1TS U7511 ( .A(Op_MY[31]), .B(Op_MY[4]), .Y(n1497) );
INVX2TS U7512 ( .A(n1485), .Y(n1263) );
INVX2TS U7513 ( .A(n1538), .Y(n1479) );
NAND2X2TS U7514 ( .A(n1479), .B(n1200), .Y(n1474) );
NOR2X2TS U7515 ( .A(n1474), .B(n1270), .Y(n1272) );
INVX2TS U7516 ( .A(n1537), .Y(n1267) );
NAND2X1TS U7517 ( .A(Op_MY[35]), .B(Op_MY[8]), .Y(n1540) );
INVX2TS U7518 ( .A(n1540), .Y(n1266) );
AOI21X4TS U7519 ( .A0(n1200), .A1(n1267), .B0(n1266), .Y(n1473) );
INVX2TS U7520 ( .A(n1469), .Y(n1268) );
AOI21X4TS U7521 ( .A0(n1463), .A1(n1272), .B0(n1271), .Y(n1445) );
OAI21X4TS U7522 ( .A0(n1445), .A1(n1276), .B0(n1275), .Y(n3992) );
INVX2TS U7523 ( .A(n4031), .Y(n3991) );
NAND2X1TS U7524 ( .A(Op_MY[16]), .B(Op_MY[43]), .Y(n3993) );
INVX2TS U7525 ( .A(n3993), .Y(n1277) );
NAND2X1TS U7526 ( .A(Op_MY[19]), .B(Op_MY[46]), .Y(n3968) );
NAND2X1TS U7527 ( .A(Op_MY[47]), .B(Op_MY[20]), .Y(n3977) );
INVX2TS U7528 ( .A(n3977), .Y(n1281) );
OAI21X4TS U7529 ( .A0(n4033), .A1(n1283), .B0(n1282), .Y(n4112) );
NAND2X1TS U7530 ( .A(Op_MY[21]), .B(Op_MY[48]), .Y(n1288) );
NAND2X1TS U7531 ( .A(n1038), .B(n1313), .Y(n1284) );
INVX2TS U7532 ( .A(n1287), .Y(n2189) );
INVX2TS U7533 ( .A(n1291), .Y(n1381) );
NOR2X2TS U7534 ( .A(Op_MX[30]), .B(Op_MX[3]), .Y(n1577) );
NOR2X1TS U7535 ( .A(n1577), .B(n1579), .Y(n1295) );
NAND2X1TS U7536 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(n1569) );
INVX2TS U7537 ( .A(n1569), .Y(n1567) );
NAND2X1TS U7538 ( .A(Op_MX[28]), .B(Op_MX[1]), .Y(n1566) );
INVX2TS U7539 ( .A(n1566), .Y(n1293) );
NOR2X2TS U7540 ( .A(Op_MX[35]), .B(Op_MX[8]), .Y(n1650) );
NOR2X2TS U7541 ( .A(Op_MX[36]), .B(Op_MX[9]), .Y(n1654) );
NOR2X2TS U7542 ( .A(n1551), .B(n1584), .Y(n1616) );
INVX2TS U7543 ( .A(n3935), .Y(n3928) );
NAND2X1TS U7544 ( .A(n1118), .B(n3928), .Y(n3950) );
NOR2X1TS U7545 ( .A(n3955), .B(n3950), .Y(n1307) );
NAND2X1TS U7546 ( .A(n3932), .B(n1307), .Y(n1309) );
NAND2X1TS U7547 ( .A(Op_MX[33]), .B(Op_MX[6]), .Y(n1585) );
NAND2X1TS U7548 ( .A(Op_MX[35]), .B(Op_MX[8]), .Y(n1649) );
NAND2X1TS U7549 ( .A(Op_MX[36]), .B(Op_MX[9]), .Y(n1655) );
OAI21X1TS U7550 ( .A0(n1596), .A1(n1641), .B0(n1597), .Y(n1674) );
NAND2X1TS U7551 ( .A(Op_MX[39]), .B(Op_MX[12]), .Y(n1680) );
INVX2TS U7552 ( .A(n1680), .Y(n1298) );
AOI21X1TS U7553 ( .A0(n999), .A1(n1674), .B0(n1298), .Y(n1299) );
OAI21X2TS U7554 ( .A0(n1300), .A1(n1591), .B0(n1299), .Y(n1701) );
INVX2TS U7555 ( .A(n1707), .Y(n1301) );
INVX2TS U7556 ( .A(n3934), .Y(n1305) );
AOI21X1TS U7557 ( .A0(n1118), .A1(n1305), .B0(n1304), .Y(n3949) );
AOI21X1TS U7558 ( .A0(n1307), .A1(n3933), .B0(n1306), .Y(n1308) );
OAI21X2TS U7559 ( .A0(n1548), .A1(n1309), .B0(n1308), .Y(n4014) );
NAND2X1TS U7560 ( .A(n827), .B(n1111), .Y(n4010) );
NAND2X1TS U7561 ( .A(Op_MX[17]), .B(Op_MX[44]), .Y(n3971) );
INVX2TS U7562 ( .A(n3971), .Y(n3985) );
NAND2X1TS U7563 ( .A(n881), .B(Op_MX[18]), .Y(n3986) );
INVX2TS U7564 ( .A(n3986), .Y(n1310) );
AOI21X1TS U7565 ( .A0(n827), .A1(n3985), .B0(n1310), .Y(n4011) );
NAND2X1TS U7566 ( .A(Op_MX[19]), .B(Op_MX[46]), .Y(n4016) );
NAND2X1TS U7567 ( .A(Op_MX[47]), .B(Op_MX[20]), .Y(n4021) );
OAI21X2TS U7568 ( .A0(n4024), .A1(n4020), .B0(n4021), .Y(n4149) );
INVX2TS U7569 ( .A(n1333), .Y(n1322) );
INVX2TS U7570 ( .A(n1340), .Y(n1321) );
INVX2TS U7571 ( .A(n4117), .Y(n2190) );
INVX2TS U7572 ( .A(n1328), .Y(n1382) );
INVX2TS U7573 ( .A(n1343), .Y(n1428) );
OAI22X1TS U7574 ( .A0(n1429), .A1(n1428), .B0(n880), .B1(n1389), .Y(n1425)
);
CLKXOR2X4TS U7575 ( .A(n1448), .B(n1447), .Y(n3063) );
INVX2TS U7576 ( .A(n1453), .Y(n1455) );
XNOR2X4TS U7577 ( .A(n1529), .B(n1461), .Y(n3052) );
INVX2TS U7578 ( .A(n1474), .Y(n1464) );
XNOR2X4TS U7579 ( .A(n1471), .B(n1470), .Y(n3201) );
XNOR2X4TS U7580 ( .A(n1477), .B(n1476), .Y(n3047) );
INVX2TS U7581 ( .A(n1482), .Y(n1500) );
AOI21X1TS U7582 ( .A0(n1500), .A1(n1484), .B0(n1483), .Y(n1487) );
NAND2X1TS U7583 ( .A(n1076), .B(n1485), .Y(n1486) );
INVX2TS U7584 ( .A(n1489), .Y(n1498) );
INVX2TS U7585 ( .A(n1497), .Y(n1490) );
AOI21X1TS U7586 ( .A0(n1500), .A1(n1498), .B0(n1490), .Y(n1495) );
INVX2TS U7587 ( .A(n1491), .Y(n1493) );
NAND2X1TS U7588 ( .A(n1493), .B(n1492), .Y(n1494) );
NAND2X1TS U7589 ( .A(n1498), .B(n1497), .Y(n1499) );
XNOR2X4TS U7590 ( .A(n1500), .B(n1499), .Y(n3051) );
OAI21X1TS U7591 ( .A0(n1514), .A1(n1510), .B0(n1511), .Y(n1508) );
INVX2TS U7592 ( .A(n1504), .Y(n1506) );
NAND2X1TS U7593 ( .A(n1506), .B(n1505), .Y(n1507) );
INVX2TS U7594 ( .A(n1510), .Y(n1512) );
NAND2X1TS U7595 ( .A(n1512), .B(n1511), .Y(n1513) );
CLKXOR2X2TS U7596 ( .A(n1514), .B(n1513), .Y(n3046) );
INVX2TS U7597 ( .A(n1516), .Y(n1518) );
CLKXOR2X4TS U7598 ( .A(n1520), .B(n1519), .Y(n3243) );
INVX2TS U7599 ( .A(n1521), .Y(n1522) );
NOR2X1TS U7600 ( .A(n1525), .B(n1522), .Y(n1528) );
INVX2TS U7601 ( .A(n1523), .Y(n1526) );
AOI21X4TS U7602 ( .A0(n1529), .A1(n1528), .B0(n1527), .Y(n4060) );
AOI21X4TS U7603 ( .A0(n1128), .A1(n1781), .B0(n1531), .Y(n1791) );
NAND2X1TS U7604 ( .A(n1200), .B(n1540), .Y(n1541) );
XNOR2X4TS U7605 ( .A(n1542), .B(n1541), .Y(n3253) );
INVX2TS U7606 ( .A(n1551), .Y(n1553) );
NAND2X1TS U7607 ( .A(n1553), .B(n1552), .Y(n1554) );
CLKXOR2X4TS U7608 ( .A(n1555), .B(n1554), .Y(n3281) );
XNOR2X4TS U7609 ( .A(n3954), .B(n1558), .Y(n3421) );
INVX2TS U7610 ( .A(n1577), .Y(n1561) );
NAND2X1TS U7611 ( .A(n1561), .B(n1576), .Y(n1563) );
INVX2TS U7612 ( .A(n1562), .Y(n1578) );
NAND2X1TS U7613 ( .A(n1008), .B(n1566), .Y(n1568) );
XNOR2X4TS U7614 ( .A(n1568), .B(n1567), .Y(n3228) );
INVX4TS U7615 ( .A(n1570), .Y(n3282) );
INVX2TS U7616 ( .A(n1571), .Y(n1573) );
NAND2X1TS U7617 ( .A(n1573), .B(n1572), .Y(n1574) );
INVX2TS U7618 ( .A(n1579), .Y(n1581) );
NAND2X1TS U7619 ( .A(n1581), .B(n1580), .Y(n1582) );
XNOR2X4TS U7620 ( .A(n1583), .B(n1582), .Y(n3391) );
INVX2TS U7621 ( .A(n1584), .Y(n1586) );
NAND2X1TS U7622 ( .A(n1586), .B(n1585), .Y(n1587) );
INVX2TS U7623 ( .A(n1590), .Y(n1593) );
INVX2TS U7624 ( .A(n1591), .Y(n1592) );
AOI21X2TS U7625 ( .A0(n1617), .A1(n1593), .B0(n1592), .Y(n1677) );
NAND2X1TS U7626 ( .A(n1598), .B(n1597), .Y(n1599) );
CLKXOR2X4TS U7627 ( .A(n1600), .B(n1599), .Y(n3347) );
NAND2X1TS U7628 ( .A(n1614), .B(n1616), .Y(n1648) );
AOI21X1TS U7629 ( .A0(n1617), .A1(n1616), .B0(n1615), .Y(n1651) );
INVX2TS U7630 ( .A(n1651), .Y(n1618) );
NAND2X1TS U7631 ( .A(n1620), .B(n1649), .Y(n1621) );
INVX2TS U7632 ( .A(n1673), .Y(n1639) );
INVX2TS U7633 ( .A(n1677), .Y(n1638) );
NAND2X1TS U7634 ( .A(n1642), .B(n1641), .Y(n1643) );
CLKXOR2X4TS U7635 ( .A(n1644), .B(n1643), .Y(n3343) );
OAI21X1TS U7636 ( .A0(n1651), .A1(n1650), .B0(n1649), .Y(n1652) );
INVX2TS U7637 ( .A(n1654), .Y(n1656) );
NAND2X1TS U7638 ( .A(n1656), .B(n1655), .Y(n1657) );
CLKXOR2X4TS U7639 ( .A(n1658), .B(n1657), .Y(n3230) );
OAI22X4TS U7640 ( .A0(n1810), .A1(n1949), .B0(n1737), .B1(n1730), .Y(n1693)
);
INVX2TS U7641 ( .A(n1672), .Y(n1676) );
INVX2TS U7642 ( .A(n1674), .Y(n1675) );
NAND2X1TS U7643 ( .A(n999), .B(n1680), .Y(n1681) );
CLKXOR2X4TS U7644 ( .A(n1682), .B(n1681), .Y(n3429) );
INVX2TS U7645 ( .A(n1699), .Y(n1703) );
INVX2TS U7646 ( .A(n1701), .Y(n1702) );
CLKXOR2X4TS U7647 ( .A(n1709), .B(n1708), .Y(n3500) );
INVX2TS U7648 ( .A(n3898), .Y(n1756) );
INVX2TS U7649 ( .A(n3892), .Y(n1942) );
AFHCINX2TS U7650 ( .CIN(n1761), .B(n3374), .A(n1762), .S(n1897), .CO(n1844)
);
AFHCONX2TS U7651 ( .A(n1767), .B(n3046), .CI(n1766), .CON(n1764), .S(n1892)
);
AFHCINX2TS U7652 ( .CIN(n1775), .B(n3243), .A(n1776), .S(n1915), .CO(n1766)
);
CMPR32X2TS U7653 ( .A(n1891), .B(n1786), .C(n1785), .CO(n1795), .S(n1777) );
AFHCONX2TS U7654 ( .A(n1801), .B(n1800), .CI(n3192), .CON(n1761), .S(n1893)
);
CMPR32X2TS U7655 ( .A(n1894), .B(n1833), .C(n1832), .CO(n1851), .S(n1797) );
AFHCINX2TS U7656 ( .CIN(n1837), .B(n3421), .A(n1838), .S(n1905), .CO(n1881)
);
AFHCONX2TS U7657 ( .A(n1845), .B(n1844), .CI(n3391), .CON(n1837), .S(n1898)
);
CMPR32X2TS U7658 ( .A(n1899), .B(n1852), .C(n1851), .CO(n1858), .S(n1834) );
CMPR32X2TS U7659 ( .A(n1892), .B(n1856), .C(n1855), .CO(n1785), .S(n1857) );
AFHCONX2TS U7660 ( .A(n1861), .B(n1860), .CI(n3282), .CON(n1868), .S(n1862)
);
AFHCINX2TS U7661 ( .CIN(n1868), .B(n3228), .A(n1869), .S(n1890), .CO(n1800)
);
AFHCINX2TS U7662 ( .CIN(n1873), .B(n3281), .A(n1874), .S(n1875), .CO(n1863)
);
AFHCONX2TS U7663 ( .A(n1882), .B(n1881), .CI(n3481), .CON(n1873), .S(n1927)
);
CMPR32X2TS U7664 ( .A(n1885), .B(n1884), .C(n1915), .CO(n1855), .S(n1886) );
NOR2X1TS U7665 ( .A(n10239), .B(n2105), .Y(n1988) );
INVX2TS U7666 ( .A(n4300), .Y(n10284) );
CMPR32X2TS U7667 ( .A(n1929), .B(n1928), .C(n1964), .CO(n1885), .S(n1930) );
INVX2TS U7668 ( .A(n4291), .Y(n2156) );
INVX2TS U7669 ( .A(n4292), .Y(n2155) );
INVX2TS U7670 ( .A(n4283), .Y(n2179) );
INVX2TS U7671 ( .A(n4286), .Y(n2166) );
NOR2X1TS U7672 ( .A(n10239), .B(n2170), .Y(n2131) );
INVX2TS U7673 ( .A(n4295), .Y(n2130) );
INVX2TS U7674 ( .A(n4299), .Y(n2136) );
INVX2TS U7675 ( .A(n4301), .Y(n10297) );
INVX2TS U7676 ( .A(n4288), .Y(n2162) );
INVX2TS U7677 ( .A(n5339), .Y(n2177) );
INVX2TS U7678 ( .A(n5340), .Y(n2175) );
INVX2TS U7679 ( .A(n4298), .Y(n2119) );
INVX2TS U7680 ( .A(n4293), .Y(n2150) );
INVX2TS U7681 ( .A(n4289), .Y(n2159) );
INVX2TS U7682 ( .A(n4296), .Y(n2141) );
INVX2TS U7683 ( .A(n5579), .Y(n4418) );
MXI2X4TS U7684 ( .A(DP_OP_338J35_122_4684_n1298), .B(
DP_OP_338J35_122_4684_n1297), .S0(DP_OP_338J35_122_4684_n1303), .Y(
DP_OP_338J35_122_4684_n1286) );
AOI21X4TS U7685 ( .A0(n1036), .A1(n1060), .B0(n2213), .Y(n2314) );
NAND2X1TS U7686 ( .A(Op_MY[24]), .B(Op_MY[10]), .Y(n2233) );
NAND2X1TS U7687 ( .A(Op_MX[16]), .B(Op_MX[2]), .Y(n2461) );
INVX2TS U7688 ( .A(n2461), .Y(n2244) );
AOI21X4TS U7689 ( .A0(n2429), .A1(n2249), .B0(n2248), .Y(n2513) );
NAND2X1TS U7690 ( .A(n1156), .B(n6843), .Y(n2256) );
NOR2X1TS U7691 ( .A(n2347), .B(n2346), .Y(n2811) );
NAND2X1TS U7692 ( .A(n2819), .B(n2818), .Y(n2820) );
NAND2X1TS U7693 ( .A(n2347), .B(n2346), .Y(n2812) );
OAI21X1TS U7694 ( .A0(n2811), .A1(n2820), .B0(n2812), .Y(n2259) );
INVX2TS U7695 ( .A(n2257), .Y(n2255) );
NAND2X1TS U7696 ( .A(n1155), .B(n2257), .Y(n2258) );
INVX2TS U7697 ( .A(n2351), .Y(n2353) );
NOR2X2TS U7698 ( .A(n2380), .B(n2688), .Y(n6547) );
INVX2TS U7699 ( .A(n6547), .Y(n2388) );
NAND2X1TS U7700 ( .A(n1060), .B(n2437), .Y(n2438) );
NOR2X1TS U7701 ( .A(n2605), .B(n2688), .Y(n2468) );
INVX2TS U7702 ( .A(n2841), .Y(n2807) );
NOR2X2TS U7703 ( .A(n2605), .B(n2285), .Y(n6548) );
INVX2TS U7704 ( .A(n6548), .Y(n2802) );
NOR2X2TS U7705 ( .A(n2831), .B(n2285), .Y(n2845) );
INVX2TS U7706 ( .A(n2845), .Y(n2794) );
NOR2X2TS U7707 ( .A(n2876), .B(n2285), .Y(n2849) );
INVX2TS U7708 ( .A(n2849), .Y(n2752) );
NOR2X2TS U7709 ( .A(n2890), .B(n2285), .Y(n2851) );
INVX2TS U7710 ( .A(n2851), .Y(n2755) );
INVX2TS U7711 ( .A(n2479), .Y(n2480) );
NOR2X2TS U7712 ( .A(n9995), .B(n2285), .Y(n2853) );
INVX2TS U7713 ( .A(n2853), .Y(n2772) );
INVX2TS U7714 ( .A(n2850), .Y(n2784) );
NOR2X2TS U7715 ( .A(n2866), .B(n2285), .Y(n2847) );
INVX2TS U7716 ( .A(n2847), .Y(n2789) );
NOR2X2TS U7717 ( .A(n2745), .B(n2285), .Y(n2842) );
INVX2TS U7718 ( .A(n2842), .Y(n2809) );
NOR2X1TS U7719 ( .A(n2380), .B(n2285), .Y(n6977) );
INVX2TS U7720 ( .A(n6977), .Y(n2927) );
INVX2TS U7721 ( .A(n2811), .Y(n2813) );
NAND2X1TS U7722 ( .A(n2813), .B(n2812), .Y(n2814) );
XOR2X1TS U7723 ( .A(n2814), .B(n2820), .Y(n6596) );
NAND2X1TS U7724 ( .A(n6548), .B(n6547), .Y(n6549) );
INVX2TS U7725 ( .A(n6549), .Y(n6551) );
NAND2X1TS U7726 ( .A(n2842), .B(n2841), .Y(n6550) );
INVX2TS U7727 ( .A(n6550), .Y(n2843) );
INVX2TS U7728 ( .A(n6538), .Y(n2848) );
NAND2X1TS U7729 ( .A(n2917), .B(n2899), .Y(n2901) );
CMPR32X2TS U7730 ( .A(n2904), .B(n2903), .C(n2902), .CO(n2821), .S(n6589) );
INVX2TS U7731 ( .A(n2921), .Y(n2906) );
INVX2TS U7732 ( .A(n2909), .Y(n2911) );
CMPR32X2TS U7733 ( .A(n2916), .B(n2915), .C(n2914), .CO(n2902), .S(n6586) );
INVX2TS U7734 ( .A(n2918), .Y(n2919) );
CMPR32X2TS U7735 ( .A(n2927), .B(n2926), .C(n2925), .CO(n2934), .S(n6571) );
CMPR32X2TS U7736 ( .A(n2935), .B(n2934), .C(n2933), .CO(n2949), .S(n6573) );
INVX2TS U7737 ( .A(n2936), .Y(n2941) );
INVX2TS U7738 ( .A(n2940), .Y(n2937) );
INVX2TS U7739 ( .A(n2942), .Y(n2944) );
CMPR32X2TS U7740 ( .A(n2949), .B(n2948), .C(n2947), .CO(n2952), .S(n6575) );
INVX2TS U7741 ( .A(n2956), .Y(n2950) );
CMPR32X2TS U7742 ( .A(n2954), .B(n2953), .C(n2952), .CO(n2963), .S(n6578) );
INVX2TS U7743 ( .A(n2958), .Y(n2960) );
CMPR32X2TS U7744 ( .A(n2965), .B(n2964), .C(n2963), .CO(n2914), .S(n6581) );
XNOR2X2TS U7745 ( .A(Op_MY[48]), .B(Op_MX[48]), .Y(n2966) );
CMPR32X4TS U7746 ( .A(Op_MX[35]), .B(Op_MX[48]), .C(n2969), .CO(n2980), .S(
DP_OP_341J35_125_6458_n267) );
INVX2TS U7747 ( .A(n7490), .Y(n9576) );
AOI22X1TS U7748 ( .A0(n2970), .A1(n7490), .B0(n9576), .B1(n9582), .Y(n9587)
);
CMPR32X4TS U7749 ( .A(Op_MX[37]), .B(Op_MX[50]), .C(n2971), .CO(n2972), .S(
n9637) );
INVX2TS U7750 ( .A(n9523), .Y(n7478) );
AOI22X1TS U7751 ( .A0(n9637), .A1(n7478), .B0(n9523), .B1(n9592), .Y(n2973)
);
OAI221X4TS U7752 ( .A0(n9523), .A1(n9582), .B0(n7478), .B1(n2970), .C0(n9588), .Y(n9586) );
AOI22X1TS U7753 ( .A0(n2970), .A1(n7486), .B0(n9660), .B1(n9582), .Y(n2975)
);
OAI22X1TS U7754 ( .A0(n9587), .A1(n9588), .B0(n9586), .B1(n2975), .Y(n2999)
);
CLKXOR2X2TS U7755 ( .A(Op_MY[39]), .B(n7434), .Y(n9590) );
INVX2TS U7756 ( .A(n9590), .Y(n9644) );
AOI22X1TS U7757 ( .A0(n9590), .A1(DP_OP_341J35_125_6458_n267), .B0(
DP_OP_341J35_125_6458_n262), .B1(n9644), .Y(n2979) );
OAI32X1TS U7758 ( .A0(n9636), .A1(n9593), .A2(DP_OP_341J35_125_6458_n262),
.B0(n2979), .B1(n9634), .Y(n2998) );
INVX2TS U7759 ( .A(n9555), .Y(n9638) );
AOI22X1TS U7760 ( .A0(DP_OP_341J35_125_6458_n267), .A1(n9638), .B0(n9555),
.B1(DP_OP_341J35_125_6458_n262), .Y(n2981) );
INVX2TS U7761 ( .A(n9584), .Y(n9583) );
AOI22X1TS U7762 ( .A0(n9637), .A1(n9583), .B0(n9584), .B1(n9592), .Y(n2993)
);
OAI221X4TS U7763 ( .A0(n9555), .A1(n9637), .B0(n9638), .B1(n9592), .C0(n9599), .Y(n9597) );
AOI22X1TS U7764 ( .A0(n9637), .A1(n9576), .B0(n7490), .B1(n9592), .Y(n2987)
);
OAI22X1TS U7765 ( .A0(n9599), .A1(n2993), .B0(n9597), .B1(n2987), .Y(n2995)
);
INVX2TS U7766 ( .A(n9593), .Y(n9594) );
AOI22X1TS U7767 ( .A0(n9593), .A1(DP_OP_341J35_125_6458_n262), .B0(
DP_OP_341J35_125_6458_n267), .B1(n9594), .Y(n2984) );
OAI32X1TS U7768 ( .A0(n9636), .A1(n9580), .A2(DP_OP_341J35_125_6458_n262),
.B0(n2984), .B1(n9634), .Y(n2994) );
INVX2TS U7769 ( .A(n9580), .Y(n9579) );
AOI22X1TS U7770 ( .A0(n9580), .A1(DP_OP_341J35_125_6458_n262), .B0(
DP_OP_341J35_125_6458_n267), .B1(n9579), .Y(n2985) );
OAI32X1TS U7771 ( .A0(n9636), .A1(n9584), .A2(DP_OP_341J35_125_6458_n262),
.B0(n2985), .B1(n9634), .Y(n2992) );
AOI22X1TS U7772 ( .A0(n7486), .A1(n9592), .B0(n9637), .B1(n9660), .Y(n2986)
);
OAI22X1TS U7773 ( .A0(n9599), .A1(n2987), .B0(n9597), .B1(n2986), .Y(n2991)
);
AOI22X1TS U7774 ( .A0(n9584), .A1(DP_OP_341J35_125_6458_n262), .B0(
DP_OP_341J35_125_6458_n267), .B1(n9583), .Y(n2988) );
OAI32X1TS U7775 ( .A0(n9636), .A1(n7490), .A2(DP_OP_341J35_125_6458_n262),
.B0(n2988), .B1(n9634), .Y(n3009) );
AOI21X1TS U7776 ( .A0(n7486), .A1(n9636), .B0(DP_OP_341J35_125_6458_n262),
.Y(n3002) );
NAND2X1TS U7777 ( .A(DP_OP_341J35_125_6458_n267), .B(n9634), .Y(n2990) );
AOI22X1TS U7778 ( .A0(n7490), .A1(DP_OP_341J35_125_6458_n262), .B0(
DP_OP_341J35_125_6458_n267), .B1(n9576), .Y(n2989) );
OAI22X1TS U7779 ( .A0(n7486), .A1(n2990), .B0(n2989), .B1(n9634), .Y(n3001)
);
AOI22X1TS U7780 ( .A0(n9637), .A1(n9579), .B0(n9580), .B1(n9592), .Y(n9596)
);
OAI22X1TS U7781 ( .A0(n9599), .A1(n9596), .B0(n9597), .B1(n2993), .Y(n9676)
);
CMPR32X2TS U7782 ( .A(n2996), .B(n2995), .C(n2994), .CO(n9675), .S(n3015) );
CMPR32X2TS U7783 ( .A(n2999), .B(n2998), .C(n2997), .CO(n3020), .S(n3016) );
CMPR32X2TS U7784 ( .A(DP_OP_341J35_125_6458_n270), .B(
DP_OP_341J35_125_6458_n272), .C(n3000), .CO(n7481), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[7]) );
ADDHX1TS U7785 ( .A(n3002), .B(n3001), .CO(n3007), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[1]) );
AOI21X1TS U7786 ( .A0(n7487), .A1(n9659), .B0(DP_OP_341J35_125_6458_n466),
.Y(n7472) );
NAND2X1TS U7787 ( .A(n2968), .B(n3003), .Y(n3006) );
INVX2TS U7788 ( .A(n7491), .Y(n9600) );
AOI22X1TS U7789 ( .A0(n2968), .A1(n9600), .B0(n7491), .B1(
DP_OP_341J35_125_6458_n466), .Y(n3005) );
OAI22X1TS U7790 ( .A0(n7487), .A1(n3006), .B0(n3005), .B1(n3003), .Y(n7471)
);
CMPR32X2TS U7791 ( .A(n3018), .B(n3017), .C(n3016), .CO(n3019), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[5]) );
CMPR32X2TS U7792 ( .A(DP_OP_341J35_125_6458_n273), .B(n3020), .C(n3019),
.CO(n3000), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[6]) );
INVX2TS U7793 ( .A(n7487), .Y(n9648) );
XOR2X1TS U7794 ( .A(n3047), .B(n3201), .Y(n3021) );
XNOR2X1TS U7795 ( .A(n3429), .B(n908), .Y(n3174) );
XNOR2X4TS U7796 ( .A(n3063), .B(n904), .Y(n3501) );
XNOR2X1TS U7797 ( .A(n3429), .B(n752), .Y(n3124) );
NAND2X2TS U7798 ( .A(n3253), .B(n3280), .Y(n3255) );
XNOR2X1TS U7799 ( .A(n3500), .B(n752), .Y(n3024) );
XNOR2X1TS U7800 ( .A(n3230), .B(n904), .Y(n3025) );
XNOR2X1TS U7801 ( .A(n3241), .B(n904), .Y(n3126) );
XOR2X1TS U7802 ( .A(n904), .B(n3052), .Y(n3022) );
INVX2TS U7803 ( .A(n3241), .Y(n3173) );
OAI22X1TS U7804 ( .A0(n3023), .A1(n3557), .B0(n3173), .B1(n3501), .Y(n3177)
);
OAI22X1TS U7805 ( .A0(n3024), .A1(n3255), .B0(n3432), .B1(n3280), .Y(n3176)
);
XNOR2X1TS U7806 ( .A(n3343), .B(n904), .Y(n3172) );
OAI22X1TS U7807 ( .A0(n3025), .A1(n3499), .B0(n3172), .B1(n877), .Y(n3175)
);
NOR2BX1TS U7808 ( .AN(n3282), .B(n878), .Y(n3035) );
XOR2X1TS U7809 ( .A(n753), .B(n3046), .Y(n3026) );
NAND2X4TS U7810 ( .A(n3026), .B(n899), .Y(n3390) );
XNOR2X1TS U7811 ( .A(n3228), .B(n753), .Y(n3029) );
XNOR2X1TS U7812 ( .A(n753), .B(n3282), .Y(n3028) );
INVX2TS U7813 ( .A(n3711), .Y(n3195) );
XNOR2X2TS U7814 ( .A(n3391), .B(n3243), .Y(n3128) );
XNOR2X2TS U7815 ( .A(n3374), .B(n3243), .Y(n3193) );
NAND2X4TS U7816 ( .A(n3243), .B(n1449), .Y(n3245) );
INVX2TS U7817 ( .A(n3712), .Y(n3194) );
XOR2X1TS U7818 ( .A(n900), .B(n3051), .Y(n3030) );
NAND2X4TS U7819 ( .A(n3030), .B(n878), .Y(n3480) );
NAND2BXLTS U7820 ( .AN(n3282), .B(n900), .Y(n3031) );
OAI22X1TS U7821 ( .A0(n3480), .A1(n3479), .B0(n3031), .B1(n878), .Y(n3038)
);
OAI22X1TS U7822 ( .A0(n3040), .A1(n899), .B0(n3036), .B1(n3390), .Y(n3041)
);
INVX2TS U7823 ( .A(n3713), .Y(n3129) );
XNOR2X4TS U7824 ( .A(n3097), .B(n900), .Y(n3483) );
INVX2TS U7825 ( .A(n3082), .Y(n3085) );
INVX2TS U7826 ( .A(n3084), .Y(n3045) );
NAND2X1TS U7827 ( .A(n1052), .B(n1137), .Y(n3050) );
NAND2X1TS U7828 ( .A(n3047), .B(n3046), .Y(n3069) );
INVX2TS U7829 ( .A(n3069), .Y(n3073) );
INVX2TS U7830 ( .A(n3075), .Y(n3048) );
NOR2X2TS U7831 ( .A(n3052), .B(n3051), .Y(n3091) );
NAND2X1TS U7832 ( .A(n3052), .B(n3051), .Y(n3092) );
OAI21X1TS U7833 ( .A0(n3095), .A1(n3091), .B0(n3092), .Y(n3055) );
INVX2TS U7834 ( .A(n3059), .Y(n3053) );
NAND2X1TS U7835 ( .A(n3053), .B(n3058), .Y(n3054) );
INVX2TS U7836 ( .A(n3089), .Y(n3064) );
NAND2X1TS U7837 ( .A(n3063), .B(n3097), .Y(n3088) );
NAND2X1TS U7838 ( .A(n3064), .B(n3088), .Y(n3065) );
INVX2TS U7839 ( .A(n3067), .Y(n3447) );
INVX2TS U7840 ( .A(n3068), .Y(n3074) );
NAND2X1TS U7841 ( .A(n1052), .B(n3069), .Y(n3070) );
NAND2X4TS U7842 ( .A(n977), .B(n3082), .Y(n3278) );
OAI22X1TS U7843 ( .A0(n3581), .A1(n3278), .B0(n3559), .B1(n3257), .Y(n3171)
);
INVX2TS U7844 ( .A(n3091), .Y(n3093) );
NAND2X1TS U7845 ( .A(n3093), .B(n3092), .Y(n3094) );
XOR2X1TS U7846 ( .A(n3095), .B(n3094), .Y(n3096) );
INVX2TS U7847 ( .A(n3228), .Y(n3118) );
XNOR2X1TS U7848 ( .A(n3374), .B(n900), .Y(n3119) );
OAI22X1TS U7849 ( .A0(n3119), .A1(n878), .B0(n3101), .B1(n3480), .Y(n3115)
);
INVX2TS U7850 ( .A(n3719), .Y(n3114) );
INVX2TS U7851 ( .A(n3108), .Y(n3364) );
OAI22X1TS U7852 ( .A0(n3364), .A1(n3446), .B0(n3354), .B1(n3478), .Y(n3112)
);
OAI22X1TS U7853 ( .A0(n3548), .A1(n3350), .B0(n3484), .B1(n3398), .Y(n3382)
);
OAI22X1TS U7854 ( .A0(n3364), .A1(n3478), .B0(n3354), .B1(n3560), .Y(n3357)
);
INVX2TS U7855 ( .A(n3425), .Y(n3395) );
INVX2TS U7856 ( .A(n3192), .Y(n3375) );
XNOR2X1TS U7857 ( .A(n3391), .B(n900), .Y(n3373) );
OAI22X1TS U7858 ( .A0(n3373), .A1(n878), .B0(n3119), .B1(n3480), .Y(n3376)
);
INVX2TS U7859 ( .A(n3721), .Y(n3356) );
OAI22X1TS U7860 ( .A0(n3497), .A1(n3398), .B0(n3427), .B1(n3446), .Y(n3355)
);
XNOR2X1TS U7861 ( .A(n3230), .B(n908), .Y(n3199) );
XNOR2X1TS U7862 ( .A(n3347), .B(n752), .Y(n3207) );
NAND2BXLTS U7863 ( .AN(n3281), .B(n904), .Y(n3125) );
XNOR2X1TS U7864 ( .A(n3281), .B(n904), .Y(n3127) );
XNOR2X2TS U7865 ( .A(n3421), .B(n3243), .Y(n3134) );
OAI22X2TS U7866 ( .A0(n3134), .A1(n1449), .B0(n3128), .B1(n3245), .Y(n3714)
);
INVX2TS U7867 ( .A(n3714), .Y(n3146) );
INVX2TS U7868 ( .A(n3717), .Y(n3140) );
OAI22X2TS U7869 ( .A0(n3141), .A1(n3245), .B0(n3425), .B1(n1449), .Y(n3718)
);
INVX2TS U7870 ( .A(n3718), .Y(n3165) );
INVX2TS U7871 ( .A(n3602), .Y(n3220) );
INVX2TS U7872 ( .A(n3720), .Y(n3381) );
XNOR2X1TS U7873 ( .A(n3347), .B(n904), .Y(n3368) );
OAI22X1TS U7874 ( .A0(n3368), .A1(n877), .B0(n3172), .B1(n3499), .Y(n3408)
);
OAI22X1TS U7875 ( .A0(n3344), .A1(n3501), .B0(n3173), .B1(n3557), .Y(n3372)
);
OAI22X1TS U7876 ( .A0(n3174), .A1(n3346), .B0(n3342), .B1(n879), .Y(n3371)
);
INVX2TS U7877 ( .A(n3636), .Y(n3457) );
INVX2TS U7878 ( .A(n3605), .Y(n3189) );
INVX2TS U7879 ( .A(n3708), .Y(n3227) );
XNOR2X2TS U7880 ( .A(n3192), .B(n3243), .Y(n3229) );
OAI22X2TS U7881 ( .A0(n3193), .A1(n1449), .B0(n3229), .B1(n3245), .Y(n3709)
);
NOR2BX1TS U7882 ( .AN(n3281), .B(n877), .Y(n3303) );
XNOR2X1TS U7883 ( .A(n3241), .B(n908), .Y(n3202) );
NAND2BXLTS U7884 ( .AN(n3281), .B(n908), .Y(n3200) );
XNOR2X1TS U7885 ( .A(n3281), .B(n3201), .Y(n3203) );
INVX2TS U7886 ( .A(n3599), .Y(n3317) );
XNOR2X2TS U7887 ( .A(n3343), .B(n752), .Y(n3231) );
OAI22X2TS U7888 ( .A0(n3207), .A1(n3280), .B0(n3231), .B1(n3255), .Y(n3597)
);
INVX2TS U7889 ( .A(n3597), .Y(n3309) );
NOR2BX1TS U7890 ( .AN(n3282), .B(n899), .Y(n4328) );
INVX2TS U7891 ( .A(n4328), .Y(n3249) );
XNOR2X2TS U7892 ( .A(n3228), .B(n3243), .Y(n3246) );
OAI22X2TS U7893 ( .A0(n3229), .A1(n1449), .B0(n3246), .B1(n3245), .Y(n4327)
);
INVX2TS U7894 ( .A(n4327), .Y(n3248) );
NOR2BX2TS U7895 ( .AN(n3281), .B(n879), .Y(n3592) );
INVX2TS U7896 ( .A(n3592), .Y(n3247) );
XNOR2X2TS U7897 ( .A(n3230), .B(n752), .Y(n3242) );
OAI22X2TS U7898 ( .A0(n3242), .A1(n3255), .B0(n3231), .B1(n3280), .Y(n3594)
);
INVX2TS U7899 ( .A(n3594), .Y(n3265) );
XNOR2X2TS U7900 ( .A(n3241), .B(n3253), .Y(n3252) );
OAI22X2TS U7901 ( .A0(n3242), .A1(n3280), .B0(n3252), .B1(n3255), .Y(n3593)
);
NAND2BXLTS U7902 ( .AN(n3282), .B(n3243), .Y(n3244) );
NAND2X1TS U7903 ( .A(n3245), .B(n3244), .Y(n4333) );
INVX2TS U7904 ( .A(n4333), .Y(n3277) );
OAI22X2TS U7905 ( .A0(n3246), .A1(n1449), .B0(n3282), .B1(n3245), .Y(n4334)
);
INVX2TS U7906 ( .A(n4334), .Y(n3276) );
INVX2TS U7907 ( .A(n3593), .Y(n3306) );
INVX2TS U7908 ( .A(n3595), .Y(n3305) );
OAI22X1TS U7909 ( .A0(n3364), .A1(n3278), .B0(n3354), .B1(n3257), .Y(n3304)
);
OAI22X2TS U7910 ( .A0(n3281), .A1(n3255), .B0(n3252), .B1(n3280), .Y(n3697)
);
NAND2X1TS U7911 ( .A(n3255), .B(n3254), .Y(n3696) );
INVX2TS U7912 ( .A(n3696), .Y(n3274) );
OAI22X1TS U7913 ( .A0(n3258), .A1(n3278), .B0(n3279), .B1(n3257), .Y(n3273)
);
INVX2TS U7914 ( .A(n3697), .Y(n3263) );
NOR2BX2TS U7915 ( .AN(n3281), .B(n3280), .Y(n3818) );
INVX2TS U7916 ( .A(n3818), .Y(n3755) );
INVX2TS U7917 ( .A(n3756), .Y(n3283) );
INVX2TS U7918 ( .A(n3741), .Y(n3286) );
INVX2TS U7919 ( .A(n3598), .Y(n3314) );
INVX2TS U7920 ( .A(n3780), .Y(n3326) );
XNOR2X1TS U7921 ( .A(n3429), .B(n904), .Y(n3367) );
XNOR2X1TS U7922 ( .A(n3500), .B(n904), .Y(n3428) );
OAI22X1TS U7923 ( .A0(n3367), .A1(n3499), .B0(n3428), .B1(n877), .Y(n3436)
);
OAI22X1TS U7924 ( .A0(n3344), .A1(n3557), .B0(n3348), .B1(n3501), .Y(n3369)
);
OAI22X1TS U7925 ( .A0(n3430), .A1(n3501), .B0(n3348), .B1(n3557), .Y(n3431)
);
OAI22X1TS U7926 ( .A0(n3581), .A1(n3350), .B0(n3559), .B1(n3398), .Y(n3365)
);
INVX2TS U7927 ( .A(n3724), .Y(n3363) );
OAI22X1TS U7928 ( .A0(n3497), .A1(n3446), .B0(n3427), .B1(n3478), .Y(n3361)
);
OAI22X1TS U7929 ( .A0(n3497), .A1(n3478), .B0(n3427), .B1(n3560), .Y(n3448)
);
OAI22X1TS U7930 ( .A0(n3368), .A1(n3499), .B0(n3367), .B1(n877), .Y(n3402)
);
INVX2TS U7931 ( .A(n3651), .Y(n3439) );
XNOR2X1TS U7932 ( .A(n3421), .B(n900), .Y(n3397) );
OAI22X1TS U7933 ( .A0(n3397), .A1(n878), .B0(n3373), .B1(n3480), .Y(n3387)
);
INVX2TS U7934 ( .A(n3374), .Y(n3392) );
OAI22X1TS U7935 ( .A0(n3378), .A1(n3390), .B0(n899), .B1(n3388), .Y(n3385)
);
INVX2TS U7936 ( .A(n3725), .Y(n3405) );
INVX2TS U7937 ( .A(n3726), .Y(n3442) );
INVX2TS U7938 ( .A(n3391), .Y(n3422) );
OAI22X1TS U7939 ( .A0(n3422), .A1(n3483), .B0(n3392), .B1(n3555), .Y(n3423)
);
XNOR2X1TS U7940 ( .A(n3481), .B(n900), .Y(n3426) );
INVX2TS U7941 ( .A(n3727), .Y(n3441) );
OAI22X1TS U7942 ( .A0(n3548), .A1(n3446), .B0(n3484), .B1(n3478), .Y(n3443)
);
INVX2TS U7943 ( .A(n3646), .Y(n3462) );
INVX2TS U7944 ( .A(n3647), .Y(n3460) );
INVX2TS U7945 ( .A(n3730), .Y(n3493) );
INVX2TS U7946 ( .A(n3421), .Y(n3482) );
OAI22X1TS U7947 ( .A0(n3482), .A1(n3483), .B0(n3422), .B1(n3555), .Y(n3496)
);
INVX2TS U7948 ( .A(n3546), .Y(n3495) );
OAI22X1TS U7949 ( .A0(n3426), .A1(n3480), .B0(n3479), .B1(n878), .Y(n3494)
);
INVX2TS U7950 ( .A(n3731), .Y(n3492) );
OAI22X1TS U7951 ( .A0(n3428), .A1(n3499), .B0(n3498), .B1(n877), .Y(n3549)
);
INVX2TS U7952 ( .A(n3549), .Y(n3487) );
INVX2TS U7953 ( .A(n3671), .Y(n3489) );
INVX2TS U7954 ( .A(n3672), .Y(n3488) );
OAI22X1TS U7955 ( .A0(n3581), .A1(n3446), .B0(n3559), .B1(n3478), .Y(n3477)
);
OAI22X1TS U7956 ( .A0(n3548), .A1(n3478), .B0(n3484), .B1(n3560), .Y(n3475)
);
OAI22X1TS U7957 ( .A0(n3581), .A1(n3478), .B0(n3559), .B1(n3560), .Y(n3563)
);
AO21XLTS U7958 ( .A0(n3480), .A1(n878), .B0(n3479), .Y(n3547) );
OAI22X1TS U7959 ( .A0(n3556), .A1(n3483), .B0(n3482), .B1(n3555), .Y(n3545)
);
INVX2TS U7960 ( .A(n3787), .Y(n3562) );
OAI22X1TS U7961 ( .A0(n3548), .A1(n3560), .B0(n3484), .B1(n805), .Y(n3561)
);
INVX2TS U7962 ( .A(n3676), .Y(n3552) );
INVX2TS U7963 ( .A(n3788), .Y(n3566) );
INVX2TS U7964 ( .A(n3500), .Y(n3558) );
INVX2TS U7965 ( .A(n3675), .Y(n3564) );
INVX2TS U7966 ( .A(n3811), .Y(n3584) );
INVX2TS U7967 ( .A(n3885), .Y(n3582) );
NOR2X1TS U7968 ( .A(n3556), .B(n3555), .Y(n3579) );
OAI22X1TS U7969 ( .A0(n3581), .A1(n3560), .B0(n3559), .B1(n805), .Y(n3578)
);
INVX2TS U7970 ( .A(n3608), .Y(n3618) );
INVX2TS U7971 ( .A(n3579), .Y(n3810) );
INVX2TS U7972 ( .A(n3580), .Y(n3884) );
NOR2X2TS U7973 ( .A(n3602), .B(n3601), .Y(n3611) );
NOR2X2TS U7974 ( .A(n3600), .B(n3599), .Y(n3846) );
NAND2X1TS U7975 ( .A(n3697), .B(n3696), .Y(n3830) );
NAND2X1TS U7976 ( .A(n3593), .B(n3592), .Y(n3828) );
INVX2TS U7977 ( .A(n3687), .Y(n3596) );
NAND2X1TS U7978 ( .A(n3602), .B(n3601), .Y(n3612) );
INVX2TS U7979 ( .A(n3670), .Y(n3656) );
INVX2TS U7980 ( .A(n3641), .Y(n3635) );
NAND2X1TS U7981 ( .A(n3635), .B(n3644), .Y(n3607) );
INVX2TS U7982 ( .A(n3610), .Y(n3850) );
INVX2TS U7983 ( .A(n3611), .Y(n3613) );
NOR2X4TS U7984 ( .A(n5223), .B(n5234), .Y(n5431) );
INVX2TS U7985 ( .A(n3616), .Y(n3617) );
XOR2X1TS U7986 ( .A(n3628), .B(n3627), .Y(n3629) );
NAND2X1TS U7987 ( .A(n3630), .B(n3629), .Y(n3631) );
NAND2X1TS U7988 ( .A(n835), .B(n3631), .Y(n3632) );
INVX2TS U7989 ( .A(n3644), .Y(n3634) );
AOI21X1TS U7990 ( .A0(n3656), .A1(n3635), .B0(n3634), .Y(n3640) );
NOR2X2TS U7991 ( .A(n3637), .B(n3636), .Y(n3645) );
INVX2TS U7992 ( .A(n3645), .Y(n3638) );
NAND2X1TS U7993 ( .A(n3637), .B(n3636), .Y(n3643) );
NAND2X1TS U7994 ( .A(n3638), .B(n3643), .Y(n3639) );
NOR2X2TS U7995 ( .A(n3641), .B(n3645), .Y(n3661) );
INVX2TS U7996 ( .A(n3661), .Y(n3642) );
NOR2X2TS U7997 ( .A(n3647), .B(n3646), .Y(n3660) );
OAI21X2TS U7998 ( .A0(n3645), .A1(n3644), .B0(n3643), .Y(n3667) );
INVX2TS U7999 ( .A(n3667), .Y(n3648) );
AOI21X1TS U8000 ( .A0(n3656), .A1(n3650), .B0(n3649), .Y(n3655) );
NOR2X2TS U8001 ( .A(n3652), .B(n3651), .Y(n3664) );
INVX2TS U8002 ( .A(n3664), .Y(n3653) );
NAND2X1TS U8003 ( .A(n3652), .B(n3651), .Y(n3662) );
NAND2X1TS U8004 ( .A(n3653), .B(n3662), .Y(n3654) );
AOI21X1TS U8005 ( .A0(n3656), .A1(n3661), .B0(n3667), .Y(n3659) );
NAND2X1TS U8006 ( .A(n3657), .B(n3663), .Y(n3658) );
NAND2X1TS U8007 ( .A(n3661), .B(n3666), .Y(n3669) );
AOI21X1TS U8008 ( .A0(n3667), .A1(n3666), .B0(n3665), .Y(n3668) );
OAI21X2TS U8009 ( .A0(n3670), .A1(n3669), .B0(n3668), .Y(n3883) );
NAND2X1TS U8010 ( .A(n3672), .B(n3671), .Y(n3674) );
NAND2X1TS U8011 ( .A(n1152), .B(n3674), .Y(n3673) );
XNOR2X1TS U8012 ( .A(n3883), .B(n3673), .Y(n5425) );
INVX2TS U8013 ( .A(n3674), .Y(n3882) );
AOI21X1TS U8014 ( .A0(n3883), .A1(n1152), .B0(n3882), .Y(n3678) );
NAND2X1TS U8015 ( .A(n3676), .B(n3675), .Y(n3880) );
NAND2X1TS U8016 ( .A(n1163), .B(n3880), .Y(n3677) );
INVX2TS U8017 ( .A(n3824), .Y(n3681) );
INVX2TS U8018 ( .A(n3682), .Y(n3684) );
NAND2X1TS U8019 ( .A(n928), .B(n3687), .Y(n3688) );
NAND2X1TS U8020 ( .A(n949), .B(n1061), .Y(n3823) );
INVX2TS U8021 ( .A(n4342), .Y(n3710) );
INVX2TS U8022 ( .A(n5318), .Y(n3715) );
AOI21X2TS U8023 ( .A0(n5319), .A1(n918), .B0(n3715), .Y(n5313) );
INVX2TS U8024 ( .A(n3800), .Y(n3729) );
NAND2X1TS U8025 ( .A(n3727), .B(n3726), .Y(n3771) );
INVX2TS U8026 ( .A(n3806), .Y(n3728) );
INVX2TS U8027 ( .A(n3799), .Y(n3784) );
INVX2TS U8028 ( .A(n3734), .Y(n3736) );
INVX2TS U8029 ( .A(n3769), .Y(n3739) );
INVX2TS U8030 ( .A(n3743), .Y(n3753) );
INVX2TS U8031 ( .A(n3744), .Y(n3746) );
INVX2TS U8032 ( .A(n3749), .Y(n3751) );
NAND2X1TS U8033 ( .A(n3751), .B(n3750), .Y(n3752) );
NAND2X1TS U8034 ( .A(n950), .B(n3756), .Y(n3758) );
XNOR2X1TS U8035 ( .A(n3758), .B(n3757), .Y(n5301) );
INVX2TS U8036 ( .A(n5295), .Y(n3761) );
INVX2TS U8037 ( .A(n5293), .Y(n3764) );
NAND2X1TS U8038 ( .A(n3800), .B(n3784), .Y(n3786) );
INVX2TS U8039 ( .A(n3802), .Y(n3783) );
NOR2X2TS U8040 ( .A(n3788), .B(n3787), .Y(n3803) );
INVX2TS U8041 ( .A(n3803), .Y(n3789) );
NAND2X1TS U8042 ( .A(n3789), .B(n3801), .Y(n3790) );
OAI21X1TS U8043 ( .A0(n3803), .A1(n3802), .B0(n3801), .Y(n3804) );
NAND2X1TS U8044 ( .A(n3811), .B(n3810), .Y(n3812) );
NAND2X1TS U8045 ( .A(n1110), .B(n3812), .Y(n3813) );
INVX2TS U8046 ( .A(n5275), .Y(n3821) );
INVX2TS U8047 ( .A(n3827), .Y(n3829) );
NAND2X1TS U8048 ( .A(n3829), .B(n3828), .Y(n3831) );
XOR2X1TS U8049 ( .A(n3831), .B(n3830), .Y(n3832) );
INVX2TS U8050 ( .A(n5267), .Y(n3834) );
OAI21X2TS U8051 ( .A0(n5259), .A1(n5262), .B0(n5260), .Y(n5238) );
INVX2TS U8052 ( .A(n3852), .Y(n3837) );
INVX2TS U8053 ( .A(n3851), .Y(n3838) );
INVX2TS U8054 ( .A(n3841), .Y(n3843) );
INVX2TS U8055 ( .A(n3846), .Y(n3848) );
NAND2X1TS U8056 ( .A(n3848), .B(n3847), .Y(n3849) );
INVX2TS U8057 ( .A(n3854), .Y(n3856) );
INVX2TS U8058 ( .A(n3859), .Y(n3861) );
NAND2X1TS U8059 ( .A(n3861), .B(n3860), .Y(n3863) );
AOI21X4TS U8060 ( .A0(n5238), .A1(n3869), .B0(n3868), .Y(n5438) );
OAI21X4TS U8061 ( .A0(n5223), .A1(n5235), .B0(n5224), .Y(n5436) );
AOI21X1TS U8062 ( .A0(n5436), .A1(n3877), .B0(n3876), .Y(n3878) );
INVX2TS U8063 ( .A(n3880), .Y(n3881) );
AOI21X1TS U8064 ( .A0(n3883), .A1(n970), .B0(n969), .Y(n3888) );
NAND2X1TS U8065 ( .A(n3885), .B(n3884), .Y(n3886) );
INVX2TS U8066 ( .A(n8946), .Y(n5447) );
NAND2X1TS U8067 ( .A(n4851), .B(n4850), .Y(n4852) );
INVX2TS U8068 ( .A(n4852), .Y(n4846) );
INVX2TS U8069 ( .A(n4879), .Y(n3894) );
INVX2TS U8070 ( .A(n4877), .Y(n3897) );
INVX2TS U8071 ( .A(n5125), .Y(n3907) );
INVX2TS U8072 ( .A(n5122), .Y(n3910) );
INVX2TS U8073 ( .A(n3913), .Y(n3915) );
CMPR32X2TS U8074 ( .A(n3920), .B(n3919), .C(n3918), .CO(n5029), .S(n5385) );
NAND2X1TS U8075 ( .A(n3925), .B(n3924), .Y(n3926) );
NAND2X1TS U8076 ( .A(n3928), .B(n3934), .Y(n3929) );
INVX2TS U8077 ( .A(n3932), .Y(n3948) );
INVX2TS U8078 ( .A(n3933), .Y(n3951) );
NAND2X1TS U8079 ( .A(n1118), .B(n3938), .Y(n3939) );
CLKXOR2X2TS U8080 ( .A(n3940), .B(n3939), .Y(n4124) );
INVX2TS U8081 ( .A(n3961), .Y(n3942) );
INVX2TS U8082 ( .A(n3965), .Y(n3941) );
AOI21X1TS U8083 ( .A0(n3954), .A1(n3953), .B0(n3952), .Y(n3959) );
NAND2X1TS U8084 ( .A(n3957), .B(n3956), .Y(n3958) );
CLKXOR2X2TS U8085 ( .A(n3959), .B(n3958), .Y(n4137) );
NAND2X1TS U8086 ( .A(n1120), .B(n3968), .Y(n3969) );
NAND2X1TS U8087 ( .A(n1111), .B(n3971), .Y(n3972) );
NAND2X1TS U8088 ( .A(n1028), .B(n3977), .Y(n3978) );
AOI21X1TS U8089 ( .A0(n4014), .A1(n1111), .B0(n3985), .Y(n3988) );
NAND2X1TS U8090 ( .A(n827), .B(n3986), .Y(n3987) );
AOI21X1TS U8091 ( .A0(n3992), .A1(n1126), .B0(n3991), .Y(n3995) );
NAND2X1TS U8092 ( .A(n1114), .B(n3993), .Y(n3994) );
INVX2TS U8093 ( .A(n4010), .Y(n4013) );
INVX2TS U8094 ( .A(n4011), .Y(n4012) );
AOI21X1TS U8095 ( .A0(n4014), .A1(n4013), .B0(n4012), .Y(n4019) );
INVX2TS U8096 ( .A(n4015), .Y(n4017) );
NAND2X1TS U8097 ( .A(n4017), .B(n4016), .Y(n4018) );
NAND2X1TS U8098 ( .A(n4022), .B(n4021), .Y(n4023) );
NAND2X1TS U8099 ( .A(n1126), .B(n4031), .Y(n4032) );
INVX2TS U8100 ( .A(n4056), .Y(n4058) );
NAND2X1TS U8101 ( .A(n4058), .B(n4057), .Y(n4059) );
INVX2TS U8102 ( .A(n4331), .Y(n4338) );
INVX2TS U8103 ( .A(n4337), .Y(n4078) );
INVX2TS U8104 ( .A(n4340), .Y(n4079) );
INVX2TS U8105 ( .A(n4506), .Y(n4106) );
INVX2TS U8106 ( .A(n4109), .Y(n4461) );
INVX2TS U8107 ( .A(n4126), .Y(n4628) );
NAND2X1TS U8108 ( .A(n1143), .B(n4144), .Y(n4133) );
INVX2TS U8109 ( .A(n4130), .Y(n4131) );
INVX2TS U8110 ( .A(n4193), .Y(n4143) );
INVX2TS U8111 ( .A(n4804), .Y(n4156) );
INVX2TS U8112 ( .A(n4810), .Y(n4152) );
INVX2TS U8113 ( .A(n4811), .Y(n4222) );
INVX2TS U8114 ( .A(n4795), .Y(n4181) );
INVX2TS U8115 ( .A(n4829), .Y(n4180) );
INVX2TS U8116 ( .A(n4169), .Y(n4214) );
INVX2TS U8117 ( .A(n4174), .Y(n4209) );
INVX2TS U8118 ( .A(n4329), .Y(n4220) );
INVX2TS U8119 ( .A(n4330), .Y(n4218) );
INVX2TS U8120 ( .A(n4178), .Y(n4212) );
INVX2TS U8121 ( .A(n4179), .Y(n4472) );
INVX2TS U8122 ( .A(DP_OP_338J35_122_4684_n1465), .Y(n4491) );
INVX2TS U8123 ( .A(n4199), .Y(n4207) );
INVX2TS U8124 ( .A(n4260), .Y(n4226) );
INVX2TS U8125 ( .A(n4235), .Y(n4231) );
INVX2TS U8126 ( .A(n4503), .Y(n4233) );
XOR2X1TS U8127 ( .A(n4577), .B(n4234), .Y(n4392) );
INVX2TS U8128 ( .A(n4239), .Y(n4241) );
INVX2TS U8129 ( .A(n4244), .Y(n4246) );
XOR2X1TS U8130 ( .A(n4248), .B(n4247), .Y(n4415) );
CMPR32X2TS U8131 ( .A(n4256), .B(n4255), .C(n4254), .CO(n4260), .S(n4320) );
INVX2TS U8132 ( .A(n5329), .Y(n4287) );
INVX2TS U8133 ( .A(n5324), .Y(n4290) );
INVX2TS U8134 ( .A(n4435), .Y(n4318) );
AFHCINX2TS U8135 ( .CIN(n4335), .B(n4327), .A(n4328), .S(n9042), .CO(n4343)
);
INVX2TS U8136 ( .A(n9042), .Y(n5338) );
NAND2X1TS U8137 ( .A(n1138), .B(n4342), .Y(n4344) );
XNOR2X2TS U8138 ( .A(n4344), .B(n4343), .Y(n9051) );
INVX2TS U8139 ( .A(n9051), .Y(n5326) );
INVX2TS U8140 ( .A(n4345), .Y(n4347) );
INVX2TS U8141 ( .A(n4350), .Y(n4352) );
NAND2X1TS U8142 ( .A(n4352), .B(n4351), .Y(n4353) );
CLKXOR2X2TS U8143 ( .A(n4354), .B(n4353), .Y(n9053) );
INVX2TS U8144 ( .A(n9053), .Y(n5321) );
INVX2TS U8145 ( .A(n4355), .Y(n4357) );
INVX2TS U8146 ( .A(n4359), .Y(n4361) );
XOR2X1TS U8147 ( .A(n4363), .B(n4362), .Y(n5315) );
AFHCONX2TS U8148 ( .A(n4381), .B(n4380), .CI(n4379), .CON(n4390), .S(n5604)
);
INVX2TS U8149 ( .A(n5604), .Y(n4421) );
INVX2TS U8150 ( .A(n4385), .Y(n4387) );
AFHCINX2TS U8151 ( .CIN(n4390), .B(n4391), .A(n4392), .S(n5609), .CO(n4519)
);
INVX2TS U8152 ( .A(n5609), .Y(n4410) );
INVX2TS U8153 ( .A(n4438), .Y(n4404) );
CMPR32X2TS U8154 ( .A(n4415), .B(n4414), .C(n4413), .CO(n4380), .S(n5601) );
CMPR32X2TS U8155 ( .A(n4420), .B(n4419), .C(n4418), .CO(n4425), .S(n5298) );
CMPR32X2TS U8156 ( .A(n4426), .B(n4425), .C(n4424), .CO(n5373), .S(n5290) );
INVX2TS U8157 ( .A(n4427), .Y(n4429) );
NAND2X1TS U8158 ( .A(n4429), .B(n4428), .Y(n4430) );
CLKXOR2X2TS U8159 ( .A(n4431), .B(n4430), .Y(n9075) );
INVX2TS U8160 ( .A(n9075), .Y(n5374) );
NAND2X1TS U8161 ( .A(n922), .B(n4432), .Y(n4434) );
INVX2TS U8162 ( .A(n9080), .Y(n5287) );
INVX2TS U8163 ( .A(n4859), .Y(n4440) );
INVX2TS U8164 ( .A(n4865), .Y(n4439) );
NAND2X1TS U8165 ( .A(n4586), .B(n4861), .Y(n4449) );
INVX2TS U8166 ( .A(n4451), .Y(n4453) );
NAND2X1TS U8167 ( .A(n4453), .B(n4452), .Y(n4454) );
CLKXOR2X2TS U8168 ( .A(n4455), .B(n4454), .Y(n9082) );
INVX2TS U8169 ( .A(n9082), .Y(n5382) );
INVX2TS U8170 ( .A(n4473), .Y(n4536) );
INVX2TS U8171 ( .A(DP_OP_338J35_122_4684_n1463), .Y(n4541) );
INVX2TS U8172 ( .A(n4496), .Y(n4534) );
INVX2TS U8173 ( .A(n4569), .Y(n4499) );
INVX2TS U8174 ( .A(n4500), .Y(n4501) );
INVX2TS U8175 ( .A(n4571), .Y(n4508) );
INVX2TS U8176 ( .A(n4574), .Y(n4507) );
NOR2X2TS U8177 ( .A(n4513), .B(n4512), .Y(n4910) );
AFHCONX2TS U8178 ( .A(n4521), .B(n4520), .CI(n4519), .CON(n4582), .S(n5612)
);
INVX2TS U8179 ( .A(n5617), .Y(n5380) );
INVX2TS U8180 ( .A(n4537), .Y(n4730) );
INVX2TS U8181 ( .A(n4604), .Y(n4552) );
INVX2TS U8182 ( .A(n4563), .Y(n4728) );
INVX2TS U8183 ( .A(n4744), .Y(n4566) );
INVX2TS U8184 ( .A(n4572), .Y(n4573) );
NOR2X2TS U8185 ( .A(n4579), .B(n4578), .Y(n4806) );
INVX2TS U8186 ( .A(n4806), .Y(n4580) );
INVX2TS U8187 ( .A(n4861), .Y(n4585) );
NOR2X2TS U8188 ( .A(n10239), .B(n4592), .Y(n10129) );
INVX2TS U8189 ( .A(n4862), .Y(n4593) );
NAND2X1TS U8190 ( .A(n4593), .B(n4860), .Y(n4594) );
INVX2TS U8191 ( .A(n5024), .Y(n4601) );
OAI21X4TS U8192 ( .A0(n5021), .A1(n4601), .B0(n5022), .Y(n5052) );
INVX2TS U8193 ( .A(n4613), .Y(n4780) );
INVX2TS U8194 ( .A(n4614), .Y(n4779) );
INVX2TS U8195 ( .A(n4668), .Y(n4721) );
INVX2TS U8196 ( .A(n4693), .Y(n4694) );
INVX2TS U8197 ( .A(n4697), .Y(n4724) );
INVX2TS U8198 ( .A(n4698), .Y(n4736) );
INVX2TS U8199 ( .A(n4715), .Y(n4741) );
AOI21X4TS U8200 ( .A0(n4755), .A1(n4792), .B0(n4754), .Y(n4983) );
INVX2TS U8201 ( .A(n4757), .Y(n4891) );
INVX2TS U8202 ( .A(n4758), .Y(n4890) );
CMPR32X2TS U8203 ( .A(n4796), .B(n4795), .C(n4794), .CO(n4828), .S(n4817) );
INVX2TS U8204 ( .A(n4797), .Y(n4799) );
CMPR32X2TS U8205 ( .A(n4804), .B(n4803), .C(n4802), .CO(n4794), .S(n4815) );
CMPR32X2TS U8206 ( .A(n4830), .B(n4829), .C(n4828), .CO(
DP_OP_338J35_122_4684_n1308), .S(n4831) );
INVX2TS U8207 ( .A(n4834), .Y(n4836) );
NAND2X1TS U8208 ( .A(n4836), .B(n4835), .Y(n4838) );
AFHCONX2TS U8209 ( .A(n4846), .B(n4845), .CI(n4844), .CON(n4837), .S(n4871)
);
INVX2TS U8210 ( .A(n4853), .Y(n4855) );
AOI21X4TS U8211 ( .A0(n5052), .A1(n4876), .B0(n4875), .Y(n5099) );
NAND2X1TS U8212 ( .A(n1019), .B(n4877), .Y(n4878) );
NAND2X1TS U8213 ( .A(n1017), .B(n4879), .Y(n4881) );
INVX2TS U8214 ( .A(n4910), .Y(n4936) );
INVX2TS U8215 ( .A(n4912), .Y(n4934) );
AOI21X4TS U8216 ( .A0(n4924), .A1(n4923), .B0(n4922), .Y(n5196) );
INVX2TS U8217 ( .A(n4974), .Y(n4930) );
INVX2TS U8218 ( .A(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(n5003) );
OAI21X4TS U8219 ( .A0(n5105), .A1(n5103), .B0(n5106), .Y(n5193) );
INVX2TS U8220 ( .A(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(n4996) );
INVX2TS U8221 ( .A(n5190), .Y(n5000) );
INVX2TS U8222 ( .A(n5007), .Y(n5009) );
CMPR32X2TS U8223 ( .A(n5020), .B(n5019), .C(n5018), .CO(n5012), .S(n5035) );
CMPR32X2TS U8224 ( .A(n5031), .B(n5030), .C(n5029), .CO(n5018), .S(n5032) );
INVX2TS U8225 ( .A(n5281), .Y(n5034) );
INVX2TS U8226 ( .A(n5270), .Y(n5039) );
INVX2TS U8227 ( .A(n5048), .Y(n5051) );
INVX2TS U8228 ( .A(n5049), .Y(n5050) );
INVX2TS U8229 ( .A(n5053), .Y(n5055) );
INVX2TS U8230 ( .A(n5069), .Y(n5071) );
INVX2TS U8231 ( .A(n5104), .Y(n5081) );
INVX2TS U8232 ( .A(n5095), .Y(n5098) );
INVX2TS U8233 ( .A(n5096), .Y(n5097) );
INVX2TS U8234 ( .A(n5168), .Y(n5131) );
INVX2TS U8235 ( .A(
Sgf_operation_ODD1_middle_RECURSIVE_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(n5140) );
INVX2TS U8236 ( .A(n5471), .Y(n5173) );
INVX2TS U8237 ( .A(n5470), .Y(n5456) );
INVX2TS U8238 ( .A(n5430), .Y(n5212) );
INVX2TS U8239 ( .A(n5433), .Y(n5206) );
AOI21X1TS U8240 ( .A0(n5436), .A1(n5212), .B0(n5206), .Y(n5207) );
INVX2TS U8241 ( .A(n8970), .Y(n5396) );
INVX2TS U8242 ( .A(n8976), .Y(n5395) );
INVX2TS U8243 ( .A(n5223), .Y(n5225) );
NAND2X1TS U8244 ( .A(n5225), .B(n5224), .Y(n5226) );
INVX2TS U8245 ( .A(n8982), .Y(n5510) );
INVX2TS U8246 ( .A(n5229), .Y(n5231) );
INVX2TS U8247 ( .A(n5234), .Y(n5236) );
NAND2X1TS U8248 ( .A(n5236), .B(n5235), .Y(n5237) );
INVX2TS U8249 ( .A(n8988), .Y(n5513) );
INVX2TS U8250 ( .A(n5238), .Y(n5253) );
INVX2TS U8251 ( .A(n5239), .Y(n5241) );
INVX2TS U8252 ( .A(n8994), .Y(n5517) );
INVX2TS U8253 ( .A(n5249), .Y(n5251) );
XOR2X2TS U8254 ( .A(n5253), .B(n5252), .Y(n9000) );
INVX2TS U8255 ( .A(n9000), .Y(n5520) );
INVX2TS U8256 ( .A(n9003), .Y(n5523) );
INVX2TS U8257 ( .A(n5273), .Y(n5279) );
AOI21X1TS U8258 ( .A0(n5279), .A1(n1061), .B0(n5274), .Y(n5277) );
INVX2TS U8259 ( .A(n9013), .Y(n5529) );
INVX2TS U8260 ( .A(n9021), .Y(n5586) );
CMPR32X2TS U8261 ( .A(n5286), .B(n5285), .C(n5284), .CO(n5377), .S(n5538) );
NAND2X1TS U8262 ( .A(n921), .B(n5293), .Y(n5294) );
XNOR2X2TS U8263 ( .A(n5294), .B(n968), .Y(n9073) );
INVX2TS U8264 ( .A(n9073), .Y(n5543) );
NAND2X1TS U8265 ( .A(n1086), .B(n5295), .Y(n5297) );
XNOR2X2TS U8266 ( .A(n5297), .B(n5296), .Y(n9069) );
INVX2TS U8267 ( .A(n9069), .Y(n5366) );
INVX2TS U8268 ( .A(n5310), .Y(n5312) );
NAND2X1TS U8269 ( .A(n5312), .B(n5311), .Y(n5314) );
CLKXOR2X2TS U8270 ( .A(n5314), .B(n5313), .Y(n9059) );
NAND2X1TS U8271 ( .A(n918), .B(n5318), .Y(n5320) );
XNOR2X2TS U8272 ( .A(n5320), .B(n5319), .Y(n9057) );
INVX2TS U8273 ( .A(n9057), .Y(n5354) );
NAND2X1TS U8274 ( .A(n1079), .B(n5329), .Y(n5331) );
INVX2TS U8275 ( .A(n5332), .Y(n5334) );
NAND2X1TS U8276 ( .A(n5334), .B(n5333), .Y(n5335) );
INVX2TS U8277 ( .A(n5576), .Y(n5581) );
INVX2TS U8278 ( .A(n5582), .Y(n5575) );
INVX2TS U8279 ( .A(n5580), .Y(n5346) );
INVX2TS U8280 ( .A(n5574), .Y(n5345) );
INVX2TS U8281 ( .A(n5571), .Y(n5568) );
INVX2TS U8282 ( .A(n5567), .Y(n5353) );
INVX2TS U8283 ( .A(n5559), .Y(n5359) );
INVX2TS U8284 ( .A(n5553), .Y(n5358) );
INVX2TS U8285 ( .A(n5549), .Y(n5368) );
CMPR32X2TS U8286 ( .A(n5373), .B(n5372), .C(n5371), .CO(n5284), .S(n5540) );
CMPR32X2TS U8287 ( .A(n5379), .B(n5378), .C(n5377), .CO(n3918), .S(n5534) );
ADDFHX4TS U8288 ( .A(n5385), .B(n5384), .CI(n5383), .CO(n4600), .S(n5531) );
INVX2TS U8289 ( .A(n9084), .Y(n5530) );
INVX2TS U8290 ( .A(n5389), .Y(n5391) );
AOI21X1TS U8291 ( .A0(n5436), .A1(n5407), .B0(n5406), .Y(n5408) );
INVX2TS U8292 ( .A(n8964), .Y(n5411) );
INVX2TS U8293 ( .A(n5419), .Y(n5420) );
AOI21X1TS U8294 ( .A0(n5436), .A1(n5422), .B0(n5421), .Y(n5423) );
INVX2TS U8295 ( .A(n8958), .Y(n5428) );
AOI21X1TS U8296 ( .A0(n5436), .A1(n5435), .B0(n5434), .Y(n5437) );
INVX2TS U8297 ( .A(n8952), .Y(n5444) );
NAND2X1TS U8298 ( .A(n5471), .B(n5456), .Y(n5458) );
INVX2TS U8299 ( .A(n5473), .Y(n5455) );
NOR2X2TS U8300 ( .A(n10120), .B(n10119), .Y(n5474) );
INVX2TS U8301 ( .A(n5474), .Y(n5463) );
NAND2X1TS U8302 ( .A(n10120), .B(n10119), .Y(n5472) );
NAND2X1TS U8303 ( .A(n5471), .B(n5476), .Y(n5479) );
AOI21X1TS U8304 ( .A0(n5477), .A1(n5476), .B0(n5475), .Y(n5478) );
AFHCONX2TS U8305 ( .A(n5511), .B(n5510), .CI(n5509), .CON(n5507), .S(n5599)
);
AFHCONX2TS U8306 ( .A(n5517), .B(n5516), .CI(n5515), .CON(n5512), .S(n5594)
);
AFHCONX2TS U8307 ( .A(n5523), .B(n5522), .CI(n5521), .CON(n5518), .S(n5588)
);
AFHCINX2TS U8308 ( .CIN(n5524), .B(n5525), .A(n5526), .S(n8927), .CO(n5521)
);
AFHCONX2TS U8309 ( .A(n5532), .B(n5531), .CI(n5530), .CON(n5584), .S(n8945)
);
CMPR32X2TS U8310 ( .A(n5535), .B(n5534), .C(n5533), .CO(n5532), .S(n8951) );
CMPR32X2TS U8311 ( .A(n5538), .B(n5537), .C(n5536), .CO(n5535), .S(n8957) );
CMPR32X2TS U8312 ( .A(n5541), .B(n5540), .C(n5539), .CO(n5536), .S(n8963) );
CMPR32X2TS U8313 ( .A(n5544), .B(n5543), .C(n5542), .CO(n5541), .S(n8969) );
NAND2X1TS U8314 ( .A(n817), .B(n5545), .Y(n5548) );
OAI21X1TS U8315 ( .A0(n5551), .A1(n5546), .B0(n5549), .Y(n5547) );
XOR2X1TS U8316 ( .A(n5552), .B(n5551), .Y(n8981) );
NAND2X1TS U8317 ( .A(n956), .B(n5553), .Y(n5558) );
AOI21X1TS U8318 ( .A0(n5556), .A1(n5572), .B0(n5555), .Y(n5557) );
XOR2X1TS U8319 ( .A(n5558), .B(n5557), .Y(n8987) );
NAND2X1TS U8320 ( .A(n5560), .B(n5559), .Y(n5566) );
INVX2TS U8321 ( .A(n5561), .Y(n5564) );
INVX2TS U8322 ( .A(n5562), .Y(n5563) );
AOI21X1TS U8323 ( .A0(n5564), .A1(n5572), .B0(n5563), .Y(n5565) );
XOR2X1TS U8324 ( .A(n5566), .B(n5565), .Y(n8993) );
NAND2X1TS U8325 ( .A(n822), .B(n5567), .Y(n5570) );
AOI21X1TS U8326 ( .A0(n5572), .A1(n1096), .B0(n5568), .Y(n5569) );
XOR2X1TS U8327 ( .A(n5570), .B(n5569), .Y(n8999) );
NAND2X1TS U8328 ( .A(n1003), .B(n5574), .Y(n5578) );
CMPR32X2TS U8329 ( .A(n4254), .B(n3754), .C(n5579), .CO(n5582), .S(n9022) );
NAND2X1TS U8330 ( .A(n5581), .B(n5580), .Y(n5583) );
AFHCINX2TS U8331 ( .CIN(n5584), .B(n5585), .A(n5586), .S(n8938), .CO(n5528)
);
NAND2X2TS U8332 ( .A(n5588), .B(n5587), .Y(n8920) );
INVX2TS U8333 ( .A(n8920), .Y(n5589) );
INVX2TS U8334 ( .A(n8906), .Y(n5595) );
AOI21X4TS U8335 ( .A0(n1080), .A1(n8907), .B0(n5595), .Y(n8902) );
INVX2TS U8336 ( .A(n8894), .Y(n5600) );
OAI21X4TS U8337 ( .A0(n8882), .A1(n8885), .B0(n8883), .Y(n8878) );
AOI21X4TS U8338 ( .A0(n8878), .A1(n1142), .B0(n5611), .Y(n8872) );
OAI21X4TS U8339 ( .A0(n8856), .A1(n8859), .B0(n8857), .Y(n8840) );
AOI21X4TS U8340 ( .A0(n5627), .A1(n8840), .B0(n5626), .Y(n8836) );
INVX2TS U8341 ( .A(n6140), .Y(n6012) );
NAND2X1TS U8342 ( .A(Op_MY[21]), .B(Op_MY[14]), .Y(n5691) );
INVX2TS U8343 ( .A(n5691), .Y(n5682) );
INVX2TS U8344 ( .A(n5681), .Y(n5630) );
AOI21X1TS U8345 ( .A0(n1025), .A1(n5682), .B0(n5630), .Y(n5678) );
OAI21X1TS U8346 ( .A0(n5675), .A1(n5678), .B0(n5676), .Y(n5662) );
NAND2X1TS U8347 ( .A(Op_MY[24]), .B(Op_MY[17]), .Y(n5660) );
INVX2TS U8348 ( .A(n5660), .Y(n5631) );
INVX2TS U8349 ( .A(n5635), .Y(n5860) );
INVX2TS U8350 ( .A(n5637), .Y(n5898) );
OAI22X1TS U8351 ( .A0(n6071), .A1(n5860), .B0(n6083), .B1(n5898), .Y(n5773)
);
NOR2X2TS U8352 ( .A(n988), .B(n1032), .Y(n6126) );
INVX2TS U8353 ( .A(n6126), .Y(n5772) );
NAND2X1TS U8354 ( .A(n5639), .B(n5638), .Y(n5641) );
INVX2TS U8355 ( .A(n5643), .Y(n5835) );
OAI22X1TS U8356 ( .A0(n6041), .A1(n5835), .B0(n5993), .B1(n6000), .Y(n5850)
);
INVX2TS U8357 ( .A(n883), .Y(n5897) );
INVX2TS U8358 ( .A(n6217), .Y(n5712) );
INVX2TS U8359 ( .A(n5659), .Y(n6040) );
NAND2X1TS U8360 ( .A(n1108), .B(n5660), .Y(n5661) );
INVX2TS U8361 ( .A(n6218), .Y(n5710) );
NOR2X1TS U8362 ( .A(DP_OP_346J35_130_4270_n836), .B(n771), .Y(n5764) );
NOR2X1TS U8363 ( .A(n1026), .B(DP_OP_346J35_130_4270_n829), .Y(n5763) );
INVX2TS U8364 ( .A(n6311), .Y(n5701) );
NOR2X1TS U8365 ( .A(n1109), .B(n772), .Y(n6320) );
INVX2TS U8366 ( .A(n6320), .Y(n5700) );
INVX2TS U8367 ( .A(n6210), .Y(n5705) );
NAND2X1TS U8368 ( .A(n5677), .B(n5676), .Y(n5679) );
NAND2X1TS U8369 ( .A(n1025), .B(n5681), .Y(n5683) );
XNOR2X1TS U8370 ( .A(n5683), .B(n5682), .Y(n5684) );
INVX3TS U8371 ( .A(n5684), .Y(n5946) );
NOR2X1TS U8372 ( .A(n1034), .B(n837), .Y(n5699) );
INVX2TS U8373 ( .A(n6213), .Y(n5694) );
NAND2X4TS U8374 ( .A(n1033), .B(n5691), .Y(n5948) );
NOR2X1TS U8375 ( .A(n6059), .B(n5948), .Y(n5693) );
OAI22X1TS U8376 ( .A0(n6082), .A1(n5948), .B0(n6059), .B1(n5946), .Y(n5811)
);
OAI22X1TS U8377 ( .A0(n5941), .A1(n6040), .B0(n5888), .B1(n5978), .Y(n5812)
);
OAI22X1TS U8378 ( .A0(n5941), .A1(n6000), .B0(n5888), .B1(n5835), .Y(n5802)
);
INVX2TS U8379 ( .A(n6214), .Y(n5801) );
INVX2TS U8380 ( .A(n6737), .Y(n5781) );
NOR2X2TS U8381 ( .A(n1026), .B(n772), .Y(n6195) );
INVX2TS U8382 ( .A(n6195), .Y(n5780) );
OAI22X1TS U8383 ( .A0(n5946), .A1(n5835), .B0(n5948), .B1(n6000), .Y(n5782)
);
INVX2TS U8384 ( .A(n6211), .Y(n5858) );
INVX2TS U8385 ( .A(n6221), .Y(n5714) );
INVX2TS U8386 ( .A(n5713), .Y(n5945) );
INVX2TS U8387 ( .A(n6223), .Y(n6003) );
INVX2TS U8388 ( .A(n6224), .Y(n6002) );
INVX2TS U8389 ( .A(n6139), .Y(n5987) );
INVX2TS U8390 ( .A(n6124), .Y(n5884) );
OAI22X1TS U8391 ( .A0(n5941), .A1(n5835), .B0(n5946), .B1(n6000), .Y(n5907)
);
INVX2TS U8392 ( .A(n6738), .Y(n5901) );
OAI22X1TS U8393 ( .A0(n5946), .A1(n5898), .B0(n5860), .B1(n5948), .Y(n5899)
);
OAI22X1TS U8394 ( .A0(n6040), .A1(n5948), .B0(n5978), .B1(n5946), .Y(n5863)
);
INVX2TS U8395 ( .A(n6321), .Y(n5891) );
INVX2TS U8396 ( .A(n6745), .Y(n5896) );
NOR2X2TS U8397 ( .A(DP_OP_346J35_130_4270_n836), .B(
DP_OP_346J35_130_4270_n829), .Y(n6194) );
INVX2TS U8398 ( .A(n6194), .Y(n5895) );
INVX2TS U8399 ( .A(n6309), .Y(n5893) );
INVX2TS U8400 ( .A(n6208), .Y(n5889) );
INVX2TS U8401 ( .A(n6114), .Y(n5861) );
INVX2TS U8402 ( .A(n6117), .Y(n5909) );
INVX2TS U8403 ( .A(n5803), .Y(n6055) );
INVX2TS U8404 ( .A(n5804), .Y(n6042) );
OAI22X1TS U8405 ( .A0(n6055), .A1(n5941), .B0(n6042), .B1(n5888), .Y(n5882)
);
INVX2TS U8406 ( .A(n6215), .Y(n5844) );
INVX2TS U8407 ( .A(n6216), .Y(n5843) );
OAI22X1TS U8408 ( .A0(n5993), .A1(n5835), .B0(n5888), .B1(n6000), .Y(n5842)
);
OAI22X1TS U8409 ( .A0(n6055), .A1(n5993), .B0(n6042), .B1(n6041), .Y(n6009)
);
INVX2TS U8410 ( .A(n6222), .Y(n5833) );
OAI22X1TS U8411 ( .A0(n6041), .A1(n5978), .B0(n5993), .B1(n6040), .Y(n5832)
);
OAI22X1TS U8412 ( .A0(n6071), .A1(n6000), .B0(n6083), .B1(n5835), .Y(n6004)
);
INVX2TS U8413 ( .A(n6127), .Y(n5852) );
OAI22X1TS U8414 ( .A0(n6041), .A1(n5898), .B0(n5993), .B1(n5860), .Y(n5878)
);
INVX2TS U8415 ( .A(n6119), .Y(n5876) );
NOR2XLTS U8416 ( .A(n5978), .B(n5948), .Y(n5937) );
OAI22X1TS U8417 ( .A0(n5941), .A1(n5945), .B0(n5888), .B1(n5947), .Y(n5935)
);
OAI22X1TS U8418 ( .A0(n6055), .A1(n5946), .B0(n6042), .B1(n5941), .Y(n5914)
);
INVX2TS U8419 ( .A(n6115), .Y(n5932) );
NOR2X1TS U8420 ( .A(n6042), .B(n5948), .Y(n5952) );
OAI22X1TS U8421 ( .A0(n5941), .A1(n5947), .B0(n5946), .B1(n5945), .Y(n6259)
);
OAI22X1TS U8422 ( .A0(n5946), .A1(n5947), .B0(n5948), .B1(n5945), .Y(n6269)
);
NOR2XLTS U8423 ( .A(n5948), .B(n5947), .Y(n6280) );
INVX2TS U8424 ( .A(n6235), .Y(n5955) );
INVX2TS U8425 ( .A(n6234), .Y(n5954) );
INVX2TS U8426 ( .A(n6288), .Y(n5960) );
INVX2TS U8427 ( .A(n6144), .Y(n6021) );
OAI22X1TS U8428 ( .A0(n6071), .A1(n6040), .B0(n6083), .B1(n5978), .Y(n6045)
);
INVX2TS U8429 ( .A(n6226), .Y(n6030) );
OAI22X1TS U8430 ( .A0(n6041), .A1(n6059), .B0(n5993), .B1(n6082), .Y(n6028)
);
NOR2X2TS U8431 ( .A(n934), .B(n774), .Y(n6143) );
INVX2TS U8432 ( .A(n6143), .Y(n6039) );
INVX2TS U8433 ( .A(n6225), .Y(n6037) );
INVX2TS U8434 ( .A(n6227), .Y(n6070) );
OAI22X1TS U8435 ( .A0(n6071), .A1(n6059), .B0(n6041), .B1(n6082), .Y(n6060)
);
INVX2TS U8436 ( .A(n6084), .Y(n6067) );
INVX2TS U8437 ( .A(n6291), .Y(n6066) );
XNOR2X1TS U8438 ( .A(n6067), .B(n6066), .Y(n6233) );
NAND2X1TS U8439 ( .A(n6195), .B(n6194), .Y(n6196) );
INVX2TS U8440 ( .A(n6196), .Y(n6310) );
NAND2X1TS U8441 ( .A(n6115), .B(n6114), .Y(n6188) );
INVX2TS U8442 ( .A(n6188), .Y(n6116) );
AOI21X1TS U8443 ( .A0(n1193), .A1(n6189), .B0(n6116), .Y(n6158) );
NAND2X1TS U8444 ( .A(n1194), .B(n1195), .Y(n6123) );
NAND2X1TS U8445 ( .A(n6118), .B(n6117), .Y(n6178) );
INVX2TS U8446 ( .A(n6178), .Y(n6159) );
NAND2X1TS U8447 ( .A(n6120), .B(n6119), .Y(n6160) );
INVX2TS U8448 ( .A(n6160), .Y(n6121) );
AOI21X1TS U8449 ( .A0(n1195), .A1(n6159), .B0(n6121), .Y(n6122) );
OAI21X1TS U8450 ( .A0(n6158), .A1(n6123), .B0(n6122), .Y(n6138) );
INVX2TS U8451 ( .A(n6138), .Y(n6170) );
NOR2X2TS U8452 ( .A(n6125), .B(n6124), .Y(n6166) );
NAND2X1TS U8453 ( .A(n6125), .B(n6124), .Y(n6167) );
NOR2X2TS U8454 ( .A(n6127), .B(n6126), .Y(n6135) );
INVX2TS U8455 ( .A(n6135), .Y(n6128) );
NAND2X1TS U8456 ( .A(n6127), .B(n6126), .Y(n6134) );
NAND2X1TS U8457 ( .A(n6128), .B(n6134), .Y(n6129) );
XNOR2X1TS U8458 ( .A(n6130), .B(n6129), .Y(n6334) );
INVX2TS U8459 ( .A(n6131), .Y(n6132) );
NOR2X1TS U8460 ( .A(n6165), .B(n6133), .Y(n6337) );
OAI21X1TS U8461 ( .A0(n6135), .A1(n6167), .B0(n6134), .Y(n6136) );
AOI21X2TS U8462 ( .A0(n6138), .A1(n6137), .B0(n6136), .Y(n6349) );
NOR2X2TS U8463 ( .A(n6140), .B(n6139), .Y(n6345) );
INVX2TS U8464 ( .A(n6345), .Y(n6141) );
NAND2X1TS U8465 ( .A(n6140), .B(n6139), .Y(n6347) );
NAND2X1TS U8466 ( .A(n6141), .B(n6347), .Y(n6142) );
NOR2X2TS U8467 ( .A(n6144), .B(n6143), .Y(n6348) );
INVX2TS U8468 ( .A(n6348), .Y(n6145) );
NAND2X1TS U8469 ( .A(n6144), .B(n6143), .Y(n6346) );
NAND2X1TS U8470 ( .A(n6145), .B(n6346), .Y(n6146) );
INVX2TS U8471 ( .A(n6172), .Y(n6148) );
INVX2TS U8472 ( .A(n6171), .Y(n6150) );
INVX2TS U8473 ( .A(n6153), .Y(n6155) );
NAND2X1TS U8474 ( .A(n6155), .B(n6154), .Y(n6156) );
INVX2TS U8475 ( .A(n6158), .Y(n6180) );
NAND2X1TS U8476 ( .A(n1195), .B(n6160), .Y(n6161) );
INVX2TS U8477 ( .A(n6166), .Y(n6168) );
NAND2X1TS U8478 ( .A(n6168), .B(n6167), .Y(n6169) );
INVX2TS U8479 ( .A(n6173), .Y(n6175) );
NAND2X1TS U8480 ( .A(n1194), .B(n6178), .Y(n6179) );
INVX2TS U8481 ( .A(n6181), .Y(n6316) );
INVX2TS U8482 ( .A(n6315), .Y(n6182) );
INVX2TS U8483 ( .A(n6183), .Y(n6185) );
NAND2X1TS U8484 ( .A(n6185), .B(n6184), .Y(n6186) );
NAND2X1TS U8485 ( .A(n1193), .B(n6188), .Y(n6190) );
INVX2TS U8486 ( .A(n6302), .Y(n6191) );
INVX2TS U8487 ( .A(n6192), .Y(n6303) );
INVX2TS U8488 ( .A(n6197), .Y(n6199) );
INVX2TS U8489 ( .A(n6202), .Y(n6204) );
NAND2X1TS U8490 ( .A(n6204), .B(n6203), .Y(n6206) );
XOR2X1TS U8491 ( .A(n6206), .B(n6205), .Y(n6286) );
NAND2X1TS U8492 ( .A(n6746), .B(n6745), .Y(n6747) );
INVX2TS U8493 ( .A(n6747), .Y(n6740) );
NAND2X1TS U8494 ( .A(n6738), .B(n6737), .Y(n6739) );
INVX2TS U8495 ( .A(n6739), .Y(n6207) );
NOR2X1TS U8496 ( .A(n6740), .B(n6207), .Y(n6732) );
NAND2X1TS U8497 ( .A(n6209), .B(n6208), .Y(n6730) );
NAND2X1TS U8498 ( .A(n6211), .B(n6210), .Y(n6723) );
INVX2TS U8499 ( .A(n6723), .Y(n6212) );
NOR2X2TS U8500 ( .A(n6228), .B(n6227), .Y(n6242) );
NAND2X1TS U8501 ( .A(n6251), .B(n6230), .Y(n6232) );
OAI21X2TS U8502 ( .A0(n6262), .A1(n6270), .B0(n6263), .Y(n6250) );
NAND2X1TS U8503 ( .A(n6228), .B(n6227), .Y(n6243) );
AOI21X1TS U8504 ( .A0(n6250), .A1(n6230), .B0(n6229), .Y(n6231) );
NAND2X1TS U8505 ( .A(n1188), .B(n6234), .Y(n6236) );
INVX2TS U8506 ( .A(n6251), .Y(n6238) );
INVX2TS U8507 ( .A(n6250), .Y(n6239) );
INVX2TS U8508 ( .A(n6242), .Y(n6244) );
NAND2X1TS U8509 ( .A(n6244), .B(n6243), .Y(n6245) );
AFHCONX2TS U8510 ( .A(n6249), .B(n6248), .CI(n6247), .CON(n6235), .S(n6698)
);
INVX2TS U8511 ( .A(n6252), .Y(n6254) );
NAND2X1TS U8512 ( .A(n6254), .B(n6253), .Y(n6255) );
XOR2X1TS U8513 ( .A(n6256), .B(n6255), .Y(n6697) );
AFHCINX2TS U8514 ( .CIN(n6257), .B(n6258), .A(n6259), .S(n6783), .CO(n6247)
);
INVX2TS U8515 ( .A(n6260), .Y(n6271) );
INVX2TS U8516 ( .A(n6270), .Y(n6261) );
INVX2TS U8517 ( .A(n6262), .Y(n6264) );
NAND2X1TS U8518 ( .A(n6264), .B(n6263), .Y(n6265) );
AFHCONX2TS U8519 ( .A(n6269), .B(n6268), .CI(n6267), .CON(n6257), .S(n6777)
);
NAND2X1TS U8520 ( .A(n6271), .B(n6270), .Y(n6272) );
INVX2TS U8521 ( .A(n6274), .Y(n6711) );
INVX2TS U8522 ( .A(n6275), .Y(n6277) );
CMPR32X2TS U8523 ( .A(n6281), .B(n6976), .C(n6280), .CO(n6268), .S(n6704) );
INVX2TS U8524 ( .A(n6682), .Y(n6287) );
NAND2X1TS U8525 ( .A(n1189), .B(n6288), .Y(n6290) );
INVX2TS U8526 ( .A(n6066), .Y(n6294) );
INVX2TS U8527 ( .A(n6292), .Y(n6293) );
INVX2TS U8528 ( .A(n6669), .Y(n6299) );
INVX2TS U8529 ( .A(n6304), .Y(n6306) );
CMPR32X2TS U8530 ( .A(n6311), .B(n6310), .C(n6309), .CO(n6319), .S(n6312) );
INVX2TS U8531 ( .A(n6655), .Y(n6314) );
CMPR32X2TS U8532 ( .A(n6321), .B(n6320), .C(n6319), .CO(n6189), .S(n6322) );
AOI21X4TS U8533 ( .A0(n6329), .A1(n6630), .B0(n6328), .Y(n6820) );
XNOR2X1TS U8534 ( .A(Op_MX[12]), .B(Op_MY[13]), .Y(n10312) );
OAI22X1TS U8535 ( .A0(n6352), .A1(n10312), .B0(n10317), .B1(n947), .Y(n6391)
);
INVX2TS U8536 ( .A(n6391), .Y(n6387) );
XNOR2X1TS U8537 ( .A(Op_MX[13]), .B(Op_MX[12]), .Y(n6355) );
OAI22X1TS U8538 ( .A0(n6354), .A1(n910), .B0(n10383), .B1(n1104), .Y(n6386)
);
XNOR2X1TS U8539 ( .A(Op_MX[12]), .B(Op_MY[7]), .Y(n6356) );
XNOR2X1TS U8540 ( .A(Op_MX[12]), .B(Op_MY[8]), .Y(n10318) );
OAI22X1TS U8541 ( .A0(n6352), .A1(n6356), .B0(n10317), .B1(n10318), .Y(n6363) );
XNOR2X1TS U8542 ( .A(Op_MX[9]), .B(Op_MX[8]), .Y(n6359) );
XOR2X1TS U8543 ( .A(Op_MX[9]), .B(Op_MX[10]), .Y(n6357) );
XNOR2X1TS U8544 ( .A(Op_MX[10]), .B(Op_MY[9]), .Y(n6360) );
BUFX3TS U8545 ( .A(n6359), .Y(n10424) );
XNOR2X1TS U8546 ( .A(Op_MX[10]), .B(Op_MY[10]), .Y(n10322) );
OAI22X1TS U8547 ( .A0(n6358), .A1(n6360), .B0(n10424), .B1(n10322), .Y(n6362) );
NAND2X2TS U8548 ( .A(Op_MX[8]), .B(n1070), .Y(n10325) );
XNOR2X1TS U8549 ( .A(Op_MX[8]), .B(Op_MY[10]), .Y(n6369) );
XNOR2X1TS U8550 ( .A(Op_MX[8]), .B(Op_MY[11]), .Y(n6364) );
OAI22X1TS U8551 ( .A0(n10325), .A1(n6369), .B0(n6364), .B1(n1070), .Y(n6368)
);
NOR2BX1TS U8552 ( .AN(Op_MY[7]), .B(n10317), .Y(n6367) );
XNOR2X1TS U8553 ( .A(Op_MX[10]), .B(Op_MY[8]), .Y(n6370) );
OAI22X1TS U8554 ( .A0(n6358), .A1(n6370), .B0(n10424), .B1(n6360), .Y(n6366)
);
CMPR32X2TS U8555 ( .A(n6363), .B(n6362), .C(n6361), .CO(n6418), .S(n6422) );
XNOR2X1TS U8556 ( .A(Op_MX[8]), .B(Op_MY[12]), .Y(n10324) );
OAI22X1TS U8557 ( .A0(n10325), .A1(n6364), .B0(n10324), .B1(n1070), .Y(
n10344) );
OAI22X1TS U8558 ( .A0(n6352), .A1(n947), .B0(n10317), .B1(n6365), .Y(n10343)
);
CMPR32X2TS U8559 ( .A(n6368), .B(n6367), .C(n6366), .CO(n6361), .S(n6426) );
XNOR2X1TS U8560 ( .A(Op_MX[8]), .B(Op_MY[9]), .Y(n6375) );
OAI22X1TS U8561 ( .A0(n10325), .A1(n6375), .B0(n6369), .B1(n1070), .Y(n6373)
);
XNOR2X1TS U8562 ( .A(Op_MX[10]), .B(Op_MY[7]), .Y(n6371) );
OAI22X1TS U8563 ( .A0(n6358), .A1(n6371), .B0(n10424), .B1(n6370), .Y(n6372)
);
NAND2BXLTS U8564 ( .AN(Op_MY[7]), .B(Op_MX[10]), .Y(n6374) );
OAI22X1TS U8565 ( .A0(n6358), .A1(n952), .B0(n10424), .B1(n6374), .Y(n6429)
);
XNOR2X1TS U8566 ( .A(Op_MX[8]), .B(Op_MY[8]), .Y(n6377) );
OAI22X1TS U8567 ( .A0(n10325), .A1(n6377), .B0(n6375), .B1(n1070), .Y(n6434)
);
NOR2BX1TS U8568 ( .AN(Op_MY[7]), .B(n10424), .Y(n6433) );
NAND2BXLTS U8569 ( .AN(Op_MY[7]), .B(Op_MX[8]), .Y(n6376) );
NAND2X1TS U8570 ( .A(n6376), .B(n10325), .Y(n6404) );
OAI22X1TS U8571 ( .A0(n10325), .A1(Op_MY[7]), .B0(n6377), .B1(n1070), .Y(
n6403) );
CMPR32X2TS U8572 ( .A(DP_OP_347J35_131_5122_n403), .B(
DP_OP_347J35_131_5122_n405), .C(n6378), .CO(n6388), .S(n10363) );
CMPR32X2TS U8573 ( .A(DP_OP_347J35_131_5122_n406), .B(
DP_OP_347J35_131_5122_n410), .C(n6379), .CO(n6378), .S(n10354) );
CMPR32X2TS U8574 ( .A(Op_MY[6]), .B(Op_MY[13]), .C(n6382), .CO(n6381), .S(
n6383) );
CMPR32X2TS U8575 ( .A(Op_MX[13]), .B(Op_MX[6]), .C(n6384), .CO(n6385), .S(
n6380) );
CMPR32X2TS U8576 ( .A(n6387), .B(n6386), .C(DP_OP_347J35_131_5122_n401),
.CO(n6834), .S(n6389) );
OAI22X1TS U8577 ( .A0(n6354), .A1(n1104), .B0(n10383), .B1(n1049), .Y(n6392)
);
CMPR32X2TS U8578 ( .A(DP_OP_347J35_131_5122_n402), .B(n6389), .C(n6388),
.CO(n6832), .S(n10338) );
CMPR32X2TS U8579 ( .A(n6392), .B(n6391), .C(n6390), .CO(n6393), .S(n6833) );
XOR2X1TS U8580 ( .A(n6393), .B(n1039), .Y(n6394) );
XOR2X1TS U8581 ( .A(n6395), .B(n6394), .Y(n6841) );
INVX2TS U8582 ( .A(n6841), .Y(n6416) );
NAND2BXLTS U8583 ( .AN(Op_MY[0]), .B(Op_MX[1]), .Y(n6396) );
NAND2X2TS U8584 ( .A(Op_MX[1]), .B(n1087), .Y(n10366) );
NAND2X1TS U8585 ( .A(n6396), .B(n10366), .Y(n6467) );
XNOR2X1TS U8586 ( .A(Op_MX[1]), .B(Op_MY[1]), .Y(n6465) );
OAI22X1TS U8587 ( .A0(n10366), .A1(Op_MY[0]), .B0(n6465), .B1(n1087), .Y(
n6466) );
NOR2BX1TS U8588 ( .AN(Op_MY[7]), .B(n1070), .Y(n6512) );
INVX2TS U8589 ( .A(n6512), .Y(n6489) );
INVX2TS U8590 ( .A(n10556), .Y(n6488) );
ADDHXLTS U8591 ( .A(Op_MX[0]), .B(Op_MX[7]), .CO(n6399), .S(n6397) );
INVX2TS U8592 ( .A(n6397), .Y(n10426) );
INVX2TS U8593 ( .A(n6398), .Y(n10393) );
NOR2XLTS U8594 ( .A(n10426), .B(n10393), .Y(n6487) );
INVX2TS U8595 ( .A(n6400), .Y(n10427) );
NOR2XLTS U8596 ( .A(n10427), .B(n10393), .Y(n10349) );
INVX2TS U8597 ( .A(n6402), .Y(n10402) );
NOR2XLTS U8598 ( .A(n10402), .B(n10426), .Y(n10348) );
ADDHX1TS U8599 ( .A(n6404), .B(n6403), .CO(n6432), .S(n10352) );
INVX2TS U8600 ( .A(n6406), .Y(n10407) );
CMPR32X2TS U8601 ( .A(n6408), .B(n6407), .C(DP_OP_347J35_131_5122_n20), .CO(
n6409), .S(n6413) );
XNOR2X1TS U8602 ( .A(n6410), .B(n6409), .Y(n6496) );
CMPR32X2TS U8603 ( .A(DP_OP_347J35_131_5122_n411), .B(
DP_OP_347J35_131_5122_n415), .C(n6411), .CO(n6379), .S(n10355) );
CMPR32X2TS U8604 ( .A(DP_OP_347J35_131_5122_n21), .B(n6413), .C(n6412), .CO(
n6410), .S(n6498) );
CMPR32X2TS U8605 ( .A(DP_OP_347J35_131_5122_n416), .B(
DP_OP_347J35_131_5122_n418), .C(n6414), .CO(n6411), .S(n10353) );
CMPR32X2TS U8606 ( .A(DP_OP_347J35_131_5122_n22), .B(n6416), .C(n6415), .CO(
n6412), .S(n6500) );
CMPR32X2TS U8607 ( .A(DP_OP_347J35_131_5122_n419), .B(n6418), .C(n6417),
.CO(n6414), .S(n10359) );
CMPR32X2TS U8608 ( .A(DP_OP_347J35_131_5122_n27), .B(
DP_OP_347J35_131_5122_n32), .C(n6419), .CO(n6415), .S(n6502) );
CMPR32X2TS U8609 ( .A(n6422), .B(n6421), .C(n6420), .CO(n6417), .S(n10358)
);
CMPR32X2TS U8610 ( .A(DP_OP_347J35_131_5122_n33), .B(
DP_OP_347J35_131_5122_n40), .C(n6423), .CO(n6419), .S(n6504) );
CMPR32X2TS U8611 ( .A(n6426), .B(n6425), .C(n6424), .CO(n6420), .S(n10356)
);
CMPR32X2TS U8612 ( .A(DP_OP_347J35_131_5122_n41), .B(
DP_OP_347J35_131_5122_n49), .C(n6427), .CO(n6423), .S(n6506) );
CMPR32X2TS U8613 ( .A(n6430), .B(n6429), .C(n6428), .CO(n6424), .S(n10357)
);
CMPR32X2TS U8614 ( .A(DP_OP_347J35_131_5122_n50), .B(
DP_OP_347J35_131_5122_n60), .C(n6431), .CO(n6427), .S(n6508) );
CMPR32X2TS U8615 ( .A(n6434), .B(n6433), .C(n6432), .CO(n6428), .S(n10362)
);
CMPR32X2TS U8616 ( .A(DP_OP_347J35_131_5122_n61), .B(
DP_OP_347J35_131_5122_n73), .C(n6435), .CO(n6431), .S(n6510) );
CMPR32X2TS U8617 ( .A(DP_OP_347J35_131_5122_n74), .B(
DP_OP_347J35_131_5122_n86), .C(n6436), .CO(n6435), .S(n6513) );
CMPR32X2TS U8618 ( .A(DP_OP_347J35_131_5122_n87), .B(
DP_OP_347J35_131_5122_n90), .C(n6437), .CO(n6436), .S(n6515) );
XNOR2X1TS U8619 ( .A(Op_MX[3]), .B(Op_MX[4]), .Y(n6440) );
XOR2X1TS U8620 ( .A(Op_MX[5]), .B(Op_MX[4]), .Y(n6438) );
XNOR2X1TS U8621 ( .A(Op_MX[5]), .B(Op_MY[6]), .Y(n10310) );
BUFX3TS U8622 ( .A(n6440), .Y(n10370) );
OAI22X1TS U8623 ( .A0(n6439), .A1(n10310), .B0(n10370), .B1(n951), .Y(n6469)
);
INVX2TS U8624 ( .A(n6469), .Y(n6444) );
XNOR2X1TS U8625 ( .A(Op_MX[5]), .B(Op_MX[6]), .Y(n6442) );
BUFX3TS U8626 ( .A(n6442), .Y(n10372) );
OAI22X1TS U8627 ( .A0(n6441), .A1(n976), .B0(n10372), .B1(n957), .Y(n6443)
);
OAI22X1TS U8628 ( .A0(n6441), .A1(n957), .B0(n10372), .B1(n966), .Y(n6470)
);
AO21XLTS U8629 ( .A0(n6439), .A1(n10370), .B0(n951), .Y(n6468) );
CMPR32X2TS U8630 ( .A(n6444), .B(n6443), .C(DP_OP_347J35_131_5122_n256),
.CO(n6477), .S(n6480) );
XNOR2X1TS U8631 ( .A(Op_MX[5]), .B(Op_MY[0]), .Y(n6445) );
XNOR2X1TS U8632 ( .A(Op_MX[5]), .B(Op_MY[1]), .Y(n10361) );
OAI22X1TS U8633 ( .A0(n6439), .A1(n6445), .B0(n10370), .B1(n10361), .Y(n6452) );
XNOR2X1TS U8634 ( .A(Op_MX[1]), .B(Op_MX[2]), .Y(n6448) );
XOR2X1TS U8635 ( .A(Op_MX[3]), .B(Op_MX[2]), .Y(n6446) );
XNOR2X1TS U8636 ( .A(Op_MX[3]), .B(Op_MY[2]), .Y(n6449) );
BUFX3TS U8637 ( .A(n6448), .Y(n10422) );
XNOR2X1TS U8638 ( .A(Op_MX[3]), .B(Op_MY[3]), .Y(n10368) );
OAI22X1TS U8639 ( .A0(n6447), .A1(n6449), .B0(n10422), .B1(n10368), .Y(n6451) );
XNOR2X1TS U8640 ( .A(Op_MX[1]), .B(Op_MY[3]), .Y(n6458) );
XNOR2X1TS U8641 ( .A(Op_MX[1]), .B(Op_MY[4]), .Y(n6453) );
OAI22X1TS U8642 ( .A0(n10366), .A1(n6458), .B0(n6453), .B1(n1087), .Y(n6457)
);
NOR2BX1TS U8643 ( .AN(Op_MY[0]), .B(n10370), .Y(n6456) );
XNOR2X1TS U8644 ( .A(Op_MX[3]), .B(Op_MY[1]), .Y(n6459) );
OAI22X1TS U8645 ( .A0(n6447), .A1(n6459), .B0(n10422), .B1(n6449), .Y(n6455)
);
CMPR32X2TS U8646 ( .A(n6452), .B(n6451), .C(n6450), .CO(n6531), .S(n6534) );
XNOR2X1TS U8647 ( .A(Op_MX[1]), .B(Op_MY[5]), .Y(n10365) );
OAI22X1TS U8648 ( .A0(n10366), .A1(n6453), .B0(n10365), .B1(n1087), .Y(
n10351) );
OAI22X1TS U8649 ( .A0(n6439), .A1(n951), .B0(n10370), .B1(n6454), .Y(n10350)
);
CMPR32X2TS U8650 ( .A(n6457), .B(n6456), .C(n6455), .CO(n6450), .S(n6537) );
XNOR2X1TS U8651 ( .A(Op_MX[1]), .B(Op_MY[2]), .Y(n6464) );
OAI22X1TS U8652 ( .A0(n10366), .A1(n6464), .B0(n6458), .B1(n1087), .Y(n6462)
);
XNOR2X1TS U8653 ( .A(Op_MX[3]), .B(Op_MY[0]), .Y(n6460) );
OAI22X1TS U8654 ( .A0(n6447), .A1(n6460), .B0(n10422), .B1(n6459), .Y(n6461)
);
NAND2BXLTS U8655 ( .AN(Op_MY[0]), .B(Op_MX[3]), .Y(n6463) );
OAI22X1TS U8656 ( .A0(n6447), .A1(n953), .B0(n10422), .B1(n6463), .Y(n6542)
);
OAI22X1TS U8657 ( .A0(n10366), .A1(n6465), .B0(n6464), .B1(n1087), .Y(n6546)
);
NOR2BX1TS U8658 ( .AN(Op_MY[0]), .B(n10422), .Y(n6545) );
CMPR32X2TS U8659 ( .A(n6470), .B(n6469), .C(n6468), .CO(n6471), .S(n6476) );
XOR2X1TS U8660 ( .A(n6471), .B(n830), .Y(n6472) );
CMPR32X2TS U8661 ( .A(DP_OP_347J35_131_5122_n98), .B(
DP_OP_347J35_131_5122_n101), .C(n6474), .CO(n6437), .S(n6517) );
CMPR32X2TS U8662 ( .A(n6477), .B(n6476), .C(n6475), .CO(n6473), .S(n10373)
);
CMPR32X2TS U8663 ( .A(DP_OP_347J35_131_5122_n108), .B(
DP_OP_347J35_131_5122_n111), .C(n6478), .CO(n6474), .S(n6519) );
CMPR32X2TS U8664 ( .A(DP_OP_347J35_131_5122_n257), .B(n6480), .C(n6479),
.CO(n6475), .S(n10384) );
CMPR32X2TS U8665 ( .A(n6481), .B(DP_OP_347J35_131_5122_n122), .C(
DP_OP_347J35_131_5122_n116), .CO(n6478), .S(n6521) );
CMPR32X2TS U8666 ( .A(DP_OP_347J35_131_5122_n258), .B(
DP_OP_347J35_131_5122_n260), .C(n6482), .CO(n6479), .S(n10385) );
CMPR32X2TS U8667 ( .A(DP_OP_347J35_131_5122_n261), .B(
DP_OP_347J35_131_5122_n265), .C(n6483), .CO(n6482), .S(n10375) );
CMPR32X2TS U8668 ( .A(n6485), .B(n6484), .C(DP_OP_347J35_131_5122_n123),
.CO(n6481), .S(n6523) );
CMPR32X2TS U8669 ( .A(DP_OP_347J35_131_5122_n271), .B(
DP_OP_347J35_131_5122_n273), .C(n6486), .CO(n6492), .S(n10374) );
CMPR32X2TS U8670 ( .A(n6489), .B(n6488), .C(n6487), .CO(n6491), .S(n6526) );
NAND2X1TS U8671 ( .A(n10374), .B(n6526), .Y(n6527) );
INVX2TS U8672 ( .A(n6527), .Y(n6525) );
CMPR32X2TS U8673 ( .A(n6749), .B(n6491), .C(n6490), .CO(n6485), .S(n6524) );
CMPR32X2TS U8674 ( .A(DP_OP_347J35_131_5122_n266), .B(
DP_OP_347J35_131_5122_n270), .C(n6492), .CO(n6483), .S(n10376) );
ADDHX1TS U8675 ( .A(n10363), .B(n6493), .CO(n6835), .S(n8581) );
CMPR32X2TS U8676 ( .A(n6496), .B(n10355), .C(n6495), .CO(n6494), .S(n8587)
);
INVX2TS U8677 ( .A(n8587), .Y(n6616) );
CMPR32X2TS U8678 ( .A(n6498), .B(n10353), .C(n6497), .CO(n6495), .S(n8590)
);
INVX2TS U8679 ( .A(n8590), .Y(n6623) );
CMPR32X2TS U8680 ( .A(n6500), .B(n10359), .C(n6499), .CO(n6497), .S(n8593)
);
INVX2TS U8681 ( .A(n8593), .Y(n6629) );
CMPR32X2TS U8682 ( .A(n6502), .B(n10358), .C(n6501), .CO(n6499), .S(n8596)
);
INVX2TS U8683 ( .A(n8596), .Y(n6638) );
CMPR32X2TS U8684 ( .A(n6504), .B(n10356), .C(n6503), .CO(n6501), .S(n8599)
);
CMPR32X2TS U8685 ( .A(n6506), .B(n10357), .C(n6505), .CO(n6503), .S(n8602)
);
INVX2TS U8686 ( .A(n8602), .Y(n6654) );
CMPR32X2TS U8687 ( .A(n6508), .B(n10362), .C(n6507), .CO(n6505), .S(n8605)
);
INVX2TS U8688 ( .A(n8605), .Y(n6660) );
CMPR32X2TS U8689 ( .A(n6510), .B(n10352), .C(n6509), .CO(n6507), .S(n8607)
);
CMPR32X2TS U8690 ( .A(n6513), .B(n6512), .C(n6511), .CO(n6509), .S(n8611) );
INVX2TS U8691 ( .A(n8611), .Y(n6674) );
CMPR32X2TS U8692 ( .A(n6515), .B(n10336), .C(n6514), .CO(n6511), .S(n10617)
);
CMPR32X2TS U8693 ( .A(n6517), .B(n10373), .C(n6516), .CO(n6514), .S(n10616)
);
CMPR32X2TS U8694 ( .A(n6519), .B(n10384), .C(n6518), .CO(n6516), .S(n10615)
);
CMPR32X2TS U8695 ( .A(n6521), .B(n10385), .C(n6520), .CO(n6518), .S(n10614)
);
CMPR32X2TS U8696 ( .A(n10375), .B(n6523), .C(n6522), .CO(n6520), .S(n10613)
);
CMPR32X2TS U8697 ( .A(n6525), .B(n6524), .C(n10376), .CO(n6522), .S(n10612)
);
OR2X1TS U8698 ( .A(n10374), .B(n6526), .Y(n6528) );
CMPR32X2TS U8699 ( .A(DP_OP_347J35_131_5122_n274), .B(n6531), .C(n6530),
.CO(n6486), .S(n10562) );
CMPR32X2TS U8700 ( .A(n6534), .B(n6533), .C(n6532), .CO(n6530), .S(n10561)
);
CMPR32X2TS U8701 ( .A(n6537), .B(n6536), .C(n6535), .CO(n6532), .S(n10560)
);
CMPR32X2TS U8702 ( .A(n6543), .B(n6542), .C(n6541), .CO(n6535), .S(n10559)
);
CMPR32X2TS U8703 ( .A(n6546), .B(n6545), .C(n6544), .CO(n6541), .S(n10558)
);
OR2X1TS U8704 ( .A(n1101), .B(n6749), .Y(n6743) );
NAND2X1TS U8705 ( .A(n828), .B(n6550), .Y(n6552) );
XNOR2X1TS U8706 ( .A(n6552), .B(n6551), .Y(n6742) );
INVX2TS U8707 ( .A(n6553), .Y(n6555) );
XOR2X1TS U8708 ( .A(n6557), .B(n6556), .Y(n6734) );
INVX2TS U8709 ( .A(n6558), .Y(n6560) );
XOR2X1TS U8710 ( .A(n6562), .B(n6561), .Y(n6720) );
INVX2TS U8711 ( .A(n6563), .Y(n6565) );
CMPR32X2TS U8712 ( .A(n6574), .B(n6573), .C(n6572), .CO(n6577), .S(n6778) );
CMPR32X2TS U8713 ( .A(n6580), .B(n6579), .C(n6578), .CO(n6583), .S(n6693) );
CMPR32X2TS U8714 ( .A(n6583), .B(n6582), .C(n6581), .CO(n6584), .S(n6685) );
CMPR32X2TS U8715 ( .A(n6586), .B(n6585), .C(n6584), .CO(n6587), .S(n6680) );
CMPR32X2TS U8716 ( .A(n6589), .B(n6588), .C(n6587), .CO(n6590), .S(n6672) );
CMPR32X2TS U8717 ( .A(n6592), .B(n6591), .C(n6590), .CO(n6593), .S(n6666) );
CMPR32X2TS U8718 ( .A(n6597), .B(n6596), .C(n6595), .CO(n6598), .S(n6652) );
NAND2X1TS U8719 ( .A(n6813), .B(n6612), .Y(n6604) );
INVX2TS U8720 ( .A(n6814), .Y(n6602) );
INVX2TS U8721 ( .A(n6813), .Y(n6611) );
INVX2TS U8722 ( .A(n6817), .Y(n6610) );
INVX2TS U8723 ( .A(n6617), .Y(n6619) );
INVX2TS U8724 ( .A(n6624), .Y(n6626) );
NAND2X1TS U8725 ( .A(n6626), .B(n6625), .Y(n6627) );
INVX2TS U8726 ( .A(n6630), .Y(n6642) );
INVX2TS U8727 ( .A(n6639), .Y(n6641) );
INVX2TS U8728 ( .A(n6647), .Y(n6649) );
INVX2TS U8729 ( .A(n6661), .Y(n6663) );
INVX2TS U8730 ( .A(n7002), .Y(n6788) );
INVX2TS U8731 ( .A(n6675), .Y(n6677) );
INVX2TS U8732 ( .A(n7000), .Y(n6785) );
INVX2TS U8733 ( .A(n6998), .Y(n6931) );
INVX2TS U8734 ( .A(n6688), .Y(n6690) );
INVX2TS U8735 ( .A(n6991), .Y(n6934) );
AFHCINX2TS U8736 ( .CIN(n6696), .B(n6697), .A(n6698), .S(n8540), .CO(n6691)
);
INVX2TS U8737 ( .A(n8540), .Y(n6937) );
INVX2TS U8738 ( .A(n6707), .Y(n6709) );
INVX2TS U8739 ( .A(n8552), .Y(n6765) );
INVX2TS U8740 ( .A(n6715), .Y(n6717) );
NAND2X1TS U8741 ( .A(n6717), .B(n6716), .Y(n6719) );
NAND2X1TS U8742 ( .A(n1067), .B(n6723), .Y(n6725) );
XNOR2X1TS U8743 ( .A(n6725), .B(n6724), .Y(n8558) );
INVX2TS U8744 ( .A(n8558), .Y(n6760) );
INVX2TS U8745 ( .A(n6729), .Y(n6731) );
NAND2X1TS U8746 ( .A(n6731), .B(n6730), .Y(n6733) );
XOR2X1TS U8747 ( .A(n6733), .B(n6732), .Y(n8561) );
INVX2TS U8748 ( .A(n8561), .Y(n6758) );
NAND2X1TS U8749 ( .A(n1099), .B(n6739), .Y(n6741) );
XNOR2X1TS U8750 ( .A(n6741), .B(n6740), .Y(n8564) );
INVX2TS U8751 ( .A(n8564), .Y(n6752) );
XNOR2X1TS U8752 ( .A(n1101), .B(n6749), .Y(n6750) );
NOR2X1TS U8753 ( .A(n6748), .B(n6750), .Y(n6969) );
INVX2TS U8754 ( .A(n6969), .Y(n6973) );
NAND2X1TS U8755 ( .A(n974), .B(n6973), .Y(n6756) );
INVX2TS U8756 ( .A(n6974), .Y(n6968) );
NAND2X1TS U8757 ( .A(n6748), .B(n6750), .Y(n6972) );
INVX2TS U8758 ( .A(n6972), .Y(n6754) );
NAND2X1TS U8759 ( .A(n6752), .B(n6751), .Y(n6967) );
INVX2TS U8760 ( .A(n6967), .Y(n6753) );
OAI21X2TS U8761 ( .A0(n6756), .A1(n6968), .B0(n6755), .Y(n6965) );
INVX2TS U8762 ( .A(n6964), .Y(n6961) );
INVX2TS U8763 ( .A(n6960), .Y(n6761) );
INVX2TS U8764 ( .A(n6952), .Y(n6767) );
AFHCINX2TS U8765 ( .CIN(n6775), .B(n6776), .A(n6777), .S(n8546), .CO(n6781)
);
INVX2TS U8766 ( .A(n8546), .Y(n6941) );
AFHCONX2TS U8767 ( .A(n6783), .B(n6782), .CI(n6781), .CON(n6696), .S(n8543)
);
INVX2TS U8768 ( .A(n6922), .Y(n6793) );
INVX2TS U8769 ( .A(n6920), .Y(n6796) );
NAND2X1TS U8770 ( .A(n6815), .B(n6814), .Y(n6816) );
INVX2TS U8771 ( .A(n6822), .Y(n6823) );
CMPR32X2TS U8772 ( .A(n6834), .B(n6833), .C(n6832), .CO(n6395), .S(n10360)
);
ADDHX1TS U8773 ( .A(n10338), .B(n6835), .CO(n6840), .S(n8579) );
ADDHX1TS U8774 ( .A(n10360), .B(n6840), .CO(n6842), .S(n8576) );
INVX2TS U8775 ( .A(n6843), .Y(n6844) );
AOI21X1TS U8776 ( .A0(n1156), .A1(n986), .B0(n6844), .Y(n10116) );
NAND2X1TS U8777 ( .A(n10084), .B(n6872), .Y(n6874) );
NAND2X1TS U8778 ( .A(n6927), .B(n6926), .Y(n6928) );
XOR2X1TS U8779 ( .A(n6928), .B(n1047), .Y(n8566) );
CMPR32X2TS U8780 ( .A(n6931), .B(n6930), .C(n6929), .CO(n6979), .S(n8575) );
CMPR32X2TS U8781 ( .A(n6934), .B(n6933), .C(n6932), .CO(n6929), .S(n8578) );
CMPR32X2TS U8782 ( .A(n6937), .B(n6936), .C(n6935), .CO(n6932), .S(n8582) );
CMPR32X2TS U8783 ( .A(n6940), .B(n6939), .C(n6938), .CO(n6935), .S(n8585) );
CMPR32X2TS U8784 ( .A(n6943), .B(n6942), .C(n6941), .CO(n6940), .S(n8588) );
AFHCINX2TS U8785 ( .CIN(n6944), .B(n6706), .A(n6945), .S(n8591), .CO(n6943)
);
NAND2X1TS U8786 ( .A(n832), .B(n6946), .Y(n6951) );
AOI21X1TS U8787 ( .A0(n6949), .A1(n6965), .B0(n6948), .Y(n6950) );
XOR2X1TS U8788 ( .A(n6951), .B(n6950), .Y(n8594) );
INVX2TS U8789 ( .A(n6954), .Y(n6957) );
XOR2X1TS U8790 ( .A(n6959), .B(n6958), .Y(n8597) );
AOI21X1TS U8791 ( .A0(n1057), .A1(n6965), .B0(n6961), .Y(n6962) );
XOR2X1TS U8792 ( .A(n6963), .B(n6962), .Y(n8600) );
NAND2X1TS U8793 ( .A(n1057), .B(n6964), .Y(n6966) );
NAND2X1TS U8794 ( .A(n974), .B(n6967), .Y(n6971) );
XNOR2X1TS U8795 ( .A(n6971), .B(n6970), .Y(n8606) );
NAND2X1TS U8796 ( .A(n6973), .B(n6972), .Y(n6975) );
XNOR2X1TS U8797 ( .A(n6975), .B(n6974), .Y(n8609) );
CMPR32X2TS U8798 ( .A(n6977), .B(n6488), .C(n6976), .CO(n6974), .S(n8610) );
INVX2TS U8799 ( .A(n8612), .Y(n8608) );
INVX2TS U8800 ( .A(n6981), .Y(n6983) );
INVX2TS U8801 ( .A(n6986), .Y(n6988) );
OAI21X4TS U8802 ( .A0(n8775), .A1(n8509), .B0(n8770), .Y(n8763) );
INVX2TS U8803 ( .A(n7025), .Y(n7026) );
INVX2TS U8804 ( .A(n7226), .Y(n7194) );
INVX2TS U8805 ( .A(n8656), .Y(n7193) );
AOI21X4TS U8806 ( .A0(n7050), .A1(n7061), .B0(n7049), .Y(n7373) );
OAI22X2TS U8807 ( .A0(n7321), .A1(DP_OP_342J35_126_4270_n853), .B0(n7053),
.B1(n728), .Y(n9877) );
XNOR2X2TS U8808 ( .A(Op_MY[50]), .B(Op_MX[48]), .Y(n7255) );
NAND2BXLTS U8809 ( .AN(Op_MY[47]), .B(Op_MX[50]), .Y(n7057) );
XNOR2X1TS U8810 ( .A(Op_MX[50]), .B(Op_MY[47]), .Y(n7058) );
INVX2TS U8811 ( .A(n7250), .Y(n7059) );
NAND2X1TS U8812 ( .A(n7059), .B(n7249), .Y(n7060) );
NOR2X2TS U8813 ( .A(n9850), .B(n9851), .Y(n7177) );
NAND2X1TS U8814 ( .A(n7209), .B(n7158), .Y(n7160) );
NOR2X2TS U8815 ( .A(n838), .B(n760), .Y(n9866) );
NOR2X2TS U8816 ( .A(n750), .B(n761), .Y(n9867) );
NAND2X1TS U8817 ( .A(n9867), .B(n9868), .Y(n7599) );
NOR2X2TS U8818 ( .A(n750), .B(n760), .Y(n9870) );
NAND2X1TS U8819 ( .A(n9870), .B(n9869), .Y(n7600) );
OAI21X1TS U8820 ( .A0(n7602), .A1(n1098), .B0(n7603), .Y(n7587) );
NOR2X2TS U8821 ( .A(n838), .B(n761), .Y(n9864) );
INVX2TS U8822 ( .A(n7585), .Y(n7136) );
AOI21X1TS U8823 ( .A0(n7587), .A1(n823), .B0(n7136), .Y(n7610) );
NOR2X2TS U8824 ( .A(n9829), .B(n760), .Y(n9863) );
INVX2TS U8825 ( .A(n7165), .Y(n7164) );
NAND2X1TS U8826 ( .A(n1091), .B(n7165), .Y(n7166) );
INVX2TS U8827 ( .A(n7209), .Y(n7172) );
INVX2TS U8828 ( .A(n7208), .Y(n7174) );
AOI21X1TS U8829 ( .A0(n7176), .A1(n7210), .B0(n7175), .Y(n7181) );
INVX2TS U8830 ( .A(n7177), .Y(n7179) );
NAND2X1TS U8831 ( .A(n7179), .B(n7178), .Y(n7180) );
AFHCONX2TS U8832 ( .A(n7185), .B(n7184), .CI(DP_OP_342J35_126_4270_n265),
.CON(n7206), .S(n7634) );
INVX2TS U8833 ( .A(n7186), .Y(n7615) );
INVX2TS U8834 ( .A(n7187), .Y(n7189) );
CMPR32X2TS U8835 ( .A(n7194), .B(n7193), .C(n7192), .CO(n7185), .S(n7522) );
INVX2TS U8836 ( .A(n7195), .Y(n7196) );
INVX2TS U8837 ( .A(n7198), .Y(n7200) );
INVX2TS U8838 ( .A(n7211), .Y(n7213) );
XNOR2X4TS U8839 ( .A(Op_MX[50]), .B(Op_MX[51]), .Y(n8753) );
INVX2TS U8840 ( .A(n7287), .Y(n7256) );
INVX2TS U8841 ( .A(n7290), .Y(n7272) );
NOR2X1TS U8842 ( .A(n728), .B(DP_OP_342J35_126_4270_n853), .Y(n7319) );
INVX2TS U8843 ( .A(n7339), .Y(n7300) );
INVX2TS U8844 ( .A(n7307), .Y(n9764) );
INVX2TS U8845 ( .A(n7342), .Y(n7325) );
INVX2TS U8846 ( .A(n8723), .Y(n7351) );
NOR2X2TS U8847 ( .A(n7342), .B(n7339), .Y(n8738) );
INVX2TS U8848 ( .A(n8737), .Y(n7348) );
INVX2TS U8849 ( .A(n8738), .Y(n7375) );
INVX2TS U8850 ( .A(n8744), .Y(n7376) );
NOR2X2TS U8851 ( .A(n9775), .B(n9774), .Y(n8741) );
INVX2TS U8852 ( .A(n8741), .Y(n7385) );
AFHCONX2TS U8853 ( .A(n7419), .B(n7418), .CI(n7417), .CON(n7420), .S(n9751)
);
AFHCINX2TS U8854 ( .CIN(n7420), .B(n7421), .A(n7422), .S(n9750), .CO(n8471)
);
CMPR32X2TS U8855 ( .A(n7425), .B(n7424), .C(n7423), .CO(n8467), .S(n9753) );
CMPR32X2TS U8856 ( .A(Op_MX[33]), .B(Op_MX[46]), .C(n7426), .CO(n2976), .S(
n7446) );
INVX2TS U8857 ( .A(n9633), .Y(n9632) );
CMPR32X2TS U8858 ( .A(Op_MY[31]), .B(Op_MY[44]), .C(n7436), .CO(n7439), .S(
n9619) );
CMPR32X2TS U8859 ( .A(Op_MY[30]), .B(Op_MY[43]), .C(n7437), .CO(n7436), .S(
n9604) );
CMPR32X2TS U8860 ( .A(Op_MY[32]), .B(Op_MY[45]), .C(n7439), .CO(n7435), .S(
n9658) );
CMPR32X2TS U8861 ( .A(n9632), .B(n9656), .C(n7441), .CO(n7442), .S(n7440) );
CMPR32X2TS U8862 ( .A(n7444), .B(n7446), .C(n7443), .CO(n7433), .S(n7445) );
INVX2TS U8863 ( .A(n9656), .Y(n9654) );
AOI2BB2X4TS U8864 ( .B0(n7446), .B1(n9607), .A0N(n9607), .A1N(n7446), .Y(
n9647) );
INVX2TS U8865 ( .A(n9658), .Y(n9616) );
OAI22X1TS U8866 ( .A0(n9654), .A1(n9647), .B0(n9616), .B1(n9601), .Y(n7451)
);
INVX2TS U8867 ( .A(n9522), .Y(n7448) );
AOI22X1TS U8868 ( .A0(n7429), .A1(n7448), .B0(n9522), .B1(n9618), .Y(n7447)
);
OAI221X4TS U8869 ( .A0(n9522), .A1(n7432), .B0(n7448), .B1(n9607), .C0(n9615), .Y(n9613) );
AOI22X1TS U8870 ( .A0(n7432), .A1(n9654), .B0(n9656), .B1(n9607), .Y(n9602)
);
OAI21X1TS U8871 ( .A0(n9618), .A1(n7448), .B0(n7432), .Y(n7449) );
INVX2TS U8872 ( .A(n7450), .Y(n7453) );
INVX2TS U8873 ( .A(n9619), .Y(n9620) );
OAI22X1TS U8874 ( .A0(n9616), .A1(n9647), .B0(n9620), .B1(n9601), .Y(n7452)
);
CMPR32X2TS U8875 ( .A(n7453), .B(n7452), .C(DP_OP_341J35_125_6458_n413),
.CO(n9643), .S(n9518) );
AOI22X1TS U8876 ( .A0(n7432), .A1(n9600), .B0(n7491), .B1(n9607), .Y(n9612)
);
AOI22X1TS U8877 ( .A0(n7432), .A1(n9648), .B0(n7487), .B1(n9607), .Y(n7454)
);
OAI22X1TS U8878 ( .A0(n9615), .A1(n9612), .B0(n9613), .B1(n7454), .Y(n7460)
);
INVX2TS U8879 ( .A(n9554), .Y(n9670) );
AOI22X1TS U8880 ( .A0(n2968), .A1(n9670), .B0(n9554), .B1(
DP_OP_341J35_125_6458_n466), .Y(n7455) );
BUFX3TS U8881 ( .A(n7455), .Y(n9625) );
INVX2TS U8882 ( .A(n9604), .Y(n9605) );
AOI22X1TS U8883 ( .A0(n7429), .A1(n9605), .B0(n9604), .B1(n9618), .Y(n9622)
);
OAI221X4TS U8884 ( .A0(n9554), .A1(n7429), .B0(n9670), .B1(n9618), .C0(n9625), .Y(n9623) );
INVX2TS U8885 ( .A(n9608), .Y(n9609) );
AOI22X1TS U8886 ( .A0(n7429), .A1(n9609), .B0(n9608), .B1(n9618), .Y(n7457)
);
OAI22X1TS U8887 ( .A0(n9625), .A1(n9622), .B0(n9623), .B1(n7457), .Y(n7459)
);
AOI22X1TS U8888 ( .A0(n2968), .A1(n9620), .B0(n9619), .B1(
DP_OP_341J35_125_6458_n466), .Y(n7456) );
OAI32X1TS U8889 ( .A0(n9659), .A1(n9604), .A2(DP_OP_341J35_125_6458_n466),
.B0(n7456), .B1(n3003), .Y(n7464) );
AOI22X1TS U8890 ( .A0(n7429), .A1(n9600), .B0(n7491), .B1(n9618), .Y(n7467)
);
OAI22X1TS U8891 ( .A0(n9625), .A1(n7457), .B0(n9623), .B1(n7467), .Y(n7462)
);
CMPR32X2TS U8892 ( .A(n7460), .B(n7459), .C(n7458), .CO(n7620), .S(n9568) );
AOI22X1TS U8893 ( .A0(n2968), .A1(n9616), .B0(n9658), .B1(
DP_OP_341J35_125_6458_n466), .Y(n7461) );
OAI32X1TS U8894 ( .A0(n9659), .A1(n9619), .A2(DP_OP_341J35_125_6458_n466),
.B0(n7461), .B1(n3003), .Y(n9678) );
CMPR32X2TS U8895 ( .A(n7464), .B(n7463), .C(n7462), .CO(n7458), .S(n9550) );
AOI22X1TS U8896 ( .A0(n2968), .A1(n9605), .B0(n9604), .B1(
DP_OP_341J35_125_6458_n466), .Y(n7465) );
OAI32X1TS U8897 ( .A0(n9659), .A1(n9608), .A2(DP_OP_341J35_125_6458_n466),
.B0(n7465), .B1(n3003), .Y(n7469) );
AOI22X1TS U8898 ( .A0(n7429), .A1(n9648), .B0(n7487), .B1(n9618), .Y(n7466)
);
OAI22X1TS U8899 ( .A0(n9625), .A1(n7467), .B0(n9623), .B1(n7466), .Y(n7468)
);
ADDHXLTS U8900 ( .A(n7469), .B(n7468), .CO(n9549), .S(n9571) );
AOI22X1TS U8901 ( .A0(n2968), .A1(n9609), .B0(n9608), .B1(
DP_OP_341J35_125_6458_n466), .Y(n7470) );
OAI32X1TS U8902 ( .A0(n9659), .A1(n7491), .A2(DP_OP_341J35_125_6458_n466),
.B0(n7470), .B1(n3003), .Y(n9574) );
ADDHX1TS U8903 ( .A(n7472), .B(n7471), .CO(n9572), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[1]) );
OAI31X1TS U8904 ( .A0(n9654), .A1(n7474), .A2(n9601), .B0(n7473), .Y(n7475)
);
INVX2TS U8905 ( .A(n9575), .Y(n9661) );
OAI22X1TS U8906 ( .A0(n9575), .A1(n9593), .B0(n9644), .B1(n9661), .Y(n7480)
);
AOI22X1TS U8907 ( .A0(n2970), .A1(n9632), .B0(n9633), .B1(n9582), .Y(n9577)
);
OAI22X1TS U8908 ( .A0(n2970), .A1(n9588), .B0(n9577), .B1(n9586), .Y(n7479)
);
AOI22X1TS U8909 ( .A0(n9661), .A1(n9590), .B0(n9633), .B1(n9575), .Y(n7498)
);
INVX2TS U8910 ( .A(n7480), .Y(n7497) );
OAI21X1TS U8911 ( .A0(n9592), .A1(n7478), .B0(n9582), .Y(n7496) );
CMPR32X2TS U8912 ( .A(n7480), .B(n7479), .C(DP_OP_341J35_125_6458_n256),
.CO(n7501), .S(n7483) );
CMPR32X2TS U8913 ( .A(DP_OP_341J35_125_6458_n266), .B(
DP_OP_341J35_125_6458_n269), .C(n7481), .CO(n7485), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[8]) );
INVX2TS U8914 ( .A(n9757), .Y(n7507) );
CMPR32X2TS U8915 ( .A(n7483), .B(DP_OP_341J35_125_6458_n257), .C(n7482),
.CO(n7499), .S(n9698) );
INVX2TS U8916 ( .A(n9698), .Y(n7509) );
CMPR32X2TS U8917 ( .A(DP_OP_341J35_125_6458_n258), .B(
DP_OP_341J35_125_6458_n260), .C(n7484), .CO(n7482), .S(n9704) );
INVX2TS U8918 ( .A(n9704), .Y(n7511) );
CMPR32X2TS U8919 ( .A(DP_OP_341J35_125_6458_n261), .B(
DP_OP_341J35_125_6458_n265), .C(n7485), .CO(n7484), .S(n9706) );
INVX2TS U8920 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[0]), .Y(n7618) );
INVX2TS U8921 ( .A(n8458), .Y(n7617) );
ADDHXLTS U8922 ( .A(n7487), .B(n7486), .CO(n7492), .S(n7488) );
ADDHXLTS U8923 ( .A(n9659), .B(n9636), .CO(n7494), .S(n7489) );
INVX2TS U8924 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[1]), .Y(n9563) );
CMPR32X2TS U8925 ( .A(n7498), .B(n7497), .C(n7496), .CO(n7505), .S(n7500) );
CMPR32X2TS U8926 ( .A(n7501), .B(n7500), .C(n7499), .CO(n7503), .S(n9757) );
OAI31X1TS U8927 ( .A0(n9633), .A1(n7503), .A2(n9575), .B0(n7502), .Y(n7504)
);
CMPR32X2TS U8928 ( .A(DP_OP_341J35_125_6458_n27), .B(n7507), .C(n7506), .CO(
n7632), .S(n7639) );
CMPR32X2TS U8929 ( .A(DP_OP_341J35_125_6458_n33), .B(n7509), .C(n7508), .CO(
n7506), .S(n7641) );
CMPR32X2TS U8930 ( .A(DP_OP_341J35_125_6458_n41), .B(n7511), .C(n7510), .CO(
n7508), .S(n7643) );
CMPR32X2TS U8931 ( .A(DP_OP_341J35_125_6458_n50), .B(n7513), .C(n7512), .CO(
n7510), .S(n7645) );
CMPR32X2TS U8932 ( .A(DP_OP_341J35_125_6458_n61), .B(n7515), .C(n7514), .CO(
n7512), .S(n7647) );
CMPR32X2TS U8933 ( .A(DP_OP_341J35_125_6458_n74), .B(n7517), .C(n7516), .CO(
n7514), .S(n7649) );
CMPR32X2TS U8934 ( .A(n7519), .B(n7518), .C(DP_OP_341J35_125_6458_n123),
.CO(n7625), .S(n8396) );
CMPR32X2TS U8935 ( .A(DP_OP_341J35_125_6458_n423), .B(
DP_OP_341J35_125_6458_n427), .C(n7520), .CO(n9528), .S(n9529) );
CMPR32X2TS U8936 ( .A(DP_OP_341J35_125_6458_n428), .B(
DP_OP_341J35_125_6458_n430), .C(n7521), .CO(n7520), .S(n9537) );
NOR2X2TS U8937 ( .A(n758), .B(n955), .Y(n7911) );
NAND2X1TS U8938 ( .A(n7911), .B(n7899), .Y(n7597) );
INVX2TS U8939 ( .A(n7597), .Y(n7594) );
NOR2X2TS U8940 ( .A(n758), .B(n812), .Y(n7901) );
INVX2TS U8941 ( .A(n7593), .Y(n7527) );
NOR2X1TS U8942 ( .A(n7594), .B(n7527), .Y(n7591) );
NAND2X1TS U8943 ( .A(n7893), .B(n7889), .Y(n7589) );
INVX2TS U8944 ( .A(n7582), .Y(n7533) );
INVX2TS U8945 ( .A(n8215), .Y(n7576) );
INVX2TS U8946 ( .A(n8213), .Y(n7567) );
INVX2TS U8947 ( .A(n8309), .Y(n7947) );
INVX2TS U8948 ( .A(n9318), .Y(n7946) );
NOR2X1TS U8949 ( .A(n7909), .B(n7943), .Y(n7945) );
INVX2TS U8950 ( .A(n8210), .Y(n7574) );
NAND2X1TS U8951 ( .A(n7574), .B(n8212), .Y(n7575) );
CLKXOR2X2TS U8952 ( .A(n7576), .B(n7575), .Y(n9334) );
INVX2TS U8953 ( .A(n7577), .Y(n7579) );
NAND2X1TS U8954 ( .A(n7579), .B(n7578), .Y(n7581) );
CLKXOR2X2TS U8955 ( .A(n7581), .B(n7580), .Y(n9331) );
NAND2X1TS U8956 ( .A(n1069), .B(n7582), .Y(n7584) );
XNOR2X2TS U8957 ( .A(n7584), .B(n7583), .Y(n9329) );
NAND2X1TS U8958 ( .A(n823), .B(n7585), .Y(n7586) );
XNOR2X1TS U8959 ( .A(n7587), .B(n7586), .Y(n8668) );
INVX2TS U8960 ( .A(n8668), .Y(n9718) );
INVX2TS U8961 ( .A(n7588), .Y(n7590) );
NAND2X1TS U8962 ( .A(n7590), .B(n7589), .Y(n7592) );
CLKXOR2X2TS U8963 ( .A(n7592), .B(n7591), .Y(n9326) );
NAND2X1TS U8964 ( .A(n1115), .B(n7593), .Y(n7595) );
XNOR2X2TS U8965 ( .A(n7595), .B(n7594), .Y(n9324) );
INVX2TS U8966 ( .A(n9324), .Y(n9725) );
NAND2X1TS U8967 ( .A(n1097), .B(n7599), .Y(n7601) );
XOR2X1TS U8968 ( .A(n7601), .B(n7600), .Y(n8662) );
INVX2TS U8969 ( .A(n8662), .Y(n9723) );
INVX2TS U8970 ( .A(n7602), .Y(n7604) );
NAND2X1TS U8971 ( .A(n7604), .B(n7603), .Y(n7605) );
INVX2TS U8972 ( .A(n7606), .Y(n7608) );
INVX2TS U8973 ( .A(n8671), .Y(n9714) );
INVX2TS U8974 ( .A(n7611), .Y(n7613) );
INVX2TS U8975 ( .A(n8674), .Y(n7621) );
CMPR32X2TS U8976 ( .A(n7618), .B(n7617), .C(n7616), .CO(n9514), .S(n9711) );
CMPR32X2TS U8977 ( .A(DP_OP_341J35_125_6458_n431), .B(n7620), .C(n7619),
.CO(n7521), .S(n9545) );
CMPR32X2TS U8978 ( .A(n7625), .B(n7624), .C(DP_OP_341J35_125_6458_n116),
.CO(n7627), .S(n8385) );
CMPR32X2TS U8979 ( .A(n7627), .B(n7626), .C(DP_OP_341J35_125_6458_n108),
.CO(n7629), .S(n8375) );
CMPR32X2TS U8980 ( .A(n7629), .B(n7628), .C(DP_OP_341J35_125_6458_n98), .CO(
n7631), .S(n7652) );
CMPR32X2TS U8981 ( .A(n7631), .B(n7630), .C(DP_OP_341J35_125_6458_n87), .CO(
n7516), .S(n7650) );
CMPR32X2TS U8982 ( .A(n7632), .B(DP_OP_341J35_125_6458_n22), .C(n9639), .CO(
n9628), .S(n7636) );
AFHCINX2TS U8983 ( .CIN(n7633), .B(n7634), .A(n7635), .S(n9754), .CO(n7425)
);
CMPR32X2TS U8984 ( .A(n7637), .B(DP_OP_344J35_128_4078_n64), .C(n7636), .CO(
n9691), .S(n8460) );
CMPR32X2TS U8985 ( .A(n7639), .B(DP_OP_344J35_128_4078_n67), .C(n7638), .CO(
n7637), .S(n8675) );
CMPR32X2TS U8986 ( .A(n7641), .B(DP_OP_344J35_128_4078_n70), .C(n7640), .CO(
n7638), .S(n8672) );
CMPR32X2TS U8987 ( .A(DP_OP_344J35_128_4078_n73), .B(n7643), .C(n7642), .CO(
n7640), .S(n8669) );
CMPR32X2TS U8988 ( .A(n7645), .B(DP_OP_344J35_128_4078_n76), .C(n7644), .CO(
n7642), .S(n8666) );
CMPR32X2TS U8989 ( .A(DP_OP_344J35_128_4078_n79), .B(n7647), .C(n7646), .CO(
n7644), .S(n8663) );
CMPR32X2TS U8990 ( .A(DP_OP_344J35_128_4078_n82), .B(n7649), .C(n7648), .CO(
n7646), .S(n8660) );
CMPR32X2TS U8991 ( .A(n7651), .B(n7650), .C(DP_OP_344J35_128_4078_n85), .CO(
n7648), .S(n8657) );
CMPR32X2TS U8992 ( .A(n7653), .B(n7652), .C(DP_OP_344J35_128_4078_n88), .CO(
n7651), .S(n8654) );
INVX2TS U8993 ( .A(n7663), .Y(n7657) );
NAND2X1TS U8994 ( .A(n7657), .B(n7662), .Y(n7658) );
INVX2TS U8995 ( .A(n7668), .Y(n7665) );
INVX2TS U8996 ( .A(n7687), .Y(n7689) );
NAND2X1TS U8997 ( .A(n7689), .B(n7688), .Y(n7691) );
INVX2TS U8998 ( .A(n7694), .Y(n7696) );
INVX2TS U8999 ( .A(n7700), .Y(n7702) );
INVX2TS U9000 ( .A(n8137), .Y(n7768) );
INVX2TS U9001 ( .A(n8139), .Y(n7789) );
OAI22X1TS U9002 ( .A0(n7900), .A1(n7847), .B0(n7910), .B1(n8018), .Y(n7897)
);
INVX2TS U9003 ( .A(n8315), .Y(n7850) );
INVX2TS U9004 ( .A(n8326), .Y(n7849) );
INVX2TS U9005 ( .A(n8130), .Y(n7851) );
INVX2TS U9006 ( .A(n8221), .Y(n8008) );
INVX2TS U9007 ( .A(n8132), .Y(n7844) );
OAI22X1TS U9008 ( .A0(n8093), .A1(n7943), .B0(n8082), .B1(n7910), .Y(n7864)
);
INVX2TS U9009 ( .A(n7842), .Y(n7965) );
INVX2TS U9010 ( .A(n7843), .Y(n7921) );
INVX2TS U9011 ( .A(n7848), .Y(n7903) );
INVX2TS U9012 ( .A(n7854), .Y(n7963) );
INVX2TS U9013 ( .A(n7882), .Y(n7927) );
INVX2TS U9014 ( .A(n7889), .Y(n7933) );
INVX2TS U9015 ( .A(n7893), .Y(n7931) );
INVX2TS U9016 ( .A(n7894), .Y(n7918) );
INVX2TS U9017 ( .A(n8314), .Y(n7907) );
INVX2TS U9018 ( .A(n7899), .Y(n7906) );
INVX2TS U9019 ( .A(n7901), .Y(n7937) );
NOR2X1TS U9020 ( .A(n7998), .B(n7943), .Y(n7930) );
INVX2TS U9021 ( .A(n7911), .Y(n7940) );
INVX2TS U9022 ( .A(n7915), .Y(n7962) );
NOR2X1TS U9023 ( .A(n7944), .B(n7943), .Y(n7948) );
AFHCONX2TS U9024 ( .A(n7947), .B(n7946), .CI(n7945), .CON(n8233), .S(n7571)
);
INVX2TS U9025 ( .A(n8225), .Y(n7952) );
INVX2TS U9026 ( .A(n8255), .Y(n7957) );
AOI21X2TS U9027 ( .A0(n1206), .A1(n8256), .B0(n7957), .Y(n8294) );
INVX2TS U9028 ( .A(n8246), .Y(n8057) );
INVX2TS U9029 ( .A(n8245), .Y(n8035) );
INVX2TS U9030 ( .A(n8251), .Y(n8072) );
NOR2X2TS U9031 ( .A(n740), .B(n8096), .Y(n8288) );
INVX2TS U9032 ( .A(n8288), .Y(n8094) );
NOR2X2TS U9033 ( .A(n8139), .B(n8138), .Y(n8183) );
NOR2X2TS U9034 ( .A(n8137), .B(n8136), .Y(n8181) );
NOR2X1TS U9035 ( .A(n8183), .B(n8181), .Y(n8141) );
INVX2TS U9036 ( .A(n8316), .Y(n8328) );
INVX2TS U9037 ( .A(n8327), .Y(n8128) );
NOR2X1TS U9038 ( .A(n8328), .B(n8128), .Y(n8342) );
INVX2TS U9039 ( .A(n8207), .Y(n8133) );
OAI21X1TS U9040 ( .A0(n8183), .A1(n8180), .B0(n8184), .Y(n8140) );
NOR2X2TS U9041 ( .A(n8143), .B(n8142), .Y(n8154) );
INVX2TS U9042 ( .A(n8154), .Y(n8144) );
NAND2X1TS U9043 ( .A(n8144), .B(n8156), .Y(n8145) );
INVX2TS U9044 ( .A(n8146), .Y(n8147) );
NOR2X2TS U9045 ( .A(n8150), .B(n8149), .Y(n8157) );
NAND2X1TS U9046 ( .A(n8151), .B(n8155), .Y(n8152) );
NOR2X1TS U9047 ( .A(n8154), .B(n8157), .Y(n8367) );
INVX2TS U9048 ( .A(n8367), .Y(n8159) );
OAI21X1TS U9049 ( .A0(n8157), .A1(n8156), .B0(n8155), .Y(n8370) );
INVX2TS U9050 ( .A(n8370), .Y(n8158) );
OAI21X1TS U9051 ( .A0(n8373), .A1(n8159), .B0(n8158), .Y(n8163) );
NAND2X1TS U9052 ( .A(n8161), .B(n8160), .Y(n8368) );
NAND2X1TS U9053 ( .A(n1127), .B(n8368), .Y(n8162) );
INVX2TS U9054 ( .A(n8189), .Y(n8165) );
INVX2TS U9055 ( .A(n8188), .Y(n8166) );
INVX2TS U9056 ( .A(n8169), .Y(n8171) );
INVX2TS U9057 ( .A(n8181), .Y(n8174) );
NAND2X1TS U9058 ( .A(n8174), .B(n8180), .Y(n8176) );
INVX2TS U9059 ( .A(n8175), .Y(n8182) );
NAND2X1TS U9060 ( .A(n8185), .B(n8184), .Y(n8186) );
INVX2TS U9061 ( .A(n8195), .Y(n8197) );
NAND2X1TS U9062 ( .A(n8197), .B(n8196), .Y(n8199) );
INVX2TS U9063 ( .A(n8240), .Y(n8228) );
INVX2TS U9064 ( .A(n8243), .Y(n8219) );
INVX2TS U9065 ( .A(n8244), .Y(n8222) );
NAND2X1TS U9066 ( .A(n8222), .B(n8242), .Y(n8223) );
NAND2X1TS U9067 ( .A(n1204), .B(n8225), .Y(n8227) );
INVX2TS U9068 ( .A(n8230), .Y(n8232) );
NAND2X1TS U9069 ( .A(n8232), .B(n8231), .Y(n8234) );
INVX2TS U9070 ( .A(n8619), .Y(n8239) );
INVX2TS U9071 ( .A(n8278), .Y(n8241) );
NOR2X1TS U9072 ( .A(n8241), .B(n8277), .Y(n8249) );
INVX2TS U9073 ( .A(n8284), .Y(n8247) );
NOR2X2TS U9074 ( .A(n8251), .B(n8250), .Y(n8280) );
INVX2TS U9075 ( .A(n8280), .Y(n8252) );
NAND2X1TS U9076 ( .A(n8251), .B(n8250), .Y(n8279) );
NAND2X1TS U9077 ( .A(n8252), .B(n8279), .Y(n8253) );
INVX2TS U9078 ( .A(n8277), .Y(n8259) );
INVX2TS U9079 ( .A(n8262), .Y(n8264) );
INVX2TS U9080 ( .A(n8627), .Y(n8271) );
NAND2X1TS U9081 ( .A(n8289), .B(n8288), .Y(n8296) );
INVX2TS U9082 ( .A(n8296), .Y(n8290) );
INVX2TS U9083 ( .A(n8291), .Y(n8293) );
NAND2X1TS U9084 ( .A(n1073), .B(n8296), .Y(n8297) );
NAND2X1TS U9085 ( .A(n1203), .B(n8327), .Y(n8329) );
INVX2TS U9086 ( .A(n8339), .Y(n8341) );
NAND2X1TS U9087 ( .A(n8341), .B(n8340), .Y(n8343) );
AOI21X4TS U9088 ( .A0(n8351), .A1(n8420), .B0(n8350), .Y(n8417) );
NAND2X1TS U9089 ( .A(n8367), .B(n1127), .Y(n8372) );
INVX2TS U9090 ( .A(n8368), .Y(n8369) );
AOI21X1TS U9091 ( .A0(n8370), .A1(n1127), .B0(n8369), .Y(n8371) );
CMPR32X2TS U9092 ( .A(n8376), .B(n8375), .C(DP_OP_344J35_128_4078_n91), .CO(
n7653), .S(n8652) );
NAND2X1TS U9093 ( .A(n8391), .B(n8401), .Y(n8378) );
INVX2TS U9094 ( .A(n8382), .Y(n8383) );
CMPR32X2TS U9095 ( .A(n8386), .B(n8385), .C(DP_OP_344J35_128_4078_n94), .CO(
n8376), .S(n8650) );
CMPR32X2TS U9096 ( .A(DP_OP_344J35_128_4078_n97), .B(n8396), .C(n8395), .CO(
n8386), .S(n8648) );
INVX2TS U9097 ( .A(n8397), .Y(n8400) );
INVX2TS U9098 ( .A(n8398), .Y(n8399) );
CMPR32X2TS U9099 ( .A(DP_OP_344J35_128_4078_n100), .B(n9529), .C(n8405),
.CO(n8395), .S(n8646) );
INVX2TS U9100 ( .A(n8406), .Y(n8408) );
CMPR32X2TS U9101 ( .A(n9537), .B(n8412), .C(n8411), .CO(n8405), .S(n8644) );
CMPR32X2TS U9102 ( .A(n9545), .B(n8419), .C(n8418), .CO(n8411), .S(n8642) );
INVX2TS U9103 ( .A(n8453), .Y(n8455) );
CMPR32X2TS U9104 ( .A(n7193), .B(n7946), .C(n8458), .CO(
DP_OP_344J35_128_4078_n40), .S(n8635) );
INVX2TS U9105 ( .A(n8676), .Y(n8461) );
CMPR32X2TS U9106 ( .A(n8467), .B(n8466), .C(n8465), .CO(n7418), .S(n9752) );
AOI21X4TS U9107 ( .A0(n8469), .A1(n8689), .B0(n8468), .Y(n8717) );
INVX2TS U9108 ( .A(n8490), .Y(n8491) );
AFHCINX2TS U9109 ( .CIN(n8541), .B(n8542), .A(n8543), .S(n10670), .CO(n8538)
);
INVX2TS U9110 ( .A(n10670), .Y(n8881) );
AFHCONX2TS U9111 ( .A(n8546), .B(n8545), .CI(n8544), .CON(n8541), .S(n10666)
);
AFHCINX2TS U9112 ( .CIN(n8547), .B(n8548), .A(n8549), .S(n10662), .CO(n8544)
);
INVX2TS U9113 ( .A(n10662), .Y(n8893) );
AFHCONX2TS U9114 ( .A(n8552), .B(n8551), .CI(n8550), .CON(n8547), .S(n10658)
);
AFHCINX2TS U9115 ( .CIN(n8553), .B(n8554), .A(n8555), .S(n10654), .CO(n8550)
);
AFHCONX2TS U9116 ( .A(n8558), .B(n8557), .CI(n8556), .CON(n8553), .S(n10650)
);
AFHCINX2TS U9117 ( .CIN(n8559), .B(n8560), .A(n8561), .S(n10646), .CO(n8557)
);
AFHCONX2TS U9118 ( .A(n8564), .B(n8563), .CI(n8562), .CON(n8559), .S(n10641)
);
AFHCINX2TS U9119 ( .CIN(n8565), .B(n8566), .A(n8567), .S(n10636), .CO(n8562)
);
INVX2TS U9120 ( .A(n10636), .Y(n8931) );
AFHCONX2TS U9121 ( .A(n8570), .B(n8569), .CI(n8568), .CON(n8565), .S(n10633)
);
INVX2TS U9122 ( .A(n10631), .Y(n8943) );
CMPR32X2TS U9123 ( .A(n8576), .B(n8575), .C(n8574), .CO(n8573), .S(n10451)
);
INVX2TS U9124 ( .A(n10451), .Y(n8949) );
CMPR32X2TS U9125 ( .A(n8579), .B(n8578), .C(n8577), .CO(n8574), .S(n10629)
);
INVX2TS U9126 ( .A(n10629), .Y(n8955) );
AFHCINX2TS U9127 ( .CIN(n8580), .B(n8581), .A(n8582), .S(n10628), .CO(n8577)
);
INVX2TS U9128 ( .A(n10628), .Y(n8961) );
AFHCONX2TS U9129 ( .A(n8585), .B(n8584), .CI(n8583), .CON(n8580), .S(n10627)
);
INVX2TS U9130 ( .A(n10627), .Y(n8967) );
AFHCINX2TS U9131 ( .CIN(n8586), .B(n8587), .A(n8588), .S(n10626), .CO(n8583)
);
INVX2TS U9132 ( .A(n10626), .Y(n8973) );
AFHCONX2TS U9133 ( .A(n8591), .B(n8590), .CI(n8589), .CON(n8586), .S(n10625)
);
INVX2TS U9134 ( .A(n10625), .Y(n8979) );
AFHCINX2TS U9135 ( .CIN(n8592), .B(n8593), .A(n8594), .S(n10624), .CO(n8589)
);
INVX2TS U9136 ( .A(n10624), .Y(n8985) );
AFHCONX2TS U9137 ( .A(n8597), .B(n8596), .CI(n8595), .CON(n8592), .S(n10623)
);
INVX2TS U9138 ( .A(n10623), .Y(n8991) );
AFHCINX2TS U9139 ( .CIN(n8598), .B(n8599), .A(n8600), .S(n10622), .CO(n8595)
);
INVX2TS U9140 ( .A(n10622), .Y(n8997) );
AFHCONX2TS U9141 ( .A(n8603), .B(n8602), .CI(n8601), .CON(n8598), .S(n10621)
);
INVX2TS U9142 ( .A(n10621), .Y(n9006) );
AFHCINX2TS U9143 ( .CIN(n8604), .B(n8605), .A(n8606), .S(n10620), .CO(n8601)
);
INVX2TS U9144 ( .A(n10620), .Y(n9012) );
AFHCONX2TS U9145 ( .A(n8609), .B(n8608), .CI(n8607), .CON(n8604), .S(n10619)
);
INVX2TS U9146 ( .A(n10619), .Y(n9018) );
INVX2TS U9147 ( .A(n8614), .Y(n8616) );
INVX2TS U9148 ( .A(n8622), .Y(n8626) );
INVX2TS U9149 ( .A(n8630), .Y(n8632) );
ADDHX1TS U9150 ( .A(n9735), .B(n8635), .CO(n8636), .S(n9346) );
INVX2TS U9151 ( .A(n9346), .Y(n9023) );
CMPR32X2TS U9152 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[1]), .B(
n9734), .C(n8636), .CO(n8637), .S(n9349) );
INVX2TS U9153 ( .A(n9349), .Y(n9019) );
CMPR32X2TS U9154 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[2]), .B(
n9733), .C(n8637), .CO(n8638), .S(n9351) );
INVX2TS U9155 ( .A(n9351), .Y(n9016) );
CMPR32X2TS U9156 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[3]), .B(
n9732), .C(n8638), .CO(n8639), .S(n9354) );
INVX2TS U9157 ( .A(n9354), .Y(n9010) );
CMPR32X2TS U9158 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[4]), .B(
n9731), .C(n8639), .CO(n8640), .S(n9359) );
INVX2TS U9159 ( .A(n9359), .Y(n9004) );
CMPR32X2TS U9160 ( .A(Sgf_operation_ODD1_left_RECURSIVE_EVEN1_S_B[5]), .B(
n9730), .C(n8640), .CO(n8641), .S(n10889) );
INVX2TS U9161 ( .A(n10889), .Y(n8995) );
CMPR32X2TS U9162 ( .A(n8642), .B(n9729), .C(n8641), .CO(n8643), .S(n10895)
);
INVX2TS U9163 ( .A(n10895), .Y(n8989) );
CMPR32X2TS U9164 ( .A(n8644), .B(n9728), .C(n8643), .CO(n8645), .S(n10453)
);
INVX2TS U9165 ( .A(n10453), .Y(n8983) );
CMPR32X2TS U9166 ( .A(n8646), .B(n9727), .C(n8645), .CO(n8647), .S(n10457)
);
INVX2TS U9167 ( .A(n10457), .Y(n8977) );
CMPR32X2TS U9168 ( .A(n8648), .B(n9726), .C(n8647), .CO(n8649), .S(n10461)
);
INVX2TS U9169 ( .A(n10461), .Y(n8971) );
CMPR32X2TS U9170 ( .A(n8650), .B(n9695), .C(n8649), .CO(n8651), .S(n10466)
);
CMPR32X2TS U9171 ( .A(n8652), .B(n9694), .C(n8651), .CO(n8653), .S(n9371) );
INVX2TS U9172 ( .A(n9371), .Y(n8959) );
CMPR32X2TS U9173 ( .A(n8654), .B(n9693), .C(n8653), .CO(n8655), .S(n9377) );
INVX2TS U9174 ( .A(n9377), .Y(n8953) );
CMPR32X2TS U9175 ( .A(n8657), .B(n8656), .C(n8655), .CO(n8658), .S(n9382) );
INVX2TS U9176 ( .A(n9382), .Y(n8947) );
CMPR32X2TS U9177 ( .A(n8660), .B(n8659), .C(n8658), .CO(n8661), .S(n9385) );
INVX2TS U9178 ( .A(n9385), .Y(n8941) );
CMPR32X2TS U9179 ( .A(n8663), .B(n8662), .C(n8661), .CO(n8664), .S(n9398) );
INVX2TS U9180 ( .A(n9398), .Y(n8935) );
CMPR32X2TS U9181 ( .A(n8666), .B(n8665), .C(n8664), .CO(n8667), .S(n9400) );
INVX2TS U9182 ( .A(n9400), .Y(n8929) );
CMPR32X2TS U9183 ( .A(n8669), .B(n8668), .C(n8667), .CO(n8670), .S(n9410) );
CMPR32X2TS U9184 ( .A(n8672), .B(n8671), .C(n8670), .CO(n8673), .S(n9486) );
CMPR32X2TS U9185 ( .A(n8675), .B(n8674), .C(n8673), .CO(n8677), .S(n9409) );
INVX2TS U9186 ( .A(n9409), .Y(n8909) );
INVX2TS U9187 ( .A(n8749), .Y(n8746) );
AFHCINX2TS U9188 ( .CIN(n8751), .B(n9871), .A(n9872), .S(n8749), .CO(n8756)
);
XNOR2X4TS U9189 ( .A(n8777), .B(n1199), .Y(n9317) );
ADDFHX4TS U9190 ( .A(n8803), .B(n8802), .CI(n8801), .CO(n8795), .S(n9105) );
ADDFHX4TS U9191 ( .A(n8806), .B(n8805), .CI(n8804), .CO(n8802), .S(n9117) );
ADDFHX4TS U9192 ( .A(n8812), .B(n8811), .CI(n8810), .CO(n8804), .S(n9120) );
ADDFHX4TS U9193 ( .A(n8819), .B(n8818), .CI(n8817), .CO(n8811), .S(n9123) );
ADDFHX4TS U9194 ( .A(n8824), .B(n8823), .CI(n8822), .CO(n8817), .S(n9126) );
INVX2TS U9195 ( .A(n8825), .Y(n8826) );
ADDFHX4TS U9196 ( .A(n8831), .B(n8830), .CI(n8829), .CO(n8823), .S(n9129) );
ADDFHX4TS U9197 ( .A(n8839), .B(n8838), .CI(n8837), .CO(n8833), .S(n9138) );
ADDFHX4TS U9198 ( .A(n8847), .B(n1224), .CI(n8846), .CO(n8838), .S(n9141) );
INVX2TS U9199 ( .A(n8856), .Y(n8858) );
ADDFHX4TS U9200 ( .A(n8862), .B(n8861), .CI(n807), .CO(n8854), .S(n9147) );
ADDFHX4TS U9201 ( .A(n8868), .B(n8867), .CI(n8866), .CO(n8861), .S(n9150) );
NAND2X2TS U9202 ( .A(n8871), .B(n8870), .Y(n8873) );
ADDFHX4TS U9203 ( .A(n8875), .B(n8874), .CI(n1222), .CO(n8867), .S(n9153) );
ADDFHX4TS U9204 ( .A(n8881), .B(n8880), .CI(n8879), .CO(n8874), .S(n9156) );
ADDFHX4TS U9205 ( .A(n8888), .B(n8887), .CI(n806), .CO(n8880), .S(n9159) );
NAND2X2TS U9206 ( .A(n997), .B(n8889), .Y(n8890) );
ADDFHX4TS U9207 ( .A(n8893), .B(n8892), .CI(n8891), .CO(n8887), .S(n9162) );
ADDFHX4TS U9208 ( .A(n8898), .B(n8897), .CI(n1051), .CO(n8892), .S(n9165) );
INVX2TS U9209 ( .A(n8899), .Y(n8901) );
ADDFHX4TS U9210 ( .A(n8905), .B(n8904), .CI(n9453), .CO(n8897), .S(n9168) );
INVX2TS U9211 ( .A(n8912), .Y(n8914) );
ADDFHX4TS U9212 ( .A(n8919), .B(n8918), .CI(n8917), .CO(n8910), .S(n9174) );
ADDFHX4TS U9213 ( .A(n8925), .B(n8924), .CI(n8923), .CO(n8918), .S(n9177) );
AFHCONX2TS U9214 ( .A(n8928), .B(n8927), .CI(n8926), .CON(n8921), .S(n9176)
);
AFHCINX2TS U9215 ( .CIN(n8932), .B(n8933), .A(n8934), .S(n9179), .CO(n8926)
);
ADDFHX4TS U9216 ( .A(n8937), .B(n8936), .CI(n8935), .CO(n8930), .S(n9183) );
AFHCONX2TS U9217 ( .A(n8940), .B(n8939), .CI(n8938), .CON(n8932), .S(n9182)
);
ADDFHX4TS U9218 ( .A(n8943), .B(n8942), .CI(n8941), .CO(n8936), .S(n9186) );
CMPR32X2TS U9219 ( .A(n8946), .B(n8945), .C(n8944), .CO(n8939), .S(n9185) );
ADDFHX4TS U9220 ( .A(n8949), .B(n8948), .CI(n8947), .CO(n8942), .S(n9135) );
CMPR32X2TS U9221 ( .A(n8952), .B(n8951), .C(n8950), .CO(n8944), .S(n9134) );
CMPR32X2TS U9222 ( .A(n8958), .B(n8957), .C(n8956), .CO(n8950), .S(n9188) );
ADDFHX4TS U9223 ( .A(n8961), .B(n8960), .CI(n8959), .CO(n8954), .S(n9192) );
CMPR32X2TS U9224 ( .A(n8964), .B(n8963), .C(n8962), .CO(n8956), .S(n9191) );
ADDFHX4TS U9225 ( .A(n8967), .B(n8966), .CI(n8965), .CO(n8960), .S(n9195) );
CMPR32X2TS U9226 ( .A(n8970), .B(n8969), .C(n8968), .CO(n8962), .S(n9194) );
ADDFHX4TS U9227 ( .A(n8973), .B(n8972), .CI(n8971), .CO(n8966), .S(n9198) );
CMPR32X2TS U9228 ( .A(n8976), .B(n8975), .C(n8974), .CO(n8968), .S(n9197) );
CMPR32X2TS U9229 ( .A(n8982), .B(n8981), .C(n8980), .CO(n8974), .S(n9200) );
CMPR32X2TS U9230 ( .A(n8988), .B(n8987), .C(n8986), .CO(n8980), .S(n9203) );
ADDFHX4TS U9231 ( .A(n8991), .B(n8990), .CI(n8989), .CO(n8984), .S(n9207) );
CMPR32X2TS U9232 ( .A(n8994), .B(n8993), .C(n8992), .CO(n8986), .S(n9206) );
ADDFHX4TS U9233 ( .A(n8997), .B(n8996), .CI(n8995), .CO(n8990), .S(n9210) );
CMPR32X2TS U9234 ( .A(n9000), .B(n8999), .C(n8998), .CO(n8992), .S(n9209) );
CMPR32X2TS U9235 ( .A(n9003), .B(n9002), .C(n9001), .CO(n8998), .S(n9102) );
ADDFHX4TS U9236 ( .A(n9006), .B(n9005), .CI(n9004), .CO(n8996), .S(n9101) );
CMPR32X2TS U9237 ( .A(n9009), .B(n9008), .C(n9007), .CO(n9001), .S(n9099) );
ADDFHX4TS U9238 ( .A(n9012), .B(n9011), .CI(n9010), .CO(n9005), .S(n9098) );
CMPR32X2TS U9239 ( .A(n9015), .B(n9014), .C(n9013), .CO(n9007), .S(n9097) );
INVX2TS U9240 ( .A(n9228), .Y(n9236) );
INVX2TS U9241 ( .A(n9272), .Y(n9276) );
NOR2X2TS U9242 ( .A(n9057), .B(n9056), .Y(n9280) );
INVX2TS U9243 ( .A(n9280), .Y(n9286) );
NAND2X1TS U9244 ( .A(n919), .B(n9286), .Y(n9063) );
NOR2X1TS U9245 ( .A(n9063), .B(n9287), .Y(n9065) );
XNOR2X1TS U9246 ( .A(n9044), .B(n6749), .Y(n9045) );
NOR2X1TS U9247 ( .A(n9045), .B(n7598), .Y(n9302) );
INVX2TS U9248 ( .A(n9302), .Y(n9306) );
INVX2TS U9249 ( .A(n9307), .Y(n9301) );
NAND2X1TS U9250 ( .A(n9045), .B(n7598), .Y(n9305) );
INVX2TS U9251 ( .A(n9305), .Y(n9048) );
NAND2X1TS U9252 ( .A(n9725), .B(n9046), .Y(n9300) );
INVX2TS U9253 ( .A(n9300), .Y(n9047) );
AOI21X1TS U9254 ( .A0(n971), .A1(n9048), .B0(n9047), .Y(n9049) );
OAI21X4TS U9255 ( .A0(n9050), .A1(n9301), .B0(n9049), .Y(n9298) );
NAND2X1TS U9256 ( .A(n9052), .B(n9051), .Y(n9297) );
INVX2TS U9257 ( .A(n9297), .Y(n9294) );
NAND2X1TS U9258 ( .A(n9054), .B(n9053), .Y(n9293) );
INVX2TS U9259 ( .A(n9293), .Y(n9055) );
AOI21X2TS U9260 ( .A0(n1009), .A1(n9294), .B0(n9055), .Y(n9288) );
NAND2X1TS U9261 ( .A(n9057), .B(n9056), .Y(n9285) );
INVX2TS U9262 ( .A(n9285), .Y(n9061) );
NAND2X1TS U9263 ( .A(n9059), .B(n9058), .Y(n9279) );
INVX2TS U9264 ( .A(n9279), .Y(n9060) );
AOI21X1TS U9265 ( .A0(n919), .A1(n9061), .B0(n9060), .Y(n9062) );
OAI21X1TS U9266 ( .A0(n9063), .A1(n9288), .B0(n9062), .Y(n9064) );
AOI21X4TS U9267 ( .A0(n9065), .A1(n9298), .B0(n9064), .Y(n9277) );
INVX2TS U9268 ( .A(n9275), .Y(n9071) );
NAND2X1TS U9269 ( .A(n9069), .B(n9068), .Y(n9271) );
INVX2TS U9270 ( .A(n9271), .Y(n9070) );
AOI21X2TS U9271 ( .A0(n1090), .A1(n9071), .B0(n9070), .Y(n9267) );
INVX2TS U9272 ( .A(n9266), .Y(n9260) );
INVX2TS U9273 ( .A(n9258), .Y(n9076) );
INVX2TS U9274 ( .A(n9255), .Y(n9246) );
INVX2TS U9275 ( .A(n9245), .Y(n9083) );
INVX2TS U9276 ( .A(n9235), .Y(n9089) );
NAND2X1TS U9277 ( .A(n9087), .B(n9086), .Y(n9227) );
INVX2TS U9278 ( .A(n9227), .Y(n9088) );
INVX2TS U9279 ( .A(n9220), .Y(n9100) );
AFHCINX2TS U9280 ( .CIN(n9118), .B(n9119), .A(n9120), .S(n10458), .CO(n9115)
);
AFHCONX2TS U9281 ( .A(n9123), .B(n9122), .CI(n9121), .CON(n9118), .S(n10454)
);
AFHCINX2TS U9282 ( .CIN(n9124), .B(n9125), .A(n9126), .S(n10896), .CO(n9121)
);
AFHCONX2TS U9283 ( .A(n9129), .B(n9128), .CI(n9127), .CON(n9124), .S(n10888)
);
AFHCINX2TS U9284 ( .CIN(n9130), .B(n9131), .A(n9132), .S(n9360), .CO(n9127)
);
AFHCINX2TS U9285 ( .CIN(n9133), .B(n9134), .A(n9135), .S(n9316), .CO(n9184)
);
NOR2X8TS U9286 ( .A(n9317), .B(n9316), .Y(n10858) );
AFHCONX2TS U9287 ( .A(n9138), .B(n9137), .CI(n9136), .CON(n9130), .S(n9355)
);
AFHCINX2TS U9288 ( .CIN(n9139), .B(n9140), .A(n9141), .S(n9352), .CO(n9136)
);
AFHCONX2TS U9289 ( .A(n9144), .B(n9143), .CI(n9142), .CON(n9139), .S(n9350)
);
AFHCINX2TS U9290 ( .CIN(n9145), .B(n9146), .A(n9147), .S(n9347), .CO(n9142)
);
AFHCONX2TS U9291 ( .A(n9150), .B(n9149), .CI(n9148), .CON(n9145), .S(n9345)
);
AFHCINX2TS U9292 ( .CIN(n9151), .B(n9152), .A(n9153), .S(n9343), .CO(n9148)
);
AFHCONX2TS U9293 ( .A(n9156), .B(n9155), .CI(n9154), .CON(n9151), .S(n9342)
);
AFHCINX2TS U9294 ( .CIN(n9157), .B(n9158), .A(n9159), .S(n9340), .CO(n9154)
);
AFHCONX2TS U9295 ( .A(n9162), .B(n9161), .CI(n9160), .CON(n9157), .S(n9339)
);
AFHCINX2TS U9296 ( .CIN(n9163), .B(n9164), .A(n9165), .S(n9337), .CO(n9160)
);
AFHCONX2TS U9297 ( .A(n9168), .B(n9167), .CI(n9166), .CON(n9163), .S(n9335)
);
AFHCINX2TS U9298 ( .CIN(n9169), .B(n9170), .A(n9171), .S(n9332), .CO(n9166)
);
AFHCONX2TS U9299 ( .A(n9174), .B(n9173), .CI(n9172), .CON(n9169), .S(n9330)
);
AFHCINX2TS U9300 ( .CIN(n9175), .B(n9176), .A(n9177), .S(n9327), .CO(n9172)
);
AFHCONX2TS U9301 ( .A(n9180), .B(n9179), .CI(n9178), .CON(n9175), .S(n9325)
);
AFHCINX2TS U9302 ( .CIN(n9181), .B(n9182), .A(n9183), .S(n9321), .CO(n9178)
);
AFHCONX2TS U9303 ( .A(n9186), .B(n9185), .CI(n9184), .CON(n9181), .S(n9319)
);
INVX2TS U9304 ( .A(n10804), .Y(n10813) );
NOR2X4TS U9305 ( .A(n10717), .B(n10714), .Y(n10703) );
NOR2X4TS U9306 ( .A(n10687), .B(n10684), .Y(n10693) );
NOR2X4TS U9307 ( .A(n10835), .B(n10832), .Y(n10844) );
AFHCONX2TS U9308 ( .A(n9189), .B(n9188), .CI(n9187), .CON(n9133), .S(n9313)
);
AFHCINX2TS U9309 ( .CIN(n9190), .B(n9191), .A(n9192), .S(n9310), .CO(n9187)
);
AFHCONX2TS U9310 ( .A(n9195), .B(n9194), .CI(n9193), .CON(n9190), .S(n10572)
);
AFHCINX2TS U9311 ( .CIN(n9196), .B(n9197), .A(n9198), .S(n10568), .CO(n9193)
);
AFHCONX2TS U9312 ( .A(n9201), .B(n9200), .CI(n9199), .CON(n9196), .S(n10565)
);
AFHCINX2TS U9313 ( .CIN(n9202), .B(n9203), .A(n9204), .S(n10593), .CO(n9199)
);
AFHCONX2TS U9314 ( .A(n9207), .B(n9206), .CI(n9205), .CON(n9202), .S(n10589)
);
AFHCINX2TS U9315 ( .CIN(n9208), .B(n9209), .A(n9210), .S(n10585), .CO(n9205)
);
INVX2TS U9316 ( .A(n9211), .Y(n9213) );
NAND2X1TS U9317 ( .A(n9213), .B(n9212), .Y(n9219) );
INVX2TS U9318 ( .A(n9214), .Y(n9217) );
INVX2TS U9319 ( .A(n9215), .Y(n9216) );
AOI21X1TS U9320 ( .A0(n9217), .A1(n9226), .B0(n9216), .Y(n9218) );
XOR2X1TS U9321 ( .A(n9219), .B(n9218), .Y(n10581) );
AOI21X1TS U9322 ( .A0(n9226), .A1(n1084), .B0(n9221), .Y(n9222) );
XOR2X1TS U9323 ( .A(n9223), .B(n9222), .Y(n10609) );
NAND2X1TS U9324 ( .A(n1084), .B(n9224), .Y(n9225) );
XNOR2X1TS U9325 ( .A(n9226), .B(n9225), .Y(n10605) );
NAND2X1TS U9326 ( .A(n1085), .B(n9227), .Y(n9234) );
NAND2X1TS U9327 ( .A(n9230), .B(n9251), .Y(n9232) );
AOI21X1TS U9328 ( .A0(n9230), .A1(n9252), .B0(n9229), .Y(n9231) );
XNOR2X1TS U9329 ( .A(n9234), .B(n9233), .Y(n10601) );
NAND2X1TS U9330 ( .A(n9236), .B(n9235), .Y(n9244) );
INVX2TS U9331 ( .A(n9237), .Y(n9240) );
AOI21X1TS U9332 ( .A0(n9240), .A1(n9252), .B0(n9239), .Y(n9241) );
XNOR2X1TS U9333 ( .A(n9244), .B(n9243), .Y(n10597) );
NAND2X1TS U9334 ( .A(n924), .B(n9245), .Y(n9250) );
NAND2X1TS U9335 ( .A(n923), .B(n9251), .Y(n9248) );
AOI21X1TS U9336 ( .A0(n923), .A1(n9252), .B0(n9246), .Y(n9247) );
XNOR2X1TS U9337 ( .A(n9250), .B(n9249), .Y(n10679) );
INVX2TS U9338 ( .A(n9251), .Y(n9254) );
INVX2TS U9339 ( .A(n9252), .Y(n9253) );
NAND2X1TS U9340 ( .A(n923), .B(n9255), .Y(n9256) );
XNOR2X1TS U9341 ( .A(n9257), .B(n9256), .Y(n10675) );
NAND2X1TS U9342 ( .A(n1020), .B(n9258), .Y(n9265) );
INVX2TS U9343 ( .A(n9268), .Y(n9259) );
NAND2X1TS U9344 ( .A(n1010), .B(n9259), .Y(n9263) );
INVX2TS U9345 ( .A(n9267), .Y(n9261) );
AOI21X1TS U9346 ( .A0(n1010), .A1(n9261), .B0(n9260), .Y(n9262) );
XNOR2X1TS U9347 ( .A(n9265), .B(n9264), .Y(n10671) );
NAND2X1TS U9348 ( .A(n1010), .B(n9266), .Y(n9270) );
XNOR2X1TS U9349 ( .A(n9270), .B(n9269), .Y(n10667) );
NAND2X1TS U9350 ( .A(n1090), .B(n9271), .Y(n9274) );
XNOR2X1TS U9351 ( .A(n9274), .B(n9273), .Y(n10663) );
NAND2X1TS U9352 ( .A(n9276), .B(n9275), .Y(n9278) );
XOR2X1TS U9353 ( .A(n9278), .B(n9277), .Y(n10659) );
NAND2X1TS U9354 ( .A(n919), .B(n9279), .Y(n9284) );
NOR2XLTS U9355 ( .A(n9280), .B(n9287), .Y(n9282) );
OAI21XLTS U9356 ( .A0(n9280), .A1(n9288), .B0(n9285), .Y(n9281) );
AOI21X1TS U9357 ( .A0(n9282), .A1(n9298), .B0(n9281), .Y(n9283) );
XOR2X1TS U9358 ( .A(n9284), .B(n9283), .Y(n10655) );
INVX2TS U9359 ( .A(n9288), .Y(n9289) );
AOI21X1TS U9360 ( .A0(n9290), .A1(n9298), .B0(n9289), .Y(n9291) );
XOR2X1TS U9361 ( .A(n9292), .B(n9291), .Y(n10651) );
NAND2X1TS U9362 ( .A(n1009), .B(n9293), .Y(n9296) );
AOI21X1TS U9363 ( .A0(n1000), .A1(n9298), .B0(n9294), .Y(n9295) );
NAND2X1TS U9364 ( .A(n1000), .B(n9297), .Y(n9299) );
XNOR2X1TS U9365 ( .A(n9299), .B(n9298), .Y(n10642) );
NAND2X1TS U9366 ( .A(n971), .B(n9300), .Y(n9304) );
OAI21XLTS U9367 ( .A0(n9302), .A1(n9301), .B0(n9305), .Y(n9303) );
XNOR2X1TS U9368 ( .A(n9304), .B(n9303), .Y(n10638) );
NAND2X1TS U9369 ( .A(n9306), .B(n9305), .Y(n9308) );
XNOR2X1TS U9370 ( .A(n9308), .B(n9307), .Y(n10634) );
CMPR32X2TS U9371 ( .A(n9309), .B(n6488), .C(n7946), .CO(n9307), .S(n10630)
);
AOI21X4TS U9372 ( .A0(n1172), .A1(n1191), .B0(n9315), .Y(n10811) );
OAI21X2TS U9373 ( .A0(n10798), .A1(n10794), .B0(n10799), .Y(n10785) );
INVX2TS U9374 ( .A(n10790), .Y(n9328) );
INVX2TS U9375 ( .A(n10769), .Y(n9333) );
INVX2TS U9376 ( .A(n10749), .Y(n9338) );
OAI21X4TS U9377 ( .A0(n10717), .A1(n10713), .B0(n10718), .Y(n10704) );
INVX2TS U9378 ( .A(n10709), .Y(n9344) );
AOI21X4TS U9379 ( .A0(n1178), .A1(n10704), .B0(n9344), .Y(n10683) );
OAI21X4TS U9380 ( .A0(n10687), .A1(n10683), .B0(n10688), .Y(n10694) );
INVX2TS U9381 ( .A(n10699), .Y(n9348) );
AOI21X4TS U9382 ( .A0(n1177), .A1(n10694), .B0(n9348), .Y(n10831) );
INVX2TS U9383 ( .A(n10850), .Y(n9353) );
AOI21X4TS U9384 ( .A0(n9358), .A1(n9357), .B0(n9356), .Y(n10874) );
OA21X4TS U9385 ( .A0(n10471), .A1(n10468), .B0(n10469), .Y(n10481) );
OAI21X4TS U9386 ( .A0(n10481), .A1(n10478), .B0(n10479), .Y(n10475) );
XNOR2X4TS U9387 ( .A(n9381), .B(n9380), .Y(n9383) );
AOI21X4TS U9388 ( .A0(n10475), .A1(n1213), .B0(n9384), .Y(n10487) );
OAI21X4TS U9389 ( .A0(n9395), .A1(n9394), .B0(n9393), .Y(n9397) );
OAI21X4TS U9390 ( .A0(n9498), .A1(n9505), .B0(n9499), .Y(n9401) );
NOR2X2TS U9391 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .Y(
n11009) );
NAND2X1TS U9392 ( .A(n11009), .B(FS_Module_state_reg[3]), .Y(n10496) );
NAND2X1TS U9393 ( .A(FSM_add_overflow_flag), .B(n11225), .Y(n9403) );
NOR3X1TS U9394 ( .A(n11175), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[3]), .Y(n10497) );
INVX2TS U9395 ( .A(n10497), .Y(n10449) );
OAI21X4TS U9396 ( .A0(n10496), .A1(n9403), .B0(n10449), .Y(n10555) );
INVX2TS U9397 ( .A(n9418), .Y(n9419) );
BUFX6TS U9398 ( .A(n10555), .Y(n10782) );
INVX2TS U9399 ( .A(n9450), .Y(n9451) );
NAND4X2TS U9400 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]),
.C(n11175), .D(n11248), .Y(n11069) );
NAND2X1TS U9401 ( .A(Sgf_normalized_result[6]), .B(n11067), .Y(n11070) );
NOR2X2TS U9402 ( .A(n11179), .B(n11070), .Y(n11072) );
NAND2X1TS U9403 ( .A(Sgf_normalized_result[8]), .B(n11072), .Y(n11074) );
NOR2X2TS U9404 ( .A(n11180), .B(n11074), .Y(n11076) );
NAND2X1TS U9405 ( .A(Sgf_normalized_result[10]), .B(n11076), .Y(n11078) );
NOR2X2TS U9406 ( .A(n11181), .B(n11078), .Y(n11080) );
NOR2X2TS U9407 ( .A(n11182), .B(n11082), .Y(n11084) );
NOR2X2TS U9408 ( .A(n11195), .B(n11134), .Y(n11136) );
NOR2X2TS U9409 ( .A(n11197), .B(n11138), .Y(n11142) );
NOR2X2TS U9410 ( .A(n11200), .B(n11144), .Y(n11146) );
NOR2X2TS U9411 ( .A(n11201), .B(n11148), .Y(n11150) );
NOR2X2TS U9412 ( .A(n11202), .B(n11152), .Y(n11154) );
NOR2X2TS U9413 ( .A(n11203), .B(n11157), .Y(n11163) );
AOI21X1TS U9414 ( .A0(n9510), .A1(Sgf_normalized_result[52]), .B0(n11158),
.Y(n9495) );
OAI2BB1X1TS U9415 ( .A0N(Add_result[52]), .A1N(n11156), .B0(n9493), .Y(n9494) );
INVX4TS U9416 ( .A(n11158), .Y(n11141) );
BUFX6TS U9417 ( .A(n10555), .Y(n10897) );
AOI211X1TS U9418 ( .A0(n11204), .A1(n11161), .B0(n9510), .C0(n11158), .Y(
n9511) );
INVX4TS U9419 ( .A(n9512), .Y(n10682) );
INVX6TS U9420 ( .A(n9512), .Y(n10554) );
CMPR32X2TS U9421 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[1]), .B(n9514), .C(n9513), .CO(n7519), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_S_B[1])
);
CMPR32X2TS U9422 ( .A(n9516), .B(n9515), .C(n9640), .CO(n9627), .S(
DP_OP_341J35_125_6458_n24) );
CMPR32X2TS U9423 ( .A(DP_OP_341J35_125_6458_n414), .B(n9518), .C(n9517),
.CO(n9641), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[11]) );
CMPR32X2TS U9424 ( .A(n9593), .B(n9619), .C(n9519), .CO(n9645), .S(n9520) );
INVX2TS U9425 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[11]), .Y(n9526) );
CMPR32X2TS U9426 ( .A(n9523), .B(n9522), .C(n9521), .CO(n9530), .S(n9524) );
CMPR32X2TS U9427 ( .A(n9527), .B(n9526), .C(n9525), .CO(
DP_OP_341J35_125_6458_n37), .S(DP_OP_341J35_125_6458_n38) );
CMPR32X2TS U9428 ( .A(DP_OP_341J35_125_6458_n418), .B(
DP_OP_341J35_125_6458_n422), .C(n9528), .CO(n9565), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[9]) );
INVX2TS U9429 ( .A(n9529), .Y(n9536) );
INVX2TS U9430 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[9]), .Y(n9533) );
CMPR32X2TS U9431 ( .A(n9534), .B(n9533), .C(n9532), .CO(
DP_OP_341J35_125_6458_n57), .S(DP_OP_341J35_125_6458_n58) );
ADDHXLTS U9432 ( .A(n9536), .B(n9535), .CO(n9534), .S(n9544) );
INVX2TS U9433 ( .A(n9537), .Y(n9680) );
CMPR32X2TS U9434 ( .A(n9544), .B(n9543), .C(n9542), .CO(
DP_OP_341J35_125_6458_n68), .S(DP_OP_341J35_125_6458_n69) );
INVX2TS U9435 ( .A(n9545), .Y(n9672) );
CMPR32X2TS U9436 ( .A(n9547), .B(n9546), .C(DP_OP_341J35_125_6458_n91), .CO(
DP_OP_341J35_125_6458_n81), .S(DP_OP_341J35_125_6458_n82) );
CMPR32X2TS U9437 ( .A(n9550), .B(n9549), .C(n9548), .CO(n9566), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[4]) );
INVX2TS U9438 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[4]), .Y(n9674) );
CMPR32X2TS U9439 ( .A(n9555), .B(n9554), .C(n9553), .CO(n9538), .S(n9556) );
CMPR32X2TS U9440 ( .A(n9558), .B(n9557), .C(DP_OP_341J35_125_6458_n109),
.CO(DP_OP_341J35_125_6458_n102), .S(DP_OP_341J35_125_6458_n103) );
CMPR32X2TS U9441 ( .A(n9561), .B(n9560), .C(n9559), .CO(
DP_OP_341J35_125_6458_n117), .S(DP_OP_341J35_125_6458_n118) );
CMPR32X2TS U9442 ( .A(n9564), .B(n9563), .C(n9562), .CO(
DP_OP_341J35_125_6458_n126), .S(n9513) );
CMPR32X2TS U9443 ( .A(DP_OP_341J35_125_6458_n415), .B(
DP_OP_341J35_125_6458_n417), .C(n9565), .CO(n9517), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[10]) );
CMPR32X2TS U9444 ( .A(n9568), .B(n9567), .C(n9566), .CO(n7619), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[5]) );
CMPR32X2TS U9445 ( .A(n9571), .B(n9570), .C(n9569), .CO(n9548), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[3]) );
CMPR32X2TS U9446 ( .A(n9574), .B(n9573), .C(n9572), .CO(n9569), .S(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[2]) );
AOI22X1TS U9447 ( .A0(n9661), .A1(n9579), .B0(n9594), .B1(n9575), .Y(
DP_OP_341J35_125_6458_n287) );
AOI22X1TS U9448 ( .A0(n9661), .A1(n9583), .B0(n9579), .B1(n9575), .Y(
DP_OP_341J35_125_6458_n288) );
AOI22X1TS U9449 ( .A0(n9661), .A1(n9576), .B0(n9583), .B1(n9575), .Y(
DP_OP_341J35_125_6458_n289) );
AOI22X1TS U9450 ( .A0(n9661), .A1(n9660), .B0(n9576), .B1(n9575), .Y(
DP_OP_341J35_125_6458_n290) );
AOI22X1TS U9451 ( .A0(n2970), .A1(n9644), .B0(n9590), .B1(n9582), .Y(n9578)
);
OAI22X1TS U9452 ( .A0(n9588), .A1(n9577), .B0(n9586), .B1(n9578), .Y(
DP_OP_341J35_125_6458_n294) );
AOI22X1TS U9453 ( .A0(n2970), .A1(n9593), .B0(n9594), .B1(n9582), .Y(n9581)
);
OAI22X1TS U9454 ( .A0(n9581), .A1(n9586), .B0(n9588), .B1(n9578), .Y(
DP_OP_341J35_125_6458_n295) );
AOI22X1TS U9455 ( .A0(n2970), .A1(n9580), .B0(n9579), .B1(n9582), .Y(n9585)
);
OAI22X1TS U9456 ( .A0(n9581), .A1(n9588), .B0(n9585), .B1(n9586), .Y(
DP_OP_341J35_125_6458_n296) );
AOI22X1TS U9457 ( .A0(n2970), .A1(n9584), .B0(n9583), .B1(n9582), .Y(n9589)
);
OAI22X1TS U9458 ( .A0(n9585), .A1(n9588), .B0(n9589), .B1(n9586), .Y(
DP_OP_341J35_125_6458_n297) );
OAI22X1TS U9459 ( .A0(n9589), .A1(n9588), .B0(n9587), .B1(n9586), .Y(
DP_OP_341J35_125_6458_n298) );
AOI22X1TS U9460 ( .A0(n9637), .A1(n9633), .B0(n9632), .B1(n9592), .Y(n9591)
);
OAI22X1TS U9461 ( .A0(n9591), .A1(n9597), .B0(n9592), .B1(n9599), .Y(
DP_OP_341J35_125_6458_n302) );
AOI22X1TS U9462 ( .A0(n9637), .A1(n9590), .B0(n9644), .B1(n9592), .Y(n9595)
);
OAI22X1TS U9463 ( .A0(n9591), .A1(n9599), .B0(n9595), .B1(n9597), .Y(
DP_OP_341J35_125_6458_n303) );
AOI22X1TS U9464 ( .A0(n9637), .A1(n9594), .B0(n9593), .B1(n9592), .Y(n9598)
);
OAI22X1TS U9465 ( .A0(n9595), .A1(n9599), .B0(n9597), .B1(n9598), .Y(
DP_OP_341J35_125_6458_n304) );
OAI22X1TS U9466 ( .A0(n9599), .A1(n9598), .B0(n9597), .B1(n9596), .Y(
DP_OP_341J35_125_6458_n305) );
AOI21X1TS U9467 ( .A0(n9632), .A1(n9634), .B0(DP_OP_341J35_125_6458_n262),
.Y(DP_OP_341J35_125_6458_n310) );
OAI22X1TS U9468 ( .A0(n9605), .A1(n9647), .B0(n9609), .B1(n9601), .Y(
DP_OP_341J35_125_6458_n419) );
OAI22X1TS U9469 ( .A0(n9609), .A1(n9647), .B0(n9600), .B1(n9601), .Y(
DP_OP_341J35_125_6458_n424) );
OAI22X1TS U9470 ( .A0(n9620), .A1(n9647), .B0(n9605), .B1(n9601), .Y(
DP_OP_341J35_125_6458_n446) );
OAI22X1TS U9471 ( .A0(n9648), .A1(n9601), .B0(n9600), .B1(n9647), .Y(
DP_OP_341J35_125_6458_n447) );
AOI22X1TS U9472 ( .A0(n7432), .A1(n9616), .B0(n9658), .B1(n9607), .Y(n9603)
);
OAI22X1TS U9473 ( .A0(n9615), .A1(n9602), .B0(n9613), .B1(n9603), .Y(
DP_OP_341J35_125_6458_n450) );
AOI22X1TS U9474 ( .A0(n7432), .A1(n9620), .B0(n9619), .B1(n9607), .Y(n9606)
);
OAI22X1TS U9475 ( .A0(n9615), .A1(n9603), .B0(n9613), .B1(n9606), .Y(
DP_OP_341J35_125_6458_n451) );
AOI22X1TS U9476 ( .A0(n7432), .A1(n9605), .B0(n9604), .B1(n9607), .Y(n9611)
);
OAI22X1TS U9477 ( .A0(n9615), .A1(n9606), .B0(n9613), .B1(n9611), .Y(
DP_OP_341J35_125_6458_n452) );
AOI22X1TS U9478 ( .A0(n7432), .A1(n9609), .B0(n9608), .B1(n9607), .Y(n9614)
);
OAI22X1TS U9479 ( .A0(n9615), .A1(n9611), .B0(n9613), .B1(n9614), .Y(
DP_OP_341J35_125_6458_n453) );
OAI22X1TS U9480 ( .A0(n9615), .A1(n9614), .B0(n9613), .B1(n9612), .Y(
DP_OP_341J35_125_6458_n454) );
AOI22X1TS U9481 ( .A0(n7429), .A1(n9654), .B0(n9656), .B1(n9618), .Y(n9617)
);
OAI22X1TS U9482 ( .A0(n9618), .A1(n9625), .B0(n9623), .B1(n9617), .Y(
DP_OP_341J35_125_6458_n458) );
AOI22X1TS U9483 ( .A0(n7429), .A1(n9616), .B0(n9658), .B1(n9618), .Y(n9621)
);
OAI22X1TS U9484 ( .A0(n9625), .A1(n9617), .B0(n9623), .B1(n9621), .Y(
DP_OP_341J35_125_6458_n459) );
AOI22X1TS U9485 ( .A0(n7429), .A1(n9620), .B0(n9619), .B1(n9618), .Y(n9624)
);
OAI22X1TS U9486 ( .A0(n9625), .A1(n9621), .B0(n9623), .B1(n9624), .Y(
DP_OP_341J35_125_6458_n460) );
OAI22X1TS U9487 ( .A0(n9625), .A1(n9624), .B0(n9623), .B1(n9622), .Y(
DP_OP_341J35_125_6458_n461) );
AOI21X1TS U9488 ( .A0(n9656), .A1(n3003), .B0(DP_OP_341J35_125_6458_n466),
.Y(DP_OP_341J35_125_6458_n467) );
CMPR32X2TS U9489 ( .A(n9627), .B(n9626), .C(DP_OP_341J35_125_6458_n20), .CO(
n9631), .S(n9629) );
CMPR32X2TS U9490 ( .A(DP_OP_341J35_125_6458_n21), .B(n9629), .C(n9628), .CO(
n9630), .S(n9692) );
XNOR2X1TS U9491 ( .A(n9631), .B(n9630), .Y(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_S_B[15]) );
AOI22X1TS U9492 ( .A0(n9633), .A1(DP_OP_341J35_125_6458_n267), .B0(
DP_OP_341J35_125_6458_n262), .B1(n9632), .Y(n9635) );
OAI32X1TS U9493 ( .A0(n9636), .A1(n9644), .A2(DP_OP_341J35_125_6458_n262),
.B0(n9635), .B1(n9634), .Y(DP_OP_341J35_125_6458_n311) );
OAI21X1TS U9494 ( .A0(DP_OP_341J35_125_6458_n262), .A1(n9638), .B0(n9637),
.Y(DP_OP_341J35_125_6458_n301) );
INVX2TS U9495 ( .A(n9639), .Y(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[13]) );
INVX2TS U9496 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[12]), .Y(DP_OP_341J35_125_6458_n129) );
INVX2TS U9497 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[10]), .Y(DP_OP_341J35_125_6458_n131) );
CMPR32X2TS U9498 ( .A(n9645), .B(n9658), .C(n9644), .CO(n7441), .S(n9646) );
INVX2TS U9499 ( .A(n9646), .Y(n9665) );
NOR2X1TS U9500 ( .A(n9665), .B(n9652), .Y(DP_OP_341J35_125_6458_n200) );
NOR2X1TS U9501 ( .A(n9648), .B(n9647), .Y(DP_OP_341J35_125_6458_n448) );
NOR2X1TS U9502 ( .A(n9665), .B(n9685), .Y(DP_OP_341J35_125_6458_n192) );
NOR2X1TS U9503 ( .A(n9649), .B(n9667), .Y(DP_OP_341J35_125_6458_n165) );
NOR2X1TS U9504 ( .A(n9665), .B(n9651), .Y(DP_OP_341J35_125_6458_n184) );
NOR2X1TS U9505 ( .A(n9666), .B(n9649), .Y(DP_OP_341J35_125_6458_n149) );
NOR2X1TS U9506 ( .A(n9649), .B(n9650), .Y(DP_OP_341J35_125_6458_n173) );
NOR2X1TS U9507 ( .A(n9682), .B(n9650), .Y(DP_OP_341J35_125_6458_n171) );
NOR2X1TS U9508 ( .A(n9686), .B(n9681), .Y(DP_OP_341J35_125_6458_n180) );
NOR2X1TS U9509 ( .A(n9686), .B(n9667), .Y(DP_OP_341J35_125_6458_n164) );
NOR2X1TS U9510 ( .A(n9686), .B(n9650), .Y(DP_OP_341J35_125_6458_n172) );
NOR2X1TS U9511 ( .A(n9664), .B(n9651), .Y(DP_OP_341J35_125_6458_n183) );
NOR2X1TS U9512 ( .A(n9668), .B(n9685), .Y(DP_OP_341J35_125_6458_n190) );
NOR2X1TS U9513 ( .A(n9649), .B(n9651), .Y(DP_OP_341J35_125_6458_n189) );
NOR2X1TS U9514 ( .A(n9665), .B(n9681), .Y(DP_OP_341J35_125_6458_n176) );
NOR2X1TS U9515 ( .A(n9649), .B(n9663), .Y(DP_OP_341J35_125_6458_n157) );
NOR2X1TS U9516 ( .A(n9649), .B(n9681), .Y(DP_OP_341J35_125_6458_n181) );
NOR2X1TS U9517 ( .A(n9682), .B(n9667), .Y(DP_OP_341J35_125_6458_n163) );
NOR2X1TS U9518 ( .A(n9664), .B(n9681), .Y(DP_OP_341J35_125_6458_n175) );
NOR2X1TS U9519 ( .A(n9682), .B(n9663), .Y(DP_OP_341J35_125_6458_n155) );
INVX2TS U9520 ( .A(DP_OP_341J35_125_6458_n424), .Y(
DP_OP_341J35_125_6458_n425) );
INVX2TS U9521 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_left[1]), .Y(DP_OP_341J35_125_6458_n234) );
NOR2X1TS U9522 ( .A(n9666), .B(n9682), .Y(DP_OP_341J35_125_6458_n147) );
NOR2X1TS U9523 ( .A(n9668), .B(n9651), .Y(DP_OP_341J35_125_6458_n182) );
NOR2X1TS U9524 ( .A(n9665), .B(n9650), .Y(DP_OP_341J35_125_6458_n168) );
NOR2X1TS U9525 ( .A(n9668), .B(n9652), .Y(DP_OP_341J35_125_6458_n198) );
NOR2X1TS U9526 ( .A(n9664), .B(n9650), .Y(DP_OP_341J35_125_6458_n167) );
NOR2X1TS U9527 ( .A(n9653), .B(n9685), .Y(DP_OP_341J35_125_6458_n194) );
NOR2X1TS U9528 ( .A(n9662), .B(n9652), .Y(DP_OP_341J35_125_6458_n201) );
INVX2TS U9529 ( .A(DP_OP_341J35_125_6458_n419), .Y(
DP_OP_341J35_125_6458_n420) );
NOR2X1TS U9530 ( .A(n9662), .B(n9651), .Y(DP_OP_341J35_125_6458_n185) );
NOR2X1TS U9531 ( .A(n9662), .B(n9685), .Y(DP_OP_341J35_125_6458_n193) );
NOR2X1TS U9532 ( .A(n9682), .B(n9652), .Y(DP_OP_341J35_125_6458_n203) );
NOR2X1TS U9533 ( .A(n9665), .B(n9667), .Y(DP_OP_341J35_125_6458_n160) );
NOR2X1TS U9534 ( .A(n9666), .B(n9653), .Y(DP_OP_341J35_125_6458_n146) );
AOI22X1TS U9535 ( .A0(n9656), .A1(DP_OP_341J35_125_6458_n466), .B0(n2968),
.B1(n9654), .Y(n9657) );
OAI32X1TS U9536 ( .A0(n9659), .A1(n9658), .A2(DP_OP_341J35_125_6458_n466),
.B0(n9657), .B1(n3003), .Y(DP_OP_341J35_125_6458_n468) );
NOR2X1TS U9537 ( .A(n9664), .B(n9667), .Y(DP_OP_341J35_125_6458_n159) );
NOR2X1TS U9538 ( .A(n9661), .B(n9660), .Y(DP_OP_341J35_125_6458_n291) );
NOR2X1TS U9539 ( .A(n9665), .B(n9663), .Y(DP_OP_341J35_125_6458_n152) );
NOR2X1TS U9540 ( .A(n9666), .B(n9665), .Y(DP_OP_341J35_125_6458_n144) );
NOR2X1TS U9541 ( .A(n9668), .B(n9667), .Y(DP_OP_341J35_125_6458_n158) );
ADDHXLTS U9542 ( .A(n9672), .B(n9671), .CO(n9547), .S(
DP_OP_341J35_125_6458_n95) );
ADDHXLTS U9543 ( .A(n9674), .B(n9673), .CO(n9558), .S(
DP_OP_341J35_125_6458_n113) );
ADDHXLTS U9544 ( .A(n9676), .B(n9675), .CO(DP_OP_341J35_125_6458_n276), .S(
n3017) );
INVX2TS U9545 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[5]), .Y(n9684) );
INVX2TS U9546 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[2]), .Y(n9688) );
INVX2TS U9547 ( .A(
Sgf_operation_ODD1_left_RECURSIVE_EVEN1_middle_RECURSIVE_EVEN1_Q_right[3]), .Y(n9690) );
CMPR32X2TS U9548 ( .A(n9692), .B(DP_OP_344J35_128_4078_n61), .C(n9691), .CO(
DP_OP_344J35_128_4078_n12), .S(n8462) );
XNOR2X1TS U9549 ( .A(n7596), .B(n7598), .Y(DP_OP_344J35_128_4078_n116) );
INVX2TS U9550 ( .A(n9735), .Y(DP_OP_344J35_128_4078_n129) );
NOR2X1TS U9551 ( .A(n9834), .B(n9841), .Y(DP_OP_342J35_126_4270_n325) );
INVX2TS U9552 ( .A(n9853), .Y(DP_OP_342J35_126_4270_n271) );
INVX2TS U9553 ( .A(n9863), .Y(DP_OP_342J35_126_4270_n281) );
INVX2TS U9554 ( .A(n9864), .Y(DP_OP_342J35_126_4270_n282) );
INVX2TS U9555 ( .A(n9866), .Y(DP_OP_342J35_126_4270_n284) );
INVX2TS U9556 ( .A(n9867), .Y(DP_OP_342J35_126_4270_n286) );
INVX2TS U9557 ( .A(n9869), .Y(DP_OP_342J35_126_4270_n288) );
INVX2TS U9558 ( .A(n9870), .Y(DP_OP_342J35_126_4270_n289) );
INVX2TS U9559 ( .A(n9874), .Y(DP_OP_342J35_126_4270_n402) );
INVX2TS U9560 ( .A(DP_OP_342J35_126_4270_n774), .Y(
DP_OP_342J35_126_4270_n409) );
CMPR32X2TS U9561 ( .A(n9881), .B(n9880), .C(n9879), .CO(
DP_OP_345J35_129_3436_n20), .S(n6597) );
INVX2TS U9562 ( .A(n9893), .Y(n9906) );
INVX2TS U9563 ( .A(n10069), .Y(n10070) );
INVX2TS U9564 ( .A(n10084), .Y(n10074) );
INVX2TS U9565 ( .A(n10083), .Y(n10075) );
INVX2TS U9566 ( .A(n10078), .Y(n10080) );
INVX2TS U9567 ( .A(n10085), .Y(n10087) );
INVX2TS U9568 ( .A(n10090), .Y(n10098) );
INVX2TS U9569 ( .A(n10097), .Y(n10091) );
INVX2TS U9570 ( .A(n10092), .Y(n10094) );
INVX2TS U9571 ( .A(n10102), .Y(n10104) );
NAND2X1TS U9572 ( .A(n10109), .B(n10108), .Y(n10110) );
INVX2TS U9573 ( .A(n10112), .Y(n10114) );
NAND2X1TS U9574 ( .A(n10114), .B(n10113), .Y(n10115) );
INVX2TS U9575 ( .A(n10129), .Y(n10146) );
INVX2TS U9576 ( .A(n10152), .Y(n10177) );
INVX2TS U9577 ( .A(n10174), .Y(n10204) );
INVX2TS U9578 ( .A(n10214), .Y(n10257) );
INVX2TS U9579 ( .A(n10243), .Y(n10278) );
INVX2TS U9580 ( .A(n10260), .Y(n10289) );
INVX2TS U9581 ( .A(n10280), .Y(n10301) );
CMPR32X2TS U9582 ( .A(n10309), .B(n10308), .C(DP_OP_347J35_131_5122_n28),
.CO(n6408), .S(DP_OP_347J35_131_5122_n24) );
OAI22X1TS U9583 ( .A0(n6441), .A1(n1167), .B0(n10372), .B1(n976), .Y(
DP_OP_347J35_131_5122_n289) );
XNOR2X1TS U9584 ( .A(Op_MX[5]), .B(Op_MY[5]), .Y(n10311) );
OAI22X1TS U9585 ( .A0(n6439), .A1(n10311), .B0(n10370), .B1(n10310), .Y(
DP_OP_347J35_131_5122_n293) );
XNOR2X1TS U9586 ( .A(Op_MX[5]), .B(Op_MY[4]), .Y(n10337) );
OAI22X1TS U9587 ( .A0(n6439), .A1(n10337), .B0(n10370), .B1(n10311), .Y(
DP_OP_347J35_131_5122_n294) );
XNOR2X1TS U9588 ( .A(Op_MX[3]), .B(Op_MY[6]), .Y(n10339) );
OAI22X1TS U9589 ( .A0(n6447), .A1(n10339), .B0(n10422), .B1(n953), .Y(
DP_OP_347J35_131_5122_n301) );
OAI22X1TS U9590 ( .A0(n6354), .A1(n965), .B0(n10383), .B1(n910), .Y(
DP_OP_347J35_131_5122_n434) );
OAI22X1TS U9591 ( .A0(n6354), .A1(n1059), .B0(n10383), .B1(n961), .Y(
DP_OP_347J35_131_5122_n435) );
XNOR2X1TS U9592 ( .A(Op_MX[12]), .B(Op_MY[12]), .Y(n10313) );
OAI22X1TS U9593 ( .A0(n6352), .A1(n10313), .B0(n10317), .B1(n10312), .Y(
DP_OP_347J35_131_5122_n438) );
XNOR2X1TS U9594 ( .A(Op_MX[12]), .B(Op_MY[11]), .Y(n10314) );
OAI22X1TS U9595 ( .A0(n6352), .A1(n10314), .B0(n10317), .B1(n10313), .Y(
DP_OP_347J35_131_5122_n439) );
XNOR2X1TS U9596 ( .A(Op_MX[12]), .B(Op_MY[10]), .Y(n10315) );
OAI22X1TS U9597 ( .A0(n6352), .A1(n10315), .B0(n10317), .B1(n10314), .Y(
DP_OP_347J35_131_5122_n440) );
XNOR2X1TS U9598 ( .A(Op_MX[12]), .B(Op_MY[9]), .Y(n10316) );
OAI22X1TS U9599 ( .A0(n6352), .A1(n10316), .B0(n10317), .B1(n10315), .Y(
DP_OP_347J35_131_5122_n441) );
OAI22X1TS U9600 ( .A0(n6352), .A1(n10318), .B0(n10317), .B1(n10316), .Y(
DP_OP_347J35_131_5122_n442) );
XNOR2X1TS U9601 ( .A(Op_MX[10]), .B(Op_MY[13]), .Y(n10319) );
OAI22X1TS U9602 ( .A0(n6358), .A1(n10319), .B0(n10424), .B1(n952), .Y(
DP_OP_347J35_131_5122_n446) );
XNOR2X1TS U9603 ( .A(Op_MX[10]), .B(Op_MY[12]), .Y(n10320) );
OAI22X1TS U9604 ( .A0(n6358), .A1(n10320), .B0(n10424), .B1(n10319), .Y(
DP_OP_347J35_131_5122_n447) );
XNOR2X1TS U9605 ( .A(Op_MX[10]), .B(Op_MY[11]), .Y(n10321) );
OAI22X1TS U9606 ( .A0(n6358), .A1(n10321), .B0(n10424), .B1(n10320), .Y(
DP_OP_347J35_131_5122_n448) );
OAI22X1TS U9607 ( .A0(n6358), .A1(n10322), .B0(n10424), .B1(n10321), .Y(
DP_OP_347J35_131_5122_n449) );
XNOR2X1TS U9608 ( .A(Op_MX[8]), .B(Op_MY[13]), .Y(n10323) );
OAI22X1TS U9609 ( .A0(n10325), .A1(n10323), .B0(n954), .B1(n1070), .Y(
DP_OP_347J35_131_5122_n455) );
OAI22X1TS U9610 ( .A0(n10325), .A1(n10324), .B0(n10323), .B1(n1070), .Y(
DP_OP_347J35_131_5122_n456) );
INVX2TS U9611 ( .A(DP_OP_347J35_131_5122_n412), .Y(
DP_OP_347J35_131_5122_n413) );
OAI22X1TS U9612 ( .A0(n6354), .A1(n1081), .B0(n10383), .B1(n965), .Y(
DP_OP_347J35_131_5122_n407) );
INVX2TS U9613 ( .A(DP_OP_347J35_131_5122_n407), .Y(
DP_OP_347J35_131_5122_n408) );
NOR2X1TS U9614 ( .A(n10425), .B(n10421), .Y(DP_OP_347J35_131_5122_n174) );
NOR2X1TS U9615 ( .A(n10420), .B(n10423), .Y(DP_OP_347J35_131_5122_n144) );
NOR2X1TS U9616 ( .A(n10408), .B(n10428), .Y(DP_OP_347J35_131_5122_n151) );
NOR2X1TS U9617 ( .A(n10428), .B(n10403), .Y(DP_OP_347J35_131_5122_n183) );
XNOR2X1TS U9618 ( .A(Op_MX[1]), .B(Op_MY[6]), .Y(n10364) );
OAI22X1TS U9619 ( .A0(n10366), .A1(n10364), .B0(n948), .B1(n1087), .Y(
DP_OP_347J35_131_5122_n310) );
INVX2TS U9620 ( .A(n10336), .Y(DP_OP_347J35_131_5122_n128) );
XNOR2X1TS U9621 ( .A(Op_MX[5]), .B(Op_MY[3]), .Y(n10369) );
OAI22X1TS U9622 ( .A0(n6439), .A1(n10369), .B0(n10370), .B1(n10337), .Y(
DP_OP_347J35_131_5122_n295) );
INVX2TS U9623 ( .A(n10338), .Y(DP_OP_347J35_131_5122_n224) );
OAI22X1TS U9624 ( .A0(n6441), .A1(n975), .B0(n10372), .B1(n1167), .Y(
DP_OP_347J35_131_5122_n262) );
XNOR2X1TS U9625 ( .A(Op_MX[3]), .B(Op_MY[5]), .Y(n10342) );
OAI22X1TS U9626 ( .A0(n6447), .A1(n10342), .B0(n10422), .B1(n10339), .Y(
DP_OP_347J35_131_5122_n302) );
NOR2X1TS U9627 ( .A(n10419), .B(n10426), .Y(DP_OP_347J35_131_5122_n201) );
NOR2X1TS U9628 ( .A(n10425), .B(n10413), .Y(DP_OP_347J35_131_5122_n158) );
XNOR2X1TS U9629 ( .A(Op_MX[3]), .B(Op_MY[4]), .Y(n10367) );
OAI22X1TS U9630 ( .A0(n6447), .A1(n10367), .B0(n10422), .B1(n10342), .Y(
DP_OP_347J35_131_5122_n303) );
ADDHXLTS U9631 ( .A(n10344), .B(n10343), .CO(DP_OP_347J35_131_5122_n422),
.S(n6421) );
CMPR32X2TS U9632 ( .A(n10347), .B(n10346), .C(n10345), .CO(
DP_OP_347J35_131_5122_n37), .S(DP_OP_347J35_131_5122_n38) );
CMPR32X2TS U9633 ( .A(n10349), .B(n10348), .C(n10352), .CO(
DP_OP_347J35_131_5122_n126), .S(n6490) );
ADDHXLTS U9634 ( .A(n10351), .B(n10350), .CO(DP_OP_347J35_131_5122_n277),
.S(n6533) );
INVX2TS U9635 ( .A(n10352), .Y(DP_OP_347J35_131_5122_n234) );
INVX2TS U9636 ( .A(n10353), .Y(DP_OP_347J35_131_5122_n228) );
INVX2TS U9637 ( .A(n10354), .Y(DP_OP_347J35_131_5122_n226) );
INVX2TS U9638 ( .A(n10355), .Y(DP_OP_347J35_131_5122_n227) );
INVX2TS U9639 ( .A(n10356), .Y(DP_OP_347J35_131_5122_n231) );
INVX2TS U9640 ( .A(n10357), .Y(DP_OP_347J35_131_5122_n232) );
INVX2TS U9641 ( .A(n10358), .Y(DP_OP_347J35_131_5122_n230) );
INVX2TS U9642 ( .A(n10359), .Y(DP_OP_347J35_131_5122_n229) );
INVX2TS U9643 ( .A(n10360), .Y(DP_OP_347J35_131_5122_n223) );
XNOR2X1TS U9644 ( .A(Op_MX[5]), .B(Op_MY[2]), .Y(n10371) );
OAI22X1TS U9645 ( .A0(n6439), .A1(n10361), .B0(n10370), .B1(n10371), .Y(
DP_OP_347J35_131_5122_n297) );
INVX2TS U9646 ( .A(n10362), .Y(DP_OP_347J35_131_5122_n233) );
NOR2BX1TS U9647 ( .AN(Op_MY[0]), .B(n10372), .Y(DP_OP_347J35_131_5122_n291)
);
OAI22X1TS U9648 ( .A0(n6441), .A1(n1157), .B0(n10372), .B1(n946), .Y(
DP_OP_347J35_131_5122_n290) );
INVX2TS U9649 ( .A(n10363), .Y(DP_OP_347J35_131_5122_n225) );
OAI22X1TS U9650 ( .A0(n10366), .A1(n10365), .B0(n10364), .B1(n1087), .Y(
DP_OP_347J35_131_5122_n311) );
OAI22X1TS U9651 ( .A0(n6447), .A1(n10368), .B0(n10422), .B1(n10367), .Y(
DP_OP_347J35_131_5122_n304) );
OAI22X1TS U9652 ( .A0(n6439), .A1(n10371), .B0(n10370), .B1(n10369), .Y(
DP_OP_347J35_131_5122_n296) );
OAI22X1TS U9653 ( .A0(n6441), .A1(n946), .B0(n10372), .B1(n975), .Y(
DP_OP_347J35_131_5122_n267) );
INVX2TS U9654 ( .A(DP_OP_347J35_131_5122_n267), .Y(
DP_OP_347J35_131_5122_n268) );
INVX2TS U9655 ( .A(n10373), .Y(DP_OP_347J35_131_5122_n129) );
INVX2TS U9656 ( .A(n10374), .Y(DP_OP_347J35_131_5122_n134) );
INVX2TS U9657 ( .A(n10375), .Y(DP_OP_347J35_131_5122_n132) );
INVX2TS U9658 ( .A(n10376), .Y(DP_OP_347J35_131_5122_n133) );
NOR2X1TS U9659 ( .A(n10420), .B(n10407), .Y(DP_OP_347J35_131_5122_n147) );
NOR2BX1TS U9660 ( .AN(Op_MY[7]), .B(n10383), .Y(DP_OP_347J35_131_5122_n436)
);
INVX2TS U9661 ( .A(n10384), .Y(DP_OP_347J35_131_5122_n130) );
INVX2TS U9662 ( .A(n10385), .Y(DP_OP_347J35_131_5122_n131) );
INVX2TS U9663 ( .A(DP_OP_347J35_131_5122_n262), .Y(
DP_OP_347J35_131_5122_n263) );
NOR2X1TS U9664 ( .A(n10420), .B(n10412), .Y(DP_OP_347J35_131_5122_n146) );
NOR2X1TS U9665 ( .A(n10403), .B(n10393), .Y(DP_OP_347J35_131_5122_n189) );
NOR2X1TS U9666 ( .A(n10408), .B(n10402), .Y(DP_OP_347J35_131_5122_n156) );
CMPR32X2TS U9667 ( .A(n10390), .B(n10389), .C(n10388), .CO(
DP_OP_347J35_131_5122_n102), .S(DP_OP_347J35_131_5122_n103) );
ADDHXLTS U9668 ( .A(n10392), .B(n10391), .CO(n10395), .S(n6484) );
CMPR32X2TS U9669 ( .A(n10396), .B(n10395), .C(n10394), .CO(
DP_OP_347J35_131_5122_n117), .S(DP_OP_347J35_131_5122_n118) );
CMPR32X2TS U9670 ( .A(n10401), .B(n10400), .C(n10399), .CO(
DP_OP_347J35_131_5122_n81), .S(DP_OP_347J35_131_5122_n82) );
NOR2X1TS U9671 ( .A(n10421), .B(n10402), .Y(DP_OP_347J35_131_5122_n180) );
NOR2X1TS U9672 ( .A(n10420), .B(n10402), .Y(DP_OP_347J35_131_5122_n148) );
NOR2X1TS U9673 ( .A(n10411), .B(n10407), .Y(DP_OP_347J35_131_5122_n171) );
NOR2X1TS U9674 ( .A(n10413), .B(n10423), .Y(DP_OP_347J35_131_5122_n160) );
CMPR32X2TS U9675 ( .A(n10406), .B(n10405), .C(n10404), .CO(
DP_OP_347J35_131_5122_n57), .S(DP_OP_347J35_131_5122_n58) );
NOR2X1TS U9676 ( .A(n10408), .B(n10407), .Y(DP_OP_347J35_131_5122_n155) );
ADDHXLTS U9677 ( .A(n10415), .B(n10414), .CO(n10417), .S(
DP_OP_347J35_131_5122_n84) );
CMPR32X2TS U9678 ( .A(n10418), .B(n10417), .C(n10416), .CO(
DP_OP_347J35_131_5122_n68), .S(DP_OP_347J35_131_5122_n69) );
NOR2X1TS U9679 ( .A(n10420), .B(n10419), .Y(DP_OP_347J35_131_5122_n145) );
NOR2X1TS U9680 ( .A(n10428), .B(n10421), .Y(DP_OP_347J35_131_5122_n175) );
AO21XLTS U9681 ( .A0(n6447), .A1(n10422), .B0(n953), .Y(
DP_OP_347J35_131_5122_n300) );
NOR2X1TS U9682 ( .A(n10423), .B(n10426), .Y(DP_OP_347J35_131_5122_n200) );
NOR2X1TS U9683 ( .A(n10423), .B(n10427), .Y(DP_OP_347J35_131_5122_n192) );
AO21XLTS U9684 ( .A0(n6358), .A1(n10424), .B0(n952), .Y(
DP_OP_347J35_131_5122_n445) );
NOR2X1TS U9685 ( .A(n10425), .B(n10426), .Y(DP_OP_347J35_131_5122_n198) );
NOR2X1TS U9686 ( .A(n10428), .B(n10426), .Y(DP_OP_347J35_131_5122_n199) );
NOR2X1TS U9687 ( .A(n10428), .B(n10427), .Y(DP_OP_347J35_131_5122_n191) );
BUFX4TS U9688 ( .A(n286), .Y(n11245) );
BUFX4TS U9689 ( .A(n286), .Y(n11244) );
BUFX4TS U9690 ( .A(n286), .Y(n11243) );
BUFX4TS U9691 ( .A(n286), .Y(n11242) );
BUFX4TS U9692 ( .A(n286), .Y(n11246) );
BUFX4TS U9693 ( .A(n286), .Y(n11247) );
BUFX4TS U9694 ( .A(n11231), .Y(n11227) );
BUFX4TS U9695 ( .A(n11249), .Y(n11228) );
BUFX6TS U9696 ( .A(n754), .Y(n11235) );
BUFX6TS U9697 ( .A(n754), .Y(n11231) );
BUFX4TS U9698 ( .A(n11234), .Y(n11232) );
BUFX4TS U9699 ( .A(n11249), .Y(n11233) );
BUFX6TS U9700 ( .A(n754), .Y(n11234) );
NAND3X1TS U9701 ( .A(n10429), .B(FS_Module_state_reg[2]), .C(
FS_Module_state_reg[0]), .Y(n11011) );
NAND2BXLTS U9702 ( .AN(n11011), .B(P_Sgf[105]), .Y(n10492) );
NAND3X1TS U9703 ( .A(FS_Module_state_reg[0]), .B(n11225), .C(n11175), .Y(
n11012) );
NOR2X4TS U9704 ( .A(FS_Module_state_reg[3]), .B(n11012), .Y(n11056) );
INVX2TS U9705 ( .A(n11056), .Y(n11054) );
NAND2X1TS U9706 ( .A(n11158), .B(n11054), .Y(n10430) );
AO21XLTS U9707 ( .A0(n10492), .A1(FSM_selector_B[0]), .B0(n10430), .Y(n419)
);
CLKXOR2X2TS U9708 ( .A(Op_MX[63]), .B(Op_MY[63]), .Y(n10494) );
NOR4X1TS U9709 ( .A(P_Sgf[0]), .B(P_Sgf[1]), .C(P_Sgf[2]), .D(P_Sgf[3]), .Y(
n10446) );
NOR4X1TS U9710 ( .A(P_Sgf[4]), .B(P_Sgf[5]), .C(P_Sgf[6]), .D(P_Sgf[7]), .Y(
n10445) );
NOR4X1TS U9711 ( .A(P_Sgf[48]), .B(P_Sgf[49]), .C(P_Sgf[50]), .D(P_Sgf[51]),
.Y(n10444) );
OR4X2TS U9712 ( .A(P_Sgf[44]), .B(P_Sgf[45]), .C(P_Sgf[46]), .D(P_Sgf[47]),
.Y(n10442) );
OR4X2TS U9713 ( .A(P_Sgf[40]), .B(P_Sgf[41]), .C(P_Sgf[42]), .D(P_Sgf[43]),
.Y(n10441) );
NOR4X1TS U9714 ( .A(P_Sgf[8]), .B(P_Sgf[9]), .C(P_Sgf[10]), .D(P_Sgf[11]),
.Y(n10434) );
NOR4X1TS U9715 ( .A(P_Sgf[12]), .B(P_Sgf[13]), .C(P_Sgf[14]), .D(P_Sgf[15]),
.Y(n10433) );
NOR4X1TS U9716 ( .A(P_Sgf[20]), .B(P_Sgf[21]), .C(P_Sgf[22]), .D(P_Sgf[23]),
.Y(n10431) );
NAND4XLTS U9717 ( .A(n10434), .B(n10433), .C(n10432), .D(n10431), .Y(n10440)
);
NOR4X1TS U9718 ( .A(P_Sgf[24]), .B(P_Sgf[25]), .C(P_Sgf[26]), .D(P_Sgf[27]),
.Y(n10438) );
NOR4X1TS U9719 ( .A(P_Sgf[28]), .B(P_Sgf[29]), .C(P_Sgf[30]), .D(P_Sgf[31]),
.Y(n10437) );
NOR4X1TS U9720 ( .A(P_Sgf[32]), .B(P_Sgf[33]), .C(P_Sgf[34]), .D(P_Sgf[35]),
.Y(n10436) );
NOR4X1TS U9721 ( .A(P_Sgf[36]), .B(P_Sgf[37]), .C(P_Sgf[38]), .D(P_Sgf[39]),
.Y(n10435) );
NAND4XLTS U9722 ( .A(n10438), .B(n10437), .C(n10436), .D(n10435), .Y(n10439)
);
NOR4X1TS U9723 ( .A(n10442), .B(n10441), .C(n10440), .D(n10439), .Y(n10443)
);
NAND4XLTS U9724 ( .A(n10446), .B(n10445), .C(n10444), .D(n10443), .Y(n10448)
);
MXI2X1TS U9725 ( .A(n10494), .B(round_mode[1]), .S0(round_mode[0]), .Y(
n10447) );
OAI211X1TS U9726 ( .A0(n10494), .A1(round_mode[1]), .B0(n10448), .C0(n10447),
.Y(n10490) );
OAI31X1TS U9727 ( .A0(n11225), .A1(n10496), .A2(n10490), .B0(n11177), .Y(
n709) );
MX2X1TS U9728 ( .A(P_Sgf[26]), .B(n10451), .S0(n10643), .Y(n447) );
ADDFHX4TS U9729 ( .A(n10462), .B(n10461), .CI(n10460), .CO(n10465), .S(
n10463) );
AFHCONX2TS U9730 ( .A(n10466), .B(n10465), .CI(n10464), .CON(n10471), .S(
n10467) );
NOR2X1TS U9731 ( .A(n11175), .B(n11176), .Y(n10536) );
AOI32X1TS U9732 ( .A0(FS_Module_state_reg[3]), .A1(n11009), .A2(n10490),
.B0(n11225), .B1(n11009), .Y(n10491) );
OAI31X1TS U9733 ( .A0(n11225), .A1(n10536), .A2(n11196), .B0(n10491), .Y(
n712) );
OAI31X1TS U9734 ( .A0(n11056), .A1(n11141), .A2(n11199), .B0(n10492), .Y(
n418) );
NOR2XLTS U9735 ( .A(n11012), .B(n11176), .Y(n10493) );
BUFX3TS U9736 ( .A(n10493), .Y(n11172) );
NOR2XLTS U9737 ( .A(n10494), .B(underflow_flag), .Y(n10495) );
OAI32X1TS U9738 ( .A0(n11169), .A1(n10495), .A2(overflow_flag), .B0(n11172),
.B1(n11224), .Y(n287) );
INVX2TS U9739 ( .A(n10496), .Y(n10499) );
AOI32X4TS U9740 ( .A0(FSM_add_overflow_flag), .A1(n11225), .A2(n10499), .B0(
n10497), .B1(n11225), .Y(n11061) );
BUFX4TS U9741 ( .A(n10507), .Y(n10914) );
AOI32X1TS U9742 ( .A0(FS_Module_state_reg[2]), .A1(n11225), .A2(n11176),
.B0(n10499), .B1(n11225), .Y(n10500) );
INVX2TS U9743 ( .A(n10500), .Y(n11060) );
INVX4TS U9744 ( .A(n11060), .Y(n11000) );
AOI22X1TS U9745 ( .A0(Add_result[1]), .A1(n10507), .B0(
Sgf_normalized_result[0]), .B1(n11000), .Y(n10504) );
NAND2X1TS U9746 ( .A(n11060), .B(n11061), .Y(n10501) );
NOR2X1TS U9747 ( .A(FSM_selector_C), .B(n10501), .Y(n11003) );
INVX2TS U9748 ( .A(n11003), .Y(n10854) );
INVX6TS U9749 ( .A(n10854), .Y(n10997) );
NOR2X2TS U9750 ( .A(n11177), .B(n10501), .Y(n10502) );
BUFX6TS U9751 ( .A(n10502), .Y(n10921) );
AOI22X1TS U9752 ( .A0(n10997), .A1(P_Sgf[52]), .B0(n10921), .B1(
Add_result[0]), .Y(n10503) );
OAI211XLTS U9753 ( .A0(n10498), .A1(n11215), .B0(n10504), .C0(n10503), .Y(
n353) );
INVX3TS U9754 ( .A(n11060), .Y(n11058) );
AOI22X1TS U9755 ( .A0(Sgf_normalized_result[3]), .A1(n11058), .B0(n10507),
.B1(Add_result[4]), .Y(n10506) );
AOI22X1TS U9756 ( .A0(n10997), .A1(P_Sgf[55]), .B0(n10921), .B1(
Add_result[3]), .Y(n10505) );
BUFX6TS U9757 ( .A(n10914), .Y(n10994) );
AOI22X1TS U9758 ( .A0(Sgf_normalized_result[4]), .A1(n11058), .B0(n10994),
.B1(Add_result[5]), .Y(n10509) );
AOI22X1TS U9759 ( .A0(n10997), .A1(P_Sgf[56]), .B0(n10921), .B1(
Add_result[4]), .Y(n10508) );
AOI22X1TS U9760 ( .A0(Sgf_normalized_result[6]), .A1(n11058), .B0(n10994),
.B1(Add_result[7]), .Y(n10511) );
AOI22X1TS U9761 ( .A0(n10997), .A1(P_Sgf[58]), .B0(n10921), .B1(
Add_result[6]), .Y(n10510) );
AOI22X1TS U9762 ( .A0(Sgf_normalized_result[2]), .A1(n11058), .B0(n10507),
.B1(Add_result[3]), .Y(n10513) );
AOI22X1TS U9763 ( .A0(n10997), .A1(P_Sgf[54]), .B0(n10921), .B1(
Add_result[2]), .Y(n10512) );
AOI22X1TS U9764 ( .A0(Add_result[2]), .A1(n10507), .B0(
Sgf_normalized_result[1]), .B1(n11000), .Y(n10515) );
AOI22X1TS U9765 ( .A0(n10997), .A1(P_Sgf[53]), .B0(n10921), .B1(
Add_result[1]), .Y(n10514) );
OAI211XLTS U9766 ( .A0(n10498), .A1(n11214), .B0(n10515), .C0(n10514), .Y(
n354) );
AOI22X1TS U9767 ( .A0(Sgf_normalized_result[7]), .A1(n11058), .B0(
Add_result[8]), .B1(n10507), .Y(n10517) );
AOI22X1TS U9768 ( .A0(n10997), .A1(P_Sgf[59]), .B0(n10921), .B1(
Add_result[7]), .Y(n10516) );
OAI211XLTS U9769 ( .A0(n10498), .A1(n11222), .B0(n10517), .C0(n10516), .Y(
n360) );
AOI22X1TS U9770 ( .A0(Sgf_normalized_result[5]), .A1(n11058), .B0(n10507),
.B1(Add_result[6]), .Y(n10519) );
AOI22X1TS U9771 ( .A0(n10997), .A1(P_Sgf[57]), .B0(n10921), .B1(
Add_result[5]), .Y(n10518) );
OAI211XLTS U9772 ( .A0(n10498), .A1(n11210), .B0(n10519), .C0(n10518), .Y(
n358) );
AOI22X1TS U9773 ( .A0(Sgf_normalized_result[14]), .A1(n11058), .B0(
Add_result[15]), .B1(n10914), .Y(n10521) );
AOI22X1TS U9774 ( .A0(Add_result[14]), .A1(n11005), .B0(n10997), .B1(
P_Sgf[66]), .Y(n10520) );
OAI211XLTS U9775 ( .A0(n10498), .A1(n11206), .B0(n10521), .C0(n10520), .Y(
n367) );
AOI22X1TS U9776 ( .A0(Sgf_normalized_result[10]), .A1(n11058), .B0(n868),
.B1(n10994), .Y(n10523) );
AOI22X1TS U9777 ( .A0(Add_result[10]), .A1(n11005), .B0(n10997), .B1(
P_Sgf[62]), .Y(n10522) );
OAI211XLTS U9778 ( .A0(n10498), .A1(n11219), .B0(n10523), .C0(n10522), .Y(
n363) );
AOI22X1TS U9779 ( .A0(Sgf_normalized_result[8]), .A1(n11058), .B0(n867),
.B1(n10994), .Y(n10525) );
AOI22X1TS U9780 ( .A0(Add_result[8]), .A1(n11005), .B0(n10997), .B1(
P_Sgf[60]), .Y(n10524) );
OAI211XLTS U9781 ( .A0(n10498), .A1(n11221), .B0(n10525), .C0(n10524), .Y(
n361) );
INVX4TS U9782 ( .A(n11060), .Y(n10960) );
AOI22X1TS U9783 ( .A0(Sgf_normalized_result[12]), .A1(n10960), .B0(n869),
.B1(n10994), .Y(n10527) );
AOI22X1TS U9784 ( .A0(Add_result[12]), .A1(n11005), .B0(n10997), .B1(
P_Sgf[64]), .Y(n10526) );
OAI211XLTS U9785 ( .A0(n10498), .A1(n11217), .B0(n10527), .C0(n10526), .Y(
n365) );
AOI22X1TS U9786 ( .A0(Sgf_normalized_result[11]), .A1(n11058), .B0(
Add_result[12]), .B1(n10507), .Y(n10529) );
AOI22X1TS U9787 ( .A0(n868), .A1(n11005), .B0(n10997), .B1(P_Sgf[63]), .Y(
n10528) );
OAI211XLTS U9788 ( .A0(n10498), .A1(n11218), .B0(n10529), .C0(n10528), .Y(
n364) );
AOI22X1TS U9789 ( .A0(Sgf_normalized_result[13]), .A1(n11058), .B0(
Add_result[14]), .B1(n10507), .Y(n10531) );
AOI22X1TS U9790 ( .A0(n869), .A1(n11005), .B0(n10997), .B1(P_Sgf[65]), .Y(
n10530) );
OAI211XLTS U9791 ( .A0(n10498), .A1(n11216), .B0(n10531), .C0(n10530), .Y(
n366) );
AOI22X1TS U9792 ( .A0(Sgf_normalized_result[9]), .A1(n11058), .B0(
Add_result[10]), .B1(n10507), .Y(n10533) );
AOI22X1TS U9793 ( .A0(n867), .A1(n11005), .B0(n10997), .B1(P_Sgf[61]), .Y(
n10532) );
OAI211XLTS U9794 ( .A0(n10498), .A1(n11220), .B0(n10533), .C0(n10532), .Y(
n362) );
AOI22X1TS U9795 ( .A0(FSM_selector_C), .A1(Add_result[52]), .B0(P_Sgf[104]),
.B1(n11177), .Y(n11059) );
AOI22X1TS U9796 ( .A0(Sgf_normalized_result[51]), .A1(n11000), .B0(
Add_result[51]), .B1(n10921), .Y(n10535) );
NAND2X1TS U9797 ( .A(n10997), .B(P_Sgf[103]), .Y(n10534) );
OAI211XLTS U9798 ( .A0(n11061), .A1(n11059), .B0(n10535), .C0(n10534), .Y(
n404) );
NAND3XLTS U9799 ( .A(n10536), .B(n11196), .C(n11248), .Y(n10537) );
INVX2TS U9800 ( .A(n10537), .Y(ready) );
INVX2TS U9801 ( .A(n10450), .Y(n11007) );
OAI22X2TS U9802 ( .A0(beg_FSM), .A1(n11249), .B0(ack_FSM), .B1(n10537), .Y(
n11010) );
OAI21XLTS U9803 ( .A0(n11175), .A1(n11010), .B0(FS_Module_state_reg[3]), .Y(
n10538) );
OAI211XLTS U9804 ( .A0(n11007), .A1(n11223), .B0(n10538), .C0(n10960), .Y(
n714) );
MX2X1TS U9805 ( .A(Data_MY[14]), .B(Op_MY[14]), .S0(n10682), .Y(n596) );
MX2X1TS U9806 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n10553), .Y(n660) );
INVX6TS U9807 ( .A(n9512), .Y(n10553) );
MX2X1TS U9808 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n10553), .Y(n673) );
MX2X1TS U9809 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n10553), .Y(n674) );
NOR3BX1TS U9810 ( .AN(Op_MY[62]), .B(FSM_selector_B[0]), .C(
FSM_selector_B[1]), .Y(n10539) );
XOR2X1TS U9811 ( .A(n10450), .B(n10539), .Y(DP_OP_36J35_134_7156_n18) );
OAI2BB1X1TS U9812 ( .A0N(Op_MY[61]), .A1N(n11199), .B0(n10549), .Y(n10540)
);
XOR2X1TS U9813 ( .A(n10450), .B(n10540), .Y(DP_OP_36J35_134_7156_n19) );
OAI2BB1X1TS U9814 ( .A0N(Op_MY[60]), .A1N(n11199), .B0(n10549), .Y(n10541)
);
XOR2X1TS U9815 ( .A(n10450), .B(n10541), .Y(DP_OP_36J35_134_7156_n20) );
OAI2BB1X1TS U9816 ( .A0N(Op_MY[59]), .A1N(n11199), .B0(n10549), .Y(n10542)
);
XOR2X1TS U9817 ( .A(n10450), .B(n10542), .Y(DP_OP_36J35_134_7156_n21) );
OAI2BB1X1TS U9818 ( .A0N(Op_MY[58]), .A1N(n11199), .B0(n10549), .Y(n10543)
);
XOR2X1TS U9819 ( .A(n10450), .B(n10543), .Y(DP_OP_36J35_134_7156_n22) );
OAI2BB1X1TS U9820 ( .A0N(Op_MY[57]), .A1N(n11199), .B0(n10549), .Y(n10544)
);
XOR2X1TS U9821 ( .A(n10450), .B(n10544), .Y(DP_OP_36J35_134_7156_n23) );
OAI2BB1X1TS U9822 ( .A0N(Op_MY[56]), .A1N(n11199), .B0(n10549), .Y(n10545)
);
XOR2X1TS U9823 ( .A(n10450), .B(n10545), .Y(DP_OP_36J35_134_7156_n24) );
OAI2BB1X1TS U9824 ( .A0N(Op_MY[55]), .A1N(n11199), .B0(n10549), .Y(n10546)
);
XOR2X1TS U9825 ( .A(n10450), .B(n10546), .Y(DP_OP_36J35_134_7156_n25) );
OAI2BB1X1TS U9826 ( .A0N(Op_MY[54]), .A1N(n11199), .B0(n10549), .Y(n10547)
);
XOR2X1TS U9827 ( .A(n10450), .B(n10547), .Y(DP_OP_36J35_134_7156_n26) );
OAI2BB1X1TS U9828 ( .A0N(Op_MY[53]), .A1N(n11199), .B0(n10549), .Y(n10548)
);
XOR2X1TS U9829 ( .A(n10450), .B(n10548), .Y(DP_OP_36J35_134_7156_n27) );
NOR2XLTS U9830 ( .A(FSM_selector_B[1]), .B(Op_MY[52]), .Y(n10550) );
XOR2X1TS U9831 ( .A(n10450), .B(n10551), .Y(DP_OP_36J35_134_7156_n28) );
MX2X1TS U9832 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n10553), .Y(n672) );
MX2X1TS U9833 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n10554), .Y(n671) );
MX2X1TS U9834 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n10554), .Y(n670) );
MX2X1TS U9835 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n10554), .Y(n669) );
MX2X1TS U9836 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n10554), .Y(n668) );
MX2X1TS U9837 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n10554), .Y(n667) );
MX2X1TS U9838 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n10553), .Y(n666) );
MX2X1TS U9839 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n10553), .Y(n665) );
MX2X1TS U9840 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n10681), .Y(n664) );
MX2X1TS U9841 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n10554), .Y(n663) );
MX2X1TS U9842 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n10554), .Y(n662) );
MX2X1TS U9843 ( .A(Data_MX[15]), .B(n883), .S0(n11006), .Y(n661) );
MX2X1TS U9844 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n10681), .Y(n659) );
MX2X1TS U9845 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n10554), .Y(n658) );
MX2X1TS U9846 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(n10553), .Y(n657) );
MX2X1TS U9847 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n10552), .Y(n656) );
MX2X1TS U9848 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n10553), .Y(n655) );
MX2X1TS U9849 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n10554), .Y(n654) );
MX2X1TS U9850 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(n10552), .Y(n653) );
MX2X1TS U9851 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n10553), .Y(n652) );
MX2X1TS U9852 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n10552), .Y(n651) );
MX2X1TS U9853 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n10681), .Y(n650) );
MX2X1TS U9854 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(n10554), .Y(n649) );
MX2X1TS U9855 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(n10554), .Y(n648) );
MX2X1TS U9856 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n11006), .Y(n647) );
MX2X1TS U9857 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n10552), .Y(n646) );
MX2X1TS U9858 ( .A(Data_MX[51]), .B(Op_MX[51]), .S0(n10552), .Y(n697) );
MX2X1TS U9859 ( .A(Data_MX[49]), .B(Op_MX[49]), .S0(n10552), .Y(n695) );
MX2X1TS U9860 ( .A(Data_MX[47]), .B(Op_MX[47]), .S0(n10552), .Y(n693) );
MX2X1TS U9861 ( .A(Data_MX[46]), .B(Op_MX[46]), .S0(n10552), .Y(n692) );
MX2X1TS U9862 ( .A(Data_MX[45]), .B(n881), .S0(n10552), .Y(n691) );
MX2X1TS U9863 ( .A(Data_MX[44]), .B(Op_MX[44]), .S0(n10552), .Y(n690) );
MX2X1TS U9864 ( .A(Data_MX[43]), .B(Op_MX[43]), .S0(n10552), .Y(n689) );
MX2X1TS U9865 ( .A(Data_MX[42]), .B(Op_MX[42]), .S0(n10552), .Y(n688) );
MX2X1TS U9866 ( .A(Data_MX[41]), .B(Op_MX[41]), .S0(n10552), .Y(n687) );
MX2X1TS U9867 ( .A(Data_MX[40]), .B(Op_MX[40]), .S0(n10552), .Y(n686) );
MX2X1TS U9868 ( .A(Data_MX[39]), .B(Op_MX[39]), .S0(n10553), .Y(n685) );
MX2X1TS U9869 ( .A(Data_MX[38]), .B(Op_MX[38]), .S0(n10553), .Y(n684) );
MX2X1TS U9870 ( .A(Data_MX[37]), .B(Op_MX[37]), .S0(n10553), .Y(n683) );
MX2X1TS U9871 ( .A(Data_MX[36]), .B(Op_MX[36]), .S0(n10553), .Y(n682) );
MX2X1TS U9872 ( .A(Data_MX[35]), .B(Op_MX[35]), .S0(n10553), .Y(n681) );
MX2X1TS U9873 ( .A(Data_MX[34]), .B(Op_MX[34]), .S0(n10553), .Y(n680) );
MX2X1TS U9874 ( .A(Data_MX[33]), .B(Op_MX[33]), .S0(n10553), .Y(n679) );
MX2X1TS U9875 ( .A(Data_MX[32]), .B(Op_MX[32]), .S0(n10553), .Y(n678) );
MX2X1TS U9876 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(n10553), .Y(n677) );
MX2X1TS U9877 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n10553), .Y(n676) );
MX2X1TS U9878 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n10553), .Y(n675) );
MX2X1TS U9879 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n10682), .Y(n608) );
MX2X1TS U9880 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n10682), .Y(n607) );
MX2X1TS U9881 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n10682), .Y(n606) );
MX2X1TS U9882 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n10682), .Y(n605) );
MX2X1TS U9883 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(n10682), .Y(n604) );
MX2X1TS U9884 ( .A(Data_MY[20]), .B(Op_MY[20]), .S0(n10682), .Y(n602) );
MX2X1TS U9885 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n10682), .Y(n601) );
MX2X1TS U9886 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n10682), .Y(n600) );
MX2X1TS U9887 ( .A(Data_MY[17]), .B(Op_MY[17]), .S0(n10682), .Y(n599) );
MX2X1TS U9888 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n10682), .Y(n598) );
MX2X1TS U9889 ( .A(Data_MY[15]), .B(Op_MY[15]), .S0(n10682), .Y(n597) );
MX2X1TS U9890 ( .A(Data_MY[13]), .B(Op_MY[13]), .S0(n11006), .Y(n595) );
MX2X1TS U9891 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n11006), .Y(n594) );
MX2X1TS U9892 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n11006), .Y(n593) );
MX2X1TS U9893 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n11006), .Y(n592) );
MX2X1TS U9894 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n11006), .Y(n591) );
MX2X1TS U9895 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n11006), .Y(n590) );
MX2X1TS U9896 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n11006), .Y(n589) );
MX2X1TS U9897 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n11006), .Y(n588) );
MX2X1TS U9898 ( .A(Data_MY[5]), .B(Op_MY[5]), .S0(n11006), .Y(n587) );
MX2X1TS U9899 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n11006), .Y(n586) );
MX2X1TS U9900 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(n11006), .Y(n585) );
MX2X1TS U9901 ( .A(Data_MY[2]), .B(Op_MY[2]), .S0(n11006), .Y(n584) );
MX2X1TS U9902 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n11006), .Y(n583) );
MX2X1TS U9903 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n11006), .Y(n582) );
MX2X1TS U9904 ( .A(Data_MY[51]), .B(Op_MY[51]), .S0(n11006), .Y(n633) );
MX2X1TS U9905 ( .A(Data_MY[50]), .B(Op_MY[50]), .S0(n11006), .Y(n632) );
MX2X1TS U9906 ( .A(Data_MY[49]), .B(Op_MY[49]), .S0(n10681), .Y(n631) );
MX2X1TS U9907 ( .A(Data_MY[48]), .B(Op_MY[48]), .S0(n10681), .Y(n630) );
MX2X1TS U9908 ( .A(Data_MY[47]), .B(Op_MY[47]), .S0(n10681), .Y(n629) );
MX2X1TS U9909 ( .A(Data_MY[46]), .B(Op_MY[46]), .S0(n10681), .Y(n628) );
MX2X1TS U9910 ( .A(Data_MY[45]), .B(Op_MY[45]), .S0(n11006), .Y(n627) );
MX2X1TS U9911 ( .A(Data_MY[44]), .B(Op_MY[44]), .S0(n11006), .Y(n626) );
MX2X1TS U9912 ( .A(Data_MY[42]), .B(Op_MY[42]), .S0(n10681), .Y(n624) );
MX2X1TS U9913 ( .A(Data_MY[41]), .B(Op_MY[41]), .S0(n11006), .Y(n623) );
MX2X1TS U9914 ( .A(Data_MY[40]), .B(Op_MY[40]), .S0(n11006), .Y(n622) );
MX2X1TS U9915 ( .A(Data_MY[38]), .B(Op_MY[38]), .S0(n10554), .Y(n620) );
MX2X1TS U9916 ( .A(Data_MY[37]), .B(Op_MY[37]), .S0(n10554), .Y(n619) );
MX2X1TS U9917 ( .A(Data_MY[36]), .B(Op_MY[36]), .S0(n10554), .Y(n618) );
MX2X1TS U9918 ( .A(Data_MY[34]), .B(Op_MY[34]), .S0(n10554), .Y(n616) );
MX2X1TS U9919 ( .A(Data_MY[33]), .B(Op_MY[33]), .S0(n10554), .Y(n615) );
MX2X1TS U9920 ( .A(Data_MY[32]), .B(Op_MY[32]), .S0(n10554), .Y(n614) );
MX2X1TS U9921 ( .A(Data_MY[31]), .B(Op_MY[31]), .S0(n10554), .Y(n613) );
MX2X1TS U9922 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n10554), .Y(n612) );
MX2X1TS U9923 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n10554), .Y(n611) );
MX2X1TS U9924 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n10554), .Y(n610) );
MX2X1TS U9925 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n10554), .Y(n609) );
BUFX6TS U9926 ( .A(n10555), .Y(n10611) );
MX2X1TS U9927 ( .A(P_Sgf[0]), .B(n10556), .S0(n10611), .Y(n421) );
MX2X1TS U9928 ( .A(P_Sgf[1]), .B(n10557), .S0(n10611), .Y(n422) );
MX2X1TS U9929 ( .A(P_Sgf[2]), .B(n10558), .S0(n10611), .Y(n423) );
MX2X1TS U9930 ( .A(P_Sgf[3]), .B(n10559), .S0(n10611), .Y(n424) );
MX2X1TS U9931 ( .A(P_Sgf[4]), .B(n10560), .S0(n10611), .Y(n425) );
MX2X1TS U9932 ( .A(P_Sgf[5]), .B(n10561), .S0(n10611), .Y(n426) );
MX2X1TS U9933 ( .A(P_Sgf[6]), .B(n10562), .S0(n10611), .Y(n427) );
MX2X1TS U9934 ( .A(P_Sgf[7]), .B(n6529), .S0(n10611), .Y(n428) );
AFHCONX2TS U9935 ( .A(n10585), .B(n10584), .CI(n10583), .CON(n10587), .S(
n10586) );
AFHCINX2TS U9936 ( .CIN(n10587), .B(n10588), .A(n10589), .S(n10590), .CO(
n10591) );
AFHCONX2TS U9937 ( .A(n10593), .B(n10592), .CI(n10591), .CON(n10563), .S(
n10594) );
AFHCINX2TS U9938 ( .CIN(n10595), .B(n10596), .A(n10597), .S(n10598), .CO(
n10599) );
MX2X1TS U9939 ( .A(P_Sgf[40]), .B(n10598), .S0(n10611), .Y(n461) );
AFHCONX2TS U9940 ( .A(n10601), .B(n10600), .CI(n10599), .CON(n10603), .S(
n10602) );
MX2X1TS U9941 ( .A(P_Sgf[41]), .B(n10602), .S0(n10611), .Y(n462) );
AFHCINX2TS U9942 ( .CIN(n10603), .B(n10604), .A(n10605), .S(n10606), .CO(
n10607) );
MX2X1TS U9943 ( .A(P_Sgf[42]), .B(n10606), .S0(n10611), .Y(n463) );
AFHCONX2TS U9944 ( .A(n10609), .B(n10608), .CI(n10607), .CON(n10579), .S(
n10610) );
MX2X1TS U9945 ( .A(P_Sgf[8]), .B(n10612), .S0(n10611), .Y(n429) );
MX2X1TS U9946 ( .A(P_Sgf[9]), .B(n10613), .S0(n10643), .Y(n430) );
MX2X1TS U9947 ( .A(P_Sgf[10]), .B(n10614), .S0(n10643), .Y(n431) );
MX2X1TS U9948 ( .A(P_Sgf[11]), .B(n10615), .S0(n10643), .Y(n432) );
MX2X1TS U9949 ( .A(P_Sgf[12]), .B(n10616), .S0(n10643), .Y(n433) );
MX2X1TS U9950 ( .A(P_Sgf[13]), .B(n10617), .S0(n10643), .Y(n434) );
MX2X1TS U9951 ( .A(P_Sgf[14]), .B(n10618), .S0(n10643), .Y(n435) );
MX2X1TS U9952 ( .A(P_Sgf[15]), .B(n10619), .S0(n10643), .Y(n436) );
MX2X1TS U9953 ( .A(P_Sgf[16]), .B(n10620), .S0(n10643), .Y(n437) );
MX2X1TS U9954 ( .A(P_Sgf[17]), .B(n10621), .S0(n10643), .Y(n438) );
MX2X1TS U9955 ( .A(P_Sgf[18]), .B(n10622), .S0(n10643), .Y(n439) );
MX2X1TS U9956 ( .A(P_Sgf[19]), .B(n10623), .S0(n10643), .Y(n440) );
MX2X1TS U9957 ( .A(P_Sgf[20]), .B(n10624), .S0(n10643), .Y(n441) );
MX2X1TS U9958 ( .A(P_Sgf[21]), .B(n10625), .S0(n10643), .Y(n442) );
MX2X1TS U9959 ( .A(P_Sgf[22]), .B(n10626), .S0(n10643), .Y(n443) );
MX2X1TS U9960 ( .A(P_Sgf[23]), .B(n10627), .S0(n10643), .Y(n444) );
MX2X1TS U9961 ( .A(P_Sgf[24]), .B(n10628), .S0(n10643), .Y(n445) );
MX2X1TS U9962 ( .A(P_Sgf[25]), .B(n10629), .S0(n10643), .Y(n446) );
MX2X1TS U9963 ( .A(P_Sgf[27]), .B(n1170), .S0(n10643), .Y(n448) );
AFHCINX2TS U9964 ( .CIN(n10632), .B(n10633), .A(n10634), .S(n10635), .CO(
n10637) );
MX2X1TS U9965 ( .A(P_Sgf[28]), .B(n10635), .S0(n10643), .Y(n449) );
AFHCONX2TS U9966 ( .A(n10638), .B(n10637), .CI(n10636), .CON(n10640), .S(
n10639) );
MX2X1TS U9967 ( .A(P_Sgf[29]), .B(n10639), .S0(n10643), .Y(n450) );
AFHCINX2TS U9968 ( .CIN(n10640), .B(n10641), .A(n10642), .S(n10644), .CO(
n10645) );
MX2X1TS U9969 ( .A(P_Sgf[30]), .B(n10644), .S0(n10643), .Y(n451) );
AFHCONX2TS U9970 ( .A(n10647), .B(n10646), .CI(n10645), .CON(n10649), .S(
n10648) );
MX2X1TS U9971 ( .A(P_Sgf[31]), .B(n10648), .S0(n10782), .Y(n452) );
AFHCINX2TS U9972 ( .CIN(n10649), .B(n10650), .A(n10651), .S(n10652), .CO(
n10653) );
MX2X1TS U9973 ( .A(P_Sgf[32]), .B(n10652), .S0(n10782), .Y(n453) );
AFHCONX2TS U9974 ( .A(n10655), .B(n10654), .CI(n10653), .CON(n10657), .S(
n10656) );
MX2X1TS U9975 ( .A(P_Sgf[33]), .B(n10656), .S0(n10782), .Y(n454) );
AFHCINX2TS U9976 ( .CIN(n10657), .B(n10658), .A(n10659), .S(n10660), .CO(
n10661) );
MX2X1TS U9977 ( .A(P_Sgf[34]), .B(n10660), .S0(n10782), .Y(n455) );
AFHCONX2TS U9978 ( .A(n10663), .B(n10662), .CI(n10661), .CON(n10665), .S(
n10664) );
MX2X1TS U9979 ( .A(P_Sgf[35]), .B(n10664), .S0(n10782), .Y(n456) );
AFHCINX2TS U9980 ( .CIN(n10665), .B(n10666), .A(n10667), .S(n10668), .CO(
n10669) );
MX2X1TS U9981 ( .A(P_Sgf[36]), .B(n10668), .S0(n10782), .Y(n457) );
AFHCONX2TS U9982 ( .A(n10671), .B(n10670), .CI(n10669), .CON(n10673), .S(
n10672) );
MX2X1TS U9983 ( .A(P_Sgf[37]), .B(n10672), .S0(n10782), .Y(n458) );
AFHCINX2TS U9984 ( .CIN(n10673), .B(n10674), .A(n10675), .S(n10676), .CO(
n10677) );
MX2X1TS U9985 ( .A(P_Sgf[38]), .B(n10676), .S0(n10782), .Y(n459) );
AFHCONX2TS U9986 ( .A(n10679), .B(n10678), .CI(n10677), .CON(n10595), .S(
n10680) );
MX2X1TS U9987 ( .A(P_Sgf[39]), .B(n10680), .S0(n10782), .Y(n460) );
MX2X1TS U9988 ( .A(Data_MY[52]), .B(Op_MY[52]), .S0(n10681), .Y(n634) );
MX2X1TS U9989 ( .A(Data_MY[61]), .B(Op_MY[61]), .S0(n10681), .Y(n643) );
MX2X1TS U9990 ( .A(Data_MY[60]), .B(Op_MY[60]), .S0(n10681), .Y(n642) );
MX2X1TS U9991 ( .A(Data_MY[59]), .B(Op_MY[59]), .S0(n10681), .Y(n641) );
MX2X1TS U9992 ( .A(Data_MY[58]), .B(Op_MY[58]), .S0(n10681), .Y(n640) );
MX2X1TS U9993 ( .A(Data_MY[57]), .B(Op_MY[57]), .S0(n10681), .Y(n639) );
MX2X1TS U9994 ( .A(Data_MY[56]), .B(Op_MY[56]), .S0(n10681), .Y(n638) );
MX2X1TS U9995 ( .A(Data_MY[55]), .B(Op_MY[55]), .S0(n10681), .Y(n637) );
MX2X1TS U9996 ( .A(Data_MY[62]), .B(Op_MY[62]), .S0(n10681), .Y(n644) );
MX2X1TS U9997 ( .A(Data_MY[54]), .B(Op_MY[54]), .S0(n10681), .Y(n636) );
MX2X1TS U9998 ( .A(Data_MY[53]), .B(Op_MY[53]), .S0(n10681), .Y(n635) );
MX2X1TS U9999 ( .A(Data_MX[62]), .B(Op_MX[62]), .S0(n10681), .Y(n708) );
MX2X1TS U10000 ( .A(Data_MX[61]), .B(Op_MX[61]), .S0(n10681), .Y(n707) );
MX2X1TS U10001 ( .A(Data_MX[60]), .B(Op_MX[60]), .S0(n10681), .Y(n706) );
MX2X1TS U10002 ( .A(Data_MX[59]), .B(Op_MX[59]), .S0(n10681), .Y(n705) );
MX2X1TS U10003 ( .A(Data_MX[58]), .B(Op_MX[58]), .S0(n10553), .Y(n704) );
MX2X1TS U10004 ( .A(Data_MX[57]), .B(Op_MX[57]), .S0(n10681), .Y(n703) );
MX2X1TS U10005 ( .A(Data_MX[56]), .B(Op_MX[56]), .S0(n10682), .Y(n702) );
MX2X1TS U10006 ( .A(Data_MX[55]), .B(Op_MX[55]), .S0(n10682), .Y(n701) );
MX2X1TS U10007 ( .A(Data_MX[54]), .B(Op_MX[54]), .S0(n11006), .Y(n700) );
MX2X1TS U10008 ( .A(Data_MX[53]), .B(Op_MX[53]), .S0(n10681), .Y(n699) );
MX2X1TS U10009 ( .A(Data_MX[52]), .B(Op_MX[52]), .S0(n10682), .Y(n698) );
INVX2TS U10010 ( .A(n10687), .Y(n10689) );
INVX2TS U10011 ( .A(n10693), .Y(n10696) );
INVX2TS U10012 ( .A(n10694), .Y(n10695) );
INVX2TS U10013 ( .A(n10703), .Y(n10706) );
INVX2TS U10014 ( .A(n10704), .Y(n10705) );
INVX2TS U10015 ( .A(n10717), .Y(n10719) );
INVX2TS U10016 ( .A(n10723), .Y(n10726) );
INVX2TS U10017 ( .A(n10724), .Y(n10725) );
INVX2TS U10018 ( .A(n10737), .Y(n10739) );
INVX2TS U10019 ( .A(n10743), .Y(n10746) );
INVX2TS U10020 ( .A(n10744), .Y(n10745) );
NAND2X1TS U10021 ( .A(n1180), .B(n10749), .Y(n10750) );
INVX2TS U10022 ( .A(n10757), .Y(n10759) );
NAND2X1TS U10023 ( .A(n10759), .B(n10758), .Y(n10760) );
INVX2TS U10024 ( .A(n10763), .Y(n10766) );
INVX2TS U10025 ( .A(n10764), .Y(n10765) );
NAND2X1TS U10026 ( .A(n1181), .B(n10769), .Y(n10770) );
INVX2TS U10027 ( .A(n10777), .Y(n10779) );
NAND2X1TS U10028 ( .A(n10779), .B(n10778), .Y(n10780) );
INVX2TS U10029 ( .A(n10784), .Y(n10787) );
INVX2TS U10030 ( .A(n10785), .Y(n10786) );
NAND2X1TS U10031 ( .A(n1182), .B(n10790), .Y(n10791) );
NAND2X1TS U10032 ( .A(n10800), .B(n10799), .Y(n10801) );
NAND2X1TS U10033 ( .A(n1175), .B(n10807), .Y(n10808) );
NAND2X1TS U10034 ( .A(n10813), .B(n10812), .Y(n10814) );
NAND2X1TS U10035 ( .A(n11054), .B(n11205), .Y(n710) );
NOR2BX1TS U10036 ( .AN(exp_oper_result[11]), .B(n11205), .Y(S_Oper_A_exp[11]) );
NOR2X6TS U10037 ( .A(n10823), .B(n11056), .Y(n10825) );
MX2X1TS U10038 ( .A(Exp_module_Data_S[10]), .B(exp_oper_result[10]), .S0(
n10825), .Y(n407) );
MX2X1TS U10039 ( .A(Op_MX[62]), .B(exp_oper_result[10]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[10]) );
MX2X1TS U10040 ( .A(Exp_module_Data_S[9]), .B(exp_oper_result[9]), .S0(
n10825), .Y(n408) );
MX2X1TS U10041 ( .A(Op_MX[61]), .B(exp_oper_result[9]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[9]) );
MX2X1TS U10042 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(
n10825), .Y(n409) );
MX2X1TS U10043 ( .A(Op_MX[60]), .B(exp_oper_result[8]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[8]) );
MX2X1TS U10044 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(
n10825), .Y(n410) );
MX2X1TS U10045 ( .A(Op_MX[59]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
MX2X1TS U10046 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(
n10825), .Y(n411) );
MX2X1TS U10047 ( .A(Op_MX[58]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
MX2X1TS U10048 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(
n10825), .Y(n412) );
MX2X1TS U10049 ( .A(Op_MX[57]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
MX2X1TS U10050 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(
n10825), .Y(n413) );
MX2X1TS U10051 ( .A(Op_MX[56]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
MX2X1TS U10052 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(
n10825), .Y(n414) );
MX2X1TS U10053 ( .A(Op_MX[55]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U10054 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(
n10825), .Y(n415) );
MX2X1TS U10055 ( .A(Op_MX[54]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
MX2X1TS U10056 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(
n10825), .Y(n416) );
MX2X1TS U10057 ( .A(Op_MX[53]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
MX2X1TS U10058 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(
n10825), .Y(n417) );
MX2X1TS U10059 ( .A(Op_MX[52]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
MX2X1TS U10060 ( .A(Exp_module_Data_S[11]), .B(exp_oper_result[11]), .S0(
n10825), .Y(n406) );
XNOR2X1TS U10061 ( .A(DP_OP_36J35_134_7156_n1), .B(n11007), .Y(n10826) );
MX2X1TS U10062 ( .A(Exp_module_Overflow_flag_A), .B(n10826), .S0(n10897),
.Y(n405) );
NAND4XLTS U10063 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n10827) );
NAND4BXLTS U10064 ( .AN(n10827), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n10828) );
NAND4BXLTS U10065 ( .AN(n10828), .B(Exp_module_Data_S[9]), .C(
Exp_module_Data_S[8]), .D(Exp_module_Data_S[7]), .Y(n10829) );
NAND3BXLTS U10066 ( .AN(Exp_module_Data_S[10]), .B(n11056), .C(n10829), .Y(
n10830) );
OAI22X1TS U10067 ( .A0(Exp_module_Data_S[11]), .A1(n10830), .B0(n11056),
.B1(n11208), .Y(n352) );
INVX2TS U10068 ( .A(n10835), .Y(n10837) );
INVX3TS U10069 ( .A(n11060), .Y(n10922) );
AOI22X1TS U10070 ( .A0(Sgf_normalized_result[15]), .A1(n10922), .B0(
Add_result[16]), .B1(n10914), .Y(n10842) );
BUFX6TS U10071 ( .A(n10965), .Y(n10962) );
NAND2X1TS U10072 ( .A(n10962), .B(P_Sgf[68]), .Y(n10841) );
AO21XLTS U10073 ( .A0(n11005), .A1(Add_result[15]), .B0(n10843), .Y(n368) );
INVX2TS U10074 ( .A(n10845), .Y(n10846) );
AOI22X1TS U10075 ( .A0(Sgf_normalized_result[16]), .A1(n10922), .B0(
Add_result[17]), .B1(n10914), .Y(n10855) );
OAI2BB1X1TS U10076 ( .A0N(P_Sgf[69]), .A1N(n10962), .B0(n10855), .Y(n10856)
);
AOI21X1TS U10077 ( .A0(n10992), .A1(P_Sgf[68]), .B0(n10856), .Y(n10857) );
OAI2BB1X1TS U10078 ( .A0N(n11005), .A1N(Add_result[16]), .B0(n10857), .Y(
n369) );
AOI22X1TS U10079 ( .A0(Sgf_normalized_result[17]), .A1(n10922), .B0(
Add_result[18]), .B1(n10914), .Y(n10870) );
OAI2BB1X1TS U10080 ( .A0N(P_Sgf[70]), .A1N(n10962), .B0(n10870), .Y(n10871)
);
AOI21X1TS U10081 ( .A0(n10997), .A1(P_Sgf[69]), .B0(n10871), .Y(n10872) );
OAI2BB1X1TS U10082 ( .A0N(n10921), .A1N(Add_result[17]), .B0(n10872), .Y(
n370) );
INVX2TS U10083 ( .A(n10873), .Y(n10876) );
AOI22X1TS U10084 ( .A0(Sgf_normalized_result[18]), .A1(n10922), .B0(
Add_result[19]), .B1(n10914), .Y(n10884) );
OAI2BB1X1TS U10085 ( .A0N(P_Sgf[71]), .A1N(n10962), .B0(n10884), .Y(n10885)
);
AOI21X1TS U10086 ( .A0(n10997), .A1(P_Sgf[70]), .B0(n10885), .Y(n10886) );
OAI2BB1X1TS U10087 ( .A0N(n10921), .A1N(Add_result[18]), .B0(n10886), .Y(
n371) );
AOI22X1TS U10088 ( .A0(Sgf_normalized_result[19]), .A1(n10922), .B0(
Add_result[20]), .B1(n10914), .Y(n10891) );
OAI2BB1X1TS U10089 ( .A0N(P_Sgf[72]), .A1N(n10962), .B0(n10891), .Y(n10892)
);
AOI21X1TS U10090 ( .A0(n10992), .A1(P_Sgf[71]), .B0(n10892), .Y(n10893) );
OAI2BB1X1TS U10091 ( .A0N(n10921), .A1N(Add_result[19]), .B0(n10893), .Y(
n372) );
AOI22X1TS U10092 ( .A0(Sgf_normalized_result[20]), .A1(n10922), .B0(
Add_result[21]), .B1(n10914), .Y(n10899) );
OAI2BB1X1TS U10093 ( .A0N(P_Sgf[73]), .A1N(n10962), .B0(n10899), .Y(n10900)
);
AOI21X1TS U10094 ( .A0(n10992), .A1(P_Sgf[72]), .B0(n10900), .Y(n10901) );
OAI2BB1X1TS U10095 ( .A0N(n10947), .A1N(Add_result[20]), .B0(n10901), .Y(
n373) );
AOI22X1TS U10096 ( .A0(Sgf_normalized_result[21]), .A1(n10922), .B0(
Add_result[22]), .B1(n10914), .Y(n10902) );
OAI2BB1X1TS U10097 ( .A0N(P_Sgf[74]), .A1N(n10962), .B0(n10902), .Y(n10903)
);
AOI21X1TS U10098 ( .A0(n10992), .A1(P_Sgf[73]), .B0(n10903), .Y(n10904) );
OAI2BB1X1TS U10099 ( .A0N(n10921), .A1N(Add_result[21]), .B0(n10904), .Y(
n374) );
AOI22X1TS U10100 ( .A0(Sgf_normalized_result[22]), .A1(n10922), .B0(
Add_result[23]), .B1(n10914), .Y(n10905) );
OAI2BB1X1TS U10101 ( .A0N(P_Sgf[75]), .A1N(n10962), .B0(n10905), .Y(n10906)
);
AOI21X1TS U10102 ( .A0(n10992), .A1(P_Sgf[74]), .B0(n10906), .Y(n10907) );
OAI2BB1X1TS U10103 ( .A0N(n10947), .A1N(Add_result[22]), .B0(n10907), .Y(
n375) );
AOI22X1TS U10104 ( .A0(Sgf_normalized_result[23]), .A1(n10922), .B0(
Add_result[24]), .B1(n10914), .Y(n10908) );
OAI2BB1X1TS U10105 ( .A0N(P_Sgf[76]), .A1N(n10962), .B0(n10908), .Y(n10909)
);
AOI21X1TS U10106 ( .A0(n10992), .A1(P_Sgf[75]), .B0(n10909), .Y(n10910) );
OAI2BB1X1TS U10107 ( .A0N(n10947), .A1N(Add_result[23]), .B0(n10910), .Y(
n376) );
AOI22X1TS U10108 ( .A0(Sgf_normalized_result[24]), .A1(n10922), .B0(
Add_result[25]), .B1(n10914), .Y(n10911) );
OAI2BB1X1TS U10109 ( .A0N(P_Sgf[77]), .A1N(n10962), .B0(n10911), .Y(n10912)
);
AOI21X1TS U10110 ( .A0(n10992), .A1(P_Sgf[76]), .B0(n10912), .Y(n10913) );
OAI2BB1X1TS U10111 ( .A0N(n10947), .A1N(Add_result[24]), .B0(n10913), .Y(
n377) );
AOI22X1TS U10112 ( .A0(Sgf_normalized_result[25]), .A1(n10922), .B0(
Add_result[26]), .B1(n10914), .Y(n10915) );
OAI2BB1X1TS U10113 ( .A0N(P_Sgf[78]), .A1N(n10962), .B0(n10915), .Y(n10916)
);
AOI21X1TS U10114 ( .A0(n10992), .A1(P_Sgf[77]), .B0(n10916), .Y(n10917) );
OAI2BB1X1TS U10115 ( .A0N(n10947), .A1N(Add_result[25]), .B0(n10917), .Y(
n378) );
AOI22X1TS U10116 ( .A0(Sgf_normalized_result[26]), .A1(n10922), .B0(
Add_result[27]), .B1(n10994), .Y(n10918) );
OAI2BB1X1TS U10117 ( .A0N(P_Sgf[79]), .A1N(n10962), .B0(n10918), .Y(n10919)
);
AOI21X1TS U10118 ( .A0(n10992), .A1(P_Sgf[78]), .B0(n10919), .Y(n10920) );
OAI2BB1X1TS U10119 ( .A0N(n10947), .A1N(Add_result[26]), .B0(n10920), .Y(
n379) );
AOI22X1TS U10120 ( .A0(Sgf_normalized_result[27]), .A1(n10922), .B0(
Add_result[28]), .B1(n10994), .Y(n10923) );
OAI2BB1X1TS U10121 ( .A0N(P_Sgf[80]), .A1N(n10962), .B0(n10923), .Y(n10924)
);
AOI21X1TS U10122 ( .A0(n10992), .A1(P_Sgf[79]), .B0(n10924), .Y(n10925) );
OAI2BB1X1TS U10123 ( .A0N(n10947), .A1N(Add_result[27]), .B0(n10925), .Y(
n380) );
AOI22X1TS U10124 ( .A0(Sgf_normalized_result[28]), .A1(n10960), .B0(
Add_result[29]), .B1(n10994), .Y(n10926) );
OAI2BB1X1TS U10125 ( .A0N(P_Sgf[81]), .A1N(n10962), .B0(n10926), .Y(n10927)
);
AOI21X1TS U10126 ( .A0(n10992), .A1(P_Sgf[80]), .B0(n10927), .Y(n10928) );
OAI2BB1X1TS U10127 ( .A0N(n10947), .A1N(Add_result[28]), .B0(n10928), .Y(
n381) );
AOI22X1TS U10128 ( .A0(Sgf_normalized_result[29]), .A1(n10960), .B0(
Add_result[30]), .B1(n10994), .Y(n10929) );
OAI2BB1X1TS U10129 ( .A0N(P_Sgf[82]), .A1N(n10962), .B0(n10929), .Y(n10930)
);
AOI21X1TS U10130 ( .A0(n10992), .A1(P_Sgf[81]), .B0(n10930), .Y(n10931) );
OAI2BB1X1TS U10131 ( .A0N(n10947), .A1N(Add_result[29]), .B0(n10931), .Y(
n382) );
AOI22X1TS U10132 ( .A0(Sgf_normalized_result[30]), .A1(n10960), .B0(
Add_result[31]), .B1(n10994), .Y(n10932) );
OAI2BB1X1TS U10133 ( .A0N(P_Sgf[83]), .A1N(n10962), .B0(n10932), .Y(n10933)
);
AOI21X1TS U10134 ( .A0(n10992), .A1(P_Sgf[82]), .B0(n10933), .Y(n10934) );
OAI2BB1X1TS U10135 ( .A0N(n10947), .A1N(Add_result[30]), .B0(n10934), .Y(
n383) );
AOI22X1TS U10136 ( .A0(Sgf_normalized_result[31]), .A1(n10960), .B0(
Add_result[32]), .B1(n10994), .Y(n10935) );
OAI2BB1X1TS U10137 ( .A0N(P_Sgf[84]), .A1N(n10962), .B0(n10935), .Y(n10936)
);
AOI21X1TS U10138 ( .A0(n10992), .A1(P_Sgf[83]), .B0(n10936), .Y(n10937) );
OAI2BB1X1TS U10139 ( .A0N(n10947), .A1N(Add_result[31]), .B0(n10937), .Y(
n384) );
AOI22X1TS U10140 ( .A0(Sgf_normalized_result[32]), .A1(n10960), .B0(
Add_result[33]), .B1(n10994), .Y(n10938) );
OAI2BB1X1TS U10141 ( .A0N(P_Sgf[85]), .A1N(n10962), .B0(n10938), .Y(n10939)
);
AOI21X1TS U10142 ( .A0(n10992), .A1(P_Sgf[84]), .B0(n10939), .Y(n10940) );
OAI2BB1X1TS U10143 ( .A0N(n10947), .A1N(Add_result[32]), .B0(n10940), .Y(
n385) );
AOI22X1TS U10144 ( .A0(Sgf_normalized_result[33]), .A1(n10960), .B0(
Add_result[34]), .B1(n10994), .Y(n10941) );
OAI2BB1X1TS U10145 ( .A0N(P_Sgf[86]), .A1N(n10962), .B0(n10941), .Y(n10942)
);
AOI21X1TS U10146 ( .A0(n10992), .A1(P_Sgf[85]), .B0(n10942), .Y(n10943) );
OAI2BB1X1TS U10147 ( .A0N(n10947), .A1N(Add_result[33]), .B0(n10943), .Y(
n386) );
AOI22X1TS U10148 ( .A0(Sgf_normalized_result[34]), .A1(n10960), .B0(
Add_result[35]), .B1(n10994), .Y(n10944) );
OAI2BB1X1TS U10149 ( .A0N(P_Sgf[87]), .A1N(n10962), .B0(n10944), .Y(n10945)
);
AOI21X1TS U10150 ( .A0(n10992), .A1(P_Sgf[86]), .B0(n10945), .Y(n10946) );
OAI2BB1X1TS U10151 ( .A0N(n10947), .A1N(Add_result[34]), .B0(n10946), .Y(
n387) );
AOI22X1TS U10152 ( .A0(Sgf_normalized_result[35]), .A1(n10960), .B0(
Add_result[36]), .B1(n10994), .Y(n10948) );
OAI2BB1X1TS U10153 ( .A0N(P_Sgf[88]), .A1N(n10962), .B0(n10948), .Y(n10949)
);
AOI21X1TS U10154 ( .A0(n10992), .A1(P_Sgf[87]), .B0(n10949), .Y(n10950) );
OAI2BB1X1TS U10155 ( .A0N(n10921), .A1N(Add_result[35]), .B0(n10950), .Y(
n388) );
AOI22X1TS U10156 ( .A0(Sgf_normalized_result[36]), .A1(n10960), .B0(
Add_result[37]), .B1(n10994), .Y(n10951) );
OAI2BB1X1TS U10157 ( .A0N(P_Sgf[89]), .A1N(n10962), .B0(n10951), .Y(n10952)
);
AOI21X1TS U10158 ( .A0(n10992), .A1(P_Sgf[88]), .B0(n10952), .Y(n10953) );
OAI2BB1X1TS U10159 ( .A0N(n10921), .A1N(Add_result[36]), .B0(n10953), .Y(
n389) );
AOI22X1TS U10160 ( .A0(Sgf_normalized_result[37]), .A1(n10960), .B0(
Add_result[38]), .B1(n10994), .Y(n10954) );
OAI2BB1X1TS U10161 ( .A0N(P_Sgf[90]), .A1N(n10962), .B0(n10954), .Y(n10955)
);
AOI21X1TS U10162 ( .A0(n10997), .A1(P_Sgf[89]), .B0(n10955), .Y(n10956) );
OAI2BB1X1TS U10163 ( .A0N(n10947), .A1N(Add_result[37]), .B0(n10956), .Y(
n390) );
AOI22X1TS U10164 ( .A0(Sgf_normalized_result[38]), .A1(n10960), .B0(
Add_result[39]), .B1(n10994), .Y(n10957) );
OAI2BB1X1TS U10165 ( .A0N(P_Sgf[91]), .A1N(n10962), .B0(n10957), .Y(n10958)
);
AOI21X1TS U10166 ( .A0(n10992), .A1(P_Sgf[90]), .B0(n10958), .Y(n10959) );
OAI2BB1X1TS U10167 ( .A0N(n10921), .A1N(Add_result[38]), .B0(n10959), .Y(
n391) );
AOI22X1TS U10168 ( .A0(Sgf_normalized_result[39]), .A1(n10960), .B0(
Add_result[40]), .B1(n10994), .Y(n10961) );
OAI2BB1X1TS U10169 ( .A0N(P_Sgf[92]), .A1N(n10962), .B0(n10961), .Y(n10963)
);
AOI21X1TS U10170 ( .A0(n10997), .A1(P_Sgf[91]), .B0(n10963), .Y(n10964) );
OAI2BB1X1TS U10171 ( .A0N(n10921), .A1N(Add_result[39]), .B0(n10964), .Y(
n392) );
AOI22X1TS U10172 ( .A0(Sgf_normalized_result[40]), .A1(n11000), .B0(
Add_result[41]), .B1(n10994), .Y(n10966) );
OAI2BB1X1TS U10173 ( .A0N(P_Sgf[93]), .A1N(n10965), .B0(n10966), .Y(n10967)
);
AOI21X1TS U10174 ( .A0(n10992), .A1(P_Sgf[92]), .B0(n10967), .Y(n10968) );
OAI2BB1X1TS U10175 ( .A0N(n10502), .A1N(Add_result[40]), .B0(n10968), .Y(
n393) );
AOI22X1TS U10176 ( .A0(Sgf_normalized_result[41]), .A1(n11000), .B0(
Add_result[42]), .B1(n10994), .Y(n10969) );
OAI2BB1X1TS U10177 ( .A0N(P_Sgf[94]), .A1N(n10965), .B0(n10969), .Y(n10970)
);
AOI21X1TS U10178 ( .A0(n10997), .A1(P_Sgf[93]), .B0(n10970), .Y(n10971) );
OAI2BB1X1TS U10179 ( .A0N(n10921), .A1N(Add_result[41]), .B0(n10971), .Y(
n394) );
AOI22X1TS U10180 ( .A0(Sgf_normalized_result[42]), .A1(n11000), .B0(n873),
.B1(n10914), .Y(n10972) );
OAI2BB1X1TS U10181 ( .A0N(P_Sgf[95]), .A1N(n10965), .B0(n10972), .Y(n10973)
);
AOI21X1TS U10182 ( .A0(n10992), .A1(P_Sgf[94]), .B0(n10973), .Y(n10974) );
OAI2BB1X1TS U10183 ( .A0N(n10502), .A1N(Add_result[42]), .B0(n10974), .Y(
n395) );
AOI22X1TS U10184 ( .A0(Sgf_normalized_result[43]), .A1(n11000), .B0(n870),
.B1(n10994), .Y(n10975) );
OAI2BB1X1TS U10185 ( .A0N(P_Sgf[96]), .A1N(n10965), .B0(n10975), .Y(n10976)
);
AOI21X1TS U10186 ( .A0(n10997), .A1(P_Sgf[95]), .B0(n10976), .Y(n10977) );
OAI2BB1X1TS U10187 ( .A0N(n10921), .A1N(n873), .B0(n10977), .Y(n396) );
AOI22X1TS U10188 ( .A0(Sgf_normalized_result[44]), .A1(n11000), .B0(n874),
.B1(n10914), .Y(n10978) );
OAI2BB1X1TS U10189 ( .A0N(P_Sgf[97]), .A1N(n10965), .B0(n10978), .Y(n10979)
);
AOI21X1TS U10190 ( .A0(n10992), .A1(P_Sgf[96]), .B0(n10979), .Y(n10980) );
OAI2BB1X1TS U10191 ( .A0N(n10502), .A1N(n870), .B0(n10980), .Y(n397) );
AOI22X1TS U10192 ( .A0(Sgf_normalized_result[45]), .A1(n11000), .B0(
Add_result[46]), .B1(n10994), .Y(n10981) );
OAI2BB1X1TS U10193 ( .A0N(P_Sgf[98]), .A1N(n10965), .B0(n10981), .Y(n10982)
);
AOI21X1TS U10194 ( .A0(n10997), .A1(P_Sgf[97]), .B0(n10982), .Y(n10983) );
OAI2BB1X1TS U10195 ( .A0N(n10921), .A1N(n874), .B0(n10983), .Y(n398) );
AOI22X1TS U10196 ( .A0(Sgf_normalized_result[46]), .A1(n11000), .B0(n875),
.B1(n10914), .Y(n10984) );
OAI2BB1X1TS U10197 ( .A0N(P_Sgf[99]), .A1N(n10965), .B0(n10984), .Y(n10985)
);
AOI21X1TS U10198 ( .A0(n10992), .A1(P_Sgf[98]), .B0(n10985), .Y(n10986) );
OAI2BB1X1TS U10199 ( .A0N(n10502), .A1N(Add_result[46]), .B0(n10986), .Y(
n399) );
AOI22X1TS U10200 ( .A0(Sgf_normalized_result[47]), .A1(n11000), .B0(n871),
.B1(n10994), .Y(n10987) );
OAI2BB1X1TS U10201 ( .A0N(P_Sgf[100]), .A1N(n10965), .B0(n10987), .Y(n10988)
);
AOI21X1TS U10202 ( .A0(n10997), .A1(P_Sgf[99]), .B0(n10988), .Y(n10989) );
OAI2BB1X1TS U10203 ( .A0N(n11005), .A1N(n875), .B0(n10989), .Y(n400) );
AOI22X1TS U10204 ( .A0(Sgf_normalized_result[48]), .A1(n11000), .B0(n876),
.B1(n10914), .Y(n10990) );
OAI2BB1X1TS U10205 ( .A0N(P_Sgf[101]), .A1N(n10965), .B0(n10990), .Y(n10991)
);
AOI21X1TS U10206 ( .A0(n10992), .A1(P_Sgf[100]), .B0(n10991), .Y(n10993) );
OAI2BB1X1TS U10207 ( .A0N(n11005), .A1N(n871), .B0(n10993), .Y(n401) );
AOI22X1TS U10208 ( .A0(Sgf_normalized_result[49]), .A1(n11000), .B0(n872),
.B1(n10994), .Y(n10995) );
OAI2BB1X1TS U10209 ( .A0N(P_Sgf[102]), .A1N(n10965), .B0(n10995), .Y(n10996)
);
AOI21X1TS U10210 ( .A0(n10997), .A1(P_Sgf[101]), .B0(n10996), .Y(n10998) );
OAI2BB1X1TS U10211 ( .A0N(n11005), .A1N(n876), .B0(n10998), .Y(n402) );
AOI22X1TS U10212 ( .A0(Sgf_normalized_result[50]), .A1(n11000), .B0(
Add_result[51]), .B1(n10914), .Y(n11001) );
OAI2BB1X1TS U10213 ( .A0N(P_Sgf[103]), .A1N(n10965), .B0(n11001), .Y(n11002)
);
AOI21X1TS U10214 ( .A0(n11003), .A1(P_Sgf[102]), .B0(n11002), .Y(n11004) );
OAI2BB1X1TS U10215 ( .A0N(n11005), .A1N(n872), .B0(n11004), .Y(n403) );
AO22XLTS U10216 ( .A0(n9512), .A1(Data_MY[63]), .B0(n11006), .B1(Op_MY[63]),
.Y(n715) );
OAI22X1TS U10217 ( .A0(n11007), .A1(zero_flag), .B0(P_Sgf[105]), .B1(n11011),
.Y(n11008) );
AOI2BB1XLTS U10218 ( .A0N(n11009), .A1N(n11008), .B0(n11010), .Y(n713) );
AOI21X1TS U10219 ( .A0(FS_Module_state_reg[2]), .A1(n11010), .B0(n10450),
.Y(n11013) );
NAND3XLTS U10220 ( .A(n11013), .B(n11012), .C(n11011), .Y(n711) );
NOR4X1TS U10221 ( .A(Op_MY[60]), .B(Op_MY[59]), .C(Op_MY[58]), .D(Op_MY[57]),
.Y(n11015) );
NOR4X1TS U10222 ( .A(Op_MY[56]), .B(Op_MY[55]), .C(Op_MY[62]), .D(Op_MY[54]),
.Y(n11014) );
NOR4X1TS U10223 ( .A(Op_MY[11]), .B(Op_MY[10]), .C(Op_MY[9]), .D(Op_MY[8]),
.Y(n11020) );
NOR4X1TS U10224 ( .A(Op_MY[12]), .B(Op_MY[2]), .C(Op_MY[1]), .D(Op_MY[0]),
.Y(n11019) );
NOR4X1TS U10225 ( .A(Op_MY[6]), .B(Op_MY[5]), .C(Op_MY[4]), .D(Op_MY[3]),
.Y(n11018) );
NAND4XLTS U10226 ( .A(n11021), .B(n11020), .C(n11019), .D(n11018), .Y(n11032) );
NAND4XLTS U10227 ( .A(n11029), .B(n11028), .C(n11027), .D(n11026), .Y(n11030) );
OR4X2TS U10228 ( .A(n11033), .B(n11032), .C(n11031), .D(n11030), .Y(n11057)
);
NAND4XLTS U10229 ( .A(n11041), .B(n11040), .C(n11039), .D(n11038), .Y(n11052) );
NAND4XLTS U10230 ( .A(n11045), .B(n11044), .C(n11043), .D(n11042), .Y(n11051) );
NOR4X1TS U10231 ( .A(Op_MX[57]), .B(Op_MX[56]), .C(Op_MX[55]), .D(Op_MX[54]),
.Y(n11049) );
NAND4XLTS U10232 ( .A(n11049), .B(n11048), .C(n11047), .D(n11046), .Y(n11050) );
OR4X2TS U10233 ( .A(n11053), .B(n11052), .C(n11051), .D(n11050), .Y(n11055)
);
AOI32X1TS U10234 ( .A0(n11057), .A1(n11056), .A2(n11055), .B0(n11223), .B1(
n11054), .Y(n581) );
AO22XLTS U10235 ( .A0(n11141), .A1(Sgf_normalized_result[0]), .B0(n11156),
.B1(Add_result[0]), .Y(n579) );
AO22XLTS U10236 ( .A0(n11141), .A1(Sgf_normalized_result[1]), .B0(n11139),
.B1(Add_result[1]), .Y(n578) );
CLKINVX6TS U10237 ( .A(n11158), .Y(n11160) );
CLKINVX6TS U10238 ( .A(n11158), .Y(n11162) );
AOI2BB2XLTS U10239 ( .B0(n11160), .B1(Sgf_normalized_result[2]), .A0N(
Add_result[2]), .A1N(n11162), .Y(n577) );
NAND2X1TS U10240 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]), .Y(n11062) );
OAI2BB1X1TS U10241 ( .A0N(Add_result[3]), .A1N(n11156), .B0(n11063), .Y(n576) );
AOI31XLTS U10242 ( .A0(Sgf_normalized_result[3]), .A1(
Sgf_normalized_result[4]), .A2(Sgf_normalized_result[2]), .B0(n11065),
.Y(n11064) );
AOI2BB2XLTS U10243 ( .B0(n11160), .B1(n11064), .A0N(Add_result[4]), .A1N(
n11160), .Y(n575) );
OAI21XLTS U10244 ( .A0(n11065), .A1(n11178), .B0(n11067), .Y(n11066) );
OAI211XLTS U10245 ( .A0(Sgf_normalized_result[6]), .A1(n11067), .B0(n11162),
.C0(n11070), .Y(n11068) );
OAI2BB1X1TS U10246 ( .A0N(Add_result[6]), .A1N(n11069), .B0(n11068), .Y(n573) );
AOI21X1TS U10247 ( .A0(n11179), .A1(n11070), .B0(n11072), .Y(n11071) );
OAI2BB1X1TS U10248 ( .A0N(Add_result[8]), .A1N(n11156), .B0(n11073), .Y(n571) );
AOI21X1TS U10249 ( .A0(n11180), .A1(n11074), .B0(n11076), .Y(n11075) );
OAI211XLTS U10250 ( .A0(Sgf_normalized_result[10]), .A1(n11076), .B0(n11162),
.C0(n11078), .Y(n11077) );
OAI2BB1X1TS U10251 ( .A0N(Add_result[10]), .A1N(n11156), .B0(n11077), .Y(
n569) );
AOI21X1TS U10252 ( .A0(n11181), .A1(n11078), .B0(n11080), .Y(n11079) );
OAI211XLTS U10253 ( .A0(Sgf_normalized_result[12]), .A1(n11080), .B0(n11162),
.C0(n11082), .Y(n11081) );
OAI2BB1X1TS U10254 ( .A0N(Add_result[12]), .A1N(n11156), .B0(n11081), .Y(
n567) );
AOI21X1TS U10255 ( .A0(n11182), .A1(n11082), .B0(n11084), .Y(n11083) );
OAI211XLTS U10256 ( .A0(Sgf_normalized_result[14]), .A1(n11084), .B0(n11162),
.C0(n11086), .Y(n11085) );
OAI2BB1X1TS U10257 ( .A0N(Add_result[14]), .A1N(n11156), .B0(n11085), .Y(
n565) );
AOI21X1TS U10258 ( .A0(n11183), .A1(n11086), .B0(n11088), .Y(n11087) );
OAI211XLTS U10259 ( .A0(Sgf_normalized_result[16]), .A1(n11088), .B0(n11160),
.C0(n11090), .Y(n11089) );
OAI2BB1X1TS U10260 ( .A0N(Add_result[16]), .A1N(n11156), .B0(n11089), .Y(
n563) );
AOI21X1TS U10261 ( .A0(n11184), .A1(n11090), .B0(n11092), .Y(n11091) );
OAI211XLTS U10262 ( .A0(Sgf_normalized_result[18]), .A1(n11092), .B0(n11160),
.C0(n11094), .Y(n11093) );
OAI2BB1X1TS U10263 ( .A0N(Add_result[18]), .A1N(n11156), .B0(n11093), .Y(
n561) );
AOI21X1TS U10264 ( .A0(n11185), .A1(n11094), .B0(n11096), .Y(n11095) );
OAI211XLTS U10265 ( .A0(Sgf_normalized_result[20]), .A1(n11096), .B0(n11160),
.C0(n11098), .Y(n11097) );
OAI2BB1X1TS U10266 ( .A0N(Add_result[20]), .A1N(n11156), .B0(n11097), .Y(
n559) );
AOI21X1TS U10267 ( .A0(n11186), .A1(n11098), .B0(n11100), .Y(n11099) );
OAI2BB1X1TS U10268 ( .A0N(Add_result[22]), .A1N(n11139), .B0(n11101), .Y(
n557) );
AOI21X1TS U10269 ( .A0(n11187), .A1(n11102), .B0(n11104), .Y(n11103) );
OAI211XLTS U10270 ( .A0(Sgf_normalized_result[24]), .A1(n11104), .B0(n11160),
.C0(n11106), .Y(n11105) );
OAI2BB1X1TS U10271 ( .A0N(Add_result[24]), .A1N(n11139), .B0(n11105), .Y(
n555) );
AOI21X1TS U10272 ( .A0(n11188), .A1(n11106), .B0(n11108), .Y(n11107) );
OAI211XLTS U10273 ( .A0(Sgf_normalized_result[26]), .A1(n11108), .B0(n11160),
.C0(n11110), .Y(n11109) );
OAI2BB1X1TS U10274 ( .A0N(Add_result[26]), .A1N(n11158), .B0(n11109), .Y(
n553) );
AOI21X1TS U10275 ( .A0(n11189), .A1(n11110), .B0(n11112), .Y(n11111) );
OAI211XLTS U10276 ( .A0(Sgf_normalized_result[28]), .A1(n11112), .B0(n11160),
.C0(n11114), .Y(n11113) );
OAI2BB1X1TS U10277 ( .A0N(Add_result[28]), .A1N(n11158), .B0(n11113), .Y(
n551) );
AOI21X1TS U10278 ( .A0(n11190), .A1(n11114), .B0(n11116), .Y(n11115) );
OAI211XLTS U10279 ( .A0(Sgf_normalized_result[30]), .A1(n11116), .B0(n11160),
.C0(n11118), .Y(n11117) );
OAI2BB1X1TS U10280 ( .A0N(Add_result[30]), .A1N(n11139), .B0(n11117), .Y(
n549) );
AOI21X1TS U10281 ( .A0(n11191), .A1(n11118), .B0(n11120), .Y(n11119) );
OAI211XLTS U10282 ( .A0(Sgf_normalized_result[32]), .A1(n11120), .B0(n11160),
.C0(n11122), .Y(n11121) );
OAI2BB1X1TS U10283 ( .A0N(Add_result[32]), .A1N(n11139), .B0(n11121), .Y(
n547) );
AOI21X1TS U10284 ( .A0(n11192), .A1(n11122), .B0(n11124), .Y(n11123) );
OAI211XLTS U10285 ( .A0(Sgf_normalized_result[34]), .A1(n11124), .B0(n11160),
.C0(n11126), .Y(n11125) );
OAI2BB1X1TS U10286 ( .A0N(Add_result[34]), .A1N(n11139), .B0(n11125), .Y(
n545) );
AOI21X1TS U10287 ( .A0(n11193), .A1(n11126), .B0(n11128), .Y(n11127) );
OAI2BB1X1TS U10288 ( .A0N(Add_result[36]), .A1N(n11139), .B0(n11129), .Y(
n543) );
AOI21X1TS U10289 ( .A0(n11194), .A1(n11130), .B0(n11132), .Y(n11131) );
OAI2BB1X1TS U10290 ( .A0N(Add_result[38]), .A1N(n11139), .B0(n11133), .Y(
n541) );
AOI21X1TS U10291 ( .A0(n11195), .A1(n11134), .B0(n11136), .Y(n11135) );
OAI2BB1X1TS U10292 ( .A0N(Add_result[40]), .A1N(n11069), .B0(n11137), .Y(
n539) );
AOI21X1TS U10293 ( .A0(n11197), .A1(n11138), .B0(n11142), .Y(n11140) );
OAI2BB1X1TS U10294 ( .A0N(Add_result[42]), .A1N(n11156), .B0(n11143), .Y(
n537) );
AOI21X1TS U10295 ( .A0(n11200), .A1(n11144), .B0(n11146), .Y(n11145) );
OAI2BB1X1TS U10296 ( .A0N(n870), .A1N(n11156), .B0(n11147), .Y(n535) );
AOI21X1TS U10297 ( .A0(n11201), .A1(n11148), .B0(n11150), .Y(n11149) );
OAI2BB1X1TS U10298 ( .A0N(Add_result[46]), .A1N(n11156), .B0(n11151), .Y(
n533) );
AOI21X1TS U10299 ( .A0(n11202), .A1(n11152), .B0(n11154), .Y(n11153) );
OAI2BB1X1TS U10300 ( .A0N(n871), .A1N(n11156), .B0(n11155), .Y(n531) );
AOI21X1TS U10301 ( .A0(n11203), .A1(n11157), .B0(n11163), .Y(n11159) );
OAI2BB1X1TS U10302 ( .A0N(n872), .A1N(n11069), .B0(n11164), .Y(n529) );
INVX3TS U10303 ( .A(n11171), .Y(n11166) );
AO22XLTS U10304 ( .A0(Sgf_normalized_result[0]), .A1(n11166), .B0(
final_result_ieee[0]), .B1(n11169), .Y(n351) );
AO22XLTS U10305 ( .A0(Sgf_normalized_result[1]), .A1(n11166), .B0(
final_result_ieee[1]), .B1(n11165), .Y(n350) );
AO22XLTS U10306 ( .A0(Sgf_normalized_result[2]), .A1(n11166), .B0(
final_result_ieee[2]), .B1(n11168), .Y(n349) );
AO22XLTS U10307 ( .A0(Sgf_normalized_result[3]), .A1(n11166), .B0(
final_result_ieee[3]), .B1(n11168), .Y(n348) );
AO22XLTS U10308 ( .A0(Sgf_normalized_result[4]), .A1(n11166), .B0(
final_result_ieee[4]), .B1(n11165), .Y(n347) );
AO22XLTS U10309 ( .A0(Sgf_normalized_result[5]), .A1(n11166), .B0(
final_result_ieee[5]), .B1(n11165), .Y(n346) );
AO22XLTS U10310 ( .A0(Sgf_normalized_result[6]), .A1(n11166), .B0(
final_result_ieee[6]), .B1(n11168), .Y(n345) );
AO22XLTS U10311 ( .A0(Sgf_normalized_result[7]), .A1(n11166), .B0(
final_result_ieee[7]), .B1(n11165), .Y(n344) );
AO22XLTS U10312 ( .A0(Sgf_normalized_result[8]), .A1(n11166), .B0(
final_result_ieee[8]), .B1(n11168), .Y(n343) );
AO22XLTS U10313 ( .A0(Sgf_normalized_result[9]), .A1(n11166), .B0(
final_result_ieee[9]), .B1(n11165), .Y(n342) );
AO22XLTS U10314 ( .A0(Sgf_normalized_result[10]), .A1(n11166), .B0(
final_result_ieee[10]), .B1(n11168), .Y(n341) );
AO22XLTS U10315 ( .A0(Sgf_normalized_result[11]), .A1(n11166), .B0(
final_result_ieee[11]), .B1(n11165), .Y(n340) );
AO22XLTS U10316 ( .A0(Sgf_normalized_result[12]), .A1(n11166), .B0(
final_result_ieee[12]), .B1(n11168), .Y(n339) );
CLKINVX6TS U10317 ( .A(n11171), .Y(n11167) );
AO22XLTS U10318 ( .A0(Sgf_normalized_result[13]), .A1(n11167), .B0(
final_result_ieee[13]), .B1(n11165), .Y(n338) );
AO22XLTS U10319 ( .A0(Sgf_normalized_result[14]), .A1(n11167), .B0(
final_result_ieee[14]), .B1(n11168), .Y(n337) );
AO22XLTS U10320 ( .A0(Sgf_normalized_result[15]), .A1(n11167), .B0(
final_result_ieee[15]), .B1(n11165), .Y(n336) );
AO22XLTS U10321 ( .A0(Sgf_normalized_result[16]), .A1(n11167), .B0(
final_result_ieee[16]), .B1(n11168), .Y(n335) );
AO22XLTS U10322 ( .A0(Sgf_normalized_result[17]), .A1(n11167), .B0(
final_result_ieee[17]), .B1(n11165), .Y(n334) );
AO22XLTS U10323 ( .A0(Sgf_normalized_result[18]), .A1(n11167), .B0(
final_result_ieee[18]), .B1(n11168), .Y(n333) );
AO22XLTS U10324 ( .A0(Sgf_normalized_result[19]), .A1(n11167), .B0(
final_result_ieee[19]), .B1(n11165), .Y(n332) );
AO22XLTS U10325 ( .A0(Sgf_normalized_result[20]), .A1(n11167), .B0(
final_result_ieee[20]), .B1(n11168), .Y(n331) );
AO22XLTS U10326 ( .A0(Sgf_normalized_result[21]), .A1(n11167), .B0(
final_result_ieee[21]), .B1(n11165), .Y(n330) );
AO22XLTS U10327 ( .A0(Sgf_normalized_result[22]), .A1(n11167), .B0(
final_result_ieee[22]), .B1(n11165), .Y(n329) );
AO22XLTS U10328 ( .A0(Sgf_normalized_result[23]), .A1(n11167), .B0(
final_result_ieee[23]), .B1(n11165), .Y(n328) );
AO22XLTS U10329 ( .A0(Sgf_normalized_result[24]), .A1(n11167), .B0(
final_result_ieee[24]), .B1(n11168), .Y(n327) );
AO22XLTS U10330 ( .A0(Sgf_normalized_result[25]), .A1(n11167), .B0(
final_result_ieee[25]), .B1(n11165), .Y(n326) );
CLKINVX6TS U10331 ( .A(n11171), .Y(n11170) );
AO22XLTS U10332 ( .A0(Sgf_normalized_result[26]), .A1(n11170), .B0(
final_result_ieee[26]), .B1(n11169), .Y(n325) );
AO22XLTS U10333 ( .A0(Sgf_normalized_result[27]), .A1(n11167), .B0(
final_result_ieee[27]), .B1(n11168), .Y(n324) );
AO22XLTS U10334 ( .A0(Sgf_normalized_result[28]), .A1(n11170), .B0(
final_result_ieee[28]), .B1(n11168), .Y(n323) );
AO22XLTS U10335 ( .A0(Sgf_normalized_result[29]), .A1(n11167), .B0(
final_result_ieee[29]), .B1(n11168), .Y(n322) );
AO22XLTS U10336 ( .A0(Sgf_normalized_result[30]), .A1(n11170), .B0(
final_result_ieee[30]), .B1(n11168), .Y(n321) );
AO22XLTS U10337 ( .A0(Sgf_normalized_result[31]), .A1(n11167), .B0(
final_result_ieee[31]), .B1(n11168), .Y(n320) );
AO22XLTS U10338 ( .A0(Sgf_normalized_result[32]), .A1(n11170), .B0(
final_result_ieee[32]), .B1(n11168), .Y(n319) );
AO22XLTS U10339 ( .A0(Sgf_normalized_result[33]), .A1(n11167), .B0(
final_result_ieee[33]), .B1(n11168), .Y(n318) );
AO22XLTS U10340 ( .A0(Sgf_normalized_result[34]), .A1(n11170), .B0(
final_result_ieee[34]), .B1(n11168), .Y(n317) );
AO22XLTS U10341 ( .A0(Sgf_normalized_result[35]), .A1(n11167), .B0(
final_result_ieee[35]), .B1(n11168), .Y(n316) );
AO22XLTS U10342 ( .A0(Sgf_normalized_result[36]), .A1(n11170), .B0(
final_result_ieee[36]), .B1(n11168), .Y(n315) );
AO22XLTS U10343 ( .A0(Sgf_normalized_result[37]), .A1(n11167), .B0(
final_result_ieee[37]), .B1(n11168), .Y(n314) );
AO22XLTS U10344 ( .A0(Sgf_normalized_result[38]), .A1(n11170), .B0(
final_result_ieee[38]), .B1(n11168), .Y(n313) );
AO22XLTS U10345 ( .A0(Sgf_normalized_result[39]), .A1(n11170), .B0(
final_result_ieee[39]), .B1(n11168), .Y(n312) );
AO22XLTS U10346 ( .A0(Sgf_normalized_result[40]), .A1(n11170), .B0(
final_result_ieee[40]), .B1(n11168), .Y(n311) );
AO22XLTS U10347 ( .A0(Sgf_normalized_result[41]), .A1(n11170), .B0(
final_result_ieee[41]), .B1(n11169), .Y(n310) );
AO22XLTS U10348 ( .A0(Sgf_normalized_result[42]), .A1(n11170), .B0(
final_result_ieee[42]), .B1(n11169), .Y(n309) );
AO22XLTS U10349 ( .A0(Sgf_normalized_result[43]), .A1(n11170), .B0(
final_result_ieee[43]), .B1(n11169), .Y(n308) );
AO22XLTS U10350 ( .A0(Sgf_normalized_result[44]), .A1(n11170), .B0(
final_result_ieee[44]), .B1(n11169), .Y(n307) );
AO22XLTS U10351 ( .A0(Sgf_normalized_result[45]), .A1(n11170), .B0(
final_result_ieee[45]), .B1(n11169), .Y(n306) );
AO22XLTS U10352 ( .A0(Sgf_normalized_result[46]), .A1(n11170), .B0(
final_result_ieee[46]), .B1(n11169), .Y(n305) );
AO22XLTS U10353 ( .A0(Sgf_normalized_result[47]), .A1(n11170), .B0(
final_result_ieee[47]), .B1(n11169), .Y(n304) );
AO22XLTS U10354 ( .A0(Sgf_normalized_result[48]), .A1(n11170), .B0(
final_result_ieee[48]), .B1(n11169), .Y(n303) );
AO22XLTS U10355 ( .A0(Sgf_normalized_result[49]), .A1(n11170), .B0(
final_result_ieee[49]), .B1(n11169), .Y(n302) );
AO22XLTS U10356 ( .A0(Sgf_normalized_result[50]), .A1(n11170), .B0(
final_result_ieee[50]), .B1(n11169), .Y(n301) );
AO22XLTS U10357 ( .A0(Sgf_normalized_result[51]), .A1(n11170), .B0(
final_result_ieee[51]), .B1(n11169), .Y(n300) );
OA22X1TS U10358 ( .A0(n11172), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n11171), .Y(n299) );
OA22X1TS U10359 ( .A0(n11172), .A1(final_result_ieee[53]), .B0(
exp_oper_result[1]), .B1(n11171), .Y(n298) );
OA22X1TS U10360 ( .A0(n11172), .A1(final_result_ieee[54]), .B0(
exp_oper_result[2]), .B1(n11171), .Y(n297) );
OA22X1TS U10361 ( .A0(n11172), .A1(final_result_ieee[55]), .B0(
exp_oper_result[3]), .B1(n11171), .Y(n296) );
OA22X1TS U10362 ( .A0(n11172), .A1(final_result_ieee[56]), .B0(
exp_oper_result[4]), .B1(n11171), .Y(n295) );
OA22X1TS U10363 ( .A0(n11172), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n11171), .Y(n294) );
OA22X1TS U10364 ( .A0(n11172), .A1(final_result_ieee[58]), .B0(
exp_oper_result[6]), .B1(n11171), .Y(n293) );
OA22X1TS U10365 ( .A0(n11172), .A1(final_result_ieee[59]), .B0(
exp_oper_result[7]), .B1(n11171), .Y(n292) );
OA22X1TS U10366 ( .A0(n11172), .A1(final_result_ieee[60]), .B0(
exp_oper_result[8]), .B1(n11171), .Y(n291) );
OA22X1TS U10367 ( .A0(n11172), .A1(final_result_ieee[61]), .B0(
exp_oper_result[9]), .B1(n11171), .Y(n290) );
OA22X1TS U10368 ( .A0(n11172), .A1(final_result_ieee[62]), .B0(
exp_oper_result[10]), .B1(n11171), .Y(n289) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk40.tcl_RKOA_1STAGE_syn.sdf");
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_width (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min_cks = 1;
parameter max_cks = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_WIDTH";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if ((max_cks > 0) && (min_cks > max_cks)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal parameter values set where min_cks > max_cks");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_width_logic.v"
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endif
`ifdef OVL_SVA
`include "./sva05/assert_width_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_width_psl_logic.v"
`else
`endmodule // ovl_width
`endif
|
`timescale 1 ns / 1 ps
module elink_tb;
reg aclk;
reg aresetn;
reg start;
wire csysreq = 1'b0;
wire done;
wire error;
// Create an instance of the example tb
elink_testbench dut
(.aclk(aclk),
.aresetn(aresetn),
.csysreq(csysreq),
.done(done),
.error(error),
.start(start));
// Reset Generator
initial begin
aresetn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge aclk);
aresetn = 1'b1;
end
// Clock Generator
initial aclk = 1'b0;
always #5 aclk = ~aclk;
// Drive the BFM
initial begin
start = 1'b0;
// Wait for end of reset
wait(aresetn === 0) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
#500 start = 1'b1;
$display("=== TB Started");
wait( done == 1'b1);
$display("=== TEST_FINISHED");
if ( error ) begin
$display("===_TEST: FAILED!");
end else begin
$display("=== TEST: PASSED!");
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21OI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A21OI_FUNCTIONAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21OI_FUNCTIONAL_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:44:04 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, ready_add_subt, underflow_flag_mult, overflow_flag_addsubt,
underflow_flag_addsubt, FPSENCOS_d_ff3_sign_out,
FPSENCOS_d_ff1_operation_out, FPMULT_FSM_selector_C,
FPMULT_FSM_selector_A, FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag,
FPADDSUB_OP_FLAG_SFG, FPADDSUB_SIGN_FLAG_SFG, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_intAS, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_,
FPMULT_Sgf_operation_EVEN1_left_N23,
FPMULT_Sgf_operation_EVEN1_left_N22,
FPMULT_Sgf_operation_EVEN1_left_N21,
FPMULT_Sgf_operation_EVEN1_left_N20,
FPMULT_Sgf_operation_EVEN1_left_N19,
FPMULT_Sgf_operation_EVEN1_left_N18,
FPMULT_Sgf_operation_EVEN1_left_N17,
FPMULT_Sgf_operation_EVEN1_left_N16,
FPMULT_Sgf_operation_EVEN1_left_N15,
FPMULT_Sgf_operation_EVEN1_left_N14,
FPMULT_Sgf_operation_EVEN1_left_N13,
FPMULT_Sgf_operation_EVEN1_left_N12,
FPMULT_Sgf_operation_EVEN1_left_N11,
FPMULT_Sgf_operation_EVEN1_left_N10,
FPMULT_Sgf_operation_EVEN1_left_N9,
FPMULT_Sgf_operation_EVEN1_left_N8,
FPMULT_Sgf_operation_EVEN1_left_N7,
FPMULT_Sgf_operation_EVEN1_left_N6,
FPMULT_Sgf_operation_EVEN1_left_N5,
FPMULT_Sgf_operation_EVEN1_left_N4,
FPMULT_Sgf_operation_EVEN1_left_N3,
FPMULT_Sgf_operation_EVEN1_left_N2,
FPMULT_Sgf_operation_EVEN1_left_N1,
FPMULT_Sgf_operation_EVEN1_middle_N25,
FPMULT_Sgf_operation_EVEN1_middle_N24,
FPMULT_Sgf_operation_EVEN1_middle_N23,
FPMULT_Sgf_operation_EVEN1_middle_N22,
FPMULT_Sgf_operation_EVEN1_middle_N21,
FPMULT_Sgf_operation_EVEN1_middle_N20,
FPMULT_Sgf_operation_EVEN1_middle_N19,
FPMULT_Sgf_operation_EVEN1_middle_N18,
FPMULT_Sgf_operation_EVEN1_middle_N17,
FPMULT_Sgf_operation_EVEN1_middle_N16,
FPMULT_Sgf_operation_EVEN1_middle_N15,
FPMULT_Sgf_operation_EVEN1_middle_N14,
FPMULT_Sgf_operation_EVEN1_middle_N13,
FPMULT_Sgf_operation_EVEN1_middle_N12,
FPMULT_Sgf_operation_EVEN1_middle_N11,
FPMULT_Sgf_operation_EVEN1_middle_N10,
FPMULT_Sgf_operation_EVEN1_middle_N9,
FPMULT_Sgf_operation_EVEN1_middle_N8,
FPMULT_Sgf_operation_EVEN1_middle_N7,
FPMULT_Sgf_operation_EVEN1_middle_N6,
FPMULT_Sgf_operation_EVEN1_middle_N5,
FPMULT_Sgf_operation_EVEN1_middle_N4,
FPMULT_Sgf_operation_EVEN1_middle_N3,
FPMULT_Sgf_operation_EVEN1_middle_N2,
FPMULT_Sgf_operation_EVEN1_middle_N1,
FPMULT_Sgf_operation_EVEN1_right_N23,
FPMULT_Sgf_operation_EVEN1_right_N22,
FPMULT_Sgf_operation_EVEN1_right_N21,
FPMULT_Sgf_operation_EVEN1_right_N20,
FPMULT_Sgf_operation_EVEN1_right_N19,
FPMULT_Sgf_operation_EVEN1_right_N18,
FPMULT_Sgf_operation_EVEN1_right_N17,
FPMULT_Sgf_operation_EVEN1_right_N16,
FPMULT_Sgf_operation_EVEN1_right_N15,
FPMULT_Sgf_operation_EVEN1_right_N14,
FPMULT_Sgf_operation_EVEN1_right_N13,
FPMULT_Sgf_operation_EVEN1_right_N12,
FPMULT_Sgf_operation_EVEN1_right_N11,
FPMULT_Sgf_operation_EVEN1_right_N10,
FPMULT_Sgf_operation_EVEN1_right_N9,
FPMULT_Sgf_operation_EVEN1_right_N8,
FPMULT_Sgf_operation_EVEN1_right_N7,
FPMULT_Sgf_operation_EVEN1_right_N6,
FPMULT_Sgf_operation_EVEN1_right_N5,
FPMULT_Sgf_operation_EVEN1_right_N4,
FPMULT_Sgf_operation_EVEN1_right_N3,
FPMULT_Sgf_operation_EVEN1_right_N2,
FPMULT_Sgf_operation_EVEN1_right_N1, n1180, n1181, n1182, n1183,
n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193,
n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203,
n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213,
n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223,
n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233,
n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243,
n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253,
n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263,
n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273,
n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283,
n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293,
n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303,
n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313,
n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323,
n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333,
n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343,
n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353,
n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363,
n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373,
n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383,
n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393,
n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403,
n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413,
n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423,
n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433,
n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443,
n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453,
n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463,
n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473,
n1474, n1475, n1476, n1477, n1478, n1480, n1481, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786,
n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796,
n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806,
n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816,
n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826,
n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836,
n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846,
n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856,
n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866,
n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876,
n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886,
n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896,
n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906,
n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916,
n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926,
n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936,
n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946,
n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956,
n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966,
n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976,
n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986,
n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996,
n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006,
n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016,
n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026,
n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036,
n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046,
n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056,
n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066,
n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076,
n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086,
n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096,
n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106,
n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116,
n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126,
n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136,
n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146,
n2147, n2148, n2149, n2191, DP_OP_26J221_124_9022_n18,
DP_OP_26J221_124_9022_n17, DP_OP_26J221_124_9022_n16,
DP_OP_26J221_124_9022_n15, DP_OP_26J221_124_9022_n14,
DP_OP_26J221_124_9022_n8, DP_OP_26J221_124_9022_n7,
DP_OP_26J221_124_9022_n6, DP_OP_26J221_124_9022_n5,
DP_OP_26J221_124_9022_n4, DP_OP_26J221_124_9022_n3,
DP_OP_26J221_124_9022_n2, DP_OP_26J221_124_9022_n1,
DP_OP_234J221_127_8543_n22, DP_OP_234J221_127_8543_n21,
DP_OP_234J221_127_8543_n20, DP_OP_234J221_127_8543_n19,
DP_OP_234J221_127_8543_n18, DP_OP_234J221_127_8543_n17,
DP_OP_234J221_127_8543_n16, DP_OP_234J221_127_8543_n15,
DP_OP_234J221_127_8543_n9, DP_OP_234J221_127_8543_n8,
DP_OP_234J221_127_8543_n7, DP_OP_234J221_127_8543_n6,
DP_OP_234J221_127_8543_n5, DP_OP_234J221_127_8543_n4,
DP_OP_234J221_127_8543_n3, DP_OP_234J221_127_8543_n2,
DP_OP_234J221_127_8543_n1, intadd_500_CI, intadd_500_SUM_2_,
intadd_500_SUM_1_, intadd_500_SUM_0_, intadd_500_n3, intadd_500_n2,
intadd_500_n1, intadd_501_B_1_, intadd_501_CI, intadd_501_SUM_2_,
intadd_501_SUM_1_, intadd_501_SUM_0_, intadd_501_n3, intadd_501_n2,
intadd_501_n1, intadd_502_CI, intadd_502_SUM_2_, intadd_502_SUM_1_,
intadd_502_SUM_0_, intadd_502_n3, intadd_502_n2, intadd_502_n1,
intadd_499_A_24_, intadd_499_A_23_, intadd_499_A_22_,
intadd_499_A_21_, intadd_499_A_20_, intadd_499_A_19_,
intadd_499_A_18_, intadd_499_A_17_, intadd_499_A_16_,
intadd_499_A_15_, intadd_499_A_14_, intadd_499_A_13_,
intadd_499_A_12_, intadd_499_A_11_, intadd_499_A_10_, intadd_499_A_9_,
intadd_499_A_8_, intadd_499_A_7_, intadd_499_A_6_, intadd_499_A_5_,
intadd_499_A_4_, intadd_499_A_3_, intadd_499_A_2_, intadd_499_B_24_,
intadd_499_B_23_, intadd_499_B_22_, intadd_499_B_21_,
intadd_499_B_20_, intadd_499_B_19_, intadd_499_B_18_,
intadd_499_B_17_, intadd_499_B_16_, intadd_499_B_15_,
intadd_499_B_14_, intadd_499_B_13_, intadd_499_B_12_,
intadd_499_B_11_, intadd_499_B_10_, intadd_499_B_9_, intadd_499_B_8_,
intadd_499_B_7_, intadd_499_B_6_, intadd_499_B_5_, intadd_499_B_4_,
intadd_499_B_3_, intadd_499_B_2_, intadd_499_B_1_, intadd_499_B_0_,
intadd_499_SUM_24_, intadd_499_SUM_23_, intadd_499_SUM_22_,
intadd_499_SUM_21_, intadd_499_SUM_20_, intadd_499_SUM_19_,
intadd_499_SUM_18_, intadd_499_SUM_17_, intadd_499_SUM_16_,
intadd_499_SUM_15_, intadd_499_SUM_14_, intadd_499_SUM_13_,
intadd_499_SUM_12_, intadd_499_SUM_11_, intadd_499_SUM_10_,
intadd_499_SUM_9_, intadd_499_SUM_8_, intadd_499_SUM_7_,
intadd_499_SUM_6_, intadd_499_SUM_5_, intadd_499_SUM_4_,
intadd_499_SUM_3_, intadd_499_SUM_2_, intadd_499_SUM_1_,
intadd_499_SUM_0_, intadd_499_n25, intadd_499_n24, intadd_499_n23,
intadd_499_n22, intadd_499_n21, intadd_499_n20, intadd_499_n19,
intadd_499_n18, intadd_499_n17, intadd_499_n16, intadd_499_n15,
intadd_499_n14, intadd_499_n13, intadd_499_n12, intadd_499_n11,
intadd_499_n10, intadd_499_n9, intadd_499_n8, intadd_499_n7,
intadd_499_n6, intadd_499_n5, intadd_499_n4, intadd_499_n3,
intadd_499_n2, intadd_499_n1, DP_OP_454J221_123_2743_n453,
DP_OP_454J221_123_2743_n367, DP_OP_454J221_123_2743_n252,
DP_OP_454J221_123_2743_n251, DP_OP_454J221_123_2743_n250,
DP_OP_454J221_123_2743_n249, DP_OP_454J221_123_2743_n248,
DP_OP_454J221_123_2743_n247, DP_OP_454J221_123_2743_n246,
DP_OP_454J221_123_2743_n245, DP_OP_454J221_123_2743_n240,
DP_OP_454J221_123_2743_n236, DP_OP_454J221_123_2743_n235,
DP_OP_454J221_123_2743_n234, DP_OP_454J221_123_2743_n233,
DP_OP_454J221_123_2743_n232, DP_OP_454J221_123_2743_n231,
DP_OP_454J221_123_2743_n227, DP_OP_454J221_123_2743_n223,
DP_OP_454J221_123_2743_n219, DP_OP_454J221_123_2743_n218,
DP_OP_454J221_123_2743_n217, DP_OP_454J221_123_2743_n216,
DP_OP_454J221_123_2743_n215, DP_OP_454J221_123_2743_n214,
DP_OP_454J221_123_2743_n213, DP_OP_454J221_123_2743_n212,
DP_OP_454J221_123_2743_n210, DP_OP_454J221_123_2743_n204,
DP_OP_454J221_123_2743_n203, DP_OP_454J221_123_2743_n202,
DP_OP_454J221_123_2743_n200, DP_OP_454J221_123_2743_n199,
DP_OP_454J221_123_2743_n198, DP_OP_454J221_123_2743_n197,
DP_OP_454J221_123_2743_n196, DP_OP_454J221_123_2743_n195,
DP_OP_454J221_123_2743_n191, DP_OP_454J221_123_2743_n188,
DP_OP_454J221_123_2743_n187, DP_OP_454J221_123_2743_n186,
DP_OP_454J221_123_2743_n185, DP_OP_454J221_123_2743_n184,
DP_OP_454J221_123_2743_n183, DP_OP_454J221_123_2743_n182,
DP_OP_454J221_123_2743_n181, DP_OP_454J221_123_2743_n180,
DP_OP_454J221_123_2743_n179, DP_OP_454J221_123_2743_n178,
DP_OP_454J221_123_2743_n177, DP_OP_454J221_123_2743_n176,
DP_OP_454J221_123_2743_n175, DP_OP_454J221_123_2743_n172,
DP_OP_454J221_123_2743_n171, DP_OP_454J221_123_2743_n170,
DP_OP_454J221_123_2743_n169, DP_OP_454J221_123_2743_n168,
DP_OP_454J221_123_2743_n167, DP_OP_454J221_123_2743_n166,
DP_OP_454J221_123_2743_n165, DP_OP_454J221_123_2743_n164,
DP_OP_454J221_123_2743_n163, DP_OP_454J221_123_2743_n162,
DP_OP_454J221_123_2743_n156, DP_OP_454J221_123_2743_n155,
DP_OP_454J221_123_2743_n148, DP_OP_454J221_123_2743_n145,
DP_OP_454J221_123_2743_n144, DP_OP_454J221_123_2743_n143,
DP_OP_454J221_123_2743_n142, DP_OP_454J221_123_2743_n140,
DP_OP_454J221_123_2743_n139, DP_OP_454J221_123_2743_n138,
DP_OP_454J221_123_2743_n137, DP_OP_454J221_123_2743_n135,
DP_OP_454J221_123_2743_n134, DP_OP_454J221_123_2743_n133,
DP_OP_454J221_123_2743_n131, DP_OP_454J221_123_2743_n130,
DP_OP_454J221_123_2743_n129, DP_OP_454J221_123_2743_n128,
DP_OP_454J221_123_2743_n127, DP_OP_454J221_123_2743_n126,
DP_OP_454J221_123_2743_n125, DP_OP_454J221_123_2743_n124,
DP_OP_454J221_123_2743_n123, DP_OP_454J221_123_2743_n122,
DP_OP_454J221_123_2743_n121, DP_OP_454J221_123_2743_n120,
DP_OP_454J221_123_2743_n119, DP_OP_454J221_123_2743_n117,
DP_OP_454J221_123_2743_n116, DP_OP_454J221_123_2743_n115,
DP_OP_454J221_123_2743_n114, DP_OP_454J221_123_2743_n113,
DP_OP_454J221_123_2743_n112, DP_OP_454J221_123_2743_n111,
DP_OP_454J221_123_2743_n109, DP_OP_454J221_123_2743_n108,
DP_OP_454J221_123_2743_n107, DP_OP_454J221_123_2743_n106,
DP_OP_454J221_123_2743_n105, DP_OP_454J221_123_2743_n104,
DP_OP_454J221_123_2743_n103, DP_OP_454J221_123_2743_n102,
DP_OP_454J221_123_2743_n101, DP_OP_454J221_123_2743_n100,
DP_OP_454J221_123_2743_n99, DP_OP_454J221_123_2743_n98,
DP_OP_454J221_123_2743_n97, DP_OP_454J221_123_2743_n96,
DP_OP_454J221_123_2743_n94, DP_OP_454J221_123_2743_n93,
DP_OP_454J221_123_2743_n92, DP_OP_454J221_123_2743_n91,
DP_OP_454J221_123_2743_n90, DP_OP_454J221_123_2743_n89,
DP_OP_454J221_123_2743_n88, DP_OP_454J221_123_2743_n87,
DP_OP_454J221_123_2743_n84, DP_OP_454J221_123_2743_n83,
DP_OP_454J221_123_2743_n82, DP_OP_454J221_123_2743_n81,
DP_OP_454J221_123_2743_n80, DP_OP_454J221_123_2743_n79,
DP_OP_454J221_123_2743_n78, DP_OP_454J221_123_2743_n77,
DP_OP_454J221_123_2743_n76, DP_OP_454J221_123_2743_n75,
DP_OP_454J221_123_2743_n74, DP_OP_454J221_123_2743_n73,
DP_OP_454J221_123_2743_n72, DP_OP_454J221_123_2743_n71,
DP_OP_454J221_123_2743_n70, DP_OP_454J221_123_2743_n69,
DP_OP_454J221_123_2743_n68, DP_OP_454J221_123_2743_n67,
DP_OP_454J221_123_2743_n66, DP_OP_454J221_123_2743_n65,
DP_OP_454J221_123_2743_n64, DP_OP_454J221_123_2743_n63,
DP_OP_454J221_123_2743_n62, DP_OP_454J221_123_2743_n61,
DP_OP_454J221_123_2743_n60, DP_OP_454J221_123_2743_n59,
DP_OP_454J221_123_2743_n58, DP_OP_454J221_123_2743_n57,
DP_OP_454J221_123_2743_n56, DP_OP_454J221_123_2743_n55,
DP_OP_454J221_123_2743_n52, DP_OP_454J221_123_2743_n51,
DP_OP_454J221_123_2743_n50, DP_OP_454J221_123_2743_n49,
DP_OP_454J221_123_2743_n48, DP_OP_454J221_123_2743_n47,
DP_OP_454J221_123_2743_n46, DP_OP_454J221_123_2743_n45,
DP_OP_454J221_123_2743_n44, DP_OP_454J221_123_2743_n43,
DP_OP_454J221_123_2743_n42, DP_OP_454J221_123_2743_n41,
DP_OP_454J221_123_2743_n40, DP_OP_454J221_123_2743_n39,
DP_OP_454J221_123_2743_n38, DP_OP_454J221_123_2743_n37,
DP_OP_454J221_123_2743_n36, DP_OP_454J221_123_2743_n35,
mult_x_254_n232, mult_x_254_n228, mult_x_254_n220, mult_x_254_n219,
mult_x_254_n216, mult_x_254_n215, mult_x_254_n213, mult_x_254_n212,
mult_x_254_n211, mult_x_254_n208, mult_x_254_n207, mult_x_254_n206,
mult_x_254_n205, mult_x_254_n204, mult_x_254_n203, mult_x_254_n202,
mult_x_254_n200, mult_x_254_n199, mult_x_254_n198, mult_x_254_n197,
mult_x_254_n196, mult_x_254_n195, mult_x_254_n194, mult_x_254_n192,
mult_x_254_n191, mult_x_254_n190, mult_x_254_n189, mult_x_254_n186,
mult_x_254_n185, mult_x_254_n183, mult_x_254_n180, mult_x_254_n179,
mult_x_254_n178, mult_x_254_n176, mult_x_254_n175, mult_x_254_n174,
mult_x_254_n173, mult_x_254_n170, mult_x_254_n169, mult_x_254_n168,
mult_x_254_n167, mult_x_254_n166, mult_x_254_n165, mult_x_254_n164,
mult_x_254_n163, mult_x_254_n162, mult_x_254_n161, mult_x_254_n160,
mult_x_254_n159, mult_x_254_n158, mult_x_254_n157, mult_x_254_n151,
mult_x_254_n149, mult_x_254_n136, mult_x_254_n133, mult_x_254_n132,
mult_x_254_n131, mult_x_254_n130, mult_x_254_n129, mult_x_254_n128,
mult_x_254_n127, mult_x_254_n126, mult_x_254_n125, mult_x_254_n124,
mult_x_254_n123, mult_x_254_n122, mult_x_254_n121, mult_x_254_n120,
mult_x_254_n119, mult_x_254_n118, mult_x_254_n117, mult_x_254_n116,
mult_x_254_n115, mult_x_254_n114, mult_x_254_n113, mult_x_254_n112,
mult_x_254_n111, mult_x_254_n110, mult_x_254_n109, mult_x_254_n108,
mult_x_254_n107, mult_x_254_n106, mult_x_254_n105, mult_x_254_n104,
mult_x_254_n103, mult_x_254_n102, mult_x_254_n101, mult_x_254_n100,
mult_x_254_n99, mult_x_254_n98, mult_x_254_n97, mult_x_254_n96,
mult_x_254_n95, mult_x_254_n94, mult_x_254_n93, mult_x_254_n92,
mult_x_254_n90, mult_x_254_n89, mult_x_254_n88, mult_x_254_n87,
mult_x_254_n86, mult_x_254_n85, mult_x_254_n84, mult_x_254_n83,
mult_x_254_n80, mult_x_254_n79, mult_x_254_n78, mult_x_254_n77,
mult_x_254_n76, mult_x_254_n75, mult_x_254_n74, mult_x_254_n73,
mult_x_254_n72, mult_x_254_n71, mult_x_254_n70, mult_x_254_n69,
mult_x_254_n68, mult_x_254_n67, mult_x_254_n66, mult_x_254_n65,
mult_x_254_n64, mult_x_254_n63, mult_x_254_n62, mult_x_254_n61,
mult_x_254_n60, mult_x_254_n59, mult_x_254_n58, mult_x_254_n57,
mult_x_254_n56, mult_x_254_n55, mult_x_254_n54, mult_x_254_n53,
mult_x_254_n52, mult_x_254_n51, mult_x_254_n48, mult_x_254_n47,
mult_x_254_n46, mult_x_254_n45, mult_x_254_n44, mult_x_254_n43,
mult_x_254_n42, mult_x_254_n41, mult_x_254_n40, mult_x_254_n39,
mult_x_254_n38, mult_x_254_n37, mult_x_254_n36, mult_x_254_n35,
mult_x_254_n34, mult_x_254_n33, mult_x_254_n32, mult_x_254_n31,
mult_x_219_n226, mult_x_219_n222, mult_x_219_n214, mult_x_219_n213,
mult_x_219_n210, mult_x_219_n209, mult_x_219_n207, mult_x_219_n206,
mult_x_219_n205, mult_x_219_n202, mult_x_219_n201, mult_x_219_n200,
mult_x_219_n199, mult_x_219_n198, mult_x_219_n197, mult_x_219_n196,
mult_x_219_n194, mult_x_219_n193, mult_x_219_n192, mult_x_219_n191,
mult_x_219_n190, mult_x_219_n189, mult_x_219_n188, mult_x_219_n186,
mult_x_219_n185, mult_x_219_n184, mult_x_219_n183, mult_x_219_n180,
mult_x_219_n179, mult_x_219_n177, mult_x_219_n174, mult_x_219_n173,
mult_x_219_n172, mult_x_219_n170, mult_x_219_n169, mult_x_219_n168,
mult_x_219_n167, mult_x_219_n164, mult_x_219_n163, mult_x_219_n162,
mult_x_219_n161, mult_x_219_n160, mult_x_219_n159, mult_x_219_n158,
mult_x_219_n157, mult_x_219_n156, mult_x_219_n155, mult_x_219_n154,
mult_x_219_n153, mult_x_219_n152, mult_x_219_n151, mult_x_219_n136,
mult_x_219_n133, mult_x_219_n132, mult_x_219_n131, mult_x_219_n130,
mult_x_219_n129, mult_x_219_n128, mult_x_219_n127, mult_x_219_n126,
mult_x_219_n125, mult_x_219_n124, mult_x_219_n123, mult_x_219_n122,
mult_x_219_n121, mult_x_219_n120, mult_x_219_n119, mult_x_219_n118,
mult_x_219_n117, mult_x_219_n116, mult_x_219_n115, mult_x_219_n114,
mult_x_219_n113, mult_x_219_n112, mult_x_219_n111, mult_x_219_n110,
mult_x_219_n109, mult_x_219_n108, mult_x_219_n107, mult_x_219_n106,
mult_x_219_n105, mult_x_219_n104, mult_x_219_n103, mult_x_219_n102,
mult_x_219_n101, mult_x_219_n100, mult_x_219_n99, mult_x_219_n98,
mult_x_219_n97, mult_x_219_n96, mult_x_219_n95, mult_x_219_n94,
mult_x_219_n93, mult_x_219_n92, mult_x_219_n90, mult_x_219_n89,
mult_x_219_n88, mult_x_219_n87, mult_x_219_n86, mult_x_219_n85,
mult_x_219_n84, mult_x_219_n83, mult_x_219_n80, mult_x_219_n79,
mult_x_219_n78, mult_x_219_n77, mult_x_219_n76, mult_x_219_n75,
mult_x_219_n74, mult_x_219_n73, mult_x_219_n72, mult_x_219_n71,
mult_x_219_n70, mult_x_219_n69, mult_x_219_n68, mult_x_219_n67,
mult_x_219_n66, mult_x_219_n65, mult_x_219_n62, mult_x_219_n61,
mult_x_219_n60, mult_x_219_n59, mult_x_219_n58, mult_x_219_n57,
mult_x_219_n56, mult_x_219_n55, mult_x_219_n54, mult_x_219_n53,
mult_x_219_n52, mult_x_219_n51, mult_x_219_n48, mult_x_219_n47,
mult_x_219_n46, mult_x_219_n45, mult_x_219_n44, mult_x_219_n43,
mult_x_219_n42, mult_x_219_n41, mult_x_219_n40, mult_x_219_n39,
mult_x_219_n36, mult_x_219_n35, mult_x_219_n34, mult_x_219_n33,
mult_x_219_n32, mult_x_219_n31, n2194, n2195, n2196, n2197, n2198,
n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208,
n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218,
n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228,
n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238,
n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248,
n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258,
n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268,
n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278,
n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288,
n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298,
n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308,
n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318,
n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328,
n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338,
n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348,
n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358,
n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368,
n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378,
n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388,
n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398,
n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2409,
n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419,
n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429,
n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439,
n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449,
n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459,
n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469,
n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479,
n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489,
n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499,
n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509,
n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519,
n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529,
n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539,
n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549,
n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559,
n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569,
n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579,
n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589,
n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599,
n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609,
n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619,
n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629,
n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639,
n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649,
n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659,
n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669,
n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679,
n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689,
n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699,
n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709,
n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719,
n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729,
n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739,
n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749,
n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759,
n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769,
n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779,
n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789,
n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859,
n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869,
n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879,
n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889,
n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949,
n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959,
n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969,
n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979,
n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989,
n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999,
n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009,
n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019,
n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029,
n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039,
n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049,
n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059,
n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069,
n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079,
n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089,
n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099,
n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109,
n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119,
n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129,
n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139,
n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149,
n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159,
n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169,
n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179,
n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189,
n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199,
n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209,
n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219,
n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229,
n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239,
n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249,
n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259,
n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269,
n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279,
n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289,
n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299,
n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309,
n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319,
n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329,
n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339,
n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349,
n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359,
n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3368, n3369, n3370,
n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380,
n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390,
n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400,
n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410,
n3411, n3412, n3413, n3414, n3416, n3417, n3418, n3419, n3420, n3421,
n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431,
n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441,
n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451,
n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461,
n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471,
n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481,
n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491,
n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501,
n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511,
n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521,
n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531,
n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541,
n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551,
n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561,
n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571,
n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581,
n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591,
n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601,
n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611,
n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621,
n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631,
n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641,
n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651,
n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661,
n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671,
n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681,
n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691,
n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701,
n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711,
n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721,
n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731,
n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741,
n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751,
n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761,
n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771,
n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781,
n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791,
n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801,
n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811,
n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821,
n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831,
n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841,
n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851,
n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861,
n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871,
n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881,
n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891,
n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901,
n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911,
n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921,
n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931,
n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941,
n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951,
n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961,
n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971,
n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981,
n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991,
n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001,
n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011,
n4012, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022,
n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032,
n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042,
n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052,
n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062,
n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072,
n4074, n4075, n4076, n4078, n4079, n4080, n4081, n4082, n4083, n4084,
n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094,
n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104,
n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114,
n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124,
n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134,
n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144,
n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154,
n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164,
n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174,
n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184,
n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194,
n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204,
n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214,
n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224,
n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234,
n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244,
n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254,
n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264,
n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274,
n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284,
n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294,
n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304,
n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314,
n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324,
n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334,
n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344,
n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354,
n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364,
n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374,
n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384,
n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394,
n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404,
n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414,
n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424,
n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434,
n4435, n4436, n4437, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4463, n4464, n4465, n4467,
n4468, n4469, n4470, n4471, n4473, n4474, n4475, n4477, n4478, n4479,
n4480, n4481, n4482, n4484, n4485, n4486, n4487, n4488, n4489, n4490,
n4491, n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500,
n4501, n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510,
n4511, n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520,
n4521, n4522, n4523, n4525, n4526, n4527, n4528, n4529, n4530, n4531,
n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541,
n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551,
n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561,
n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571,
n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581,
n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591,
n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601,
n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611,
n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621,
n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631,
n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641,
n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651,
n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661,
n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671,
n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681,
n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691,
n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701,
n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711,
n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721,
n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731,
n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741,
n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751,
n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761,
n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771,
n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781,
n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791,
n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801,
n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811,
n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821,
n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4831, n4832,
n4833, n4834, n4835, n4836;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:1] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:0] FPMULT_P_Sgf;
wire [25:0] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [25:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:1] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [11:0] FPMULT_Sgf_operation_Result;
wire [25:1] FPMULT_Sgf_operation_EVEN1_Q_middle;
wire [23:12] FPMULT_Sgf_operation_EVEN1_Q_right;
wire [23:0] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n4808), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n4803), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n4806), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n4812), .Q(
dataB[23]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n4807), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n4807), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n4807), .Q(
dataB[28]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n4807), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n4807), .Q(
dataB[31]) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n4807), .Q(NaN_flag)
);
DFFRXLTS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2137), .CK(clk), .RN(n4799),
.Q(FPSENCOS_cont_var_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2126), .CK(clk), .RN(n4809), .Q(
FPSENCOS_d_ff3_LUT_out[7]), .QN(n4740) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2125), .CK(clk), .RN(n4798), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2124), .CK(clk), .RN(n4793), .Q(
FPSENCOS_d_ff3_LUT_out[9]), .QN(n4739) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2123), .CK(clk), .RN(n4805), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2121), .CK(clk), .RN(n4805), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2120), .CK(clk), .RN(n4805), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2119), .CK(clk), .RN(n4805), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2118), .CK(clk), .RN(n4805), .Q(
FPSENCOS_d_ff3_LUT_out[21]), .QN(n4754) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2117), .CK(clk), .RN(n4805), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2113), .CK(clk), .RN(n4805), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1853), .CK(clk), .RN(n4805),
.QN(n2198) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1852), .CK(clk), .RN(n4805),
.Q(FPSENCOS_d_ff3_sh_y_out[24]), .QN(n4751) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1851), .CK(clk), .RN(n4805),
.Q(FPSENCOS_d_ff3_sh_y_out[25]), .QN(n4752) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1850), .CK(clk), .RN(n4804),
.Q(FPSENCOS_d_ff3_sh_y_out[26]), .QN(n4753) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1849), .CK(clk), .RN(n4804),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1848), .CK(clk), .RN(n4804),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1847), .CK(clk), .RN(n4804),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1846), .CK(clk), .RN(n4804),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1951), .CK(clk), .RN(n4804),
.Q(FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1950), .CK(clk), .RN(n4804),
.Q(FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1949), .CK(clk), .RN(n4800),
.Q(FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1948), .CK(clk), .RN(n4800),
.Q(FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1947), .CK(clk), .RN(n4804),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1946), .CK(clk), .RN(n4804),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2112), .CK(clk), .RN(n4807), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2111), .CK(clk), .RN(n4817), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2110), .CK(clk), .RN(n4814), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2109), .CK(clk), .RN(n4817), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2108), .CK(clk), .RN(n4814), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2107), .CK(clk), .RN(n4817), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2106), .CK(clk), .RN(n4814), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2105), .CK(clk), .RN(n4817), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2104), .CK(clk), .RN(n4814), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2103), .CK(clk), .RN(n4817), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2102), .CK(clk), .RN(n4795), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2101), .CK(clk), .RN(n4816), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2100), .CK(clk), .RN(n4813), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2099), .CK(clk), .RN(n4802), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2098), .CK(clk), .RN(n2930), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2097), .CK(clk), .RN(n4810), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2096), .CK(clk), .RN(n4809), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2095), .CK(clk), .RN(n4795), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2094), .CK(clk), .RN(n4816), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2093), .CK(clk), .RN(n4813), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2092), .CK(clk), .RN(n4802), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2091), .CK(clk), .RN(n4810), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2090), .CK(clk), .RN(n4801), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2089), .CK(clk), .RN(n4811), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2088), .CK(clk), .RN(n2202), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2087), .CK(clk), .RN(n2929), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2086), .CK(clk), .RN(n4812), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2085), .CK(clk), .RN(n2928), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2084), .CK(clk), .RN(n4815), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2083), .CK(clk), .RN(n4801), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2082), .CK(clk), .RN(n4811), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2081), .CK(clk), .RN(n4812), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n4812), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1741), .CK(clk), .RN(
n4815), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1703), .CK(clk), .RN(n4811),
.Q(cordic_result[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n4812), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1740), .CK(clk), .RN(
n4812), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1702), .CK(clk), .RN(n4814),
.Q(cordic_result[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n4817), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1739), .CK(clk), .RN(
n4814), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1701), .CK(clk), .RN(n4817),
.Q(cordic_result[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n4814), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1738), .CK(clk), .RN(
n4817), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1700), .CK(clk), .RN(n4795),
.Q(cordic_result[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n4816), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1737), .CK(clk), .RN(
n4813), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1772), .CK(clk), .RN(n4802), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1699), .CK(clk), .RN(n4810),
.Q(cordic_result[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n4809), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1913), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n4684) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n4815), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1735), .CK(clk), .RN(
n4801), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1697), .CK(clk), .RN(n2929),
.Q(cordic_result[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1765), .CK(clk), .RN(n2928), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1734), .CK(clk), .RN(
n2202), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1696), .CK(clk), .RN(n4811),
.Q(cordic_result[30]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1788), .CK(clk), .RN(n4772),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n4801), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1742), .CK(clk), .RN(
n4815), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1862), .CK(clk), .RN(n4802),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1961), .CK(clk), .RN(
n2930), .Q(FPSENCOS_d_ff2_X[22]), .QN(n4737) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1960), .CK(clk), .RN(n4810),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n4809), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1749), .CK(clk), .RN(
n4795), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1876), .CK(clk), .RN(n4816),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1975), .CK(clk), .RN(
n4813), .Q(FPSENCOS_d_ff2_X[15]), .QN(n4734) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1974), .CK(clk), .RN(n4802),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n4809), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1746), .CK(clk), .RN(
n4810), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1870), .CK(clk), .RN(n2930),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1969), .CK(clk), .RN(
n4795), .Q(FPSENCOS_d_ff2_X[18]), .QN(n4735) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1968), .CK(clk), .RN(n4816),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1789), .CK(clk), .RN(n2267),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n4813), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1743), .CK(clk), .RN(
n4810), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1864), .CK(clk), .RN(n2929),
.Q(FPSENCOS_d_ff3_sh_y_out[21]), .QN(n4750) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1963), .CK(clk), .RN(
n4809), .Q(FPSENCOS_d_ff2_X[21]), .QN(n4736) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1962), .CK(clk), .RN(n4804),
.Q(FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n4814), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1745), .CK(clk), .RN(
n2930), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1868), .CK(clk), .RN(n2202),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1967), .CK(clk), .RN(
n2928), .Q(FPSENCOS_d_ff2_X[19]), .QN(n2271) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1966), .CK(clk), .RN(n2928),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1790), .CK(clk), .RN(n4775),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n2928), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1744), .CK(clk), .RN(
n4799), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1866), .CK(clk), .RN(n4791),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1964), .CK(clk), .RN(n4797),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n4817), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1872), .CK(clk), .RN(n4814),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2021), .CK(clk), .RN(n4814), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1971), .CK(clk), .RN(
n4790), .Q(FPSENCOS_d_ff2_X[17]), .QN(n2276) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1970), .CK(clk), .RN(n4794),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n4809), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1760), .CK(clk), .RN(
n4797), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1898), .CK(clk), .RN(n4794),
.Q(FPSENCOS_d_ff3_sh_y_out[4]), .QN(n4744) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1997), .CK(clk), .RN(
n4805), .Q(FPSENCOS_d_ff2_X[4]), .QN(n4730) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1996), .CK(clk), .RN(n4797),
.Q(FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n4794), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1758), .CK(clk), .RN(
n4793), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1894), .CK(clk), .RN(n4791),
.Q(FPSENCOS_d_ff3_sh_y_out[6]), .QN(n4745) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1993), .CK(clk), .RN(
n4793), .Q(FPSENCOS_d_ff2_X[6]), .QN(n2197) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1992), .CK(clk), .RN(n4796),
.Q(FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n4791), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1751), .CK(clk), .RN(
n4793), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1880), .CK(clk), .RN(n4800),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2033), .CK(clk), .RN(n4796), .Q(
FPSENCOS_d_ff_Xn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1979), .CK(clk), .RN(
n4791), .Q(FPSENCOS_d_ff2_X[13]), .QN(n2295) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1978), .CK(clk), .RN(n4803),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n4816), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1748), .CK(clk), .RN(
n4810), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1874), .CK(clk), .RN(n4806),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1973), .CK(clk), .RN(
n4810), .Q(FPSENCOS_d_ff2_X[16]), .QN(n2277) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1972), .CK(clk), .RN(n4806),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n4795), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1756), .CK(clk), .RN(
n2202), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1890), .CK(clk), .RN(n4792),
.Q(FPSENCOS_d_ff3_sh_y_out[8]), .QN(n4746) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1989), .CK(clk), .RN(
n4792), .Q(FPSENCOS_d_ff2_X[8]), .QN(n4731) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1988), .CK(clk), .RN(n4792),
.Q(FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n4792), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1753), .CK(clk), .RN(
n4792), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1884), .CK(clk), .RN(n4792),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1983), .CK(clk), .RN(
n4797), .Q(FPSENCOS_d_ff2_X[11]), .QN(n4733) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1982), .CK(clk), .RN(n4794),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n4796), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1750), .CK(clk), .RN(
n4797), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1878), .CK(clk), .RN(n4794),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1977), .CK(clk), .RN(
n4797), .Q(FPSENCOS_d_ff2_X[14]), .QN(n2282) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1976), .CK(clk), .RN(n4794),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n4792), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1754), .CK(clk), .RN(
n4797), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1886), .CK(clk), .RN(n4791),
.Q(FPSENCOS_d_ff3_sh_y_out[10]), .QN(n4748) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1985), .CK(clk), .RN(
n4793), .Q(FPSENCOS_d_ff2_X[10]), .QN(n2288) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1984), .CK(clk), .RN(n4796),
.Q(FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n4791), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1752), .CK(clk), .RN(
n4793), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1882), .CK(clk), .RN(n4793),
.Q(FPSENCOS_d_ff3_sh_y_out[12]), .QN(n4749) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1981), .CK(clk), .RN(
n4791), .Q(FPSENCOS_d_ff2_X[12]), .QN(n2302) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1980), .CK(clk), .RN(n4817),
.Q(FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1909), .CK(clk), .RN(n4793), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1844), .CK(clk), .RN(n4791),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1943), .CK(clk), .RN(
n4803), .Q(FPSENCOS_d_ff2_X[31]), .QN(n4738) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1942), .CK(clk), .RN(n4793),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2078), .CK(clk), .RN(
n4784), .Q(FPADDSUB_left_right_SHT2) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n4796), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1761), .CK(clk), .RN(
n4790), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1900), .CK(clk), .RN(n4790),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n1999), .CK(clk), .RN(
n4790), .Q(FPSENCOS_d_ff2_X[3]), .QN(n2196) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n1998), .CK(clk), .RN(n4790),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1723), .CK(clk), .RN(n4790),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n4790), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1762), .CK(clk), .RN(
n4790), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1902), .CK(clk), .RN(n4808),
.Q(FPSENCOS_d_ff3_sh_y_out[2]), .QN(n4743) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2001), .CK(clk), .RN(
n4808), .Q(FPSENCOS_d_ff2_X[2]), .QN(n2294) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2000), .CK(clk), .RN(n4799),
.Q(FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1724), .CK(clk), .RN(n4799),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n2202), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1757), .CK(clk), .RN(
n2202), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1892), .CK(clk), .RN(n4806),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2051), .CK(clk), .RN(n2930), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1990), .CK(clk), .RN(n4810),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1719), .CK(clk), .RN(n4809),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n4795), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1764), .CK(clk), .RN(
n4816), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1906), .CK(clk), .RN(n4813),
.Q(FPSENCOS_d_ff3_sh_y_out[0]), .QN(n4741) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2005), .CK(clk), .RN(
n4802), .Q(FPSENCOS_d_ff2_X[0]), .QN(n4729) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2004), .CK(clk), .RN(n2930),
.Q(FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1726), .CK(clk), .RN(n2928),
.Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n4815), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1763), .CK(clk), .RN(
n4801), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1904), .CK(clk), .RN(n2202),
.Q(FPSENCOS_d_ff3_sh_y_out[1]), .QN(n4742) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2069), .CK(clk), .RN(n2929), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2003), .CK(clk), .RN(
n4812), .Q(FPSENCOS_d_ff2_X[1]), .QN(n2234) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2002), .CK(clk), .RN(n2928),
.Q(FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1725), .CK(clk), .RN(n4815),
.Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n4801), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1755), .CK(clk), .RN(
n4811), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1888), .CK(clk), .RN(n4800),
.Q(FPSENCOS_d_ff3_sh_y_out[9]), .QN(n4747) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1987), .CK(clk), .RN(
n4800), .Q(FPSENCOS_d_ff2_X[9]), .QN(n4732) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1986), .CK(clk), .RN(n4800),
.Q(FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1717), .CK(clk), .RN(n4800),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n4800), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1759), .CK(clk), .RN(
n4800), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1896), .CK(clk), .RN(n4800),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2057), .CK(clk), .RN(n4808), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1995), .CK(clk), .RN(
n4799), .Q(FPSENCOS_d_ff2_X[5]), .QN(n2296) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1994), .CK(clk), .RN(n4803),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1721), .CK(clk), .RN(n4794),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1695), .CK(clk), .RN(n4806),
.Q(cordic_result[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1714), .CK(clk), .RN(n2202),
.Q(cordic_result[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1716), .CK(clk), .RN(n2202),
.Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1712), .CK(clk), .RN(n4808),
.Q(cordic_result[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1715), .CK(clk), .RN(n4799),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1718), .CK(clk), .RN(n4806),
.Q(cordic_result[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1710), .CK(clk), .RN(n4803),
.Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1713), .CK(clk), .RN(n4792),
.Q(cordic_result[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1720), .CK(clk), .RN(n4806),
.Q(cordic_result[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1722), .CK(clk), .RN(n2202),
.Q(cordic_result[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1709), .CK(clk), .RN(n4808),
.Q(cordic_result[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1706), .CK(clk), .RN(n4799),
.Q(cordic_result[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1707), .CK(clk), .RN(n4803),
.Q(cordic_result[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1705), .CK(clk), .RN(n4810),
.Q(cordic_result[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1708), .CK(clk), .RN(n4790),
.Q(cordic_result[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1711), .CK(clk), .RN(n4806),
.Q(cordic_result[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1704), .CK(clk), .RN(n2202),
.Q(cordic_result[22]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1787), .CK(clk), .RN(n2266),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1624), .CK(clk),
.RN(n4818), .Q(FPMULT_Op_MY[31]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1657), .CK(clk),
.RN(n4819), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1599), .CK(clk),
.RN(n4819), .Q(FPMULT_Add_result[21]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1600), .CK(clk),
.RN(n4821), .Q(FPMULT_Add_result[20]), .QN(n4726) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1602), .CK(clk),
.RN(n4828), .Q(FPMULT_Add_result[18]), .QN(n4727) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1608), .CK(clk),
.RN(n4819), .Q(FPMULT_Add_result[12]), .QN(n4728) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1613), .CK(clk), .RN(
n4820), .Q(FPMULT_Add_result[7]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1616), .CK(clk), .RN(
n4820), .Q(FPMULT_Add_result[4]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1618), .CK(clk), .RN(
n4820), .Q(FPMULT_Add_result[2]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1620), .CK(clk), .RN(
n4820), .Q(FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1596), .CK(clk),
.RN(n4820), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n1638), .CK(clk),
.RN(n2201), .Q(FPMULT_Op_MY[12]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1637), .CK(clk),
.RN(n2201), .Q(FPMULT_Op_MY[11]), .QN(n2203) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1635), .CK(clk),
.RN(n2201), .Q(FPMULT_Op_MY[9]), .QN(n2213) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1633), .CK(clk),
.RN(n2201), .Q(FPMULT_Op_MY[7]), .QN(n2215) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n1565), .CK(clk),
.RN(n4794), .Q(FPMULT_P_Sgf[36]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n1557), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[28]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n1552), .CK(clk),
.RN(n4793), .Q(FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n1551), .CK(clk),
.RN(n4792), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n1550), .CK(clk),
.RN(n4796), .Q(FPMULT_P_Sgf[21]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n1548), .CK(clk),
.RN(n4793), .Q(FPMULT_P_Sgf[19]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n1547), .CK(clk),
.RN(n4803), .Q(FPMULT_P_Sgf[18]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n1546), .CK(clk),
.RN(n4796), .Q(FPMULT_P_Sgf[17]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n1544), .CK(clk),
.RN(n4793), .Q(FPMULT_P_Sgf[15]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n1543), .CK(clk),
.RN(n4805), .Q(FPMULT_P_Sgf[14]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n1542), .CK(clk),
.RN(n4796), .Q(FPMULT_P_Sgf[13]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n1541), .CK(clk),
.RN(n4809), .Q(FPMULT_P_Sgf[12]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n1539), .CK(clk),
.RN(n4795), .Q(FPMULT_P_Sgf[10]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n1538), .CK(clk),
.RN(n4816), .Q(FPMULT_P_Sgf[9]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n1537), .CK(clk),
.RN(n4813), .Q(FPMULT_P_Sgf[8]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n1536), .CK(clk),
.RN(n4802), .Q(FPMULT_P_Sgf[7]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n1535), .CK(clk),
.RN(n4810), .Q(FPMULT_P_Sgf[6]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n1534), .CK(clk),
.RN(n4809), .Q(FPMULT_P_Sgf[5]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n1533), .CK(clk),
.RN(n4795), .Q(FPMULT_P_Sgf[4]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n1532), .CK(clk),
.RN(n4816), .Q(FPMULT_P_Sgf[3]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n1531), .CK(clk),
.RN(n4813), .Q(FPMULT_P_Sgf[2]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n1530), .CK(clk),
.RN(n4802), .Q(FPMULT_P_Sgf[1]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n1529), .CK(clk),
.RN(n4806), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1523), .CK(
clk), .RN(n4822), .Q(FPMULT_Sgf_normalized_result[18]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1517), .CK(
clk), .RN(n4825), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1515), .CK(
clk), .RN(n4824), .Q(FPMULT_Sgf_normalized_result[10]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1513), .CK(
clk), .RN(n4826), .Q(FPMULT_Sgf_normalized_result[8]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1509), .CK(
clk), .RN(n4822), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n4598) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1576), .CK(clk), .RN(n4825), .Q(mult_result[31]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1584), .CK(clk), .RN(n4824), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1583), .CK(clk), .RN(n4826), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1582), .CK(clk), .RN(n4822), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1581), .CK(clk), .RN(n4825), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1580), .CK(clk), .RN(n4824), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1579), .CK(clk), .RN(n4826), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1578), .CK(clk), .RN(n4822), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1577), .CK(clk), .RN(n4825), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1504), .CK(clk), .RN(n4824), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1503), .CK(clk), .RN(n4826), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1502), .CK(clk), .RN(n4822), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1501), .CK(clk), .RN(n4825), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1500), .CK(clk), .RN(n4824), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1499), .CK(clk), .RN(n4826), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1498), .CK(clk), .RN(n4827), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1497), .CK(clk), .RN(n4827), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1496), .CK(clk), .RN(n4827), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1495), .CK(clk), .RN(n4827), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1494), .CK(clk), .RN(n4827), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1493), .CK(clk), .RN(n4827), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1492), .CK(clk), .RN(n4827), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1491), .CK(clk), .RN(n4827), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1490), .CK(clk), .RN(n4827), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1489), .CK(clk), .RN(n4827), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1488), .CK(clk), .RN(n4827), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1487), .CK(clk), .RN(n4827), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1486), .CK(clk), .RN(n2201), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1485), .CK(clk), .RN(n2201), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1484), .CK(clk), .RN(n2201), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1483), .CK(clk), .RN(n2201), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1481), .CK(clk), .RN(n4828), .Q(mult_result[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1478), .CK(clk), .RN(
n4781), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1477), .CK(clk), .RN(
n4775), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1476), .CK(clk), .RN(
n4771), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1474), .CK(clk), .RN(
n4770), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1460), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1459), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1458), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1456), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1455), .CK(clk), .RN(n4779),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1454), .CK(clk), .RN(
n4789), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n4765),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1451), .CK(clk), .RN(n4763),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1450), .CK(clk), .RN(n4780),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1449), .CK(clk), .RN(
n4789), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n4772),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(clk), .RN(n4786),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1445), .CK(clk), .RN(n4764),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1444), .CK(clk), .RN(
n4789), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n2267),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(clk), .RN(n4767),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1440), .CK(clk), .RN(n2931),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1439), .CK(clk), .RN(
n4789), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n2266),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1436), .CK(clk), .RN(n4784),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1435), .CK(clk), .RN(n2266),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1434), .CK(clk), .RN(
n4778), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n4786),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1431), .CK(clk), .RN(n4781),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1430), .CK(clk), .RN(n4763),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1429), .CK(clk), .RN(
n4761), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n4764),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1426), .CK(clk), .RN(n4769),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1425), .CK(clk), .RN(n4779),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1424), .CK(clk), .RN(
n4783), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n4767),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1421), .CK(clk), .RN(n4775),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1420), .CK(clk), .RN(n4771),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1419), .CK(clk), .RN(
n4773), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1416), .CK(clk), .RN(n4780),
.Q(FPADDSUB_DmP_EXP_EWSW[24]), .QN(n4707) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1415), .CK(clk), .RN(n4773),
.Q(FPADDSUB_DmP_EXP_EWSW[25]), .QN(n4706) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1414), .CK(clk), .RN(n4773),
.Q(FPADDSUB_DmP_EXP_EWSW[26]), .QN(n4715) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1412), .CK(clk), .RN(n4773), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1411), .CK(clk), .RN(n4787), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1409), .CK(clk), .RN(
n4762), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1407), .CK(clk), .RN(n4773),
.Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1406), .CK(clk), .RN(
n4773), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1404), .CK(clk), .RN(n4773),
.Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1403), .CK(clk), .RN(
n4773), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1401), .CK(clk), .RN(n4774),
.Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1400), .CK(clk), .RN(
n4774), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1398), .CK(clk), .RN(n4774),
.Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1397), .CK(clk), .RN(
n4774), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1395), .CK(clk), .RN(n4774),
.Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1394), .CK(clk), .RN(
n4774), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1392), .CK(clk), .RN(n4774),
.Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1391), .CK(clk), .RN(
n4774), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1389), .CK(clk), .RN(n4781),
.Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1388), .CK(clk), .RN(
n4763), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1386), .CK(clk), .RN(n4775),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1385), .CK(clk), .RN(
n4771), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]), .QN(n4692) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1383), .CK(clk), .RN(n4777),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1382), .CK(clk), .RN(
n4769), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]), .QN(n4691) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1380), .CK(clk), .RN(n4779),
.Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1379), .CK(clk), .RN(
n4780), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1377), .CK(clk), .RN(n4776),
.Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1376), .CK(clk), .RN(
n4776), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1374), .CK(clk), .RN(n4776),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1373), .CK(clk), .RN(
n4776), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1371), .CK(clk), .RN(n4776),
.Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1370), .CK(clk), .RN(
n4776), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1368), .CK(clk), .RN(n4776),
.Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1367), .CK(clk), .RN(
n4776), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1365), .CK(clk), .RN(n2931),
.Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1364), .CK(clk), .RN(
n2267), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n2266),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n4769), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1360), .CK(clk), .RN(n4781), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1359), .CK(clk), .RN(n4784),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1358), .CK(clk), .RN(n4775),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(
n4788), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n4771),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n4765), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1353), .CK(clk), .RN(n4777), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1330), .CK(clk), .RN(
n4789), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1328), .CK(clk), .RN(n2931),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(
n4772), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n4784),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n4763),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1324), .CK(clk), .RN(n4777),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1322), .CK(clk), .RN(
n4789), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1318), .CK(clk), .RN(
n4789), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1314), .CK(clk), .RN(
n4768), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1312), .CK(clk), .RN(n4779),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(
n4784), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n2266),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n4769),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1308), .CK(clk), .RN(n4771),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1305), .CK(clk), .RN(n4781),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(
n4763), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n4775),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n4779),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1301), .CK(clk), .RN(n4777),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1298), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(
n4782), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1294), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1291), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(
n4782), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1287), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1284), .CK(clk), .RN(n4783),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(
n4783), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]), .QN(n4694) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n4783),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n4783),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1280), .CK(clk), .RN(n4783),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1277), .CK(clk), .RN(n4783),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(
n4783), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n4783),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1273), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1271), .CK(clk), .RN(n4789),
.Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(
n4778), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]), .QN(n4693) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n4783),
.Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1267), .CK(clk), .RN(n4776),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n4773),
.Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n4764),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1263), .CK(clk), .RN(n4774),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n4766),
.Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1259), .CK(clk), .RN(n4773),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n4783),
.Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n4768),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1255), .CK(clk), .RN(n4774),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1251), .CK(clk), .RN(n4776),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n4786),
.Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n4764),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1247), .CK(clk), .RN(n4767),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n2931),
.Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n2266),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1243), .CK(clk), .RN(n4784),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n4772),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n4765),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1239), .CK(clk), .RN(n2267),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n4768),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n4788),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1235), .CK(clk), .RN(n4776),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1231), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n4787),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1227), .CK(clk), .RN(n4762),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1223), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1219), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1215), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n4769),
.Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n4767),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1211), .CK(clk), .RN(n4779),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n4763),
.Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n4764),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1207), .CK(clk), .RN(n4780),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_1_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_2_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_3_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_4_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_5_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_6_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_7_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_8_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_9_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_10_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_11_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_12_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[12]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_13_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[13]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_14_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[14]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_15_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[15]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_16_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[16]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_17_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[17]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_18_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[18]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_19_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[19]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_20_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[20]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_21_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[21]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_22_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[22]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_23_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[23]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_1_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_2_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_3_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_4_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_5_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_6_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_7_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_8_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_9_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_10_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_11_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_12_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[12]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_13_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[13]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_14_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[14]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_15_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[15]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_16_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[16]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_17_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[17]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_18_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[18]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_19_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[19]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_20_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[20]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_21_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[21]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_22_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[22]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_23_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[23]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_24_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N24), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[24]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_25_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N25), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[25]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_1_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_2_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_3_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_4_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_5_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_6_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_7_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_8_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_9_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_10_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_11_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_12_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[12]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_13_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[13]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_14_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[14]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_15_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[15]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_16_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[16]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_17_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[17]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_18_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[18]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_19_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[19]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_20_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[20]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_21_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[21]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_22_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[22]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_23_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[23]) );
CMPR32X2TS DP_OP_234J221_127_8543_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n4759), .C(DP_OP_234J221_127_8543_n22), .CO(DP_OP_234J221_127_8543_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_234J221_127_8543_U9 ( .A(DP_OP_234J221_127_8543_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J221_127_8543_n9), .CO(
DP_OP_234J221_127_8543_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J221_127_8543_U8 ( .A(DP_OP_234J221_127_8543_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J221_127_8543_n8), .CO(
DP_OP_234J221_127_8543_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J221_127_8543_U7 ( .A(DP_OP_234J221_127_8543_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J221_127_8543_n7), .CO(
DP_OP_234J221_127_8543_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J221_127_8543_U6 ( .A(DP_OP_234J221_127_8543_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J221_127_8543_n6), .CO(
DP_OP_234J221_127_8543_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J221_127_8543_U5 ( .A(DP_OP_234J221_127_8543_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J221_127_8543_n5), .CO(
DP_OP_234J221_127_8543_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J221_127_8543_U4 ( .A(DP_OP_234J221_127_8543_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J221_127_8543_n4), .CO(
DP_OP_234J221_127_8543_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J221_127_8543_U3 ( .A(DP_OP_234J221_127_8543_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J221_127_8543_n3), .CO(
DP_OP_234J221_127_8543_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_234J221_127_8543_U2 ( .A(n4759), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_234J221_127_8543_n2), .CO(DP_OP_234J221_127_8543_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_502_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n4609), .C(
intadd_502_CI), .CO(intadd_502_n3), .S(intadd_502_SUM_0_) );
CMPR32X2TS intadd_502_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(intadd_501_B_1_),
.C(intadd_502_n3), .CO(intadd_502_n2), .S(intadd_502_SUM_1_) );
CMPR32X2TS intadd_502_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n4559), .C(
intadd_502_n2), .CO(intadd_502_n1), .S(intadd_502_SUM_2_) );
CMPR32X2TS intadd_499_U26 ( .A(FPMULT_Sgf_operation_Result[0]), .B(
intadd_499_B_0_), .C(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .CO(
intadd_499_n25), .S(intadd_499_SUM_0_) );
CMPR32X2TS intadd_499_U25 ( .A(FPMULT_Sgf_operation_Result[1]), .B(
intadd_499_B_1_), .C(intadd_499_n25), .CO(intadd_499_n24), .S(
intadd_499_SUM_1_) );
CMPR32X2TS intadd_499_U24 ( .A(intadd_499_A_2_), .B(intadd_499_B_2_), .C(
intadd_499_n24), .CO(intadd_499_n23), .S(intadd_499_SUM_2_) );
CMPR32X2TS intadd_499_U23 ( .A(intadd_499_A_3_), .B(intadd_499_B_3_), .C(
intadd_499_n23), .CO(intadd_499_n22), .S(intadd_499_SUM_3_) );
CMPR32X2TS intadd_499_U22 ( .A(intadd_499_A_4_), .B(intadd_499_B_4_), .C(
intadd_499_n22), .CO(intadd_499_n21), .S(intadd_499_SUM_4_) );
CMPR32X2TS intadd_499_U21 ( .A(intadd_499_A_5_), .B(intadd_499_B_5_), .C(
intadd_499_n21), .CO(intadd_499_n20), .S(intadd_499_SUM_5_) );
CMPR32X2TS intadd_499_U20 ( .A(intadd_499_A_6_), .B(intadd_499_B_6_), .C(
intadd_499_n20), .CO(intadd_499_n19), .S(intadd_499_SUM_6_) );
CMPR32X2TS intadd_499_U19 ( .A(intadd_499_A_7_), .B(intadd_499_B_7_), .C(
intadd_499_n19), .CO(intadd_499_n18), .S(intadd_499_SUM_7_) );
CMPR32X2TS intadd_499_U18 ( .A(intadd_499_A_8_), .B(intadd_499_B_8_), .C(
intadd_499_n18), .CO(intadd_499_n17), .S(intadd_499_SUM_8_) );
CMPR32X2TS intadd_499_U17 ( .A(intadd_499_A_9_), .B(intadd_499_B_9_), .C(
intadd_499_n17), .CO(intadd_499_n16), .S(intadd_499_SUM_9_) );
CMPR32X2TS intadd_499_U16 ( .A(intadd_499_A_10_), .B(intadd_499_B_10_), .C(
intadd_499_n16), .CO(intadd_499_n15), .S(intadd_499_SUM_10_) );
CMPR32X2TS intadd_499_U15 ( .A(intadd_499_A_11_), .B(intadd_499_B_11_), .C(
intadd_499_n15), .CO(intadd_499_n14), .S(intadd_499_SUM_11_) );
CMPR32X2TS intadd_499_U14 ( .A(intadd_499_A_12_), .B(intadd_499_B_12_), .C(
intadd_499_n14), .CO(intadd_499_n13), .S(intadd_499_SUM_12_) );
CMPR32X2TS intadd_499_U13 ( .A(intadd_499_A_13_), .B(intadd_499_B_13_), .C(
intadd_499_n13), .CO(intadd_499_n12), .S(intadd_499_SUM_13_) );
CMPR32X2TS intadd_499_U12 ( .A(intadd_499_A_14_), .B(intadd_499_B_14_), .C(
intadd_499_n12), .CO(intadd_499_n11), .S(intadd_499_SUM_14_) );
CMPR32X2TS intadd_499_U11 ( .A(intadd_499_A_15_), .B(intadd_499_B_15_), .C(
intadd_499_n11), .CO(intadd_499_n10), .S(intadd_499_SUM_15_) );
CMPR32X2TS intadd_499_U10 ( .A(intadd_499_A_16_), .B(intadd_499_B_16_), .C(
intadd_499_n10), .CO(intadd_499_n9), .S(intadd_499_SUM_16_) );
CMPR32X2TS intadd_499_U9 ( .A(intadd_499_A_17_), .B(intadd_499_B_17_), .C(
intadd_499_n9), .CO(intadd_499_n8), .S(intadd_499_SUM_17_) );
CMPR32X2TS intadd_499_U8 ( .A(intadd_499_A_18_), .B(intadd_499_B_18_), .C(
intadd_499_n8), .CO(intadd_499_n7), .S(intadd_499_SUM_18_) );
CMPR32X2TS intadd_499_U7 ( .A(intadd_499_A_19_), .B(intadd_499_B_19_), .C(
intadd_499_n7), .CO(intadd_499_n6), .S(intadd_499_SUM_19_) );
CMPR32X2TS intadd_499_U6 ( .A(intadd_499_A_20_), .B(intadd_499_B_20_), .C(
intadd_499_n6), .CO(intadd_499_n5), .S(intadd_499_SUM_20_) );
CMPR32X2TS intadd_499_U5 ( .A(intadd_499_A_21_), .B(intadd_499_B_21_), .C(
intadd_499_n5), .CO(intadd_499_n4), .S(intadd_499_SUM_21_) );
CMPR32X2TS intadd_499_U4 ( .A(intadd_499_A_22_), .B(intadd_499_B_22_), .C(
intadd_499_n4), .CO(intadd_499_n3), .S(intadd_499_SUM_22_) );
CMPR32X2TS intadd_499_U3 ( .A(intadd_499_A_23_), .B(intadd_499_B_23_), .C(
intadd_499_n3), .CO(intadd_499_n2), .S(intadd_499_SUM_23_) );
CMPR32X2TS intadd_499_U2 ( .A(intadd_499_A_24_), .B(intadd_499_B_24_), .C(
intadd_499_n2), .CO(intadd_499_n1), .S(intadd_499_SUM_24_) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1180), .CK(clk), .RN(
n4788), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n4724) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1956), .CK(clk), .RN(
n4816), .Q(FPSENCOS_d_ff2_X[26]), .QN(n4722) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1957), .CK(clk), .RN(
n4817), .Q(FPSENCOS_d_ff2_X[25]), .QN(n4721) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1958), .CK(clk), .RN(
n4811), .Q(FPSENCOS_d_ff2_X[24]), .QN(n4720) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1955), .CK(clk), .RN(
n4795), .Q(FPSENCOS_d_ff2_X[27]), .QN(n4716) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1621), .CK(
clk), .RN(n4823), .Q(FPMULT_Sgf_normalized_result[23]), .QN(n4714) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1952), .CK(clk), .RN(
n4811), .Q(FPSENCOS_d_ff2_X[30]), .QN(n4713) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1514), .CK(
clk), .RN(n4824), .Q(FPMULT_Sgf_normalized_result[9]), .QN(n4712) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1520), .CK(
clk), .RN(n4825), .Q(FPMULT_Sgf_normalized_result[15]), .QN(n4711) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n4761),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n4710) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1505), .CK(
clk), .RN(n4826), .Q(FPMULT_Sgf_normalized_result[0]), .QN(n4709) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1953), .CK(clk), .RN(
n4811), .Q(FPSENCOS_d_ff2_X[29]), .QN(n4708) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2080), .CK(clk), .RN(n2928),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n4703) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1797), .CK(clk), .RN(n2267), .Q(FPADDSUB_Data_array_SWR[10]), .QN(n4701) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1525), .CK(
clk), .RN(n4822), .Q(FPMULT_Sgf_normalized_result[20]), .QN(n4690) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1935), .CK(clk), .RN(
n4780), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n4688) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1806), .CK(clk), .RN(n4767), .Q(FPADDSUB_Data_array_SWR[19]), .QN(n4686) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1805), .CK(clk), .RN(n4768), .Q(FPADDSUB_Data_array_SWR[18]), .QN(n4683) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1919), .CK(clk), .RN(
n4767), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n4681) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1924), .CK(clk), .RN(
n4771), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n4680) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1933), .CK(clk), .RN(
n4766), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n4679) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1929), .CK(clk), .RN(
n4786), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n4677) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1939), .CK(clk), .RN(
n4768), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n4676) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1921), .CK(clk), .RN(
n4769), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n4674) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1930), .CK(clk), .RN(
n4766), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n4672) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1940), .CK(clk), .RN(
n4768), .Q(FPADDSUB_intDX_EWSW[1]), .QN(n4671) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1922), .CK(clk), .RN(
n4777), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n4670) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1915), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n4668) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1917), .CK(clk), .RN(
n4761), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n4667) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1928), .CK(clk), .RN(
n2931), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n4666) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1920), .CK(clk), .RN(
n4786), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n4665) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1356), .CK(clk), .RN(
n4774), .Q(result_add_subt[31]), .QN(n4664) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n2931), .Q(result_add_subt[0]), .QN(n4663) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n4773), .Q(result_add_subt[18]), .QN(n4662) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n4773), .Q(result_add_subt[15]), .QN(n4661) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n4773), .Q(result_add_subt[22]), .QN(n4660) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n4783), .Q(result_add_subt[9]), .QN(n4659) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n4776), .Q(result_add_subt[11]), .QN(n4658) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n4776), .Q(result_add_subt[8]), .QN(n4657) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1218), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SFG[21]), .QN(n4656) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n4783), .Q(result_add_subt[5]), .QN(n4655) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n4764), .Q(result_add_subt[7]), .QN(n4654) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n4776), .Q(result_add_subt[14]), .QN(n4653) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n2266), .Q(result_add_subt[16]), .QN(n4652) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n2267), .Q(result_add_subt[6]), .QN(n4651) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n4774), .Q(result_add_subt[17]), .QN(n4650) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n4774), .Q(result_add_subt[20]), .QN(n4649) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n4774), .Q(result_add_subt[19]), .QN(n4648) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1363), .CK(clk), .RN(
n4765), .Q(result_add_subt[12]), .QN(n4647) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n4776), .Q(result_add_subt[10]), .QN(n4646) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n4784), .Q(result_add_subt[13]), .QN(n4645) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1813), .CK(clk), .RN(
n4779), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n4644) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1347), .CK(clk), .RN(
n4778), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]), .QN(n4642) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1226), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SFG[20]), .QN(n4640) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1345), .CK(clk), .RN(
n4778), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n4639) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1623), .CK(clk), .RN(n4822), .Q(
FPMULT_FSM_selector_B[0]), .QN(n4637) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1521), .CK(
clk), .RN(n4822), .Q(FPMULT_Sgf_normalized_result[16]), .QN(n4634) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1344), .CK(clk), .RN(
n4778), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n4633) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1320), .CK(clk), .RN(
n4781), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n4631) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1222), .CK(clk), .RN(n4785),
.Q(FPADDSUB_DMP_SFG[19]), .QN(n4630) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1692), .CK(clk), .RN(n4798),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n4624) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1331), .CK(clk), .RN(
n4779), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n4622) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1519), .CK(
clk), .RN(n4826), .Q(FPMULT_Sgf_normalized_result[14]), .QN(n4618) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1186), .CK(clk), .RN(
n4788), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n4607) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1187), .CK(clk), .RN(
n4788), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n4606) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1188), .CK(clk), .RN(
n4788), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n4605) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1242), .CK(clk), .RN(n4781),
.Q(FPADDSUB_DMP_SFG[13]), .QN(n4604) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1189), .CK(clk), .RN(
n4788), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n4603) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1266), .CK(clk), .RN(n4767),
.Q(FPADDSUB_DMP_SFG[12]), .QN(n4601) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1511), .CK(
clk), .RN(n4822), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n4600) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1193), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n4599) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1194), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n4597) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1195), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n4596) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1300), .CK(clk), .RN(n4780),
.Q(FPADDSUB_DMP_SFG[7]), .QN(n4595) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1234), .CK(clk), .RN(n4778),
.Q(FPADDSUB_DMP_SFG[4]), .QN(n4594) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1238), .CK(clk), .RN(n4761),
.Q(FPADDSUB_DMP_SFG[6]), .QN(n4593) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1272), .CK(clk), .RN(n4784),
.Q(FPADDSUB_DMP_SFG[5]), .QN(n4592) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1307), .CK(clk), .RN(n4763),
.Q(FPADDSUB_DMP_SFG[2]), .QN(n4591) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1286), .CK(clk), .RN(n4783),
.Q(FPADDSUB_DMP_SFG[1]), .QN(n4590) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1323), .CK(clk), .RN(n4775),
.Q(FPADDSUB_DMP_SFG[3]), .QN(n4589) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1203), .CK(clk), .RN(
n4763), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n4588) );
DFFRX2TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1954), .CK(clk), .RN(
n2929), .QN(n4584) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n2202),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n4583) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1916), .CK(clk), .RN(
n4761), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n4581) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1941), .CK(clk), .RN(
n4768), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n4580) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1923), .CK(clk), .RN(
n4786), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n4578) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1914), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n4577) );
DFFRX1TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2136), .CK(clk), .RN(n4803),
.Q(FPSENCOS_cont_var_out[1]), .QN(n4576) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1932), .CK(clk), .RN(
n4765), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n4574) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1927), .CK(clk), .RN(
n4766), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n4573) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1335), .CK(clk), .RN(
n2931), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n4572) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1321), .CK(clk), .RN(
n4769), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]), .QN(n4571) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1938), .CK(clk), .RN(
n4764), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n4569) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1926), .CK(clk), .RN(
n4777), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n4568) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1466), .CK(clk), .RN(
n4766), .Q(result_add_subt[30]), .QN(n4567) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1814), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n4566) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1341), .CK(clk), .RN(
n4778), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n4564) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1184), .CK(clk), .RN(
n4788), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n4561) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1346), .CK(clk), .RN(
n4778), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n4560) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1262), .CK(clk), .RN(n4788),
.Q(FPADDSUB_DMP_SFG[10]), .QN(n4555) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1279), .CK(clk), .RN(n4783),
.Q(FPADDSUB_DMP_SFG[9]), .QN(n4554) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1250), .CK(clk), .RN(n4775),
.Q(FPADDSUB_DMP_SFG[8]), .QN(n4553) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1199), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n4552) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1200), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n4551) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n4816),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n4550) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1471), .CK(clk), .RN(
n4778), .Q(result_add_subt[25]), .QN(n4548) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n4772), .Q(result_add_subt[4]), .QN(n4547) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n4774), .Q(result_add_subt[21]), .QN(n4546) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1343), .CK(clk), .RN(
n4778), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n4545) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1473), .CK(clk), .RN(
n4788), .Q(result_add_subt[23]), .QN(n4544) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1348), .CK(clk), .RN(
n4778), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n4541) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1191), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n4539) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1467), .CK(clk), .RN(
n4773), .Q(result_add_subt[29]), .QN(n4538) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1468), .CK(clk), .RN(
n4783), .Q(result_add_subt[28]), .QN(n4537) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1469), .CK(clk), .RN(
n4761), .Q(result_add_subt[27]), .QN(n4536) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1470), .CK(clk), .RN(
n4766), .Q(result_add_subt[26]), .QN(n4535) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1472), .CK(clk), .RN(
n4789), .Q(result_add_subt[24]), .QN(n4534) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n4782), .Q(result_add_subt[1]), .QN(n4533) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n4771), .Q(result_add_subt[2]), .QN(n4532) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n4772), .Q(result_add_subt[3]), .QN(n4531) );
CMPR42X1TS DP_OP_454J221_123_2743_U75 ( .A(DP_OP_454J221_123_2743_n240), .B(
DP_OP_454J221_123_2743_n227), .C(DP_OP_454J221_123_2743_n148), .D(
DP_OP_454J221_123_2743_n252), .ICI(DP_OP_454J221_123_2743_n214), .S(
DP_OP_454J221_123_2743_n145), .ICO(DP_OP_454J221_123_2743_n143), .CO(
DP_OP_454J221_123_2743_n144) );
CMPR42X1TS DP_OP_454J221_123_2743_U73 ( .A(DP_OP_454J221_123_2743_n143), .B(
DP_OP_454J221_123_2743_n251), .C(DP_OP_454J221_123_2743_n142), .D(
DP_OP_454J221_123_2743_n213), .ICI(DP_OP_454J221_123_2743_n156), .S(
DP_OP_454J221_123_2743_n140), .ICO(DP_OP_454J221_123_2743_n138), .CO(
DP_OP_454J221_123_2743_n139) );
CMPR42X1TS DP_OP_454J221_123_2743_U71 ( .A(DP_OP_454J221_123_2743_n212), .B(
DP_OP_454J221_123_2743_n137), .C(DP_OP_454J221_123_2743_n138), .D(
DP_OP_454J221_123_2743_n250), .ICI(DP_OP_454J221_123_2743_n200), .S(
DP_OP_454J221_123_2743_n135), .ICO(DP_OP_454J221_123_2743_n133), .CO(
DP_OP_454J221_123_2743_n134) );
CMPR42X1TS DP_OP_454J221_123_2743_U68 ( .A(DP_OP_454J221_123_2743_n133), .B(
DP_OP_454J221_123_2743_n249), .C(DP_OP_454J221_123_2743_n130), .D(
DP_OP_454J221_123_2743_n199), .ICI(DP_OP_454J221_123_2743_n155), .S(
DP_OP_454J221_123_2743_n128), .ICO(DP_OP_454J221_123_2743_n126), .CO(
DP_OP_454J221_123_2743_n127) );
CMPR42X1TS DP_OP_454J221_123_2743_U67 ( .A(DP_OP_454J221_123_2743_n223), .B(
DP_OP_454J221_123_2743_n210), .C(DP_OP_454J221_123_2743_n131), .D(
DP_OP_454J221_123_2743_n236), .ICI(DP_OP_454J221_123_2743_n129), .S(
DP_OP_454J221_123_2743_n125), .ICO(DP_OP_454J221_123_2743_n123), .CO(
DP_OP_454J221_123_2743_n124) );
CMPR42X1TS DP_OP_454J221_123_2743_U66 ( .A(DP_OP_454J221_123_2743_n198), .B(
DP_OP_454J221_123_2743_n248), .C(DP_OP_454J221_123_2743_n187), .D(
DP_OP_454J221_123_2743_n126), .ICI(DP_OP_454J221_123_2743_n125), .S(
DP_OP_454J221_123_2743_n122), .ICO(DP_OP_454J221_123_2743_n120), .CO(
DP_OP_454J221_123_2743_n121) );
CMPR42X1TS DP_OP_454J221_123_2743_U64 ( .A(DP_OP_454J221_123_2743_n123), .B(
DP_OP_454J221_123_2743_n235), .C(DP_OP_454J221_123_2743_n119), .D(
DP_OP_454J221_123_2743_n197), .ICI(DP_OP_454J221_123_2743_n124), .S(
DP_OP_454J221_123_2743_n117), .ICO(DP_OP_454J221_123_2743_n115), .CO(
DP_OP_454J221_123_2743_n116) );
CMPR42X1TS DP_OP_454J221_123_2743_U63 ( .A(DP_OP_454J221_123_2743_n120), .B(
DP_OP_454J221_123_2743_n117), .C(DP_OP_454J221_123_2743_n247), .D(
DP_OP_454J221_123_2743_n121), .ICI(DP_OP_454J221_123_2743_n186), .S(
DP_OP_454J221_123_2743_n114), .ICO(DP_OP_454J221_123_2743_n112), .CO(
DP_OP_454J221_123_2743_n113) );
CMPR42X1TS DP_OP_454J221_123_2743_U61 ( .A(DP_OP_454J221_123_2743_n196), .B(
DP_OP_454J221_123_2743_n111), .C(DP_OP_454J221_123_2743_n115), .D(
DP_OP_454J221_123_2743_n234), .ICI(DP_OP_454J221_123_2743_n116), .S(
DP_OP_454J221_123_2743_n109), .ICO(DP_OP_454J221_123_2743_n107), .CO(
DP_OP_454J221_123_2743_n108) );
CMPR42X1TS DP_OP_454J221_123_2743_U60 ( .A(DP_OP_454J221_123_2743_n246), .B(
DP_OP_454J221_123_2743_n172), .C(DP_OP_454J221_123_2743_n185), .D(
DP_OP_454J221_123_2743_n109), .ICI(DP_OP_454J221_123_2743_n112), .S(
DP_OP_454J221_123_2743_n106), .ICO(DP_OP_454J221_123_2743_n104), .CO(
DP_OP_454J221_123_2743_n105) );
CMPR42X1TS DP_OP_454J221_123_2743_U58 ( .A(DP_OP_454J221_123_2743_n195), .B(
DP_OP_454J221_123_2743_n245), .C(DP_OP_454J221_123_2743_n103), .D(
DP_OP_454J221_123_2743_n107), .ICI(DP_OP_454J221_123_2743_n233), .S(
DP_OP_454J221_123_2743_n101), .ICO(DP_OP_454J221_123_2743_n99), .CO(
DP_OP_454J221_123_2743_n100) );
CMPR42X1TS DP_OP_454J221_123_2743_U57 ( .A(DP_OP_454J221_123_2743_n108), .B(
DP_OP_454J221_123_2743_n171), .C(DP_OP_454J221_123_2743_n184), .D(
DP_OP_454J221_123_2743_n101), .ICI(DP_OP_454J221_123_2743_n104), .S(
DP_OP_454J221_123_2743_n98), .ICO(DP_OP_454J221_123_2743_n96), .CO(
DP_OP_454J221_123_2743_n97) );
CMPR42X1TS DP_OP_454J221_123_2743_U54 ( .A(DP_OP_454J221_123_2743_n219), .B(
DP_OP_454J221_123_2743_n102), .C(DP_OP_454J221_123_2743_n94), .D(
DP_OP_454J221_123_2743_n99), .ICI(DP_OP_454J221_123_2743_n232), .S(
DP_OP_454J221_123_2743_n92), .ICO(DP_OP_454J221_123_2743_n90), .CO(
DP_OP_454J221_123_2743_n91) );
CMPR42X1TS DP_OP_454J221_123_2743_U53 ( .A(DP_OP_454J221_123_2743_n170), .B(
DP_OP_454J221_123_2743_n183), .C(DP_OP_454J221_123_2743_n100), .D(
DP_OP_454J221_123_2743_n96), .ICI(DP_OP_454J221_123_2743_n92), .S(
DP_OP_454J221_123_2743_n89), .ICO(DP_OP_454J221_123_2743_n87), .CO(
DP_OP_454J221_123_2743_n88) );
CMPR42X1TS DP_OP_454J221_123_2743_U50 ( .A(DP_OP_454J221_123_2743_n231), .B(
DP_OP_454J221_123_2743_n93), .C(DP_OP_454J221_123_2743_n84), .D(
DP_OP_454J221_123_2743_n90), .ICI(DP_OP_454J221_123_2743_n218), .S(
DP_OP_454J221_123_2743_n82), .ICO(DP_OP_454J221_123_2743_n80), .CO(
DP_OP_454J221_123_2743_n81) );
CMPR42X1TS DP_OP_454J221_123_2743_U49 ( .A(DP_OP_454J221_123_2743_n169), .B(
DP_OP_454J221_123_2743_n182), .C(DP_OP_454J221_123_2743_n91), .D(
DP_OP_454J221_123_2743_n87), .ICI(DP_OP_454J221_123_2743_n82), .S(
DP_OP_454J221_123_2743_n79), .ICO(DP_OP_454J221_123_2743_n77), .CO(
DP_OP_454J221_123_2743_n78) );
CMPR42X1TS DP_OP_454J221_123_2743_U47 ( .A(DP_OP_454J221_123_2743_n204), .B(
DP_OP_454J221_123_2743_n83), .C(DP_OP_454J221_123_2743_n76), .D(
DP_OP_454J221_123_2743_n80), .ICI(DP_OP_454J221_123_2743_n217), .S(
DP_OP_454J221_123_2743_n74), .ICO(DP_OP_454J221_123_2743_n72), .CO(
DP_OP_454J221_123_2743_n73) );
CMPR42X1TS DP_OP_454J221_123_2743_U46 ( .A(DP_OP_454J221_123_2743_n168), .B(
DP_OP_454J221_123_2743_n181), .C(DP_OP_454J221_123_2743_n81), .D(
DP_OP_454J221_123_2743_n74), .ICI(DP_OP_454J221_123_2743_n77), .S(
DP_OP_454J221_123_2743_n71), .ICO(DP_OP_454J221_123_2743_n69), .CO(
DP_OP_454J221_123_2743_n70) );
CMPR42X1TS DP_OP_454J221_123_2743_U44 ( .A(DP_OP_454J221_123_2743_n68), .B(
DP_OP_454J221_123_2743_n216), .C(DP_OP_454J221_123_2743_n75), .D(
DP_OP_454J221_123_2743_n72), .ICI(DP_OP_454J221_123_2743_n203), .S(
DP_OP_454J221_123_2743_n66), .ICO(DP_OP_454J221_123_2743_n64), .CO(
DP_OP_454J221_123_2743_n65) );
CMPR42X1TS DP_OP_454J221_123_2743_U43 ( .A(DP_OP_454J221_123_2743_n167), .B(
DP_OP_454J221_123_2743_n180), .C(DP_OP_454J221_123_2743_n73), .D(
DP_OP_454J221_123_2743_n66), .ICI(DP_OP_454J221_123_2743_n69), .S(
DP_OP_454J221_123_2743_n63), .ICO(DP_OP_454J221_123_2743_n61), .CO(
DP_OP_454J221_123_2743_n62) );
CMPR42X1TS DP_OP_454J221_123_2743_U42 ( .A(DP_OP_454J221_123_2743_n215), .B(
DP_OP_454J221_123_2743_n67), .C(DP_OP_454J221_123_2743_n191), .D(
DP_OP_454J221_123_2743_n64), .ICI(DP_OP_454J221_123_2743_n202), .S(
DP_OP_454J221_123_2743_n60), .ICO(DP_OP_454J221_123_2743_n58), .CO(
DP_OP_454J221_123_2743_n59) );
CMPR42X1TS DP_OP_454J221_123_2743_U41 ( .A(DP_OP_454J221_123_2743_n166), .B(
DP_OP_454J221_123_2743_n179), .C(DP_OP_454J221_123_2743_n65), .D(
DP_OP_454J221_123_2743_n60), .ICI(DP_OP_454J221_123_2743_n61), .S(
DP_OP_454J221_123_2743_n57), .ICO(DP_OP_454J221_123_2743_n55), .CO(
DP_OP_454J221_123_2743_n56) );
CMPR42X1TS DP_OP_454J221_123_2743_U38 ( .A(DP_OP_454J221_123_2743_n165), .B(
DP_OP_454J221_123_2743_n178), .C(DP_OP_454J221_123_2743_n52), .D(
DP_OP_454J221_123_2743_n59), .ICI(DP_OP_454J221_123_2743_n55), .S(
DP_OP_454J221_123_2743_n50), .ICO(DP_OP_454J221_123_2743_n48), .CO(
DP_OP_454J221_123_2743_n49) );
CMPR42X1TS DP_OP_454J221_123_2743_U36 ( .A(DP_OP_454J221_123_2743_n164), .B(
DP_OP_454J221_123_2743_n177), .C(DP_OP_454J221_123_2743_n51), .D(
DP_OP_454J221_123_2743_n47), .ICI(DP_OP_454J221_123_2743_n48), .S(
DP_OP_454J221_123_2743_n45), .ICO(DP_OP_454J221_123_2743_n43), .CO(
DP_OP_454J221_123_2743_n44) );
CMPR42X1TS DP_OP_454J221_123_2743_U34 ( .A(DP_OP_454J221_123_2743_n42), .B(
DP_OP_454J221_123_2743_n163), .C(DP_OP_454J221_123_2743_n176), .D(
DP_OP_454J221_123_2743_n46), .ICI(DP_OP_454J221_123_2743_n43), .S(
DP_OP_454J221_123_2743_n40), .ICO(DP_OP_454J221_123_2743_n38), .CO(
DP_OP_454J221_123_2743_n39) );
CMPR42X1TS DP_OP_454J221_123_2743_U33 ( .A(DP_OP_454J221_123_2743_n188), .B(
DP_OP_454J221_123_2743_n41), .C(DP_OP_454J221_123_2743_n162), .D(
DP_OP_454J221_123_2743_n175), .ICI(DP_OP_454J221_123_2743_n38), .S(
DP_OP_454J221_123_2743_n37), .ICO(DP_OP_454J221_123_2743_n35), .CO(
DP_OP_454J221_123_2743_n36) );
CMPR42X1TS mult_x_254_U69 ( .A(mult_x_254_n196), .B(mult_x_254_n232), .C(
mult_x_254_n220), .D(mult_x_254_n208), .ICI(mult_x_254_n136), .S(
mult_x_254_n133), .ICO(mult_x_254_n131), .CO(mult_x_254_n132) );
CMPR42X1TS mult_x_254_U67 ( .A(mult_x_254_n219), .B(mult_x_254_n195), .C(
mult_x_254_n207), .D(mult_x_254_n131), .ICI(mult_x_254_n130), .S(
mult_x_254_n128), .ICO(mult_x_254_n126), .CO(mult_x_254_n127) );
CMPR42X1TS mult_x_254_U65 ( .A(mult_x_254_n206), .B(mult_x_254_n194), .C(
mult_x_254_n129), .D(mult_x_254_n126), .ICI(mult_x_254_n125), .S(
mult_x_254_n123), .ICO(mult_x_254_n121), .CO(mult_x_254_n122) );
CMPR42X1TS mult_x_254_U62 ( .A(mult_x_254_n205), .B(mult_x_254_n124), .C(
mult_x_254_n120), .D(mult_x_254_n118), .ICI(mult_x_254_n121), .S(
mult_x_254_n116), .ICO(mult_x_254_n114), .CO(mult_x_254_n115) );
CMPR42X1TS mult_x_254_U61 ( .A(mult_x_254_n168), .B(mult_x_254_n228), .C(
mult_x_254_n216), .D(mult_x_254_n204), .ICI(mult_x_254_n180), .S(
mult_x_254_n113), .ICO(mult_x_254_n111), .CO(mult_x_254_n112) );
CMPR42X1TS mult_x_254_U60 ( .A(mult_x_254_n192), .B(mult_x_254_n119), .C(
mult_x_254_n117), .D(mult_x_254_n114), .ICI(mult_x_254_n113), .S(
mult_x_254_n110), .ICO(mult_x_254_n108), .CO(mult_x_254_n109) );
CMPR42X1TS mult_x_254_U58 ( .A(mult_x_254_n215), .B(mult_x_254_n167), .C(
mult_x_254_n203), .D(mult_x_254_n179), .ICI(mult_x_254_n107), .S(
mult_x_254_n105), .ICO(mult_x_254_n103), .CO(mult_x_254_n104) );
CMPR42X1TS mult_x_254_U57 ( .A(mult_x_254_n191), .B(mult_x_254_n111), .C(
mult_x_254_n108), .D(mult_x_254_n112), .ICI(mult_x_254_n105), .S(
mult_x_254_n102), .ICO(mult_x_254_n100), .CO(mult_x_254_n101) );
CMPR42X1TS mult_x_254_U55 ( .A(mult_x_254_n202), .B(mult_x_254_n166), .C(
mult_x_254_n190), .D(mult_x_254_n178), .ICI(mult_x_254_n99), .S(
mult_x_254_n97), .ICO(mult_x_254_n95), .CO(mult_x_254_n96) );
CMPR42X1TS mult_x_254_U54 ( .A(mult_x_254_n106), .B(mult_x_254_n103), .C(
mult_x_254_n104), .D(mult_x_254_n97), .ICI(mult_x_254_n100), .S(
mult_x_254_n94), .ICO(mult_x_254_n92), .CO(mult_x_254_n93) );
CMPR42X1TS mult_x_254_U51 ( .A(mult_x_254_n189), .B(mult_x_254_n165), .C(
mult_x_254_n213), .D(n4530), .ICI(mult_x_254_n90), .S(mult_x_254_n88),
.ICO(mult_x_254_n86), .CO(mult_x_254_n87) );
CMPR42X1TS mult_x_254_U50 ( .A(mult_x_254_n95), .B(mult_x_254_n98), .C(
mult_x_254_n96), .D(mult_x_254_n88), .ICI(mult_x_254_n92), .S(
mult_x_254_n85), .ICO(mult_x_254_n83), .CO(mult_x_254_n84) );
CMPR42X1TS mult_x_254_U47 ( .A(mult_x_254_n176), .B(mult_x_254_n212), .C(
mult_x_254_n200), .D(mult_x_254_n164), .ICI(mult_x_254_n89), .S(
mult_x_254_n78), .ICO(mult_x_254_n76), .CO(mult_x_254_n77) );
CMPR42X1TS mult_x_254_U46 ( .A(mult_x_254_n86), .B(mult_x_254_n80), .C(
mult_x_254_n87), .D(mult_x_254_n78), .ICI(mult_x_254_n83), .S(
mult_x_254_n75), .ICO(mult_x_254_n73), .CO(mult_x_254_n74) );
CMPR42X1TS mult_x_254_U44 ( .A(mult_x_254_n175), .B(mult_x_254_n163), .C(
mult_x_254_n199), .D(mult_x_254_n211), .ICI(mult_x_254_n72), .S(
mult_x_254_n70), .ICO(mult_x_254_n68), .CO(mult_x_254_n69) );
CMPR42X1TS mult_x_254_U43 ( .A(mult_x_254_n76), .B(mult_x_254_n79), .C(
mult_x_254_n77), .D(mult_x_254_n70), .ICI(mult_x_254_n73), .S(
mult_x_254_n67), .ICO(mult_x_254_n65), .CO(mult_x_254_n66) );
CMPR42X1TS mult_x_254_U41 ( .A(mult_x_254_n64), .B(mult_x_254_n174), .C(
mult_x_254_n186), .D(mult_x_254_n162), .ICI(mult_x_254_n198), .S(
mult_x_254_n62), .ICO(mult_x_254_n60), .CO(mult_x_254_n61) );
CMPR42X1TS mult_x_254_U40 ( .A(mult_x_254_n68), .B(mult_x_254_n71), .C(
mult_x_254_n69), .D(mult_x_254_n62), .ICI(mult_x_254_n65), .S(
mult_x_254_n59), .ICO(mult_x_254_n57), .CO(mult_x_254_n58) );
CMPR42X1TS mult_x_254_U39 ( .A(mult_x_254_n63), .B(mult_x_254_n151), .C(
mult_x_254_n185), .D(mult_x_254_n173), .ICI(mult_x_254_n161), .S(
mult_x_254_n56), .ICO(mult_x_254_n54), .CO(mult_x_254_n55) );
CMPR42X1TS mult_x_254_U38 ( .A(mult_x_254_n197), .B(mult_x_254_n60), .C(
mult_x_254_n61), .D(mult_x_254_n56), .ICI(mult_x_254_n57), .S(
mult_x_254_n53), .ICO(mult_x_254_n51), .CO(mult_x_254_n52) );
CMPR42X1TS mult_x_254_U35 ( .A(mult_x_254_n160), .B(mult_x_254_n54), .C(
mult_x_254_n48), .D(mult_x_254_n55), .ICI(mult_x_254_n51), .S(
mult_x_254_n46), .ICO(mult_x_254_n44), .CO(mult_x_254_n45) );
CMPR42X1TS mult_x_254_U33 ( .A(mult_x_254_n159), .B(mult_x_254_n183), .C(
mult_x_254_n43), .D(mult_x_254_n47), .ICI(mult_x_254_n44), .S(
mult_x_254_n41), .ICO(mult_x_254_n39), .CO(mult_x_254_n40) );
CMPR42X1TS mult_x_254_U31 ( .A(mult_x_254_n38), .B(mult_x_254_n170), .C(
mult_x_254_n158), .D(mult_x_254_n42), .ICI(mult_x_254_n39), .S(
mult_x_254_n36), .ICO(mult_x_254_n34), .CO(mult_x_254_n35) );
CMPR42X1TS mult_x_254_U30 ( .A(mult_x_254_n37), .B(mult_x_254_n149), .C(
mult_x_254_n157), .D(mult_x_254_n169), .ICI(mult_x_254_n34), .S(
mult_x_254_n33), .ICO(mult_x_254_n31), .CO(mult_x_254_n32) );
CMPR42X1TS mult_x_219_U69 ( .A(mult_x_219_n190), .B(mult_x_219_n226), .C(
mult_x_219_n214), .D(mult_x_219_n202), .ICI(mult_x_219_n136), .S(
mult_x_219_n133), .ICO(mult_x_219_n131), .CO(mult_x_219_n132) );
CMPR42X1TS mult_x_219_U67 ( .A(mult_x_219_n213), .B(mult_x_219_n189), .C(
mult_x_219_n201), .D(mult_x_219_n131), .ICI(mult_x_219_n130), .S(
mult_x_219_n128), .ICO(mult_x_219_n126), .CO(mult_x_219_n127) );
CMPR42X1TS mult_x_219_U65 ( .A(mult_x_219_n200), .B(mult_x_219_n188), .C(
mult_x_219_n129), .D(mult_x_219_n126), .ICI(mult_x_219_n125), .S(
mult_x_219_n123), .ICO(mult_x_219_n121), .CO(mult_x_219_n122) );
CMPR42X1TS mult_x_219_U62 ( .A(mult_x_219_n199), .B(mult_x_219_n124), .C(
mult_x_219_n120), .D(mult_x_219_n118), .ICI(mult_x_219_n121), .S(
mult_x_219_n116), .ICO(mult_x_219_n114), .CO(mult_x_219_n115) );
CMPR42X1TS mult_x_219_U61 ( .A(mult_x_219_n162), .B(mult_x_219_n222), .C(
mult_x_219_n210), .D(mult_x_219_n198), .ICI(mult_x_219_n174), .S(
mult_x_219_n113), .ICO(mult_x_219_n111), .CO(mult_x_219_n112) );
CMPR42X1TS mult_x_219_U60 ( .A(mult_x_219_n186), .B(mult_x_219_n119), .C(
mult_x_219_n117), .D(mult_x_219_n114), .ICI(mult_x_219_n113), .S(
mult_x_219_n110), .ICO(mult_x_219_n108), .CO(mult_x_219_n109) );
CMPR42X1TS mult_x_219_U58 ( .A(mult_x_219_n209), .B(mult_x_219_n161), .C(
mult_x_219_n197), .D(mult_x_219_n173), .ICI(mult_x_219_n107), .S(
mult_x_219_n105), .ICO(mult_x_219_n103), .CO(mult_x_219_n104) );
CMPR42X1TS mult_x_219_U57 ( .A(mult_x_219_n185), .B(mult_x_219_n111), .C(
mult_x_219_n108), .D(mult_x_219_n112), .ICI(mult_x_219_n105), .S(
mult_x_219_n102), .ICO(mult_x_219_n100), .CO(mult_x_219_n101) );
CMPR42X1TS mult_x_219_U55 ( .A(mult_x_219_n196), .B(mult_x_219_n160), .C(
mult_x_219_n184), .D(mult_x_219_n172), .ICI(mult_x_219_n99), .S(
mult_x_219_n97), .ICO(mult_x_219_n95), .CO(mult_x_219_n96) );
CMPR42X1TS mult_x_219_U54 ( .A(mult_x_219_n106), .B(mult_x_219_n103), .C(
mult_x_219_n104), .D(mult_x_219_n97), .ICI(mult_x_219_n100), .S(
mult_x_219_n94), .ICO(mult_x_219_n92), .CO(mult_x_219_n93) );
CMPR42X1TS mult_x_219_U51 ( .A(mult_x_219_n183), .B(mult_x_219_n159), .C(
mult_x_219_n207), .D(n2273), .ICI(mult_x_219_n90), .S(mult_x_219_n88),
.ICO(mult_x_219_n86), .CO(mult_x_219_n87) );
CMPR42X1TS mult_x_219_U50 ( .A(mult_x_219_n95), .B(mult_x_219_n98), .C(
mult_x_219_n96), .D(mult_x_219_n88), .ICI(mult_x_219_n92), .S(
mult_x_219_n85), .ICO(mult_x_219_n83), .CO(mult_x_219_n84) );
CMPR42X1TS mult_x_219_U47 ( .A(mult_x_219_n170), .B(mult_x_219_n206), .C(
mult_x_219_n194), .D(mult_x_219_n158), .ICI(mult_x_219_n89), .S(
mult_x_219_n78), .ICO(mult_x_219_n76), .CO(mult_x_219_n77) );
CMPR42X1TS mult_x_219_U46 ( .A(mult_x_219_n86), .B(mult_x_219_n80), .C(
mult_x_219_n87), .D(mult_x_219_n78), .ICI(mult_x_219_n83), .S(
mult_x_219_n75), .ICO(mult_x_219_n73), .CO(mult_x_219_n74) );
CMPR42X1TS mult_x_219_U44 ( .A(mult_x_219_n169), .B(mult_x_219_n157), .C(
mult_x_219_n193), .D(mult_x_219_n205), .ICI(mult_x_219_n72), .S(
mult_x_219_n70), .ICO(mult_x_219_n68), .CO(mult_x_219_n69) );
CMPR42X1TS mult_x_219_U43 ( .A(mult_x_219_n76), .B(mult_x_219_n79), .C(
mult_x_219_n77), .D(mult_x_219_n70), .ICI(mult_x_219_n73), .S(
mult_x_219_n67), .ICO(mult_x_219_n65), .CO(mult_x_219_n66) );
CMPR42X1TS mult_x_219_U41 ( .A(n2304), .B(mult_x_219_n168), .C(
mult_x_219_n180), .D(mult_x_219_n156), .ICI(mult_x_219_n192), .S(
mult_x_219_n62), .ICO(mult_x_219_n60), .CO(mult_x_219_n61) );
CMPR42X1TS mult_x_219_U40 ( .A(mult_x_219_n68), .B(mult_x_219_n71), .C(
mult_x_219_n69), .D(mult_x_219_n62), .ICI(mult_x_219_n65), .S(
mult_x_219_n59), .ICO(mult_x_219_n57), .CO(mult_x_219_n58) );
CMPR42X1TS mult_x_219_U39 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[17]), .C(
mult_x_219_n179), .D(mult_x_219_n167), .ICI(mult_x_219_n155), .S(
mult_x_219_n56), .ICO(mult_x_219_n54), .CO(mult_x_219_n55) );
CMPR42X1TS mult_x_219_U38 ( .A(mult_x_219_n191), .B(mult_x_219_n60), .C(
mult_x_219_n61), .D(mult_x_219_n56), .ICI(mult_x_219_n57), .S(
mult_x_219_n53), .ICO(mult_x_219_n51), .CO(mult_x_219_n52) );
CMPR42X1TS mult_x_219_U35 ( .A(mult_x_219_n154), .B(mult_x_219_n54), .C(
mult_x_219_n48), .D(mult_x_219_n55), .ICI(mult_x_219_n51), .S(
mult_x_219_n46), .ICO(mult_x_219_n44), .CO(mult_x_219_n45) );
CMPR42X1TS mult_x_219_U33 ( .A(mult_x_219_n153), .B(mult_x_219_n177), .C(
mult_x_219_n43), .D(mult_x_219_n47), .ICI(mult_x_219_n44), .S(
mult_x_219_n41), .ICO(mult_x_219_n39), .CO(mult_x_219_n40) );
CMPR42X1TS mult_x_219_U31 ( .A(n2217), .B(mult_x_219_n164), .C(
mult_x_219_n152), .D(mult_x_219_n42), .ICI(mult_x_219_n39), .S(
mult_x_219_n36), .ICO(mult_x_219_n34), .CO(mult_x_219_n35) );
CMPR42X1TS mult_x_219_U30 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[21]), .C(
mult_x_219_n151), .D(mult_x_219_n163), .ICI(mult_x_219_n34), .S(
mult_x_219_n33), .ICO(mult_x_219_n31), .CO(mult_x_219_n32) );
DFFSX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n2226), .CK(clk),
.SN(n4828), .Q(n4529), .QN(FPMULT_Op_MX[11]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2142), .CK(clk), .RN(
n2267), .Q(n4829), .QN(n4704) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1689), .CK(clk), .RN(n4818), .Q(
FPMULT_FSM_selector_A), .QN(n4705) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1206), .CK(clk), .RN(n2931),
.Q(FPADDSUB_DMP_SFG[22]), .QN(n4695) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1622), .CK(clk), .RN(n4826), .Q(
FPMULT_FSM_selector_B[1]), .QN(n4641) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2138), .CK(clk), .RN(n4799),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n4559) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1190), .CK(clk), .RN(
n4788), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n4540) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2077), .CK(clk), .RN(
n4765), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n4623) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1691), .CK(clk), .RN(n4803),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n4614) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1690), .CK(clk), .RN(n4806),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n4610) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1693), .CK(clk), .RN(n4805),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n4557) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1336), .CK(clk), .RN(
n2267), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]), .QN(n4626) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1925), .CK(clk), .RN(
n4781), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n4673) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1918), .CK(clk), .RN(
n4761), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n4570) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1821), .CK(clk), .RN(
n4779), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n4612) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1824), .CK(clk), .RN(
n4763), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n4565) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1825), .CK(clk), .RN(
n4764), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n4643) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1829), .CK(clk), .RN(
n4766), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n4608) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1830), .CK(clk), .RN(
n4775), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n4629) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1832), .CK(clk), .RN(
n4766), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n4619) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1840), .CK(clk), .RN(
n4784), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n4611) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1931), .CK(clk), .RN(
n4766), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n4678) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1934), .CK(clk), .RN(
n4768), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n4579) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1937), .CK(clk), .RN(
n4771), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n4575) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1936), .CK(clk), .RN(
n4775), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n4675) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1823), .CK(clk), .RN(
n4764), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n4625) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1826), .CK(clk), .RN(
n4780), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n4635) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1828), .CK(clk), .RN(
n4763), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n4558) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1842), .CK(clk), .RN(
n4768), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n4615) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1817), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n4627) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1818), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n4620) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1820), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n4562) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1822), .CK(clk), .RN(
n4780), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n4628) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1837), .CK(clk), .RN(
n4777), .Q(FPADDSUB_intDY_EWSW[6]), .QN(n4689) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1835), .CK(clk), .RN(
n4769), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n4636) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1831), .CK(clk), .RN(
n4766), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n4613) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1333), .CK(clk), .RN(
n2266), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n4638) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1317), .CK(clk), .RN(
n4769), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n4563) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1316), .CK(clk), .RN(
n4786), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]), .QN(n4687) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_0_ ( .D(FPMULT_Op_MY[0]),
.RN(FPMULT_Op_MX[0]), .CK(clk), .Q(FPMULT_Sgf_operation_Result[0]) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_0_ ( .D(
DP_OP_454J221_123_2743_n367), .RN(DP_OP_454J221_123_2743_n453), .CK(
clk), .QN(intadd_499_B_0_) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_0_ ( .D(n2268), .RN(
FPMULT_Op_MX[12]), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[0]),
.QN(n4836) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n4817), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1254), .CK(clk), .RN(n4787),
.Q(FPADDSUB_DMP_SFG[11]), .QN(n4602) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1626), .CK(clk),
.RN(n4824), .Q(FPMULT_Op_MY[0]), .QN(n2209) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n1659), .CK(clk),
.RN(n2201), .Q(FPMULT_Op_MX[1]), .QN(n2309) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1646), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[20]), .QN(n2217) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1648), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[22]), .QN(n2221) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1643), .CK(clk),
.RN(n2201), .Q(FPMULT_Op_MY[17]), .QN(n2303) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1836), .CK(clk), .RN(
n4768), .Q(FPADDSUB_intDY_EWSW[7]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1838), .CK(clk), .RN(
n4771), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2076), .CK(clk), .RN(
n4772), .Q(FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1337), .CK(clk), .RN(
n4781), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1834), .CK(clk), .RN(
n4777), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1833), .CK(clk), .RN(
n4766), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1827), .CK(clk), .RN(
n4779), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1819), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDY_EWSW[24]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1816), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1841), .CK(clk), .RN(
n4768), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1319), .CK(clk), .RN(
n4767), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1340), .CK(clk), .RN(
n4778), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1668), .CK(clk),
.RN(n4819), .Q(FPMULT_Op_MX[10]), .QN(n2307) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1815), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1843), .CK(clk), .RN(
n4768), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1182), .CK(clk), .RN(
n4788), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1183), .CK(clk), .RN(
n4788), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1196), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1202), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1210), .CK(clk), .RN(n4765),
.Q(FPADDSUB_DMP_SFG[15]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1214), .CK(clk), .RN(n4784),
.Q(FPADDSUB_DMP_SFG[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1230), .CK(clk), .RN(n4762),
.Q(FPADDSUB_DMP_SFG[17]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1246), .CK(clk), .RN(n4767),
.Q(FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1258), .CK(clk), .RN(n4761),
.Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1811), .CK(clk), .RN(n4768), .Q(FPADDSUB_Data_array_SWR[24]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1809), .CK(clk), .RN(n4768), .Q(FPADDSUB_Data_array_SWR[22]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n1672), .CK(clk),
.RN(n4828), .Q(FPMULT_Op_MX[14]), .QN(n2285) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1342), .CK(clk), .RN(
n4778), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1810), .CK(clk), .RN(n4768), .Q(FPADDSUB_Data_array_SWR[23]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1676), .CK(clk),
.RN(n4819), .Q(FPMULT_Op_MX[18]), .QN(n2280) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1664), .CK(clk),
.RN(n4819), .Q(FPMULT_Op_MX[6]), .QN(n2272) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1181), .CK(clk), .RN(
n4788), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1662), .CK(clk),
.RN(n4828), .Q(FPMULT_Op_MX[4]), .QN(n2300) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1812), .CK(clk), .RN(n2267), .Q(FPADDSUB_Data_array_SWR[25]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1808), .CK(clk), .RN(n2931), .Q(FPADDSUB_Data_array_SWR[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1293), .CK(clk), .RN(n4782),
.Q(FPADDSUB_DMP_SFG[0]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1506), .CK(
clk), .RN(n4825), .Q(FPMULT_Sgf_normalized_result[1]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1197), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1198), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1201), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1205), .CK(clk), .RN(
n4772), .Q(FPADDSUB_DmP_mant_SFG_SWR[0]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1803), .CK(clk), .RN(n4786), .Q(FPADDSUB_Data_array_SWR[16]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(
n4767), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1795), .CK(clk), .RN(n2266),
.Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1339), .CK(clk), .RN(
n4778), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1527), .CK(
clk), .RN(n4823), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1410), .CK(clk), .RN(
n4773), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n4632) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1508), .CK(
clk), .RN(n4825), .Q(FPMULT_Sgf_normalized_result[3]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1512), .CK(
clk), .RN(n4824), .Q(FPMULT_Sgf_normalized_result[7]) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1528), .CK(clk), .RN(n4823), .Q(
FPMULT_FSM_selector_C) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1510), .CK(
clk), .RN(n4822), .Q(FPMULT_Sgf_normalized_result[5]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1794), .CK(clk), .RN(n4765),
.Q(FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_EXP_EWSW[26]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1463), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_EXP_EWSW[25]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1192), .CK(clk), .RN(
n4787), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n2298) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n4790),
.Q(operation_reg[0]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2149), .CK(
clk), .RN(n4761), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n4699) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1417), .CK(clk), .RN(n4777),
.Q(FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1793), .CK(clk), .RN(n4771),
.Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1733), .CK(clk), .RN(
n4796), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1911), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n4682) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n1558), .CK(clk),
.RN(n4794), .Q(FPMULT_P_Sgf[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1912), .CK(clk), .RN(
n4762), .Q(FPADDSUB_intDX_EWSW[29]), .QN(n4685) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n1569), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[40]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1609), .CK(clk),
.RN(n4828), .Q(FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1601), .CK(clk),
.RN(n4819), .Q(FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1611), .CK(clk), .RN(
n4828), .Q(FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1617), .CK(clk), .RN(
n4820), .Q(FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n1560), .CK(clk),
.RN(n4797), .Q(FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n1562), .CK(clk),
.RN(n4791), .Q(FPMULT_P_Sgf[33]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2058), .CK(clk), .RN(n4800), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2046), .CK(clk), .RN(n4800), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2070), .CK(clk), .RN(n4812), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2067), .CK(clk), .RN(n4790), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2064), .CK(clk), .RN(n4790), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2043), .CK(clk), .RN(n4796), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2031), .CK(clk), .RN(n4797), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2040), .CK(clk), .RN(n4792), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2049), .CK(clk), .RN(n2929), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2034), .CK(clk), .RN(n4810), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2028), .CK(clk), .RN(n4809), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n1567), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n1564), .CK(clk),
.RN(n4794), .Q(FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1625), .CK(
clk), .RN(n4825), .Q(FPMULT_zero_flag) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n1553), .CK(clk),
.RN(n4796), .Q(FPMULT_P_Sgf[24]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n1573), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[44]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n1575), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[46]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1792), .CK(clk), .RN(n4765),
.Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1652), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1587), .CK(clk), .RN(
n4823), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1588), .CK(clk), .RN(
n4823), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1589), .CK(clk), .RN(
n4823), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1590), .CK(clk), .RN(
n4823), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1591), .CK(clk), .RN(
n4823), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1592), .CK(clk), .RN(
n4823), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1593), .CK(clk), .RN(
n4824), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1594), .CK(clk), .RN(
n4826), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n1570), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[41]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2045), .CK(clk), .RN(n4800), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2072), .CK(clk), .RN(n4802), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2039), .CK(clk), .RN(n4792), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2048), .CK(clk), .RN(n4792), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2060), .CK(clk), .RN(n4797), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2009), .CK(clk), .RN(n4811), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2018), .CK(clk), .RN(n4809), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2006), .CK(clk), .RN(n4810), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1729), .CK(clk), .RN(n4812), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1784), .CK(clk), .RN(n4812), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1727), .CK(clk), .RN(n4793), .Q(
FPSENCOS_d_ff_Xn[31]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1893), .CK(clk), .RN(
n4803), .Q(FPSENCOS_d_ff2_Y[7]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1873), .CK(clk), .RN(
n4796), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n1574), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[45]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n1671), .CK(clk),
.RN(n4819), .Q(FPMULT_Op_MX[13]), .QN(n2273) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n1639), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[13]), .QN(n2207) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1631), .CK(clk),
.RN(n4822), .Q(FPMULT_Op_MY[5]), .QN(n2214) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1628), .CK(clk),
.RN(n4822), .Q(FPMULT_Op_MY[2]), .QN(n2216) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1630), .CK(clk),
.RN(n4822), .Q(FPMULT_Op_MY[4]), .QN(n2218) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1629), .CK(clk),
.RN(n4822), .Q(FPMULT_Op_MY[3]), .QN(n2211) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1627), .CK(clk),
.RN(n4826), .Q(FPMULT_Op_MY[1]), .QN(n2212) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n4799), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1698), .CK(clk), .RN(n2202),
.Q(cordic_result[28]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1769), .CK(clk), .RN(n2929), .Q(
FPSENCOS_d_ff_Xn[28]), .QN(n2235) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1770), .CK(clk), .RN(n4812), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1736), .CK(clk), .RN(
n4812), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1856), .CK(clk), .RN(
n2928), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n4702) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1686), .CK(clk),
.RN(n4818), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n1540), .CK(clk),
.RN(n4813), .Q(FPMULT_P_Sgf[11]) );
DFFSX1TS R_11 ( .D(n4756), .CK(clk), .SN(n2928), .Q(n4832) );
DFFSX1TS R_3 ( .D(n4758), .CK(clk), .SN(n4806), .Q(n4833) );
DFFSX1TS R_4 ( .D(n4757), .CK(clk), .SN(n4815), .Q(n4834) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1798), .CK(clk), .RN(n4766), .Q(FPADDSUB_Data_array_SWR[11]), .QN(n2233) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n1670), .CK(clk),
.RN(n4828), .Q(FPMULT_Op_MX[12]), .QN(n2208) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1728), .CK(clk), .RN(
n4767), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1418), .CK(clk), .RN(
n4774), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1423), .CK(clk), .RN(
n4782), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1428), .CK(clk), .RN(
n4770), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1433), .CK(clk), .RN(
n4776), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1438), .CK(clk), .RN(
n4789), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1443), .CK(clk), .RN(
n4789), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1448), .CK(clk), .RN(
n4789), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1453), .CK(clk), .RN(
n4789), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2115), .CK(clk), .RN(n4805), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2116), .CK(clk), .RN(n4805), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2129), .CK(clk), .RN(n4814), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2131), .CK(clk), .RN(n4816), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n4807), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n4794), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n4803), .Q(
dataA[29]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1991), .CK(clk), .RN(
n4813), .Q(FPSENCOS_d_ff2_X[7]), .QN(n2236) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1965), .CK(clk), .RN(
n4792), .Q(FPSENCOS_d_ff2_X[20]), .QN(n2237) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2114), .CK(clk), .RN(n4805), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2122), .CK(clk), .RN(n4817), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2132), .CK(clk), .RN(n4797), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2133), .CK(clk), .RN(n4796), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2128), .CK(clk), .RN(n4790), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRX1TS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1944), .CK(clk), .RN(n4790),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRX1TS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1945), .CK(clk), .RN(n4804),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n1658), .CK(clk),
.RN(n2201), .Q(FPMULT_Op_MX[0]), .QN(n2210) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1636), .CK(clk),
.RN(n2201), .Q(FPMULT_Op_MY[10]), .QN(n2223) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1647), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[21]), .QN(n2308) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1642), .CK(clk),
.RN(n4820), .Q(FPMULT_Op_MY[16]), .QN(n2304) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1644), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[18]), .QN(n2290) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1640), .CK(clk),
.RN(n4820), .Q(FPMULT_Op_MY[14]), .QN(n2305) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1645), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[19]), .QN(n2291) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n1641), .CK(clk),
.RN(n2201), .QN(n2306) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1632), .CK(clk),
.RN(n4820), .Q(FPMULT_Op_MY[6]), .QN(n2219) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1634), .CK(clk),
.RN(n2201), .Q(FPMULT_Op_MY[8]), .QN(n2222) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1839), .CK(clk), .RN(
n4777), .Q(FPADDSUB_intDY_EWSW[4]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n1660), .CK(clk),
.RN(n1480), .Q(FPMULT_Op_MX[2]), .QN(n2311) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1801), .CK(clk), .RN(n4772), .Q(FPADDSUB_Data_array_SWR[14]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1678), .CK(clk),
.RN(n4828), .Q(FPMULT_Op_MX[20]), .QN(n2278) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1674), .CK(clk),
.RN(n4828), .QN(n2283) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1666), .CK(clk),
.RN(n4819), .QN(n2289) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1804), .CK(clk), .RN(n4765), .Q(FPADDSUB_Data_array_SWR[17]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1802), .CK(clk), .RN(n2267), .Q(FPADDSUB_Data_array_SWR[15]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1807), .CK(clk), .RN(n4781), .Q(FPADDSUB_Data_array_SWR[20]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1679), .CK(clk),
.RN(n4818), .Q(FPMULT_Op_MX[21]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1675), .CK(clk),
.RN(n4819), .Q(FPMULT_Op_MX[17]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1667), .CK(clk),
.RN(n4828), .Q(FPMULT_Op_MX[9]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1663), .CK(clk),
.RN(n4828), .Q(FPMULT_Op_MX[5]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1677), .CK(clk),
.RN(n4819), .Q(FPMULT_Op_MX[19]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n1673), .CK(clk),
.RN(n4828), .Q(FPMULT_Op_MX[15]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1665), .CK(clk),
.RN(n4819), .Q(FPMULT_Op_MX[7]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n1661), .CK(clk),
.RN(n2201), .Q(FPMULT_Op_MX[3]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1796), .CK(clk), .RN(n4766),
.Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1522), .CK(
clk), .RN(n4826), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n4807), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1855), .CK(clk), .RN(
n4801), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1349), .CK(clk), .RN(
n4778), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1524), .CK(
clk), .RN(n4822), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1518), .CK(
clk), .RN(n4825), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1516), .CK(
clk), .RN(n4824), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1526), .CK(
clk), .RN(n4823), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1857), .CK(clk), .RN(
n4809), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1861), .CK(clk), .RN(
n4801), .Q(FPSENCOS_d_ff2_Y[23]) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1585), .CK(clk), .RN(
n4823), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1507), .CK(
clk), .RN(n4825), .Q(FPMULT_Sgf_normalized_result[2]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1204), .CK(clk), .RN(
n4786), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1315), .CK(clk), .RN(
n4769), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]), .QN(n4700) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n4808), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1854), .CK(clk), .RN(
n4812), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1586), .CK(clk), .RN(
n4824), .Q(underflow_flag_mult) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1800), .CK(clk), .RN(n4766), .Q(FPADDSUB_Data_array_SWR[13]), .QN(n2284) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1464), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_EXP_EWSW[24]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1619), .CK(clk), .RN(
n4820), .Q(FPMULT_Add_result[1]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1799), .CK(clk), .RN(n4766), .Q(FPADDSUB_Data_array_SWR[12]), .QN(n4697) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1685), .CK(clk),
.RN(n4818), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2052), .CK(clk), .RN(n4806), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n1556), .CK(clk),
.RN(n4797), .Q(FPMULT_P_Sgf[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2055), .CK(clk), .RN(n4794), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2037), .CK(clk), .RN(n4793), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1656), .CK(clk),
.RN(n4820), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1776), .CK(clk), .RN(n4814), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n1555), .CK(clk),
.RN(n4816), .Q(FPMULT_P_Sgf[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1908), .CK(clk), .RN(n4795), .Q(
FPSENCOS_d_ff_Yn[31]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1791), .CK(clk), .RN(n2267),
.Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1651), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1863), .CK(clk), .RN(
n4801), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1877), .CK(clk), .RN(
n2930), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1871), .CK(clk), .RN(
n4802), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1869), .CK(clk), .RN(
n2202), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1867), .CK(clk), .RN(
n4798), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1881), .CK(clk), .RN(
n4793), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1875), .CK(clk), .RN(
n4806), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1885), .CK(clk), .RN(
n4792), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1879), .CK(clk), .RN(
n4814), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1845), .CK(clk), .RN(
n4791), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1901), .CK(clk), .RN(
n4790), .Q(FPSENCOS_d_ff2_Y[3]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1897), .CK(clk), .RN(
n4800), .Q(FPSENCOS_d_ff2_Y[5]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n1572), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[43]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1865), .CK(clk), .RN(
n4813), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1899), .CK(clk), .RN(
n4797), .Q(FPSENCOS_d_ff2_Y[4]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1895), .CK(clk), .RN(
n4791), .Q(FPSENCOS_d_ff2_Y[6]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1891), .CK(clk), .RN(
n4792), .Q(FPSENCOS_d_ff2_Y[8]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1887), .CK(clk), .RN(
n4809), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1883), .CK(clk), .RN(
n4791), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1903), .CK(clk), .RN(
n4792), .Q(FPSENCOS_d_ff2_Y[2]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1907), .CK(clk), .RN(
n4816), .Q(FPSENCOS_d_ff2_Y[0]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1905), .CK(clk), .RN(
n2202), .Q(FPSENCOS_d_ff2_Y[1]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1889), .CK(clk), .RN(
n4800), .Q(FPSENCOS_d_ff2_Y[9]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1650), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1682), .CK(clk),
.RN(n4818), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n1561), .CK(clk),
.RN(n4794), .Q(FPMULT_P_Sgf[32]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1785), .CK(clk), .RN(n2928), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1782), .CK(clk), .RN(n4815), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1779), .CK(clk), .RN(n4817), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1773), .CK(clk), .RN(n4810), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1767), .CK(clk), .RN(n4815), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1730), .CK(clk), .RN(n2928), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2007), .CK(clk), .RN(n4815), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2010), .CK(clk), .RN(n4816), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2016), .CK(clk), .RN(n2928), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2013), .CK(clk), .RN(n2928), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2022), .CK(clk), .RN(n4797), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2061), .CK(clk), .RN(n4793), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2025), .CK(clk), .RN(n2928), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2073), .CK(clk), .RN(n4795), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2019), .CK(clk), .RN(n4795), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n1571), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[42]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2027), .CK(clk), .RN(n4802), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1649), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n1568), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[39]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2145), .CK(clk), .RN(
n4761), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1653), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1654), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1655), .CK(clk),
.RN(n4821), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n1694), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[47]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n2202), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .QN(n4617) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1350), .CK(clk), .RN(
n4789), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n4556) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n4808), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2140), .CK(clk), .RN(n4807),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n4609) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n4816), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n4806), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1681), .CK(clk),
.RN(n4820), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1683), .CK(clk),
.RN(n4818), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1684), .CK(clk),
.RN(n4818), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1687), .CK(clk),
.RN(n4818), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1688), .CK(clk),
.RN(n4818), .Q(FPMULT_Op_MX[30]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1605), .CK(clk),
.RN(n4819), .Q(FPMULT_Add_result[15]), .QN(n4719) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1603), .CK(clk),
.RN(n4828), .Q(FPMULT_Add_result[17]), .QN(n4717) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1607), .CK(clk),
.RN(n4828), .Q(FPMULT_Add_result[13]), .QN(n4718) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1604), .CK(clk),
.RN(n4821), .Q(FPMULT_Add_result[16]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1747), .CK(clk), .RN(
n4791), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n1549), .CK(clk),
.RN(n4791), .Q(FPMULT_P_Sgf[20]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n1545), .CK(clk),
.RN(n4791), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2079), .CK(clk), .RN(
n2931), .Q(FPADDSUB_bit_shift_SHT2), .QN(n2231) );
DFFRX1TS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1475), .CK(clk), .RN(
n4770), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1338), .CK(clk), .RN(
n4784), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n4543) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1185), .CK(clk), .RN(
n4788), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n4621) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1731), .CK(clk), .RN(
n4764), .Q(FPADDSUB_intAS) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2127), .CK(clk), .RN(n4791), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1959), .CK(clk), .RN(
n4801), .Q(FPSENCOS_d_ff2_X[23]), .QN(n2232) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n4799), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n2202), .Q(
dataA[28]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n4807), .Q(
dataB[26]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1781), .CK(clk), .RN(n4815), .Q(
FPSENCOS_d_ff_Xn[24]), .QN(n2269) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1778), .CK(clk), .RN(n4814), .Q(
FPSENCOS_d_ff_Xn[25]), .QN(n2270) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1775), .CK(clk), .RN(n4810), .Q(
FPSENCOS_d_ff_Xn[26]), .QN(n2275) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1766), .CK(clk), .RN(n4811), .Q(
FPSENCOS_d_ff_Xn[29]), .QN(n2281) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2015), .CK(clk), .RN(n4808), .Q(
FPSENCOS_d_ff_Xn[19]), .QN(n2286) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2012), .CK(clk), .RN(n4794), .Q(
FPSENCOS_d_ff_Xn[20]), .QN(n2301) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2054), .CK(clk), .RN(n4795), .Q(
FPSENCOS_d_ff_Xn[6]), .QN(n2293) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2024), .CK(clk), .RN(n4806), .Q(
FPSENCOS_d_ff_Xn[16]), .QN(n2297) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2030), .CK(clk), .RN(n4809), .Q(
FPSENCOS_d_ff_Xn[14]), .QN(n2279) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2042), .CK(clk), .RN(n4795), .Q(
FPSENCOS_d_ff_Xn[10]), .QN(n2287) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2036), .CK(clk), .RN(n4796), .Q(
FPSENCOS_d_ff_Xn[12]), .QN(n2299) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2063), .CK(clk), .RN(n4790), .Q(
FPSENCOS_d_ff_Xn[3]), .QN(n2274) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2066), .CK(clk), .RN(n2930), .Q(
FPSENCOS_d_ff_Xn[2]), .QN(n2292) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n2202), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n4796), .Q(
dataA[27]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n2202), .Q(
dataB[24]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1413), .CK(clk), .RN(n4773),
.Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1598), .CK(clk),
.RN(n4828), .Q(FPMULT_Add_result[22]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1860), .CK(clk), .RN(
n2928), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1859), .CK(clk), .RN(
n4817), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1858), .CK(clk), .RN(
n4814), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1606), .CK(clk),
.RN(n4819), .Q(FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1610), .CK(clk),
.RN(n4821), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1461), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1612), .CK(clk), .RN(
n4820), .Q(FPMULT_Add_result[8]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2191), .CK(
clk), .RN(n4761), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n4616) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n2928),
.Q(operation_reg[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1614), .CK(clk), .RN(
n4820), .Q(FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n1563), .CK(clk),
.RN(n4797), .Q(FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n1559), .CK(clk),
.RN(n4794), .Q(FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n1554), .CK(clk),
.RN(n4797), .Q(FPMULT_P_Sgf[25]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1732), .CK(clk), .RN(n4796), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1332), .CK(clk), .RN(
n4764), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n4542) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1334), .CK(clk), .RN(
n4780), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n4696) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2130), .CK(clk), .RN(n4794), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n1566), .CK(clk),
.RN(n4798), .Q(FPMULT_P_Sgf[37]) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2141), .CK(clk), .RN(n4800),
.Q(n4760), .QN(n2228) );
DFFRX1TS R_12 ( .D(n4755), .CK(clk), .RN(n4812), .Q(n4831) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1615), .CK(clk), .RN(
n4820), .Q(FPMULT_Add_result[5]), .QN(n4723) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1465), .CK(clk), .RN(n4770),
.Q(FPADDSUB_DMP_EXP_EWSW[23]), .QN(n4698) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1351), .CK(clk), .RN(n4778),
.Q(FPADDSUB_ADD_OVRFLW_NRM), .QN(n4669) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1597), .CK(clk),
.RN(n4820), .Q(FPMULT_Add_result[23]), .QN(n4586) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1595), .CK(clk), .RN(
n4822), .Q(FPMULT_exp_oper_result[8]), .QN(n4582) );
DFFSX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n4704), .CK(clk), .SN(n4761), .Q(
n4835), .QN(ready_add_subt) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1680), .CK(clk),
.RN(n4818), .Q(FPMULT_Op_MX[22]), .QN(n2220) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n4789),
.Q(FPADDSUB_DMP_EXP_EWSW[17]) );
CMPR32X2TS DP_OP_26J221_124_9022_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n4556), .C(DP_OP_26J221_124_9022_n18), .CO(DP_OP_26J221_124_9022_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J221_124_9022_U8 ( .A(DP_OP_26J221_124_9022_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J221_124_9022_n8), .CO(
DP_OP_26J221_124_9022_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J221_124_9022_U7 ( .A(DP_OP_26J221_124_9022_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J221_124_9022_n7), .CO(
DP_OP_26J221_124_9022_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J221_124_9022_U6 ( .A(DP_OP_26J221_124_9022_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J221_124_9022_n6), .CO(
DP_OP_26J221_124_9022_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2139), .CK(clk), .RN(n4808),
.Q(FPSENCOS_cont_iter_out[2]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2143), .CK(clk), .RN(
n4785), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n2195) );
CMPR32X2TS DP_OP_26J221_124_9022_U5 ( .A(DP_OP_26J221_124_9022_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J221_124_9022_n5), .CO(
DP_OP_26J221_124_9022_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2146), .CK(clk), .RN(
n4761), .QN(n4725) );
CMPR32X2TS DP_OP_26J221_124_9022_U4 ( .A(n4556), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J221_124_9022_n4), .CO(
DP_OP_26J221_124_9022_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J221_124_9022_U3 ( .A(n4556), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J221_124_9022_n3), .CO(
DP_OP_26J221_124_9022_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1352), .CK(clk), .RN(n4772),
.Q(FPADDSUB_OP_FLAG_SFG) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2144), .CK(clk), .RN(
n4761), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n4585) );
CMPR32X2TS DP_OP_26J221_124_9022_U2 ( .A(n4556), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J221_124_9022_n2), .CO(
DP_OP_26J221_124_9022_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS intadd_501_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n4609), .C(
intadd_501_CI), .CO(intadd_501_n3), .S(intadd_501_SUM_0_) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2075), .CK(clk), .RN(
n2266), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2194) );
CMPR32X2TS intadd_501_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(intadd_501_B_1_),
.C(intadd_501_n3), .CO(intadd_501_n2), .S(intadd_501_SUM_1_) );
CMPR32X2TS intadd_501_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n4559), .C(
intadd_501_n2), .CO(intadd_501_n1), .S(intadd_501_SUM_2_) );
CMPR32X2TS intadd_500_U4 ( .A(n4707), .B(FPADDSUB_DMP_EXP_EWSW[24]), .C(
intadd_500_CI), .CO(intadd_500_n3), .S(intadd_500_SUM_0_) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2148), .CK(clk), .RN(
n4761), .Q(FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n4549) );
CMPR32X2TS intadd_500_U3 ( .A(n4706), .B(FPADDSUB_DMP_EXP_EWSW[25]), .C(
intadd_500_n3), .CO(intadd_500_n2), .S(intadd_500_SUM_1_) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2147), .CK(clk), .RN(
n4761), .Q(FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n4587) );
CMPR32X2TS intadd_500_U2 ( .A(n4715), .B(FPADDSUB_DMP_EXP_EWSW[26]), .C(
intadd_500_n2), .CO(intadd_500_n1), .S(intadd_500_SUM_2_) );
AOI222X1TS U2217 ( .A0(n4121), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n3255)
);
AOI222X1TS U2218 ( .A0(n2200), .A1(cordic_result[3]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[3]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[3]), .Y(n3478)
);
AOI222X1TS U2219 ( .A0(n3514), .A1(cordic_result[12]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[12]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[12]), .Y(n3515) );
AOI222X1TS U2220 ( .A0(n3514), .A1(cordic_result[22]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[22]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[22]), .Y(n3486) );
AOI222X1TS U2221 ( .A0(n2200), .A1(cordic_result[1]), .B0(n3473), .B1(
FPSENCOS_d_ff_Xn[1]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[1]), .Y(n3502)
);
AOI222X1TS U2222 ( .A0(n2200), .A1(cordic_result[6]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[6]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[6]), .Y(n3480)
);
AOI222X1TS U2223 ( .A0(n2200), .A1(cordic_result[7]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[7]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[7]), .Y(n3477)
);
AOI222X1TS U2224 ( .A0(n2200), .A1(cordic_result[4]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[4]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[4]), .Y(n3506)
);
AOI222X1TS U2225 ( .A0(n2200), .A1(cordic_result[8]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[8]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[8]), .Y(n3508)
);
AOI222X1TS U2226 ( .A0(n2200), .A1(cordic_result[11]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[11]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[11]), .Y(n3510) );
AOI222X1TS U2227 ( .A0(n2200), .A1(cordic_result[9]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[9]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[9]), .Y(n3509)
);
AOI222X1TS U2228 ( .A0(n2200), .A1(cordic_result[5]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[5]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[5]), .Y(n3479)
);
AOI222X1TS U2229 ( .A0(n3514), .A1(cordic_result[26]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[26]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[26]), .Y(n3503) );
AOI222X1TS U2230 ( .A0(n2200), .A1(cordic_result[10]), .B0(n3501), .B1(
FPSENCOS_d_ff_Xn[10]), .C0(n3476), .C1(FPSENCOS_d_ff_Yn[10]), .Y(n3475) );
AOI222X1TS U2231 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n3446), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n4115), .Y(n3242)
);
AOI222X1TS U2232 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n3252)
);
AOI222X1TS U2233 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n3251)
);
AOI222X1TS U2234 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n3257)
);
AOI222X1TS U2235 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n3253)
);
AOI222X1TS U2236 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n3250) );
AOI222X1TS U2237 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n3249) );
AOI222X1TS U2238 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n3254)
);
AOI222X1TS U2239 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n3259)
);
AOI222X1TS U2240 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n3258)
);
AOI222X1TS U2241 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n3256)
);
AOI222X1TS U2242 ( .A0(n2200), .A1(cordic_result[2]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[2]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[2]), .Y(n3494)
);
AOI222X1TS U2243 ( .A0(n2200), .A1(cordic_result[0]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[0]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[0]), .Y(n3495)
);
AOI222X1TS U2244 ( .A0(n2200), .A1(cordic_result[15]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[15]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[15]), .Y(n3487) );
AOI222X1TS U2245 ( .A0(n3514), .A1(cordic_result[27]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[27]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[27]), .Y(n3505) );
AOI222X1TS U2246 ( .A0(n3514), .A1(cordic_result[29]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[29]), .C0(n3507), .C1(FPSENCOS_d_ff_Yn[29]), .Y(n3512) );
AOI222X1TS U2247 ( .A0(n3514), .A1(cordic_result[30]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[30]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[30]), .Y(n3511) );
AOI222X1TS U2248 ( .A0(n3514), .A1(cordic_result[13]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[13]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[13]), .Y(n3500) );
AOI222X1TS U2249 ( .A0(n3514), .A1(cordic_result[17]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[17]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[17]), .Y(n3488) );
AOI222X1TS U2250 ( .A0(n3514), .A1(cordic_result[24]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[24]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[24]), .Y(n3497) );
AOI222X1TS U2251 ( .A0(n3514), .A1(cordic_result[20]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[20]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[20]), .Y(n3493) );
AOI222X1TS U2252 ( .A0(n3514), .A1(cordic_result[14]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[14]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[14]), .Y(n3492) );
AOI222X1TS U2253 ( .A0(n3514), .A1(cordic_result[16]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[16]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[16]), .Y(n3491) );
AOI222X1TS U2254 ( .A0(n3514), .A1(cordic_result[25]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[25]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[25]), .Y(n3489) );
AOI222X1TS U2255 ( .A0(n3514), .A1(cordic_result[19]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[19]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[19]), .Y(n3485) );
AOI222X1TS U2256 ( .A0(n3514), .A1(cordic_result[18]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[18]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[18]), .Y(n3498) );
AOI222X1TS U2257 ( .A0(n3514), .A1(cordic_result[23]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[23]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[23]), .Y(n3496) );
AOI222X1TS U2258 ( .A0(n3514), .A1(cordic_result[21]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[21]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[21]), .Y(n3490) );
AOI222X1TS U2259 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n4120), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n3450) );
AOI211X1TS U2260 ( .A0(n4122), .A1(FPSENCOS_d_ff3_LUT_out[15]), .B0(n3440),
.C0(n3424), .Y(n3425) );
AOI222X1TS U2261 ( .A0(n4104), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n3371) );
AOI222X1TS U2262 ( .A0(n4104), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n3447) );
AOI222X1TS U2263 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n3372) );
AOI222X1TS U2264 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n3386) );
AOI222X1TS U2265 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n3384) );
AOI222X1TS U2266 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n3383) );
AOI222X1TS U2267 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n3382) );
AOI222X1TS U2268 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n3381) );
AOI222X1TS U2269 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n3380) );
AOI222X1TS U2270 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n3379) );
AOI222X1TS U2271 ( .A0(n4102), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n3376) );
AOI222X1TS U2272 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n3375) );
AOI222X1TS U2273 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n3374) );
AOI222X1TS U2274 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n4117), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n3445) );
AOI222X1TS U2275 ( .A0(n4104), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n4117), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n3443) );
AOI222X1TS U2276 ( .A0(n4104), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n4117), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n3448) );
AOI32X1TS U2277 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n4124), .A2(n2963),
.B0(FPSENCOS_d_ff3_LUT_out[10]), .B1(n4122), .Y(n2964) );
OR2X4TS U2278 ( .A(n4413), .B(n4549), .Y(n3225) );
AOI211X1TS U2279 ( .A0(FPADDSUB_Data_array_SWR[0]), .A1(n3275), .B0(n4486),
.C0(n4485), .Y(n4523) );
NAND2X4TS U2280 ( .A(n2194), .B(n4522), .Y(n3279) );
NAND2X4TS U2281 ( .A(n4468), .B(n4445), .Y(n2910) );
CLKINVX6TS U2282 ( .A(n4068), .Y(n3759) );
NAND2X2TS U2283 ( .A(n3677), .B(n4064), .Y(n3758) );
NOR2X1TS U2284 ( .A(n3882), .B(n3883), .Y(n3881) );
NOR2X1TS U2285 ( .A(n3875), .B(n3876), .Y(n3874) );
NOR2BX1TS U2286 ( .AN(intadd_499_SUM_24_), .B(n3038), .Y(n3889) );
NOR2X1TS U2287 ( .A(n3867), .B(n3868), .Y(n3866) );
NOR2X1TS U2288 ( .A(n3855), .B(n3856), .Y(n3854) );
NOR2X1TS U2289 ( .A(n3847), .B(n3848), .Y(n3846) );
CMPR32X2TS U2290 ( .A(n2863), .B(n2862), .C(n2861), .CO(n2823), .S(
DP_OP_454J221_123_2743_n137) );
CMPR32X2TS U2291 ( .A(n2461), .B(n2460), .C(n2459), .CO(mult_x_219_n124),
.S(mult_x_219_n125) );
NAND2X4TS U2292 ( .A(n2449), .B(n2220), .Y(n2365) );
NOR2X1TS U2293 ( .A(n3833), .B(n3834), .Y(n3832) );
CMPR32X2TS U2294 ( .A(n2260), .B(FPMULT_Op_MY[21]), .C(n2712), .CO(n2703),
.S(n2798) );
CMPR32X2TS U2295 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[20]), .C(n2707),
.CO(n2712), .S(n2871) );
AO21X1TS U2296 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(n3752), .Y(n4446) );
CMPR32X2TS U2297 ( .A(n2255), .B(FPMULT_Op_MX[20]), .C(n2700), .CO(n2673),
.S(n2702) );
CMPR32X2TS U2298 ( .A(n2258), .B(FPMULT_Op_MY[19]), .C(n2708), .CO(n2707),
.S(n2848) );
CMPR32X2TS U2299 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[18]), .C(n2713),
.CO(n2708), .S(n2874) );
CMPR32X2TS U2300 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MY[17]), .C(n2694),
.CO(n2713), .S(n2838) );
CMPR32X2TS U2301 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .C(n2696),
.CO(n2695), .S(n2698) );
CMPR32X2TS U2302 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[16]), .C(n2666),
.CO(n2694), .S(n2810) );
NOR2X1TS U2303 ( .A(n3005), .B(n3006), .Y(n3004) );
CMPR32X2TS U2304 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[14]), .C(n2651),
.CO(n2646), .S(n2743) );
OAI21XLTS U2305 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n4461), .B0(n4460), .Y(
n4465) );
NOR2X4TS U2306 ( .A(n3946), .B(n3039), .Y(n4316) );
OAI21XLTS U2307 ( .A0(n3863), .A1(n4011), .B0(n3862), .Y(n1562) );
OAI21XLTS U2308 ( .A0(n3887), .A1(n3886), .B0(n3885), .Y(n1319) );
OAI21XLTS U2309 ( .A0(n4468), .A1(n4571), .B0(n3871), .Y(n1321) );
OAI21XLTS U2310 ( .A0(n4468), .A1(n4631), .B0(n3879), .Y(n1320) );
AO22X1TS U2311 ( .A0(n4333), .A1(FPMULT_P_Sgf[47]), .B0(n4344), .B1(n3046),
.Y(n1694) );
AO22X1TS U2312 ( .A0(n4345), .A1(FPMULT_P_Sgf[46]), .B0(n3089), .B1(n3044),
.Y(n1575) );
AO22X1TS U2313 ( .A0(n4345), .A1(FPMULT_P_Sgf[44]), .B0(n4342), .B1(n3043),
.Y(n1573) );
AO22X1TS U2314 ( .A0(n4345), .A1(FPMULT_P_Sgf[42]), .B0(n3089), .B1(n3042),
.Y(n1571) );
AO22X1TS U2315 ( .A0(n4333), .A1(FPMULT_P_Sgf[40]), .B0(n4342), .B1(n3041),
.Y(n1569) );
OAI211X1TS U2316 ( .A0(n4316), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[15]),
.B0(n4321), .C0(n4315), .Y(n4317) );
AO22X1TS U2317 ( .A0(n4345), .A1(FPMULT_P_Sgf[38]), .B0(n3089), .B1(n3040),
.Y(n1567) );
OAI21X1TS U2318 ( .A0(n3897), .A1(n4011), .B0(n3896), .Y(n1566) );
AO21XLTS U2319 ( .A0(n3892), .A1(n4342), .B0(n3891), .Y(n1565) );
AO21X1TS U2320 ( .A0(FPADDSUB_ADD_OVRFLW_NRM), .A1(n4424), .B0(n4423), .Y(
n1351) );
AO22X1TS U2321 ( .A0(n4345), .A1(FPMULT_P_Sgf[35]), .B0(n4342), .B1(n3035),
.Y(n1564) );
AOI31X1TS U2322 ( .A0(n4724), .A1(n4463), .A2(n4422), .B0(n2910), .Y(n4423)
);
AO21X1TS U2323 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[23]), .B0(n4452), .Y(n4461) );
AOI211X1TS U2324 ( .A0(n4459), .A1(n4453), .B0(n4452), .C0(n2910), .Y(n4454)
);
OAI21X1TS U2325 ( .A0(n3843), .A1(n4011), .B0(n3842), .Y(n1560) );
OAI21X1TS U2326 ( .A0(n4459), .A1(n4457), .B0(n4455), .Y(n4456) );
CLKBUFX2TS U2327 ( .A(n3877), .Y(n2252) );
CLKBUFX2TS U2328 ( .A(n3869), .Y(n2251) );
INVX6TS U2329 ( .A(n3020), .Y(n3021) );
NAND2X2TS U2330 ( .A(n4320), .B(n4322), .Y(n3826) );
CLKBUFX2TS U2331 ( .A(n3857), .Y(n2250) );
NAND2X2TS U2332 ( .A(n4318), .B(n4319), .Y(n4322) );
INVX1TS U2333 ( .A(n4320), .Y(n4323) );
OR2X2TS U2334 ( .A(intadd_499_SUM_15_), .B(n3017), .Y(n4319) );
CLKBUFX2TS U2335 ( .A(n3849), .Y(n2249) );
CLKBUFX2TS U2336 ( .A(n3835), .Y(n2248) );
INVX4TS U2337 ( .A(n2991), .Y(n2992) );
OAI21X2TS U2338 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_right[20]), .A1(n2988),
.B0(n2987), .Y(n4326) );
NAND2X2TS U2339 ( .A(intadd_499_SUM_8_), .B(n2974), .Y(n2987) );
NOR2X4TS U2340 ( .A(intadd_499_SUM_8_), .B(n2974), .Y(n2988) );
OAI21X2TS U2341 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_right[19]), .A1(n2973),
.B0(n2972), .Y(n2974) );
NOR2X2TS U2342 ( .A(intadd_499_SUM_7_), .B(n2968), .Y(n2973) );
OAI21X2TS U2343 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_right[18]), .A1(n2967),
.B0(n2966), .Y(n2968) );
CLKBUFX2TS U2344 ( .A(n2982), .Y(n2244) );
NOR2X2TS U2345 ( .A(intadd_499_SUM_6_), .B(n2958), .Y(n2967) );
CLKINVX6TS U2346 ( .A(n3595), .Y(n3596) );
NOR2XLTS U2347 ( .A(n4020), .B(n4023), .Y(n3286) );
NAND2X4TS U2348 ( .A(n3562), .B(n3561), .Y(n3563) );
OR2X2TS U2349 ( .A(n3559), .B(n3555), .Y(n3556) );
CLKBUFX2TS U2350 ( .A(n3467), .Y(n2247) );
INVX3TS U2351 ( .A(n2765), .Y(n2772) );
CMPR32X2TS U2352 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .C(n2703),
.CO(n2699), .S(n2795) );
NAND2BXLTS U2353 ( .AN(n3284), .B(n2944), .Y(n3280) );
NOR2XLTS U2354 ( .A(n2943), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n2944) );
CLKBUFX2TS U2355 ( .A(n3393), .Y(n2246) );
NAND2X4TS U2356 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .B(n4413), .Y(n3224) );
INVX3TS U2357 ( .A(n3146), .Y(n3076) );
NOR2X4TS U2358 ( .A(n3680), .B(n4060), .Y(n3708) );
OAI21X1TS U2359 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_right[14]), .A1(n4339),
.B0(n4338), .Y(n2949) );
BUFX6TS U2360 ( .A(n4153), .Y(n2199) );
BUFX4TS U2361 ( .A(n3474), .Y(n2200) );
NOR2X2TS U2362 ( .A(operation[1]), .B(n3678), .Y(n3679) );
BUFX6TS U2363 ( .A(n3241), .Y(n3446) );
AOI21X2TS U2364 ( .A0(n3597), .A1(n4622), .B0(n3568), .Y(n2230) );
OAI221X4TS U2365 ( .A0(n2652), .A1(n2807), .B0(n2706), .B1(n2808), .C0(n2821), .Y(n2653) );
CLKBUFX2TS U2366 ( .A(n3069), .Y(n2245) );
NAND2X4TS U2367 ( .A(n3991), .B(n3676), .Y(n3678) );
ADDFX1TS U2368 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[13]), .B(n2947), .CI(
n2946), .CO(n2948), .S(n2936) );
OAI221X4TS U2369 ( .A0(n2256), .A1(n2425), .B0(n2283), .B1(n2409), .C0(n2393), .Y(n2313) );
OAI221X4TS U2370 ( .A0(FPMULT_Op_MX[4]), .A1(n2581), .B0(n2300), .B1(n2564),
.C0(n2587), .Y(n2463) );
NAND2X4TS U2371 ( .A(n2985), .B(n2918), .Y(n4342) );
NOR2X2TS U2372 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_501_n1), .Y(n4125) );
NAND3XLTS U2373 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FSM_add_overflow_flag), .C(n2917), .Y(n2918) );
INVX3TS U2374 ( .A(n2402), .Y(n2364) );
INVX4TS U2375 ( .A(n2897), .Y(n2898) );
CLKAND2X2TS U2376 ( .A(n4055), .B(n4059), .Y(n4076) );
CLKBUFX3TS U2377 ( .A(n4188), .Y(n4094) );
OAI221X4TS U2378 ( .A0(FPMULT_Op_MX[2]), .A1(n2567), .B0(n2311), .B1(n2582),
.C0(n2635), .Y(n2466) );
NAND2X2TS U2379 ( .A(n4051), .B(n4058), .Y(n4089) );
OR3X4TS U2380 ( .A(n4200), .B(n4576), .C(n4835), .Y(n4093) );
OR3X4TS U2381 ( .A(n4200), .B(FPSENCOS_cont_var_out[1]), .C(n4835), .Y(n4189) );
CLKINVX3TS U2382 ( .A(n4482), .Y(n3274) );
NOR2X6TS U2383 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n3300), .Y(n3275)
);
NOR2XLTS U2384 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n3578), .Y(n3051) );
INVX4TS U2385 ( .A(n2889), .Y(n2649) );
ADDFX1TS U2386 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .CI(n2648), .CO(
n2639), .S(n2652) );
NAND2BXLTS U2387 ( .AN(n3519), .B(n4624), .Y(n2985) );
BUFX6TS U2388 ( .A(n1480), .Y(n2201) );
OR3X4TS U2389 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[3]), .C(n3987), .Y(n2310) );
NAND2X4TS U2390 ( .A(n4490), .B(n2194), .Y(n3329) );
AND3X4TS U2391 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .C(n4300), .Y(n4302) );
INVX4TS U2392 ( .A(n4071), .Y(n3792) );
BUFX6TS U2393 ( .A(n2930), .Y(n2202) );
AND2X4TS U2394 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(n4704), .Y(n4506) );
NOR2X1TS U2395 ( .A(FPADDSUB_DmP_mant_SFG_SWR[13]), .B(n4602), .Y(n2904) );
INVX3TS U2396 ( .A(n2306), .Y(n2261) );
BUFX4TS U2397 ( .A(n2928), .Y(n2929) );
CLKINVX6TS U2398 ( .A(rst), .Y(n2928) );
AOI222X4TS U2399 ( .A0(intadd_499_SUM_16_), .A1(n3826), .B0(
intadd_499_SUM_16_), .B1(n3906), .C0(n3826), .C1(n3906), .Y(n3020) );
NAND2BX1TS U2400 ( .AN(intadd_499_SUM_24_), .B(n3038), .Y(n3888) );
ADDFHX2TS U2401 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .B(n3029), .CI(
n3028), .CO(n3860), .S(n3027) );
NAND2X4TS U2402 ( .A(n4310), .B(FPMULT_Sgf_operation_EVEN1_Q_left[19]), .Y(
n4309) );
NAND2X4TS U2403 ( .A(n4316), .B(FPMULT_Sgf_operation_EVEN1_Q_left[15]), .Y(
n4315) );
NOR2BX2TS U2404 ( .AN(n2948), .B(intadd_499_SUM_2_), .Y(n4339) );
NAND2BX1TS U2405 ( .AN(n2948), .B(intadd_499_SUM_2_), .Y(n4338) );
AOI222X4TS U2406 ( .A0(intadd_499_SUM_9_), .A1(n4326), .B0(intadd_499_SUM_9_), .B1(n3975), .C0(n4326), .C1(n3975), .Y(n2991) );
NAND2X4TS U2407 ( .A(n4313), .B(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .Y(
n4312) );
AOI21X4TS U2408 ( .A0(n3938), .A1(n3888), .B0(n3889), .Y(n3894) );
AOI222X2TS U2409 ( .A0(intadd_499_SUM_17_), .A1(n3910), .B0(
intadd_499_SUM_17_), .B1(n3021), .C0(n3910), .C1(n3021), .Y(n3023) );
NOR2X8TS U2410 ( .A(n4306), .B(n3978), .Y(n3045) );
NAND2X4TS U2411 ( .A(n4307), .B(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .Y(
n4306) );
NOR2X6TS U2412 ( .A(n4312), .B(n3962), .Y(n4310) );
AOI21X1TS U2413 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .A1(n3016),
.B0(n3015), .Y(n3017) );
OAI21X1TS U2414 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_right[16]), .A1(n4330),
.B0(n4329), .Y(n2951) );
OAI21X1TS U2415 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_right[17]), .A1(n2957),
.B0(n2956), .Y(n2958) );
OAI21X1TS U2416 ( .A0(n3000), .A1(n4836), .B0(n2999), .Y(n3010) );
NAND2BX1TS U2417 ( .AN(intadd_499_SUM_12_), .B(n2998), .Y(n2999) );
NOR2X1TS U2418 ( .A(intadd_499_SUM_4_), .B(n2950), .Y(n4330) );
NAND2X1TS U2419 ( .A(intadd_499_SUM_4_), .B(n2950), .Y(n4329) );
NOR2BX1TS U2420 ( .AN(n3012), .B(intadd_499_SUM_14_), .Y(n3015) );
NAND2BX1TS U2421 ( .AN(n3012), .B(intadd_499_SUM_14_), .Y(n3016) );
NAND2X1TS U2422 ( .A(intadd_499_SUM_15_), .B(n3017), .Y(n4320) );
OAI21X1TS U2423 ( .A0(n3026), .A1(n3918), .B0(n3025), .Y(n3028) );
NAND2BX1TS U2424 ( .AN(intadd_499_SUM_19_), .B(n3840), .Y(n3025) );
NOR2X2TS U2425 ( .A(n4315), .B(n3954), .Y(n4313) );
NOR2X1TS U2426 ( .A(intadd_499_SUM_5_), .B(n2951), .Y(n2957) );
NAND2X1TS U2427 ( .A(intadd_499_SUM_5_), .B(n2951), .Y(n2956) );
NAND2X1TS U2428 ( .A(intadd_499_SUM_6_), .B(n2958), .Y(n2966) );
NAND2X1TS U2429 ( .A(intadd_499_SUM_7_), .B(n2968), .Y(n2972) );
NAND2BXLTS U2430 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n3175) );
NOR2X1TS U2431 ( .A(n4215), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[1]), .Y(
intadd_499_A_2_) );
NOR2BX1TS U2432 ( .AN(intadd_499_SUM_12_), .B(n2998), .Y(n3000) );
NOR2X1TS U2433 ( .A(n3391), .B(n3392), .Y(n3390) );
NOR2X1TS U2434 ( .A(n2980), .B(n2981), .Y(n2979) );
AOI211X1TS U2435 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n3275), .B0(n3318),
.C0(n3317), .Y(n3335) );
AOI211X1TS U2436 ( .A0(FPADDSUB_Data_array_SWR[6]), .A1(n4481), .B0(n3298),
.C0(n3297), .Y(n3341) );
OAI32X1TS U2437 ( .A0(n2618), .A1(FPMULT_Op_MY[0]), .A2(n2617), .B0(n2513),
.B1(n2618), .Y(n2619) );
OAI32X1TS U2438 ( .A0(n2611), .A1(n2562), .A2(n2513), .B0(n2617), .B1(n2561),
.Y(mult_x_254_n167) );
OAI32X1TS U2439 ( .A0(FPMULT_Op_MX[0]), .A1(n2260), .A2(n2309), .B0(n2575),
.B1(n2210), .Y(mult_x_254_n228) );
OAI32X1TS U2440 ( .A0(FPMULT_Op_MX[0]), .A1(n2258), .A2(n2309), .B0(n2631),
.B1(n2210), .Y(n2638) );
OAI32X1TS U2441 ( .A0(n2624), .A1(FPMULT_Op_MY[0]), .A2(n2623), .B0(n2508),
.B1(n2624), .Y(n2625) );
INVX2TS U2442 ( .A(n2795), .Y(n2793) );
INVX2TS U2443 ( .A(n2798), .Y(n2791) );
INVX2TS U2444 ( .A(n2871), .Y(n2868) );
INVX2TS U2445 ( .A(n2848), .Y(n2847) );
INVX2TS U2446 ( .A(n2874), .Y(n2875) );
INVX2TS U2447 ( .A(n2788), .Y(n2787) );
CLKINVX6TS U2448 ( .A(n2876), .Y(n2873) );
BUFX4TS U2449 ( .A(n2701), .Y(n2887) );
ADDHXLTS U2450 ( .A(n2865), .B(n2864), .CO(n2861), .S(
DP_OP_454J221_123_2743_n142) );
BUFX4TS U2451 ( .A(n2697), .Y(n2883) );
CLKINVX6TS U2452 ( .A(n2835), .Y(n2836) );
BUFX4TS U2453 ( .A(n2640), .Y(n2846) );
OAI32X1TS U2454 ( .A0(n2449), .A1(n2268), .A2(n2454), .B0(n2353), .B1(n2449),
.Y(n2450) );
NAND2BXLTS U2455 ( .AN(n3417), .B(n3416), .Y(n3535) );
NAND2BXLTS U2456 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n3149) );
AOI221X1TS U2457 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n4644), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n4566), .C0(n3153), .Y(n3155) );
AOI221X1TS U2458 ( .A0(n4574), .A1(FPADDSUB_intDY_EWSW[9]), .B0(
FPADDSUB_intDY_EWSW[30]), .B1(n4682), .C0(n4400), .Y(n4408) );
INVX2TS U2459 ( .A(n3471), .Y(n4070) );
OAI21X1TS U2460 ( .A0(n3031), .A1(n3926), .B0(n3030), .Y(n3034) );
NAND2BX1TS U2461 ( .AN(intadd_499_SUM_21_), .B(n3860), .Y(n3030) );
NOR2X1TS U2462 ( .A(n3588), .B(n3587), .Y(n3586) );
AOI211X1TS U2463 ( .A0(n4760), .A1(FPSENCOS_cont_iter_out[2]), .B0(
FPSENCOS_cont_iter_out[3]), .C0(n4122), .Y(n4085) );
OAI222X1TS U2464 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(FPADDSUB_Raw_mant_NRM_SWR[13]),
.B1(n4186), .C0(FPADDSUB_Raw_mant_NRM_SWR[12]), .C1(n3599), .Y(n3641)
);
NOR2X1TS U2465 ( .A(n2911), .B(n2912), .Y(n4352) );
AO21X1TS U2466 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(FPADDSUB_DmP_mant_SFG_SWR[5]),
.B0(n3099), .Y(n4433) );
CLKINVX6TS U2467 ( .A(n4153), .Y(n3825) );
OAI222X1TS U2468 ( .A0(n4014), .A1(FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n3599), .C0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .C1(n4186), .Y(n3582) );
AO22XLTS U2469 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n3273), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n4481), .Y(n4486) );
OAI32X1TS U2470 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[5]), .A2(n4530),
.B0(n2574), .B1(n2210), .Y(mult_x_254_n232) );
BUFX4TS U2471 ( .A(n2309), .Y(n4530) );
NOR2XLTS U2472 ( .A(n2771), .B(n2887), .Y(DP_OP_454J221_123_2743_n200) );
NOR2XLTS U2473 ( .A(n2771), .B(n2883), .Y(DP_OP_454J221_123_2743_n214) );
CLKINVX6TS U2474 ( .A(n2807), .Y(n2808) );
OAI32X1TS U2475 ( .A0(FPMULT_Op_MX[12]), .A1(n2261), .A2(n2273), .B0(n2317),
.B1(n2208), .Y(n2325) );
CLKBUFX3TS U2476 ( .A(n3224), .Y(n3396) );
AOI31X1TS U2477 ( .A0(n3539), .A1(n2225), .A2(n3538), .B0(n2195), .Y(n4016)
);
AOI211X1TS U2478 ( .A0(n3545), .A1(n3544), .B0(n2265), .C0(n3543), .Y(n3553)
);
BUFX4TS U2479 ( .A(n4115), .Y(n4117) );
AOI2BB2XLTS U2480 ( .B0(n4446), .B1(n4445), .A0N(n4445), .A1N(n4444), .Y(
n4449) );
AO22XLTS U2481 ( .A0(n4343), .A1(FPMULT_P_Sgf[30]), .B0(n4342), .B1(n3022),
.Y(n1559) );
AO22XLTS U2482 ( .A0(n4333), .A1(FPMULT_P_Sgf[34]), .B0(n4342), .B1(n3032),
.Y(n1563) );
AO22XLTS U2483 ( .A0(n4284), .A1(n4263), .B0(n4299), .B1(
FPMULT_Add_result[6]), .Y(n1614) );
AO22XLTS U2484 ( .A0(n4284), .A1(n4266), .B0(n4299), .B1(
FPMULT_Add_result[8]), .Y(n1612) );
AO22XLTS U2485 ( .A0(n4284), .A1(n4271), .B0(n4299), .B1(
FPMULT_Add_result[10]), .Y(n1610) );
AO22XLTS U2486 ( .A0(n4284), .A1(n4280), .B0(n4299), .B1(
FPMULT_Add_result[14]), .Y(n1606) );
AO22XLTS U2487 ( .A0(n4072), .A1(n4468), .B0(n4074), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2144) );
NAND2BXLTS U2488 ( .AN(n4330), .B(n4329), .Y(n4331) );
NAND2BXLTS U2489 ( .AN(n2988), .B(n2987), .Y(n2975) );
AO22XLTS U2490 ( .A0(n4284), .A1(n4283), .B0(n4299), .B1(
FPMULT_Add_result[16]), .Y(n1604) );
OAI21XLTS U2491 ( .A0(n4717), .A1(n4284), .B0(n3674), .Y(n1603) );
AO22XLTS U2492 ( .A0(Data_1[30]), .A1(n4009), .B0(n4224), .B1(
FPMULT_Op_MX[30]), .Y(n1688) );
AO22XLTS U2493 ( .A0(Data_1[29]), .A1(n4009), .B0(n4224), .B1(
FPMULT_Op_MX[29]), .Y(n1687) );
AO22XLTS U2494 ( .A0(Data_1[26]), .A1(n4009), .B0(n4223), .B1(
FPMULT_Op_MX[26]), .Y(n1684) );
AO22XLTS U2495 ( .A0(Data_1[25]), .A1(n4009), .B0(n4223), .B1(
FPMULT_Op_MX[25]), .Y(n1683) );
AO22XLTS U2496 ( .A0(Data_1[23]), .A1(n4009), .B0(n4223), .B1(
FPMULT_Op_MX[23]), .Y(n1681) );
AO22XLTS U2497 ( .A0(Data_2[29]), .A1(n4009), .B0(n4223), .B1(
FPMULT_Op_MY[29]), .Y(n1655) );
AO22XLTS U2498 ( .A0(Data_2[28]), .A1(n4009), .B0(n4223), .B1(
FPMULT_Op_MY[28]), .Y(n1654) );
AO22XLTS U2499 ( .A0(Data_2[27]), .A1(n4009), .B0(n4223), .B1(
FPMULT_Op_MY[27]), .Y(n1653) );
AO22XLTS U2500 ( .A0(n4074), .A1(busy), .B0(n4072), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2145) );
AO22XLTS U2501 ( .A0(Data_2[23]), .A1(n4009), .B0(n4248), .B1(
FPMULT_Op_MY[23]), .Y(n1649) );
AO22XLTS U2502 ( .A0(n4209), .A1(result_add_subt[15]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(n2027) );
AO22XLTS U2503 ( .A0(n4343), .A1(FPMULT_P_Sgf[32]), .B0(n4342), .B1(n3027),
.Y(n1561) );
AO22XLTS U2504 ( .A0(Data_1[24]), .A1(n4009), .B0(n4223), .B1(
FPMULT_Op_MX[24]), .Y(n1682) );
AO22XLTS U2505 ( .A0(Data_2[24]), .A1(n4009), .B0(n2310), .B1(
FPMULT_Op_MY[24]), .Y(n1650) );
OAI211XLTS U2506 ( .A0(n4310), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[19]),
.B0(n4344), .C0(n4309), .Y(n4311) );
AO22XLTS U2507 ( .A0(Data_2[25]), .A1(n4009), .B0(n4222), .B1(
FPMULT_Op_MY[25]), .Y(n1651) );
NAND2BXLTS U2508 ( .AN(n3015), .B(n3016), .Y(n3013) );
AO22XLTS U2509 ( .A0(Data_2[30]), .A1(n4009), .B0(n4223), .B1(
FPMULT_Op_MY[30]), .Y(n1656) );
OAI21XLTS U2510 ( .A0(n4323), .A1(n4322), .B0(n4321), .Y(n4324) );
AO22XLTS U2511 ( .A0(Data_1[27]), .A1(n4009), .B0(n4223), .B1(
FPMULT_Op_MX[27]), .Y(n1685) );
AO22XLTS U2512 ( .A0(n4225), .A1(Data_1[3]), .B0(n4223), .B1(FPMULT_Op_MX[3]), .Y(n1661) );
AO22XLTS U2513 ( .A0(n4225), .A1(Data_1[7]), .B0(n4222), .B1(FPMULT_Op_MX[7]), .Y(n1665) );
AO22XLTS U2514 ( .A0(n4009), .A1(Data_1[15]), .B0(n4222), .B1(
FPMULT_Op_MX[15]), .Y(n1673) );
AO22XLTS U2515 ( .A0(n4221), .A1(Data_1[19]), .B0(n4222), .B1(
FPMULT_Op_MX[19]), .Y(n1677) );
AO22XLTS U2516 ( .A0(n4225), .A1(Data_1[5]), .B0(n4222), .B1(FPMULT_Op_MX[5]), .Y(n1663) );
AO22XLTS U2517 ( .A0(n4225), .A1(Data_1[9]), .B0(n4222), .B1(FPMULT_Op_MX[9]), .Y(n1667) );
AO22XLTS U2518 ( .A0(n4221), .A1(Data_1[17]), .B0(n4224), .B1(
FPMULT_Op_MX[17]), .Y(n1675) );
AO22XLTS U2519 ( .A0(n4221), .A1(Data_1[21]), .B0(n2310), .B1(
FPMULT_Op_MX[21]), .Y(n1679) );
AO22XLTS U2520 ( .A0(n4225), .A1(Data_1[8]), .B0(n4222), .B1(n2255), .Y(
n1666) );
AO22XLTS U2521 ( .A0(n4009), .A1(Data_1[16]), .B0(n2310), .B1(n2256), .Y(
n1674) );
AO22XLTS U2522 ( .A0(n4221), .A1(Data_1[20]), .B0(n4222), .B1(
FPMULT_Op_MX[20]), .Y(n1678) );
AO22XLTS U2523 ( .A0(n4225), .A1(Data_1[2]), .B0(n4223), .B1(FPMULT_Op_MX[2]), .Y(n1660) );
OAI211XLTS U2524 ( .A0(n3821), .A1(n4744), .B0(n3804), .C0(n3803), .Y(n1839)
);
AO22XLTS U2525 ( .A0(n4225), .A1(Data_2[15]), .B0(n2310), .B1(n2261), .Y(
n1641) );
AO22XLTS U2526 ( .A0(n4225), .A1(Data_2[14]), .B0(n2310), .B1(
FPMULT_Op_MY[14]), .Y(n1640) );
AO22XLTS U2527 ( .A0(n4225), .A1(Data_1[0]), .B0(n4223), .B1(FPMULT_Op_MX[0]), .Y(n1658) );
OAI31X1TS U2528 ( .A0(n4609), .A1(n4122), .A2(n2900), .B0(n2899), .Y(n2115)
);
AO22XLTS U2529 ( .A0(n4225), .A1(Data_1[12]), .B0(n4222), .B1(
FPMULT_Op_MX[12]), .Y(n1670) );
AO22XLTS U2530 ( .A0(Data_1[28]), .A1(n4009), .B0(n4224), .B1(
FPMULT_Op_MX[28]), .Y(n1686) );
AO22XLTS U2531 ( .A0(n4221), .A1(Data_1[22]), .B0(n2310), .B1(
FPMULT_Op_MX[22]), .Y(n1680) );
AO22XLTS U2532 ( .A0(n4225), .A1(Data_2[1]), .B0(n4248), .B1(FPMULT_Op_MY[1]), .Y(n1627) );
AO22XLTS U2533 ( .A0(n4225), .A1(Data_2[3]), .B0(n4248), .B1(FPMULT_Op_MY[3]), .Y(n1629) );
AO22XLTS U2534 ( .A0(n4225), .A1(Data_2[2]), .B0(n4248), .B1(FPMULT_Op_MY[2]), .Y(n1628) );
AO22XLTS U2535 ( .A0(n4225), .A1(Data_2[5]), .B0(n4248), .B1(FPMULT_Op_MY[5]), .Y(n1631) );
AO22XLTS U2536 ( .A0(n4225), .A1(Data_2[13]), .B0(n4224), .B1(
FPMULT_Op_MY[13]), .Y(n1639) );
AO22XLTS U2537 ( .A0(n4221), .A1(Data_1[13]), .B0(n4222), .B1(
FPMULT_Op_MX[13]), .Y(n1671) );
OAI211XLTS U2538 ( .A0(n4307), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[21]),
.B0(n4344), .C0(n4306), .Y(n4308) );
AO22XLTS U2539 ( .A0(n4209), .A1(result_add_subt[31]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[31]), .Y(n1727) );
AO22XLTS U2540 ( .A0(n4209), .A1(result_add_subt[23]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(n1784) );
AO22XLTS U2541 ( .A0(n4209), .A1(result_add_subt[30]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(n1729) );
AO22XLTS U2542 ( .A0(n4209), .A1(result_add_subt[22]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(n2006) );
AO22XLTS U2543 ( .A0(n4194), .A1(result_add_subt[18]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(n2018) );
AO22XLTS U2544 ( .A0(n4209), .A1(result_add_subt[21]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(n2009) );
AO22XLTS U2545 ( .A0(n4209), .A1(result_add_subt[4]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(n2060) );
AO22XLTS U2546 ( .A0(n4194), .A1(result_add_subt[8]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(n2048) );
AO22XLTS U2547 ( .A0(n4194), .A1(result_add_subt[11]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(n2039) );
AO22XLTS U2548 ( .A0(n4209), .A1(result_add_subt[0]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(n2072) );
AO22XLTS U2549 ( .A0(n4209), .A1(result_add_subt[9]), .B0(n4189), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(n2045) );
OAI211XLTS U2550 ( .A0(n4313), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[17]),
.B0(n4344), .C0(n4312), .Y(n4314) );
AO22XLTS U2551 ( .A0(Data_2[26]), .A1(n4009), .B0(n2310), .B1(
FPMULT_Op_MY[26]), .Y(n1652) );
AO22XLTS U2552 ( .A0(n4343), .A1(FPMULT_P_Sgf[29]), .B0(n3089), .B1(n3019),
.Y(n1558) );
OAI211XLTS U2553 ( .A0(n3821), .A1(n4713), .B0(n3691), .C0(n3690), .Y(n1911)
);
OAI211XLTS U2554 ( .A0(n3821), .A1(n4738), .B0(n3687), .C0(n3686), .Y(n1910)
);
AO22XLTS U2555 ( .A0(n4474), .A1(FPADDSUB_DMP_SHT2_EWSW[0]), .B0(n4473),
.B1(FPADDSUB_DMP_SFG[0]), .Y(n1293) );
AO22XLTS U2556 ( .A0(n4249), .A1(Data_1[4]), .B0(n4248), .B1(FPMULT_Op_MX[4]), .Y(n1662) );
AO22XLTS U2557 ( .A0(n4249), .A1(Data_1[6]), .B0(n4222), .B1(FPMULT_Op_MX[6]), .Y(n1664) );
AO22XLTS U2558 ( .A0(n4221), .A1(Data_1[18]), .B0(n4224), .B1(
FPMULT_Op_MX[18]), .Y(n1676) );
AO22XLTS U2559 ( .A0(n4221), .A1(Data_1[14]), .B0(n4222), .B1(
FPMULT_Op_MX[14]), .Y(n1672) );
NAND3XLTS U2560 ( .A(n4178), .B(n4177), .C(n4179), .Y(n1815) );
AO22XLTS U2561 ( .A0(n4249), .A1(Data_1[10]), .B0(n4222), .B1(
FPMULT_Op_MX[10]), .Y(n1668) );
AOI2BB2XLTS U2562 ( .B0(n3883), .B1(n3880), .A0N(n3880), .A1N(n3883), .Y(
n3886) );
NAND3XLTS U2563 ( .A(n4176), .B(n4175), .C(n4179), .Y(n1816) );
NAND3XLTS U2564 ( .A(n4156), .B(n4155), .C(n4154), .Y(n1827) );
OAI211XLTS U2565 ( .A0(n3821), .A1(n4747), .B0(n3797), .C0(n3796), .Y(n1834)
);
NAND3XLTS U2566 ( .A(n4139), .B(n4138), .C(n4148), .Y(n1838) );
NAND3XLTS U2567 ( .A(n4142), .B(n4141), .C(n4143), .Y(n1836) );
AO22XLTS U2568 ( .A0(n4225), .A1(Data_1[1]), .B0(n4248), .B1(FPMULT_Op_MX[1]), .Y(n1659) );
AO22XLTS U2569 ( .A0(n4225), .A1(Data_2[0]), .B0(n4248), .B1(FPMULT_Op_MY[0]), .Y(n1626) );
OAI21XLTS U2570 ( .A0(n4468), .A1(n4638), .B0(n3837), .Y(n1333) );
OAI21XLTS U2571 ( .A0(n3833), .A1(n3831), .B0(n3830), .Y(n3836) );
OAI211XLTS U2572 ( .A0(n3825), .A1(n4749), .B0(n3818), .C0(n3817), .Y(n1831)
);
OAI211XLTS U2573 ( .A0(n3825), .A1(n4745), .B0(n3824), .C0(n3823), .Y(n1837)
);
OAI211XLTS U2574 ( .A0(n3825), .A1(n2198), .B0(n3816), .C0(n3815), .Y(n1820)
);
OAI211XLTS U2575 ( .A0(n3821), .A1(n4742), .B0(n3820), .C0(n3819), .Y(n1842)
);
NAND3XLTS U2576 ( .A(n4152), .B(n4151), .C(n4168), .Y(n1828) );
NAND3XLTS U2577 ( .A(n4159), .B(n4158), .C(n4168), .Y(n1826) );
NAND3XLTS U2578 ( .A(n4170), .B(n4169), .C(n4168), .Y(n1823) );
OAI211XLTS U2579 ( .A0(n3800), .A1(n4730), .B0(n3748), .C0(n3747), .Y(n1937)
);
OAI211XLTS U2580 ( .A0(n3800), .A1(n2236), .B0(n3726), .C0(n3725), .Y(n1934)
);
NAND3XLTS U2581 ( .A(n4135), .B(n4134), .C(n4154), .Y(n1840) );
NAND3XLTS U2582 ( .A(n4145), .B(n4144), .C(n4143), .Y(n1832) );
NAND3XLTS U2583 ( .A(n4147), .B(n4146), .C(n4160), .Y(n1830) );
NAND3XLTS U2584 ( .A(n4150), .B(n4149), .C(n4148), .Y(n1829) );
NAND3XLTS U2585 ( .A(n4162), .B(n4161), .C(n4160), .Y(n1825) );
NAND3XLTS U2586 ( .A(n4166), .B(n4165), .C(n4171), .Y(n1824) );
NAND3XLTS U2587 ( .A(n4173), .B(n4172), .C(n4171), .Y(n1821) );
NAND3XLTS U2588 ( .A(n4181), .B(n4180), .C(n4179), .Y(n1814) );
OAI211XLTS U2589 ( .A0(n3825), .A1(n4734), .B0(n3710), .C0(n3709), .Y(n1926)
);
OAI211XLTS U2590 ( .A0(n3800), .A1(n2196), .B0(n3735), .C0(n3734), .Y(n1938)
);
OAI21XLTS U2591 ( .A0(n3887), .A1(n3757), .B0(n3756), .Y(n1335) );
OAI211XLTS U2592 ( .A0(n3800), .A1(n4732), .B0(n3720), .C0(n3719), .Y(n1932)
);
OAI31X1TS U2593 ( .A0(n4078), .A1(FPSENCOS_cont_var_out[1]), .A2(n3986),
.B0(n3985), .Y(n2136) );
OAI211XLTS U2594 ( .A0(n3821), .A1(n4716), .B0(n3695), .C0(n3694), .Y(n1914)
);
OAI211XLTS U2595 ( .A0(n3825), .A1(n4735), .B0(n3712), .C0(n3711), .Y(n1923)
);
OAI211XLTS U2596 ( .A0(n3800), .A1(n4729), .B0(n3750), .C0(n3749), .Y(n1941)
);
OAI211XLTS U2597 ( .A0(n3821), .A1(n4721), .B0(n3697), .C0(n3696), .Y(n1916)
);
OAI21XLTS U2598 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(n4622), .B0(n3859),
.Y(n1331) );
OAI21XLTS U2599 ( .A0(n3875), .A1(n3873), .B0(n3872), .Y(n3878) );
OAI211XLTS U2600 ( .A0(n3825), .A1(n4736), .B0(n3701), .C0(n3700), .Y(n1920)
);
OAI211XLTS U2601 ( .A0(n3821), .A1(n4720), .B0(n3699), .C0(n3698), .Y(n1917)
);
OAI211XLTS U2602 ( .A0(n3821), .A1(n4722), .B0(n3689), .C0(n3688), .Y(n1915)
);
OAI211XLTS U2603 ( .A0(n3800), .A1(n4733), .B0(n3731), .C0(n3730), .Y(n1930)
);
OAI211XLTS U2604 ( .A0(n3825), .A1(n2237), .B0(n3705), .C0(n3704), .Y(n1921)
);
OAI211XLTS U2605 ( .A0(n3800), .A1(n4731), .B0(n3733), .C0(n3732), .Y(n1933)
);
OAI211XLTS U2606 ( .A0(n3825), .A1(n4737), .B0(n3714), .C0(n3713), .Y(n1919)
);
OAI211XLTS U2607 ( .A0(n3800), .A1(n2197), .B0(n3737), .C0(n3736), .Y(n1935)
);
XOR2XLTS U2608 ( .A(n2560), .B(n2559), .Y(
FPMULT_Sgf_operation_EVEN1_right_N23) );
OAI21XLTS U2609 ( .A0(n2206), .A1(n2765), .B0(n2766), .Y(n2764) );
OAI21XLTS U2610 ( .A0(n2220), .A1(n2449), .B0(n2406), .Y(n2405) );
AO22XLTS U2611 ( .A0(n4345), .A1(FPMULT_P_Sgf[0]), .B0(n4344), .B1(
FPMULT_Sgf_operation_Result[0]), .Y(n1529) );
AO22XLTS U2612 ( .A0(n4343), .A1(FPMULT_P_Sgf[1]), .B0(n4344), .B1(
FPMULT_Sgf_operation_Result[1]), .Y(n1530) );
NAND2BXLTS U2613 ( .AN(n4339), .B(n4338), .Y(n4340) );
NAND2BXLTS U2614 ( .AN(n4335), .B(n4334), .Y(n4336) );
NAND2BXLTS U2615 ( .AN(n2957), .B(n2956), .Y(n2952) );
NAND2BXLTS U2616 ( .AN(n2967), .B(n2966), .Y(n2959) );
NAND2BXLTS U2617 ( .AN(n2973), .B(n2972), .Y(n2969) );
OAI21XLTS U2618 ( .A0(n3829), .A1(n4011), .B0(n3828), .Y(n1557) );
NAND2BXLTS U2619 ( .AN(n3889), .B(n3888), .Y(n3890) );
AO22XLTS U2620 ( .A0(n4225), .A1(Data_2[7]), .B0(n2310), .B1(n2258), .Y(
n1633) );
AO22XLTS U2621 ( .A0(n4225), .A1(Data_2[9]), .B0(n4224), .B1(n2260), .Y(
n1635) );
AO22XLTS U2622 ( .A0(n4225), .A1(Data_2[12]), .B0(n4224), .B1(n2268), .Y(
n1638) );
AO22XLTS U2623 ( .A0(FPMULT_FSM_add_overflow_flag), .A1(n4299), .B0(n4298),
.B1(FPMULT_Sgf_normalized_result[23]), .Y(n1596) );
AO22XLTS U2624 ( .A0(n3052), .A1(FPMULT_Add_result[18]), .B0(n4296), .B1(
n4287), .Y(n1602) );
AO22XLTS U2625 ( .A0(n3052), .A1(FPMULT_Add_result[20]), .B0(n4296), .B1(
n4291), .Y(n1600) );
AO22XLTS U2626 ( .A0(n4108), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n4129),
.B1(FPSENCOS_d_ff2_Y[9]), .Y(n1888) );
AO22XLTS U2627 ( .A0(n4119), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n4129),
.B1(FPSENCOS_d_ff2_Y[1]), .Y(n1904) );
AO22XLTS U2628 ( .A0(n4108), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n4129),
.B1(FPSENCOS_d_ff2_Y[0]), .Y(n1906) );
AO22XLTS U2629 ( .A0(n4119), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n4118),
.B1(FPSENCOS_d_ff2_Y[2]), .Y(n1902) );
AO22XLTS U2630 ( .A0(n4119), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n4129),
.B1(FPSENCOS_d_ff2_Y[12]), .Y(n1882) );
AO22XLTS U2631 ( .A0(n4119), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n2898),
.B1(FPSENCOS_d_ff2_Y[10]), .Y(n1886) );
AO22XLTS U2632 ( .A0(n4119), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n2898),
.B1(FPSENCOS_d_ff2_Y[8]), .Y(n1890) );
AO22XLTS U2633 ( .A0(n4108), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n4129),
.B1(FPSENCOS_d_ff2_Y[6]), .Y(n1894) );
AO22XLTS U2634 ( .A0(n4108), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n2898),
.B1(FPSENCOS_d_ff2_Y[4]), .Y(n1898) );
AO22XLTS U2635 ( .A0(n4108), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n4129),
.B1(FPSENCOS_d_ff2_Y[21]), .Y(n1864) );
OAI211XLTS U2636 ( .A0(n3821), .A1(n4584), .B0(n3683), .C0(n3682), .Y(n1913)
);
OR2X1TS U2637 ( .A(n4617), .B(n2264), .Y(n2204) );
OR2X1TS U2638 ( .A(n2194), .B(n2231), .Y(n2205) );
NOR2X4TS U2639 ( .A(n2263), .B(n2699), .Y(n2206) );
OR2X1TS U2640 ( .A(n3562), .B(n3555), .Y(n2224) );
OR4X2TS U2641 ( .A(FPADDSUB_Raw_mant_NRM_SWR[17]), .B(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C(FPADDSUB_Raw_mant_NRM_SWR[16]), .D(
n3535), .Y(n2225) );
AOI22X1TS U2642 ( .A0(n4249), .A1(Data_1[11]), .B0(n4222), .B1(
FPMULT_Op_MX[11]), .Y(n2226) );
OR2X1TS U2643 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n2227) );
AOI21X2TS U2644 ( .A0(n3638), .A1(n4622), .B0(n3637), .Y(n2229) );
BUFX4TS U2645 ( .A(n4301), .Y(n4348) );
CLKINVX3TS U2646 ( .A(n3556), .Y(n2238) );
CLKINVX3TS U2647 ( .A(n3556), .Y(n2239) );
INVX2TS U2648 ( .A(n4348), .Y(n2240) );
INVX2TS U2649 ( .A(n2240), .Y(n2241) );
OAI221X1TS U2650 ( .A0(FPADDSUB_intDX_EWSW[6]), .A1(n4689), .B0(n4688), .B1(
FPADDSUB_intDY_EWSW[6]), .C0(n4399), .Y(n4410) );
NOR4X2TS U2651 ( .A(FPADDSUB_Raw_mant_NRM_SWR[17]), .B(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C(FPADDSUB_Raw_mant_NRM_SWR[16]), .D(
FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n3417) );
OAI221X4TS U2652 ( .A0(FPMULT_Op_MX[20]), .A1(n2442), .B0(n2278), .B1(n2449),
.C0(n2454), .Y(n2353) );
CLKINVX6TS U2653 ( .A(n2442), .Y(n2449) );
AOI32X1TS U2654 ( .A0(FPSENCOS_d_ff3_sign_out), .A1(n4201), .A2(n4200), .B0(
n4199), .B1(n4201), .Y(n1731) );
AOI21X2TS U2655 ( .A0(n3597), .A1(n4638), .B0(n3569), .Y(n3645) );
NOR2XLTS U2656 ( .A(n4298), .B(n3839), .Y(n1598) );
AOI21X2TS U2657 ( .A0(n3597), .A1(n4696), .B0(n3567), .Y(n3655) );
AOI21X2TS U2658 ( .A0(n3597), .A1(n4639), .B0(n3575), .Y(n3668) );
BUFX6TS U2659 ( .A(n3679), .Y(n3746) );
BUFX6TS U2660 ( .A(n3679), .Y(n4163) );
BUFX4TS U2661 ( .A(n3679), .Y(n4205) );
OAI21X2TS U2662 ( .A0(n4687), .A1(n4186), .B0(n3560), .Y(n3633) );
INVX4TS U2663 ( .A(n3597), .Y(n4186) );
NOR2XLTS U2664 ( .A(n4321), .B(n2921), .Y(n2922) );
BUFX4TS U2665 ( .A(n4342), .Y(n4321) );
NOR2XLTS U2666 ( .A(n2954), .B(n4121), .Y(n2955) );
BUFX4TS U2667 ( .A(n3240), .Y(n4121) );
INVX3TS U2668 ( .A(n3396), .Y(n3413) );
CLKINVX3TS U2669 ( .A(n2224), .Y(n2242) );
INVX3TS U2670 ( .A(n2224), .Y(n2243) );
OAI21X1TS U2671 ( .A0(n4686), .A1(n3300), .B0(n3307), .Y(n3301) );
OAI21X1TS U2672 ( .A0(n4683), .A1(n3300), .B0(n3307), .Y(n3296) );
OAI211XLTS U2673 ( .A0(n3800), .A1(n2296), .B0(n3724), .C0(n3723), .Y(n1936)
);
OAI211XLTS U2674 ( .A0(n3800), .A1(n2294), .B0(n3739), .C0(n3738), .Y(n1939)
);
OAI211XLTS U2675 ( .A0(n3825), .A1(n2302), .B0(n3722), .C0(n3721), .Y(n1929)
);
OAI211XLTS U2676 ( .A0(n3800), .A1(n2288), .B0(n3729), .C0(n3728), .Y(n1931)
);
OAI211XLTS U2677 ( .A0(n3825), .A1(n2282), .B0(n3743), .C0(n3742), .Y(n1927)
);
OAI211XLTS U2678 ( .A0(n3825), .A1(n2295), .B0(n3745), .C0(n3744), .Y(n1928)
);
OAI211XLTS U2679 ( .A0(n3825), .A1(n2276), .B0(n3703), .C0(n3702), .Y(n1924)
);
OAI211XLTS U2680 ( .A0(n3825), .A1(n2271), .B0(n3707), .C0(n3706), .Y(n1922)
);
NOR2X1TS U2681 ( .A(FPMULT_Op_MY[22]), .B(n2365), .Y(mult_x_219_n151) );
NOR2X1TS U2682 ( .A(n2455), .B(n2364), .Y(mult_x_219_n162) );
CLKINVX6TS U2683 ( .A(n2757), .Y(n2753) );
OAI211XLTS U2684 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4278), .B0(
n4296), .C0(n4282), .Y(n3585) );
CLKINVX6TS U2685 ( .A(n4299), .Y(n4296) );
BUFX4TS U2686 ( .A(n3507), .Y(n3513) );
BUFX3TS U2687 ( .A(n3476), .Y(n3507) );
OAI32X1TS U2688 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[4]), .A2(n2309),
.B0(n2472), .B1(n2210), .Y(n2607) );
OAI32X1TS U2689 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[20]), .A2(n2273),
.B0(n2448), .B1(n2208), .Y(n2451) );
AOI21X2TS U2690 ( .A0(n3638), .A1(n4638), .B0(n3579), .Y(n3662) );
AOI21X2TS U2691 ( .A0(n3638), .A1(n4639), .B0(n3572), .Y(n3631) );
BUFX4TS U2692 ( .A(n3051), .Y(n3638) );
BUFX4TS U2693 ( .A(n2929), .Y(n4816) );
AOI222X4TS U2694 ( .A0(n3366), .A1(FPADDSUB_intDY_EWSW[24]), .B0(
FPADDSUB_DmP_EXP_EWSW[24]), .B1(n4549), .C0(FPADDSUB_intDX_EWSW[24]),
.C1(n3327), .Y(n3328) );
AOI222X4TS U2695 ( .A0(n3366), .A1(FPADDSUB_intDY_EWSW[25]), .B0(
FPADDSUB_DmP_EXP_EWSW[25]), .B1(n4549), .C0(FPADDSUB_intDX_EWSW[25]),
.C1(n3327), .Y(n3326) );
AOI222X1TS U2696 ( .A0(n3366), .A1(FPADDSUB_intDY_EWSW[26]), .B0(
FPADDSUB_DmP_EXP_EWSW[26]), .B1(n4549), .C0(FPADDSUB_intDX_EWSW[26]),
.C1(n3368), .Y(n3325) );
AOI222X4TS U2697 ( .A0(n3368), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DMP_EXP_EWSW[23]), .B1(n4549), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n3366), .Y(n3369) );
OAI31X1TS U2698 ( .A0(n4080), .A1(n4609), .A2(n4122), .B0(n2902), .Y(n2133)
);
AOI21X2TS U2699 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n4559), .B0(n2963),
.Y(n4080) );
BUFX4TS U2700 ( .A(n2201), .Y(n4827) );
NOR2X2TS U2701 ( .A(n4634), .B(n4282), .Y(n4281) );
NOR2X2TS U2702 ( .A(n4600), .B(n4262), .Y(n4261) );
NOR2X2TS U2703 ( .A(n4265), .B(n4264), .Y(n4267) );
NOR2X2TS U2704 ( .A(n4276), .B(n4275), .Y(n4274) );
NOR2X2TS U2705 ( .A(n4286), .B(n4285), .Y(n4288) );
BUFX6TS U2706 ( .A(n2922), .Y(n3143) );
NOR4X1TS U2707 ( .A(FPMULT_Op_MY[6]), .B(n2258), .C(FPMULT_Op_MY[8]), .D(
n2260), .Y(n4230) );
NOR4X1TS U2708 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[11]), .C(
FPMULT_Op_MX[12]), .D(FPMULT_Op_MX[13]), .Y(n4239) );
NOR4X1TS U2709 ( .A(FPMULT_Op_MY[10]), .B(n2263), .C(n2268), .D(
FPMULT_Op_MY[13]), .Y(n4231) );
NOR4X1TS U2710 ( .A(FPMULT_Op_MY[14]), .B(n2261), .C(FPMULT_Op_MY[16]), .D(
FPMULT_Op_MY[17]), .Y(n4228) );
NOR2X2TS U2711 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .Y(n3482) );
BUFX4TS U2712 ( .A(n4811), .Y(n4805) );
BUFX4TS U2713 ( .A(n4798), .Y(n4791) );
NOR4X1TS U2714 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[19]), .C(
FPMULT_Op_MY[20]), .D(FPMULT_Op_MY[21]), .Y(n4229) );
BUFX4TS U2715 ( .A(n4814), .Y(n4790) );
BUFX4TS U2716 ( .A(n4817), .Y(n4796) );
BUFX4TS U2717 ( .A(n4809), .Y(n4793) );
INVX2TS U2718 ( .A(n4076), .Y(n2253) );
BUFX3TS U2719 ( .A(n2929), .Y(n2930) );
BUFX4TS U2720 ( .A(n2929), .Y(n4809) );
BUFX4TS U2721 ( .A(n2929), .Y(n4795) );
BUFX4TS U2722 ( .A(n2929), .Y(n4810) );
BUFX4TS U2723 ( .A(n4799), .Y(n4814) );
BUFX4TS U2724 ( .A(n4808), .Y(n4817) );
OAI32X1TS U2725 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[22]), .A2(n2453),
.B0(FPMULT_Op_MX[13]), .B1(n2208), .Y(n2366) );
BUFX4TS U2726 ( .A(n4801), .Y(n4792) );
BUFX4TS U2727 ( .A(n4819), .Y(n4820) );
BUFX4TS U2728 ( .A(n2202), .Y(n4798) );
BUFX4TS U2729 ( .A(n4806), .Y(n4794) );
BUFX4TS U2730 ( .A(n4817), .Y(n4797) );
AOI21X2TS U2731 ( .A0(n4559), .A1(intadd_501_B_1_), .B0(n3439), .Y(n3440) );
BUFX4TS U2732 ( .A(n2930), .Y(n4806) );
INVX4TS U2733 ( .A(n2310), .Y(n4249) );
CLKINVX6TS U2734 ( .A(n2310), .Y(n4225) );
BUFX4TS U2735 ( .A(n4812), .Y(n4800) );
BUFX4TS U2736 ( .A(n2931), .Y(n4787) );
OAI21X2TS U2737 ( .A0(n4687), .A1(n3599), .B0(n3598), .Y(n3625) );
CLKINVX6TS U2738 ( .A(n3638), .Y(n3599) );
NOR4BX2TS U2739 ( .AN(n2971), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3406) );
NOR4X2TS U2740 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n2916) );
NAND2X4TS U2741 ( .A(n4247), .B(n4011), .Y(n4010) );
OAI32X1TS U2742 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[17]), .A2(n2453),
.B0(n2418), .B1(n2208), .Y(mult_x_219_n226) );
OAI22X2TS U2743 ( .A0(n2905), .A1(n3751), .B0(FPADDSUB_DmP_mant_SFG_SWR[14]),
.B1(n4601), .Y(n4444) );
OAI22X2TS U2744 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(n2298), .B0(n2904), .B1(
n4440), .Y(n3751) );
CLKINVX3TS U2745 ( .A(n3563), .Y(n3670) );
OAI221X4TS U2746 ( .A0(FPMULT_Op_MX[6]), .A1(n2563), .B0(n2272), .B1(n2624),
.C0(n2623), .Y(n2508) );
CLKINVX6TS U2747 ( .A(n2563), .Y(n2624) );
BUFX4TS U2748 ( .A(n2201), .Y(n4821) );
BUFX4TS U2749 ( .A(n2201), .Y(n4828) );
BUFX4TS U2750 ( .A(n2201), .Y(n4819) );
CLKINVX6TS U2751 ( .A(n2581), .Y(n2564) );
AOI222X1TS U2752 ( .A0(n3141), .A1(n4714), .B0(n2923), .B1(n3125), .C0(n4586), .C1(n3143), .Y(n1621) );
CLKINVX6TS U2753 ( .A(n2920), .Y(n3141) );
CLKINVX6TS U2754 ( .A(n2567), .Y(n2582) );
NOR3BX2TS U2755 ( .AN(n4061), .B(n4055), .C(ready_add_subt), .Y(n4078) );
NAND3X2TS U2756 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n3072),
.C(n3370), .Y(n4061) );
NOR3X2TS U2757 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n2971) );
AO22XLTS U2758 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n4481), .B0(
FPADDSUB_Data_array_SWR[20]), .B1(n3274), .Y(n3294) );
AOI211X1TS U2759 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n4481), .B0(n3312),
.C0(n3311), .Y(n3338) );
AOI211X1TS U2760 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n4481), .B0(n3303),
.C0(n3302), .Y(n3350) );
AOI211X1TS U2761 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n4481), .B0(n3321),
.C0(n3320), .Y(n3332) );
CLKINVX3TS U2762 ( .A(n4379), .Y(n4481) );
NOR4X1TS U2763 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[29]), .C(
FPMULT_Op_MY[28]), .D(FPMULT_Op_MY[27]), .Y(n4226) );
AOI211X1TS U2764 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n3273), .B0(n3315),
.C0(n3314), .Y(n3347) );
AOI211X1TS U2765 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n3273), .B0(n3277),
.C0(n3276), .Y(n3330) );
AOI211X1TS U2766 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n3273), .B0(n3291),
.C0(n3290), .Y(n4489) );
CLKINVX3TS U2767 ( .A(n4362), .Y(n3273) );
BUFX6TS U2768 ( .A(n4137), .Y(n4164) );
BUFX4TS U2769 ( .A(n4137), .Y(n4206) );
NOR3XLTS U2770 ( .A(FPMULT_Op_MY[23]), .B(FPMULT_Op_MY[0]), .C(
FPMULT_Op_MY[1]), .Y(n4232) );
OAI2BB2XLTS U2771 ( .B0(n4203), .B1(n4662), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[18]), .Y(n2019) );
NOR3XLTS U2772 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_Op_MX[0]), .C(
FPMULT_Op_MX[1]), .Y(n4240) );
OAI2BB2XLTS U2773 ( .B0(n4203), .B1(n4664), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[31]), .Y(n1908) );
NOR2X2TS U2774 ( .A(n4557), .B(FPMULT_FS_Module_state_reg[2]), .Y(n4300) );
BUFX6TS U2775 ( .A(n4102), .Y(n4104) );
BUFX6TS U2776 ( .A(n3240), .Y(n4102) );
OAI221X4TS U2777 ( .A0(FPMULT_Op_MX[18]), .A1(n2422), .B0(n2280), .B1(n2445),
.C0(n2444), .Y(n2356) );
BUFX4TS U2778 ( .A(n2355), .Y(n2444) );
NOR2X1TS U2779 ( .A(n2455), .B(n2444), .Y(mult_x_219_n190) );
OAI32X1TS U2780 ( .A0(n2564), .A1(FPMULT_Op_MY[0]), .A2(n2587), .B0(n2463),
.B1(n2564), .Y(n2606) );
BUFX4TS U2781 ( .A(n2462), .Y(n2587) );
INVX2TS U2782 ( .A(n2205), .Y(n2254) );
OAI221X4TS U2783 ( .A0(FPMULT_Op_MX[10]), .A1(n2580), .B0(n2307), .B1(n4529),
.C0(n2617), .Y(n2513) );
NOR2X1TS U2784 ( .A(n2617), .B(n2209), .Y(mult_x_254_n168) );
BUFX4TS U2785 ( .A(n2512), .Y(n2617) );
OAI221X4TS U2786 ( .A0(n2255), .A1(n2621), .B0(n2289), .B1(n2628), .C0(n2632), .Y(n2503) );
OAI32X1TS U2787 ( .A0(n2628), .A1(FPMULT_Op_MY[0]), .A2(n2632), .B0(n2503),
.B1(n2628), .Y(n2629) );
NOR2XLTS U2788 ( .A(n2209), .B(n2632), .Y(n2637) );
BUFX4TS U2789 ( .A(n2502), .Y(n2632) );
OAI32X1TS U2790 ( .A0(n3412), .A1(FPADDSUB_intDX_EWSW[31]), .A2(n4420), .B0(
FPADDSUB_Shift_reg_FLAGS_7_6), .B1(FPADDSUB_OP_FLAG_EXP), .Y(n2932) );
OAI32X1TS U2791 ( .A0(n4418), .A1(FPADDSUB_intDX_EWSW[31]), .A2(n4417), .B0(
FPADDSUB_Shift_reg_FLAGS_7_6), .B1(FPADDSUB_SIGN_FLAG_EXP), .Y(n4419)
);
BUFX4TS U2792 ( .A(n3261), .Y(n4418) );
INVX3TS U2793 ( .A(n4131), .Y(n4122) );
NOR2XLTS U2794 ( .A(n2618), .B(n2216), .Y(n2579) );
INVX3TS U2795 ( .A(FPMULT_Op_MX[11]), .Y(n2618) );
INVX4TS U2796 ( .A(n4089), .Y(n4092) );
CLKINVX3TS U2797 ( .A(n4118), .Y(n4108) );
INVX4TS U2798 ( .A(n4118), .Y(n4132) );
CLKINVX3TS U2799 ( .A(n4118), .Y(n4119) );
NOR4X1TS U2800 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(underflow_flag_mult), .D(n4347),
.Y(n4301) );
NOR4X2TS U2801 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .C(FPADDSUB_Raw_mant_NRM_SWR[23]), .D(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n3432) );
OAI31X1TS U2802 ( .A0(n4427), .A1(FPADDSUB_DmP_mant_SFG_SWR[1]), .A2(
FPADDSUB_DmP_mant_SFG_SWR[0]), .B0(n4428), .Y(n3057) );
XOR2X1TS U2803 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(n4425), .Y(n4426) );
NOR3XLTS U2804 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n4347), .Y(n4303) );
NOR2X2TS U2805 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n4128), .Y(n4127) );
NOR3BX4TS U2806 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(n2896), .Y(n4055) );
NOR3BX2TS U2807 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .C(n2896), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]) );
OAI211XLTS U2808 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4281), .B0(
n4296), .C0(n4285), .Y(n3674) );
NOR4X1TS U2809 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[3]), .C(
FPMULT_Op_MX[4]), .D(FPMULT_Op_MX[5]), .Y(n4241) );
NOR4X1TS U2810 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[7]), .C(n2255), .D(
FPMULT_Op_MX[9]), .Y(n4238) );
NOR4X1TS U2811 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[15]), .C(n2256), .D(
FPMULT_Op_MX[17]), .Y(n4236) );
NOR4X1TS U2812 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[19]), .C(
FPMULT_Op_MX[20]), .D(FPMULT_Op_MX[21]), .Y(n4237) );
INVX2TS U2813 ( .A(n2289), .Y(n2255) );
INVX2TS U2814 ( .A(n2283), .Y(n2256) );
AOI222X1TS U2815 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4575), .B0(n3164), .B1(
n3163), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n4675), .Y(n3166) );
AOI221X1TS U2816 ( .A0(n4575), .A1(FPADDSUB_intDY_EWSW[4]), .B0(
FPADDSUB_intDY_EWSW[24]), .B1(n4667), .C0(n4398), .Y(n4399) );
INVX2TS U2817 ( .A(FPMULT_Op_MY[7]), .Y(n2257) );
CLKINVX3TS U2818 ( .A(n2257), .Y(n2258) );
INVX2TS U2819 ( .A(FPMULT_Op_MY[9]), .Y(n2259) );
CLKINVX3TS U2820 ( .A(n2259), .Y(n2260) );
OAI32X1TS U2821 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[8]), .A2(n2309),
.B0(n2627), .B1(n2210), .Y(n2630) );
OAI32X1TS U2822 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[6]), .A2(n2309),
.B0(n2622), .B1(n2210), .Y(n2626) );
OAI32X1TS U2823 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[19]), .A2(n2453),
.B0(n2452), .B1(n2208), .Y(n2461) );
OAI32X1TS U2824 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[14]), .A2(n2453),
.B0(n2326), .B1(n2208), .Y(n2330) );
OAI32X1TS U2825 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[18]), .A2(n2453),
.B0(n2443), .B1(n2208), .Y(n2447) );
OAI32X1TS U2826 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[16]), .A2(n2453),
.B0(n2322), .B1(n2208), .Y(n2437) );
OAI32X1TS U2827 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[21]), .A2(n2273),
.B0(n2419), .B1(n2208), .Y(mult_x_219_n222) );
OAI32X1TS U2828 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[10]), .A2(n4530),
.B0(n2616), .B1(n2210), .Y(n2620) );
INVX2TS U2829 ( .A(FPMULT_Op_MY[11]), .Y(n2262) );
INVX3TS U2830 ( .A(n2262), .Y(n2263) );
ADDHX4TS U2831 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[0]), .CO(n2645), .S(
DP_OP_454J221_123_2743_n453) );
OAI32X1TS U2832 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[2]), .A2(n4530),
.B0(n2476), .B1(n2210), .Y(n2480) );
OAI32X1TS U2833 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[1]), .A2(n4530),
.B0(n2481), .B1(n2210), .Y(n2615) );
OAI32X1TS U2834 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[3]), .A2(n4530),
.B0(n2467), .B1(n2210), .Y(n2475) );
AOI222X4TS U2835 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(n4594), .B0(
FPADDSUB_DmP_mant_SFG_SWR[6]), .B1(n4434), .C0(n4594), .C1(n4434), .Y(
n3389) );
OAI22X2TS U2836 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(n4551), .B0(n2903), .B1(
n3103), .Y(n4434) );
OAI221X1TS U2837 ( .A0(n4672), .A1(FPADDSUB_intDY_EWSW[11]), .B0(n4569),
.B1(FPADDSUB_intDY_EWSW[3]), .C0(n4388), .Y(n4395) );
NOR2X1TS U2838 ( .A(n2209), .B(n2623), .Y(mult_x_254_n196) );
BUFX4TS U2839 ( .A(n2507), .Y(n2623) );
NOR4X1TS U2840 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n4757) );
NOR4X1TS U2841 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n4758) );
NOR4X1TS U2842 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n2895),
.Y(n4756) );
OAI33X1TS U2843 ( .A0(FPSENCOS_d_ff1_shift_region_flag_out[1]), .A1(
FPSENCOS_d_ff1_operation_out), .A2(n4583), .B0(n4550), .B1(n4703),
.B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n4212) );
NOR4X1TS U2844 ( .A(FPMULT_P_Sgf[8]), .B(FPMULT_P_Sgf[6]), .C(
FPMULT_P_Sgf[7]), .D(FPMULT_P_Sgf[11]), .Y(n3451) );
NOR2X2TS U2845 ( .A(n4270), .B(n4269), .Y(n4272) );
NOR4X1TS U2846 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[30]), .C(
FPMULT_Op_MX[29]), .D(FPMULT_Op_MX[28]), .Y(n4234) );
NOR4X1TS U2847 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[3]), .C(
FPMULT_Op_MY[4]), .D(FPMULT_Op_MY[5]), .Y(n4233) );
BUFX4TS U2848 ( .A(n2929), .Y(n4812) );
NOR2X1TS U2849 ( .A(n2227), .B(n2204), .Y(n3471) );
INVX2TS U2850 ( .A(n3370), .Y(n2264) );
INVX2TS U2851 ( .A(n2225), .Y(n2265) );
BUFX4TS U2852 ( .A(n4827), .Y(n4822) );
NOR2XLTS U2853 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n4292), .Y(n4294)
);
NOR2X2TS U2854 ( .A(n4690), .B(n4290), .Y(n4292) );
AOI32X2TS U2855 ( .A0(n3210), .A1(n3211), .A2(n3209), .B0(n3208), .B1(n3211),
.Y(n4413) );
NOR2X2TS U2856 ( .A(n4618), .B(n4279), .Y(n4278) );
AOI211X2TS U2857 ( .A0(FPADDSUB_Data_array_SWR[24]), .A1(n3288), .B0(n4363),
.C0(n3278), .Y(n4484) );
AOI211X2TS U2858 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n3310), .B0(n4363),
.C0(n3289), .Y(n3345) );
NOR2X2TS U2859 ( .A(n4623), .B(n3307), .Y(n4363) );
AOI222X4TS U2860 ( .A0(n3894), .A1(n3893), .B0(n3894), .B1(
FPMULT_Sgf_operation_EVEN1_Q_left[13]), .C0(n3893), .C1(
FPMULT_Sgf_operation_EVEN1_Q_left[13]), .Y(n3039) );
OAI211X2TS U2861 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n4613), .B0(n3183),
.C0(n3169), .Y(n3185) );
INVX4TS U2862 ( .A(n4704), .Y(n4351) );
AOI211XLTS U2863 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n4673), .B0(n3197),
.C0(n3198), .Y(n3189) );
OAI211X2TS U2864 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n4625), .B0(n3203),
.C0(n3188), .Y(n3197) );
AOI211X1TS U2865 ( .A0(n3525), .A1(n3524), .B0(n3523), .C0(n2910), .Y(n3526)
);
AOI22X2TS U2866 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(n4553), .B0(
FPADDSUB_DMP_SFG[8]), .B1(n4596), .Y(n3524) );
AOI2BB2X2TS U2867 ( .B0(n3427), .B1(n3430), .A0N(n4622), .A1N(n3531), .Y(
n3552) );
NOR2X2TS U2868 ( .A(n3418), .B(n3542), .Y(n3430) );
AOI211X1TS U2869 ( .A0(n3591), .A1(n3590), .B0(n3589), .C0(n2910), .Y(n3592)
);
NOR2X1TS U2870 ( .A(n3590), .B(n3591), .Y(n3589) );
AOI22X2TS U2871 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n4554), .B0(
FPADDSUB_DMP_SFG[9]), .B1(n4597), .Y(n3590) );
NAND2X2TS U2872 ( .A(FPMULT_FS_Module_state_reg[2]), .B(n4557), .Y(n3519) );
OAI22X2TS U2873 ( .A0(n3599), .A1(n4016), .B0(n4014), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n3559) );
AOI222X1TS U2874 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n3385), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n3449), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n3378) );
OAI2BB2XLTS U2875 ( .B0(n4203), .B1(n4661), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[15]), .Y(n2028) );
OAI2BB2XLTS U2876 ( .B0(n4203), .B1(n4659), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[9]), .Y(n2046) );
OAI2BB2XLTS U2877 ( .B0(n4203), .B1(n4655), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[5]), .Y(n2058) );
BUFX6TS U2878 ( .A(n3792), .Y(n3788) );
OAI211XLTS U2879 ( .A0(n3821), .A1(n4708), .B0(n3693), .C0(n3692), .Y(n1912)
);
AOI222X1TS U2880 ( .A0(n4099), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4115), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n3377) );
AOI222X4TS U2881 ( .A0(n3366), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DmP_EXP_EWSW[23]), .B1(n4549), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n3368), .Y(n3324) );
INVX4TS U2882 ( .A(n4224), .Y(n4009) );
AOI211X1TS U2883 ( .A0(n3883), .A1(n3882), .B0(n3881), .C0(n2910), .Y(n3884)
);
AOI22X2TS U2884 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n4630), .B0(
FPADDSUB_DMP_SFG[19]), .B1(n4561), .Y(n3883) );
BUFX4TS U2885 ( .A(n2312), .Y(n2393) );
BUFX3TS U2886 ( .A(n3047), .Y(n2266) );
BUFX3TS U2887 ( .A(n3047), .Y(n2267) );
BUFX4TS U2888 ( .A(n2266), .Y(n4762) );
BUFX4TS U2889 ( .A(n4781), .Y(n4768) );
BUFX4TS U2890 ( .A(n4769), .Y(n4783) );
BUFX4TS U2891 ( .A(n4775), .Y(n4766) );
BUFX4TS U2892 ( .A(n4771), .Y(n4778) );
BUFX4TS U2893 ( .A(n4777), .Y(n4788) );
BUFX4TS U2894 ( .A(n4772), .Y(n4789) );
BUFX4TS U2895 ( .A(n4765), .Y(n4761) );
BUFX4TS U2896 ( .A(n4763), .Y(n4774) );
BUFX4TS U2897 ( .A(n4779), .Y(n4773) );
BUFX4TS U2898 ( .A(n4786), .Y(n4776) );
BUFX4TS U2899 ( .A(n4780), .Y(n4785) );
BUFX4TS U2900 ( .A(n4786), .Y(n4782) );
BUFX4TS U2901 ( .A(n4780), .Y(n4770) );
AOI32X1TS U2902 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n3554), .A2(
n2195), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n4185), .Y(n3358)
);
AOI211X1TS U2903 ( .A0(n3754), .A1(n3753), .B0(n3752), .C0(n2910), .Y(n3755)
);
NOR2X1TS U2904 ( .A(n3753), .B(n3754), .Y(n3752) );
AOI22X2TS U2905 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(n4601), .B0(
FPADDSUB_DMP_SFG[12]), .B1(n4539), .Y(n3754) );
BUFX4TS U2906 ( .A(n2352), .Y(n2454) );
CLKINVX6TS U2907 ( .A(n4490), .Y(n4522) );
BUFX6TS U2908 ( .A(FPADDSUB_left_right_SHT2), .Y(n4490) );
AOI21X2TS U2909 ( .A0(n3638), .A1(n4560), .B0(n3564), .Y(n3632) );
NOR2X1TS U2910 ( .A(n3100), .B(n3102), .Y(n3099) );
AOI22X2TS U2911 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n4589), .B0(
FPADDSUB_DMP_SFG[3]), .B1(n4551), .Y(n3102) );
AOI211X1TS U2912 ( .A0(n3006), .A1(n3005), .B0(n3004), .C0(n2910), .Y(n3007)
);
NAND2X1TS U2913 ( .A(n3005), .B(n3003), .Y(n3002) );
AOI22X2TS U2914 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(n4555), .B0(
FPADDSUB_DMP_SFG[10]), .B1(n4599), .Y(n3005) );
BUFX3TS U2915 ( .A(n3473), .Y(n3501) );
BUFX4TS U2916 ( .A(n3501), .Y(n3499) );
CLKINVX6TS U2917 ( .A(n4725), .Y(busy) );
NAND2X2TS U2918 ( .A(FPSENCOS_cont_iter_out[3]), .B(
FPSENCOS_cont_iter_out[2]), .Y(n4083) );
NOR3XLTS U2919 ( .A(FPSENCOS_cont_iter_out[3]), .B(FPSENCOS_cont_iter_out[2]), .C(n3362), .Y(n2954) );
NOR4X1TS U2920 ( .A(FPSENCOS_cont_iter_out[3]), .B(FPSENCOS_cont_iter_out[2]), .C(n4121), .D(n3362), .Y(n3241) );
AOI22X2TS U2921 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(
FPSENCOS_cont_iter_out[2]), .B0(n2228), .B1(n4559), .Y(n2963) );
BUFX4TS U2922 ( .A(n4094), .Y(n4192) );
INVX3TS U2923 ( .A(n4299), .Y(n4284) );
BUFX4TS U2924 ( .A(n3052), .Y(n4299) );
OAI211XLTS U2925 ( .A0(n3825), .A1(n2232), .B0(n3718), .C0(n3717), .Y(n1918)
);
OAI211XLTS U2926 ( .A0(n3825), .A1(n4746), .B0(n3808), .C0(n3807), .Y(n1835)
);
OAI211XLTS U2927 ( .A0(n3825), .A1(n4753), .B0(n3810), .C0(n3809), .Y(n1817)
);
OAI211XLTS U2928 ( .A0(n3825), .A1(n4752), .B0(n3812), .C0(n3811), .Y(n1818)
);
OAI211XLTS U2929 ( .A0(n3825), .A1(n4750), .B0(n3814), .C0(n3813), .Y(n1822)
);
NOR2BX2TS U2930 ( .AN(n2916), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n3370) );
NOR4X2TS U2931 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[12]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .D(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n3418) );
AOI211X1TS U2932 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n3275), .B0(n3294),
.C0(n3293), .Y(n3344) );
BUFX4TS U2933 ( .A(n4120), .Y(n4103) );
BUFX4TS U2934 ( .A(n4120), .Y(n3385) );
BUFX4TS U2935 ( .A(n4116), .Y(n4120) );
INVX4TS U2936 ( .A(n4302), .Y(n4346) );
INVX4TS U2937 ( .A(n4090), .Y(n4088) );
AOI21X2TS U2938 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(n4591), .B0(n3063),
.Y(n3103) );
OAI2BB2X2TS U2939 ( .B0(n4591), .B1(FPADDSUB_DmP_mant_SFG_SWR[4]), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[4]), .A1N(n4591), .Y(n3064) );
OAI2BB2X2TS U2940 ( .B0(n4592), .B1(FPADDSUB_DmP_mant_SFG_SWR[7]), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[7]), .A1N(n4592), .Y(n3388) );
OAI2BB2X2TS U2941 ( .B0(n4593), .B1(FPADDSUB_DmP_mant_SFG_SWR[8]), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[8]), .A1N(n4593), .Y(n3462) );
AND3X1TS U2942 ( .A(FPADDSUB_DmP_mant_SFG_SWR[2]), .B(FPADDSUB_DMP_SFG[0]),
.C(n3058), .Y(n3062) );
AOI21X2TS U2943 ( .A0(n3308), .A1(FPADDSUB_Data_array_SWR[25]), .B0(n3304),
.Y(n4525) );
AOI21X2TS U2944 ( .A0(FPADDSUB_Data_array_SWR[25]), .A1(n3310), .B0(n3306),
.Y(n3339) );
OAI21XLTS U2945 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(
FPADDSUB_DMP_SFG[22]), .B0(n4463), .Y(n4464) );
AOI21X2TS U2946 ( .A0(n3308), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n3304),
.Y(n3342) );
AOI21X2TS U2947 ( .A0(FPADDSUB_Data_array_SWR[23]), .A1(n3310), .B0(n3301),
.Y(n3348) );
NOR2BX2TS U2948 ( .AN(n3550), .B(FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n3534) );
NOR2X2TS U2949 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(
FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n3546) );
OAI221X4TS U2950 ( .A0(FPMULT_Op_MX[14]), .A1(n2441), .B0(n2285), .B1(n2426),
.C0(n2458), .Y(n2316) );
AOI21X2TS U2951 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n3310), .B0(n3296),
.Y(n3336) );
AOI21X2TS U2952 ( .A0(n3308), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n3304),
.Y(n3351) );
AOI21X2TS U2953 ( .A0(n3308), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n3304),
.Y(n4491) );
AOI21X2TS U2954 ( .A0(FPADDSUB_Data_array_SWR[24]), .A1(n3310), .B0(n3309),
.Y(n3333) );
OAI21X2TS U2955 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(n4621), .B0(n3872), .Y(
n3880) );
OAI21X2TS U2956 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(n4640), .B0(n4353),
.Y(n4457) );
AOI2BB2X2TS U2957 ( .B0(FPADDSUB_DmP_mant_SFG_SWR[23]), .B1(n4656), .A0N(
n4656), .A1N(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n4459) );
OAI211XLTS U2958 ( .A0(n3821), .A1(n4741), .B0(n3685), .C0(n3684), .Y(n1843)
);
AOI221X1TS U2959 ( .A0(n4665), .A1(FPADDSUB_intDY_EWSW[21]), .B0(
FPADDSUB_intDY_EWSW[28]), .B1(n4404), .C0(n4403), .Y(n4405) );
NOR3X1TS U2960 ( .A(n4404), .B(n3152), .C(FPADDSUB_intDY_EWSW[28]), .Y(n3153) );
NOR3X2TS U2961 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n3354), .Y(n3550) );
OAI211XLTS U2962 ( .A0(n3821), .A1(n4743), .B0(n3806), .C0(n3805), .Y(n1841)
);
OAI221X1TS U2963 ( .A0(n4577), .A1(FPADDSUB_intDY_EWSW[27]), .B0(n4681),
.B1(FPADDSUB_intDY_EWSW[22]), .C0(n4390), .Y(n4393) );
OAI211XLTS U2964 ( .A0(n3825), .A1(n4751), .B0(n3802), .C0(n3801), .Y(n1819)
);
OAI221X1TS U2965 ( .A0(n4673), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n4677),
.B1(FPADDSUB_intDY_EWSW[12]), .C0(n4382), .Y(n4385) );
OAI211XLTS U2966 ( .A0(n3800), .A1(n4748), .B0(n3799), .C0(n3798), .Y(n1833)
);
NOR3X1TS U2967 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[12]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(
n3427) );
NOR2X4TS U2968 ( .A(n4623), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n3310)
);
NAND2X2TS U2969 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n3307) );
NAND3X2TS U2970 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .C(n2194), .Y(n4482) );
OAI221XLTS U2971 ( .A0(n4674), .A1(FPADDSUB_intDY_EWSW[20]), .B0(n4675),
.B1(FPADDSUB_intDY_EWSW[5]), .C0(n4381), .Y(n4386) );
OAI221X1TS U2972 ( .A0(n4666), .A1(FPADDSUB_intDY_EWSW[13]), .B0(n4579),
.B1(FPADDSUB_intDY_EWSW[7]), .C0(n4380), .Y(n4387) );
BUFX6TS U2973 ( .A(FPMULT_Op_MY[12]), .Y(n2268) );
ADDHX4TS U2974 ( .A(n2268), .B(FPMULT_Op_MY[0]), .CO(n2644), .S(
DP_OP_454J221_123_2743_n367) );
OAI32X1TS U2975 ( .A0(n2445), .A1(n2268), .A2(n2444), .B0(n2356), .B1(n2445),
.Y(n2446) );
OAI32X1TS U2976 ( .A0(n2409), .A1(n2268), .A2(n2393), .B0(n2313), .B1(n2409),
.Y(n2436) );
OAI32X1TS U2977 ( .A0(n2426), .A1(n2268), .A2(n2458), .B0(n2316), .B1(n2426),
.Y(n2428) );
OAI21XLTS U2978 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n4615), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n3159) );
OAI21XLTS U2979 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n4558), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n3179) );
NOR2XLTS U2980 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n2940) );
NOR2XLTS U2981 ( .A(n2941), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n2942) );
NOR2XLTS U2982 ( .A(FPADDSUB_DmP_mant_SFG_SWR[23]), .B(n4656), .Y(n4355) );
NOR2X1TS U2983 ( .A(n3465), .B(n3466), .Y(n3464) );
NOR2X1TS U2984 ( .A(n3067), .B(n3068), .Y(n3066) );
NOR2XLTS U2985 ( .A(n2618), .B(n2211), .Y(n2511) );
OAI21XLTS U2986 ( .A0(n2825), .A1(n2836), .B0(n2869), .Y(n2829) );
CLKINVX6TS U2987 ( .A(n2869), .Y(n2870) );
OAI21XLTS U2988 ( .A0(n2273), .A1(n2285), .B0(n2441), .Y(mult_x_219_n205) );
NOR2X1TS U2989 ( .A(n3524), .B(n3525), .Y(n3523) );
NOR2X1TS U2990 ( .A(intadd_499_SUM_3_), .B(n2949), .Y(n4335) );
NOR2BX1TS U2991 ( .AN(intadd_499_SUM_21_), .B(n3860), .Y(n3031) );
OAI21XLTS U2992 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n3455), .Y(n3456) );
NOR3XLTS U2993 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n4028) );
NOR2XLTS U2994 ( .A(n2771), .B(n2846), .Y(n2654) );
OAI211XLTS U2995 ( .A0(n2911), .A1(n2908), .B0(n4455), .C0(n4353), .Y(n2915)
);
OAI21XLTS U2996 ( .A0(n3322), .A1(n4513), .B0(n4365), .Y(n3295) );
OAI21XLTS U2997 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4259), .B0(
n4262), .Y(n4260) );
NOR2XLTS U2998 ( .A(n2771), .B(n2821), .Y(n2693) );
INVX2TS U2999 ( .A(FPMULT_Add_result[2]), .Y(n4252) );
OAI211XLTS U3000 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4288), .B0(
n4296), .C0(n4290), .Y(n4289) );
OAI21XLTS U3001 ( .A0(n4200), .A1(FPSENCOS_d_ff3_sign_out), .B0(n4198), .Y(
n4199) );
OR2X1TS U3002 ( .A(FPSENCOS_d_ff2_Y[23]), .B(n2228), .Y(intadd_501_CI) );
OAI211XLTS U3003 ( .A0(n3825), .A1(n2277), .B0(n3716), .C0(n3715), .Y(n1925)
);
OAI21XLTS U3004 ( .A0(n4468), .A1(n4542), .B0(n3851), .Y(n1332) );
OAI21XLTS U3005 ( .A0(n3469), .A1(n3887), .B0(n3468), .Y(n1341) );
OAI21XLTS U3006 ( .A0(n3071), .A1(n3887), .B0(n3070), .Y(n1345) );
OAI211XLTS U3007 ( .A0(n3800), .A1(n2234), .B0(n3741), .C0(n3740), .Y(n1940)
);
OAI211XLTS U3008 ( .A0(n3644), .A1(n3667), .B0(n3643), .C0(n3642), .Y(n1797)
);
OAI21XLTS U3009 ( .A0(n4679), .A1(n3396), .B0(n3245), .Y(n1253) );
OAI21XLTS U3010 ( .A0(n4579), .A1(n3225), .B0(n3414), .Y(n1305) );
OAI21XLTS U3011 ( .A0(n4569), .A1(n3224), .B0(n3227), .Y(n1326) );
OAI21XLTS U3012 ( .A0(n4670), .A1(n3401), .B0(n3221), .Y(n1395) );
OAI21XLTS U3013 ( .A0(n4577), .A1(n3225), .B0(n3213), .Y(n1413) );
OAI211XLTS U3014 ( .A0(n3636), .A1(n3595), .B0(n3566), .C0(n3565), .Y(n1809)
);
OAI211XLTS U3015 ( .A0(n3563), .A1(n3615), .B0(n3614), .C0(n3613), .Y(n1801)
);
OAI211XLTS U3016 ( .A0(n3673), .A1(n3563), .B0(n3623), .C0(n3622), .Y(n1789)
);
OAI211XLTS U3017 ( .A0(n3563), .A1(n3602), .B0(n3601), .C0(n3600), .Y(n1788)
);
NOR2XLTS U3018 ( .A(n4062), .B(n4195), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
OAI21XLTS U3019 ( .A0(n4069), .A1(n4532), .B0(n3787), .Y(op_result[2]) );
OAI21XLTS U3020 ( .A0(n3790), .A1(n4650), .B0(n3785), .Y(op_result[17]) );
NAND2X1TS U3021 ( .A(FPMULT_FS_Module_state_reg[0]), .B(n4614), .Y(n3987) );
BUFX3TS U3022 ( .A(n2310), .Y(n4222) );
BUFX3TS U3023 ( .A(n2273), .Y(n2453) );
BUFX4TS U3024 ( .A(FPMULT_Op_MX[15]), .Y(n2441) );
INVX4TS U3025 ( .A(n2441), .Y(n2426) );
AOI22X1TS U3026 ( .A0(n2441), .A1(n2283), .B0(n2256), .B1(n2426), .Y(n2312)
);
BUFX4TS U3027 ( .A(FPMULT_Op_MX[17]), .Y(n2425) );
INVX4TS U3028 ( .A(n2425), .Y(n2409) );
AOI22X1TS U3029 ( .A0(n2425), .A1(n2207), .B0(FPMULT_Op_MY[13]), .B1(n2409),
.Y(n2391) );
INVX2TS U3030 ( .A(n2268), .Y(n2455) );
AOI22X1TS U3031 ( .A0(n2268), .A1(n2409), .B0(n2425), .B1(n2455), .Y(n2314)
);
OAI22X1TS U3032 ( .A0(n2393), .A1(n2391), .B0(n2313), .B1(n2314), .Y(n2321)
);
AOI22X1TS U3033 ( .A0(FPMULT_Op_MX[13]), .A1(n2285), .B0(FPMULT_Op_MX[14]),
.B1(n2273), .Y(n2315) );
BUFX4TS U3034 ( .A(n2315), .Y(n2458) );
AOI22X1TS U3035 ( .A0(n2441), .A1(n2306), .B0(n2261), .B1(n2426), .Y(n2397)
);
AOI22X1TS U3036 ( .A0(n2441), .A1(n2305), .B0(FPMULT_Op_MY[14]), .B1(n2426),
.Y(n2318) );
OAI22X1TS U3037 ( .A0(n2458), .A1(n2397), .B0(n2316), .B1(n2318), .Y(n2320)
);
AOI22X1TS U3038 ( .A0(FPMULT_Op_MX[13]), .A1(n2304), .B0(FPMULT_Op_MY[16]),
.B1(n2453), .Y(n2317) );
NOR2XLTS U3039 ( .A(n2455), .B(n2393), .Y(n2324) );
AOI22X1TS U3040 ( .A0(n2441), .A1(n2207), .B0(FPMULT_Op_MY[13]), .B1(n2426),
.Y(n2328) );
OAI22X1TS U3041 ( .A0(n2458), .A1(n2318), .B0(n2316), .B1(n2328), .Y(n2323)
);
CMPR32X2TS U3042 ( .A(n2321), .B(n2320), .C(n2319), .CO(n2349), .S(n2435) );
AOI22X1TS U3043 ( .A0(FPMULT_Op_MX[13]), .A1(n2303), .B0(FPMULT_Op_MY[17]),
.B1(n2273), .Y(n2322) );
CMPR32X2TS U3044 ( .A(n2325), .B(n2324), .C(n2323), .CO(n2319), .S(n2432) );
AOI22X1TS U3045 ( .A0(FPMULT_Op_MX[13]), .A1(n2306), .B0(n2261), .B1(n2453),
.Y(n2326) );
AOI22X1TS U3046 ( .A0(n2268), .A1(n2426), .B0(n2441), .B1(n2455), .Y(n2327)
);
OAI22X1TS U3047 ( .A0(n2458), .A1(n2328), .B0(n2316), .B1(n2327), .Y(n2329)
);
ADDHXLTS U3048 ( .A(n2330), .B(n2329), .CO(n2431), .S(n2429) );
AOI22X1TS U3049 ( .A0(FPMULT_Op_MX[13]), .A1(n2305), .B0(FPMULT_Op_MY[14]),
.B1(n2453), .Y(n2331) );
OAI32X1TS U3050 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[13]), .A2(n2453),
.B0(n2331), .B1(n2208), .Y(n2440) );
NOR2XLTS U3051 ( .A(n2455), .B(n2458), .Y(n2439) );
AOI21X1TS U3052 ( .A0(n2268), .A1(FPMULT_Op_MX[12]), .B0(n2453), .Y(n2351)
);
NAND2X1TS U3053 ( .A(FPMULT_Op_MX[13]), .B(n2208), .Y(n2333) );
AOI22X1TS U3054 ( .A0(FPMULT_Op_MX[13]), .A1(n2207), .B0(FPMULT_Op_MY[13]),
.B1(n2453), .Y(n2332) );
OAI22X1TS U3055 ( .A0(n2268), .A1(n2333), .B0(n2332), .B1(n2208), .Y(n2350)
);
CMPR32X2TS U3056 ( .A(mult_x_219_n40), .B(mult_x_219_n36), .C(n2334), .CO(
n2399), .S(FPMULT_Sgf_operation_EVEN1_left_N20) );
CMPR32X2TS U3057 ( .A(mult_x_219_n45), .B(mult_x_219_n41), .C(n2335), .CO(
n2334), .S(FPMULT_Sgf_operation_EVEN1_left_N19) );
CMPR32X2TS U3058 ( .A(mult_x_219_n46), .B(mult_x_219_n52), .C(n2336), .CO(
n2335), .S(FPMULT_Sgf_operation_EVEN1_left_N18) );
CMPR32X2TS U3059 ( .A(mult_x_219_n53), .B(mult_x_219_n58), .C(n2337), .CO(
n2336), .S(FPMULT_Sgf_operation_EVEN1_left_N17) );
CMPR32X2TS U3060 ( .A(mult_x_219_n59), .B(mult_x_219_n66), .C(n2338), .CO(
n2337), .S(FPMULT_Sgf_operation_EVEN1_left_N16) );
CMPR32X2TS U3061 ( .A(mult_x_219_n67), .B(mult_x_219_n74), .C(n2339), .CO(
n2338), .S(FPMULT_Sgf_operation_EVEN1_left_N15) );
CMPR32X2TS U3062 ( .A(mult_x_219_n75), .B(mult_x_219_n84), .C(n2340), .CO(
n2339), .S(FPMULT_Sgf_operation_EVEN1_left_N14) );
CMPR32X2TS U3063 ( .A(mult_x_219_n85), .B(mult_x_219_n93), .C(n2341), .CO(
n2340), .S(FPMULT_Sgf_operation_EVEN1_left_N13) );
CMPR32X2TS U3064 ( .A(mult_x_219_n94), .B(mult_x_219_n101), .C(n2342), .CO(
n2341), .S(FPMULT_Sgf_operation_EVEN1_left_N12) );
CMPR32X2TS U3065 ( .A(mult_x_219_n102), .B(mult_x_219_n109), .C(n2343), .CO(
n2342), .S(FPMULT_Sgf_operation_EVEN1_left_N11) );
CMPR32X2TS U3066 ( .A(mult_x_219_n110), .B(mult_x_219_n115), .C(n2344), .CO(
n2343), .S(FPMULT_Sgf_operation_EVEN1_left_N10) );
CMPR32X2TS U3067 ( .A(mult_x_219_n116), .B(mult_x_219_n122), .C(n2345), .CO(
n2344), .S(FPMULT_Sgf_operation_EVEN1_left_N9) );
CMPR32X2TS U3068 ( .A(mult_x_219_n123), .B(mult_x_219_n127), .C(n2346), .CO(
n2345), .S(FPMULT_Sgf_operation_EVEN1_left_N8) );
CMPR32X2TS U3069 ( .A(mult_x_219_n128), .B(mult_x_219_n132), .C(n2347), .CO(
n2346), .S(FPMULT_Sgf_operation_EVEN1_left_N7) );
CMPR32X2TS U3070 ( .A(mult_x_219_n133), .B(n2349), .C(n2348), .CO(n2347),
.S(FPMULT_Sgf_operation_EVEN1_left_N6) );
ADDHXLTS U3071 ( .A(n2351), .B(n2350), .CO(n2438), .S(
FPMULT_Sgf_operation_EVEN1_left_N1) );
BUFX4TS U3072 ( .A(FPMULT_Op_MX[21]), .Y(n2442) );
BUFX4TS U3073 ( .A(FPMULT_Op_MX[19]), .Y(n2422) );
INVX4TS U3074 ( .A(n2422), .Y(n2445) );
AOI22X1TS U3075 ( .A0(n2422), .A1(n2278), .B0(FPMULT_Op_MX[20]), .B1(n2445),
.Y(n2352) );
AOI22X1TS U3076 ( .A0(n2442), .A1(n2221), .B0(FPMULT_Op_MY[22]), .B1(n2449),
.Y(n2421) );
OAI22X1TS U3077 ( .A0(n2442), .A1(n2454), .B0(n2421), .B1(n2353), .Y(n2354)
);
CMPR32X2TS U3078 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MY[18]), .C(n2354),
.CO(mult_x_219_n42), .S(mult_x_219_n43) );
AOI22X1TS U3079 ( .A0(n2425), .A1(n2280), .B0(FPMULT_Op_MX[18]), .B1(n2409),
.Y(n2355) );
AOI22X1TS U3080 ( .A0(n2422), .A1(n2308), .B0(FPMULT_Op_MY[21]), .B1(n2445),
.Y(n2375) );
AOI22X1TS U3081 ( .A0(n2422), .A1(n2217), .B0(FPMULT_Op_MY[20]), .B1(n2445),
.Y(n2358) );
OAI22X1TS U3082 ( .A0(n2444), .A1(n2375), .B0(n2356), .B1(n2358), .Y(n2357)
);
CMPR32X2TS U3083 ( .A(n2261), .B(FPMULT_Op_MY[13]), .C(n2357), .CO(
mult_x_219_n71), .S(mult_x_219_n72) );
AOI22X1TS U3084 ( .A0(n2422), .A1(n2291), .B0(FPMULT_Op_MY[19]), .B1(n2445),
.Y(n2377) );
OAI22X1TS U3085 ( .A0(n2444), .A1(n2358), .B0(n2356), .B1(n2377), .Y(n2359)
);
CMPR32X2TS U3086 ( .A(n2207), .B(FPMULT_Op_MY[14]), .C(n2359), .CO(
mult_x_219_n79), .S(mult_x_219_n80) );
AOI22X1TS U3087 ( .A0(n2442), .A1(n2303), .B0(FPMULT_Op_MY[17]), .B1(n2449),
.Y(n2370) );
AOI22X1TS U3088 ( .A0(n2442), .A1(n2304), .B0(FPMULT_Op_MY[16]), .B1(n2449),
.Y(n2372) );
OAI22X1TS U3089 ( .A0(n2454), .A1(n2370), .B0(n2353), .B1(n2372), .Y(n2361)
);
AOI22X1TS U3090 ( .A0(n2425), .A1(n2308), .B0(FPMULT_Op_MY[21]), .B1(n2409),
.Y(n2383) );
AOI22X1TS U3091 ( .A0(n2425), .A1(n2217), .B0(FPMULT_Op_MY[20]), .B1(n2409),
.Y(n2385) );
OAI22X1TS U3092 ( .A0(n2393), .A1(n2383), .B0(n2313), .B1(n2385), .Y(n2360)
);
CMPR32X2TS U3093 ( .A(n2361), .B(n2207), .C(n2360), .CO(mult_x_219_n89), .S(
mult_x_219_n90) );
NOR2XLTS U3094 ( .A(n2453), .B(n2208), .Y(n2363) );
AOI22X1TS U3095 ( .A0(n2441), .A1(n2221), .B0(FPMULT_Op_MY[22]), .B1(n2426),
.Y(n2394) );
AOI22X1TS U3096 ( .A0(n2441), .A1(n2308), .B0(FPMULT_Op_MY[21]), .B1(n2426),
.Y(n2395) );
OAI22X1TS U3097 ( .A0(n2458), .A1(n2394), .B0(n2316), .B1(n2395), .Y(n2362)
);
CMPR32X2TS U3098 ( .A(n2363), .B(n2268), .C(n2362), .CO(mult_x_219_n98), .S(
mult_x_219_n99) );
AOI22X1TS U3099 ( .A0(n2442), .A1(FPMULT_Op_MX[22]), .B0(n2220), .B1(n2449),
.Y(n2402) );
OAI21XLTS U3100 ( .A0(n2268), .A1(n2364), .B0(n2365), .Y(n2367) );
ADDHXLTS U3101 ( .A(n2367), .B(n2366), .CO(mult_x_219_n106), .S(
mult_x_219_n107) );
OAI22X1TS U3102 ( .A0(FPMULT_Op_MY[21]), .A1(n2365), .B0(FPMULT_Op_MY[22]),
.B1(n2364), .Y(mult_x_219_n152) );
OAI22X1TS U3103 ( .A0(FPMULT_Op_MY[20]), .A1(n2365), .B0(FPMULT_Op_MY[21]),
.B1(n2364), .Y(mult_x_219_n153) );
OAI22X1TS U3104 ( .A0(FPMULT_Op_MY[19]), .A1(n2365), .B0(FPMULT_Op_MY[20]),
.B1(n2364), .Y(mult_x_219_n154) );
OAI22X1TS U3105 ( .A0(FPMULT_Op_MY[18]), .A1(n2365), .B0(FPMULT_Op_MY[19]),
.B1(n2364), .Y(mult_x_219_n155) );
OAI22X1TS U3106 ( .A0(FPMULT_Op_MY[17]), .A1(n2365), .B0(FPMULT_Op_MY[18]),
.B1(n2364), .Y(mult_x_219_n156) );
OAI22X1TS U3107 ( .A0(FPMULT_Op_MY[16]), .A1(n2365), .B0(FPMULT_Op_MY[17]),
.B1(n2364), .Y(mult_x_219_n157) );
OAI22X1TS U3108 ( .A0(n2261), .A1(n2365), .B0(FPMULT_Op_MY[16]), .B1(n2364),
.Y(mult_x_219_n158) );
OAI22X1TS U3109 ( .A0(FPMULT_Op_MY[14]), .A1(n2365), .B0(n2261), .B1(n2364),
.Y(mult_x_219_n159) );
OAI22X1TS U3110 ( .A0(FPMULT_Op_MY[13]), .A1(n2365), .B0(FPMULT_Op_MY[14]),
.B1(n2364), .Y(mult_x_219_n160) );
OAI22X1TS U3111 ( .A0(FPMULT_Op_MY[13]), .A1(n2364), .B0(n2268), .B1(n2365),
.Y(mult_x_219_n161) );
AOI22X1TS U3112 ( .A0(n2442), .A1(n2454), .B0(n2353), .B1(n2449), .Y(
mult_x_219_n164) );
AOI22X1TS U3113 ( .A0(n2442), .A1(n2308), .B0(FPMULT_Op_MY[21]), .B1(n2449),
.Y(n2420) );
AOI22X1TS U3114 ( .A0(n2442), .A1(n2217), .B0(FPMULT_Op_MY[20]), .B1(n2449),
.Y(n2368) );
OAI22X1TS U3115 ( .A0(n2454), .A1(n2420), .B0(n2353), .B1(n2368), .Y(
mult_x_219_n167) );
AOI22X1TS U3116 ( .A0(n2442), .A1(n2291), .B0(FPMULT_Op_MY[19]), .B1(n2449),
.Y(n2369) );
OAI22X1TS U3117 ( .A0(n2454), .A1(n2368), .B0(n2353), .B1(n2369), .Y(
mult_x_219_n168) );
AOI22X1TS U3118 ( .A0(n2442), .A1(n2290), .B0(FPMULT_Op_MY[18]), .B1(n2449),
.Y(n2371) );
OAI22X1TS U3119 ( .A0(n2454), .A1(n2369), .B0(n2353), .B1(n2371), .Y(
mult_x_219_n169) );
OAI22X1TS U3120 ( .A0(n2454), .A1(n2371), .B0(n2353), .B1(n2370), .Y(
mult_x_219_n170) );
AOI22X1TS U3121 ( .A0(n2442), .A1(n2306), .B0(n2261), .B1(n2449), .Y(n2373)
);
OAI22X1TS U3122 ( .A0(n2454), .A1(n2372), .B0(n2353), .B1(n2373), .Y(
mult_x_219_n172) );
AOI22X1TS U3123 ( .A0(n2442), .A1(n2305), .B0(FPMULT_Op_MY[14]), .B1(n2449),
.Y(n2374) );
OAI22X1TS U3124 ( .A0(n2454), .A1(n2373), .B0(n2353), .B1(n2374), .Y(
mult_x_219_n173) );
AOI22X1TS U3125 ( .A0(n2442), .A1(n2207), .B0(FPMULT_Op_MY[13]), .B1(n2449),
.Y(n2411) );
OAI22X1TS U3126 ( .A0(n2454), .A1(n2374), .B0(n2353), .B1(n2411), .Y(
mult_x_219_n174) );
AOI22X1TS U3127 ( .A0(n2422), .A1(n2221), .B0(FPMULT_Op_MY[22]), .B1(n2445),
.Y(n2376) );
OAI22X1TS U3128 ( .A0(n2422), .A1(n2444), .B0(n2376), .B1(n2356), .Y(
mult_x_219_n179) );
OAI22X1TS U3129 ( .A0(n2444), .A1(n2376), .B0(n2356), .B1(n2375), .Y(
mult_x_219_n180) );
AOI22X1TS U3130 ( .A0(n2422), .A1(n2290), .B0(FPMULT_Op_MY[18]), .B1(n2445),
.Y(n2378) );
OAI22X1TS U3131 ( .A0(n2444), .A1(n2377), .B0(n2356), .B1(n2378), .Y(
mult_x_219_n183) );
AOI22X1TS U3132 ( .A0(n2422), .A1(n2303), .B0(FPMULT_Op_MY[17]), .B1(n2445),
.Y(n2379) );
OAI22X1TS U3133 ( .A0(n2444), .A1(n2378), .B0(n2356), .B1(n2379), .Y(
mult_x_219_n184) );
AOI22X1TS U3134 ( .A0(n2422), .A1(n2304), .B0(FPMULT_Op_MY[16]), .B1(n2445),
.Y(n2380) );
OAI22X1TS U3135 ( .A0(n2444), .A1(n2379), .B0(n2356), .B1(n2380), .Y(
mult_x_219_n185) );
AOI22X1TS U3136 ( .A0(n2422), .A1(n2306), .B0(n2261), .B1(n2445), .Y(n2414)
);
OAI22X1TS U3137 ( .A0(n2444), .A1(n2380), .B0(n2356), .B1(n2414), .Y(
mult_x_219_n186) );
AOI22X1TS U3138 ( .A0(n2422), .A1(n2305), .B0(FPMULT_Op_MY[14]), .B1(n2445),
.Y(n2413) );
AOI22X1TS U3139 ( .A0(n2422), .A1(n2207), .B0(FPMULT_Op_MY[13]), .B1(n2445),
.Y(n2382) );
OAI22X1TS U3140 ( .A0(n2444), .A1(n2413), .B0(n2356), .B1(n2382), .Y(
mult_x_219_n188) );
AOI22X1TS U3141 ( .A0(n2268), .A1(n2445), .B0(n2422), .B1(n2455), .Y(n2381)
);
OAI22X1TS U3142 ( .A0(n2444), .A1(n2382), .B0(n2356), .B1(n2381), .Y(
mult_x_219_n189) );
AOI22X1TS U3143 ( .A0(n2425), .A1(n2393), .B0(n2313), .B1(n2409), .Y(
mult_x_219_n192) );
AOI22X1TS U3144 ( .A0(n2425), .A1(n2221), .B0(FPMULT_Op_MY[22]), .B1(n2409),
.Y(n2384) );
OAI22X1TS U3145 ( .A0(n2425), .A1(n2393), .B0(n2384), .B1(n2313), .Y(
mult_x_219_n193) );
OAI22X1TS U3146 ( .A0(n2393), .A1(n2384), .B0(n2313), .B1(n2383), .Y(
mult_x_219_n194) );
AOI22X1TS U3147 ( .A0(n2425), .A1(n2291), .B0(FPMULT_Op_MY[19]), .B1(n2409),
.Y(n2386) );
OAI22X1TS U3148 ( .A0(n2393), .A1(n2385), .B0(n2313), .B1(n2386), .Y(
mult_x_219_n196) );
AOI22X1TS U3149 ( .A0(n2425), .A1(n2290), .B0(FPMULT_Op_MY[18]), .B1(n2409),
.Y(n2387) );
OAI22X1TS U3150 ( .A0(n2393), .A1(n2386), .B0(n2313), .B1(n2387), .Y(
mult_x_219_n197) );
AOI22X1TS U3151 ( .A0(n2425), .A1(n2303), .B0(FPMULT_Op_MY[17]), .B1(n2409),
.Y(n2388) );
OAI22X1TS U3152 ( .A0(n2393), .A1(n2387), .B0(n2313), .B1(n2388), .Y(
mult_x_219_n198) );
AOI22X1TS U3153 ( .A0(n2425), .A1(n2304), .B0(FPMULT_Op_MY[16]), .B1(n2409),
.Y(n2389) );
OAI22X1TS U3154 ( .A0(n2393), .A1(n2388), .B0(n2313), .B1(n2389), .Y(
mult_x_219_n199) );
AOI22X1TS U3155 ( .A0(n2425), .A1(n2306), .B0(n2261), .B1(n2409), .Y(n2390)
);
OAI22X1TS U3156 ( .A0(n2393), .A1(n2389), .B0(n2313), .B1(n2390), .Y(
mult_x_219_n200) );
AOI22X1TS U3157 ( .A0(n2425), .A1(n2305), .B0(FPMULT_Op_MY[14]), .B1(n2409),
.Y(n2392) );
OAI22X1TS U3158 ( .A0(n2393), .A1(n2390), .B0(n2313), .B1(n2392), .Y(
mult_x_219_n201) );
OAI22X1TS U3159 ( .A0(n2393), .A1(n2392), .B0(n2313), .B1(n2391), .Y(
mult_x_219_n202) );
AOI22X1TS U3160 ( .A0(n2441), .A1(n2458), .B0(n2316), .B1(n2426), .Y(
mult_x_219_n206) );
OAI22X1TS U3161 ( .A0(n2441), .A1(n2458), .B0(n2394), .B1(n2316), .Y(
mult_x_219_n207) );
AOI22X1TS U3162 ( .A0(n2441), .A1(n2217), .B0(FPMULT_Op_MY[20]), .B1(n2426),
.Y(n2396) );
OAI22X1TS U3163 ( .A0(n2458), .A1(n2395), .B0(n2316), .B1(n2396), .Y(
mult_x_219_n209) );
AOI22X1TS U3164 ( .A0(n2441), .A1(n2291), .B0(FPMULT_Op_MY[19]), .B1(n2426),
.Y(n2412) );
OAI22X1TS U3165 ( .A0(n2458), .A1(n2396), .B0(n2316), .B1(n2412), .Y(
mult_x_219_n210) );
AOI22X1TS U3166 ( .A0(n2441), .A1(n2303), .B0(FPMULT_Op_MY[17]), .B1(n2426),
.Y(n2456) );
AOI22X1TS U3167 ( .A0(n2441), .A1(n2304), .B0(FPMULT_Op_MY[16]), .B1(n2426),
.Y(n2398) );
OAI22X1TS U3168 ( .A0(n2458), .A1(n2456), .B0(n2316), .B1(n2398), .Y(
mult_x_219_n213) );
OAI22X1TS U3169 ( .A0(n2458), .A1(n2398), .B0(n2316), .B1(n2397), .Y(
mult_x_219_n214) );
CMPR32X2TS U3170 ( .A(mult_x_219_n35), .B(mult_x_219_n33), .C(n2399), .CO(
n2400), .S(FPMULT_Sgf_operation_EVEN1_left_N21) );
CMPR32X2TS U3171 ( .A(mult_x_219_n32), .B(n2401), .C(n2400), .CO(n2404), .S(
FPMULT_Sgf_operation_EVEN1_left_N22) );
CMPR32X2TS U3172 ( .A(n2402), .B(n2221), .C(mult_x_219_n31), .CO(n2403), .S(
n2401) );
XOR2X1TS U3173 ( .A(n2404), .B(n2403), .Y(n2406) );
OAI31X1TS U3174 ( .A0(n2406), .A1(n2220), .A2(n2449), .B0(n2405), .Y(n2407)
);
XNOR2X1TS U3175 ( .A(FPMULT_Op_MY[22]), .B(n2407), .Y(
FPMULT_Sgf_operation_EVEN1_left_N23) );
OAI21X1TS U3176 ( .A0(n2409), .A1(n2280), .B0(n2422), .Y(mult_x_219_n177) );
AOI22X1TS U3177 ( .A0(n2442), .A1(n2455), .B0(n2268), .B1(n2449), .Y(n2410)
);
OAI22X1TS U3178 ( .A0(n2454), .A1(n2411), .B0(n2353), .B1(n2410), .Y(n2417)
);
AOI22X1TS U3179 ( .A0(n2441), .A1(n2290), .B0(FPMULT_Op_MY[18]), .B1(n2426),
.Y(n2457) );
OAI22X1TS U3180 ( .A0(n2458), .A1(n2412), .B0(n2316), .B1(n2457), .Y(n2416)
);
OAI22X1TS U3181 ( .A0(n2444), .A1(n2414), .B0(n2356), .B1(n2413), .Y(n2415)
);
CMPR32X2TS U3182 ( .A(n2417), .B(n2416), .C(n2415), .CO(mult_x_219_n117),
.S(mult_x_219_n118) );
AOI22X1TS U3183 ( .A0(FPMULT_Op_MX[13]), .A1(n2290), .B0(FPMULT_Op_MY[18]),
.B1(n2273), .Y(n2418) );
AOI22X1TS U3184 ( .A0(FPMULT_Op_MX[13]), .A1(n2221), .B0(FPMULT_Op_MY[22]),
.B1(n2273), .Y(n2419) );
OAI22X1TS U3185 ( .A0(n2454), .A1(n2421), .B0(n2353), .B1(n2420), .Y(n2424)
);
AOI22X1TS U3186 ( .A0(n2422), .A1(n2444), .B0(n2356), .B1(n2445), .Y(n2423)
);
CMPR32X2TS U3187 ( .A(n2424), .B(n2290), .C(n2423), .CO(mult_x_219_n47), .S(
mult_x_219_n48) );
OAI21X1TS U3188 ( .A0(n2426), .A1(n2283), .B0(n2425), .Y(mult_x_219_n191) );
CMPR32X2TS U3189 ( .A(n2429), .B(n2428), .C(n2427), .CO(n2430), .S(
FPMULT_Sgf_operation_EVEN1_left_N3) );
CMPR32X2TS U3190 ( .A(n2432), .B(n2431), .C(n2430), .CO(n2433), .S(
FPMULT_Sgf_operation_EVEN1_left_N4) );
CMPR32X2TS U3191 ( .A(n2435), .B(n2434), .C(n2433), .CO(n2348), .S(
FPMULT_Sgf_operation_EVEN1_left_N5) );
ADDHXLTS U3192 ( .A(n2437), .B(n2436), .CO(mult_x_219_n136), .S(n2434) );
CMPR32X2TS U3193 ( .A(n2440), .B(n2439), .C(n2438), .CO(n2427), .S(
FPMULT_Sgf_operation_EVEN1_left_N2) );
OAI21XLTS U3194 ( .A0(n2445), .A1(n2278), .B0(n2442), .Y(mult_x_219_n163) );
AOI22X1TS U3195 ( .A0(FPMULT_Op_MX[13]), .A1(n2291), .B0(FPMULT_Op_MY[19]),
.B1(n2273), .Y(n2443) );
ADDHXLTS U3196 ( .A(n2447), .B(n2446), .CO(mult_x_219_n129), .S(
mult_x_219_n130) );
AOI22X1TS U3197 ( .A0(FPMULT_Op_MX[13]), .A1(n2308), .B0(FPMULT_Op_MY[21]),
.B1(n2273), .Y(n2448) );
ADDHXLTS U3198 ( .A(n2451), .B(n2450), .CO(mult_x_219_n119), .S(
mult_x_219_n120) );
AOI22X1TS U3199 ( .A0(FPMULT_Op_MX[13]), .A1(n2217), .B0(FPMULT_Op_MY[20]),
.B1(n2273), .Y(n2452) );
NOR2XLTS U3200 ( .A(n2455), .B(n2454), .Y(n2460) );
OAI22X1TS U3201 ( .A0(n2458), .A1(n2457), .B0(n2316), .B1(n2456), .Y(n2459)
);
BUFX4TS U3202 ( .A(FPMULT_Op_MX[3]), .Y(n2567) );
AOI22X1TS U3203 ( .A0(n2567), .A1(n2300), .B0(FPMULT_Op_MX[4]), .B1(n2582),
.Y(n2462) );
BUFX4TS U3204 ( .A(FPMULT_Op_MX[5]), .Y(n2581) );
AOI22X1TS U3205 ( .A0(n2581), .A1(n2212), .B0(FPMULT_Op_MY[1]), .B1(n2564),
.Y(n2543) );
AOI22X1TS U3206 ( .A0(FPMULT_Op_MY[0]), .A1(n2564), .B0(n2581), .B1(n2209),
.Y(n2464) );
OAI22X1TS U3207 ( .A0(n2587), .A1(n2543), .B0(n2463), .B1(n2464), .Y(n2471)
);
AOI22X1TS U3208 ( .A0(FPMULT_Op_MX[1]), .A1(n2311), .B0(FPMULT_Op_MX[2]),
.B1(n4530), .Y(n2465) );
BUFX4TS U3209 ( .A(n2465), .Y(n2635) );
AOI22X1TS U3210 ( .A0(n2567), .A1(n2211), .B0(FPMULT_Op_MY[3]), .B1(n2582),
.Y(n2547) );
AOI22X1TS U3211 ( .A0(n2567), .A1(n2216), .B0(FPMULT_Op_MY[2]), .B1(n2582),
.Y(n2468) );
OAI22X1TS U3212 ( .A0(n2635), .A1(n2547), .B0(n2466), .B1(n2468), .Y(n2470)
);
AOI22X1TS U3213 ( .A0(FPMULT_Op_MX[1]), .A1(n2218), .B0(FPMULT_Op_MY[4]),
.B1(n4530), .Y(n2467) );
NOR2XLTS U3214 ( .A(n2209), .B(n2587), .Y(n2474) );
AOI22X1TS U3215 ( .A0(n2567), .A1(n2212), .B0(FPMULT_Op_MY[1]), .B1(n2582),
.Y(n2478) );
OAI22X1TS U3216 ( .A0(n2635), .A1(n2468), .B0(n2466), .B1(n2478), .Y(n2473)
);
CMPR32X2TS U3217 ( .A(n2471), .B(n2470), .C(n2469), .CO(n2499), .S(n2605) );
AOI22X1TS U3218 ( .A0(FPMULT_Op_MX[1]), .A1(n2214), .B0(FPMULT_Op_MY[5]),
.B1(n4530), .Y(n2472) );
CMPR32X2TS U3219 ( .A(n2475), .B(n2474), .C(n2473), .CO(n2469), .S(n2602) );
AOI22X1TS U3220 ( .A0(FPMULT_Op_MX[1]), .A1(n2211), .B0(FPMULT_Op_MY[3]),
.B1(n4530), .Y(n2476) );
AOI22X1TS U3221 ( .A0(FPMULT_Op_MY[0]), .A1(n2582), .B0(n2567), .B1(n2209),
.Y(n2477) );
OAI22X1TS U3222 ( .A0(n2635), .A1(n2478), .B0(n2466), .B1(n2477), .Y(n2479)
);
ADDHXLTS U3223 ( .A(n2480), .B(n2479), .CO(n2601), .S(n2599) );
OAI32X1TS U3224 ( .A0(n2582), .A1(FPMULT_Op_MY[0]), .A2(n2635), .B0(n2466),
.B1(n2582), .Y(n2598) );
AOI22X1TS U3225 ( .A0(FPMULT_Op_MX[1]), .A1(n2216), .B0(FPMULT_Op_MY[2]),
.B1(n4530), .Y(n2481) );
NOR2XLTS U3226 ( .A(n2209), .B(n2635), .Y(n2614) );
AOI21X1TS U3227 ( .A0(FPMULT_Op_MY[0]), .A1(FPMULT_Op_MX[0]), .B0(n4530),
.Y(n2501) );
NAND2X1TS U3228 ( .A(FPMULT_Op_MX[1]), .B(n2210), .Y(n2483) );
AOI22X1TS U3229 ( .A0(FPMULT_Op_MX[1]), .A1(n2212), .B0(FPMULT_Op_MY[1]),
.B1(n4530), .Y(n2482) );
OAI22X1TS U3230 ( .A0(FPMULT_Op_MY[0]), .A1(n2483), .B0(n2482), .B1(n2210),
.Y(n2500) );
CMPR32X2TS U3231 ( .A(mult_x_254_n40), .B(mult_x_254_n36), .C(n2484), .CO(
n2550), .S(FPMULT_Sgf_operation_EVEN1_right_N20) );
CMPR32X2TS U3232 ( .A(mult_x_254_n45), .B(mult_x_254_n41), .C(n2485), .CO(
n2484), .S(FPMULT_Sgf_operation_EVEN1_right_N19) );
CMPR32X2TS U3233 ( .A(mult_x_254_n46), .B(mult_x_254_n52), .C(n2486), .CO(
n2485), .S(FPMULT_Sgf_operation_EVEN1_right_N18) );
CMPR32X2TS U3234 ( .A(mult_x_254_n53), .B(mult_x_254_n58), .C(n2487), .CO(
n2486), .S(FPMULT_Sgf_operation_EVEN1_right_N17) );
CMPR32X2TS U3235 ( .A(mult_x_254_n59), .B(mult_x_254_n66), .C(n2488), .CO(
n2487), .S(FPMULT_Sgf_operation_EVEN1_right_N16) );
CMPR32X2TS U3236 ( .A(mult_x_254_n67), .B(mult_x_254_n74), .C(n2489), .CO(
n2488), .S(FPMULT_Sgf_operation_EVEN1_right_N15) );
CMPR32X2TS U3237 ( .A(mult_x_254_n75), .B(mult_x_254_n84), .C(n2490), .CO(
n2489), .S(FPMULT_Sgf_operation_EVEN1_right_N14) );
CMPR32X2TS U3238 ( .A(mult_x_254_n85), .B(mult_x_254_n93), .C(n2491), .CO(
n2490), .S(FPMULT_Sgf_operation_EVEN1_right_N13) );
CMPR32X2TS U3239 ( .A(mult_x_254_n94), .B(mult_x_254_n101), .C(n2492), .CO(
n2491), .S(FPMULT_Sgf_operation_EVEN1_right_N12) );
CMPR32X2TS U3240 ( .A(mult_x_254_n102), .B(mult_x_254_n109), .C(n2493), .CO(
n2492), .S(FPMULT_Sgf_operation_EVEN1_right_N11) );
CMPR32X2TS U3241 ( .A(mult_x_254_n110), .B(mult_x_254_n115), .C(n2494), .CO(
n2493), .S(FPMULT_Sgf_operation_EVEN1_right_N10) );
CMPR32X2TS U3242 ( .A(mult_x_254_n116), .B(mult_x_254_n122), .C(n2495), .CO(
n2494), .S(FPMULT_Sgf_operation_EVEN1_right_N9) );
CMPR32X2TS U3243 ( .A(mult_x_254_n123), .B(mult_x_254_n127), .C(n2496), .CO(
n2495), .S(FPMULT_Sgf_operation_EVEN1_right_N8) );
CMPR32X2TS U3244 ( .A(mult_x_254_n128), .B(mult_x_254_n132), .C(n2497), .CO(
n2496), .S(FPMULT_Sgf_operation_EVEN1_right_N7) );
CMPR32X2TS U3245 ( .A(mult_x_254_n133), .B(n2499), .C(n2498), .CO(n2497),
.S(FPMULT_Sgf_operation_EVEN1_right_N6) );
ADDHXLTS U3246 ( .A(n2501), .B(n2500), .CO(n2613), .S(
FPMULT_Sgf_operation_EVEN1_right_N1) );
NOR2XLTS U3247 ( .A(n2618), .B(n2215), .Y(n2506) );
BUFX3TS U3248 ( .A(FPMULT_Op_MX[11]), .Y(n2580) );
NAND2X1TS U3249 ( .A(n2580), .B(FPMULT_Op_MY[6]), .Y(n2595) );
INVX2TS U3250 ( .A(n2595), .Y(n2505) );
BUFX4TS U3251 ( .A(FPMULT_Op_MX[7]), .Y(n2563) );
AOI22X1TS U3252 ( .A0(n2563), .A1(n2289), .B0(n2255), .B1(n2624), .Y(n2502)
);
BUFX4TS U3253 ( .A(FPMULT_Op_MX[9]), .Y(n2621) );
INVX4TS U3254 ( .A(n2621), .Y(n2628) );
AOI22X1TS U3255 ( .A0(n2621), .A1(n2262), .B0(n2263), .B1(n2628), .Y(n2523)
);
AOI22X1TS U3256 ( .A0(n2621), .A1(n2223), .B0(FPMULT_Op_MY[10]), .B1(n2628),
.Y(n2592) );
OAI22X1TS U3257 ( .A0(n2632), .A1(n2523), .B0(n2503), .B1(n2592), .Y(n2504)
);
CMPR32X2TS U3258 ( .A(n2506), .B(n2505), .C(n2504), .CO(mult_x_254_n42), .S(
mult_x_254_n43) );
NAND2X1TS U3259 ( .A(n2580), .B(FPMULT_Op_MY[1]), .Y(n2589) );
INVX2TS U3260 ( .A(n2589), .Y(n2510) );
AOI22X1TS U3261 ( .A0(n2581), .A1(n2272), .B0(FPMULT_Op_MX[6]), .B1(n2564),
.Y(n2507) );
AOI22X1TS U3262 ( .A0(n2563), .A1(n2259), .B0(n2260), .B1(n2624), .Y(n2529)
);
AOI22X1TS U3263 ( .A0(n2563), .A1(n2222), .B0(FPMULT_Op_MY[8]), .B1(n2624),
.Y(n2577) );
OAI22X1TS U3264 ( .A0(n2623), .A1(n2529), .B0(n2508), .B1(n2577), .Y(n2509)
);
CMPR32X2TS U3265 ( .A(n2511), .B(n2510), .C(n2509), .CO(mult_x_254_n71), .S(
mult_x_254_n72) );
AOI22X1TS U3266 ( .A0(FPMULT_Op_MX[10]), .A1(n2628), .B0(n2621), .B1(n2307),
.Y(n2512) );
AOI22X1TS U3267 ( .A0(FPMULT_Op_MX[11]), .A1(n2262), .B0(n2263), .B1(n2618),
.Y(n2549) );
AOI22X1TS U3268 ( .A0(FPMULT_Op_MX[11]), .A1(n2223), .B0(FPMULT_Op_MY[10]),
.B1(n2618), .Y(n2514) );
OAI22X1TS U3269 ( .A0(n2617), .A1(n2549), .B0(n2513), .B1(n2514), .Y(
mult_x_254_n157) );
AOI22X1TS U3270 ( .A0(FPMULT_Op_MX[11]), .A1(n2259), .B0(n2260), .B1(n2618),
.Y(n2515) );
OAI22X1TS U3271 ( .A0(n2617), .A1(n2514), .B0(n2513), .B1(n2515), .Y(
mult_x_254_n158) );
AOI22X1TS U3272 ( .A0(FPMULT_Op_MX[11]), .A1(n2222), .B0(FPMULT_Op_MY[8]),
.B1(n2618), .Y(n2516) );
OAI22X1TS U3273 ( .A0(n2617), .A1(n2515), .B0(n2513), .B1(n2516), .Y(
mult_x_254_n159) );
AOI22X1TS U3274 ( .A0(FPMULT_Op_MX[11]), .A1(n2257), .B0(n2258), .B1(n4529),
.Y(n2517) );
OAI22X1TS U3275 ( .A0(n2617), .A1(n2516), .B0(n2513), .B1(n2517), .Y(
mult_x_254_n160) );
AOI22X1TS U3276 ( .A0(n2580), .A1(n2219), .B0(FPMULT_Op_MY[6]), .B1(n4529),
.Y(n2518) );
OAI22X1TS U3277 ( .A0(n2617), .A1(n2517), .B0(n2513), .B1(n2518), .Y(
mult_x_254_n161) );
AOI22X1TS U3278 ( .A0(n2580), .A1(n2214), .B0(FPMULT_Op_MY[5]), .B1(n4529),
.Y(n2519) );
OAI22X1TS U3279 ( .A0(n2617), .A1(n2518), .B0(n2513), .B1(n2519), .Y(
mult_x_254_n162) );
AOI22X1TS U3280 ( .A0(n2580), .A1(n2218), .B0(FPMULT_Op_MY[4]), .B1(n4529),
.Y(n2520) );
OAI22X1TS U3281 ( .A0(n2617), .A1(n2519), .B0(n2513), .B1(n2520), .Y(
mult_x_254_n163) );
AOI22X1TS U3282 ( .A0(n2580), .A1(n2211), .B0(FPMULT_Op_MY[3]), .B1(n4529),
.Y(n2521) );
OAI22X1TS U3283 ( .A0(n2617), .A1(n2520), .B0(n2513), .B1(n2521), .Y(
mult_x_254_n164) );
AOI22X1TS U3284 ( .A0(n2580), .A1(n2216), .B0(FPMULT_Op_MY[2]), .B1(n4529),
.Y(n2522) );
OAI22X1TS U3285 ( .A0(n2617), .A1(n2521), .B0(n2513), .B1(n2522), .Y(
mult_x_254_n165) );
AOI22X1TS U3286 ( .A0(n2580), .A1(n2212), .B0(FPMULT_Op_MY[1]), .B1(n4529),
.Y(n2561) );
OAI22X1TS U3287 ( .A0(n2617), .A1(n2522), .B0(n2513), .B1(n2561), .Y(
mult_x_254_n166) );
OAI22X1TS U3288 ( .A0(n2628), .A1(n2632), .B0(n2503), .B1(n2523), .Y(
mult_x_254_n170) );
AOI22X1TS U3289 ( .A0(n2621), .A1(n2259), .B0(n2260), .B1(n2628), .Y(n2591)
);
AOI22X1TS U3290 ( .A0(n2621), .A1(n2222), .B0(FPMULT_Op_MY[8]), .B1(n2628),
.Y(n2524) );
OAI22X1TS U3291 ( .A0(n2632), .A1(n2591), .B0(n2503), .B1(n2524), .Y(
mult_x_254_n173) );
AOI22X1TS U3292 ( .A0(n2621), .A1(n2257), .B0(n2258), .B1(n2628), .Y(n2525)
);
OAI22X1TS U3293 ( .A0(n2632), .A1(n2524), .B0(n2503), .B1(n2525), .Y(
mult_x_254_n174) );
AOI22X1TS U3294 ( .A0(n2621), .A1(n2219), .B0(FPMULT_Op_MY[6]), .B1(n2628),
.Y(n2526) );
OAI22X1TS U3295 ( .A0(n2632), .A1(n2525), .B0(n2503), .B1(n2526), .Y(
mult_x_254_n175) );
AOI22X1TS U3296 ( .A0(n2621), .A1(n2214), .B0(FPMULT_Op_MY[5]), .B1(n2628),
.Y(n2584) );
OAI22X1TS U3297 ( .A0(n2632), .A1(n2526), .B0(n2503), .B1(n2584), .Y(
mult_x_254_n176) );
AOI22X1TS U3298 ( .A0(n2621), .A1(n2218), .B0(FPMULT_Op_MY[4]), .B1(n2628),
.Y(n2583) );
AOI22X1TS U3299 ( .A0(n2621), .A1(n2211), .B0(FPMULT_Op_MY[3]), .B1(n2628),
.Y(n2527) );
OAI22X1TS U3300 ( .A0(n2632), .A1(n2583), .B0(n2503), .B1(n2527), .Y(
mult_x_254_n178) );
AOI22X1TS U3301 ( .A0(n2621), .A1(n2216), .B0(FPMULT_Op_MY[2]), .B1(n2628),
.Y(n2528) );
OAI22X1TS U3302 ( .A0(n2632), .A1(n2527), .B0(n2503), .B1(n2528), .Y(
mult_x_254_n179) );
AOI22X1TS U3303 ( .A0(n2621), .A1(n2212), .B0(FPMULT_Op_MY[1]), .B1(n2628),
.Y(n2566) );
OAI22X1TS U3304 ( .A0(n2632), .A1(n2528), .B0(n2503), .B1(n2566), .Y(
mult_x_254_n180) );
AOI22X1TS U3305 ( .A0(n2263), .A1(n2624), .B0(n2563), .B1(n2262), .Y(n2593)
);
AOI22X1TS U3306 ( .A0(FPMULT_Op_MY[10]), .A1(n2624), .B0(n2563), .B1(n2223),
.Y(n2530) );
OAI22X1TS U3307 ( .A0(n2623), .A1(n2593), .B0(n2508), .B1(n2530), .Y(
mult_x_254_n185) );
OAI22X1TS U3308 ( .A0(n2623), .A1(n2530), .B0(n2508), .B1(n2529), .Y(
mult_x_254_n186) );
AOI22X1TS U3309 ( .A0(n2563), .A1(n2257), .B0(n2258), .B1(n2624), .Y(n2576)
);
AOI22X1TS U3310 ( .A0(n2563), .A1(n2219), .B0(FPMULT_Op_MY[6]), .B1(n2624),
.Y(n2531) );
OAI22X1TS U3311 ( .A0(n2623), .A1(n2576), .B0(n2508), .B1(n2531), .Y(
mult_x_254_n189) );
AOI22X1TS U3312 ( .A0(n2563), .A1(n2214), .B0(FPMULT_Op_MY[5]), .B1(n2624),
.Y(n2532) );
OAI22X1TS U3313 ( .A0(n2623), .A1(n2531), .B0(n2508), .B1(n2532), .Y(
mult_x_254_n190) );
AOI22X1TS U3314 ( .A0(n2563), .A1(n2218), .B0(FPMULT_Op_MY[4]), .B1(n2624),
.Y(n2533) );
OAI22X1TS U3315 ( .A0(n2623), .A1(n2532), .B0(n2508), .B1(n2533), .Y(
mult_x_254_n191) );
AOI22X1TS U3316 ( .A0(n2563), .A1(n2211), .B0(FPMULT_Op_MY[3]), .B1(n2624),
.Y(n2570) );
OAI22X1TS U3317 ( .A0(n2623), .A1(n2533), .B0(n2508), .B1(n2570), .Y(
mult_x_254_n192) );
AOI22X1TS U3318 ( .A0(n2563), .A1(n2216), .B0(FPMULT_Op_MY[2]), .B1(n2624),
.Y(n2569) );
AOI22X1TS U3319 ( .A0(n2563), .A1(n2212), .B0(FPMULT_Op_MY[1]), .B1(n2624),
.Y(n2535) );
OAI22X1TS U3320 ( .A0(n2623), .A1(n2569), .B0(n2508), .B1(n2535), .Y(
mult_x_254_n194) );
AOI22X1TS U3321 ( .A0(FPMULT_Op_MY[0]), .A1(n2624), .B0(n2563), .B1(n2209),
.Y(n2534) );
OAI22X1TS U3322 ( .A0(n2623), .A1(n2535), .B0(n2508), .B1(n2534), .Y(
mult_x_254_n195) );
AOI22X1TS U3323 ( .A0(n2263), .A1(n2564), .B0(n2581), .B1(n2262), .Y(n2536)
);
OAI22X1TS U3324 ( .A0(n2564), .A1(n2587), .B0(n2463), .B1(n2536), .Y(
mult_x_254_n198) );
AOI22X1TS U3325 ( .A0(FPMULT_Op_MY[10]), .A1(n2564), .B0(n2581), .B1(n2223),
.Y(n2537) );
OAI22X1TS U3326 ( .A0(n2587), .A1(n2536), .B0(n2463), .B1(n2537), .Y(
mult_x_254_n199) );
AOI22X1TS U3327 ( .A0(n2581), .A1(n2259), .B0(n2260), .B1(n2564), .Y(n2586)
);
OAI22X1TS U3328 ( .A0(n2587), .A1(n2537), .B0(n2463), .B1(n2586), .Y(
mult_x_254_n200) );
AOI22X1TS U3329 ( .A0(n2581), .A1(n2222), .B0(FPMULT_Op_MY[8]), .B1(n2564),
.Y(n2585) );
AOI22X1TS U3330 ( .A0(n2581), .A1(n2257), .B0(n2258), .B1(n2564), .Y(n2538)
);
OAI22X1TS U3331 ( .A0(n2587), .A1(n2585), .B0(n2463), .B1(n2538), .Y(
mult_x_254_n202) );
AOI22X1TS U3332 ( .A0(n2581), .A1(n2219), .B0(FPMULT_Op_MY[6]), .B1(n2564),
.Y(n2539) );
OAI22X1TS U3333 ( .A0(n2587), .A1(n2538), .B0(n2463), .B1(n2539), .Y(
mult_x_254_n203) );
AOI22X1TS U3334 ( .A0(n2581), .A1(n2214), .B0(FPMULT_Op_MY[5]), .B1(n2564),
.Y(n2540) );
OAI22X1TS U3335 ( .A0(n2587), .A1(n2539), .B0(n2463), .B1(n2540), .Y(
mult_x_254_n204) );
AOI22X1TS U3336 ( .A0(n2581), .A1(n2218), .B0(FPMULT_Op_MY[4]), .B1(n2564),
.Y(n2541) );
OAI22X1TS U3337 ( .A0(n2587), .A1(n2540), .B0(n2463), .B1(n2541), .Y(
mult_x_254_n205) );
AOI22X1TS U3338 ( .A0(n2581), .A1(n2211), .B0(FPMULT_Op_MY[3]), .B1(n2564),
.Y(n2542) );
OAI22X1TS U3339 ( .A0(n2587), .A1(n2541), .B0(n2463), .B1(n2542), .Y(
mult_x_254_n206) );
AOI22X1TS U3340 ( .A0(n2581), .A1(n2216), .B0(FPMULT_Op_MY[2]), .B1(n2564),
.Y(n2544) );
OAI22X1TS U3341 ( .A0(n2587), .A1(n2542), .B0(n2463), .B1(n2544), .Y(
mult_x_254_n207) );
OAI22X1TS U3342 ( .A0(n2587), .A1(n2544), .B0(n2463), .B1(n2543), .Y(
mult_x_254_n208) );
AOI22X1TS U3343 ( .A0(n2263), .A1(n2582), .B0(n2567), .B1(n2203), .Y(n2545)
);
OAI22X1TS U3344 ( .A0(n2582), .A1(n2635), .B0(n2466), .B1(n2545), .Y(
mult_x_254_n212) );
AOI22X1TS U3345 ( .A0(FPMULT_Op_MY[10]), .A1(n2582), .B0(n2567), .B1(n2223),
.Y(n2609) );
OAI22X1TS U3346 ( .A0(n2635), .A1(n2545), .B0(n2466), .B1(n2609), .Y(
mult_x_254_n213) );
AOI22X1TS U3347 ( .A0(n2567), .A1(n2259), .B0(n2260), .B1(n2582), .Y(n2608)
);
AOI22X1TS U3348 ( .A0(n2567), .A1(n2222), .B0(FPMULT_Op_MY[8]), .B1(n2582),
.Y(n2546) );
OAI22X1TS U3349 ( .A0(n2635), .A1(n2608), .B0(n2466), .B1(n2546), .Y(
mult_x_254_n215) );
AOI22X1TS U3350 ( .A0(n2567), .A1(n2257), .B0(n2258), .B1(n2582), .Y(n2568)
);
OAI22X1TS U3351 ( .A0(n2635), .A1(n2546), .B0(n2466), .B1(n2568), .Y(
mult_x_254_n216) );
AOI22X1TS U3352 ( .A0(n2567), .A1(n2214), .B0(FPMULT_Op_MY[5]), .B1(n2582),
.Y(n2633) );
AOI22X1TS U3353 ( .A0(n2567), .A1(n2218), .B0(FPMULT_Op_MY[4]), .B1(n2582),
.Y(n2548) );
OAI22X1TS U3354 ( .A0(n2635), .A1(n2633), .B0(n2466), .B1(n2548), .Y(
mult_x_254_n219) );
OAI22X1TS U3355 ( .A0(n2635), .A1(n2548), .B0(n2466), .B1(n2547), .Y(
mult_x_254_n220) );
OAI22X1TS U3356 ( .A0(n2618), .A1(n2617), .B0(n2513), .B1(n2549), .Y(n2556)
);
NAND2X1TS U3357 ( .A(n2580), .B(FPMULT_Op_MY[10]), .Y(n2555) );
CMPR32X2TS U3358 ( .A(mult_x_254_n35), .B(mult_x_254_n33), .C(n2550), .CO(
n2553), .S(FPMULT_Sgf_operation_EVEN1_right_N21) );
AOI21X1TS U3359 ( .A0(FPMULT_Op_MX[10]), .A1(n2621), .B0(n4529), .Y(n2552)
);
OAI221XLTS U3360 ( .A0(FPMULT_Op_MY[10]), .A1(n2263), .B0(n2223), .B1(n2262),
.C0(FPMULT_Op_MX[11]), .Y(n2551) );
XNOR2X1TS U3361 ( .A(n2552), .B(n2551), .Y(n2560) );
CMPR32X2TS U3362 ( .A(mult_x_254_n32), .B(n2554), .C(n2553), .CO(n2558), .S(
FPMULT_Sgf_operation_EVEN1_right_N22) );
CMPR32X2TS U3363 ( .A(n2556), .B(n2555), .C(mult_x_254_n31), .CO(n2557), .S(
n2554) );
XNOR2X1TS U3364 ( .A(n2558), .B(n2557), .Y(n2559) );
OAI21XLTS U3365 ( .A0(n2309), .A1(n2311), .B0(n2567), .Y(mult_x_254_n211) );
NOR2X1TS U3366 ( .A(n2618), .B(n2209), .Y(n2611) );
NOR2XLTS U3367 ( .A(n2580), .B(FPMULT_Op_MY[0]), .Y(n2562) );
OAI21X1TS U3368 ( .A0(n2564), .A1(n2272), .B0(n2563), .Y(mult_x_254_n183) );
AOI22X1TS U3369 ( .A0(n2621), .A1(n2209), .B0(FPMULT_Op_MY[0]), .B1(n2628),
.Y(n2565) );
OAI22X1TS U3370 ( .A0(n2632), .A1(n2566), .B0(n2503), .B1(n2565), .Y(n2573)
);
AOI22X1TS U3371 ( .A0(n2567), .A1(n2219), .B0(FPMULT_Op_MY[6]), .B1(n2582),
.Y(n2634) );
OAI22X1TS U3372 ( .A0(n2635), .A1(n2568), .B0(n2466), .B1(n2634), .Y(n2572)
);
OAI22X1TS U3373 ( .A0(n2623), .A1(n2570), .B0(n2508), .B1(n2569), .Y(n2571)
);
CMPR32X2TS U3374 ( .A(n2573), .B(n2572), .C(n2571), .CO(mult_x_254_n117),
.S(mult_x_254_n118) );
AOI22X1TS U3375 ( .A0(FPMULT_Op_MX[1]), .A1(n2219), .B0(FPMULT_Op_MY[6]),
.B1(n4530), .Y(n2574) );
AOI22X1TS U3376 ( .A0(FPMULT_Op_MY[10]), .A1(n2309), .B0(FPMULT_Op_MX[1]),
.B1(n2223), .Y(n2575) );
OAI22X1TS U3377 ( .A0(n2623), .A1(n2577), .B0(n2508), .B1(n2576), .Y(n2578)
);
CMPR32X2TS U3378 ( .A(n2589), .B(n2579), .C(n2578), .CO(mult_x_254_n79), .S(
mult_x_254_n80) );
NOR2X1TS U3379 ( .A(n2618), .B(n2214), .Y(mult_x_254_n151) );
NAND2X1TS U3380 ( .A(n2580), .B(FPMULT_Op_MY[4]), .Y(mult_x_254_n64) );
NOR2X1TS U3381 ( .A(n2618), .B(n2259), .Y(mult_x_254_n149) );
NAND2X1TS U3382 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MY[8]), .Y(
mult_x_254_n38) );
OAI21X1TS U3383 ( .A0(n2582), .A1(n2300), .B0(n2581), .Y(mult_x_254_n197) );
OAI22X1TS U3384 ( .A0(n2632), .A1(n2584), .B0(n2503), .B1(n2583), .Y(n2590)
);
OAI22X1TS U3385 ( .A0(n2587), .A1(n2586), .B0(n2463), .B1(n2585), .Y(n2588)
);
CMPR32X2TS U3386 ( .A(n2590), .B(n2589), .C(n2588), .CO(mult_x_254_n89), .S(
mult_x_254_n90) );
OAI22X1TS U3387 ( .A0(n2632), .A1(n2592), .B0(n2503), .B1(n2591), .Y(n2596)
);
OAI22X1TS U3388 ( .A0(n2624), .A1(n2623), .B0(n2508), .B1(n2593), .Y(n2594)
);
CMPR32X2TS U3389 ( .A(n2596), .B(n2595), .C(n2594), .CO(mult_x_254_n47), .S(
mult_x_254_n48) );
CMPR32X2TS U3390 ( .A(n2599), .B(n2598), .C(n2597), .CO(n2600), .S(
FPMULT_Sgf_operation_EVEN1_right_N3) );
CMPR32X2TS U3391 ( .A(n2602), .B(n2601), .C(n2600), .CO(n2603), .S(
FPMULT_Sgf_operation_EVEN1_right_N4) );
CMPR32X2TS U3392 ( .A(n2605), .B(n2604), .C(n2603), .CO(n2498), .S(
FPMULT_Sgf_operation_EVEN1_right_N5) );
ADDHXLTS U3393 ( .A(n2607), .B(n2606), .CO(mult_x_254_n136), .S(n2604) );
AOI21X1TS U3394 ( .A0(n2263), .A1(n2210), .B0(n4530), .Y(n2612) );
OAI22X1TS U3395 ( .A0(n2635), .A1(n2609), .B0(n2466), .B1(n2608), .Y(n2610)
);
CMPR32X2TS U3396 ( .A(n2612), .B(n2611), .C(n2610), .CO(mult_x_254_n98), .S(
mult_x_254_n99) );
INVX2TS U3397 ( .A(mult_x_254_n64), .Y(mult_x_254_n63) );
INVX2TS U3398 ( .A(mult_x_254_n38), .Y(mult_x_254_n37) );
CMPR32X2TS U3399 ( .A(n2615), .B(n2614), .C(n2613), .CO(n2597), .S(
FPMULT_Sgf_operation_EVEN1_right_N2) );
AOI22X1TS U3400 ( .A0(n2263), .A1(n2309), .B0(FPMULT_Op_MX[1]), .B1(n2203),
.Y(n2616) );
ADDHXLTS U3401 ( .A(n2620), .B(n2619), .CO(mult_x_254_n106), .S(
mult_x_254_n107) );
OAI21XLTS U3402 ( .A0(n2624), .A1(n2289), .B0(n2621), .Y(mult_x_254_n169) );
AOI22X1TS U3403 ( .A0(FPMULT_Op_MX[1]), .A1(n2215), .B0(n2258), .B1(n4530),
.Y(n2622) );
ADDHXLTS U3404 ( .A(n2626), .B(n2625), .CO(mult_x_254_n129), .S(
mult_x_254_n130) );
AOI22X1TS U3405 ( .A0(FPMULT_Op_MX[1]), .A1(n2213), .B0(n2260), .B1(n4530),
.Y(n2627) );
ADDHXLTS U3406 ( .A(n2630), .B(n2629), .CO(mult_x_254_n119), .S(
mult_x_254_n120) );
AOI22X1TS U3407 ( .A0(FPMULT_Op_MX[1]), .A1(n2222), .B0(FPMULT_Op_MY[8]),
.B1(n4530), .Y(n2631) );
OAI22X1TS U3408 ( .A0(n2635), .A1(n2634), .B0(n2466), .B1(n2633), .Y(n2636)
);
CMPR32X2TS U3409 ( .A(n2638), .B(n2637), .C(n2636), .CO(mult_x_254_n124),
.S(mult_x_254_n125) );
CMPR32X4TS U3410 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[15]), .C(n2639),
.CO(n2641), .S(n2807) );
INVX2TS U3411 ( .A(n2642), .Y(n2776) );
AOI22X1TS U3412 ( .A0(n2807), .A1(n2776), .B0(n2642), .B1(n2808), .Y(n2640)
);
CMPR32X2TS U3413 ( .A(FPMULT_Op_MX[4]), .B(n2256), .C(n2641), .CO(n2671),
.S(n2642) );
INVX2TS U3414 ( .A(n2736), .Y(n2735) );
AOI22X1TS U3415 ( .A0(n2736), .A1(n2836), .B0(n2835), .B1(n2735), .Y(n2744)
);
OAI221X4TS U3416 ( .A0(n2642), .A1(n2835), .B0(n2776), .B1(n2836), .C0(n2846), .Y(n2844) );
INVX3TS U3417 ( .A(DP_OP_454J221_123_2743_n367), .Y(n2771) );
AOI22X1TS U3418 ( .A0(DP_OP_454J221_123_2743_n367), .A1(n2836), .B0(n2835),
.B1(n2771), .Y(n2643) );
OAI22X1TS U3419 ( .A0(n2846), .A1(n2744), .B0(n2844), .B1(n2643), .Y(n2670)
);
CMPR32X2TS U3420 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[13]), .C(n2644),
.CO(n2651), .S(n2736) );
CMPR32X4TS U3421 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[13]), .C(n2645),
.CO(n2648), .S(n2889) );
BUFX4TS U3422 ( .A(n2649), .Y(n2794) );
CMPR32X2TS U3423 ( .A(FPMULT_Op_MY[3]), .B(n2261), .C(n2646), .CO(n2666),
.S(n2812) );
INVX2TS U3424 ( .A(n2810), .Y(n2809) );
AOI22X1TS U3425 ( .A0(n2810), .A1(n2794), .B0(n2889), .B1(n2809), .Y(n2647)
);
INVX4TS U3426 ( .A(DP_OP_454J221_123_2743_n453), .Y(n2796) );
OAI32X1TS U3427 ( .A0(DP_OP_454J221_123_2743_n453), .A1(n2812), .A2(n2794),
.B0(n2647), .B1(n2796), .Y(n2656) );
INVX2TS U3428 ( .A(n2652), .Y(n2706) );
AOI22X1TS U3429 ( .A0(n2889), .A1(n2706), .B0(n2652), .B1(n2649), .Y(n2650)
);
BUFX4TS U3430 ( .A(n2650), .Y(n2821) );
INVX2TS U3431 ( .A(n2743), .Y(n2742) );
AOI22X1TS U3432 ( .A0(n2743), .A1(n2808), .B0(n2807), .B1(n2742), .Y(n2665)
);
AOI22X1TS U3433 ( .A0(n2736), .A1(n2808), .B0(n2807), .B1(n2735), .Y(n2659)
);
OAI22X1TS U3434 ( .A0(n2821), .A1(n2665), .B0(n2653), .B1(n2659), .Y(n2655)
);
OAI32X1TS U3435 ( .A0(n2836), .A1(DP_OP_454J221_123_2743_n367), .A2(n2846),
.B0(n2844), .B1(n2836), .Y(n2668) );
CMPR32X2TS U3436 ( .A(n2656), .B(n2655), .C(n2654), .CO(n2669), .S(n2780) );
INVX2TS U3437 ( .A(n2812), .Y(n2811) );
AOI22X1TS U3438 ( .A0(n2812), .A1(n2794), .B0(n2889), .B1(n2811), .Y(n2657)
);
OAI32X1TS U3439 ( .A0(DP_OP_454J221_123_2743_n453), .A1(n2743), .A2(n2649),
.B0(n2657), .B1(n2796), .Y(n2664) );
AOI22X1TS U3440 ( .A0(DP_OP_454J221_123_2743_n367), .A1(n2808), .B0(n2807),
.B1(n2771), .Y(n2658) );
OAI22X1TS U3441 ( .A0(n2821), .A1(n2659), .B0(n2653), .B1(n2658), .Y(n2663)
);
OAI32X1TS U3442 ( .A0(n2808), .A1(DP_OP_454J221_123_2743_n367), .A2(n2821),
.B0(n2653), .B1(n2808), .Y(n2801) );
AOI22X1TS U3443 ( .A0(n2743), .A1(n2794), .B0(n2889), .B1(n2742), .Y(n2660)
);
OAI32X1TS U3444 ( .A0(DP_OP_454J221_123_2743_n453), .A1(n2736), .A2(n2649),
.B0(n2660), .B1(n2796), .Y(n2692) );
AOI21X1TS U3445 ( .A0(DP_OP_454J221_123_2743_n367), .A1(
DP_OP_454J221_123_2743_n453), .B0(n2649), .Y(n2832) );
NAND2X1TS U3446 ( .A(n2889), .B(n2796), .Y(n2662) );
AOI22X1TS U3447 ( .A0(n2736), .A1(n2794), .B0(n2889), .B1(n2735), .Y(n2661)
);
OAI22X1TS U3448 ( .A0(DP_OP_454J221_123_2743_n367), .A1(n2662), .B0(n2661),
.B1(n2796), .Y(n2831) );
ADDHXLTS U3449 ( .A(n2664), .B(n2663), .CO(n2779), .S(n2799) );
AOI22X1TS U3450 ( .A0(n2812), .A1(n2808), .B0(n2807), .B1(n2811), .Y(n2750)
);
OAI22X1TS U3451 ( .A0(n2821), .A1(n2750), .B0(n2653), .B1(n2665), .Y(n2834)
);
INVX2TS U3452 ( .A(n2838), .Y(n2837) );
AOI22X1TS U3453 ( .A0(n2838), .A1(n2794), .B0(n2889), .B1(n2837), .Y(n2667)
);
OAI32X1TS U3454 ( .A0(DP_OP_454J221_123_2743_n453), .A1(n2810), .A2(n2794),
.B0(n2667), .B1(n2796), .Y(n2833) );
CMPR32X2TS U3455 ( .A(n2670), .B(n2669), .C(n2668), .CO(n2782), .S(n2802) );
CMPR32X4TS U3456 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MX[17]), .C(n2671),
.CO(n2696), .S(n2835) );
XNOR2X1TS U3457 ( .A(n2711), .B(FPMULT_Op_MX[11]), .Y(n2672) );
BUFX4TS U3458 ( .A(n2672), .Y(n2757) );
CMPR32X4TS U3459 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[21]), .C(n2673),
.CO(n2674), .S(n2876) );
CMPR32X2TS U3460 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .C(n2674),
.CO(n2711), .S(n2676) );
INVX2TS U3461 ( .A(n2676), .Y(n2758) );
AOI22X1TS U3462 ( .A0(n2876), .A1(n2758), .B0(n2676), .B1(n2873), .Y(n2675)
);
BUFX4TS U3463 ( .A(n2675), .Y(n2770) );
OAI221X4TS U3464 ( .A0(n2676), .A1(n2757), .B0(n2758), .B1(n2753), .C0(n2770), .Y(n2751) );
OAI32X1TS U3465 ( .A0(n2753), .A1(DP_OP_454J221_123_2743_n367), .A2(n2770),
.B0(n2751), .B1(n2753), .Y(n2783) );
CMPR32X2TS U3466 ( .A(DP_OP_454J221_123_2743_n40), .B(
DP_OP_454J221_123_2743_n44), .C(n2677), .CO(n2754), .S(
FPMULT_Sgf_operation_EVEN1_middle_N21) );
CMPR32X2TS U3467 ( .A(DP_OP_454J221_123_2743_n49), .B(
DP_OP_454J221_123_2743_n45), .C(n2678), .CO(n2677), .S(
FPMULT_Sgf_operation_EVEN1_middle_N20) );
CMPR32X2TS U3468 ( .A(DP_OP_454J221_123_2743_n50), .B(
DP_OP_454J221_123_2743_n56), .C(n2679), .CO(n2678), .S(
FPMULT_Sgf_operation_EVEN1_middle_N19) );
CMPR32X2TS U3469 ( .A(DP_OP_454J221_123_2743_n57), .B(
DP_OP_454J221_123_2743_n62), .C(n2680), .CO(n2679), .S(
FPMULT_Sgf_operation_EVEN1_middle_N18) );
CMPR32X2TS U3470 ( .A(DP_OP_454J221_123_2743_n63), .B(
DP_OP_454J221_123_2743_n70), .C(n2681), .CO(n2680), .S(
FPMULT_Sgf_operation_EVEN1_middle_N17) );
CMPR32X2TS U3471 ( .A(DP_OP_454J221_123_2743_n71), .B(
DP_OP_454J221_123_2743_n78), .C(n2682), .CO(n2681), .S(
FPMULT_Sgf_operation_EVEN1_middle_N16) );
CMPR32X2TS U3472 ( .A(DP_OP_454J221_123_2743_n79), .B(
DP_OP_454J221_123_2743_n88), .C(n2683), .CO(n2682), .S(
FPMULT_Sgf_operation_EVEN1_middle_N15) );
CMPR32X2TS U3473 ( .A(DP_OP_454J221_123_2743_n89), .B(
DP_OP_454J221_123_2743_n97), .C(n2684), .CO(n2683), .S(
FPMULT_Sgf_operation_EVEN1_middle_N14) );
CMPR32X2TS U3474 ( .A(DP_OP_454J221_123_2743_n98), .B(
DP_OP_454J221_123_2743_n105), .C(n2685), .CO(n2684), .S(
FPMULT_Sgf_operation_EVEN1_middle_N13) );
CMPR32X2TS U3475 ( .A(DP_OP_454J221_123_2743_n106), .B(
DP_OP_454J221_123_2743_n113), .C(n2686), .CO(n2685), .S(
FPMULT_Sgf_operation_EVEN1_middle_N12) );
CMPR32X2TS U3476 ( .A(DP_OP_454J221_123_2743_n122), .B(
DP_OP_454J221_123_2743_n127), .C(n2687), .CO(n2784), .S(
FPMULT_Sgf_operation_EVEN1_middle_N10) );
CMPR32X2TS U3477 ( .A(DP_OP_454J221_123_2743_n128), .B(
DP_OP_454J221_123_2743_n134), .C(n2688), .CO(n2687), .S(
FPMULT_Sgf_operation_EVEN1_middle_N9) );
CMPR32X2TS U3478 ( .A(DP_OP_454J221_123_2743_n135), .B(
DP_OP_454J221_123_2743_n139), .C(n2689), .CO(n2688), .S(
FPMULT_Sgf_operation_EVEN1_middle_N8) );
CMPR32X2TS U3479 ( .A(n2690), .B(DP_OP_454J221_123_2743_n144), .C(
DP_OP_454J221_123_2743_n140), .CO(n2689), .S(
FPMULT_Sgf_operation_EVEN1_middle_N7) );
CMPR32X2TS U3480 ( .A(n2693), .B(n2692), .C(n2691), .CO(n2800), .S(
FPMULT_Sgf_operation_EVEN1_middle_N2) );
CMPR32X4TS U3481 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[19]), .C(n2695),
.CO(n2700), .S(n2869) );
INVX2TS U3482 ( .A(n2206), .Y(n2775) );
AOI22X1TS U3483 ( .A0(n2206), .A1(n2869), .B0(n2870), .B1(n2775), .Y(n2732)
);
INVX2TS U3484 ( .A(n2698), .Y(n2825) );
AOI22X1TS U3485 ( .A0(n2698), .A1(n2836), .B0(n2835), .B1(n2825), .Y(n2697)
);
OAI221X4TS U3486 ( .A0(n2698), .A1(n2869), .B0(n2825), .B1(n2870), .C0(n2883), .Y(n2881) );
OAI22X1TS U3487 ( .A0(n2732), .A1(n2881), .B0(n2870), .B1(n2883), .Y(n2830)
);
INVX2TS U3488 ( .A(n2830), .Y(n2705) );
CLKXOR2X4TS U3489 ( .A(n2263), .B(n2699), .Y(n2788) );
AOI22X1TS U3490 ( .A0(n2876), .A1(n2788), .B0(n2787), .B1(n2873), .Y(n2826)
);
INVX2TS U3491 ( .A(n2702), .Y(n2777) );
AOI22X1TS U3492 ( .A0(n2702), .A1(n2870), .B0(n2869), .B1(n2777), .Y(n2701)
);
OAI221X4TS U3493 ( .A0(n2702), .A1(n2876), .B0(n2777), .B1(n2873), .C0(n2887), .Y(n2885) );
AOI22X1TS U3494 ( .A0(n2876), .A1(n2793), .B0(n2795), .B1(n2873), .Y(n2726)
);
OAI22X1TS U3495 ( .A0(n2826), .A1(n2887), .B0(n2885), .B1(n2726), .Y(n2704)
);
CMPR32X2TS U3496 ( .A(n2705), .B(DP_OP_454J221_123_2743_n58), .C(n2704),
.CO(DP_OP_454J221_123_2743_n51), .S(DP_OP_454J221_123_2743_n52) );
OAI21XLTS U3497 ( .A0(n2649), .A1(n2706), .B0(n2807), .Y(n2710) );
AOI22X1TS U3498 ( .A0(n2876), .A1(n2868), .B0(n2871), .B1(n2873), .Y(n2773)
);
AOI22X1TS U3499 ( .A0(n2876), .A1(n2847), .B0(n2848), .B1(n2873), .Y(n2877)
);
OAI22X1TS U3500 ( .A0(n2887), .A1(n2773), .B0(n2885), .B1(n2877), .Y(n2709)
);
CMPR32X2TS U3501 ( .A(n2710), .B(n2794), .C(n2709), .CO(
DP_OP_454J221_123_2743_n75), .S(DP_OP_454J221_123_2743_n76) );
NAND2X4TS U3502 ( .A(n2711), .B(FPMULT_Op_MX[11]), .Y(n2765) );
AOI22X1TS U3503 ( .A0(n2772), .A1(n2791), .B0(n2793), .B1(n2765), .Y(
DP_OP_454J221_123_2743_n162) );
AOI22X1TS U3504 ( .A0(n2772), .A1(n2868), .B0(n2791), .B1(n2765), .Y(
DP_OP_454J221_123_2743_n163) );
AOI22X1TS U3505 ( .A0(n2772), .A1(n2847), .B0(n2868), .B1(n2765), .Y(
DP_OP_454J221_123_2743_n164) );
AOI22X1TS U3506 ( .A0(n2772), .A1(n2875), .B0(n2847), .B1(n2765), .Y(
DP_OP_454J221_123_2743_n165) );
AOI22X1TS U3507 ( .A0(n2772), .A1(n2837), .B0(n2875), .B1(n2765), .Y(
DP_OP_454J221_123_2743_n166) );
AOI22X1TS U3508 ( .A0(n2772), .A1(n2809), .B0(n2837), .B1(n2765), .Y(
DP_OP_454J221_123_2743_n167) );
AOI22X1TS U3509 ( .A0(n2772), .A1(n2811), .B0(n2809), .B1(n2765), .Y(
DP_OP_454J221_123_2743_n168) );
AOI22X1TS U3510 ( .A0(n2772), .A1(n2742), .B0(n2811), .B1(n2765), .Y(
DP_OP_454J221_123_2743_n169) );
AOI22X1TS U3511 ( .A0(n2772), .A1(n2735), .B0(n2742), .B1(n2765), .Y(
DP_OP_454J221_123_2743_n170) );
AOI22X1TS U3512 ( .A0(n2772), .A1(n2771), .B0(n2735), .B1(n2765), .Y(
DP_OP_454J221_123_2743_n171) );
AOI22X1TS U3513 ( .A0(n2753), .A1(n2775), .B0(n2206), .B1(n2757), .Y(n2752)
);
AOI22X1TS U3514 ( .A0(n2753), .A1(n2787), .B0(n2788), .B1(n2757), .Y(n2714)
);
OAI22X1TS U3515 ( .A0(n2770), .A1(n2752), .B0(n2751), .B1(n2714), .Y(
DP_OP_454J221_123_2743_n175) );
AOI22X1TS U3516 ( .A0(n2753), .A1(n2795), .B0(n2793), .B1(n2757), .Y(n2715)
);
OAI22X1TS U3517 ( .A0(n2715), .A1(n2751), .B0(n2770), .B1(n2714), .Y(
DP_OP_454J221_123_2743_n176) );
AOI22X1TS U3518 ( .A0(n2753), .A1(n2798), .B0(n2791), .B1(n2757), .Y(n2716)
);
OAI22X1TS U3519 ( .A0(n2715), .A1(n2770), .B0(n2716), .B1(n2751), .Y(
DP_OP_454J221_123_2743_n177) );
AOI22X1TS U3520 ( .A0(n2753), .A1(n2871), .B0(n2868), .B1(n2757), .Y(n2717)
);
OAI22X1TS U3521 ( .A0(n2716), .A1(n2770), .B0(n2717), .B1(n2751), .Y(
DP_OP_454J221_123_2743_n178) );
AOI22X1TS U3522 ( .A0(n2753), .A1(n2848), .B0(n2847), .B1(n2757), .Y(n2718)
);
OAI22X1TS U3523 ( .A0(n2717), .A1(n2770), .B0(n2718), .B1(n2751), .Y(
DP_OP_454J221_123_2743_n179) );
AOI22X1TS U3524 ( .A0(n2753), .A1(n2874), .B0(n2875), .B1(n2757), .Y(n2719)
);
OAI22X1TS U3525 ( .A0(n2718), .A1(n2770), .B0(n2719), .B1(n2751), .Y(
DP_OP_454J221_123_2743_n180) );
AOI22X1TS U3526 ( .A0(n2753), .A1(n2838), .B0(n2837), .B1(n2757), .Y(n2720)
);
OAI22X1TS U3527 ( .A0(n2719), .A1(n2770), .B0(n2720), .B1(n2751), .Y(
DP_OP_454J221_123_2743_n181) );
AOI22X1TS U3528 ( .A0(n2753), .A1(n2810), .B0(n2809), .B1(n2757), .Y(n2721)
);
OAI22X1TS U3529 ( .A0(n2720), .A1(n2770), .B0(n2721), .B1(n2751), .Y(
DP_OP_454J221_123_2743_n182) );
AOI22X1TS U3530 ( .A0(n2753), .A1(n2812), .B0(n2811), .B1(n2757), .Y(n2722)
);
OAI22X1TS U3531 ( .A0(n2721), .A1(n2770), .B0(n2722), .B1(n2751), .Y(
DP_OP_454J221_123_2743_n183) );
AOI22X1TS U3532 ( .A0(n2753), .A1(n2743), .B0(n2742), .B1(n2757), .Y(n2723)
);
OAI22X1TS U3533 ( .A0(n2722), .A1(n2770), .B0(n2723), .B1(n2751), .Y(
DP_OP_454J221_123_2743_n184) );
AOI22X1TS U3534 ( .A0(n2753), .A1(n2736), .B0(n2735), .B1(n2757), .Y(n2725)
);
OAI22X1TS U3535 ( .A0(n2723), .A1(n2770), .B0(n2725), .B1(n2751), .Y(
DP_OP_454J221_123_2743_n185) );
AOI22X1TS U3536 ( .A0(n2753), .A1(DP_OP_454J221_123_2743_n367), .B0(n2771),
.B1(n2757), .Y(n2724) );
OAI22X1TS U3537 ( .A0(n2725), .A1(n2770), .B0(n2751), .B1(n2724), .Y(
DP_OP_454J221_123_2743_n186) );
AOI22X1TS U3538 ( .A0(n2876), .A1(n2791), .B0(n2798), .B1(n2873), .Y(n2774)
);
OAI22X1TS U3539 ( .A0(n2887), .A1(n2726), .B0(n2885), .B1(n2774), .Y(
DP_OP_454J221_123_2743_n191) );
AOI22X1TS U3540 ( .A0(n2876), .A1(n2837), .B0(n2838), .B1(n2873), .Y(n2884)
);
AOI22X1TS U3541 ( .A0(n2876), .A1(n2809), .B0(n2810), .B1(n2873), .Y(n2727)
);
OAI22X1TS U3542 ( .A0(n2887), .A1(n2884), .B0(n2885), .B1(n2727), .Y(
DP_OP_454J221_123_2743_n195) );
AOI22X1TS U3543 ( .A0(n2876), .A1(n2811), .B0(n2812), .B1(n2873), .Y(n2728)
);
OAI22X1TS U3544 ( .A0(n2887), .A1(n2727), .B0(n2885), .B1(n2728), .Y(
DP_OP_454J221_123_2743_n196) );
AOI22X1TS U3545 ( .A0(n2876), .A1(n2742), .B0(n2743), .B1(n2873), .Y(n2729)
);
OAI22X1TS U3546 ( .A0(n2887), .A1(n2728), .B0(n2885), .B1(n2729), .Y(
DP_OP_454J221_123_2743_n197) );
AOI22X1TS U3547 ( .A0(n2876), .A1(n2735), .B0(n2736), .B1(n2873), .Y(n2731)
);
OAI22X1TS U3548 ( .A0(n2887), .A1(n2729), .B0(n2885), .B1(n2731), .Y(
DP_OP_454J221_123_2743_n198) );
AOI22X1TS U3549 ( .A0(DP_OP_454J221_123_2743_n367), .A1(n2873), .B0(n2876),
.B1(n2771), .Y(n2730) );
OAI22X1TS U3550 ( .A0(n2887), .A1(n2731), .B0(n2885), .B1(n2730), .Y(
DP_OP_454J221_123_2743_n199) );
AOI22X1TS U3551 ( .A0(n2788), .A1(n2869), .B0(n2870), .B1(n2787), .Y(n2733)
);
OAI22X1TS U3552 ( .A0(n2732), .A1(n2883), .B0(n2733), .B1(n2881), .Y(
DP_OP_454J221_123_2743_n202) );
AOI22X1TS U3553 ( .A0(n2795), .A1(n2870), .B0(n2869), .B1(n2793), .Y(n2734)
);
OAI22X1TS U3554 ( .A0(n2733), .A1(n2883), .B0(n2881), .B1(n2734), .Y(
DP_OP_454J221_123_2743_n203) );
AOI22X1TS U3555 ( .A0(n2798), .A1(n2870), .B0(n2869), .B1(n2791), .Y(n2872)
);
OAI22X1TS U3556 ( .A0(n2883), .A1(n2734), .B0(n2881), .B1(n2872), .Y(
DP_OP_454J221_123_2743_n204) );
AOI22X1TS U3557 ( .A0(n2810), .A1(n2870), .B0(n2869), .B1(n2809), .Y(n2841)
);
AOI22X1TS U3558 ( .A0(n2812), .A1(n2870), .B0(n2869), .B1(n2811), .Y(n2806)
);
OAI22X1TS U3559 ( .A0(n2883), .A1(n2841), .B0(n2881), .B1(n2806), .Y(
DP_OP_454J221_123_2743_n210) );
AOI22X1TS U3560 ( .A0(n2743), .A1(n2870), .B0(n2869), .B1(n2742), .Y(n2805)
);
AOI22X1TS U3561 ( .A0(n2736), .A1(n2870), .B0(n2869), .B1(n2735), .Y(n2738)
);
OAI22X1TS U3562 ( .A0(n2883), .A1(n2805), .B0(n2881), .B1(n2738), .Y(
DP_OP_454J221_123_2743_n212) );
AOI22X1TS U3563 ( .A0(DP_OP_454J221_123_2743_n367), .A1(n2870), .B0(n2869),
.B1(n2771), .Y(n2737) );
OAI22X1TS U3564 ( .A0(n2883), .A1(n2738), .B0(n2881), .B1(n2737), .Y(
DP_OP_454J221_123_2743_n213) );
AOI22X1TS U3565 ( .A0(n2206), .A1(n2835), .B0(n2836), .B1(n2775), .Y(n2739)
);
OAI22X1TS U3566 ( .A0(n2739), .A1(n2844), .B0(n2836), .B1(n2846), .Y(
DP_OP_454J221_123_2743_n216) );
AOI22X1TS U3567 ( .A0(n2788), .A1(n2835), .B0(n2836), .B1(n2787), .Y(n2740)
);
OAI22X1TS U3568 ( .A0(n2739), .A1(n2846), .B0(n2740), .B1(n2844), .Y(
DP_OP_454J221_123_2743_n217) );
AOI22X1TS U3569 ( .A0(n2795), .A1(n2836), .B0(n2835), .B1(n2793), .Y(n2741)
);
OAI22X1TS U3570 ( .A0(n2740), .A1(n2846), .B0(n2844), .B1(n2741), .Y(
DP_OP_454J221_123_2743_n218) );
AOI22X1TS U3571 ( .A0(n2798), .A1(n2836), .B0(n2835), .B1(n2791), .Y(n2845)
);
OAI22X1TS U3572 ( .A0(n2846), .A1(n2741), .B0(n2844), .B1(n2845), .Y(
DP_OP_454J221_123_2743_n219) );
AOI22X1TS U3573 ( .A0(n2874), .A1(n2836), .B0(n2835), .B1(n2875), .Y(n2839)
);
AOI22X1TS U3574 ( .A0(n2838), .A1(n2836), .B0(n2835), .B1(n2837), .Y(n2818)
);
OAI22X1TS U3575 ( .A0(n2846), .A1(n2839), .B0(n2844), .B1(n2818), .Y(
DP_OP_454J221_123_2743_n223) );
AOI22X1TS U3576 ( .A0(n2743), .A1(n2836), .B0(n2835), .B1(n2742), .Y(n2815)
);
OAI22X1TS U3577 ( .A0(n2846), .A1(n2815), .B0(n2844), .B1(n2744), .Y(
DP_OP_454J221_123_2743_n227) );
AOI22X1TS U3578 ( .A0(n2206), .A1(n2807), .B0(n2808), .B1(n2775), .Y(n2745)
);
OAI22X1TS U3579 ( .A0(n2745), .A1(n2653), .B0(n2808), .B1(n2821), .Y(
DP_OP_454J221_123_2743_n231) );
AOI22X1TS U3580 ( .A0(n2788), .A1(n2807), .B0(n2808), .B1(n2787), .Y(n2746)
);
OAI22X1TS U3581 ( .A0(n2745), .A1(n2821), .B0(n2746), .B1(n2653), .Y(
DP_OP_454J221_123_2743_n232) );
AOI22X1TS U3582 ( .A0(n2795), .A1(n2808), .B0(n2807), .B1(n2793), .Y(n2747)
);
OAI22X1TS U3583 ( .A0(n2746), .A1(n2821), .B0(n2653), .B1(n2747), .Y(
DP_OP_454J221_123_2743_n233) );
AOI22X1TS U3584 ( .A0(n2798), .A1(n2808), .B0(n2807), .B1(n2791), .Y(n2748)
);
OAI22X1TS U3585 ( .A0(n2821), .A1(n2747), .B0(n2653), .B1(n2748), .Y(
DP_OP_454J221_123_2743_n234) );
AOI22X1TS U3586 ( .A0(n2871), .A1(n2808), .B0(n2807), .B1(n2868), .Y(n2749)
);
OAI22X1TS U3587 ( .A0(n2821), .A1(n2748), .B0(n2653), .B1(n2749), .Y(
DP_OP_454J221_123_2743_n235) );
AOI22X1TS U3588 ( .A0(n2848), .A1(n2808), .B0(n2807), .B1(n2847), .Y(n2820)
);
OAI22X1TS U3589 ( .A0(n2821), .A1(n2749), .B0(n2653), .B1(n2820), .Y(
DP_OP_454J221_123_2743_n236) );
AOI22X1TS U3590 ( .A0(n2810), .A1(n2808), .B0(n2807), .B1(n2809), .Y(n2813)
);
OAI22X1TS U3591 ( .A0(n2821), .A1(n2813), .B0(n2653), .B1(n2750), .Y(
DP_OP_454J221_123_2743_n240) );
AOI21X1TS U3592 ( .A0(n2775), .A1(n2796), .B0(n2649), .Y(
DP_OP_454J221_123_2743_n245) );
OAI22X1TS U3593 ( .A0(n2765), .A1(n2795), .B0(n2787), .B1(n2772), .Y(n2756)
);
OAI22X1TS U3594 ( .A0(n2753), .A1(n2770), .B0(n2752), .B1(n2751), .Y(n2755)
);
CMPR32X2TS U3595 ( .A(DP_OP_454J221_123_2743_n37), .B(
DP_OP_454J221_123_2743_n39), .C(n2754), .CO(n2759), .S(
FPMULT_Sgf_operation_EVEN1_middle_N22) );
CMPR32X2TS U3596 ( .A(n2756), .B(n2755), .C(DP_OP_454J221_123_2743_n35),
.CO(n2858), .S(n2760) );
AOI22X1TS U3597 ( .A0(n2772), .A1(n2788), .B0(n2206), .B1(n2765), .Y(n2763)
);
INVX2TS U3598 ( .A(n2756), .Y(n2762) );
OAI21XLTS U3599 ( .A0(n2873), .A1(n2758), .B0(n2757), .Y(n2761) );
CMPR32X2TS U3600 ( .A(n2760), .B(DP_OP_454J221_123_2743_n36), .C(n2759),
.CO(n2856), .S(FPMULT_Sgf_operation_EVEN1_middle_N23) );
CMPR32X2TS U3601 ( .A(n2763), .B(n2762), .C(n2761), .CO(n2766), .S(n2857) );
OAI31X1TS U3602 ( .A0(n2206), .A1(n2766), .A2(n2765), .B0(n2764), .Y(n2767)
);
XNOR2X1TS U3603 ( .A(n2768), .B(n2767), .Y(
FPMULT_Sgf_operation_EVEN1_middle_N25) );
AOI22X1TS U3604 ( .A0(n2206), .A1(n2889), .B0(n2649), .B1(n2775), .Y(n2769)
);
OAI32X1TS U3605 ( .A0(DP_OP_454J221_123_2743_n453), .A1(n2787), .A2(n2649),
.B0(n2769), .B1(n2796), .Y(DP_OP_454J221_123_2743_n246) );
NOR2X1TS U3606 ( .A(n2771), .B(n2770), .Y(DP_OP_454J221_123_2743_n187) );
NOR2X1TS U3607 ( .A(n2772), .B(n2771), .Y(DP_OP_454J221_123_2743_n172) );
OAI22X1TS U3608 ( .A0(n2887), .A1(n2774), .B0(n2885), .B1(n2773), .Y(
DP_OP_454J221_123_2743_n67) );
INVX2TS U3609 ( .A(DP_OP_454J221_123_2743_n67), .Y(
DP_OP_454J221_123_2743_n68) );
AOI22X1TS U3610 ( .A0(n2876), .A1(n2206), .B0(n2775), .B1(n2873), .Y(n2827)
);
OAI22X1TS U3611 ( .A0(n2827), .A1(n2885), .B0(n2873), .B1(n2887), .Y(
DP_OP_454J221_123_2743_n41) );
INVX2TS U3612 ( .A(DP_OP_454J221_123_2743_n41), .Y(
DP_OP_454J221_123_2743_n42) );
OAI21X1TS U3613 ( .A0(n2808), .A1(n2776), .B0(n2835), .Y(
DP_OP_454J221_123_2743_n215) );
OAI21X1TS U3614 ( .A0(n2777), .A1(n2870), .B0(n2876), .Y(
DP_OP_454J221_123_2743_n188) );
CMPR32X2TS U3615 ( .A(n2780), .B(n2779), .C(n2778), .CO(n2804), .S(
FPMULT_Sgf_operation_EVEN1_middle_N4) );
CMPR32X2TS U3616 ( .A(DP_OP_454J221_123_2743_n145), .B(n2782), .C(n2781),
.CO(n2690), .S(FPMULT_Sgf_operation_EVEN1_middle_N6) );
CMPR32X2TS U3617 ( .A(n2784), .B(n2783), .C(DP_OP_454J221_123_2743_n114),
.CO(n2686), .S(FPMULT_Sgf_operation_EVEN1_middle_N11) );
AOI22X1TS U3618 ( .A0(n2874), .A1(n2794), .B0(n2889), .B1(n2875), .Y(n2785)
);
OAI32X1TS U3619 ( .A0(DP_OP_454J221_123_2743_n453), .A1(n2838), .A2(n2649),
.B0(n2785), .B1(n2796), .Y(DP_OP_454J221_123_2743_n252) );
AOI22X1TS U3620 ( .A0(n2848), .A1(n2794), .B0(n2889), .B1(n2847), .Y(n2786)
);
OAI32X1TS U3621 ( .A0(DP_OP_454J221_123_2743_n453), .A1(n2874), .A2(n2794),
.B0(n2786), .B1(n2796), .Y(DP_OP_454J221_123_2743_n251) );
AOI22X1TS U3622 ( .A0(n2788), .A1(n2889), .B0(n2649), .B1(n2787), .Y(n2789)
);
OAI32X1TS U3623 ( .A0(DP_OP_454J221_123_2743_n453), .A1(n2795), .A2(n2649),
.B0(n2789), .B1(n2796), .Y(DP_OP_454J221_123_2743_n247) );
AOI22X1TS U3624 ( .A0(n2871), .A1(n2794), .B0(n2889), .B1(n2868), .Y(n2790)
);
OAI32X1TS U3625 ( .A0(DP_OP_454J221_123_2743_n453), .A1(n2848), .A2(n2649),
.B0(n2790), .B1(n2796), .Y(DP_OP_454J221_123_2743_n250) );
AOI22X1TS U3626 ( .A0(n2798), .A1(n2794), .B0(n2889), .B1(n2791), .Y(n2792)
);
OAI32X1TS U3627 ( .A0(DP_OP_454J221_123_2743_n453), .A1(n2871), .A2(n2649),
.B0(n2792), .B1(n2796), .Y(DP_OP_454J221_123_2743_n249) );
AOI22X1TS U3628 ( .A0(n2795), .A1(n2794), .B0(n2889), .B1(n2793), .Y(n2797)
);
OAI32X1TS U3629 ( .A0(DP_OP_454J221_123_2743_n453), .A1(n2798), .A2(n2649),
.B0(n2797), .B1(n2796), .Y(DP_OP_454J221_123_2743_n248) );
OAI32X1TS U3630 ( .A0(n2870), .A1(DP_OP_454J221_123_2743_n367), .A2(n2883),
.B0(n2881), .B1(n2870), .Y(DP_OP_454J221_123_2743_n156) );
OAI32X1TS U3631 ( .A0(n2873), .A1(DP_OP_454J221_123_2743_n367), .A2(n2887),
.B0(n2885), .B1(n2873), .Y(DP_OP_454J221_123_2743_n155) );
CMPR32X2TS U3632 ( .A(n2801), .B(n2800), .C(n2799), .CO(n2778), .S(
FPMULT_Sgf_operation_EVEN1_middle_N3) );
CMPR32X2TS U3633 ( .A(n2804), .B(n2803), .C(n2802), .CO(n2781), .S(
FPMULT_Sgf_operation_EVEN1_middle_N5) );
OAI22X1TS U3634 ( .A0(n2883), .A1(n2806), .B0(n2881), .B1(n2805), .Y(n2824)
);
AOI22X1TS U3635 ( .A0(n2874), .A1(n2808), .B0(n2807), .B1(n2875), .Y(n2819)
);
AOI22X1TS U3636 ( .A0(n2838), .A1(n2808), .B0(n2807), .B1(n2837), .Y(n2814)
);
OAI22X1TS U3637 ( .A0(n2821), .A1(n2819), .B0(n2653), .B1(n2814), .Y(n2863)
);
AOI22X1TS U3638 ( .A0(n2810), .A1(n2836), .B0(n2835), .B1(n2809), .Y(n2817)
);
AOI22X1TS U3639 ( .A0(n2812), .A1(n2836), .B0(n2835), .B1(n2811), .Y(n2816)
);
OAI22X1TS U3640 ( .A0(n2846), .A1(n2817), .B0(n2844), .B1(n2816), .Y(n2862)
);
OAI22X1TS U3641 ( .A0(n2821), .A1(n2814), .B0(n2653), .B1(n2813), .Y(n2865)
);
OAI22X1TS U3642 ( .A0(n2846), .A1(n2816), .B0(n2844), .B1(n2815), .Y(n2864)
);
OAI22X1TS U3643 ( .A0(n2846), .A1(n2818), .B0(n2844), .B1(n2817), .Y(n2860)
);
OAI22X1TS U3644 ( .A0(n2821), .A1(n2820), .B0(n2653), .B1(n2819), .Y(n2859)
);
CMPR32X2TS U3645 ( .A(n2824), .B(n2823), .C(n2822), .CO(
DP_OP_454J221_123_2743_n129), .S(DP_OP_454J221_123_2743_n130) );
OAI22X1TS U3646 ( .A0(n2827), .A1(n2887), .B0(n2826), .B1(n2885), .Y(n2828)
);
CMPR32X2TS U3647 ( .A(n2830), .B(n2829), .C(n2828), .CO(
DP_OP_454J221_123_2743_n46), .S(DP_OP_454J221_123_2743_n47) );
ADDHXLTS U3648 ( .A(n2832), .B(n2831), .CO(n2691), .S(
FPMULT_Sgf_operation_EVEN1_middle_N1) );
ADDHXLTS U3649 ( .A(n2834), .B(n2833), .CO(DP_OP_454J221_123_2743_n148), .S(
n2803) );
AOI22X1TS U3650 ( .A0(n2871), .A1(n2836), .B0(n2835), .B1(n2868), .Y(n2843)
);
AOI22X1TS U3651 ( .A0(n2848), .A1(n2836), .B0(n2835), .B1(n2847), .Y(n2840)
);
OAI22X1TS U3652 ( .A0(n2846), .A1(n2843), .B0(n2844), .B1(n2840), .Y(n2852)
);
AOI22X1TS U3653 ( .A0(n2874), .A1(n2870), .B0(n2869), .B1(n2875), .Y(n2849)
);
AOI22X1TS U3654 ( .A0(n2838), .A1(n2870), .B0(n2869), .B1(n2837), .Y(n2842)
);
OAI22X1TS U3655 ( .A0(n2883), .A1(n2849), .B0(n2881), .B1(n2842), .Y(n2851)
);
OAI22X1TS U3656 ( .A0(n2846), .A1(n2840), .B0(n2844), .B1(n2839), .Y(n2867)
);
OAI22X1TS U3657 ( .A0(n2883), .A1(n2842), .B0(n2881), .B1(n2841), .Y(n2866)
);
OAI22X1TS U3658 ( .A0(n2846), .A1(n2845), .B0(n2844), .B1(n2843), .Y(n2855)
);
AOI22X1TS U3659 ( .A0(n2848), .A1(n2870), .B0(n2869), .B1(n2847), .Y(n2880)
);
OAI22X1TS U3660 ( .A0(n2883), .A1(n2880), .B0(n2881), .B1(n2849), .Y(n2854)
);
CMPR32X2TS U3661 ( .A(n2852), .B(n2851), .C(n2850), .CO(n2853), .S(
DP_OP_454J221_123_2743_n111) );
CMPR32X2TS U3662 ( .A(n2855), .B(n2854), .C(n2853), .CO(
DP_OP_454J221_123_2743_n102), .S(DP_OP_454J221_123_2743_n103) );
CMPR32X2TS U3663 ( .A(n2858), .B(n2857), .C(n2856), .CO(n2768), .S(
FPMULT_Sgf_operation_EVEN1_middle_N24) );
ADDHXLTS U3664 ( .A(n2860), .B(n2859), .CO(DP_OP_454J221_123_2743_n131), .S(
n2822) );
ADDHXLTS U3665 ( .A(n2867), .B(n2866), .CO(n2850), .S(
DP_OP_454J221_123_2743_n119) );
AOI22X1TS U3666 ( .A0(n2871), .A1(n2870), .B0(n2869), .B1(n2868), .Y(n2882)
);
OAI22X1TS U3667 ( .A0(n2883), .A1(n2872), .B0(n2881), .B1(n2882), .Y(n2879)
);
AOI22X1TS U3668 ( .A0(n2876), .A1(n2875), .B0(n2874), .B1(n2873), .Y(n2886)
);
OAI22X1TS U3669 ( .A0(n2887), .A1(n2877), .B0(n2885), .B1(n2886), .Y(n2878)
);
CMPR32X2TS U3670 ( .A(n2879), .B(n2889), .C(n2878), .CO(
DP_OP_454J221_123_2743_n83), .S(DP_OP_454J221_123_2743_n84) );
OAI22X1TS U3671 ( .A0(n2883), .A1(n2882), .B0(n2881), .B1(n2880), .Y(n2890)
);
OAI22X1TS U3672 ( .A0(n2887), .A1(n2886), .B0(n2885), .B1(n2884), .Y(n2888)
);
CMPR32X2TS U3673 ( .A(n2890), .B(n2889), .C(n2888), .CO(
DP_OP_454J221_123_2743_n93), .S(DP_OP_454J221_123_2743_n94) );
INVX2TS U3674 ( .A(FPSENCOS_cont_iter_out[2]), .Y(intadd_501_B_1_) );
NOR2XLTS U3675 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .Y(n2891) );
NAND3BX1TS U3676 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n2891),
.C(n2971), .Y(n2896) );
NOR2X2TS U3677 ( .A(n4609), .B(n2228), .Y(n4059) );
NOR2X2TS U3678 ( .A(n2253), .B(n4083), .Y(n3470) );
OAI32X1TS U3679 ( .A0(n3470), .A1(n2253), .A2(intadd_501_B_1_), .B0(n4559),
.B1(n3470), .Y(n2138) );
NOR4X1TS U3680 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n2894) );
NOR4X1TS U3681 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n2893) );
NOR4X1TS U3682 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n2892) );
NAND3XLTS U3683 ( .A(n2894), .B(n2893), .C(n2892), .Y(n2895) );
INVX2TS U3684 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(n4215) );
NAND4BXLTS U3685 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(n3370), .D(n4617), .Y(
n2897) );
BUFX3TS U3686 ( .A(n2898), .Y(n4124) );
BUFX4TS U3687 ( .A(n4124), .Y(n4131) );
NOR2X1TS U3688 ( .A(FPSENCOS_cont_iter_out[3]), .B(intadd_501_B_1_), .Y(
n2961) );
NAND2X1TS U3689 ( .A(n4760), .B(n2961), .Y(n2900) );
NAND2X1TS U3690 ( .A(n4131), .B(intadd_501_B_1_), .Y(n2925) );
INVX2TS U3691 ( .A(n2925), .Y(n4079) );
INVX2TS U3692 ( .A(n4059), .Y(n3272) );
AOI22X1TS U3693 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n4122), .B0(n4079),
.B1(n3272), .Y(n2899) );
AOI22X1TS U3694 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n4122), .B0(n4085),
.B1(n4609), .Y(n2901) );
OAI21XLTS U3695 ( .A0(n4609), .A1(n2925), .B0(n2901), .Y(n2129) );
CLKBUFX2TS U3696 ( .A(n2898), .Y(n4118) );
INVX2TS U3697 ( .A(n4083), .Y(n4057) );
NOR2X2TS U3698 ( .A(n4057), .B(n4132), .Y(n4081) );
OAI31X4TS U3699 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(
FPSENCOS_cont_iter_out[2]), .A2(n2228), .B0(n4081), .Y(n3442) );
NOR3X1TS U3700 ( .A(FPSENCOS_cont_iter_out[1]), .B(n3442), .C(n2925), .Y(
n2965) );
AOI21X1TS U3701 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n4132), .B0(n2965),
.Y(n2902) );
AOI2BB2X2TS U3702 ( .B0(FPADDSUB_DmP_mant_SFG_SWR[22]), .B1(n4640), .A0N(
n4640), .A1N(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n2911) );
NAND2X1TS U3703 ( .A(FPADDSUB_DMP_SFG[19]), .B(n4561), .Y(n2906) );
AOI2BB2X2TS U3704 ( .B0(FPADDSUB_DMP_SFG[18]), .B1(n4621), .A0N(n4621),
.A1N(FPADDSUB_DMP_SFG[18]), .Y(n3875) );
AOI2BB2X2TS U3705 ( .B0(FPADDSUB_DMP_SFG[17]), .B1(n4607), .A0N(n4607),
.A1N(FPADDSUB_DMP_SFG[17]), .Y(n3867) );
AOI2BB2X2TS U3706 ( .B0(FPADDSUB_DMP_SFG[16]), .B1(n4606), .A0N(n4606),
.A1N(FPADDSUB_DMP_SFG[16]), .Y(n3855) );
AOI2BB2X2TS U3707 ( .B0(FPADDSUB_DMP_SFG[15]), .B1(n4605), .A0N(n4605),
.A1N(FPADDSUB_DMP_SFG[15]), .Y(n3847) );
AOI2BB2X2TS U3708 ( .B0(FPADDSUB_DMP_SFG[14]), .B1(n4603), .A0N(n4603),
.A1N(FPADDSUB_DMP_SFG[14]), .Y(n3833) );
NOR2X1TS U3709 ( .A(FPADDSUB_DMP_SFG[12]), .B(n4539), .Y(n2905) );
INVX2TS U3710 ( .A(n3524), .Y(n3522) );
AOI2BB2X2TS U3711 ( .B0(FPADDSUB_DmP_mant_SFG_SWR[9]), .B1(n4595), .A0N(
n4595), .A1N(FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n2980) );
NOR2X1TS U3712 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(n4589), .Y(n2903) );
AOI2BB2X2TS U3713 ( .B0(FPADDSUB_DmP_mant_SFG_SWR[3]), .B1(
FPADDSUB_DMP_SFG[1]), .A0N(FPADDSUB_DMP_SFG[1]), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n3058) );
NOR2X1TS U3714 ( .A(FPADDSUB_DMP_SFG[0]), .B(n4588), .Y(n4427) );
NAND2X1TS U3715 ( .A(FPADDSUB_DMP_SFG[0]), .B(n4588), .Y(n4428) );
NOR2X1TS U3716 ( .A(n3058), .B(n3057), .Y(n3056) );
AOI21X1TS U3717 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n4590), .B0(n3056),
.Y(n3065) );
NOR2X1TS U3718 ( .A(n3065), .B(n3064), .Y(n3063) );
NOR2X1TS U3719 ( .A(n3389), .B(n3388), .Y(n3387) );
AOI21X1TS U3720 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n4592), .B0(n3387),
.Y(n3463) );
NOR2X1TS U3721 ( .A(n3463), .B(n3462), .Y(n3461) );
AOI21X1TS U3722 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(n4593), .B0(n3461),
.Y(n2978) );
NAND2X1TS U3723 ( .A(n2980), .B(n2978), .Y(n2977) );
OAI21X1TS U3724 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n4595), .B0(n2977),
.Y(n3521) );
NOR2X1TS U3725 ( .A(n3522), .B(n3521), .Y(n3520) );
AOI21X1TS U3726 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(n4553), .B0(n3520),
.Y(n3588) );
INVX2TS U3727 ( .A(n3590), .Y(n3587) );
AOI21X1TS U3728 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n4554), .B0(n3586),
.Y(n3003) );
OAI21X1TS U3729 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(n4555), .B0(n3002),
.Y(n4440) );
AOI222X1TS U3730 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n4540), .B0(
FPADDSUB_DMP_SFG[13]), .B1(n4444), .C0(n4540), .C1(n4444), .Y(n3831)
);
NAND2X1TS U3731 ( .A(n3833), .B(n3831), .Y(n3830) );
OAI21X1TS U3732 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(n4603), .B0(n3830), .Y(
n3845) );
NAND2X1TS U3733 ( .A(n3847), .B(n3845), .Y(n3844) );
OAI21X1TS U3734 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n4605), .B0(n3844), .Y(
n3853) );
NAND2X1TS U3735 ( .A(n3855), .B(n3853), .Y(n3852) );
OAI21X1TS U3736 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(n4606), .B0(n3852), .Y(
n3865) );
NAND2X1TS U3737 ( .A(n3867), .B(n3865), .Y(n3864) );
OAI21X1TS U3738 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(n4607), .B0(n3864), .Y(
n3873) );
NAND2X1TS U3739 ( .A(n3875), .B(n3873), .Y(n3872) );
AOI22X1TS U3740 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n4630), .B0(n2906),
.B1(n3880), .Y(n2908) );
INVX2TS U3741 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n4445) );
NOR2XLTS U3742 ( .A(n4585), .B(n4445), .Y(n2907) );
BUFX3TS U3743 ( .A(n2907), .Y(n4455) );
NAND2X1TS U3744 ( .A(n2911), .B(n2908), .Y(n4353) );
INVX4TS U3745 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n4424) );
NAND2X1TS U3746 ( .A(n4540), .B(n4604), .Y(n4447) );
AOI22X1TS U3747 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(
FPADDSUB_DMP_SFG[11]), .B0(n4602), .B1(n2298), .Y(n4441) );
INVX2TS U3748 ( .A(n3462), .Y(n3465) );
INVX2TS U3749 ( .A(n3388), .Y(n3391) );
NAND2X1TS U3750 ( .A(n4552), .B(n4594), .Y(n4432) );
INVX2TS U3751 ( .A(n3064), .Y(n3067) );
AOI21X1TS U3752 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(FPADDSUB_DmP_mant_SFG_SWR[3]), .B0(n3062), .Y(n3068) );
AOI21X1TS U3753 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(FPADDSUB_DmP_mant_SFG_SWR[4]), .B0(n3066), .Y(n3100) );
AOI22X1TS U3754 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(FPADDSUB_DMP_SFG[4]), .B0(n4432), .B1(n4433), .Y(n3392) );
AOI21X1TS U3755 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(FPADDSUB_DmP_mant_SFG_SWR[7]), .B0(n3390), .Y(n3466) );
AOI21X1TS U3756 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(FPADDSUB_DmP_mant_SFG_SWR[8]), .B0(n3464), .Y(n2981) );
AOI21X1TS U3757 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(FPADDSUB_DmP_mant_SFG_SWR[9]), .B0(n2979), .Y(n3525) );
AOI21X1TS U3758 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[10]), .B0(n3523), .Y(n3591) );
AOI21X1TS U3759 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[11]), .B0(n3589), .Y(n3006) );
AOI21X1TS U3760 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(n3004), .Y(n4439) );
INVX2TS U3761 ( .A(n4439), .Y(n2909) );
AOI22X1TS U3762 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(
FPADDSUB_DMP_SFG[11]), .B0(n4441), .B1(n2909), .Y(n3753) );
AOI22X1TS U3763 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(
FPADDSUB_DMP_SFG[13]), .B0(n4447), .B1(n4446), .Y(n3834) );
AOI21X1TS U3764 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(n3832), .Y(n3848) );
AOI21X1TS U3765 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[17]), .B0(n3846), .Y(n3856) );
AOI21X1TS U3766 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .B0(n3854), .Y(n3868) );
AOI21X1TS U3767 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[19]), .B0(n3866), .Y(n3876) );
AOI21X1TS U3768 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[20]), .B0(n3874), .Y(n3882) );
AOI21X1TS U3769 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[21]), .B0(n3881), .Y(n2912) );
BUFX4TS U3770 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n4468) );
AOI211X1TS U3771 ( .A0(n2912), .A1(n2911), .B0(n4352), .C0(n2910), .Y(n2913)
);
AOI21X1TS U3772 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[22]), .A1(n4424), .B0(n2913),
.Y(n2914) );
NAND2X1TS U3773 ( .A(n2915), .B(n2914), .Y(n1317) );
NAND3X1TS U3774 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n2916),
.C(n2971), .Y(n4062) );
INVX2TS U3775 ( .A(FPSENCOS_cont_var_out[0]), .Y(n3986) );
INVX2TS U3776 ( .A(n3986), .Y(n4200) );
BUFX4TS U3777 ( .A(n4093), .Y(n4195) );
NAND2X1TS U3778 ( .A(n4624), .B(n4300), .Y(n3989) );
AOI21X1TS U3779 ( .A0(n3519), .A1(n3989), .B0(n4614), .Y(n2920) );
INVX2TS U3780 ( .A(n3989), .Y(n2917) );
NOR2XLTS U3781 ( .A(FPMULT_P_Sgf[46]), .B(n4321), .Y(n2923) );
NOR2XLTS U3782 ( .A(FPMULT_FSM_selector_C), .B(n3141), .Y(n2919) );
BUFX4TS U3783 ( .A(n2919), .Y(n3125) );
CLKBUFX3TS U3784 ( .A(n2920), .Y(n3092) );
NAND2X1TS U3785 ( .A(n3092), .B(FPMULT_FSM_selector_C), .Y(n2921) );
NOR2X2TS U3786 ( .A(FPSENCOS_cont_iter_out[1]), .B(n4132), .Y(n3361) );
AOI22X1TS U3787 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n4122), .B0(n3361),
.B1(n2963), .Y(n2924) );
OAI21XLTS U3788 ( .A0(n3442), .A1(n4609), .B0(n2924), .Y(n2128) );
NOR2X1TS U3789 ( .A(n4559), .B(n2925), .Y(n3363) );
AOI21X1TS U3790 ( .A0(FPSENCOS_d_ff3_LUT_out[12]), .A1(n4132), .B0(n3363),
.Y(n2926) );
OAI21XLTS U3791 ( .A0(n3442), .A1(n4609), .B0(n2926), .Y(n2122) );
NAND3X1TS U3792 ( .A(n3482), .B(n4610), .C(n4557), .Y(n1480) );
BUFX3TS U3793 ( .A(n4827), .Y(n4823) );
OR2X1TS U3794 ( .A(n4055), .B(rst), .Y(n2927) );
INVX4TS U3795 ( .A(n2927), .Y(n3047) );
BUFX3TS U3796 ( .A(n3047), .Y(n2931) );
BUFX3TS U3797 ( .A(n3047), .Y(n4767) );
BUFX3TS U3798 ( .A(n4827), .Y(n4826) );
BUFX3TS U3799 ( .A(n2929), .Y(n4815) );
BUFX3TS U3800 ( .A(n4819), .Y(n4818) );
BUFX3TS U3801 ( .A(n2929), .Y(n4811) );
BUFX3TS U3802 ( .A(n4810), .Y(n4808) );
BUFX3TS U3803 ( .A(n2930), .Y(n4799) );
BUFX3TS U3804 ( .A(n4812), .Y(n4804) );
BUFX3TS U3805 ( .A(n2930), .Y(n4801) );
BUFX3TS U3806 ( .A(n4827), .Y(n4825) );
BUFX3TS U3807 ( .A(n4815), .Y(n4807) );
BUFX3TS U3808 ( .A(n2929), .Y(n4813) );
BUFX3TS U3809 ( .A(n4827), .Y(n4824) );
BUFX3TS U3810 ( .A(n3047), .Y(n4765) );
BUFX3TS U3811 ( .A(n2929), .Y(n4802) );
BUFX3TS U3812 ( .A(n4795), .Y(n4803) );
BUFX4TS U3813 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4475) );
INVX4TS U3814 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n2934) );
AO22XLTS U3815 ( .A0(n4475), .A1(FPADDSUB_DmP_EXP_EWSW[7]), .B0(n2934), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1304) );
AO22XLTS U3816 ( .A0(n4359), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n2934), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1288) );
AO22XLTS U3817 ( .A0(n4475), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n2934), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1354) );
AO22XLTS U3818 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[2]), .B0(n2934), .B1(FPADDSUB_DMP_SHT1_EWSW[2]),
.Y(n1309) );
AO22XLTS U3819 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[0]), .B0(n2934), .B1(FPADDSUB_DMP_SHT1_EWSW[0]),
.Y(n1295) );
AO22XLTS U3820 ( .A0(n4475), .A1(FPADDSUB_DmP_EXP_EWSW[2]), .B0(n2934), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1311) );
BUFX3TS U3821 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4477) );
AO22XLTS U3822 ( .A0(n4477), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n2934),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1208) );
AO22XLTS U3823 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[13]), .B0(n2934), .B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1244) );
AO22XLTS U3824 ( .A0(n4475), .A1(FPADDSUB_DmP_EXP_EWSW[5]), .B0(n2934), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1276) );
BUFX3TS U3825 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4359) );
AO22XLTS U3826 ( .A0(n4359), .A1(FPADDSUB_DMP_EXP_EWSW[23]), .B0(n2934),
.B1(FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1457) );
AO22XLTS U3827 ( .A0(n4475), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n2934), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1327) );
AO22XLTS U3828 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[3]), .B0(n2934), .B1(FPADDSUB_DMP_SHT1_EWSW[3]),
.Y(n1325) );
AO22XLTS U3829 ( .A0(n4359), .A1(FPADDSUB_DMP_EXP_EWSW[25]), .B0(n2934),
.B1(FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1447) );
AO22XLTS U3830 ( .A0(n4475), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n2934), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1297) );
AO22XLTS U3831 ( .A0(n4475), .A1(FPADDSUB_DMP_EXP_EWSW[12]), .B0(n2934),
.B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1268) );
AO22XLTS U3832 ( .A0(n4359), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n2934), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1302) );
INVX2TS U3833 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n3578) );
AO22XLTS U3834 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n3578), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n1357) );
INVX4TS U3835 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4421) );
AO22XLTS U3836 ( .A0(n4477), .A1(intadd_500_SUM_0_), .B0(n4421), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n1476) );
CLKXOR2X2TS U3837 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(
n4420) );
BUFX4TS U3838 ( .A(n4549), .Y(n3261) );
AOI31XLTS U3839 ( .A0(FPADDSUB_intDX_EWSW[31]), .A1(
FPADDSUB_Shift_reg_FLAGS_7_6), .A2(n4420), .B0(n2932), .Y(n1355) );
AO22XLTS U3840 ( .A0(n4475), .A1(intadd_500_SUM_1_), .B0(n2934), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1477) );
INVX4TS U3841 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4478) );
AO22XLTS U3842 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(intadd_500_SUM_2_),
.B0(n4478), .B1(FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1478) );
XNOR2X1TS U3843 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(
FPADDSUB_DmP_EXP_EWSW[27]), .Y(n2933) );
XOR2XLTS U3844 ( .A(intadd_500_n1), .B(n2933), .Y(n2935) );
AO22XLTS U3845 ( .A0(n4477), .A1(n2935), .B0(n2934), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1474) );
NAND2X1TS U3846 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(n4616),
.Y(n4065) );
NAND2X1TS U3847 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B(n4065),
.Y(n3993) );
OAI21X1TS U3848 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n3993), .Y(n3676) );
OAI32X4TS U3849 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n3993), .B1(n4699),
.Y(n4072) );
NOR2BX1TS U3850 ( .AN(n3676), .B(n4072), .Y(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
AO21XLTS U3851 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_6), .A1(n4072), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .Y(n2148) );
INVX4TS U3852 ( .A(n4342), .Y(n4343) );
BUFX4TS U3853 ( .A(n4342), .Y(n3089) );
INVX2TS U3854 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[12]), .Y(n3939) );
NOR2X1TS U3855 ( .A(intadd_499_SUM_0_), .B(n3939), .Y(n2947) );
INVX2TS U3856 ( .A(intadd_499_SUM_1_), .Y(n2946) );
AO22XLTS U3857 ( .A0(n4343), .A1(FPMULT_P_Sgf[13]), .B0(n3089), .B1(n2936),
.Y(n1542) );
AOI21X1TS U3858 ( .A0(intadd_499_SUM_0_), .A1(n3939), .B0(n2947), .Y(n2937)
);
AO22XLTS U3859 ( .A0(n4333), .A1(FPMULT_P_Sgf[12]), .B0(n3089), .B1(n2937),
.Y(n1541) );
AO22XLTS U3860 ( .A0(n3089), .A1(FPMULT_Sgf_operation_Result[4]), .B0(n4343),
.B1(FPMULT_P_Sgf[4]), .Y(n1533) );
AO22XLTS U3861 ( .A0(n4321), .A1(FPMULT_Sgf_operation_Result[10]), .B0(n4333), .B1(FPMULT_P_Sgf[10]), .Y(n1539) );
AO22XLTS U3862 ( .A0(n3089), .A1(FPMULT_Sgf_operation_Result[9]), .B0(n4343),
.B1(FPMULT_P_Sgf[9]), .Y(n1538) );
AO22XLTS U3863 ( .A0(n4321), .A1(FPMULT_Sgf_operation_Result[7]), .B0(n4333),
.B1(FPMULT_P_Sgf[7]), .Y(n1536) );
AO22XLTS U3864 ( .A0(n3089), .A1(FPMULT_Sgf_operation_Result[3]), .B0(n4343),
.B1(FPMULT_P_Sgf[3]), .Y(n1532) );
AO22XLTS U3865 ( .A0(n3089), .A1(FPMULT_Sgf_operation_Result[6]), .B0(n4333),
.B1(FPMULT_P_Sgf[6]), .Y(n1535) );
AO22XLTS U3866 ( .A0(n4321), .A1(FPMULT_Sgf_operation_Result[5]), .B0(n4343),
.B1(FPMULT_P_Sgf[5]), .Y(n1534) );
AO22XLTS U3867 ( .A0(n3089), .A1(FPMULT_Sgf_operation_Result[2]), .B0(n4333),
.B1(FPMULT_P_Sgf[2]), .Y(n1531) );
NAND2X1TS U3868 ( .A(n4055), .B(n4760), .Y(n4075) );
OA21XLTS U3869 ( .A0(n4055), .A1(n4760), .B0(n4075), .Y(n2141) );
NAND2X1TS U3870 ( .A(n4125), .B(n4702), .Y(n4128) );
OAI21XLTS U3871 ( .A0(n4125), .A1(n4702), .B0(n4128), .Y(n2938) );
AO22XLTS U3872 ( .A0(n4124), .A1(n2938), .B0(n4119), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1848) );
INVX4TS U3873 ( .A(n4124), .Y(n4197) );
AO22XLTS U3874 ( .A0(n4118), .A1(intadd_502_SUM_2_), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[26]), .Y(n1948) );
AO22XLTS U3875 ( .A0(n4131), .A1(intadd_502_SUM_1_), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[25]), .Y(n1949) );
AO22XLTS U3876 ( .A0(n4131), .A1(intadd_502_SUM_0_), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[24]), .Y(n1950) );
XNOR2X1TS U3877 ( .A(DP_OP_26J221_124_9022_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n3284) );
INVX2TS U3878 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n4024) );
INVX2TS U3879 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n2939) );
NAND4BXLTS U3880 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n2940), .C(n4024),
.D(n2939), .Y(n2941) );
NAND2BXLTS U3881 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(n2942), .Y(n2943)
);
NAND2X2TS U3882 ( .A(n3280), .B(n4829), .Y(n4025) );
OA22X1TS U3883 ( .A0(n4025), .A1(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B0(n4829),
.B1(result_add_subt[29]), .Y(n1467) );
OA22X1TS U3884 ( .A0(n4025), .A1(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B0(n4829),
.B1(result_add_subt[27]), .Y(n1469) );
OA22X1TS U3885 ( .A0(n4025), .A1(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B0(n4829),
.B1(result_add_subt[25]), .Y(n1471) );
OA22X1TS U3886 ( .A0(n4025), .A1(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B0(n4829),
.B1(result_add_subt[23]), .Y(n1473) );
OA22X1TS U3887 ( .A0(n4025), .A1(FPADDSUB_exp_rslt_NRM2_EW1[5]), .B0(n4829),
.B1(result_add_subt[28]), .Y(n1468) );
BUFX4TS U3888 ( .A(n4124), .Y(n4133) );
AOI2BB2XLTS U3889 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n4127), .A0N(n4127),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n2945) );
AO22XLTS U3890 ( .A0(n4133), .A1(n2945), .B0(n4132), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1846) );
INVX4TS U3891 ( .A(n4342), .Y(n4333) );
NAND2X1TS U3892 ( .A(intadd_499_SUM_3_), .B(n2949), .Y(n4334) );
OAI21X1TS U3893 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_right[15]), .A1(n4335),
.B0(n4334), .Y(n2950) );
XNOR2X1TS U3894 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[17]), .B(n2952), .Y(
n2953) );
AO22XLTS U3895 ( .A0(n4333), .A1(FPMULT_P_Sgf[17]), .B0(n4321), .B1(n2953),
.Y(n1546) );
INVX2TS U3896 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .Y(n3240) );
NAND2X1TS U3897 ( .A(n4609), .B(n2228), .Y(n3362) );
CLKBUFX2TS U3898 ( .A(n2955), .Y(n4116) );
AO22XLTS U3899 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[31]), .B1(n4120), .Y(n1845) );
AO22XLTS U3900 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[28]), .B1(n4120), .Y(n1856) );
XNOR2X1TS U3901 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[18]), .B(n2959), .Y(
n2960) );
AO22XLTS U3902 ( .A0(n4343), .A1(FPMULT_P_Sgf[18]), .B0(n4321), .B1(n2960),
.Y(n1547) );
NAND2X1TS U3903 ( .A(FPSENCOS_cont_iter_out[1]), .B(n4081), .Y(n3423) );
OAI221XLTS U3904 ( .A0(n4131), .A1(n4754), .B0(n4132), .B1(n4080), .C0(n3423), .Y(n2118) );
AOI22X1TS U3905 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n4122), .B0(n2961),
.B1(n3361), .Y(n2962) );
NAND2X1TS U3906 ( .A(n4059), .B(n4079), .Y(n3364) );
NAND2X1TS U3907 ( .A(n2962), .B(n3364), .Y(n2131) );
NAND2BXLTS U3908 ( .AN(n2965), .B(n2964), .Y(n2123) );
XNOR2X1TS U3909 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[19]), .B(n2969), .Y(
n2970) );
AO22XLTS U3910 ( .A0(n4333), .A1(FPMULT_P_Sgf[19]), .B0(n4321), .B1(n2970),
.Y(n1548) );
INVX2TS U3911 ( .A(operation[1]), .Y(n3677) );
INVX2TS U3912 ( .A(begin_operation), .Y(n3675) );
NOR2X1TS U3913 ( .A(n3677), .B(n3675), .Y(n4052) );
NAND3BX1TS U3914 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(n3406), .Y(n4051) );
NOR2BX1TS U3915 ( .AN(n4052), .B(n4051), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
BUFX3TS U3916 ( .A(n4342), .Y(n4344) );
XNOR2X1TS U3917 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[20]), .B(n2975), .Y(
n2976) );
AO22XLTS U3918 ( .A0(n4333), .A1(FPMULT_P_Sgf[20]), .B0(n4344), .B1(n2976),
.Y(n1549) );
OAI211XLTS U3919 ( .A0(n2980), .A1(n2978), .B0(n4455), .C0(n2977), .Y(n2984)
);
AOI211XLTS U3920 ( .A0(n2981), .A1(n2980), .B0(n2979), .C0(n2910), .Y(n2982)
);
AOI21X1TS U3921 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n4424), .B0(n2244),
.Y(n2983) );
NAND2X1TS U3922 ( .A(n2984), .B(n2983), .Y(n1340) );
NOR2XLTS U3923 ( .A(n2985), .B(FPMULT_FS_Module_state_reg[1]), .Y(n2986) );
BUFX3TS U3924 ( .A(n2986), .Y(n4759) );
INVX2TS U3925 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[21]), .Y(n3975) );
XOR2XLTS U3926 ( .A(intadd_499_SUM_10_), .B(n2991), .Y(n2989) );
XNOR2X1TS U3927 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[22]), .B(n2989), .Y(
n2990) );
AO22XLTS U3928 ( .A0(n4333), .A1(FPMULT_P_Sgf[22]), .B0(n3089), .B1(n2990),
.Y(n1551) );
INVX2TS U3929 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[22]), .Y(n3979) );
AOI222X1TS U3930 ( .A0(intadd_499_SUM_10_), .A1(n3979), .B0(
intadd_499_SUM_10_), .B1(n2992), .C0(n3979), .C1(n2992), .Y(n2995) );
INVX2TS U3931 ( .A(intadd_499_SUM_11_), .Y(n2994) );
AO22XLTS U3932 ( .A0(n4333), .A1(FPMULT_P_Sgf[23]), .B0(n4344), .B1(n2993),
.Y(n1552) );
CMPR32X2TS U3933 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[23]), .B(n2995),
.C(n2994), .CO(n2998), .S(n2993) );
XOR2XLTS U3934 ( .A(intadd_499_SUM_12_), .B(n2998), .Y(n2996) );
XNOR2X1TS U3935 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .B(n2996), .Y(
n2997) );
AO22XLTS U3936 ( .A0(n4343), .A1(FPMULT_P_Sgf[24]), .B0(n3089), .B1(n2997),
.Y(n1553) );
INVX2TS U3937 ( .A(intadd_499_SUM_13_), .Y(n3011) );
AO22XLTS U3938 ( .A0(n4343), .A1(FPMULT_P_Sgf[25]), .B0(n4342), .B1(n3001),
.Y(n1554) );
OAI211XLTS U3939 ( .A0(n3005), .A1(n3003), .B0(n4455), .C0(n3002), .Y(n3009)
);
AOI21X1TS U3940 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n4585), .B0(n3007),
.Y(n3008) );
NAND2X1TS U3941 ( .A(n3009), .B(n3008), .Y(n1337) );
CMPR32X2TS U3942 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .B(n3011), .C(
n3010), .CO(n3012), .S(n3001) );
XNOR2X1TS U3943 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .B(n3013), .Y(
n3014) );
AO22XLTS U3944 ( .A0(n4343), .A1(FPMULT_P_Sgf[26]), .B0(n3089), .B1(n3014),
.Y(n1555) );
INVX2TS U3945 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(n4318) );
INVX2TS U3946 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(n3906) );
XOR2X1TS U3947 ( .A(intadd_499_SUM_17_), .B(n3020), .Y(n3018) );
XNOR2X1TS U3948 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .B(n3018), .Y(
n3019) );
INVX2TS U3949 ( .A(intadd_499_SUM_18_), .Y(n3024) );
INVX2TS U3950 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(n3910) );
INVX2TS U3951 ( .A(intadd_499_SUM_20_), .Y(n3029) );
CMPR32X2TS U3952 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .B(n3024), .C(
n3023), .CO(n3840), .S(n3022) );
NOR2BX2TS U3953 ( .AN(intadd_499_SUM_19_), .B(n3840), .Y(n3026) );
INVX2TS U3954 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .Y(n3918) );
INVX2TS U3955 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .Y(n3926) );
INVX2TS U3956 ( .A(intadd_499_SUM_22_), .Y(n3033) );
INVX4TS U3957 ( .A(n4344), .Y(n4345) );
CMPR32X2TS U3958 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .B(n3034), .C(
n3033), .CO(n3037), .S(n3032) );
INVX2TS U3959 ( .A(intadd_499_SUM_23_), .Y(n3036) );
INVX2TS U3960 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[14]), .Y(n3946) );
INVX2TS U3961 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .Y(n3938) );
CMPR32X2TS U3962 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .B(n3037), .C(
n3036), .CO(n3038), .S(n3035) );
CLKXOR2X2TS U3963 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[25]), .B(
intadd_499_n1), .Y(n3893) );
AOI21X1TS U3964 ( .A0(n3946), .A1(n3039), .B0(n4316), .Y(n3040) );
INVX2TS U3965 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[16]), .Y(n3954) );
AOI21X1TS U3966 ( .A0(n4315), .A1(n3954), .B0(n4313), .Y(n3041) );
INVX2TS U3967 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[18]), .Y(n3962) );
AOI21X1TS U3968 ( .A0(n4312), .A1(n3962), .B0(n4310), .Y(n3042) );
INVX2TS U3969 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[20]), .Y(n3970) );
NOR2X2TS U3970 ( .A(n4309), .B(n3970), .Y(n4307) );
AOI21X1TS U3971 ( .A0(n4309), .A1(n3970), .B0(n4307), .Y(n3043) );
INVX2TS U3972 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[22]), .Y(n3978) );
AOI21X1TS U3973 ( .A0(n4306), .A1(n3978), .B0(n3045), .Y(n3044) );
INVX2TS U3974 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[23]), .Y(n3983) );
XNOR2X1TS U3975 ( .A(n3045), .B(n3983), .Y(n3046) );
BUFX3TS U3976 ( .A(n3047), .Y(n4772) );
BUFX3TS U3977 ( .A(n3047), .Y(n4777) );
BUFX3TS U3978 ( .A(n3047), .Y(n4771) );
BUFX3TS U3979 ( .A(n3047), .Y(n4775) );
BUFX3TS U3980 ( .A(n3047), .Y(n4784) );
BUFX3TS U3981 ( .A(n3047), .Y(n4764) );
BUFX3TS U3982 ( .A(n3047), .Y(n4786) );
BUFX3TS U3983 ( .A(n3047), .Y(n4779) );
BUFX3TS U3984 ( .A(n3047), .Y(n4769) );
BUFX3TS U3985 ( .A(n3047), .Y(n4780) );
BUFX3TS U3986 ( .A(n3047), .Y(n4763) );
BUFX3TS U3987 ( .A(n3047), .Y(n4781) );
NAND2X1TS U3988 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n4698), .Y(intadd_500_CI) );
OR2X1TS U3989 ( .A(n3519), .B(n3987), .Y(n4216) );
NOR2BX1TS U3990 ( .AN(FPMULT_P_Sgf[47]), .B(n4216), .Y(n3053) );
INVX2TS U3991 ( .A(n4300), .Y(n3517) );
OR3X1TS U3992 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n4624), .C(n3517), .Y(
n3052) );
NAND2X1TS U3993 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .Y(n3483) );
INVX2TS U3994 ( .A(n3483), .Y(n3048) );
CLKAND2X2TS U3995 ( .A(n4557), .B(n3048), .Y(n3049) );
NAND2X2TS U3996 ( .A(n3049), .B(n4610), .Y(n4247) );
OAI211XLTS U3997 ( .A0(n3053), .A1(n4637), .B0(n4299), .C0(n4247), .Y(n1623)
);
NOR2XLTS U3998 ( .A(n4669), .B(n3578), .Y(n3050) );
BUFX3TS U3999 ( .A(n3050), .Y(n3597) );
OAI21XLTS U4000 ( .A0(n4556), .A1(FPADDSUB_Shift_reg_FLAGS_7[1]), .B0(n4186),
.Y(n1350) );
BUFX3TS U4001 ( .A(n4725), .Y(n4451) );
INVX4TS U4002 ( .A(n4451), .Y(n4480) );
OR2X2TS U4003 ( .A(n4480), .B(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n3554) );
OAI21XLTS U4004 ( .A0(n3554), .A1(n4522), .B0(n3599), .Y(n2078) );
OAI21XLTS U4005 ( .A0(n3554), .A1(n2231), .B0(n4186), .Y(n2079) );
INVX2TS U4006 ( .A(n4247), .Y(n3055) );
INVX2TS U4007 ( .A(n3053), .Y(n3054) );
OAI31X1TS U4008 ( .A0(n4284), .A1(n3055), .A2(n4641), .B0(n3054), .Y(n1622)
);
AOI21X1TS U4009 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(FPADDSUB_DMP_SFG[0]), .B0(n3058), .Y(n3061) );
AO21XLTS U4010 ( .A0(n3058), .A1(n3057), .B0(n3056), .Y(n3059) );
AOI22X1TS U4011 ( .A0(n4455), .A1(n3059), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.B1(n4585), .Y(n3060) );
OAI31X1TS U4012 ( .A0(n3062), .A1(n3061), .A2(n2910), .B0(n3060), .Y(n1346)
);
AOI21X1TS U4013 ( .A0(n3065), .A1(n3064), .B0(n3063), .Y(n3071) );
INVX2TS U4014 ( .A(n4455), .Y(n3887) );
AOI211XLTS U4015 ( .A0(n3068), .A1(n3067), .B0(n3066), .C0(n2910), .Y(n3069)
);
AOI21X1TS U4016 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[4]), .A1(n4424), .B0(n2245),
.Y(n3070) );
NAND2X1TS U4017 ( .A(n4200), .B(FPSENCOS_cont_var_out[1]), .Y(n4060) );
INVX2TS U4018 ( .A(n4060), .Y(n3073) );
NOR2XLTS U4019 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n3072) );
OAI21XLTS U4020 ( .A0(n3073), .A1(n4061), .B0(n4132), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
INVX2TS U4021 ( .A(FPMULT_Add_result[7]), .Y(n3133) );
OR3X1TS U4022 ( .A(FPMULT_Sgf_normalized_result[2]), .B(
FPMULT_Sgf_normalized_result[1]), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n4254) );
NAND2X1TS U4023 ( .A(FPMULT_Sgf_normalized_result[3]), .B(n4254), .Y(n4256)
);
NAND2X1TS U4024 ( .A(n4598), .B(n4256), .Y(n4259) );
NAND2X1TS U4025 ( .A(FPMULT_Sgf_normalized_result[5]), .B(n4259), .Y(n4262)
);
NAND2X1TS U4026 ( .A(FPMULT_Sgf_normalized_result[7]), .B(n4261), .Y(n4264)
);
OAI211XLTS U4027 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4261), .B0(
n4296), .C0(n4264), .Y(n3074) );
OAI21XLTS U4028 ( .A0(n3133), .A1(n4284), .B0(n3074), .Y(n1613) );
NAND3XLTS U4029 ( .A(n3092), .B(FPMULT_FSM_selector_C), .C(n4321), .Y(n3075)
);
CLKBUFX3TS U4030 ( .A(n3075), .Y(n3146) );
AOI22X1TS U4031 ( .A0(n3076), .A1(FPMULT_Add_result[1]), .B0(n3143), .B1(
FPMULT_Add_result[0]), .Y(n3078) );
OAI221XLTS U4032 ( .A0(n4345), .A1(FPMULT_P_Sgf[24]), .B0(n4321), .B1(
FPMULT_P_Sgf[23]), .C0(n3125), .Y(n3077) );
OAI211XLTS U4033 ( .A0(n3092), .A1(n4709), .B0(n3078), .C0(n3077), .Y(n1505)
);
INVX1TS U4034 ( .A(FPMULT_Sgf_normalized_result[12]), .Y(n4276) );
AOI22X1TS U4035 ( .A0(FPMULT_Add_result[13]), .A1(n3076), .B0(
FPMULT_Add_result[12]), .B1(n3143), .Y(n3080) );
OAI221XLTS U4036 ( .A0(n4345), .A1(FPMULT_P_Sgf[36]), .B0(n3089), .B1(
FPMULT_P_Sgf[35]), .C0(n3125), .Y(n3079) );
OAI211XLTS U4037 ( .A0(n3092), .A1(n4276), .B0(n3080), .C0(n3079), .Y(n1517)
);
INVX1TS U4038 ( .A(FPMULT_Sgf_normalized_result[18]), .Y(n4286) );
AOI22X1TS U4039 ( .A0(FPMULT_Add_result[19]), .A1(n3076), .B0(
FPMULT_Add_result[18]), .B1(n3143), .Y(n3082) );
OAI221XLTS U4040 ( .A0(n4345), .A1(FPMULT_P_Sgf[42]), .B0(n3089), .B1(
FPMULT_P_Sgf[41]), .C0(n3125), .Y(n3081) );
OAI211XLTS U4041 ( .A0(n3092), .A1(n4286), .B0(n3082), .C0(n3081), .Y(n1523)
);
INVX1TS U4042 ( .A(FPMULT_Sgf_normalized_result[10]), .Y(n4270) );
AOI22X1TS U4043 ( .A0(FPMULT_Add_result[11]), .A1(n3076), .B0(
FPMULT_Add_result[10]), .B1(n3143), .Y(n3084) );
OAI221XLTS U4044 ( .A0(n4345), .A1(FPMULT_P_Sgf[34]), .B0(n3089), .B1(
FPMULT_P_Sgf[33]), .C0(n3125), .Y(n3083) );
OAI211XLTS U4045 ( .A0(n3092), .A1(n4270), .B0(n3084), .C0(n3083), .Y(n1515)
);
INVX1TS U4046 ( .A(FPMULT_Sgf_normalized_result[8]), .Y(n4265) );
AOI22X1TS U4047 ( .A0(FPMULT_Add_result[9]), .A1(n3076), .B0(
FPMULT_Add_result[8]), .B1(n3143), .Y(n3086) );
OAI221XLTS U4048 ( .A0(n4345), .A1(FPMULT_P_Sgf[32]), .B0(n4321), .B1(
FPMULT_P_Sgf[31]), .C0(n3125), .Y(n3085) );
OAI211XLTS U4049 ( .A0(n3092), .A1(n4265), .B0(n3086), .C0(n3085), .Y(n1513)
);
AOI22X1TS U4050 ( .A0(FPMULT_Add_result[16]), .A1(n3076), .B0(
FPMULT_Add_result[15]), .B1(n3143), .Y(n3088) );
OAI221XLTS U4051 ( .A0(n4345), .A1(FPMULT_P_Sgf[39]), .B0(n3089), .B1(
FPMULT_P_Sgf[38]), .C0(n3125), .Y(n3087) );
OAI211XLTS U4052 ( .A0(n3092), .A1(n4711), .B0(n3088), .C0(n3087), .Y(n1520)
);
AOI22X1TS U4053 ( .A0(FPMULT_Add_result[10]), .A1(n3076), .B0(
FPMULT_Add_result[9]), .B1(n3143), .Y(n3091) );
OAI221XLTS U4054 ( .A0(n4345), .A1(FPMULT_P_Sgf[33]), .B0(n3089), .B1(
FPMULT_P_Sgf[32]), .C0(n3125), .Y(n3090) );
OAI211XLTS U4055 ( .A0(n3092), .A1(n4712), .B0(n3091), .C0(n3090), .Y(n1514)
);
NAND2X1TS U4056 ( .A(n4760), .B(n2232), .Y(intadd_502_CI) );
INVX2TS U4057 ( .A(FPMULT_Add_result[4]), .Y(n4257) );
INVX2TS U4058 ( .A(n3143), .Y(n3129) );
AOI22X1TS U4059 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n3141), .B0(
n3076), .B1(FPMULT_Add_result[5]), .Y(n3094) );
OAI221XLTS U4060 ( .A0(n4345), .A1(FPMULT_P_Sgf[28]), .B0(n4344), .B1(
FPMULT_P_Sgf[27]), .C0(n3125), .Y(n3093) );
OAI211XLTS U4061 ( .A0(n4257), .A1(n3129), .B0(n3094), .C0(n3093), .Y(n1509)
);
AOI22X1TS U4062 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n3141), .B0(
n3076), .B1(FPMULT_Add_result[3]), .Y(n3096) );
OAI221XLTS U4063 ( .A0(n4345), .A1(FPMULT_P_Sgf[26]), .B0(n4321), .B1(
FPMULT_P_Sgf[25]), .C0(n3125), .Y(n3095) );
OAI211XLTS U4064 ( .A0(n4252), .A1(n3129), .B0(n3096), .C0(n3095), .Y(n1507)
);
AOI22X1TS U4065 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n3141), .B0(
FPMULT_Add_result[8]), .B1(n3076), .Y(n3098) );
OAI221XLTS U4066 ( .A0(n4345), .A1(FPMULT_P_Sgf[31]), .B0(n4321), .B1(
FPMULT_P_Sgf[30]), .C0(n3125), .Y(n3097) );
OAI211XLTS U4067 ( .A0(n3129), .A1(n3133), .B0(n3098), .C0(n3097), .Y(n1512)
);
AOI211X1TS U4068 ( .A0(n3102), .A1(n3100), .B0(n3099), .C0(n2910), .Y(n3104)
);
AOI21X1TS U4069 ( .A0(n3103), .A1(n3102), .B0(n3887), .Y(n3101) );
OAI32X1TS U4070 ( .A0(n3104), .A1(n3103), .A2(n3102), .B0(n3101), .B1(n3104),
.Y(n3105) );
OAI21XLTS U4071 ( .A0(n4468), .A1(n4633), .B0(n3105), .Y(n1344) );
INVX4TS U4072 ( .A(n4344), .Y(n4011) );
NAND2X1TS U4073 ( .A(n4011), .B(FPMULT_P_Sgf[28]), .Y(n3828) );
INVX2TS U4074 ( .A(n3125), .Y(n3130) );
AOI2BB2XLTS U4075 ( .B0(FPMULT_Sgf_normalized_result[5]), .B1(n3141), .A0N(
n3828), .A1N(n3130), .Y(n3108) );
NOR2XLTS U4076 ( .A(n4011), .B(n3130), .Y(n3106) );
BUFX3TS U4077 ( .A(n3106), .Y(n3142) );
AOI22X1TS U4078 ( .A0(FPMULT_P_Sgf[29]), .A1(n3142), .B0(n3076), .B1(
FPMULT_Add_result[6]), .Y(n3107) );
OAI211XLTS U4079 ( .A0(n3129), .A1(n4723), .B0(n3108), .C0(n3107), .Y(n1510)
);
CLKAND2X2TS U4080 ( .A(FPMULT_P_Sgf[36]), .B(n4345), .Y(n3891) );
AOI22X1TS U4081 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n3141), .B0(
n3125), .B1(n3891), .Y(n3110) );
AOI22X1TS U4082 ( .A0(FPMULT_Add_result[14]), .A1(n3076), .B0(n3142), .B1(
FPMULT_P_Sgf[37]), .Y(n3109) );
OAI211XLTS U4083 ( .A0(n4718), .A1(n3129), .B0(n3110), .C0(n3109), .Y(n1518)
);
INVX2TS U4084 ( .A(FPMULT_Add_result[21]), .Y(n4295) );
CLKAND2X2TS U4085 ( .A(FPMULT_P_Sgf[43]), .B(n4011), .Y(n3111) );
AOI22X1TS U4086 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n3141), .B0(
n3111), .B1(n3125), .Y(n3113) );
AOI22X1TS U4087 ( .A0(FPMULT_Add_result[20]), .A1(n3143), .B0(
FPMULT_P_Sgf[44]), .B1(n3142), .Y(n3112) );
OAI211XLTS U4088 ( .A0(n4295), .A1(n3146), .B0(n3113), .C0(n3112), .Y(n1525)
);
CLKAND2X2TS U4089 ( .A(FPMULT_P_Sgf[42]), .B(n4011), .Y(n3114) );
AOI22X1TS U4090 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n3141), .B0(
n3114), .B1(n3125), .Y(n3116) );
AOI22X1TS U4091 ( .A0(FPMULT_Add_result[19]), .A1(n3143), .B0(
FPMULT_P_Sgf[43]), .B1(n3142), .Y(n3115) );
OAI211XLTS U4092 ( .A0(n4726), .A1(n3146), .B0(n3116), .C0(n3115), .Y(n1524)
);
CLKAND2X2TS U4093 ( .A(FPMULT_P_Sgf[45]), .B(n4011), .Y(n3117) );
AOI22X1TS U4094 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n3141), .B0(
n3117), .B1(n3125), .Y(n3119) );
AOI22X1TS U4095 ( .A0(FPMULT_Add_result[22]), .A1(n3143), .B0(
FPMULT_P_Sgf[46]), .B1(n3142), .Y(n3118) );
OAI211XLTS U4096 ( .A0(n4586), .A1(n3146), .B0(n3119), .C0(n3118), .Y(n1527)
);
CLKAND2X2TS U4097 ( .A(FPMULT_P_Sgf[39]), .B(n4011), .Y(n3120) );
AOI22X1TS U4098 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n3141), .B0(
n3120), .B1(n3125), .Y(n3122) );
AOI22X1TS U4099 ( .A0(FPMULT_Add_result[16]), .A1(n3143), .B0(
FPMULT_P_Sgf[40]), .B1(n3142), .Y(n3121) );
OAI211XLTS U4100 ( .A0(n4717), .A1(n3146), .B0(n3122), .C0(n3121), .Y(n1521)
);
NAND2X1TS U4101 ( .A(n4011), .B(FPMULT_P_Sgf[37]), .Y(n3896) );
AOI2BB2XLTS U4102 ( .B0(FPMULT_Sgf_normalized_result[14]), .B1(n3141), .A0N(
n3130), .A1N(n3896), .Y(n3124) );
AOI22X1TS U4103 ( .A0(FPMULT_Add_result[14]), .A1(n3143), .B0(
FPMULT_P_Sgf[38]), .B1(n3142), .Y(n3123) );
OAI211XLTS U4104 ( .A0(n4719), .A1(n3146), .B0(n3124), .C0(n3123), .Y(n1519)
);
CLKAND2X2TS U4105 ( .A(FPMULT_P_Sgf[44]), .B(n4011), .Y(n3126) );
AOI22X1TS U4106 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n3141), .B0(
n3126), .B1(n3125), .Y(n3128) );
AOI22X1TS U4107 ( .A0(FPMULT_Add_result[22]), .A1(n3076), .B0(
FPMULT_P_Sgf[45]), .B1(n3142), .Y(n3127) );
OAI211XLTS U4108 ( .A0(n4295), .A1(n3129), .B0(n3128), .C0(n3127), .Y(n1526)
);
AOI22X1TS U4109 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n3141), .B0(
n3142), .B1(FPMULT_P_Sgf[30]), .Y(n3132) );
NOR2X2TS U4110 ( .A(n4321), .B(n3130), .Y(n3140) );
AOI22X1TS U4111 ( .A0(FPMULT_P_Sgf[29]), .A1(n3140), .B0(n3143), .B1(
FPMULT_Add_result[6]), .Y(n3131) );
OAI211XLTS U4112 ( .A0(n3133), .A1(n3146), .B0(n3132), .C0(n3131), .Y(n1511)
);
AOI22X1TS U4113 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n3141), .B0(
n3142), .B1(FPMULT_P_Sgf[35]), .Y(n3135) );
AOI22X1TS U4114 ( .A0(FPMULT_Add_result[11]), .A1(n3143), .B0(n3140), .B1(
FPMULT_P_Sgf[34]), .Y(n3134) );
OAI211XLTS U4115 ( .A0(n4728), .A1(n3146), .B0(n3135), .C0(n3134), .Y(n1516)
);
AOI22X1TS U4116 ( .A0(FPMULT_Sgf_normalized_result[1]), .A1(n3141), .B0(
n3142), .B1(FPMULT_P_Sgf[25]), .Y(n3137) );
AOI22X1TS U4117 ( .A0(n3143), .A1(FPMULT_Add_result[1]), .B0(n3140), .B1(
FPMULT_P_Sgf[24]), .Y(n3136) );
OAI211XLTS U4118 ( .A0(n3146), .A1(n4252), .B0(n3137), .C0(n3136), .Y(n1506)
);
AOI22X1TS U4119 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n3141), .B0(
n3140), .B1(FPMULT_P_Sgf[26]), .Y(n3139) );
AOI22X1TS U4120 ( .A0(n3143), .A1(FPMULT_Add_result[3]), .B0(n3142), .B1(
FPMULT_P_Sgf[27]), .Y(n3138) );
OAI211XLTS U4121 ( .A0(n3146), .A1(n4257), .B0(n3139), .C0(n3138), .Y(n1508)
);
AOI22X1TS U4122 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n3141), .B0(
FPMULT_P_Sgf[40]), .B1(n3140), .Y(n3145) );
AOI22X1TS U4123 ( .A0(FPMULT_Add_result[17]), .A1(n3143), .B0(
FPMULT_P_Sgf[41]), .B1(n3142), .Y(n3144) );
OAI211XLTS U4124 ( .A0(n4727), .A1(n3146), .B0(n3145), .C0(n3144), .Y(n1522)
);
NOR2X1TS U4125 ( .A(n4620), .B(FPADDSUB_intDX_EWSW[25]), .Y(n3206) );
NOR2XLTS U4126 ( .A(n3206), .B(FPADDSUB_intDY_EWSW[24]), .Y(n3147) );
AOI22X1TS U4127 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n4620), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n3147), .Y(n3151) );
NAND2BXLTS U4128 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n3148) );
OAI21X1TS U4129 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n4627), .B0(n3148), .Y(
n3207) );
NAND3XLTS U4130 ( .A(n4627), .B(n3148), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n3150) );
OAI211XLTS U4131 ( .A0(n3151), .A1(n3207), .B0(n3150), .C0(n3149), .Y(n3156)
);
INVX1TS U4132 ( .A(FPADDSUB_intDX_EWSW[28]), .Y(n4404) );
NOR2X1TS U4133 ( .A(n4644), .B(FPADDSUB_intDX_EWSW[30]), .Y(n3154) );
NOR2X1TS U4134 ( .A(n4566), .B(FPADDSUB_intDX_EWSW[29]), .Y(n3152) );
AOI211X1TS U4135 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n4404), .B0(n3154),
.C0(n3152), .Y(n3205) );
AOI2BB2X1TS U4136 ( .B0(n3156), .B1(n3205), .A0N(n3155), .A1N(n3154), .Y(
n3211) );
NOR2X1TS U4137 ( .A(n4635), .B(FPADDSUB_intDX_EWSW[17]), .Y(n3192) );
NAND2BXLTS U4138 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n3173) );
NOR2X1TS U4139 ( .A(n4619), .B(FPADDSUB_intDX_EWSW[11]), .Y(n3171) );
AOI21X1TS U4140 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n4678), .B0(n3171), .Y(
n3176) );
OAI211XLTS U4141 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n4636), .B0(n3173), .C0(
n3176), .Y(n3187) );
OAI2BB1X1TS U4142 ( .A0N(n4675), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n3157) );
OAI22X1TS U4143 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3157), .B0(n4675), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n3168) );
OAI2BB1X1TS U4144 ( .A0N(n4579), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n3158) );
OAI22X1TS U4145 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3158), .B0(n4579), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n3167) );
OAI2BB2XLTS U4146 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n3159), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n4615), .Y(n3161) );
NAND2BXLTS U4147 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n3160) );
OAI211XLTS U4148 ( .A0(n4611), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n3161), .C0(
n3160), .Y(n3164) );
OAI21XLTS U4149 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n4611), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n3162) );
AOI2BB2XLTS U4150 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n4611), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n3162), .Y(n3163) );
AOI22X1TS U4151 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n4579), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n4688), .Y(n3165) );
OAI32X1TS U4152 ( .A0(n3168), .A1(n3167), .A2(n3166), .B0(n3165), .B1(n3167),
.Y(n3186) );
OA22X1TS U4153 ( .A0(n4608), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n4558), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n3183) );
NAND2BXLTS U4154 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n3169) );
OAI21XLTS U4155 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n4629), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n3170) );
OAI2BB2XLTS U4156 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n3170), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n4629), .Y(n3182) );
NOR2XLTS U4157 ( .A(n3171), .B(FPADDSUB_intDY_EWSW[10]), .Y(n3172) );
AOI22X1TS U4158 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n4619), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n3172), .Y(n3178) );
NAND3XLTS U4159 ( .A(n4636), .B(n3173), .C(FPADDSUB_intDX_EWSW[8]), .Y(n3174) );
AOI21X1TS U4160 ( .A0(n3175), .A1(n3174), .B0(n3185), .Y(n3177) );
OAI2BB2XLTS U4161 ( .B0(n3178), .B1(n3185), .A0N(n3177), .A1N(n3176), .Y(
n3181) );
OAI2BB2XLTS U4162 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n3179), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n4558), .Y(n3180) );
AOI211X1TS U4163 ( .A0(n3183), .A1(n3182), .B0(n3181), .C0(n3180), .Y(n3184)
);
OAI31X1TS U4164 ( .A0(n3187), .A1(n3186), .A2(n3185), .B0(n3184), .Y(n3190)
);
OA22X1TS U4165 ( .A0(n4612), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n4562), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n3203) );
NAND2BXLTS U4166 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n3188) );
NAND2BXLTS U4167 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n3194) );
OAI21X1TS U4168 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n4643), .B0(n3194), .Y(
n3198) );
NAND3BXLTS U4169 ( .AN(n3192), .B(n3190), .C(n3189), .Y(n3210) );
OAI21XLTS U4170 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n4628), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n3191) );
OAI2BB2XLTS U4171 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n3191), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n4628), .Y(n3202) );
NOR2XLTS U4172 ( .A(n3192), .B(FPADDSUB_intDY_EWSW[16]), .Y(n3193) );
AOI22X1TS U4173 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n4635), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n3193), .Y(n3196) );
AOI32X1TS U4174 ( .A0(n4643), .A1(n3194), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n4565), .Y(n3195) );
OAI32X1TS U4175 ( .A0(n3198), .A1(n3197), .A2(n3196), .B0(n3195), .B1(n3197),
.Y(n3201) );
OAI21XLTS U4176 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n4562), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n3199) );
OAI2BB2XLTS U4177 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n3199), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n4562), .Y(n3200) );
AOI211X1TS U4178 ( .A0(n3203), .A1(n3202), .B0(n3201), .C0(n3200), .Y(n3209)
);
NAND2BXLTS U4179 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n3204) );
NAND4BBX1TS U4180 ( .AN(n3207), .BN(n3206), .C(n3205), .D(n3204), .Y(n3208)
);
INVX4TS U4181 ( .A(n3224), .Y(n3366) );
AOI22X1TS U4182 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n3261), .Y(n3212) );
OAI21XLTS U4183 ( .A0(n4578), .A1(n3225), .B0(n3212), .Y(n1401) );
AOI22X1TS U4184 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n3261), .Y(n3213) );
BUFX3TS U4185 ( .A(n3225), .Y(n3401) );
AOI22X1TS U4186 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n3261), .Y(n3214) );
OAI21XLTS U4187 ( .A0(n4688), .A1(n3401), .B0(n3214), .Y(n1383) );
AOI22X1TS U4188 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n3261), .Y(n3215) );
OAI21XLTS U4189 ( .A0(n4575), .A1(n3401), .B0(n3215), .Y(n1386) );
BUFX4TS U4190 ( .A(n3261), .Y(n3412) );
AOI22X1TS U4191 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n3412), .Y(n3216) );
OAI21XLTS U4192 ( .A0(n4673), .A1(n3401), .B0(n3216), .Y(n1377) );
AOI22X1TS U4193 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n3261), .Y(n3217) );
OAI21XLTS U4194 ( .A0(n4568), .A1(n3401), .B0(n3217), .Y(n1404) );
AOI22X1TS U4195 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n3261), .Y(n3218) );
OAI21XLTS U4196 ( .A0(n4666), .A1(n3401), .B0(n3218), .Y(n1380) );
AOI22X1TS U4197 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n3261), .Y(n3219) );
OAI21XLTS U4198 ( .A0(n4680), .A1(n3401), .B0(n3219), .Y(n1389) );
AOI22X1TS U4199 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n3261), .Y(n3220) );
OAI21XLTS U4200 ( .A0(n4681), .A1(n3401), .B0(n3220), .Y(n1407) );
AOI22X1TS U4201 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n3261), .Y(n3221) );
AOI22X1TS U4202 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n3261), .Y(n3222) );
OAI21XLTS U4203 ( .A0(n4674), .A1(n3401), .B0(n3222), .Y(n1392) );
AOI22X1TS U4204 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n3366), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n3261), .Y(n3223) );
OAI21XLTS U4205 ( .A0(n4665), .A1(n3401), .B0(n3223), .Y(n1398) );
CLKBUFX3TS U4206 ( .A(n3224), .Y(n3268) );
INVX4TS U4207 ( .A(n3225), .Y(n3368) );
AOI22X1TS U4208 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n3412), .Y(n3226) );
OAI21XLTS U4209 ( .A0(n4681), .A1(n3268), .B0(n3226), .Y(n1209) );
AOI22X1TS U4210 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n4418), .Y(n3227) );
INVX4TS U4211 ( .A(n3225), .Y(n3327) );
AOI22X1TS U4212 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n3261), .Y(n3228) );
OAI21XLTS U4213 ( .A0(n4665), .A1(n3268), .B0(n3228), .Y(n1221) );
AOI22X1TS U4214 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n3412), .Y(n3229) );
OAI21XLTS U4215 ( .A0(n4666), .A1(n3268), .B0(n3229), .Y(n1245) );
AOI22X1TS U4216 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n4418), .Y(n3230) );
OAI21XLTS U4217 ( .A0(n4568), .A1(n3268), .B0(n3230), .Y(n1213) );
AOI22X1TS U4218 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n3412), .Y(n3231) );
OAI21XLTS U4219 ( .A0(n4680), .A1(n3268), .B0(n3231), .Y(n1233) );
AOI22X1TS U4220 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n4418), .Y(n3232) );
OAI21XLTS U4221 ( .A0(n4578), .A1(n3268), .B0(n3232), .Y(n1217) );
AOI22X1TS U4222 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n3412), .Y(n3233) );
OAI21XLTS U4223 ( .A0(n4670), .A1(n3268), .B0(n3233), .Y(n1225) );
AOI22X1TS U4224 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n4418), .Y(n3234) );
OAI21XLTS U4225 ( .A0(n4674), .A1(n3268), .B0(n3234), .Y(n1229) );
AOI22X1TS U4226 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n3261), .Y(n3235) );
OAI21XLTS U4227 ( .A0(n4682), .A1(n3224), .B0(n3235), .Y(n1458) );
AOI22X1TS U4228 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n4549), .Y(n3236) );
OAI21XLTS U4229 ( .A0(n4685), .A1(n3224), .B0(n3236), .Y(n1459) );
AOI22X1TS U4230 ( .A0(FPADDSUB_intDY_EWSW[26]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[26]), .B1(n4549), .Y(n3237) );
OAI21XLTS U4231 ( .A0(n4668), .A1(n3224), .B0(n3237), .Y(n1462) );
AOI22X1TS U4232 ( .A0(FPADDSUB_intDY_EWSW[25]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[25]), .B1(n4549), .Y(n3238) );
OAI21XLTS U4233 ( .A0(n4581), .A1(n3224), .B0(n3238), .Y(n1463) );
AOI22X1TS U4234 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n4549), .Y(n3239) );
OAI21XLTS U4235 ( .A0(n4684), .A1(n3224), .B0(n3239), .Y(n1460) );
BUFX4TS U4236 ( .A(n4116), .Y(n4115) );
INVX2TS U4237 ( .A(n3242), .Y(n1764) );
AOI22X1TS U4238 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n3412), .Y(n3243) );
OAI21XLTS U4239 ( .A0(n4580), .A1(n3396), .B0(n3243), .Y(n1296) );
AOI22X1TS U4240 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n3261), .Y(n3244) );
OAI21XLTS U4241 ( .A0(n4671), .A1(n3396), .B0(n3244), .Y(n1289) );
AOI22X1TS U4242 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n3412), .Y(n3245) );
AOI22X1TS U4243 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n4418), .Y(n3246) );
OAI21XLTS U4244 ( .A0(n4677), .A1(n3396), .B0(n3246), .Y(n1269) );
AOI22X1TS U4245 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n3261), .Y(n3247) );
OAI21XLTS U4246 ( .A0(n4672), .A1(n3396), .B0(n3247), .Y(n1257) );
AOI22X1TS U4247 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n3412), .Y(n3248) );
OAI21XLTS U4248 ( .A0(n4573), .A1(n3396), .B0(n3248), .Y(n1261) );
INVX2TS U4249 ( .A(n3249), .Y(n1754) );
INVX2TS U4250 ( .A(n3250), .Y(n1753) );
INVX2TS U4251 ( .A(n3251), .Y(n1760) );
INVX2TS U4252 ( .A(n3252), .Y(n1757) );
INVX2TS U4253 ( .A(n3253), .Y(n1756) );
INVX2TS U4254 ( .A(n3254), .Y(n1761) );
INVX2TS U4255 ( .A(n3255), .Y(n1763) );
INVX2TS U4256 ( .A(n3256), .Y(n1759) );
INVX2TS U4257 ( .A(n3257), .Y(n1758) );
INVX2TS U4258 ( .A(n3258), .Y(n1755) );
INVX2TS U4259 ( .A(n3259), .Y(n1762) );
AOI22X1TS U4260 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n4418), .Y(n3260) );
OAI21XLTS U4261 ( .A0(n4676), .A1(n3224), .B0(n3260), .Y(n1310) );
AOI22X1TS U4262 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[27]), .B1(n3261), .Y(n3262) );
OAI21XLTS U4263 ( .A0(n4577), .A1(n3224), .B0(n3262), .Y(n1461) );
AOI22X1TS U4264 ( .A0(FPADDSUB_intDY_EWSW[24]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[24]), .B1(n4549), .Y(n3263) );
OAI21XLTS U4265 ( .A0(n4667), .A1(n3224), .B0(n3263), .Y(n1464) );
AOI22X1TS U4266 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n4418), .Y(n3264) );
OAI21XLTS U4267 ( .A0(n4678), .A1(n3396), .B0(n3264), .Y(n1265) );
AOI22X1TS U4268 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n3412), .Y(n3265) );
OAI21XLTS U4269 ( .A0(n4574), .A1(n3396), .B0(n3265), .Y(n1282) );
AOI22X1TS U4270 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n4418), .Y(n3266) );
OAI21XLTS U4271 ( .A0(n4673), .A1(n3396), .B0(n3266), .Y(n1249) );
AOI22X1TS U4272 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3327), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n3412), .Y(n3267) );
OAI21XLTS U4273 ( .A0(n4575), .A1(n3268), .B0(n3267), .Y(n1237) );
AOI22X1TS U4274 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n4418), .Y(n3269) );
OAI21XLTS U4275 ( .A0(n4675), .A1(n3396), .B0(n3269), .Y(n1275) );
AOI22X1TS U4276 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3368), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n3412), .Y(n3270) );
OAI21XLTS U4277 ( .A0(n4579), .A1(n3224), .B0(n3270), .Y(n1303) );
INVX2TS U4278 ( .A(n4081), .Y(n3439) );
NAND2X1TS U4279 ( .A(n4760), .B(n4083), .Y(n4082) );
AOI22X1TS U4280 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n4122), .B0(n3361),
.B1(n4082), .Y(n3271) );
OAI21XLTS U4281 ( .A0(n3272), .A1(n3439), .B0(n3271), .Y(n2116) );
NAND2X1TS U4282 ( .A(n4522), .B(n2254), .Y(n4511) );
INVX2TS U4283 ( .A(n4511), .Y(n3322) );
NAND3X2TS U4284 ( .A(n4623), .B(n2194), .C(FPADDSUB_shift_value_SHT2_EWR[3]),
.Y(n4362) );
NOR2X4TS U4285 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n3308) );
INVX2TS U4286 ( .A(n3308), .Y(n3300) );
AO22XLTS U4287 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n3274), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n3275), .Y(n3277) );
NOR2X2TS U4288 ( .A(n3308), .B(n2231), .Y(n3304) );
NAND2X2TS U4289 ( .A(n2194), .B(n3310), .Y(n4379) );
OAI22X1TS U4290 ( .A0(n4525), .A1(n2194), .B0(n2284), .B1(n4379), .Y(n3276)
);
NOR2BX1TS U4291 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n3288) );
AO22XLTS U4292 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n3308), .B0(
FPADDSUB_Data_array_SWR[20]), .B1(n3310), .Y(n3278) );
OAI22X1TS U4293 ( .A0(n3330), .A1(n4522), .B0(n4484), .B1(n3279), .Y(n4512)
);
INVX2TS U4294 ( .A(n3280), .Y(n4020) );
INVX2TS U4295 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n4022) );
AND4X1TS U4296 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n3281) );
NAND3XLTS U4297 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[5]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[4]), .C(n3281), .Y(n3282) );
NAND2BXLTS U4298 ( .AN(n3282), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n3283)
);
NOR2XLTS U4299 ( .A(n4022), .B(n3283), .Y(n3285) );
OAI2BB1X1TS U4300 ( .A0N(n3285), .A1N(n3284), .B0(n4351), .Y(n4023) );
BUFX4TS U4301 ( .A(n3286), .Y(n4365) );
OAI21XLTS U4302 ( .A0(n3322), .A1(n4512), .B0(n4365), .Y(n3287) );
OAI21XLTS U4303 ( .A0(n4351), .A1(n4653), .B0(n3287), .Y(n1369) );
AO22XLTS U4304 ( .A0(FPADDSUB_Data_array_SWR[5]), .A1(n4481), .B0(
FPADDSUB_Data_array_SWR[1]), .B1(n3275), .Y(n3291) );
AO22XLTS U4305 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n3308), .B0(
FPADDSUB_Data_array_SWR[25]), .B1(n3288), .Y(n3289) );
OAI22X1TS U4306 ( .A0(n3345), .A1(n2194), .B0(n2284), .B1(n4482), .Y(n3290)
);
OAI22X1TS U4307 ( .A0(n4489), .A1(n4522), .B0(n4491), .B1(n3279), .Y(n4521)
);
OAI21XLTS U4308 ( .A0(n3322), .A1(n4521), .B0(n4365), .Y(n3292) );
OAI21XLTS U4309 ( .A0(n4351), .A1(n4660), .B0(n3292), .Y(n1408) );
OAI2BB2XLTS U4310 ( .B0(n4491), .B1(n2194), .A0N(FPADDSUB_Data_array_SWR[16]), .A1N(n3273), .Y(n3293) );
OAI22X1TS U4311 ( .A0(n3345), .A1(n3279), .B0(n3344), .B1(n4522), .Y(n4513)
);
OAI21XLTS U4312 ( .A0(n4351), .A1(n4661), .B0(n3295), .Y(n1405) );
AO22XLTS U4313 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n3274), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n3275), .Y(n3298) );
OAI22X1TS U4314 ( .A0(n3336), .A1(n2194), .B0(n4701), .B1(n4362), .Y(n3297)
);
OAI22X1TS U4315 ( .A0(n3341), .A1(n4522), .B0(n3342), .B1(n3279), .Y(n4519)
);
OAI21XLTS U4316 ( .A0(n3322), .A1(n4519), .B0(n4365), .Y(n3299) );
OAI21XLTS U4317 ( .A0(n4351), .A1(n4546), .B0(n3299), .Y(n1399) );
AO22XLTS U4318 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n3274), .B0(
FPADDSUB_Data_array_SWR[3]), .B1(n3275), .Y(n3303) );
OAI22X1TS U4319 ( .A0(n3348), .A1(n2194), .B0(n2233), .B1(n4362), .Y(n3302)
);
OAI22X1TS U4320 ( .A0(n3350), .A1(n4522), .B0(n3351), .B1(n3279), .Y(n4518)
);
OAI21XLTS U4321 ( .A0(n3322), .A1(n4518), .B0(n4365), .Y(n3305) );
OAI21XLTS U4322 ( .A0(n4351), .A1(n4649), .B0(n3305), .Y(n1393) );
OAI2BB1X1TS U4323 ( .A0N(FPADDSUB_Data_array_SWR[21]), .A1N(n3308), .B0(
n3307), .Y(n3306) );
AO22XLTS U4324 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n3274), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n3275), .Y(n3312) );
OAI2BB1X1TS U4325 ( .A0N(FPADDSUB_Data_array_SWR[20]), .A1N(n3308), .B0(
n3307), .Y(n3309) );
OAI22X1TS U4326 ( .A0(n3333), .A1(n2194), .B0(n4697), .B1(n4362), .Y(n3311)
);
OAI22X1TS U4327 ( .A0(n3339), .A1(n3279), .B0(n3338), .B1(n4522), .Y(n4517)
);
OAI21XLTS U4328 ( .A0(n3322), .A1(n4517), .B0(n4365), .Y(n3313) );
OAI21XLTS U4329 ( .A0(n4351), .A1(n4648), .B0(n3313), .Y(n1396) );
AO22XLTS U4330 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n3274), .B0(
FPADDSUB_Data_array_SWR[6]), .B1(n3275), .Y(n3315) );
OAI22X1TS U4331 ( .A0(n3351), .A1(n2194), .B0(n4701), .B1(n4379), .Y(n3314)
);
OAI22X1TS U4332 ( .A0(n3348), .A1(n3279), .B0(n3347), .B1(n4522), .Y(n4515)
);
OAI21XLTS U4333 ( .A0(n3322), .A1(n4515), .B0(n4365), .Y(n3316) );
OAI21XLTS U4334 ( .A0(n4351), .A1(n4650), .B0(n3316), .Y(n1390) );
OAI2BB2XLTS U4335 ( .B0(n4686), .B1(n4482), .A0N(FPADDSUB_Data_array_SWR[15]), .A1N(n3273), .Y(n3318) );
OAI22X1TS U4336 ( .A0(n3342), .A1(n2194), .B0(n2233), .B1(n4379), .Y(n3317)
);
OAI22X1TS U4337 ( .A0(n3336), .A1(n3279), .B0(n3335), .B1(n4522), .Y(n4514)
);
OAI21XLTS U4338 ( .A0(n3322), .A1(n4514), .B0(n4365), .Y(n3319) );
OAI21XLTS U4339 ( .A0(n4351), .A1(n4652), .B0(n3319), .Y(n1378) );
AO22XLTS U4340 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n3274), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n3275), .Y(n3321) );
OAI22X1TS U4341 ( .A0(n3339), .A1(n2194), .B0(n2284), .B1(n4362), .Y(n3320)
);
OAI22X1TS U4342 ( .A0(n3332), .A1(n4522), .B0(n3333), .B1(n3279), .Y(n4516)
);
OAI21XLTS U4343 ( .A0(n3322), .A1(n4516), .B0(n4365), .Y(n3323) );
OAI21XLTS U4344 ( .A0(n4351), .A1(n4662), .B0(n3323), .Y(n1402) );
INVX2TS U4345 ( .A(n3324), .Y(n1417) );
INVX2TS U4346 ( .A(n3325), .Y(n1414) );
INVX2TS U4347 ( .A(n3326), .Y(n1415) );
INVX2TS U4348 ( .A(n3328), .Y(n1416) );
NAND2X1TS U4349 ( .A(n4490), .B(n2254), .Y(n4487) );
INVX2TS U4350 ( .A(n4487), .Y(n3352) );
OAI22X1TS U4351 ( .A0(n4490), .A1(n3330), .B0(n4484), .B1(n3329), .Y(n4500)
);
OAI21XLTS U4352 ( .A0(n3352), .A1(n4500), .B0(n4365), .Y(n3331) );
OAI21XLTS U4353 ( .A0(n4829), .A1(n4654), .B0(n3331), .Y(n1306) );
OAI22X1TS U4354 ( .A0(n3333), .A1(n3329), .B0(n4490), .B1(n3332), .Y(n4496)
);
OAI21XLTS U4355 ( .A0(n3352), .A1(n4496), .B0(n4365), .Y(n3334) );
OAI21XLTS U4356 ( .A0(n4829), .A1(n4531), .B0(n3334), .Y(n1329) );
OAI22X1TS U4357 ( .A0(n3336), .A1(n3329), .B0(n4490), .B1(n3335), .Y(n4498)
);
OAI21XLTS U4358 ( .A0(n3352), .A1(n4498), .B0(n4365), .Y(n3337) );
OAI21XLTS U4359 ( .A0(n4829), .A1(n4655), .B0(n3337), .Y(n1278) );
OAI22X1TS U4360 ( .A0(n3339), .A1(n3329), .B0(n4490), .B1(n3338), .Y(n4495)
);
OAI21XLTS U4361 ( .A0(n3352), .A1(n4495), .B0(n4365), .Y(n3340) );
OAI21XLTS U4362 ( .A0(n4829), .A1(n4532), .B0(n3340), .Y(n1313) );
OAI22X1TS U4363 ( .A0(n3342), .A1(n3329), .B0(n4490), .B1(n3341), .Y(n4493)
);
OAI21XLTS U4364 ( .A0(n3352), .A1(n4493), .B0(n4365), .Y(n3343) );
OAI21XLTS U4365 ( .A0(n4351), .A1(n4663), .B0(n3343), .Y(n1299) );
OAI22X1TS U4366 ( .A0(n3345), .A1(n3329), .B0(n4490), .B1(n3344), .Y(n4499)
);
OAI21XLTS U4367 ( .A0(n3352), .A1(n4499), .B0(n4365), .Y(n3346) );
OAI21XLTS U4368 ( .A0(n4351), .A1(n4651), .B0(n3346), .Y(n1384) );
OAI22X1TS U4369 ( .A0(n3348), .A1(n3329), .B0(n4490), .B1(n3347), .Y(n4497)
);
OAI21XLTS U4370 ( .A0(n3352), .A1(n4497), .B0(n4365), .Y(n3349) );
OAI21XLTS U4371 ( .A0(n4351), .A1(n4547), .B0(n3349), .Y(n1387) );
OAI22X1TS U4372 ( .A0(n3351), .A1(n3329), .B0(n4490), .B1(n3350), .Y(n4494)
);
OAI21XLTS U4373 ( .A0(n3352), .A1(n4494), .B0(n4365), .Y(n3353) );
OAI21XLTS U4374 ( .A0(n4351), .A1(n4533), .B0(n3353), .Y(n1292) );
NOR3X1TS U4375 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(
n3426) );
NAND2X1TS U4376 ( .A(n3426), .B(n3432), .Y(n3531) );
NOR2X1TS U4377 ( .A(FPADDSUB_Raw_mant_NRM_SWR[18]), .B(n3531), .Y(n3416) );
NAND2X1TS U4378 ( .A(n3416), .B(n3417), .Y(n3542) );
INVX2TS U4379 ( .A(n3542), .Y(n3537) );
NAND2X1TS U4380 ( .A(n3418), .B(n3537), .Y(n3354) );
NOR2XLTS U4381 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n3356) );
NAND2X1TS U4382 ( .A(n4560), .B(n4642), .Y(n3547) );
NOR4X1TS U4383 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(
FPADDSUB_Raw_mant_NRM_SWR[1]), .C(FPADDSUB_Raw_mant_NRM_SWR[0]), .D(
n3547), .Y(n3355) );
AOI31XLTS U4384 ( .A0(n3356), .A1(n3546), .A2(n3355), .B0(n3354), .Y(n3357)
);
AOI21X1TS U4385 ( .A0(n3534), .A1(FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n3357),
.Y(n3360) );
INVX4TS U4386 ( .A(n3554), .Y(n4185) );
OAI21XLTS U4387 ( .A0(n3360), .A1(n3599), .B0(n3358), .Y(n2075) );
NAND2X1TS U4388 ( .A(n2195), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n3359)
);
OAI21XLTS U4389 ( .A0(n3360), .A1(n2195), .B0(n3359), .Y(n1330) );
NAND2X1TS U4390 ( .A(n3361), .B(n4559), .Y(n4086) );
AOI22X1TS U4391 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n4122), .B0(n3363),
.B1(n3362), .Y(n3365) );
OAI211XLTS U4392 ( .A0(n4760), .A1(n4086), .B0(n3365), .C0(n3364), .Y(n2127)
);
INVX2TS U4393 ( .A(n3369), .Y(n1465) );
AOI21X1TS U4394 ( .A0(operation[1]), .A1(ack_operation), .B0(n4070), .Y(
n4054) );
OR2X1TS U4395 ( .A(n3470), .B(n4054), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
INVX2TS U4396 ( .A(n3371), .Y(n1737) );
INVX2TS U4397 ( .A(n3372), .Y(n1752) );
OAI211XLTS U4398 ( .A0(n4124), .A1(n4740), .B0(n3442), .C0(n3423), .Y(n2126)
);
NAND2X1TS U4399 ( .A(n4081), .B(n4609), .Y(n3373) );
OAI211XLTS U4400 ( .A0(n4124), .A1(n4739), .B0(n3442), .C0(n3373), .Y(n2124)
);
NOR2XLTS U4401 ( .A(n4582), .B(n4705), .Y(FPMULT_S_Oper_A_exp[8]) );
BUFX4TS U4402 ( .A(n3240), .Y(n4099) );
BUFX3TS U4403 ( .A(n3446), .Y(n3449) );
INVX2TS U4404 ( .A(n3374), .Y(n1745) );
INVX2TS U4405 ( .A(n3375), .Y(n1742) );
INVX2TS U4406 ( .A(n3376), .Y(n1751) );
INVX2TS U4407 ( .A(n3377), .Y(n1733) );
INVX2TS U4408 ( .A(n3378), .Y(n1747) );
INVX2TS U4409 ( .A(n3379), .Y(n1748) );
INVX2TS U4410 ( .A(n3380), .Y(n1746) );
INVX2TS U4411 ( .A(n3381), .Y(n1750) );
INVX2TS U4412 ( .A(n3382), .Y(n1743) );
INVX2TS U4413 ( .A(n3383), .Y(n1749) );
INVX2TS U4414 ( .A(n3384), .Y(n1741) );
INVX2TS U4415 ( .A(n3386), .Y(n1744) );
AOI21X1TS U4416 ( .A0(n3389), .A1(n3388), .B0(n3387), .Y(n3395) );
AOI211XLTS U4417 ( .A0(n3392), .A1(n3391), .B0(n3390), .C0(n2910), .Y(n3393)
);
AOI21X1TS U4418 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n4424), .B0(n2246),
.Y(n3394) );
OAI21XLTS U4419 ( .A0(n3395), .A1(n3887), .B0(n3394), .Y(n1342) );
AOI22X1TS U4420 ( .A0(FPADDSUB_intDX_EWSW[6]), .A1(n3413), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n4418), .Y(n3397) );
OAI21XLTS U4421 ( .A0(n4689), .A1(n3401), .B0(n3397), .Y(n1241) );
AOI22X1TS U4422 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n3412), .Y(n3398) );
OAI21XLTS U4423 ( .A0(n4672), .A1(n3401), .B0(n3398), .Y(n1371) );
AOI22X1TS U4424 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n3412), .Y(n3399) );
OAI21XLTS U4425 ( .A0(n4679), .A1(n3401), .B0(n3399), .Y(n1374) );
AOI22X1TS U4426 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n4418), .Y(n3400) );
OAI21XLTS U4427 ( .A0(n4573), .A1(n3401), .B0(n3400), .Y(n1368) );
AOI22X1TS U4428 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n4418), .Y(n3402) );
OAI21XLTS U4429 ( .A0(n4671), .A1(n3225), .B0(n3402), .Y(n1291) );
AOI22X1TS U4430 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n3412), .Y(n3403) );
OAI21XLTS U4431 ( .A0(n4569), .A1(n3225), .B0(n3403), .Y(n1328) );
AOI22X1TS U4432 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n3412), .Y(n3404) );
OAI21XLTS U4433 ( .A0(n4677), .A1(n3225), .B0(n3404), .Y(n1271) );
AOI22X1TS U4434 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n4418), .Y(n3405) );
OAI21XLTS U4435 ( .A0(n4580), .A1(n3225), .B0(n3405), .Y(n1298) );
NAND3BX1TS U4436 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n3406), .Y(n4058) );
BUFX4TS U4437 ( .A(n4089), .Y(n4090) );
INVX2TS U4438 ( .A(operation[0]), .Y(n3407) );
OAI32X1TS U4439 ( .A0(n4088), .A1(n3407), .A2(n3677), .B0(n4703), .B1(n4090),
.Y(n2080) );
AOI22X1TS U4440 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n3412), .Y(n3408) );
OAI21XLTS U4441 ( .A0(n4676), .A1(n3225), .B0(n3408), .Y(n1312) );
AOI22X1TS U4442 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n3412), .Y(n3409) );
OAI21XLTS U4443 ( .A0(n4574), .A1(n3225), .B0(n3409), .Y(n1284) );
AOI22X1TS U4444 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n4418), .Y(n3410) );
OAI21XLTS U4445 ( .A0(n4678), .A1(n3225), .B0(n3410), .Y(n1365) );
AOI22X1TS U4446 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n4418), .Y(n3411) );
OAI21XLTS U4447 ( .A0(n4675), .A1(n3225), .B0(n3411), .Y(n1277) );
AOI22X1TS U4448 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3413), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n4418), .Y(n3414) );
NAND3X1TS U4449 ( .A(n3546), .B(n3550), .C(n4633), .Y(n3428) );
NOR4X1TS U4450 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(n3428), .C(n3547), .D(
n4541), .Y(n3419) );
NOR3BX1TS U4451 ( .AN(n3535), .B(n3430), .C(n3419), .Y(n3422) );
NAND2X1TS U4452 ( .A(n2195), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n3420)
);
OAI21XLTS U4453 ( .A0(n3422), .A1(n2195), .B0(n3420), .Y(n1322) );
AOI32X1TS U4454 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n3554), .A2(
n2195), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n4185), .Y(n3421)
);
OAI21XLTS U4455 ( .A0(n3422), .A1(n3599), .B0(n3421), .Y(n2076) );
INVX2TS U4456 ( .A(n3423), .Y(n3424) );
INVX2TS U4457 ( .A(n3425), .Y(n2120) );
NOR2X1TS U4458 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(n3428), .Y(n3548) );
INVX2TS U4459 ( .A(n3426), .Y(n3431) );
AOI32X1TS U4460 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n4560), .A2(n4541),
.B0(FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n4560), .Y(n3429) );
AOI32X1TS U4461 ( .A0(n4639), .A1(n3552), .A2(n3429), .B0(n3428), .B1(n3552),
.Y(n3533) );
AOI211XLTS U4462 ( .A0(n3432), .A1(n3431), .B0(n3430), .C0(n3533), .Y(n3433)
);
OAI2BB1X1TS U4463 ( .A0N(n3548), .A1N(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(
n3433), .Y(n3434) );
AOI31X1TS U4464 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n3534), .A2(n4545),
.B0(n3434), .Y(n3437) );
NAND2X1TS U4465 ( .A(n2195), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n3435)
);
OAI21XLTS U4466 ( .A0(n3437), .A1(n2195), .B0(n3435), .Y(n1318) );
AOI32X1TS U4467 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n3554), .A2(
n2195), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n4185), .Y(n3436)
);
OAI21XLTS U4468 ( .A0(n3437), .A1(n3599), .B0(n3436), .Y(n2077) );
AOI21X1TS U4469 ( .A0(FPSENCOS_d_ff3_LUT_out[3]), .A1(n4132), .B0(n3440),
.Y(n3438) );
OAI21XLTS U4470 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3439), .B0(n3438),
.Y(n2130) );
AOI21X1TS U4471 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n4132), .B0(n3440),
.Y(n3441) );
OAI21XLTS U4472 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3442), .B0(n3441),
.Y(n2132) );
INVX2TS U4473 ( .A(n3443), .Y(n1738) );
AOI222X1TS U4474 ( .A0(n4104), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n4117), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n3446), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n3444) );
INVX2TS U4475 ( .A(n3444), .Y(n1736) );
INVX2TS U4476 ( .A(n3445), .Y(n1735) );
INVX2TS U4477 ( .A(n3447), .Y(n1734) );
INVX2TS U4478 ( .A(n3448), .Y(n1740) );
INVX2TS U4479 ( .A(n3450), .Y(n1739) );
NOR4X1TS U4480 ( .A(FPMULT_P_Sgf[17]), .B(FPMULT_P_Sgf[16]), .C(
FPMULT_P_Sgf[15]), .D(FPMULT_P_Sgf[13]), .Y(n3459) );
NOR4X1TS U4481 ( .A(FPMULT_P_Sgf[21]), .B(FPMULT_P_Sgf[20]), .C(
FPMULT_P_Sgf[19]), .D(FPMULT_P_Sgf[18]), .Y(n3458) );
NOR4X1TS U4482 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_P_Sgf[5]), .C(
FPMULT_P_Sgf[3]), .D(FPMULT_P_Sgf[4]), .Y(n3454) );
NOR3XLTS U4483 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[2]), .C(
FPMULT_P_Sgf[0]), .Y(n3453) );
NOR4X1TS U4484 ( .A(FPMULT_P_Sgf[9]), .B(FPMULT_P_Sgf[10]), .C(
FPMULT_P_Sgf[14]), .D(FPMULT_P_Sgf[12]), .Y(n3452) );
AND4X1TS U4485 ( .A(n3454), .B(n3453), .C(n3452), .D(n3451), .Y(n3457) );
XOR2X1TS U4486 ( .A(FPMULT_Op_MY[31]), .B(FPMULT_Op_MX[31]), .Y(n4304) );
MXI2X1TS U4487 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n4304), .Y(n3455) );
AOI31X1TS U4488 ( .A0(n3459), .A1(n3458), .A2(n3457), .B0(n3456), .Y(n3990)
);
AOI31XLTS U4489 ( .A0(n4300), .A1(n3990), .A2(n3482), .B0(
FPMULT_FSM_selector_C), .Y(n3460) );
INVX2TS U4490 ( .A(n3460), .Y(n1528) );
AOI21X1TS U4491 ( .A0(n3463), .A1(n3462), .B0(n3461), .Y(n3469) );
AOI211XLTS U4492 ( .A0(n3466), .A1(n3465), .B0(n3464), .C0(n2910), .Y(n3467)
);
AOI21X1TS U4493 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(n4424), .B0(n2247),
.Y(n3468) );
NOR2XLTS U4494 ( .A(n3471), .B(n3470), .Y(n3474) );
BUFX4TS U4495 ( .A(n2200), .Y(n3514) );
XOR2X1TS U4496 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[1]), .B(
FPSENCOS_d_ff1_operation_out), .Y(n3472) );
CLKXOR2X2TS U4497 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .B(n3472),
.Y(n4210) );
NOR2X1TS U4498 ( .A(n3514), .B(n4210), .Y(n3473) );
INVX2TS U4499 ( .A(n4210), .Y(n4211) );
NOR2X1TS U4500 ( .A(n4211), .B(n2200), .Y(n3476) );
INVX2TS U4501 ( .A(n3475), .Y(n1716) );
INVX2TS U4502 ( .A(n3477), .Y(n1719) );
INVX2TS U4503 ( .A(n3478), .Y(n1723) );
INVX2TS U4504 ( .A(n3479), .Y(n1721) );
INVX2TS U4505 ( .A(n3480), .Y(n1720) );
NAND2X1TS U4506 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n4267), .Y(n4269)
);
NAND2X1TS U4507 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n4272), .Y(n4275)
);
NAND2X1TS U4508 ( .A(FPMULT_Sgf_normalized_result[13]), .B(n4274), .Y(n4279)
);
OAI211XLTS U4509 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4274), .B0(
n4296), .C0(n4279), .Y(n3481) );
OAI21XLTS U4510 ( .A0(n4718), .A1(n4284), .B0(n3481), .Y(n1607) );
NAND2X1TS U4511 ( .A(operation[2]), .B(n3677), .Y(n4068) );
BUFX4TS U4512 ( .A(n3759), .Y(n3794) );
NOR2X1TS U4513 ( .A(n4610), .B(n4557), .Y(n3988) );
NAND2X1TS U4514 ( .A(n3482), .B(n3988), .Y(n4067) );
AOI21X1TS U4515 ( .A0(ack_operation), .A1(n3794), .B0(n4067), .Y(n3516) );
AOI22X1TS U4516 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(
FPMULT_FS_Module_state_reg[1]), .B0(n3519), .B1(n3483), .Y(n3484) );
OR2X1TS U4517 ( .A(n3516), .B(n3484), .Y(n1690) );
INVX2TS U4518 ( .A(n3485), .Y(n1707) );
INVX2TS U4519 ( .A(n3486), .Y(n1704) );
INVX2TS U4520 ( .A(n3487), .Y(n1711) );
INVX2TS U4521 ( .A(n3488), .Y(n1709) );
INVX2TS U4522 ( .A(n3489), .Y(n1701) );
INVX2TS U4523 ( .A(n3490), .Y(n1705) );
INVX2TS U4524 ( .A(n3491), .Y(n1710) );
INVX2TS U4525 ( .A(n3492), .Y(n1712) );
INVX2TS U4526 ( .A(n3493), .Y(n1706) );
INVX2TS U4527 ( .A(n3494), .Y(n1724) );
INVX2TS U4528 ( .A(n3495), .Y(n1726) );
INVX2TS U4529 ( .A(n3496), .Y(n1703) );
INVX2TS U4530 ( .A(n3497), .Y(n1702) );
INVX2TS U4531 ( .A(n3498), .Y(n1708) );
INVX2TS U4532 ( .A(n3500), .Y(n1713) );
INVX2TS U4533 ( .A(n3502), .Y(n1725) );
INVX2TS U4534 ( .A(n3503), .Y(n1700) );
AOI222X1TS U4535 ( .A0(n3514), .A1(cordic_result[28]), .B0(n3499), .B1(
FPSENCOS_d_ff_Xn[28]), .C0(n3513), .C1(FPSENCOS_d_ff_Yn[28]), .Y(n3504) );
INVX2TS U4536 ( .A(n3504), .Y(n1698) );
INVX2TS U4537 ( .A(n3505), .Y(n1699) );
INVX2TS U4538 ( .A(n3506), .Y(n1722) );
INVX2TS U4539 ( .A(n3508), .Y(n1718) );
INVX2TS U4540 ( .A(n3509), .Y(n1717) );
INVX2TS U4541 ( .A(n3510), .Y(n1715) );
INVX2TS U4542 ( .A(n3511), .Y(n1696) );
INVX2TS U4543 ( .A(n3512), .Y(n1697) );
INVX2TS U4544 ( .A(n3515), .Y(n1714) );
AOI21X1TS U4545 ( .A0(FPMULT_zero_flag), .A1(n4759), .B0(n3516), .Y(n3518)
);
OAI211XLTS U4546 ( .A0(n4614), .A1(n3519), .B0(n3518), .C0(n3517), .Y(n1693)
);
AOI21X1TS U4547 ( .A0(n3522), .A1(n3521), .B0(n3520), .Y(n3528) );
AOI21X1TS U4548 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1(n4424), .B0(n3526),
.Y(n3527) );
OAI21XLTS U4549 ( .A0(n3528), .A1(n3887), .B0(n3527), .Y(n1339) );
AOI222X4TS U4550 ( .A0(n3578), .A1(FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(n3638), .B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .C0(FPADDSUB_Raw_mant_NRM_SWR[24]), .C1(
n3597), .Y(n3636) );
OAI32X1TS U4551 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n4631), .B0(n4563), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3529) );
OAI21XLTS U4552 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n3529), .B0(n4632),
.Y(n3530) );
OAI31X1TS U4553 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n4638), .A2(n3531),
.B0(n3530), .Y(n3532) );
AOI211X1TS U4554 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(n3534), .B0(n3533),
.C0(n3532), .Y(n3539) );
NOR4X1TS U4555 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .C(FPADDSUB_Raw_mant_NRM_SWR[9]), .D(
n4564), .Y(n3536) );
AOI32X1TS U4556 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n3537), .A2(n4626),
.B0(n3536), .B1(n3537), .Y(n3538) );
BUFX4TS U4557 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n4014) );
INVX2TS U4558 ( .A(n3559), .Y(n3562) );
NOR2XLTS U4559 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n3545) );
AOI31XLTS U4560 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n4542), .A2(n4638),
.B0(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n3541) );
NOR2XLTS U4561 ( .A(FPADDSUB_Raw_mant_NRM_SWR[23]), .B(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n3540) );
OAI31X1TS U4562 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[21]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[20]), .A2(n3541), .B0(n3540), .Y(n3544) );
NOR4X1TS U4563 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[12]), .C(n4543), .D(n3542), .Y(n3543) );
INVX2TS U4564 ( .A(n3546), .Y(n3549) );
AOI22X1TS U4565 ( .A0(n3550), .A1(n3549), .B0(n3548), .B1(n3547), .Y(n3551)
);
AOI31X1TS U4566 ( .A0(n3553), .A1(n3552), .A2(n3551), .B0(n2195), .Y(n4015)
);
AOI22X1TS U4567 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[1]), .A1(n2195), .B0(
n4015), .B1(n4669), .Y(n3558) );
NAND2X1TS U4568 ( .A(n3558), .B(n3554), .Y(n3555) );
INVX2TS U4569 ( .A(n2242), .Y(n3644) );
INVX4TS U4570 ( .A(n3554), .Y(n3656) );
OA22X1TS U4571 ( .A0(n4186), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n3599),
.B1(FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n4184) );
AOI22X1TS U4572 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n4184),
.B1(n2238), .Y(n3557) );
OAI21XLTS U4573 ( .A0(n3636), .A1(n3644), .B0(n3557), .Y(n1811) );
NOR2X1TS U4574 ( .A(n3656), .B(n3558), .Y(n3561) );
NAND2X2TS U4575 ( .A(n3561), .B(n3559), .Y(n3595) );
AOI22X1TS U4576 ( .A0(n3638), .A1(FPADDSUB_Raw_mant_NRM_SWR[2]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[21]), .B1(n2195), .Y(n3560) );
AOI22X1TS U4577 ( .A0(n4185), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n2239),
.B1(n3633), .Y(n3566) );
OAI22X1TS U4578 ( .A0(n4014), .A1(FPADDSUB_DmP_mant_SHT1_SW[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .B1(n4186), .Y(n3564) );
AOI22X1TS U4579 ( .A0(n3670), .A1(n4184), .B0(n2242), .B1(n3632), .Y(n3565)
);
OAI222X4TS U4580 ( .A0(FPADDSUB_DmP_mant_SHT1_SW[15]), .A1(
FPADDSUB_Shift_reg_FLAGS_7[1]), .B0(FPADDSUB_Raw_mant_NRM_SWR[17]),
.B1(n4186), .C0(FPADDSUB_Raw_mant_NRM_SWR[8]), .C1(n3599), .Y(n3615)
);
OAI22X1TS U4581 ( .A0(n4014), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n3599), .Y(n3567) );
AOI22X1TS U4582 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n2243),
.B1(n3655), .Y(n3571) );
OAI22X1TS U4583 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n3599), .B0(n4014),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n3568) );
OAI22X1TS U4584 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n3599), .B0(n4014),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n3569) );
AOI22X1TS U4585 ( .A0(n3670), .A1(n2230), .B0(n2239), .B1(n3645), .Y(n3570)
);
OAI211XLTS U4586 ( .A0(n3595), .A1(n3615), .B0(n3571), .C0(n3570), .Y(n1802)
);
OAI222X4TS U4587 ( .A0(FPADDSUB_DmP_mant_SHT1_SW[18]), .A1(
FPADDSUB_Shift_reg_FLAGS_7[1]), .B0(FPADDSUB_Raw_mant_NRM_SWR[20]),
.B1(n4186), .C0(FPADDSUB_Raw_mant_NRM_SWR[5]), .C1(n3599), .Y(n3612)
);
AOI22X1TS U4588 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n2242),
.B1(n2230), .Y(n3574) );
OAI22X1TS U4589 ( .A0(n4014), .A1(FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n4186), .Y(n3572) );
OAI222X1TS U4590 ( .A0(FPADDSUB_DmP_mant_SHT1_SW[17]), .A1(
FPADDSUB_Shift_reg_FLAGS_7[1]), .B0(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B1(n4186), .C0(FPADDSUB_Raw_mant_NRM_SWR[6]), .C1(n3599), .Y(n3608)
);
INVX2TS U4591 ( .A(n3608), .Y(n3616) );
AOI22X1TS U4592 ( .A0(n3670), .A1(n3631), .B0(n2239), .B1(n3616), .Y(n3573)
);
OAI211XLTS U4593 ( .A0(n3595), .A1(n3612), .B0(n3574), .C0(n3573), .Y(n1805)
);
AOI222X4TS U4594 ( .A0(n3578), .A1(FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .B1(n3597), .C0(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C1(n3638), .Y(n3673) );
OAI22X1TS U4595 ( .A0(n4014), .A1(FPADDSUB_DmP_mant_SHT1_SW[2]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n3599), .Y(n3575) );
AOI22X1TS U4596 ( .A0(n4185), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n2239),
.B1(n3668), .Y(n3577) );
AOI222X4TS U4597 ( .A0(n4692), .A1(n3578), .B0(n4571), .B1(n3638), .C0(n4545), .C1(n3597), .Y(n3669) );
OAI222X1TS U4598 ( .A0(FPADDSUB_DmP_mant_SHT1_SW[1]), .A1(
FPADDSUB_Shift_reg_FLAGS_7[1]), .B0(FPADDSUB_Raw_mant_NRM_SWR[22]),
.B1(n3599), .C0(FPADDSUB_Raw_mant_NRM_SWR[3]), .C1(n4186), .Y(n3628)
);
INVX2TS U4599 ( .A(n3628), .Y(n3621) );
AOI22X1TS U4600 ( .A0(n3670), .A1(n3669), .B0(n2242), .B1(n3621), .Y(n3576)
);
OAI211XLTS U4601 ( .A0(n3673), .A1(n3595), .B0(n3577), .C0(n3576), .Y(n1790)
);
OAI222X4TS U4602 ( .A0(n3599), .A1(FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(n4186), .B1(FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(FPADDSUB_Shift_reg_FLAGS_7[1]), .C1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n3667) );
AOI222X4TS U4603 ( .A0(n4691), .A1(n3578), .B0(n4542), .B1(n3638), .C0(n4564), .C1(n3597), .Y(n3651) );
AOI22X1TS U4604 ( .A0(n4185), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n2242),
.B1(n3651), .Y(n3581) );
AOI222X4TS U4605 ( .A0(n2195), .A1(n4694), .B0(n4572), .B1(n3638), .C0(n4543), .C1(n3597), .Y(n3663) );
OAI22X1TS U4606 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n4186), .B0(n4014),
.B1(FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n3579) );
AOI22X1TS U4607 ( .A0(n3670), .A1(n3663), .B0(n2239), .B1(n3662), .Y(n3580)
);
OAI211XLTS U4608 ( .A0(n3595), .A1(n3667), .B0(n3581), .C0(n3580), .Y(n1795)
);
AOI22X1TS U4609 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n2242),
.B1(n3663), .Y(n3584) );
AOI222X4TS U4610 ( .A0(n2195), .A1(n4693), .B0(n4572), .B1(n3597), .C0(n4543), .C1(n3638), .Y(n3658) );
INVX2TS U4611 ( .A(n3582), .Y(n3664) );
AOI22X1TS U4612 ( .A0(n3670), .A1(n3658), .B0(n2239), .B1(n3664), .Y(n3583)
);
OAI211XLTS U4613 ( .A0(n3595), .A1(n3641), .B0(n3584), .C0(n3583), .Y(n1798)
);
NAND2X1TS U4614 ( .A(FPMULT_Sgf_normalized_result[15]), .B(n4278), .Y(n4282)
);
OAI21XLTS U4615 ( .A0(n4719), .A1(n4284), .B0(n3585), .Y(n1605) );
AOI21X1TS U4616 ( .A0(n3588), .A1(n3587), .B0(n3586), .Y(n3594) );
AOI21X1TS U4617 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n4424), .B0(n3592),
.Y(n3593) );
OAI21XLTS U4618 ( .A0(n3594), .A1(n3887), .B0(n3593), .Y(n1338) );
INVX2TS U4619 ( .A(n3668), .Y(n3602) );
OAI22X1TS U4620 ( .A0(n4700), .A1(n3599), .B0(n4541), .B1(n4186), .Y(n3624)
);
AOI22X1TS U4621 ( .A0(n4185), .A1(FPADDSUB_Data_array_SWR[1]), .B0(n2243),
.B1(n3624), .Y(n3601) );
AOI22X1TS U4622 ( .A0(n3597), .A1(FPADDSUB_Raw_mant_NRM_SWR[2]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[0]), .B1(n2195), .Y(n3598) );
AOI22X1TS U4623 ( .A0(n3596), .A1(n3621), .B0(n2238), .B1(n3625), .Y(n3600)
);
INVX2TS U4624 ( .A(n3633), .Y(n3605) );
INVX2TS U4625 ( .A(n3612), .Y(n3617) );
AOI22X1TS U4626 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n2243),
.B1(n3617), .Y(n3604) );
AOI22X1TS U4627 ( .A0(n3596), .A1(n3632), .B0(n2239), .B1(n3631), .Y(n3603)
);
OAI211XLTS U4628 ( .A0(n3605), .A1(n3563), .B0(n3604), .C0(n3603), .Y(n1807)
);
AOI22X1TS U4629 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n2243),
.B1(n3645), .Y(n3607) );
INVX2TS U4630 ( .A(n3615), .Y(n3609) );
AOI22X1TS U4631 ( .A0(n3596), .A1(n2230), .B0(n2239), .B1(n3609), .Y(n3606)
);
OAI211XLTS U4632 ( .A0(n3563), .A1(n3608), .B0(n3607), .C0(n3606), .Y(n1803)
);
AOI22X1TS U4633 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n2243),
.B1(n3609), .Y(n3611) );
AOI22X1TS U4634 ( .A0(n3596), .A1(n3616), .B0(n2239), .B1(n2230), .Y(n3610)
);
OAI211XLTS U4635 ( .A0(n3563), .A1(n3612), .B0(n3611), .C0(n3610), .Y(n1804)
);
AOI22X1TS U4636 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n2243),
.B1(n3658), .Y(n3614) );
AOI22X1TS U4637 ( .A0(n3596), .A1(n3645), .B0(n2239), .B1(n3655), .Y(n3613)
);
INVX2TS U4638 ( .A(n3632), .Y(n3620) );
AOI22X1TS U4639 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n2242),
.B1(n3616), .Y(n3619) );
AOI22X1TS U4640 ( .A0(n3596), .A1(n3631), .B0(n2238), .B1(n3617), .Y(n3618)
);
OAI211XLTS U4641 ( .A0(n3563), .A1(n3620), .B0(n3619), .C0(n3618), .Y(n1806)
);
AOI22X1TS U4642 ( .A0(n4185), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n2243),
.B1(n3625), .Y(n3623) );
AOI22X1TS U4643 ( .A0(n3596), .A1(n3668), .B0(n2238), .B1(n3621), .Y(n3622)
);
AOI22X1TS U4644 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n3638), .B0(n4185),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n3627) );
AOI21X1TS U4645 ( .A0(n3596), .A1(n3625), .B0(n3624), .Y(n3626) );
OAI211XLTS U4646 ( .A0(n3563), .A1(n3628), .B0(n3627), .C0(n3626), .Y(n1787)
);
AOI22X1TS U4647 ( .A0(n4184), .A1(n3596), .B0(n2243), .B1(n3633), .Y(n3630)
);
NAND2X1TS U4648 ( .A(n4185), .B(FPADDSUB_Data_array_SWR[23]), .Y(n3629) );
OAI211XLTS U4649 ( .A0(n3636), .A1(n3556), .B0(n3630), .C0(n3629), .Y(n1810)
);
AOI22X1TS U4650 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n2243),
.B1(n3631), .Y(n3635) );
AOI22X1TS U4651 ( .A0(n3596), .A1(n3633), .B0(n3632), .B1(n2238), .Y(n3634)
);
OAI211XLTS U4652 ( .A0(n3636), .A1(n3563), .B0(n3635), .C0(n3634), .Y(n1808)
);
OAI22X1TS U4653 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n4186), .B0(n4014),
.B1(FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n3637) );
AOI22X1TS U4654 ( .A0(n4185), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n3596),
.B1(n2229), .Y(n3640) );
AOI22X1TS U4655 ( .A0(n3670), .A1(n3651), .B0(n2238), .B1(n3669), .Y(n3639)
);
OAI211XLTS U4656 ( .A0(n3673), .A1(n3644), .B0(n3640), .C0(n3639), .Y(n1792)
);
AOI22X1TS U4657 ( .A0(n4185), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n2239),
.B1(n3663), .Y(n3643) );
INVX2TS U4658 ( .A(n3641), .Y(n3657) );
AOI22X1TS U4659 ( .A0(n3670), .A1(n3657), .B0(n3596), .B1(n3664), .Y(n3642)
);
INVX2TS U4660 ( .A(n3645), .Y(n3648) );
AOI22X1TS U4661 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n2242),
.B1(n3657), .Y(n3647) );
AOI22X1TS U4662 ( .A0(n3596), .A1(n3655), .B0(n2238), .B1(n3658), .Y(n3646)
);
OAI211XLTS U4663 ( .A0(n3563), .A1(n3648), .B0(n3647), .C0(n3646), .Y(n1800)
);
AOI22X1TS U4664 ( .A0(n4185), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n2243),
.B1(n2229), .Y(n3650) );
AOI22X1TS U4665 ( .A0(n3596), .A1(n3662), .B0(n2238), .B1(n3651), .Y(n3649)
);
OAI211XLTS U4666 ( .A0(n3563), .A1(n3667), .B0(n3650), .C0(n3649), .Y(n1794)
);
INVX2TS U4667 ( .A(n3662), .Y(n3654) );
AOI22X1TS U4668 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n2242),
.B1(n3669), .Y(n3653) );
AOI22X1TS U4669 ( .A0(n3596), .A1(n3651), .B0(n2238), .B1(n2229), .Y(n3652)
);
OAI211XLTS U4670 ( .A0(n3563), .A1(n3654), .B0(n3653), .C0(n3652), .Y(n1793)
);
INVX2TS U4671 ( .A(n3655), .Y(n3661) );
AOI22X1TS U4672 ( .A0(n3656), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n2242),
.B1(n3664), .Y(n3660) );
AOI22X1TS U4673 ( .A0(n3596), .A1(n3658), .B0(n2238), .B1(n3657), .Y(n3659)
);
OAI211XLTS U4674 ( .A0(n3563), .A1(n3661), .B0(n3660), .C0(n3659), .Y(n1799)
);
AOI22X1TS U4675 ( .A0(n4185), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n2243),
.B1(n3662), .Y(n3666) );
AOI22X1TS U4676 ( .A0(n3670), .A1(n3664), .B0(n3596), .B1(n3663), .Y(n3665)
);
OAI211XLTS U4677 ( .A0(n3556), .A1(n3667), .B0(n3666), .C0(n3665), .Y(n1796)
);
AOI22X1TS U4678 ( .A0(n4185), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n2242),
.B1(n3668), .Y(n3672) );
AOI22X1TS U4679 ( .A0(n3670), .A1(n2229), .B0(n3596), .B1(n3669), .Y(n3671)
);
OAI211XLTS U4680 ( .A0(n3673), .A1(n3556), .B0(n3672), .C0(n3671), .Y(n1791)
);
NAND2X1TS U4681 ( .A(FPMULT_Sgf_normalized_result[17]), .B(n4281), .Y(n4285)
);
INVX2TS U4682 ( .A(operation[2]), .Y(n4064) );
NAND2X1TS U4683 ( .A(n4061), .B(n4062), .Y(n4049) );
OAI2BB2X1TS U4684 ( .B0(n3675), .B1(n3758), .A0N(operation[1]), .A1N(n4049),
.Y(n3991) );
NOR2X2TS U4685 ( .A(n3677), .B(n3678), .Y(n4198) );
AND3X1TS U4686 ( .A(n4200), .B(n4198), .C(n4576), .Y(n4153) );
INVX3TS U4687 ( .A(n2199), .Y(n3821) );
BUFX3TS U4688 ( .A(n3679), .Y(n4136) );
BUFX4TS U4689 ( .A(n3678), .Y(n4167) );
AOI22X1TS U4690 ( .A0(Data_1[28]), .A1(n4163), .B0(FPADDSUB_intDX_EWSW[28]),
.B1(n4167), .Y(n3683) );
INVX2TS U4691 ( .A(n4198), .Y(n3680) );
BUFX4TS U4692 ( .A(n3708), .Y(n3727) );
NOR3X1TS U4693 ( .A(n4200), .B(n3680), .C(n4576), .Y(n3681) );
BUFX4TS U4694 ( .A(n3681), .Y(n4137) );
AOI22X1TS U4695 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n4137), .B1(
FPSENCOS_d_ff2_Y[28]), .Y(n3682) );
BUFX4TS U4696 ( .A(n3678), .Y(n4140) );
AOI22X1TS U4697 ( .A0(Data_2[0]), .A1(n4136), .B0(FPADDSUB_intDY_EWSW[0]),
.B1(n4140), .Y(n3685) );
AOI22X1TS U4698 ( .A0(n3727), .A1(FPSENCOS_d_ff3_LUT_out[0]), .B0(n4137),
.B1(FPSENCOS_d_ff3_sh_x_out[0]), .Y(n3684) );
AOI22X1TS U4699 ( .A0(Data_1[31]), .A1(n4163), .B0(FPADDSUB_intDX_EWSW[31]),
.B1(n4140), .Y(n3687) );
AOI22X1TS U4700 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4137), .B1(
FPSENCOS_d_ff2_Y[31]), .Y(n3686) );
AOI22X1TS U4701 ( .A0(Data_1[26]), .A1(n3746), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n4140), .Y(n3689) );
AOI22X1TS U4702 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n4137), .B1(
FPSENCOS_d_ff2_Y[26]), .Y(n3688) );
AOI22X1TS U4703 ( .A0(Data_1[30]), .A1(n4205), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n4140), .Y(n3691) );
AOI22X1TS U4704 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n4137), .B1(
FPSENCOS_d_ff2_Y[30]), .Y(n3690) );
AOI22X1TS U4705 ( .A0(Data_1[29]), .A1(n4136), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n4140), .Y(n3693) );
AOI22X1TS U4706 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n4137), .B1(
FPSENCOS_d_ff2_Y[29]), .Y(n3692) );
AOI22X1TS U4707 ( .A0(Data_1[27]), .A1(n3746), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n4140), .Y(n3695) );
AOI22X1TS U4708 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n4137), .B1(
FPSENCOS_d_ff2_Y[27]), .Y(n3694) );
AOI22X1TS U4709 ( .A0(Data_1[25]), .A1(n3746), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n4140), .Y(n3697) );
AOI22X1TS U4710 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n4164), .B1(
FPSENCOS_d_ff2_Y[25]), .Y(n3696) );
AOI22X1TS U4711 ( .A0(Data_1[24]), .A1(n4205), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n4167), .Y(n3699) );
AOI22X1TS U4712 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n4164), .B1(
FPSENCOS_d_ff2_Y[24]), .Y(n3698) );
AOI22X1TS U4713 ( .A0(Data_1[21]), .A1(n3746), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n4140), .Y(n3701) );
AOI22X1TS U4714 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n4206), .B1(
FPSENCOS_d_ff2_Y[21]), .Y(n3700) );
AOI22X1TS U4715 ( .A0(Data_1[17]), .A1(n4205), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n4140), .Y(n3703) );
AOI22X1TS U4716 ( .A0(n3708), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n4206), .B1(
FPSENCOS_d_ff2_Y[17]), .Y(n3702) );
AOI22X1TS U4717 ( .A0(Data_1[20]), .A1(n4163), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n4167), .Y(n3705) );
AOI22X1TS U4718 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n4164), .B1(
FPSENCOS_d_ff2_Y[20]), .Y(n3704) );
AOI22X1TS U4719 ( .A0(Data_1[19]), .A1(n3746), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n4140), .Y(n3707) );
AOI22X1TS U4720 ( .A0(n3708), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n4164), .B1(
FPSENCOS_d_ff2_Y[19]), .Y(n3706) );
AOI22X1TS U4721 ( .A0(Data_1[15]), .A1(n4163), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n3678), .Y(n3710) );
AOI22X1TS U4722 ( .A0(n3708), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n4164), .B1(
FPSENCOS_d_ff2_Y[15]), .Y(n3709) );
AOI22X1TS U4723 ( .A0(Data_1[18]), .A1(n4205), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n4167), .Y(n3712) );
AOI22X1TS U4724 ( .A0(n3708), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n4206), .B1(
FPSENCOS_d_ff2_Y[18]), .Y(n3711) );
AOI22X1TS U4725 ( .A0(Data_1[22]), .A1(n3746), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n4167), .Y(n3714) );
AOI22X1TS U4726 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n4164), .B1(
FPSENCOS_d_ff2_Y[22]), .Y(n3713) );
AOI22X1TS U4727 ( .A0(Data_1[16]), .A1(n3746), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n3678), .Y(n3716) );
AOI22X1TS U4728 ( .A0(n3708), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n4157), .B1(
FPSENCOS_d_ff2_Y[16]), .Y(n3715) );
AOI22X1TS U4729 ( .A0(Data_1[23]), .A1(n4205), .B0(FPADDSUB_intDX_EWSW[23]),
.B1(n4167), .Y(n3718) );
AOI22X1TS U4730 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n4157), .B1(
FPSENCOS_d_ff2_Y[23]), .Y(n3717) );
INVX3TS U4731 ( .A(n2199), .Y(n3800) );
AOI22X1TS U4732 ( .A0(Data_1[9]), .A1(n4163), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n3678), .Y(n3720) );
BUFX4TS U4733 ( .A(n4137), .Y(n4157) );
AOI22X1TS U4734 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n4157), .B1(
FPSENCOS_d_ff2_Y[9]), .Y(n3719) );
AOI22X1TS U4735 ( .A0(Data_1[12]), .A1(n4136), .B0(FPADDSUB_intDX_EWSW[12]),
.B1(n3678), .Y(n3722) );
AOI22X1TS U4736 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n4164), .B1(
FPSENCOS_d_ff2_Y[12]), .Y(n3721) );
AOI22X1TS U4737 ( .A0(Data_1[5]), .A1(n3679), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n3678), .Y(n3724) );
AOI22X1TS U4738 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n4157), .B1(
FPSENCOS_d_ff2_Y[5]), .Y(n3723) );
AOI22X1TS U4739 ( .A0(Data_1[7]), .A1(n4205), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n3678), .Y(n3726) );
AOI22X1TS U4740 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n4157), .B1(
FPSENCOS_d_ff2_Y[7]), .Y(n3725) );
AOI22X1TS U4741 ( .A0(Data_1[10]), .A1(n4136), .B0(FPADDSUB_intDX_EWSW[10]),
.B1(n3678), .Y(n3729) );
AOI22X1TS U4742 ( .A0(n3727), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n4157), .B1(
FPSENCOS_d_ff2_Y[10]), .Y(n3728) );
AOI22X1TS U4743 ( .A0(Data_1[11]), .A1(n3746), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n3678), .Y(n3731) );
BUFX4TS U4744 ( .A(n3708), .Y(n4174) );
AOI22X1TS U4745 ( .A0(n4174), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n4157), .B1(
FPSENCOS_d_ff2_Y[11]), .Y(n3730) );
AOI22X1TS U4746 ( .A0(Data_1[8]), .A1(n3746), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n3678), .Y(n3733) );
AOI22X1TS U4747 ( .A0(n4174), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n4157), .B1(
FPSENCOS_d_ff2_Y[8]), .Y(n3732) );
BUFX4TS U4748 ( .A(n3678), .Y(n4204) );
AOI22X1TS U4749 ( .A0(Data_1[3]), .A1(n4163), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n4204), .Y(n3735) );
AOI22X1TS U4750 ( .A0(n4174), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n4157), .B1(
FPSENCOS_d_ff2_Y[3]), .Y(n3734) );
AOI22X1TS U4751 ( .A0(Data_1[6]), .A1(n4163), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n3678), .Y(n3737) );
AOI22X1TS U4752 ( .A0(n4174), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4206), .B1(
FPSENCOS_d_ff2_Y[6]), .Y(n3736) );
AOI22X1TS U4753 ( .A0(Data_1[2]), .A1(n4136), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n4204), .Y(n3739) );
AOI22X1TS U4754 ( .A0(n4174), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n4164), .B1(
FPSENCOS_d_ff2_Y[2]), .Y(n3738) );
AOI22X1TS U4755 ( .A0(Data_1[1]), .A1(n4136), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n4204), .Y(n3741) );
AOI22X1TS U4756 ( .A0(n4174), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4157), .B1(
FPSENCOS_d_ff2_Y[1]), .Y(n3740) );
AOI22X1TS U4757 ( .A0(Data_1[14]), .A1(n4163), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n3678), .Y(n3743) );
AOI22X1TS U4758 ( .A0(n4174), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n4206), .B1(
FPSENCOS_d_ff2_Y[14]), .Y(n3742) );
AOI22X1TS U4759 ( .A0(Data_1[13]), .A1(n4163), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n3678), .Y(n3745) );
AOI22X1TS U4760 ( .A0(n4174), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n4164), .B1(
FPSENCOS_d_ff2_Y[13]), .Y(n3744) );
AOI22X1TS U4761 ( .A0(Data_1[4]), .A1(n4205), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n4204), .Y(n3748) );
AOI22X1TS U4762 ( .A0(n4174), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n4157), .B1(
FPSENCOS_d_ff2_Y[4]), .Y(n3747) );
AOI22X1TS U4763 ( .A0(n4205), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n4204), .Y(n3750) );
AOI22X1TS U4764 ( .A0(n4174), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n4206), .B1(
FPSENCOS_d_ff2_Y[0]), .Y(n3749) );
AOI2BB2XLTS U4765 ( .B0(n3754), .B1(n3751), .A0N(n3751), .A1N(n3754), .Y(
n3757) );
AOI21X1TS U4766 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[14]), .A1(n4585), .B0(n3755),
.Y(n3756) );
BUFX3TS U4767 ( .A(n3758), .Y(n3790) );
BUFX3TS U4768 ( .A(n3790), .Y(n4069) );
NAND2X1TS U4769 ( .A(operation[1]), .B(n4064), .Y(n4071) );
AOI22X1TS U4770 ( .A0(cordic_result[31]), .A1(n3788), .B0(n3759), .B1(
mult_result[31]), .Y(n3760) );
OAI21XLTS U4771 ( .A0(n4069), .A1(n4664), .B0(n3760), .Y(op_result[31]) );
AOI22X1TS U4772 ( .A0(n3788), .A1(cordic_result[12]), .B0(n3794), .B1(
mult_result[12]), .Y(n3761) );
OAI21XLTS U4773 ( .A0(n3790), .A1(n4647), .B0(n3761), .Y(op_result[12]) );
AOI22X1TS U4774 ( .A0(n3788), .A1(cordic_result[15]), .B0(n3794), .B1(
mult_result[15]), .Y(n3762) );
OAI21XLTS U4775 ( .A0(n3790), .A1(n4661), .B0(n3762), .Y(op_result[15]) );
AOI22X1TS U4776 ( .A0(n3788), .A1(cordic_result[11]), .B0(n3794), .B1(
mult_result[11]), .Y(n3763) );
OAI21XLTS U4777 ( .A0(n4069), .A1(n4658), .B0(n3763), .Y(op_result[11]) );
AOI22X1TS U4778 ( .A0(n3788), .A1(cordic_result[13]), .B0(n3794), .B1(
mult_result[13]), .Y(n3764) );
OAI21XLTS U4779 ( .A0(n3790), .A1(n4645), .B0(n3764), .Y(op_result[13]) );
AOI22X1TS U4780 ( .A0(n3792), .A1(cordic_result[1]), .B0(n3759), .B1(
mult_result[1]), .Y(n3765) );
OAI21XLTS U4781 ( .A0(n4069), .A1(n4533), .B0(n3765), .Y(op_result[1]) );
AOI22X1TS U4782 ( .A0(n3788), .A1(cordic_result[23]), .B0(n3759), .B1(
mult_result[23]), .Y(n3766) );
OAI21XLTS U4783 ( .A0(n3790), .A1(n4544), .B0(n3766), .Y(op_result[23]) );
AOI22X1TS U4784 ( .A0(n3788), .A1(cordic_result[22]), .B0(n3759), .B1(
mult_result[22]), .Y(n3767) );
OAI21XLTS U4785 ( .A0(n3790), .A1(n4660), .B0(n3767), .Y(op_result[22]) );
AOI22X1TS U4786 ( .A0(n3792), .A1(cordic_result[27]), .B0(n3759), .B1(
mult_result[27]), .Y(n3768) );
OAI21XLTS U4787 ( .A0(n3758), .A1(n4536), .B0(n3768), .Y(op_result[27]) );
AOI22X1TS U4788 ( .A0(n3788), .A1(cordic_result[21]), .B0(n3759), .B1(
mult_result[21]), .Y(n3769) );
OAI21XLTS U4789 ( .A0(n3790), .A1(n4546), .B0(n3769), .Y(op_result[21]) );
AOI22X1TS U4790 ( .A0(n3788), .A1(cordic_result[14]), .B0(n3794), .B1(
mult_result[14]), .Y(n3770) );
OAI21XLTS U4791 ( .A0(n3790), .A1(n4653), .B0(n3770), .Y(op_result[14]) );
AOI22X1TS U4792 ( .A0(n3788), .A1(cordic_result[18]), .B0(n3794), .B1(
mult_result[18]), .Y(n3771) );
OAI21XLTS U4793 ( .A0(n3790), .A1(n4662), .B0(n3771), .Y(op_result[18]) );
AOI22X1TS U4794 ( .A0(n3788), .A1(cordic_result[16]), .B0(n3794), .B1(
mult_result[16]), .Y(n3772) );
OAI21XLTS U4795 ( .A0(n3790), .A1(n4652), .B0(n3772), .Y(op_result[16]) );
AOI22X1TS U4796 ( .A0(n3792), .A1(cordic_result[29]), .B0(n3759), .B1(
mult_result[29]), .Y(n3773) );
OAI21XLTS U4797 ( .A0(n3758), .A1(n4538), .B0(n3773), .Y(op_result[29]) );
AOI22X1TS U4798 ( .A0(n3788), .A1(cordic_result[10]), .B0(n3794), .B1(
mult_result[10]), .Y(n3774) );
OAI21XLTS U4799 ( .A0(n4069), .A1(n4646), .B0(n3774), .Y(op_result[10]) );
AOI22X1TS U4800 ( .A0(n3792), .A1(cordic_result[30]), .B0(n3759), .B1(
mult_result[30]), .Y(n3775) );
OAI21XLTS U4801 ( .A0(n3758), .A1(n4567), .B0(n3775), .Y(op_result[30]) );
AOI22X1TS U4802 ( .A0(n3792), .A1(cordic_result[24]), .B0(n3759), .B1(
mult_result[24]), .Y(n3776) );
OAI21XLTS U4803 ( .A0(n3758), .A1(n4534), .B0(n3776), .Y(op_result[24]) );
AOI22X1TS U4804 ( .A0(n3788), .A1(cordic_result[6]), .B0(n3794), .B1(
mult_result[6]), .Y(n3777) );
OAI21XLTS U4805 ( .A0(n3790), .A1(n4651), .B0(n3777), .Y(op_result[6]) );
AOI22X1TS U4806 ( .A0(n3792), .A1(cordic_result[3]), .B0(n3759), .B1(
mult_result[3]), .Y(n3778) );
OAI21XLTS U4807 ( .A0(n4069), .A1(n4531), .B0(n3778), .Y(op_result[3]) );
AOI22X1TS U4808 ( .A0(n3788), .A1(cordic_result[7]), .B0(n3794), .B1(
mult_result[7]), .Y(n3779) );
OAI21XLTS U4809 ( .A0(n4069), .A1(n4654), .B0(n3779), .Y(op_result[7]) );
AOI22X1TS U4810 ( .A0(n3788), .A1(cordic_result[26]), .B0(n3759), .B1(
mult_result[26]), .Y(n3780) );
OAI21XLTS U4811 ( .A0(n3758), .A1(n4535), .B0(n3780), .Y(op_result[26]) );
AOI22X1TS U4812 ( .A0(n3792), .A1(cordic_result[20]), .B0(n3759), .B1(
mult_result[20]), .Y(n3781) );
OAI21XLTS U4813 ( .A0(n3790), .A1(n4649), .B0(n3781), .Y(op_result[20]) );
AOI22X1TS U4814 ( .A0(n3788), .A1(cordic_result[8]), .B0(n3794), .B1(
mult_result[8]), .Y(n3782) );
OAI21XLTS U4815 ( .A0(n4069), .A1(n4657), .B0(n3782), .Y(op_result[8]) );
AOI22X1TS U4816 ( .A0(n3792), .A1(cordic_result[5]), .B0(n3759), .B1(
mult_result[5]), .Y(n3783) );
OAI21XLTS U4817 ( .A0(n4069), .A1(n4655), .B0(n3783), .Y(op_result[5]) );
AOI22X1TS U4818 ( .A0(n3788), .A1(cordic_result[9]), .B0(n3794), .B1(
mult_result[9]), .Y(n3784) );
OAI21XLTS U4819 ( .A0(n4069), .A1(n4659), .B0(n3784), .Y(op_result[9]) );
AOI22X1TS U4820 ( .A0(n3788), .A1(cordic_result[17]), .B0(n3794), .B1(
mult_result[17]), .Y(n3785) );
AOI22X1TS U4821 ( .A0(n3788), .A1(cordic_result[25]), .B0(n3759), .B1(
mult_result[25]), .Y(n3786) );
OAI21XLTS U4822 ( .A0(n3758), .A1(n4548), .B0(n3786), .Y(op_result[25]) );
AOI22X1TS U4823 ( .A0(n3792), .A1(cordic_result[2]), .B0(n3794), .B1(
mult_result[2]), .Y(n3787) );
AOI22X1TS U4824 ( .A0(n3788), .A1(cordic_result[19]), .B0(n3759), .B1(
mult_result[19]), .Y(n3789) );
OAI21XLTS U4825 ( .A0(n3790), .A1(n4648), .B0(n3789), .Y(op_result[19]) );
AOI22X1TS U4826 ( .A0(n3792), .A1(cordic_result[0]), .B0(n3794), .B1(
mult_result[0]), .Y(n3791) );
OAI21XLTS U4827 ( .A0(n4069), .A1(n4663), .B0(n3791), .Y(op_result[0]) );
AOI22X1TS U4828 ( .A0(cordic_result[28]), .A1(n3792), .B0(n3759), .B1(
mult_result[28]), .Y(n3793) );
OAI21XLTS U4829 ( .A0(n3758), .A1(n4537), .B0(n3793), .Y(op_result[28]) );
AOI22X1TS U4830 ( .A0(n3792), .A1(cordic_result[4]), .B0(n3794), .B1(
mult_result[4]), .Y(n3795) );
OAI21XLTS U4831 ( .A0(n4069), .A1(n4547), .B0(n3795), .Y(op_result[4]) );
AOI22X1TS U4832 ( .A0(Data_2[9]), .A1(n3746), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n4167), .Y(n3797) );
BUFX3TS U4833 ( .A(n4174), .Y(n3822) );
AOI22X1TS U4834 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[9]), .B0(n4206),
.B1(FPSENCOS_d_ff3_sh_x_out[9]), .Y(n3796) );
AOI22X1TS U4835 ( .A0(Data_2[10]), .A1(n4136), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n4167), .Y(n3799) );
AOI22X1TS U4836 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[10]), .B0(n4157),
.B1(FPSENCOS_d_ff3_sh_x_out[10]), .Y(n3798) );
AOI22X1TS U4837 ( .A0(Data_2[24]), .A1(n4136), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n4204), .Y(n3802) );
AOI22X1TS U4838 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[24]), .B0(n4157),
.B1(FPSENCOS_d_ff3_sh_x_out[24]), .Y(n3801) );
AOI22X1TS U4839 ( .A0(Data_2[4]), .A1(n4205), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n4140), .Y(n3804) );
AOI22X1TS U4840 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[4]), .B0(n4137),
.B1(FPSENCOS_d_ff3_sh_x_out[4]), .Y(n3803) );
AOI22X1TS U4841 ( .A0(Data_2[2]), .A1(n4136), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n4140), .Y(n3806) );
AOI22X1TS U4842 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[2]), .B0(n4137),
.B1(FPSENCOS_d_ff3_sh_x_out[2]), .Y(n3805) );
AOI22X1TS U4843 ( .A0(Data_2[8]), .A1(n4136), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n4140), .Y(n3808) );
AOI22X1TS U4844 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[8]), .B0(n4157),
.B1(FPSENCOS_d_ff3_sh_x_out[8]), .Y(n3807) );
AOI22X1TS U4845 ( .A0(Data_2[26]), .A1(n4136), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n4204), .Y(n3810) );
AOI22X1TS U4846 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[26]), .B0(n4157),
.B1(FPSENCOS_d_ff3_sh_x_out[26]), .Y(n3809) );
AOI22X1TS U4847 ( .A0(Data_2[25]), .A1(n4205), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n4204), .Y(n3812) );
AOI22X1TS U4848 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[25]), .B0(n4157),
.B1(FPSENCOS_d_ff3_sh_x_out[25]), .Y(n3811) );
AOI22X1TS U4849 ( .A0(Data_2[21]), .A1(n3746), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n4204), .Y(n3814) );
AOI22X1TS U4850 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[21]), .B0(n4157),
.B1(FPSENCOS_d_ff3_sh_x_out[21]), .Y(n3813) );
AOI22X1TS U4851 ( .A0(Data_2[23]), .A1(n3746), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n4204), .Y(n3816) );
AOI22X1TS U4852 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[23]), .B0(n4206),
.B1(FPSENCOS_d_ff3_sh_x_out[23]), .Y(n3815) );
AOI22X1TS U4853 ( .A0(Data_2[12]), .A1(n4163), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n4167), .Y(n3818) );
AOI22X1TS U4854 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[12]), .B0(n4157),
.B1(FPSENCOS_d_ff3_sh_x_out[12]), .Y(n3817) );
AOI22X1TS U4855 ( .A0(Data_2[1]), .A1(n3746), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n4140), .Y(n3820) );
AOI22X1TS U4856 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[1]), .B0(n4137),
.B1(FPSENCOS_d_ff3_sh_x_out[1]), .Y(n3819) );
AOI22X1TS U4857 ( .A0(Data_2[6]), .A1(n4163), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n4140), .Y(n3824) );
AOI22X1TS U4858 ( .A0(n3822), .A1(FPSENCOS_d_ff3_LUT_out[6]), .B0(n4137),
.B1(FPSENCOS_d_ff3_sh_x_out[6]), .Y(n3823) );
XOR2X1TS U4859 ( .A(intadd_499_SUM_16_), .B(n3826), .Y(n3827) );
XNOR2X1TS U4860 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .B(n3827), .Y(
n3829) );
AOI211XLTS U4861 ( .A0(n3834), .A1(n3833), .B0(n3832), .C0(n2910), .Y(n3835)
);
AOI21X1TS U4862 ( .A0(n4455), .A1(n3836), .B0(n2248), .Y(n3837) );
NAND2X1TS U4863 ( .A(FPMULT_Sgf_normalized_result[19]), .B(n4288), .Y(n4290)
);
NAND2X1TS U4864 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n4292), .Y(n3838)
);
NOR3BX2TS U4865 ( .AN(FPMULT_Sgf_normalized_result[22]), .B(n4299), .C(n3838), .Y(n4298) );
NAND2X1TS U4866 ( .A(n4284), .B(n3838), .Y(n4293) );
OAI22X1TS U4867 ( .A0(n4296), .A1(FPMULT_Add_result[22]), .B0(
FPMULT_Sgf_normalized_result[22]), .B1(n4293), .Y(n3839) );
XNOR2X1TS U4868 ( .A(intadd_499_SUM_19_), .B(n3840), .Y(n3841) );
XNOR2X1TS U4869 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .B(n3841), .Y(
n3843) );
NAND2X1TS U4870 ( .A(n4011), .B(FPMULT_P_Sgf[31]), .Y(n3842) );
OAI21XLTS U4871 ( .A0(n3847), .A1(n3845), .B0(n3844), .Y(n3850) );
AOI211XLTS U4872 ( .A0(n3848), .A1(n3847), .B0(n3846), .C0(n2910), .Y(n3849)
);
AOI21X1TS U4873 ( .A0(n4455), .A1(n3850), .B0(n2249), .Y(n3851) );
OAI21XLTS U4874 ( .A0(n3855), .A1(n3853), .B0(n3852), .Y(n3858) );
AOI211XLTS U4875 ( .A0(n3856), .A1(n3855), .B0(n3854), .C0(n2910), .Y(n3857)
);
AOI21X1TS U4876 ( .A0(n4455), .A1(n3858), .B0(n2250), .Y(n3859) );
XNOR2X1TS U4877 ( .A(intadd_499_SUM_21_), .B(n3860), .Y(n3861) );
XNOR2X1TS U4878 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .B(n3861), .Y(
n3863) );
NAND2X1TS U4879 ( .A(n4011), .B(FPMULT_P_Sgf[33]), .Y(n3862) );
OAI21XLTS U4880 ( .A0(n3867), .A1(n3865), .B0(n3864), .Y(n3870) );
AOI211XLTS U4881 ( .A0(n3868), .A1(n3867), .B0(n3866), .C0(n2910), .Y(n3869)
);
AOI21X1TS U4882 ( .A0(n4455), .A1(n3870), .B0(n2251), .Y(n3871) );
AOI211XLTS U4883 ( .A0(n3876), .A1(n3875), .B0(n3874), .C0(n2910), .Y(n3877)
);
AOI21X1TS U4884 ( .A0(n4455), .A1(n3878), .B0(n2252), .Y(n3879) );
AOI21X1TS U4885 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[21]), .A1(n4424), .B0(n3884),
.Y(n3885) );
XNOR2X1TS U4886 ( .A(n3890), .B(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .Y(
n3892) );
XOR2X1TS U4887 ( .A(n3894), .B(n3893), .Y(n3895) );
XNOR2X1TS U4888 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .B(n3895), .Y(
n3897) );
INVX2TS U4889 ( .A(FPMULT_Sgf_operation_Result[2]), .Y(n3900) );
INVX2TS U4890 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(n3899) );
INVX2TS U4891 ( .A(n3898), .Y(intadd_499_B_2_) );
CMPR32X2TS U4892 ( .A(n3900), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[2]),
.C(n3899), .CO(n3901), .S(n3898) );
INVX2TS U4893 ( .A(n3901), .Y(intadd_499_B_3_) );
INVX2TS U4894 ( .A(FPMULT_Sgf_operation_Result[3]), .Y(n3903) );
INVX2TS U4895 ( .A(n3902), .Y(intadd_499_A_3_) );
CMPR32X2TS U4896 ( .A(n3903), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[3]),
.C(n4318), .CO(n3904), .S(n3902) );
INVX2TS U4897 ( .A(n3904), .Y(intadd_499_B_4_) );
INVX2TS U4898 ( .A(FPMULT_Sgf_operation_Result[4]), .Y(n3907) );
INVX2TS U4899 ( .A(n3905), .Y(intadd_499_A_4_) );
CMPR32X2TS U4900 ( .A(n3907), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[4]),
.C(n3906), .CO(n3908), .S(n3905) );
INVX2TS U4901 ( .A(n3908), .Y(intadd_499_B_5_) );
INVX2TS U4902 ( .A(FPMULT_Sgf_operation_Result[5]), .Y(n3911) );
INVX2TS U4903 ( .A(n3909), .Y(intadd_499_A_5_) );
CMPR32X2TS U4904 ( .A(n3911), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[5]),
.C(n3910), .CO(n3912), .S(n3909) );
INVX2TS U4905 ( .A(n3912), .Y(intadd_499_B_6_) );
INVX2TS U4906 ( .A(FPMULT_Sgf_operation_Result[6]), .Y(n3915) );
INVX2TS U4907 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .Y(n3914) );
INVX2TS U4908 ( .A(n3913), .Y(intadd_499_A_6_) );
CMPR32X2TS U4909 ( .A(n3915), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[6]),
.C(n3914), .CO(n3916), .S(n3913) );
INVX2TS U4910 ( .A(n3916), .Y(intadd_499_B_7_) );
INVX2TS U4911 ( .A(FPMULT_Sgf_operation_Result[7]), .Y(n3919) );
INVX2TS U4912 ( .A(n3917), .Y(intadd_499_A_7_) );
CMPR32X2TS U4913 ( .A(n3919), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[7]),
.C(n3918), .CO(n3920), .S(n3917) );
INVX2TS U4914 ( .A(n3920), .Y(intadd_499_B_8_) );
INVX2TS U4915 ( .A(FPMULT_Sgf_operation_Result[8]), .Y(n3923) );
INVX2TS U4916 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .Y(n3922) );
INVX2TS U4917 ( .A(n3921), .Y(intadd_499_A_8_) );
CMPR32X2TS U4918 ( .A(n3923), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[8]),
.C(n3922), .CO(n3924), .S(n3921) );
INVX2TS U4919 ( .A(n3924), .Y(intadd_499_B_9_) );
INVX2TS U4920 ( .A(FPMULT_Sgf_operation_Result[9]), .Y(n3927) );
INVX2TS U4921 ( .A(n3925), .Y(intadd_499_A_9_) );
CMPR32X2TS U4922 ( .A(n3927), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[9]),
.C(n3926), .CO(n3928), .S(n3925) );
INVX2TS U4923 ( .A(n3928), .Y(intadd_499_B_10_) );
INVX2TS U4924 ( .A(FPMULT_Sgf_operation_Result[10]), .Y(n3931) );
INVX2TS U4925 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .Y(n3930) );
INVX2TS U4926 ( .A(n3929), .Y(intadd_499_A_10_) );
CMPR32X2TS U4927 ( .A(n3931), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[10]),
.C(n3930), .CO(n3932), .S(n3929) );
INVX2TS U4928 ( .A(n3932), .Y(intadd_499_B_11_) );
INVX2TS U4929 ( .A(FPMULT_Sgf_operation_Result[11]), .Y(n3935) );
INVX2TS U4930 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .Y(n3934) );
INVX2TS U4931 ( .A(n3933), .Y(intadd_499_A_11_) );
CMPR32X2TS U4932 ( .A(n3935), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[11]),
.C(n3934), .CO(n3936), .S(n3933) );
INVX2TS U4933 ( .A(n3936), .Y(intadd_499_B_12_) );
INVX2TS U4934 ( .A(n3937), .Y(intadd_499_A_12_) );
CMPR32X2TS U4935 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[12]), .B(n3939),
.C(n3938), .CO(n3940), .S(n3937) );
INVX2TS U4936 ( .A(n3940), .Y(intadd_499_B_13_) );
INVX2TS U4937 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[13]), .Y(n3943) );
INVX2TS U4938 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .Y(n3942) );
INVX2TS U4939 ( .A(n3941), .Y(intadd_499_A_13_) );
CMPR32X2TS U4940 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[13]), .B(n3943),
.C(n3942), .CO(n3944), .S(n3941) );
INVX2TS U4941 ( .A(n3944), .Y(intadd_499_B_14_) );
INVX2TS U4942 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[14]), .Y(n3947) );
INVX2TS U4943 ( .A(n3945), .Y(intadd_499_A_14_) );
CMPR32X2TS U4944 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[14]), .B(n3947),
.C(n3946), .CO(n3948), .S(n3945) );
INVX2TS U4945 ( .A(n3948), .Y(intadd_499_B_15_) );
INVX2TS U4946 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[15]), .Y(n3951) );
INVX2TS U4947 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[15]), .Y(n3950) );
INVX2TS U4948 ( .A(n3949), .Y(intadd_499_A_15_) );
CMPR32X2TS U4949 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[15]), .B(n3951),
.C(n3950), .CO(n3952), .S(n3949) );
INVX2TS U4950 ( .A(n3952), .Y(intadd_499_B_16_) );
INVX2TS U4951 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[16]), .Y(n3955) );
INVX2TS U4952 ( .A(n3953), .Y(intadd_499_A_16_) );
CMPR32X2TS U4953 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[16]), .B(n3955),
.C(n3954), .CO(n3956), .S(n3953) );
INVX2TS U4954 ( .A(n3956), .Y(intadd_499_B_17_) );
INVX2TS U4955 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[17]), .Y(n3959) );
INVX2TS U4956 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .Y(n3958) );
INVX2TS U4957 ( .A(n3957), .Y(intadd_499_A_17_) );
CMPR32X2TS U4958 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[17]), .B(n3959),
.C(n3958), .CO(n3960), .S(n3957) );
INVX2TS U4959 ( .A(n3960), .Y(intadd_499_B_18_) );
INVX2TS U4960 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[18]), .Y(n3963) );
INVX2TS U4961 ( .A(n3961), .Y(intadd_499_A_18_) );
CMPR32X2TS U4962 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[18]), .B(n3963),
.C(n3962), .CO(n3964), .S(n3961) );
INVX2TS U4963 ( .A(n3964), .Y(intadd_499_B_19_) );
INVX2TS U4964 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[19]), .Y(n3967) );
INVX2TS U4965 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[19]), .Y(n3966) );
INVX2TS U4966 ( .A(n3965), .Y(intadd_499_A_19_) );
CMPR32X2TS U4967 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[19]), .B(n3967),
.C(n3966), .CO(n3968), .S(n3965) );
INVX2TS U4968 ( .A(n3968), .Y(intadd_499_B_20_) );
INVX2TS U4969 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[20]), .Y(n3971) );
INVX2TS U4970 ( .A(n3969), .Y(intadd_499_A_20_) );
CMPR32X2TS U4971 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[20]), .B(n3971),
.C(n3970), .CO(n3972), .S(n3969) );
INVX2TS U4972 ( .A(n3972), .Y(intadd_499_B_21_) );
INVX2TS U4973 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .Y(n3974) );
INVX2TS U4974 ( .A(n3973), .Y(intadd_499_A_21_) );
CMPR32X2TS U4975 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[21]), .B(n3975),
.C(n3974), .CO(n3976), .S(n3973) );
INVX2TS U4976 ( .A(n3976), .Y(intadd_499_B_22_) );
INVX2TS U4977 ( .A(n3977), .Y(intadd_499_A_22_) );
CMPR32X2TS U4978 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[22]), .B(n3979),
.C(n3978), .CO(n3980), .S(n3977) );
INVX2TS U4979 ( .A(n3980), .Y(intadd_499_B_23_) );
INVX2TS U4980 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[23]), .Y(n3982) );
INVX2TS U4981 ( .A(n3981), .Y(intadd_499_A_23_) );
CMPR32X2TS U4982 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[23]), .B(n3983),
.C(n3982), .CO(n3984), .S(n3981) );
INVX2TS U4983 ( .A(n3984), .Y(intadd_499_B_24_) );
INVX2TS U4984 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[24]), .Y(
intadd_499_A_24_) );
OAI21XLTS U4985 ( .A0(n4078), .A1(n3986), .B0(FPSENCOS_cont_var_out[1]), .Y(
n3985) );
NAND2X1TS U4986 ( .A(n4624), .B(n4610), .Y(n4219) );
OAI222X1TS U4987 ( .A0(n4614), .A1(n4219), .B0(n3990), .B1(n3989), .C0(n3988), .C1(n3987), .Y(n1691) );
NOR3X1TS U4988 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .C(n4616), .Y(n4066) );
AOI31XLTS U4989 ( .A0(n3991), .A1(n4065), .A2(n4710), .B0(n4066), .Y(n3992)
);
OAI21XLTS U4990 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
n3993), .B0(n3992), .Y(n2149) );
NOR3BX1TS U4991 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n3994) );
XOR2X1TS U4992 ( .A(n4759), .B(n3994), .Y(DP_OP_234J221_127_8543_n15) );
OR2X2TS U4993 ( .A(FPMULT_FSM_selector_B[1]), .B(n4637), .Y(n4001) );
OAI2BB1X1TS U4994 ( .A0N(FPMULT_Op_MY[29]), .A1N(n4641), .B0(n4001), .Y(
n3995) );
XOR2X1TS U4995 ( .A(n4759), .B(n3995), .Y(DP_OP_234J221_127_8543_n16) );
OAI2BB1X1TS U4996 ( .A0N(FPMULT_Op_MY[28]), .A1N(n4641), .B0(n4001), .Y(
n3996) );
XOR2X1TS U4997 ( .A(n4759), .B(n3996), .Y(DP_OP_234J221_127_8543_n17) );
OAI2BB1X1TS U4998 ( .A0N(FPMULT_Op_MY[27]), .A1N(n4641), .B0(n4001), .Y(
n3997) );
XOR2X1TS U4999 ( .A(n4759), .B(n3997), .Y(DP_OP_234J221_127_8543_n18) );
OAI2BB1X1TS U5000 ( .A0N(FPMULT_Op_MY[26]), .A1N(n4641), .B0(n4001), .Y(
n3998) );
XOR2X1TS U5001 ( .A(n4759), .B(n3998), .Y(DP_OP_234J221_127_8543_n19) );
OAI2BB1X1TS U5002 ( .A0N(FPMULT_Op_MY[25]), .A1N(n4641), .B0(n4001), .Y(
n3999) );
XOR2X1TS U5003 ( .A(n4759), .B(n3999), .Y(DP_OP_234J221_127_8543_n20) );
OAI2BB1X1TS U5004 ( .A0N(FPMULT_Op_MY[24]), .A1N(n4641), .B0(n4001), .Y(
n4000) );
XOR2X1TS U5005 ( .A(n4759), .B(n4000), .Y(DP_OP_234J221_127_8543_n21) );
NOR2XLTS U5006 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n4002) );
OAI21XLTS U5007 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n4002), .B0(n4001), .Y(
n4003) );
XOR2X1TS U5008 ( .A(n4759), .B(n4003), .Y(DP_OP_234J221_127_8543_n22) );
NOR2BX1TS U5009 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4004) );
XOR2X1TS U5010 ( .A(n4556), .B(n4004), .Y(DP_OP_26J221_124_9022_n14) );
NOR2BX1TS U5011 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4005) );
XOR2X1TS U5012 ( .A(n4556), .B(n4005), .Y(DP_OP_26J221_124_9022_n15) );
NOR2BX1TS U5013 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4006) );
XOR2X1TS U5014 ( .A(n4556), .B(n4006), .Y(DP_OP_26J221_124_9022_n16) );
NOR2BX1TS U5015 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4007) );
XOR2X1TS U5016 ( .A(n4556), .B(n4007), .Y(DP_OP_26J221_124_9022_n17) );
OR2X1TS U5017 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n4008) );
XOR2X1TS U5018 ( .A(n4556), .B(n4008), .Y(DP_OP_26J221_124_9022_n18) );
NAND2X1TS U5019 ( .A(n4247), .B(n4705), .Y(n1689) );
BUFX3TS U5020 ( .A(n2310), .Y(n4224) );
MX2X1TS U5021 ( .A(FPMULT_exp_oper_result[7]), .B(
FPMULT_Exp_module_Data_S[7]), .S0(n4010), .Y(n1587) );
MX2X1TS U5022 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
MX2X1TS U5023 ( .A(FPMULT_exp_oper_result[6]), .B(
FPMULT_Exp_module_Data_S[6]), .S0(n4010), .Y(n1588) );
MX2X1TS U5024 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U5025 ( .A(FPMULT_exp_oper_result[5]), .B(
FPMULT_Exp_module_Data_S[5]), .S0(n4010), .Y(n1589) );
MX2X1TS U5026 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
BUFX3TS U5027 ( .A(n2310), .Y(n4223) );
MX2X1TS U5028 ( .A(FPMULT_exp_oper_result[4]), .B(
FPMULT_Exp_module_Data_S[4]), .S0(n4010), .Y(n1590) );
MX2X1TS U5029 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
MX2X1TS U5030 ( .A(FPMULT_exp_oper_result[3]), .B(
FPMULT_Exp_module_Data_S[3]), .S0(n4010), .Y(n1591) );
MX2X1TS U5031 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U5032 ( .A(FPMULT_exp_oper_result[2]), .B(
FPMULT_Exp_module_Data_S[2]), .S0(n4010), .Y(n1592) );
MX2X1TS U5033 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U5034 ( .A(FPMULT_exp_oper_result[1]), .B(
FPMULT_Exp_module_Data_S[1]), .S0(n4010), .Y(n1593) );
MX2X1TS U5035 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U5036 ( .A(FPMULT_exp_oper_result[0]), .B(
FPMULT_Exp_module_Data_S[0]), .S0(n4010), .Y(n1594) );
MX2X1TS U5037 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
INVX2TS U5038 ( .A(n4224), .Y(n4221) );
BUFX3TS U5039 ( .A(n2310), .Y(n4248) );
MX2X1TS U5040 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Data_S[8]), .S0(n4010), .Y(n1595) );
INVX2TS U5041 ( .A(n4759), .Y(n4217) );
XNOR2X1TS U5042 ( .A(DP_OP_234J221_127_8543_n1), .B(n4217), .Y(n4012) );
MX2X1TS U5043 ( .A(n4012), .B(FPMULT_Exp_module_Overflow_flag_A), .S0(n4011),
.Y(n1585) );
MX2X1TS U5044 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n4014), .Y(n1418) );
MX2X1TS U5045 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1423) );
MX2X1TS U5046 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(n4014), .Y(n1428) );
MX2X1TS U5047 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n4014), .Y(n1433) );
MX2X1TS U5048 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(n4014), .Y(n1438) );
MX2X1TS U5049 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n4014), .Y(n1443) );
MX2X1TS U5050 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n4014), .Y(n1448) );
MX2X1TS U5051 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n4014), .Y(n1453) );
AO21XLTS U5052 ( .A0(FPADDSUB_LZD_output_NRM2_EW[1]), .A1(n2195), .B0(n4015),
.Y(n1409) );
AO21XLTS U5053 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n2195), .B0(n4016),
.Y(n1314) );
OA21XLTS U5054 ( .A0(n4829), .A1(overflow_flag_addsubt), .B0(n4023), .Y(
n1411) );
AND4X1TS U5055 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n4017) );
AND4X1TS U5056 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[5]), .C(FPMULT_Exp_module_Data_S[4]), .D(
n4017), .Y(n4018) );
NOR4X1TS U5057 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_Exp_module_Data_S[7]), .C(n4018), .D(n4247), .Y(n4019) );
AO21XLTS U5058 ( .A0(underflow_flag_mult), .A1(n4247), .B0(n4019), .Y(n1586)
);
NOR2XLTS U5059 ( .A(n4020), .B(FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n4021) );
OAI22X1TS U5060 ( .A0(n4021), .A1(n4023), .B0(n4829), .B1(n4664), .Y(n1356)
);
OAI22X1TS U5061 ( .A0(n4023), .A1(n4022), .B0(n4829), .B1(n4567), .Y(n1466)
);
INVX2TS U5062 ( .A(n4025), .Y(n4350) );
AOI22X1TS U5063 ( .A0(n4350), .A1(n4024), .B0(n4704), .B1(n4535), .Y(n1470)
);
AOI2BB2XLTS U5064 ( .B0(n4704), .B1(n4534), .A0N(n4025), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n1472) );
NOR4X1TS U5065 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n4032) );
NOR4X1TS U5066 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n4031) );
NOR4X1TS U5067 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n4029) );
NOR4X1TS U5068 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n4027) );
NOR4X1TS U5069 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n4026) );
AND4X1TS U5070 ( .A(n4029), .B(n4028), .C(n4027), .D(n4026), .Y(n4030) );
NAND3XLTS U5071 ( .A(n4032), .B(n4031), .C(n4030), .Y(n4755) );
NOR4BX1TS U5072 ( .AN(operation_reg[1]), .B(operation_reg[0]), .C(dataB[28]),
.D(dataB[23]), .Y(n4037) );
NOR4X1TS U5073 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n4036) );
NAND4XLTS U5074 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n4034) );
NAND4XLTS U5075 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n4033) );
OR3X1TS U5076 ( .A(n4831), .B(n4034), .C(n4033), .Y(n4038) );
NOR3XLTS U5077 ( .A(dataB[25]), .B(dataB[31]), .C(n4038), .Y(n4035) );
AOI31XLTS U5078 ( .A0(n4037), .A1(n4036), .A2(n4035), .B0(dataB[27]), .Y(
n4048) );
NOR4X1TS U5079 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n4041) );
NOR4X1TS U5080 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n4040) );
NOR4BX1TS U5081 ( .AN(operation_reg[1]), .B(operation_reg[0]), .C(dataA[31]),
.D(n4831), .Y(n4039) );
NOR2X1TS U5082 ( .A(operation_reg[1]), .B(n4038), .Y(n4046) );
AOI31XLTS U5083 ( .A0(n4041), .A1(n4040), .A2(n4039), .B0(n4046), .Y(n4044)
);
NAND3XLTS U5084 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n4043) );
NAND4XLTS U5085 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n4042) );
OAI31X1TS U5086 ( .A0(n4044), .A1(n4043), .A2(n4042), .B0(dataB[27]), .Y(
n4045) );
NAND4XLTS U5087 ( .A(n4834), .B(n4833), .C(n4832), .D(n4045), .Y(n4047) );
OAI2BB2XLTS U5088 ( .B0(n4048), .B1(n4047), .A0N(n4046), .A1N(
operation_reg[0]), .Y(NaN_reg) );
NOR4X1TS U5089 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .B(n4055),
.C(n4049), .D(n4090), .Y(n4050) );
NAND2X1TS U5090 ( .A(n4108), .B(n4050), .Y(n4053) );
OAI22X1TS U5091 ( .A0(n4054), .A1(n4053), .B0(n4052), .B1(n4051), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
INVX2TS U5092 ( .A(n4055), .Y(n4056) );
AOI32X1TS U5093 ( .A0(n4059), .A1(n4058), .A2(n4057), .B0(n4056), .B1(n4058),
.Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
INVX4TS U5094 ( .A(n4093), .Y(n4191) );
OAI22X1TS U5095 ( .A0(n4191), .A1(n4062), .B0(n4061), .B1(n4060), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
OR2X1TS U5096 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .Y(n4063) );
AO22XLTS U5097 ( .A0(operation[2]), .A1(n4063), .B0(n4064), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U5098 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n4064),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
NAND2BXLTS U5099 ( .AN(n4066), .B(n4065), .Y(n2191) );
OAI222X1TS U5100 ( .A0(n4071), .A1(n4070), .B0(n4835), .B1(n4069), .C0(n4068), .C1(n4067), .Y(operation_ready) );
INVX2TS U5101 ( .A(n4072), .Y(n4074) );
AOI22X1TS U5102 ( .A0(n4074), .A1(n4418), .B0(n4478), .B1(n4072), .Y(n2147)
);
AOI22X1TS U5103 ( .A0(n4074), .A1(n4478), .B0(n4451), .B1(n4072), .Y(n2146)
);
AOI22X1TS U5104 ( .A0(n4074), .A1(n4585), .B0(n2195), .B1(n4072), .Y(n2143)
);
AOI22X1TS U5105 ( .A0(n4074), .A1(n2195), .B0(n4704), .B1(n4072), .Y(n2142)
);
AOI21X1TS U5106 ( .A0(n4609), .A1(n4075), .B0(n4076), .Y(n2140) );
AOI22X1TS U5107 ( .A0(n4076), .A1(FPSENCOS_cont_iter_out[2]), .B0(
intadd_501_B_1_), .B1(n2253), .Y(n2139) );
XNOR2X1TS U5108 ( .A(n4200), .B(n4078), .Y(n2137) );
AO22XLTS U5109 ( .A0(n4088), .A1(FPSENCOS_d_ff1_shift_region_flag_out[0]),
.B0(n4090), .B1(region_flag[0]), .Y(n2135) );
BUFX3TS U5110 ( .A(n4090), .Y(n4091) );
AO22XLTS U5111 ( .A0(n4088), .A1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.B0(n4091), .B1(region_flag[1]), .Y(n2134) );
INVX4TS U5112 ( .A(n4124), .Y(n4100) );
AO21XLTS U5113 ( .A0(FPSENCOS_d_ff3_LUT_out[8]), .A1(n4100), .B0(n4079), .Y(
n2125) );
BUFX3TS U5114 ( .A(n4131), .Y(n4129) );
AOI2BB2XLTS U5115 ( .B0(n4124), .B1(n4080), .A0N(FPSENCOS_d_ff3_LUT_out[13]),
.A1N(n4129), .Y(n2121) );
AO21XLTS U5116 ( .A0(FPSENCOS_d_ff3_LUT_out[19]), .A1(n4100), .B0(n4081),
.Y(n2119) );
OAI21XLTS U5117 ( .A0(n4760), .A1(n4083), .B0(n4082), .Y(n4084) );
AO22XLTS U5118 ( .A0(n2898), .A1(n4084), .B0(n4197), .B1(
FPSENCOS_d_ff3_LUT_out[23]), .Y(n2117) );
AOI21X1TS U5119 ( .A0(FPSENCOS_d_ff3_LUT_out[26]), .A1(n4132), .B0(n4085),
.Y(n4087) );
NAND2X1TS U5120 ( .A(n4087), .B(n4086), .Y(n2114) );
NAND2BXLTS U5121 ( .AN(FPSENCOS_d_ff3_LUT_out[27]), .B(n4119), .Y(n2113) );
AO22XLTS U5122 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n4090), .B1(
Data_1[0]), .Y(n2112) );
AO22XLTS U5123 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n4091), .B1(
Data_1[1]), .Y(n2111) );
AO22XLTS U5124 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n4091), .B1(
Data_1[2]), .Y(n2110) );
AO22XLTS U5125 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n4091), .B1(
Data_1[3]), .Y(n2109) );
AO22XLTS U5126 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n4091), .B1(
Data_1[4]), .Y(n2108) );
AO22XLTS U5127 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n4091), .B1(
Data_1[5]), .Y(n2107) );
AO22XLTS U5128 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n4091), .B1(
Data_1[6]), .Y(n2106) );
AO22XLTS U5129 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n4091), .B1(
Data_1[7]), .Y(n2105) );
AO22XLTS U5130 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n4091), .B1(
Data_1[8]), .Y(n2104) );
AO22XLTS U5131 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n4091), .B1(
Data_1[9]), .Y(n2103) );
AO22XLTS U5132 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n4091), .B1(
Data_1[10]), .Y(n2102) );
AO22XLTS U5133 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n4091), .B1(
Data_1[11]), .Y(n2101) );
AO22XLTS U5134 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n4090), .B1(
Data_1[12]), .Y(n2100) );
AO22XLTS U5135 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n4090), .B1(
Data_1[13]), .Y(n2099) );
AO22XLTS U5136 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n4090), .B1(
Data_1[14]), .Y(n2098) );
AO22XLTS U5137 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n4090), .B1(
Data_1[15]), .Y(n2097) );
AO22XLTS U5138 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n4089), .B1(
Data_1[16]), .Y(n2096) );
AO22XLTS U5139 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n4089), .B1(
Data_1[17]), .Y(n2095) );
AO22XLTS U5140 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n4089), .B1(
Data_1[18]), .Y(n2094) );
AO22XLTS U5141 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n4089), .B1(
Data_1[19]), .Y(n2093) );
AO22XLTS U5142 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n4089), .B1(
Data_1[20]), .Y(n2092) );
AO22XLTS U5143 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n4089), .B1(
Data_1[21]), .Y(n2091) );
AO22XLTS U5144 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n4090), .B1(
Data_1[22]), .Y(n2090) );
AO22XLTS U5145 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n4090), .B1(
Data_1[23]), .Y(n2089) );
AO22XLTS U5146 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n4089), .B1(
Data_1[24]), .Y(n2088) );
AO22XLTS U5147 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n4090), .B1(
Data_1[25]), .Y(n2087) );
AO22XLTS U5148 ( .A0(n4088), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n4090), .B1(
Data_1[26]), .Y(n2086) );
AO22XLTS U5149 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n4090), .B1(
Data_1[27]), .Y(n2085) );
AO22XLTS U5150 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n4090), .B1(
Data_1[28]), .Y(n2084) );
AO22XLTS U5151 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n4090), .B1(
Data_1[29]), .Y(n2083) );
AO22XLTS U5152 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n4090), .B1(
Data_1[30]), .Y(n2082) );
AO22XLTS U5153 ( .A0(n4092), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n4091), .B1(
Data_1[31]), .Y(n2081) );
AO22XLTS U5154 ( .A0(n4191), .A1(result_add_subt[0]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(n2074) );
NAND3X1TS U5155 ( .A(n4576), .B(n4200), .C(ready_add_subt), .Y(n4188) );
BUFX4TS U5156 ( .A(n4188), .Y(n4203) );
OAI2BB2XLTS U5157 ( .B0(n4192), .B1(n4663), .A0N(n4203), .A1N(
FPSENCOS_d_ff_Yn[0]), .Y(n2073) );
INVX4TS U5158 ( .A(n4189), .Y(n4209) );
AO22XLTS U5159 ( .A0(n4191), .A1(result_add_subt[1]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(n2071) );
BUFX4TS U5160 ( .A(n4094), .Y(n4202) );
OAI2BB2XLTS U5161 ( .B0(n4094), .B1(n4533), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[1]), .Y(n2070) );
INVX4TS U5162 ( .A(n4189), .Y(n4194) );
INVX1TS U5163 ( .A(FPSENCOS_d_ff_Xn[1]), .Y(n4095) );
BUFX4TS U5164 ( .A(n4189), .Y(n4193) );
AOI22X1TS U5165 ( .A0(n4194), .A1(n4533), .B0(n4095), .B1(n4193), .Y(n2069)
);
AO22XLTS U5166 ( .A0(n4191), .A1(result_add_subt[2]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(n2068) );
OAI2BB2XLTS U5167 ( .B0(n4203), .B1(n4532), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[2]), .Y(n2067) );
AOI22X1TS U5168 ( .A0(n4194), .A1(n4532), .B0(n2292), .B1(n4193), .Y(n2066)
);
AO22XLTS U5169 ( .A0(n4191), .A1(result_add_subt[3]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(n2065) );
OAI2BB2XLTS U5170 ( .B0(n4203), .B1(n4531), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[3]), .Y(n2064) );
AOI22X1TS U5171 ( .A0(n4194), .A1(n4531), .B0(n2274), .B1(n4193), .Y(n2063)
);
AO22XLTS U5172 ( .A0(n4191), .A1(result_add_subt[4]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(n2062) );
OAI2BB2XLTS U5173 ( .B0(n4202), .B1(n4547), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[4]), .Y(n2061) );
AO22XLTS U5174 ( .A0(n4191), .A1(result_add_subt[5]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(n2059) );
INVX1TS U5175 ( .A(FPSENCOS_d_ff_Xn[5]), .Y(n4096) );
AOI22X1TS U5176 ( .A0(n4194), .A1(n4655), .B0(n4096), .B1(n4193), .Y(n2057)
);
AO22XLTS U5177 ( .A0(n4191), .A1(result_add_subt[6]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(n2056) );
OAI2BB2XLTS U5178 ( .B0(n4094), .B1(n4651), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[6]), .Y(n2055) );
AOI22X1TS U5179 ( .A0(n4194), .A1(n4651), .B0(n2293), .B1(n4193), .Y(n2054)
);
AO22XLTS U5180 ( .A0(n4191), .A1(result_add_subt[7]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(n2053) );
OAI2BB2XLTS U5181 ( .B0(n4203), .B1(n4654), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[7]), .Y(n2052) );
INVX1TS U5182 ( .A(FPSENCOS_d_ff_Xn[7]), .Y(n4097) );
AOI22X1TS U5183 ( .A0(n4194), .A1(n4654), .B0(n4097), .B1(n4193), .Y(n2051)
);
AO22XLTS U5184 ( .A0(n4191), .A1(result_add_subt[8]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(n2050) );
OAI2BB2XLTS U5185 ( .B0(n4203), .B1(n4657), .A0N(n4203), .A1N(
FPSENCOS_d_ff_Yn[8]), .Y(n2049) );
AO22XLTS U5186 ( .A0(n4191), .A1(result_add_subt[9]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(n2047) );
AO22XLTS U5187 ( .A0(n4191), .A1(result_add_subt[10]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(n2044) );
OAI2BB2XLTS U5188 ( .B0(n4203), .B1(n4646), .A0N(n4094), .A1N(
FPSENCOS_d_ff_Yn[10]), .Y(n2043) );
AOI22X1TS U5189 ( .A0(n4194), .A1(n4646), .B0(n2287), .B1(n4193), .Y(n2042)
);
AO22XLTS U5190 ( .A0(n4191), .A1(result_add_subt[11]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(n2041) );
OAI2BB2XLTS U5191 ( .B0(n4203), .B1(n4658), .A0N(n4094), .A1N(
FPSENCOS_d_ff_Yn[11]), .Y(n2040) );
AO22XLTS U5192 ( .A0(n4191), .A1(result_add_subt[12]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(n2038) );
OAI2BB2XLTS U5193 ( .B0(n4203), .B1(n4647), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[12]), .Y(n2037) );
AOI22X1TS U5194 ( .A0(n4194), .A1(n4647), .B0(n2299), .B1(n4193), .Y(n2036)
);
INVX4TS U5195 ( .A(n4093), .Y(n4196) );
AO22XLTS U5196 ( .A0(n4196), .A1(result_add_subt[13]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(n2035) );
OAI2BB2XLTS U5197 ( .B0(n4203), .B1(n4645), .A0N(n4094), .A1N(
FPSENCOS_d_ff_Yn[13]), .Y(n2034) );
INVX1TS U5198 ( .A(FPSENCOS_d_ff_Xn[13]), .Y(n4098) );
AOI22X1TS U5199 ( .A0(n4194), .A1(n4645), .B0(n4098), .B1(n4193), .Y(n2033)
);
AO22XLTS U5200 ( .A0(n4196), .A1(result_add_subt[14]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(n2032) );
OAI2BB2XLTS U5201 ( .B0(n4203), .B1(n4653), .A0N(n4094), .A1N(
FPSENCOS_d_ff_Yn[14]), .Y(n2031) );
AOI22X1TS U5202 ( .A0(n4194), .A1(n4653), .B0(n2279), .B1(n4193), .Y(n2030)
);
AO22XLTS U5203 ( .A0(n4196), .A1(result_add_subt[15]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(n2029) );
AO22XLTS U5204 ( .A0(n4196), .A1(result_add_subt[16]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(n2026) );
OAI2BB2XLTS U5205 ( .B0(n4203), .B1(n4652), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[16]), .Y(n2025) );
AOI22X1TS U5206 ( .A0(n4209), .A1(n4652), .B0(n2297), .B1(n4193), .Y(n2024)
);
AO22XLTS U5207 ( .A0(n4196), .A1(result_add_subt[17]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(n2023) );
OAI2BB2XLTS U5208 ( .B0(n4203), .B1(n4650), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[17]), .Y(n2022) );
INVX1TS U5209 ( .A(FPSENCOS_d_ff_Xn[17]), .Y(n4101) );
AOI22X1TS U5210 ( .A0(n4209), .A1(n4650), .B0(n4101), .B1(n4193), .Y(n2021)
);
AO22XLTS U5211 ( .A0(n4196), .A1(result_add_subt[18]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(n2020) );
AO22XLTS U5212 ( .A0(n4196), .A1(result_add_subt[19]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(n2017) );
OAI2BB2XLTS U5213 ( .B0(n4192), .B1(n4648), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[19]), .Y(n2016) );
AOI22X1TS U5214 ( .A0(n4209), .A1(n4648), .B0(n2286), .B1(n4193), .Y(n2015)
);
AO22XLTS U5215 ( .A0(n4196), .A1(result_add_subt[20]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(n2014) );
OAI2BB2XLTS U5216 ( .B0(n4202), .B1(n4649), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[20]), .Y(n2013) );
AOI22X1TS U5217 ( .A0(n4209), .A1(n4649), .B0(n2301), .B1(n4189), .Y(n2012)
);
AO22XLTS U5218 ( .A0(n4196), .A1(result_add_subt[21]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(n2011) );
OAI2BB2XLTS U5219 ( .B0(n4094), .B1(n4546), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[21]), .Y(n2010) );
AO22XLTS U5220 ( .A0(n4196), .A1(result_add_subt[22]), .B0(n4093), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(n2008) );
OAI2BB2XLTS U5221 ( .B0(n4202), .B1(n4660), .A0N(n4192), .A1N(
FPSENCOS_d_ff_Yn[22]), .Y(n2007) );
AO22XLTS U5222 ( .A0(FPSENCOS_d_ff2_X[0]), .A1(n4121), .B0(
FPSENCOS_d_ff_Xn[0]), .B1(n4103), .Y(n2005) );
AO22XLTS U5223 ( .A0(n2898), .A1(FPSENCOS_d_ff2_X[0]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[0]), .Y(n2004) );
AOI22X1TS U5224 ( .A0(n4103), .A1(n4095), .B0(n2234), .B1(n4099), .Y(n2003)
);
AO22XLTS U5225 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[1]), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[1]), .Y(n2002) );
AOI22X1TS U5226 ( .A0(n4103), .A1(n2292), .B0(n2294), .B1(n4104), .Y(n2001)
);
AO22XLTS U5227 ( .A0(n2898), .A1(FPSENCOS_d_ff2_X[2]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[2]), .Y(n2000) );
AOI22X1TS U5228 ( .A0(n4103), .A1(n2274), .B0(n2196), .B1(n4099), .Y(n1999)
);
AO22XLTS U5229 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[3]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1998) );
BUFX4TS U5230 ( .A(n4099), .Y(n4114) );
AO22XLTS U5231 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n4114), .B0(
FPSENCOS_d_ff_Xn[4]), .B1(n4103), .Y(n1997) );
AO22XLTS U5232 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[4]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[4]), .Y(n1996) );
AOI22X1TS U5233 ( .A0(n4103), .A1(n4096), .B0(n2296), .B1(n4114), .Y(n1995)
);
AO22XLTS U5234 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[5]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1994) );
AOI22X1TS U5235 ( .A0(n4103), .A1(n2293), .B0(n2197), .B1(n4099), .Y(n1993)
);
AO22XLTS U5236 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[6]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[6]), .Y(n1992) );
AOI22X1TS U5237 ( .A0(n4103), .A1(n4097), .B0(n2236), .B1(n4104), .Y(n1991)
);
AO22XLTS U5238 ( .A0(n4131), .A1(FPSENCOS_d_ff2_X[7]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1990) );
AO22XLTS U5239 ( .A0(FPSENCOS_d_ff2_X[8]), .A1(n4114), .B0(
FPSENCOS_d_ff_Xn[8]), .B1(n4117), .Y(n1989) );
AO22XLTS U5240 ( .A0(n2898), .A1(FPSENCOS_d_ff2_X[8]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[8]), .Y(n1988) );
AO22XLTS U5241 ( .A0(FPSENCOS_d_ff2_X[9]), .A1(n4114), .B0(
FPSENCOS_d_ff_Xn[9]), .B1(n4117), .Y(n1987) );
AO22XLTS U5242 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[9]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[9]), .Y(n1986) );
AOI22X1TS U5243 ( .A0(n4103), .A1(n2287), .B0(n2288), .B1(n4104), .Y(n1985)
);
AO22XLTS U5244 ( .A0(n4131), .A1(FPSENCOS_d_ff2_X[10]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[10]), .Y(n1984) );
AO22XLTS U5245 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n4114), .B0(
FPSENCOS_d_ff_Xn[11]), .B1(n4117), .Y(n1983) );
AO22XLTS U5246 ( .A0(n4129), .A1(FPSENCOS_d_ff2_X[11]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1982) );
AOI22X1TS U5247 ( .A0(n4103), .A1(n2299), .B0(n2302), .B1(n4104), .Y(n1981)
);
AO22XLTS U5248 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[12]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[12]), .Y(n1980) );
AOI22X1TS U5249 ( .A0(n4103), .A1(n4098), .B0(n2295), .B1(n4114), .Y(n1979)
);
AO22XLTS U5250 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[13]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1978) );
AOI22X1TS U5251 ( .A0(n4103), .A1(n2279), .B0(n2282), .B1(n4104), .Y(n1977)
);
AO22XLTS U5252 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[14]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1976) );
AO22XLTS U5253 ( .A0(FPSENCOS_d_ff2_X[15]), .A1(n4099), .B0(
FPSENCOS_d_ff_Xn[15]), .B1(n4117), .Y(n1975) );
AO22XLTS U5254 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[15]), .B0(n4100), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1974) );
AOI22X1TS U5255 ( .A0(n4103), .A1(n2297), .B0(n2277), .B1(n4104), .Y(n1973)
);
AO22XLTS U5256 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[16]), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1972) );
AOI22X1TS U5257 ( .A0(n4103), .A1(n4101), .B0(n2276), .B1(n4104), .Y(n1971)
);
AO22XLTS U5258 ( .A0(n4133), .A1(FPSENCOS_d_ff2_X[17]), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1970) );
AO22XLTS U5259 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n4102), .B0(
FPSENCOS_d_ff_Xn[18]), .B1(n4117), .Y(n1969) );
AO22XLTS U5260 ( .A0(n2898), .A1(FPSENCOS_d_ff2_X[18]), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1968) );
AOI22X1TS U5261 ( .A0(n4103), .A1(n2286), .B0(n2271), .B1(n4104), .Y(n1967)
);
AO22XLTS U5262 ( .A0(n2898), .A1(FPSENCOS_d_ff2_X[19]), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1966) );
AOI22X1TS U5263 ( .A0(n3385), .A1(n2301), .B0(n2237), .B1(n4104), .Y(n1965)
);
AO22XLTS U5264 ( .A0(n4131), .A1(FPSENCOS_d_ff2_X[20]), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1964) );
AO22XLTS U5265 ( .A0(FPSENCOS_d_ff2_X[21]), .A1(n4114), .B0(
FPSENCOS_d_ff_Xn[21]), .B1(n4117), .Y(n1963) );
AO22XLTS U5266 ( .A0(n2898), .A1(FPSENCOS_d_ff2_X[21]), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[21]), .Y(n1962) );
AO22XLTS U5267 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n4114), .B0(
FPSENCOS_d_ff_Xn[22]), .B1(n4117), .Y(n1961) );
AO22XLTS U5268 ( .A0(n2898), .A1(FPSENCOS_d_ff2_X[22]), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1960) );
AO22XLTS U5269 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n4121), .B0(
FPSENCOS_d_ff_Xn[23]), .B1(n4117), .Y(n1959) );
AOI22X1TS U5270 ( .A0(n4103), .A1(n2269), .B0(n4720), .B1(n4104), .Y(n1958)
);
AOI22X1TS U5271 ( .A0(n3385), .A1(n2270), .B0(n4721), .B1(n4104), .Y(n1957)
);
AOI22X1TS U5272 ( .A0(n4103), .A1(n2275), .B0(n4722), .B1(n4104), .Y(n1956)
);
INVX1TS U5273 ( .A(FPSENCOS_d_ff_Xn[27]), .Y(n4190) );
AOI22X1TS U5274 ( .A0(n3385), .A1(n4190), .B0(n4716), .B1(n4104), .Y(n1955)
);
AOI22X1TS U5275 ( .A0(n4103), .A1(n2235), .B0(n4584), .B1(n4104), .Y(n1954)
);
AOI22X1TS U5276 ( .A0(n3385), .A1(n2281), .B0(n4708), .B1(n4104), .Y(n1953)
);
AO22XLTS U5277 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n4114), .B0(
FPSENCOS_d_ff_Xn[30]), .B1(n4117), .Y(n1952) );
OAI21XLTS U5278 ( .A0(n4760), .A1(n2232), .B0(intadd_502_CI), .Y(n4105) );
AO22XLTS U5279 ( .A0(n2898), .A1(n4105), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[23]), .Y(n1951) );
NOR2X2TS U5280 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_502_n1), .Y(n4110) );
AOI21X1TS U5281 ( .A0(intadd_502_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4110),
.Y(n4106) );
AOI2BB2XLTS U5282 ( .B0(n4131), .B1(n4106), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n4129), .Y(n1947) );
AOI21X1TS U5283 ( .A0(n4110), .A1(n4584), .B0(n4132), .Y(n4109) );
OAI21XLTS U5284 ( .A0(n4110), .A1(n4584), .B0(n4109), .Y(n4107) );
OA21XLTS U5285 ( .A0(FPSENCOS_d_ff3_sh_x_out[28]), .A1(n4131), .B0(n4107),
.Y(n1946) );
AOI22X1TS U5286 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n4109), .B0(
FPSENCOS_d_ff3_sh_x_out[29]), .B1(n4132), .Y(n4111) );
NAND4XLTS U5287 ( .A(n4124), .B(n4110), .C(n4584), .D(n4708), .Y(n4112) );
NAND2X1TS U5288 ( .A(n4111), .B(n4112), .Y(n1945) );
AOI22X1TS U5289 ( .A0(n4124), .A1(FPSENCOS_d_ff2_X[30]), .B0(
FPSENCOS_d_ff3_sh_x_out[30]), .B1(n4122), .Y(n4113) );
MXI2X1TS U5290 ( .A(FPSENCOS_d_ff2_X[30]), .B(n4113), .S0(n4112), .Y(n1944)
);
AO22XLTS U5291 ( .A0(FPSENCOS_d_ff2_X[31]), .A1(n4114), .B0(
FPSENCOS_d_ff_Xn[31]), .B1(n4117), .Y(n1943) );
AO22XLTS U5292 ( .A0(n4131), .A1(FPSENCOS_d_ff2_X[31]), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1942) );
AO22XLTS U5293 ( .A0(n4196), .A1(result_add_subt[31]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(n1909) );
AO22XLTS U5294 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n4114), .B0(
FPSENCOS_d_ff_Yn[0]), .B1(n4117), .Y(n1907) );
AO22XLTS U5295 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n4114), .B0(
FPSENCOS_d_ff_Yn[1]), .B1(n4117), .Y(n1905) );
AO22XLTS U5296 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n4114), .B0(
FPSENCOS_d_ff_Yn[2]), .B1(n4117), .Y(n1903) );
AO22XLTS U5297 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n4114), .B0(
FPSENCOS_d_ff_Yn[3]), .B1(n4117), .Y(n1901) );
AO22XLTS U5298 ( .A0(n4133), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n4119), .B1(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1900) );
AO22XLTS U5299 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n4114), .B0(
FPSENCOS_d_ff_Yn[4]), .B1(n4120), .Y(n1899) );
AO22XLTS U5300 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n4114), .B0(
FPSENCOS_d_ff_Yn[5]), .B1(n4117), .Y(n1897) );
AO22XLTS U5301 ( .A0(n4129), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n4108), .B1(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1896) );
AO22XLTS U5302 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n4114), .B0(
FPSENCOS_d_ff_Yn[6]), .B1(n4115), .Y(n1895) );
AO22XLTS U5303 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n4114), .B0(
FPSENCOS_d_ff_Yn[7]), .B1(n4115), .Y(n1893) );
AO22XLTS U5304 ( .A0(n4131), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n4197), .B1(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1892) );
AO22XLTS U5305 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n4114), .B0(
FPSENCOS_d_ff_Yn[8]), .B1(n4115), .Y(n1891) );
AO22XLTS U5306 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n4114), .B0(
FPSENCOS_d_ff_Yn[9]), .B1(n4115), .Y(n1889) );
AO22XLTS U5307 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[10]), .B1(n4115), .Y(n1887) );
AO22XLTS U5308 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[11]), .B1(n4116), .Y(n1885) );
AO22XLTS U5309 ( .A0(n4131), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n4132), .B1(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1884) );
AO22XLTS U5310 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[12]), .B1(n4116), .Y(n1883) );
AO22XLTS U5311 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n3240), .B0(
FPSENCOS_d_ff_Yn[13]), .B1(n4116), .Y(n1881) );
AO22XLTS U5312 ( .A0(n4131), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n4108), .B1(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1880) );
AO22XLTS U5313 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n3240), .B0(
FPSENCOS_d_ff_Yn[14]), .B1(n4116), .Y(n1879) );
AO22XLTS U5314 ( .A0(n4133), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n4132), .B1(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1878) );
AO22XLTS U5315 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n3240), .B0(
FPSENCOS_d_ff_Yn[15]), .B1(n4116), .Y(n1877) );
AO22XLTS U5316 ( .A0(n4133), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n4119), .B1(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1876) );
AO22XLTS U5317 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n3240), .B0(
FPSENCOS_d_ff_Yn[16]), .B1(n4120), .Y(n1875) );
AO22XLTS U5318 ( .A0(n4131), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n4119), .B1(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1874) );
AO22XLTS U5319 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n4102), .B0(
FPSENCOS_d_ff_Yn[17]), .B1(n4117), .Y(n1873) );
AO22XLTS U5320 ( .A0(n4133), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n4132), .B1(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1872) );
AO22XLTS U5321 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n4102), .B0(
FPSENCOS_d_ff_Yn[18]), .B1(n4120), .Y(n1871) );
AO22XLTS U5322 ( .A0(n4131), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n4108), .B1(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1870) );
AO22XLTS U5323 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n4102), .B0(
FPSENCOS_d_ff_Yn[19]), .B1(n4120), .Y(n1869) );
AO22XLTS U5324 ( .A0(n4118), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n4108), .B1(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1868) );
AO22XLTS U5325 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n4102), .B0(
FPSENCOS_d_ff_Yn[20]), .B1(n4120), .Y(n1867) );
AO22XLTS U5326 ( .A0(n4133), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n4132), .B1(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1866) );
AO22XLTS U5327 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n4102), .B0(
FPSENCOS_d_ff_Yn[21]), .B1(n4120), .Y(n1865) );
AO22XLTS U5328 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n3240), .B0(
FPSENCOS_d_ff_Yn[22]), .B1(n4120), .Y(n1863) );
AO22XLTS U5329 ( .A0(n4133), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n4132), .B1(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1862) );
AO22XLTS U5330 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[23]), .B1(n4120), .Y(n1861) );
AO22XLTS U5331 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[24]), .B1(n4120), .Y(n1860) );
AO22XLTS U5332 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[25]), .B1(n4120), .Y(n1859) );
AO22XLTS U5333 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[26]), .B1(n4120), .Y(n1858) );
AO22XLTS U5334 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[27]), .B1(n4120), .Y(n1857) );
AO22XLTS U5335 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[29]), .B1(n4120), .Y(n1855) );
AO22XLTS U5336 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n4121), .B0(
FPSENCOS_d_ff_Yn[30]), .B1(n4120), .Y(n1854) );
NAND2X1TS U5337 ( .A(FPSENCOS_d_ff2_Y[23]), .B(n2228), .Y(n4123) );
AOI32X1TS U5338 ( .A0(intadd_501_CI), .A1(n4124), .A2(n4123), .B0(n2198),
.B1(n4122), .Y(n1853) );
AO22XLTS U5339 ( .A0(n4119), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n4129),
.B1(intadd_501_SUM_0_), .Y(n1852) );
AO22XLTS U5340 ( .A0(n4108), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n2898),
.B1(intadd_501_SUM_1_), .Y(n1851) );
AO22XLTS U5341 ( .A0(n4108), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n4129),
.B1(intadd_501_SUM_2_), .Y(n1850) );
AOI21X1TS U5342 ( .A0(intadd_501_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n4125),
.Y(n4126) );
AOI2BB2XLTS U5343 ( .B0(n4131), .B1(n4126), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n4129), .Y(n1849) );
AOI21X1TS U5344 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4128), .B0(n4127), .Y(
n4130) );
AOI2BB2XLTS U5345 ( .B0(n4131), .B1(n4130), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n4129), .Y(n1847) );
AO22XLTS U5346 ( .A0(n4133), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n4119), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1844) );
AOI22X1TS U5347 ( .A0(Data_2[3]), .A1(n4163), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n4140), .Y(n4135) );
AOI22X1TS U5348 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n4137),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n4134) );
NAND2X1TS U5349 ( .A(n4174), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n4154) );
AOI22X1TS U5350 ( .A0(Data_2[5]), .A1(n3746), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n4140), .Y(n4139) );
AOI22X1TS U5351 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n4137),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n4138) );
NAND2X1TS U5352 ( .A(n4174), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n4148) );
AOI22X1TS U5353 ( .A0(Data_2[7]), .A1(n4163), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n4140), .Y(n4142) );
AOI22X1TS U5354 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n4164),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n4141) );
NAND2X1TS U5355 ( .A(n4174), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n4143) );
AOI22X1TS U5356 ( .A0(Data_2[11]), .A1(n4205), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n4167), .Y(n4145) );
AOI22X1TS U5357 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n4206),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n4144) );
AOI22X1TS U5358 ( .A0(Data_2[13]), .A1(n3746), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n4167), .Y(n4147) );
AOI22X1TS U5359 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n4164),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n4146) );
NAND2X1TS U5360 ( .A(n4174), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n4160) );
AOI22X1TS U5361 ( .A0(Data_2[14]), .A1(n4163), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n4167), .Y(n4150) );
AOI22X1TS U5362 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n4164),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n4149) );
AOI22X1TS U5363 ( .A0(Data_2[15]), .A1(n4205), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n4167), .Y(n4152) );
AOI22X1TS U5364 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n4206),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n4151) );
NAND2X1TS U5365 ( .A(n4174), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n4168) );
AOI22X1TS U5366 ( .A0(Data_2[16]), .A1(n4163), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n4167), .Y(n4156) );
AOI22X1TS U5367 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n4164),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n4155) );
AOI22X1TS U5368 ( .A0(Data_2[17]), .A1(n3746), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n4167), .Y(n4159) );
AOI22X1TS U5369 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n4164),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n4158) );
AOI22X1TS U5370 ( .A0(Data_2[18]), .A1(n4205), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n4167), .Y(n4162) );
AOI22X1TS U5371 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n4206),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n4161) );
AOI22X1TS U5372 ( .A0(Data_2[19]), .A1(n4163), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n4167), .Y(n4166) );
AOI22X1TS U5373 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n4164),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n4165) );
NAND2X1TS U5374 ( .A(n4174), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n4171) );
AOI22X1TS U5375 ( .A0(Data_2[20]), .A1(n3746), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n4167), .Y(n4170) );
AOI22X1TS U5376 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n4206),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n4169) );
AOI22X1TS U5377 ( .A0(Data_2[22]), .A1(n4163), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n4204), .Y(n4173) );
AOI22X1TS U5378 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n4206),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n4172) );
AOI22X1TS U5379 ( .A0(Data_2[27]), .A1(n3746), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n4204), .Y(n4176) );
AOI22X1TS U5380 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n4164),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n4175) );
NAND2X1TS U5381 ( .A(n4174), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n4179) );
AOI22X1TS U5382 ( .A0(Data_2[28]), .A1(n4205), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n4204), .Y(n4178) );
AOI22X1TS U5383 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n4164),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n4177) );
AOI22X1TS U5384 ( .A0(Data_2[29]), .A1(n4163), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n4204), .Y(n4181) );
AOI22X1TS U5385 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n4164),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n4180) );
AOI22X1TS U5386 ( .A0(Data_2[30]), .A1(n4163), .B0(FPADDSUB_intDY_EWSW[30]),
.B1(n4204), .Y(n4183) );
AOI22X1TS U5387 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[30]), .B0(n4206),
.B1(FPSENCOS_d_ff3_sh_x_out[30]), .Y(n4182) );
NAND2X1TS U5388 ( .A(n4183), .B(n4182), .Y(n1813) );
AOI22X1TS U5389 ( .A0(n4185), .A1(FPADDSUB_Data_array_SWR[25]), .B0(n4184),
.B1(n2243), .Y(n4187) );
NAND2X1TS U5390 ( .A(n4187), .B(n4186), .Y(n1812) );
AO22XLTS U5391 ( .A0(n4196), .A1(result_add_subt[23]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(n1786) );
OAI2BB2XLTS U5392 ( .B0(n4202), .B1(n4544), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[23]), .Y(n1785) );
AO22XLTS U5393 ( .A0(n4196), .A1(result_add_subt[24]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(n1783) );
OAI2BB2XLTS U5394 ( .B0(n4192), .B1(n4534), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[24]), .Y(n1782) );
AOI22X1TS U5395 ( .A0(n4209), .A1(n4534), .B0(n2269), .B1(n4193), .Y(n1781)
);
AO22XLTS U5396 ( .A0(n4196), .A1(result_add_subt[25]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(n1780) );
OAI2BB2XLTS U5397 ( .B0(n4188), .B1(n4548), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[25]), .Y(n1779) );
AOI22X1TS U5398 ( .A0(n4209), .A1(n4548), .B0(n2270), .B1(n4189), .Y(n1778)
);
AO22XLTS U5399 ( .A0(n4196), .A1(result_add_subt[26]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(n1777) );
OAI2BB2XLTS U5400 ( .B0(n4202), .B1(n4535), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[26]), .Y(n1776) );
AOI22X1TS U5401 ( .A0(n4209), .A1(n4535), .B0(n2275), .B1(n4193), .Y(n1775)
);
AO22XLTS U5402 ( .A0(n4191), .A1(result_add_subt[27]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(n1774) );
OAI2BB2XLTS U5403 ( .B0(n4202), .B1(n4536), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[27]), .Y(n1773) );
AOI22X1TS U5404 ( .A0(n4194), .A1(n4536), .B0(n4190), .B1(n4193), .Y(n1772)
);
AO22XLTS U5405 ( .A0(n4196), .A1(result_add_subt[28]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(n1771) );
OAI2BB2XLTS U5406 ( .B0(n4202), .B1(n4537), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[28]), .Y(n1770) );
AOI22X1TS U5407 ( .A0(n4194), .A1(n4537), .B0(n2235), .B1(n4193), .Y(n1769)
);
AO22XLTS U5408 ( .A0(n4191), .A1(result_add_subt[29]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(n1768) );
OAI2BB2XLTS U5409 ( .B0(n4192), .B1(n4538), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[29]), .Y(n1767) );
AOI22X1TS U5410 ( .A0(n4194), .A1(n4538), .B0(n2281), .B1(n4193), .Y(n1766)
);
AO22XLTS U5411 ( .A0(n4196), .A1(result_add_subt[30]), .B0(n4195), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(n1765) );
AO22XLTS U5412 ( .A0(n2898), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4197), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1732) );
AOI22X1TS U5413 ( .A0(operation[0]), .A1(n4136), .B0(FPADDSUB_intAS), .B1(
n4204), .Y(n4201) );
OAI2BB2XLTS U5414 ( .B0(n4203), .B1(n4567), .A0N(n4202), .A1N(
FPSENCOS_d_ff_Yn[30]), .Y(n1730) );
AOI22X1TS U5415 ( .A0(Data_2[31]), .A1(n3746), .B0(FPADDSUB_intDY_EWSW[31]),
.B1(n4204), .Y(n4208) );
AOI22X1TS U5416 ( .A0(n2199), .A1(FPSENCOS_d_ff3_sh_y_out[31]), .B0(n4164),
.B1(FPSENCOS_d_ff3_sh_x_out[31]), .Y(n4207) );
NAND2X1TS U5417 ( .A(n4208), .B(n4207), .Y(n1728) );
AOI22X1TS U5418 ( .A0(n4211), .A1(FPSENCOS_d_ff_Xn[31]), .B0(
FPSENCOS_d_ff_Yn[31]), .B1(n4210), .Y(n4213) );
XOR2XLTS U5419 ( .A(n4213), .B(n4212), .Y(n4214) );
OAI2BB2XLTS U5420 ( .B0(n2200), .B1(n4214), .A0N(n2200), .A1N(
cordic_result[31]), .Y(n1695) );
AOI21X1TS U5421 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_middle[1]), .A1(n4215),
.B0(intadd_499_A_2_), .Y(intadd_499_B_1_) );
OA22X1TS U5422 ( .A0(FPMULT_zero_flag), .A1(n4217), .B0(FPMULT_P_Sgf[47]),
.B1(n4216), .Y(n4220) );
AOI21X1TS U5423 ( .A0(begin_operation), .A1(n3759), .B0(n2201), .Y(n4218) );
AOI21X1TS U5424 ( .A0(n4220), .A1(n4219), .B0(n4218), .Y(n1692) );
AO22XLTS U5425 ( .A0(n4249), .A1(Data_1[31]), .B0(n2310), .B1(
FPMULT_Op_MX[31]), .Y(n1657) );
AO22XLTS U5426 ( .A0(n4249), .A1(Data_2[22]), .B0(n4248), .B1(
FPMULT_Op_MY[22]), .Y(n1648) );
AO22XLTS U5427 ( .A0(n4249), .A1(Data_2[21]), .B0(n4248), .B1(
FPMULT_Op_MY[21]), .Y(n1647) );
AO22XLTS U5428 ( .A0(n4249), .A1(Data_2[20]), .B0(n4223), .B1(
FPMULT_Op_MY[20]), .Y(n1646) );
AO22XLTS U5429 ( .A0(n4249), .A1(Data_2[19]), .B0(n4223), .B1(
FPMULT_Op_MY[19]), .Y(n1645) );
AO22XLTS U5430 ( .A0(n4249), .A1(Data_2[18]), .B0(n4248), .B1(
FPMULT_Op_MY[18]), .Y(n1644) );
AO22XLTS U5431 ( .A0(n4249), .A1(Data_2[17]), .B0(n4224), .B1(
FPMULT_Op_MY[17]), .Y(n1643) );
AO22XLTS U5432 ( .A0(n4249), .A1(Data_2[16]), .B0(n4224), .B1(
FPMULT_Op_MY[16]), .Y(n1642) );
AO22XLTS U5433 ( .A0(n4249), .A1(Data_2[11]), .B0(n4224), .B1(n2263), .Y(
n1637) );
AO22XLTS U5434 ( .A0(n4249), .A1(Data_2[10]), .B0(n2310), .B1(
FPMULT_Op_MY[10]), .Y(n1636) );
AO22XLTS U5435 ( .A0(n4249), .A1(Data_2[8]), .B0(n2310), .B1(FPMULT_Op_MY[8]), .Y(n1634) );
AO22XLTS U5436 ( .A0(n4249), .A1(Data_2[6]), .B0(n4248), .B1(FPMULT_Op_MY[6]), .Y(n1632) );
AO22XLTS U5437 ( .A0(n4249), .A1(Data_2[4]), .B0(n4248), .B1(FPMULT_Op_MY[4]), .Y(n1630) );
NOR4X1TS U5438 ( .A(FPMULT_Op_MY[26]), .B(FPMULT_Op_MY[25]), .C(
FPMULT_Op_MY[30]), .D(FPMULT_Op_MY[24]), .Y(n4227) );
NAND4XLTS U5439 ( .A(n4229), .B(n4228), .C(n4227), .D(n4226), .Y(n4245) );
NAND4XLTS U5440 ( .A(n4233), .B(n4232), .C(n4231), .D(n4230), .Y(n4244) );
NOR4X1TS U5441 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_Op_MX[26]), .C(
FPMULT_Op_MX[23]), .D(FPMULT_Op_MX[25]), .Y(n4235) );
NAND4XLTS U5442 ( .A(n4237), .B(n4236), .C(n4235), .D(n4234), .Y(n4243) );
NAND4XLTS U5443 ( .A(n4241), .B(n4240), .C(n4239), .D(n4238), .Y(n4242) );
OA22X1TS U5444 ( .A0(n4245), .A1(n4244), .B0(n4243), .B1(n4242), .Y(n4246)
);
OAI2BB2XLTS U5445 ( .B0(n4247), .B1(n4246), .A0N(n4247), .A1N(
FPMULT_zero_flag), .Y(n1625) );
AO22XLTS U5446 ( .A0(n4249), .A1(Data_2[31]), .B0(n4248), .B1(
FPMULT_Op_MY[31]), .Y(n1624) );
AO22XLTS U5447 ( .A0(n4296), .A1(n4709), .B0(n4299), .B1(
FPMULT_Add_result[0]), .Y(n1620) );
NOR2X1TS U5448 ( .A(FPMULT_Sgf_normalized_result[1]), .B(
FPMULT_Sgf_normalized_result[0]), .Y(n4251) );
AOI21X1TS U5449 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(
FPMULT_Sgf_normalized_result[1]), .B0(n4251), .Y(n4250) );
AOI2BB2XLTS U5450 ( .B0(n4284), .B1(n4250), .A0N(FPMULT_Add_result[1]),
.A1N(n4296), .Y(n1619) );
NAND2BXLTS U5451 ( .AN(n4251), .B(FPMULT_Sgf_normalized_result[2]), .Y(n4253) );
AOI32X1TS U5452 ( .A0(n4254), .A1(n4284), .A2(n4253), .B0(n4252), .B1(n4299),
.Y(n1618) );
OAI211XLTS U5453 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4254), .B0(
n4296), .C0(n4256), .Y(n4255) );
OAI2BB1X1TS U5454 ( .A0N(FPMULT_Add_result[3]), .A1N(n4299), .B0(n4255), .Y(
n1617) );
OA21XLTS U5455 ( .A0(n4256), .A1(n4598), .B0(n4259), .Y(n4258) );
AOI22X1TS U5456 ( .A0(n4296), .A1(n4258), .B0(n4257), .B1(n3052), .Y(n1616)
);
AOI22X1TS U5457 ( .A0(n4296), .A1(n4260), .B0(n4723), .B1(n4299), .Y(n1615)
);
AOI21X1TS U5458 ( .A0(n4600), .A1(n4262), .B0(n4261), .Y(n4263) );
AOI21X1TS U5459 ( .A0(n4265), .A1(n4264), .B0(n4267), .Y(n4266) );
OAI211XLTS U5460 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4267), .B0(
n4296), .C0(n4269), .Y(n4268) );
OAI2BB1X1TS U5461 ( .A0N(FPMULT_Add_result[9]), .A1N(n4299), .B0(n4268), .Y(
n1611) );
AOI21X1TS U5462 ( .A0(n4270), .A1(n4269), .B0(n4272), .Y(n4271) );
OAI211XLTS U5463 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4272), .B0(
n4296), .C0(n4275), .Y(n4273) );
OAI2BB1X1TS U5464 ( .A0N(FPMULT_Add_result[11]), .A1N(n4299), .B0(n4273),
.Y(n1609) );
AOI21X1TS U5465 ( .A0(n4276), .A1(n4275), .B0(n4274), .Y(n4277) );
AO22XLTS U5466 ( .A0(n4299), .A1(FPMULT_Add_result[12]), .B0(n4296), .B1(
n4277), .Y(n1608) );
AOI21X1TS U5467 ( .A0(n4618), .A1(n4279), .B0(n4278), .Y(n4280) );
AOI21X1TS U5468 ( .A0(n4634), .A1(n4282), .B0(n4281), .Y(n4283) );
AOI21X1TS U5469 ( .A0(n4286), .A1(n4285), .B0(n4288), .Y(n4287) );
OAI2BB1X1TS U5470 ( .A0N(FPMULT_Add_result[19]), .A1N(n4299), .B0(n4289),
.Y(n1601) );
AOI21X1TS U5471 ( .A0(n4690), .A1(n4290), .B0(n4292), .Y(n4291) );
OAI22X1TS U5472 ( .A0(n4296), .A1(n4295), .B0(n4294), .B1(n4293), .Y(n1599)
);
AOI221X1TS U5473 ( .A0(FPMULT_Sgf_normalized_result[23]), .A1(n4296), .B0(
FPMULT_Add_result[23]), .B1(n4299), .C0(n4298), .Y(n4297) );
AOI21X1TS U5474 ( .A0(FPMULT_Sgf_normalized_result[23]), .A1(n4298), .B0(
n4297), .Y(n1597) );
OA22X1TS U5475 ( .A0(n4302), .A1(mult_result[23]), .B0(
FPMULT_exp_oper_result[0]), .B1(n2240), .Y(n1584) );
OA22X1TS U5476 ( .A0(n4302), .A1(mult_result[24]), .B0(
FPMULT_exp_oper_result[1]), .B1(n2240), .Y(n1583) );
OA22X1TS U5477 ( .A0(n4302), .A1(mult_result[25]), .B0(
FPMULT_exp_oper_result[2]), .B1(n2240), .Y(n1582) );
OA22X1TS U5478 ( .A0(n4302), .A1(mult_result[26]), .B0(
FPMULT_exp_oper_result[3]), .B1(n2240), .Y(n1581) );
OA22X1TS U5479 ( .A0(n4302), .A1(mult_result[27]), .B0(
FPMULT_exp_oper_result[4]), .B1(n2240), .Y(n1580) );
OA22X1TS U5480 ( .A0(n4302), .A1(mult_result[28]), .B0(
FPMULT_exp_oper_result[5]), .B1(n2240), .Y(n1579) );
OA22X1TS U5481 ( .A0(n4302), .A1(mult_result[29]), .B0(
FPMULT_exp_oper_result[6]), .B1(n2240), .Y(n1578) );
OA22X1TS U5482 ( .A0(n4302), .A1(mult_result[30]), .B0(
FPMULT_exp_oper_result[7]), .B1(n2240), .Y(n1577) );
INVX2TS U5483 ( .A(n4302), .Y(n4347) );
OAI21XLTS U5484 ( .A0(n4304), .A1(underflow_flag_mult), .B0(n4303), .Y(n4305) );
OAI2BB1X1TS U5485 ( .A0N(mult_result[31]), .A1N(n4346), .B0(n4305), .Y(n1576) );
OAI2BB1X1TS U5486 ( .A0N(FPMULT_P_Sgf[45]), .A1N(n4343), .B0(n4308), .Y(
n1574) );
OAI2BB1X1TS U5487 ( .A0N(FPMULT_P_Sgf[43]), .A1N(n4333), .B0(n4311), .Y(
n1572) );
OAI2BB1X1TS U5488 ( .A0N(FPMULT_P_Sgf[41]), .A1N(n4333), .B0(n4314), .Y(
n1570) );
OAI2BB1X1TS U5489 ( .A0N(FPMULT_P_Sgf[39]), .A1N(n4343), .B0(n4317), .Y(
n1568) );
AOI21X1TS U5490 ( .A0(n4320), .A1(n4319), .B0(n4318), .Y(n4325) );
OA22X1TS U5491 ( .A0(FPMULT_P_Sgf[27]), .A1(n4342), .B0(n4325), .B1(n4324),
.Y(n1556) );
XNOR2X1TS U5492 ( .A(intadd_499_SUM_9_), .B(n4326), .Y(n4327) );
XNOR2X1TS U5493 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[21]), .B(n4327), .Y(
n4328) );
AO22XLTS U5494 ( .A0(n4343), .A1(FPMULT_P_Sgf[21]), .B0(n4344), .B1(n4328),
.Y(n1550) );
XNOR2X1TS U5495 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[16]), .B(n4331), .Y(
n4332) );
AO22XLTS U5496 ( .A0(n4333), .A1(FPMULT_P_Sgf[16]), .B0(n4342), .B1(n4332),
.Y(n1545) );
XNOR2X1TS U5497 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[15]), .B(n4336), .Y(
n4337) );
AO22XLTS U5498 ( .A0(n4333), .A1(FPMULT_P_Sgf[15]), .B0(n4342), .B1(n4337),
.Y(n1544) );
XNOR2X1TS U5499 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[14]), .B(n4340), .Y(
n4341) );
AO22XLTS U5500 ( .A0(n4343), .A1(FPMULT_P_Sgf[14]), .B0(n4342), .B1(n4341),
.Y(n1543) );
AO22XLTS U5501 ( .A0(n4342), .A1(FPMULT_Sgf_operation_Result[11]), .B0(n4333), .B1(FPMULT_P_Sgf[11]), .Y(n1540) );
AO22XLTS U5502 ( .A0(n4342), .A1(FPMULT_Sgf_operation_Result[8]), .B0(n4343),
.B1(FPMULT_P_Sgf[8]), .Y(n1537) );
OAI2BB2XLTS U5503 ( .B0(n4709), .B1(n2240), .A0N(mult_result[0]), .A1N(n4346), .Y(n1504) );
AO22XLTS U5504 ( .A0(FPMULT_Sgf_normalized_result[1]), .A1(n2241), .B0(
mult_result[1]), .B1(n4347), .Y(n1503) );
AO22XLTS U5505 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n2241), .B0(
mult_result[2]), .B1(n4347), .Y(n1502) );
AO22XLTS U5506 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n2241), .B0(
mult_result[3]), .B1(n4347), .Y(n1501) );
AO22XLTS U5507 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n2241), .B0(
mult_result[4]), .B1(n4347), .Y(n1500) );
AO22XLTS U5508 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4348), .B0(
mult_result[5]), .B1(n4347), .Y(n1499) );
AO22XLTS U5509 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n4348), .B0(
mult_result[6]), .B1(n4347), .Y(n1498) );
AO22XLTS U5510 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4348), .B0(
mult_result[7]), .B1(n4346), .Y(n1497) );
AO22XLTS U5511 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n4348), .B0(
mult_result[8]), .B1(n4346), .Y(n1496) );
AO22XLTS U5512 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4348), .B0(
mult_result[9]), .B1(n4346), .Y(n1495) );
AO22XLTS U5513 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n4348), .B0(
mult_result[10]), .B1(n4346), .Y(n1494) );
AO22XLTS U5514 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4348), .B0(
mult_result[11]), .B1(n4346), .Y(n1493) );
AO22XLTS U5515 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n4348), .B0(
mult_result[12]), .B1(n4346), .Y(n1492) );
AO22XLTS U5516 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4348), .B0(
mult_result[13]), .B1(n4346), .Y(n1491) );
AO22XLTS U5517 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n4348), .B0(
mult_result[14]), .B1(n4346), .Y(n1490) );
AO22XLTS U5518 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4348), .B0(
mult_result[15]), .B1(n4346), .Y(n1489) );
AO22XLTS U5519 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n4348), .B0(
mult_result[16]), .B1(n4346), .Y(n1488) );
AO22XLTS U5520 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4348), .B0(
mult_result[17]), .B1(n4346), .Y(n1487) );
AO22XLTS U5521 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n4348), .B0(
mult_result[18]), .B1(n4346), .Y(n1486) );
AO22XLTS U5522 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4348), .B0(
mult_result[19]), .B1(n4346), .Y(n1485) );
AO22XLTS U5523 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n4348), .B0(
mult_result[20]), .B1(n4346), .Y(n1484) );
AO22XLTS U5524 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n4348), .B0(
mult_result[21]), .B1(n4346), .Y(n1483) );
AO22XLTS U5525 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n4348), .B0(
mult_result[22]), .B1(n4346), .Y(n1481) );
OAI21XLTS U5526 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n4698), .B0(
intadd_500_CI), .Y(n4349) );
AO22XLTS U5527 ( .A0(n4359), .A1(n4349), .B0(n4421), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1475) );
BUFX3TS U5528 ( .A(n4451), .Y(n4479) );
AO22XLTS U5529 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n4479),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1456) );
CLKBUFX2TS U5530 ( .A(n4506), .Y(n4520) );
INVX4TS U5531 ( .A(n4520), .Y(n4507) );
AO22XLTS U5532 ( .A0(n4506), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n4507),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1455) );
AO22XLTS U5533 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[23]), .B0(n4585), .B1(FPADDSUB_DMP_exp_NRM_EW[0]),
.Y(n1454) );
AO22XLTS U5534 ( .A0(n4359), .A1(FPADDSUB_DMP_EXP_EWSW[24]), .B0(n4421),
.B1(FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1452) );
AO22XLTS U5535 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n4451),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1451) );
BUFX3TS U5536 ( .A(n4506), .Y(n4474) );
INVX4TS U5537 ( .A(n4520), .Y(n4473) );
AO22XLTS U5538 ( .A0(n4474), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n4473),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1450) );
AO22XLTS U5539 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[24]), .B0(n4585), .B1(FPADDSUB_DMP_exp_NRM_EW[1]),
.Y(n1449) );
AO22XLTS U5540 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n4451),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1446) );
AO22XLTS U5541 ( .A0(n4474), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n4507),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1445) );
AO22XLTS U5542 ( .A0(n4468), .A1(FPADDSUB_DMP_SFG[25]), .B0(n4424), .B1(
FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1444) );
AO22XLTS U5543 ( .A0(n4359), .A1(FPADDSUB_DMP_EXP_EWSW[26]), .B0(n4421),
.B1(FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1442) );
AO22XLTS U5544 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n4451),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1441) );
AO22XLTS U5545 ( .A0(n4474), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n4473),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1440) );
AO22XLTS U5546 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[26]), .B0(n4424), .B1(FPADDSUB_DMP_exp_NRM_EW[3]),
.Y(n1439) );
AO22XLTS U5547 ( .A0(n4359), .A1(FPADDSUB_DMP_EXP_EWSW[27]), .B0(n4421),
.B1(FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1437) );
AO22XLTS U5548 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n4451),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1436) );
INVX4TS U5549 ( .A(n4520), .Y(n4528) );
AO22XLTS U5550 ( .A0(n4474), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n4528),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1435) );
AO22XLTS U5551 ( .A0(n4468), .A1(FPADDSUB_DMP_SFG[27]), .B0(n4424), .B1(
FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1434) );
AO22XLTS U5552 ( .A0(n4359), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n4421),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1432) );
AO22XLTS U5553 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n4451),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1431) );
AO22XLTS U5554 ( .A0(n4474), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n4507),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1430) );
AO22XLTS U5555 ( .A0(n4468), .A1(FPADDSUB_DMP_SFG[28]), .B0(n4424), .B1(
FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1429) );
AO22XLTS U5556 ( .A0(n4359), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n4421),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1427) );
AO22XLTS U5557 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n4451),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1426) );
AO22XLTS U5558 ( .A0(n4474), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n4473),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1425) );
AO22XLTS U5559 ( .A0(n4468), .A1(FPADDSUB_DMP_SFG[29]), .B0(n4424), .B1(
FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1424) );
AO22XLTS U5560 ( .A0(n4359), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n4421),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1422) );
AO22XLTS U5561 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n4451),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1421) );
AO22XLTS U5562 ( .A0(n4474), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n4528),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1420) );
AO22XLTS U5563 ( .A0(n4468), .A1(FPADDSUB_DMP_SFG[30]), .B0(n4424), .B1(
FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1419) );
AOI2BB1XLTS U5564 ( .A0N(n4351), .A1N(underflow_flag_addsubt), .B0(n4350),
.Y(n1412) );
AOI21X1TS U5565 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[22]), .B0(n4352), .Y(n4453) );
NOR2X1TS U5566 ( .A(n4453), .B(n4459), .Y(n4452) );
OAI21X1TS U5567 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(
FPADDSUB_DMP_SFG[22]), .B0(n4461), .Y(n4422) );
NAND2X1TS U5568 ( .A(FPADDSUB_DmP_mant_SFG_SWR[24]), .B(FPADDSUB_DMP_SFG[22]), .Y(n4463) );
OAI221X1TS U5569 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n4422), .B0(n4445), .B1(
FPADDSUB_DMP_SFG[22]), .C0(n4463), .Y(n4356) );
NAND2X1TS U5570 ( .A(FPADDSUB_DmP_mant_SFG_SWR[23]), .B(n4656), .Y(n4354) );
OAI211X1TS U5571 ( .A0(n4355), .A1(n4457), .B0(FPADDSUB_OP_FLAG_SFG), .C0(
n4354), .Y(n4460) );
AOI32X1TS U5572 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n4356), .A2(n4695),
.B0(n4460), .B1(n4356), .Y(n4357) );
XNOR2X1TS U5573 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .B(n4357), .Y(n4358) );
AOI22X1TS U5574 ( .A0(n4468), .A1(n4358), .B0(n4632), .B1(n4585), .Y(n1410)
);
AO22XLTS U5575 ( .A0(n4475), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n4421),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1406) );
AO22XLTS U5576 ( .A0(n4478), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(n4477),
.B1(FPADDSUB_DmP_EXP_EWSW[15]), .Y(n1403) );
AO22XLTS U5577 ( .A0(n4478), .A1(FPADDSUB_DmP_mant_SHT1_SW[18]), .B0(n4359),
.B1(FPADDSUB_DmP_EXP_EWSW[18]), .Y(n1400) );
AO22XLTS U5578 ( .A0(n4359), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n4421),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1397) );
AO22XLTS U5579 ( .A0(n4359), .A1(FPADDSUB_DmP_EXP_EWSW[19]), .B0(n4421),
.B1(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1394) );
AO22XLTS U5580 ( .A0(n4475), .A1(FPADDSUB_DmP_EXP_EWSW[20]), .B0(n4421),
.B1(FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1391) );
AO22XLTS U5581 ( .A0(n4478), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(n4477),
.B1(FPADDSUB_DmP_EXP_EWSW[17]), .Y(n1388) );
AO22XLTS U5582 ( .A0(n4478), .A1(FPADDSUB_DmP_mant_SHT1_SW[4]), .B0(n4477),
.B1(FPADDSUB_DmP_EXP_EWSW[4]), .Y(n1385) );
AO22XLTS U5583 ( .A0(n4478), .A1(FPADDSUB_DmP_mant_SHT1_SW[6]), .B0(n4477),
.B1(FPADDSUB_DmP_EXP_EWSW[6]), .Y(n1382) );
AOI21X1TS U5584 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n4481), .B0(n2254),
.Y(n4361) );
AOI22X1TS U5585 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n3274), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n3275), .Y(n4360) );
OAI211X1TS U5586 ( .A0(n4683), .A1(n4362), .B0(n4361), .C0(n4360), .Y(n4366)
);
NOR2X1TS U5587 ( .A(n2254), .B(n4363), .Y(n4378) );
AOI22X1TS U5588 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n3275), .B0(
FPADDSUB_Data_array_SWR[23]), .B1(n3273), .Y(n4364) );
OAI211X1TS U5589 ( .A0(n4686), .A1(n4379), .B0(n4378), .C0(n4364), .Y(n4367)
);
AOI22X1TS U5590 ( .A0(n4490), .A1(n4366), .B0(n4367), .B1(n4522), .Y(n4509)
);
INVX2TS U5591 ( .A(n4365), .Y(n4471) );
OAI22X1TS U5592 ( .A0(n4829), .A1(n4645), .B0(n4509), .B1(n4471), .Y(n1381)
);
AO22XLTS U5593 ( .A0(n4475), .A1(FPADDSUB_DmP_EXP_EWSW[13]), .B0(n4421),
.B1(FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1379) );
AO22XLTS U5594 ( .A0(n4475), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n4421),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1376) );
AOI22X1TS U5595 ( .A0(n4490), .A1(n4367), .B0(n4366), .B1(n4522), .Y(n4502)
);
OAI22X1TS U5596 ( .A0(n4829), .A1(n4657), .B0(n4502), .B1(n4471), .Y(n1375)
);
AO22XLTS U5597 ( .A0(n4475), .A1(FPADDSUB_DmP_EXP_EWSW[8]), .B0(n4421), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1373) );
AOI22X1TS U5598 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n3273), .B0(
FPADDSUB_Data_array_SWR[16]), .B1(n4481), .Y(n4369) );
AOI22X1TS U5599 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n3275), .B0(
FPADDSUB_Data_array_SWR[24]), .B1(n3274), .Y(n4368) );
NAND2X1TS U5600 ( .A(n4369), .B(n4368), .Y(n4372) );
AOI22X1TS U5601 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n3273), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n3275), .Y(n4371) );
AOI22X1TS U5602 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n4481), .B0(
FPADDSUB_Data_array_SWR[25]), .B1(n3274), .Y(n4370) );
NAND2X1TS U5603 ( .A(n4371), .B(n4370), .Y(n4373) );
AOI221X1TS U5604 ( .A0(n4490), .A1(n4372), .B0(n4522), .B1(n4373), .C0(n2254), .Y(n4505) );
OAI22X1TS U5605 ( .A0(n4829), .A1(n4658), .B0(n4505), .B1(n4471), .Y(n1372)
);
AO22XLTS U5606 ( .A0(n4478), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n4477),
.B1(FPADDSUB_DmP_EXP_EWSW[11]), .Y(n1370) );
AO22XLTS U5607 ( .A0(n4475), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n4421),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1367) );
AOI221X1TS U5608 ( .A0(n4490), .A1(n4373), .B0(n4522), .B1(n4372), .C0(n2254), .Y(n4504) );
OAI22X1TS U5609 ( .A0(n4829), .A1(n4646), .B0(n4504), .B1(n4471), .Y(n1366)
);
AO22XLTS U5610 ( .A0(n4478), .A1(FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(n4477),
.B1(FPADDSUB_DmP_EXP_EWSW[10]), .Y(n1364) );
INVX2TS U5611 ( .A(n3275), .Y(n4376) );
AOI21X1TS U5612 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n3273), .B0(n2254),
.Y(n4375) );
AOI22X1TS U5613 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n4481), .B0(
FPADDSUB_Data_array_SWR[23]), .B1(n3274), .Y(n4374) );
OAI211X1TS U5614 ( .A0(n2233), .A1(n4376), .B0(n4375), .C0(n4374), .Y(n4469)
);
AOI22X1TS U5615 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n3273), .B0(
FPADDSUB_Data_array_SWR[14]), .B1(n3275), .Y(n4377) );
OAI211X1TS U5616 ( .A0(n4683), .A1(n4379), .B0(n4378), .C0(n4377), .Y(n4470)
);
AOI22X1TS U5617 ( .A0(n4490), .A1(n4469), .B0(n4470), .B1(n4522), .Y(n4508)
);
OAI22X1TS U5618 ( .A0(n4829), .A1(n4647), .B0(n4508), .B1(n4471), .Y(n1363)
);
AOI22X1TS U5619 ( .A0(n4666), .A1(FPADDSUB_intDY_EWSW[13]), .B0(n4579), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n4380) );
AOI22X1TS U5620 ( .A0(n4674), .A1(FPADDSUB_intDY_EWSW[20]), .B0(n4675), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n4381) );
AOI22X1TS U5621 ( .A0(n4673), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n4677), .B1(
FPADDSUB_intDY_EWSW[12]), .Y(n4382) );
AOI22X1TS U5622 ( .A0(n4685), .A1(FPADDSUB_intDY_EWSW[29]), .B0(n4580), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n4383) );
OAI221XLTS U5623 ( .A0(n4685), .A1(FPADDSUB_intDY_EWSW[29]), .B0(n4580),
.B1(FPADDSUB_intDY_EWSW[0]), .C0(n4383), .Y(n4384) );
NOR4X1TS U5624 ( .A(n4387), .B(n4386), .C(n4385), .D(n4384), .Y(n4416) );
AOI22X1TS U5625 ( .A0(n4672), .A1(FPADDSUB_intDY_EWSW[11]), .B0(n4569), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n4388) );
AOI22X1TS U5626 ( .A0(n4570), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n4680), .B1(
FPADDSUB_intDY_EWSW[17]), .Y(n4389) );
OAI221XLTS U5627 ( .A0(n4570), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n4680),
.B1(FPADDSUB_intDY_EWSW[17]), .C0(n4389), .Y(n4394) );
AOI22X1TS U5628 ( .A0(n4577), .A1(FPADDSUB_intDY_EWSW[27]), .B0(n4681), .B1(
FPADDSUB_intDY_EWSW[22]), .Y(n4390) );
AOI22X1TS U5629 ( .A0(n4668), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n4678), .B1(
FPADDSUB_intDY_EWSW[10]), .Y(n4391) );
OAI221XLTS U5630 ( .A0(n4668), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n4678),
.B1(FPADDSUB_intDY_EWSW[10]), .C0(n4391), .Y(n4392) );
NOR4X1TS U5631 ( .A(n4395), .B(n4394), .C(n4393), .D(n4392), .Y(n4415) );
AOI22X1TS U5632 ( .A0(n4578), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n4676), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n4396) );
OAI221XLTS U5633 ( .A0(n4578), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n4676),
.B1(FPADDSUB_intDY_EWSW[2]), .C0(n4396), .Y(n4412) );
AOI22X1TS U5634 ( .A0(n4581), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n4679), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n4397) );
OAI221XLTS U5635 ( .A0(n4581), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n4679),
.B1(FPADDSUB_intDY_EWSW[8]), .C0(n4397), .Y(n4411) );
OAI22X1TS U5636 ( .A0(n4575), .A1(FPADDSUB_intDY_EWSW[4]), .B0(n4667), .B1(
FPADDSUB_intDY_EWSW[24]), .Y(n4398) );
OAI22X1TS U5637 ( .A0(n4574), .A1(FPADDSUB_intDY_EWSW[9]), .B0(n4682), .B1(
FPADDSUB_intDY_EWSW[30]), .Y(n4400) );
OAI22X1TS U5638 ( .A0(n4568), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n4670), .B1(
FPADDSUB_intDY_EWSW[19]), .Y(n4401) );
AOI221X1TS U5639 ( .A0(n4568), .A1(FPADDSUB_intDY_EWSW[15]), .B0(
FPADDSUB_intDY_EWSW[19]), .B1(n4670), .C0(n4401), .Y(n4407) );
OAI22X1TS U5640 ( .A0(n4671), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n4573), .B1(
FPADDSUB_intDY_EWSW[14]), .Y(n4402) );
AOI221X1TS U5641 ( .A0(n4671), .A1(FPADDSUB_intDY_EWSW[1]), .B0(
FPADDSUB_intDY_EWSW[14]), .B1(n4573), .C0(n4402), .Y(n4406) );
OAI22X1TS U5642 ( .A0(n4665), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n4684), .B1(
FPADDSUB_intDY_EWSW[28]), .Y(n4403) );
NAND4XLTS U5643 ( .A(n4408), .B(n4407), .C(n4406), .D(n4405), .Y(n4409) );
NOR4X1TS U5644 ( .A(n4409), .B(n4411), .C(n4410), .D(n4412), .Y(n4414) );
AOI31XLTS U5645 ( .A0(n4416), .A1(n4415), .A2(n4414), .B0(n4413), .Y(n4417)
);
AOI2BB1XLTS U5646 ( .A0N(n3225), .A1N(n4420), .B0(n4419), .Y(n1362) );
AO22XLTS U5647 ( .A0(n4475), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n4421), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1361) );
AO22XLTS U5648 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n4451), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1360) );
AO22XLTS U5649 ( .A0(n4474), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n4507), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1359) );
AO22XLTS U5650 ( .A0(n4468), .A1(FPADDSUB_SIGN_FLAG_SFG), .B0(n4424), .B1(
FPADDSUB_SIGN_FLAG_NRM), .Y(n1358) );
AO22XLTS U5651 ( .A0(busy), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n4451), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1353) );
BUFX4TS U5652 ( .A(n4474), .Y(n4510) );
AO22XLTS U5653 ( .A0(n4473), .A1(FPADDSUB_OP_FLAG_SFG), .B0(n4510), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1352) );
OA22X1TS U5654 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(
FPADDSUB_Shift_reg_FLAGS_7[2]), .B0(n4424), .B1(
FPADDSUB_DmP_mant_SFG_SWR[0]), .Y(n1349) );
NAND2X1TS U5655 ( .A(FPADDSUB_OP_FLAG_SFG), .B(FPADDSUB_DmP_mant_SFG_SWR[0]),
.Y(n4425) );
AOI22X1TS U5656 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(n4426), .B0(n4541),
.B1(n4585), .Y(n1348) );
NOR2BX1TS U5657 ( .AN(n4428), .B(n4427), .Y(n4430) );
OAI21XLTS U5658 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[1]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[0]), .B0(FPADDSUB_OP_FLAG_SFG), .Y(n4429) );
XNOR2X1TS U5659 ( .A(n4430), .B(n4429), .Y(n4431) );
AOI22X1TS U5660 ( .A0(n4468), .A1(n4431), .B0(n4642), .B1(n4585), .Y(n1347)
);
OAI21XLTS U5661 ( .A0(n4594), .A1(n4552), .B0(n4432), .Y(n4436) );
AOI22X1TS U5662 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n4434), .B0(n4433), .B1(
n4445), .Y(n4435) );
XNOR2X1TS U5663 ( .A(n4436), .B(n4435), .Y(n4437) );
AOI22X1TS U5664 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(n4437), .B0(n4545),
.B1(n4585), .Y(n1343) );
AOI22X1TS U5665 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n4440), .B0(n4439), .B1(
n4445), .Y(n4442) );
XNOR2X1TS U5666 ( .A(n4442), .B(n4441), .Y(n4443) );
AOI22X1TS U5667 ( .A0(n4468), .A1(n4443), .B0(n4626), .B1(n4585), .Y(n1336)
);
OAI21XLTS U5668 ( .A0(n4604), .A1(n4540), .B0(n4447), .Y(n4448) );
XNOR2X1TS U5669 ( .A(n4449), .B(n4448), .Y(n4450) );
AOI22X1TS U5670 ( .A0(n4468), .A1(n4450), .B0(n4696), .B1(n4585), .Y(n1334)
);
AO22XLTS U5671 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(n4451), .B1(
FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1324) );
AO22XLTS U5672 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[3]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1323) );
AOI21X1TS U5673 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(n4585), .B0(n4454),
.Y(n4458) );
AOI32X1TS U5674 ( .A0(n4459), .A1(n4458), .A2(n4457), .B0(n4456), .B1(n4458),
.Y(n1316) );
XNOR2X1TS U5675 ( .A(n4465), .B(n4464), .Y(n4467) );
AOI22X1TS U5676 ( .A0(n4468), .A1(n4467), .B0(n4700), .B1(n4585), .Y(n1315)
);
AO22XLTS U5677 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(n4725), .B1(
FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1308) );
AO22XLTS U5678 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[2]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1307) );
AO22XLTS U5679 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(n4725), .B1(
FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1301) );
AO22XLTS U5680 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[7]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1300) );
AO22XLTS U5681 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(n4725), .B1(
FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1294) );
AO22XLTS U5682 ( .A0(n4478), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(n4477),
.B1(FPADDSUB_DmP_EXP_EWSW[1]), .Y(n1290) );
AO22XLTS U5683 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(n4725), .B1(
FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1287) );
AO22XLTS U5684 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[1]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1286) );
AOI22X1TS U5685 ( .A0(n4490), .A1(n4470), .B0(n4469), .B1(n4522), .Y(n4503)
);
OAI22X1TS U5686 ( .A0(n4829), .A1(n4659), .B0(n4503), .B1(n4471), .Y(n1285)
);
AO22XLTS U5687 ( .A0(n4478), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(n4477),
.B1(FPADDSUB_DmP_EXP_EWSW[9]), .Y(n1283) );
AO22XLTS U5688 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[9]), .B0(n4587), .B1(FPADDSUB_DMP_SHT1_EWSW[9]),
.Y(n1281) );
AO22XLTS U5689 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n4725), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1280) );
AO22XLTS U5690 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[9]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1279) );
AO22XLTS U5691 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[5]), .B0(n4587), .B1(FPADDSUB_DMP_SHT1_EWSW[5]),
.Y(n1274) );
AO22XLTS U5692 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(n4725), .B1(
FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1273) );
AO22XLTS U5693 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[5]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1272) );
AO22XLTS U5694 ( .A0(n4478), .A1(FPADDSUB_DmP_mant_SHT1_SW[12]), .B0(n4477),
.B1(FPADDSUB_DmP_EXP_EWSW[12]), .Y(n1270) );
AO22XLTS U5695 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n4725),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1267) );
AO22XLTS U5696 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[12]), .B0(n4474), .B1(
FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1266) );
AO22XLTS U5697 ( .A0(n4475), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n4587),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1264) );
AO22XLTS U5698 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n4725),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1263) );
AO22XLTS U5699 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[10]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1262) );
AO22XLTS U5700 ( .A0(n4475), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n4587),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1260) );
AO22XLTS U5701 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n4725),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1259) );
AO22XLTS U5702 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[14]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1258) );
AO22XLTS U5703 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[11]), .B0(n4587), .B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1256) );
AO22XLTS U5704 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n4725),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1255) );
AO22XLTS U5705 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[11]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1254) );
AO22XLTS U5706 ( .A0(n4477), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n4587), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1252) );
AO22XLTS U5707 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n4725),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1251) );
AO22XLTS U5708 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[8]), .B0(n4474), .B1(
FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1250) );
AO22XLTS U5709 ( .A0(n4475), .A1(FPADDSUB_DMP_EXP_EWSW[16]), .B0(n4478),
.B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1248) );
AO22XLTS U5710 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n4479),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1247) );
AO22XLTS U5711 ( .A0(n4473), .A1(FPADDSUB_DMP_SFG[16]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1246) );
AO22XLTS U5712 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n4479),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1243) );
AO22XLTS U5713 ( .A0(n4507), .A1(FPADDSUB_DMP_SFG[13]), .B0(n4474), .B1(
FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1242) );
AO22XLTS U5714 ( .A0(n4475), .A1(FPADDSUB_DMP_EXP_EWSW[6]), .B0(n4478), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1240) );
AO22XLTS U5715 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(n4479),
.B1(FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1239) );
AO22XLTS U5716 ( .A0(n4507), .A1(FPADDSUB_DMP_SFG[6]), .B0(n4506), .B1(
FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1238) );
AO22XLTS U5717 ( .A0(n4475), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n4587), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1236) );
AO22XLTS U5718 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(n4479), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1235) );
AO22XLTS U5719 ( .A0(n4507), .A1(FPADDSUB_DMP_SFG[4]), .B0(n4506), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1234) );
AO22XLTS U5720 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[17]), .B0(n4478), .B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1232) );
AO22XLTS U5721 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n4479),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1231) );
AO22XLTS U5722 ( .A0(n4507), .A1(FPADDSUB_DMP_SFG[17]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1230) );
AO22XLTS U5723 ( .A0(n4477), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n4587),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1228) );
AO22XLTS U5724 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n4479),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1227) );
AO22XLTS U5725 ( .A0(n4507), .A1(FPADDSUB_DMP_SFG[20]), .B0(n4506), .B1(
FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1226) );
AO22XLTS U5726 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[19]), .B0(n4478), .B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1224) );
AO22XLTS U5727 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n4479),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1223) );
AO22XLTS U5728 ( .A0(n4507), .A1(FPADDSUB_DMP_SFG[19]), .B0(n4506), .B1(
FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1222) );
AO22XLTS U5729 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[21]), .B0(n4587), .B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1220) );
AO22XLTS U5730 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n4479),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1219) );
AO22XLTS U5731 ( .A0(n4507), .A1(FPADDSUB_DMP_SFG[21]), .B0(n4506), .B1(
FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1218) );
AO22XLTS U5732 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[18]), .B0(n4478), .B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1216) );
AO22XLTS U5733 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n4479),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1215) );
AO22XLTS U5734 ( .A0(n4507), .A1(FPADDSUB_DMP_SFG[18]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1214) );
AO22XLTS U5735 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[15]), .B0(n4587), .B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1212) );
AO22XLTS U5736 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n4479),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1211) );
AO22XLTS U5737 ( .A0(n4507), .A1(FPADDSUB_DMP_SFG[15]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1210) );
AO22XLTS U5738 ( .A0(n4480), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n4479),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1207) );
AO22XLTS U5739 ( .A0(n4507), .A1(FPADDSUB_DMP_SFG[22]), .B0(n4510), .B1(
FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1206) );
OAI22X1TS U5740 ( .A0(n4484), .A1(n2194), .B0(n4697), .B1(n4482), .Y(n4485)
);
OAI22X1TS U5741 ( .A0(n4490), .A1(n4523), .B0(n4525), .B1(n3329), .Y(n4488)
);
NAND2X2TS U5742 ( .A(n4506), .B(n4487), .Y(n4501) );
OA22X1TS U5743 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[0]), .A1(n4506), .B0(n4488),
.B1(n4501), .Y(n1205) );
OAI22X1TS U5744 ( .A0(n4491), .A1(n3329), .B0(n4490), .B1(n4489), .Y(n4492)
);
OA22X1TS U5745 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[1]), .A1(n4506), .B0(n4492),
.B1(n4501), .Y(n1204) );
AOI2BB2XLTS U5746 ( .B0(n4588), .B1(n4528), .A0N(n4501), .A1N(n4493), .Y(
n1203) );
OA22X1TS U5747 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n4506), .B0(n4501),
.B1(n4494), .Y(n1202) );
OA22X1TS U5748 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(n4506), .B0(n4501),
.B1(n4495), .Y(n1201) );
AOI2BB2XLTS U5749 ( .B0(n4551), .B1(n4528), .A0N(n4501), .A1N(n4496), .Y(
n1200) );
AOI2BB2XLTS U5750 ( .B0(n4552), .B1(n4528), .A0N(n4501), .A1N(n4497), .Y(
n1199) );
OA22X1TS U5751 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n4506), .B0(n4501),
.B1(n4498), .Y(n1198) );
OA22X1TS U5752 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(n4506), .B0(n4501),
.B1(n4499), .Y(n1197) );
OA22X1TS U5753 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n4506), .B0(n4500),
.B1(n4501), .Y(n1196) );
AOI22X1TS U5754 ( .A0(n4510), .A1(n4502), .B0(n4596), .B1(n4507), .Y(n1195)
);
AOI22X1TS U5755 ( .A0(n4510), .A1(n4503), .B0(n4597), .B1(n4507), .Y(n1194)
);
AOI22X1TS U5756 ( .A0(n4506), .A1(n4504), .B0(n4599), .B1(n4528), .Y(n1193)
);
AOI22X1TS U5757 ( .A0(n4506), .A1(n4505), .B0(n2298), .B1(n4528), .Y(n1192)
);
AOI22X1TS U5758 ( .A0(n4510), .A1(n4508), .B0(n4539), .B1(n4507), .Y(n1191)
);
AOI22X1TS U5759 ( .A0(n4510), .A1(n4509), .B0(n4540), .B1(n4528), .Y(n1190)
);
NAND2X2TS U5760 ( .A(n4520), .B(n4511), .Y(n4526) );
AOI2BB2XLTS U5761 ( .B0(n4603), .B1(n4528), .A0N(n4526), .A1N(n4512), .Y(
n1189) );
AOI2BB2XLTS U5762 ( .B0(n4605), .B1(n4528), .A0N(n4526), .A1N(n4513), .Y(
n1188) );
AOI2BB2XLTS U5763 ( .B0(n4606), .B1(n4528), .A0N(n4526), .A1N(n4514), .Y(
n1187) );
AOI2BB2XLTS U5764 ( .B0(n4607), .B1(n4528), .A0N(n4526), .A1N(n4515), .Y(
n1186) );
AOI2BB2XLTS U5765 ( .B0(n4621), .B1(n4528), .A0N(n4526), .A1N(n4516), .Y(
n1185) );
AOI2BB2XLTS U5766 ( .B0(n4561), .B1(n4528), .A0N(n4526), .A1N(n4517), .Y(
n1184) );
OA22X1TS U5767 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(n4506), .B0(n4526),
.B1(n4518), .Y(n1183) );
OA22X1TS U5768 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[23]), .A1(n4520), .B0(n4526),
.B1(n4519), .Y(n1182) );
OA22X1TS U5769 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n4506), .B0(n4526),
.B1(n4521), .Y(n1181) );
OAI22X1TS U5770 ( .A0(n4525), .A1(n3279), .B0(n4523), .B1(n4522), .Y(n4527)
);
AOI2BB2XLTS U5771 ( .B0(n4724), .B1(n4528), .A0N(n4527), .A1N(n4526), .Y(
n1180) );
endmodule
|
module premuat1_8(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [15:0] i_0;
input signed [15:0] i_1;
input signed [15:0] i_2;
input signed [15:0] i_3;
input signed [15:0] i_4;
input signed [15:0] i_5;
input signed [15:0] i_6;
input signed [15:0] i_7;
output signed [15:0] o_0;
output signed [15:0] o_1;
output signed [15:0] o_2;
output signed [15:0] o_3;
output signed [15:0] o_4;
output signed [15:0] o_5;
output signed [15:0] o_6;
output signed [15:0] o_7;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [15:0] o1;
reg signed [15:0] o2;
reg signed [15:0] o3;
reg signed [15:0] o4;
reg signed [15:0] o5;
reg signed [15:0] o6;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1=i_2;
o2=i_4;
o3=i_6;
o4=i_1;
o5=i_3;
o6=i_5;
end
else
begin
o1=i_4;
o2=i_1;
o3=i_5;
o4=i_2;
o5=i_6;
o6=i_3;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=i_7;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A32O_FUNCTIONAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a32o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 and0_out ;
wire B1 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_FUNCTIONAL_V |
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 15.0.2 Build 153 07/15/2015 SJ Web Edition"
// CREATED "Sun Oct 25 12:01:05 2015"
module vga_export(
CLOCK_50,
KEY,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HSYNC,
VGA_VSYNC
);
input wire CLOCK_50;
input wire [0:0] KEY;
output wire VGA_RED;
output wire VGA_GREEN;
output wire VGA_BLUE;
output wire VGA_HSYNC;
output wire VGA_VSYNC;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire [15:0] SYNTHESIZED_WIRE_4;
wire [10:0] SYNTHESIZED_WIRE_5;
wire [10:0] SYNTHESIZED_WIRE_6;
wire [15:0] SYNTHESIZED_WIRE_7;
vga_bw b2v_inst(
.CLOCK_PIXEL(SYNTHESIZED_WIRE_0),
.RESET(SYNTHESIZED_WIRE_9),
.PIXEL(SYNTHESIZED_WIRE_2),
.VGA_RED(VGA_RED),
.VGA_GREEN(VGA_GREEN),
.VGA_BLUE(VGA_BLUE),
.VGA_HS(VGA_HSYNC),
.VGA_VS(VGA_VSYNC),
.PIXEL_H(SYNTHESIZED_WIRE_5),
.PIXEL_V(SYNTHESIZED_WIRE_6));
frame_buffer b2v_inst1(
.clk(CLOCK_50),
.load(SYNTHESIZED_WIRE_3),
.data_in(SYNTHESIZED_WIRE_4),
.vga_h(SYNTHESIZED_WIRE_5),
.vga_v(SYNTHESIZED_WIRE_6),
.write_address(SYNTHESIZED_WIRE_7),
.pixel_out(SYNTHESIZED_WIRE_2));
image_generator b2v_inst5(
.clk(CLOCK_50),
.reset(SYNTHESIZED_WIRE_9),
.load(SYNTHESIZED_WIRE_3),
.address(SYNTHESIZED_WIRE_7),
.out(SYNTHESIZED_WIRE_4));
clock_25 b2v_pixel_clock_25(
.CLOCK_50(CLOCK_50),
.CLOCK_25(SYNTHESIZED_WIRE_0));
assign SYNTHESIZED_WIRE_9 = ~KEY;
endmodule |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_cfg_fe1_clk_a
//
// Generated
// by: lutscher
// on: Wed Dec 14 16:43:30 2005
// cmd: /home/lutscher/work/MIX/mix_0.pl -strip -nodelta ../../reg_shell.sxc
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: lutscher $
// $Id: rs_cfg_fe1_clk_a.v,v 1.8 2005/12/14 15:43:55 lutscher Exp $
// $Date: 2005/12/14 15:43:55 $
// $Log: rs_cfg_fe1_clk_a.v,v $
// Revision 1.8 2005/12/14 15:43:55 lutscher
// updated
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.43 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_cfg_fe1_clk_a
//
// No user `defines in this module
`define tie0_1_c 1'b0
module rs_cfg_fe1_clk_a
//
// Generated module rs_cfg_fe1_clk_a_i
//
(
input wire clk_a,
input wire res_a_n_i,
input wire test_i,
input wire [13:0] addr_i,
input wire trans_start,
input wire [31:0] wr_data_i,
input wire rd_wr_i,
output wire [31:0] rd_data_o,
output wire rd_err_o,
output wire trans_done_o,
output wire [3:0] dgatel_par_o,
output wire [4:0] dgates_par_o,
output wire [2:0] dummy_fe_par_o,
output wire [3:0] usr_w_test_par_o,
input wire usr_w_test_trans_done_p_i,
output reg usr_w_test_wr_p_o,
output wire [3:0] w_test_par_o,
output reg [3:0] sha_w_test_par_o,
input wire [2:0] r_test_par_i,
input wire upd_w_en_i,
input wire upd_w_force_i,
input wire upd_w_i
);
// Module parameters:
parameter sync = 1;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire int_upd_w_p;
wire tie0_1;
wire u2_sync_generic_i_trans_start_p;
wire u3_sync_rst_i_int_rst_n;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign tie0_1 = `tie0_1_c;
/*
Generator information:
used package Micronas::Reg is version 1.16
this module is version 1.20
*/
/*
local definitions
*/
`define REG_00_OFFS 0 // reg_0x0
`define REG_04_OFFS 1 // reg_0x4
`define REG_08_OFFS 2 // reg_0x8
`define REG_0C_OFFS 3 // reg_0xC
`define REG_10_OFFS 4 // reg_0x10
`define REG_14_OFFS 5 // reg_0x14
`define REG_18_OFFS 6 // reg_0x18
`define REG_1C_OFFS 7 // reg_0x1C
`define REG_20_OFFS 8 // reg_0x20
`define REG_28_OFFS 10 // reg_0x28
/*
local wire or register declarations
*/
reg [31:0] REG_00;
reg [31:0] REG_04;
reg [31:0] REG_08;
reg [31:0] REG_0C;
reg [31:0] REG_10;
reg [31:0] REG_14;
reg [31:0] REG_18;
reg [31:0] REG_1C;
reg [31:0] REG_20;
wire [3:0] sha_w_test_shdw;
reg [31:0] REG_28;
reg int_upd_w;
wire wr_p;
wire rd_p;
reg int_trans_done;
wire [3:0] iaddr;
wire addr_overshoot;
wire trans_done_p;
reg rd_done_p;
reg wr_done_p;
reg fwd_txn;
wire [0:0] fwd_decode_vec;
wire [0:0] fwd_done_vec;
reg [31:0] mux_rd_data;
reg mux_rd_err;
/*
local wire and output assignments
*/
assign dummy_fe_par_o = REG_00[11:9];
assign dgatel_par_o = REG_00[3:0];
assign dgates_par_o = REG_00[8:4];
assign w_test_par_o = REG_20[19:16];
assign sha_w_test_shdw = REG_20[23:20];
assign usr_w_test_par_o = wr_data_i[3:0];
// clip address to decoded range
assign iaddr = addr_i[5:2];
assign addr_overshoot = |addr_i[13:6];
// write txn start pulse
assign wr_p = ~rd_wr_i & u2_sync_generic_i_trans_start_p;
// read txn start pulse
assign rd_p = rd_wr_i & u2_sync_generic_i_trans_start_p;
/*
generate txn done signals
*/
assign fwd_done_vec = {usr_w_test_trans_done_p_i}; // ack for forwarded txns
assign trans_done_p = ((wr_done_p | rd_done_p) & ~fwd_txn) | ((fwd_done_vec != 0) & fwd_txn);
always @(posedge clk_a or negedge u3_sync_rst_i_int_rst_n) begin
if (~u3_sync_rst_i_int_rst_n) begin
int_trans_done <= 0;
wr_done_p <= 0;
rd_done_p <= 0;
end
else begin
wr_done_p <= wr_p;
rd_done_p <= rd_p;
if (trans_done_p)
int_trans_done <= ~int_trans_done;
end
end
assign trans_done_o = int_trans_done;
/*
write process
*/
always @(posedge clk_a or negedge u3_sync_rst_i_int_rst_n) begin
if (~u3_sync_rst_i_int_rst_n) begin
REG_00[11:9] <= 'h0;
REG_00[3:0] <= 'h4;
REG_00[8:4] <= 'hf;
REG_20[19:16] <= 'h0;
REG_20[23:20] <= 'h0;
end
else begin
if (wr_p)
case (iaddr)
`REG_00_OFFS: begin
REG_00[11:9] <= wr_data_i[11:9];
REG_00[3:0] <= wr_data_i[3:0];
REG_00[8:4] <= wr_data_i[8:4];
end
`REG_20_OFFS: begin
REG_20[19:16] <= wr_data_i[19:16];
REG_20[23:20] <= wr_data_i[23:20];
end
endcase
end
end
/*
txn forwarding process
*/
// decode addresses of USR registers and read/write
assign fwd_decode_vec = {(iaddr == `REG_20_OFFS) & ~rd_wr_i};
always @(posedge clk_a or negedge u3_sync_rst_i_int_rst_n) begin
if (~u3_sync_rst_i_int_rst_n) begin
fwd_txn <= 0;
usr_w_test_wr_p_o <= 0;
end
else begin
usr_w_test_wr_p_o <= 0;
if (u2_sync_generic_i_trans_start_p) begin
fwd_txn <= |fwd_decode_vec; // set flag for forwarded txn
usr_w_test_wr_p_o <= fwd_decode_vec[0] & ~rd_wr_i;
end
else if (trans_done_p)
fwd_txn <= 0; // reset flag for forwarded transaction
end
end
/*
shadowing for update signal 'upd_w'
*/
// generate internal update signal
always @(posedge clk_a or negedge u3_sync_rst_i_int_rst_n) begin
if (~u3_sync_rst_i_int_rst_n)
int_upd_w <= 1;
else
int_upd_w <= (int_upd_w_p & upd_w_en_i) | upd_w_force_i;
end
// shadow process
always @(posedge clk_a) begin
if (int_upd_w) begin
sha_w_test_par_o <= sha_w_test_shdw;
end
end
/*
read logic and mux process
*/
assign rd_data_o = mux_rd_data;
assign rd_err_o = mux_rd_err | addr_overshoot;
always @(REG_00 or iaddr or r_test_par_i) begin
mux_rd_err <= 0;
mux_rd_data <= 0;
case (iaddr)
`REG_00_OFFS : begin
mux_rd_data[3:0] <= REG_00[3:0];
mux_rd_data[8:4] <= REG_00[8:4];
mux_rd_data[11:9] <= REG_00[11:9];
end
`REG_28_OFFS : begin
mux_rd_data[2:0] <= r_test_par_i;
end
default: begin
mux_rd_err <= 1; // no decode
end
endcase
end
/*
checking code
*/
`ifdef ASSERT_ON
property p_pos_pulse_check (sig); // check for positive pulse
@(posedge clk_a) disable iff (~u3_sync_rst_i_int_rst_n)
sig |=> ~sig;
endproperty
assert property(p_pos_pulse_check(usr_w_test_trans_done_p_i));
p_fwd_done_expected: assert property
(
@(posedge clk_a) disable iff (~u3_sync_rst_i_int_rst_n)
usr_w_test_trans_done_p_i |-> fwd_txn
);
p_fwd_done_onehot: assert property
(
@(posedge clk_a) disable iff (~u3_sync_rst_i_int_rst_n)
usr_w_test_trans_done_p_i |-> onehot(fwd_done_vec)
);
p_fwd_done_only_when_fwd_txn: assert property
(
@(posedge clk_a) disable iff (~u3_sync_rst_i_int_rst_n)
fwd_done_vec != 0 |-> fwd_txn
);
function onehot (input [0:0] vec); // not built-in to SV yet
integer i,j;
begin
j = 0;
for (i=0; i<1; i=i+1) j = j + vec[i] ? 1 : 0;
onehot = (j==1) ? 1 : 0;
end
endfunction
`endif
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for u2_sync_generic_i
sync_generic #(
.act(1),
.kind(2),
.rstact(0),
.rstval(0),
.sync(1)
) u2_sync_generic_i ( // Synchronizer for trans_done signal
.clk_r(clk_a),
.clk_s(tie0_1),
.rcv_o(u2_sync_generic_i_trans_start_p),
.rst_r(res_a_n_i),
.rst_s(tie0_1),
.snd_i(trans_start)
);
// End of Generated Instance Port Map for u2_sync_generic_i
// Generated Instance Port Map for u3_sync_rst_i
sync_rst #(
.act(0),
.sync(1)
) u3_sync_rst_i ( // Reset synchronizer
.clk_r(clk_a),
.rst_i(res_a_n_i),
.rst_o(u3_sync_rst_i_int_rst_n)
);
// End of Generated Instance Port Map for u3_sync_rst_i
// Generated Instance Port Map for u8_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u8_sync_generic_i ( // Synchronizer for update-signal upd_w
.clk_r(clk_a),
.clk_s(tie0_1),
.rcv_o(int_upd_w_p),
.rst_r(res_a_n_i),
.rst_s(tie0_1),
.snd_i(upd_w_i)
);
// End of Generated Instance Port Map for u8_sync_generic_i
endmodule
//
// End of Generated Module rtl of rs_cfg_fe1_clk_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVN_8_V
`define SKY130_FD_SC_HS__EINVN_8_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvn_8 (
A ,
TE_B,
Z ,
VPWR,
VGND
);
input A ;
input TE_B;
output Z ;
input VPWR;
input VGND;
sky130_fd_sc_hs__einvn base (
.A(A),
.TE_B(TE_B),
.Z(Z),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvn_8 (
A ,
TE_B,
Z
);
input A ;
input TE_B;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__einvn base (
.A(A),
.TE_B(TE_B),
.Z(Z)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVN_8_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:58 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_sim_netlist.v
// Design : zynq_design_1_xbar_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zynq_design_1_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zynq_design_1_xbar_0
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *) input [0:0]s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *) output [0:0]s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input [0:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [11:0] [23:12]" *) output [23:0]m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *) output [63:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8]" *) output [15:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3]" *) output [5:0]m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2]" *) output [3:0]m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1]" *) output [1:0]m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4]" *) output [7:0]m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *) output [5:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4]" *) output [7:0]m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4]" *) output [7:0]m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *) output [1:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *) input [1:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *) output [63:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *) output [7:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1]" *) output [1:0]m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *) output [1:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *) input [1:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [11:0] [23:12]" *) input [23:0]m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *) input [3:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *) input [1:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *) output [1:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [11:0] [23:12]" *) output [23:0]m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *) output [63:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8]" *) output [15:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3]" *) output [5:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2]" *) output [3:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1]" *) output [1:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4]" *) output [7:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *) output [5:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4]" *) output [7:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4]" *) output [7:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *) output [1:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *) input [1:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [11:0] [23:12]" *) input [23:0]m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *) input [63:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *) input [3:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1]" *) input [1:0]m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *) input [1:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *) output [1:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [63:0]m_axi_araddr;
wire [3:0]m_axi_arburst;
wire [7:0]m_axi_arcache;
wire [23:0]m_axi_arid;
wire [15:0]m_axi_arlen;
wire [1:0]m_axi_arlock;
wire [5:0]m_axi_arprot;
wire [7:0]m_axi_arqos;
wire [1:0]m_axi_arready;
wire [7:0]m_axi_arregion;
wire [5:0]m_axi_arsize;
wire [1:0]m_axi_arvalid;
wire [63:0]m_axi_awaddr;
wire [3:0]m_axi_awburst;
wire [7:0]m_axi_awcache;
wire [23:0]m_axi_awid;
wire [15:0]m_axi_awlen;
wire [1:0]m_axi_awlock;
wire [5:0]m_axi_awprot;
wire [7:0]m_axi_awqos;
wire [1:0]m_axi_awready;
wire [7:0]m_axi_awregion;
wire [5:0]m_axi_awsize;
wire [1:0]m_axi_awvalid;
wire [23:0]m_axi_bid;
wire [1:0]m_axi_bready;
wire [3:0]m_axi_bresp;
wire [1:0]m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [23:0]m_axi_rid;
wire [1:0]m_axi_rlast;
wire [1:0]m_axi_rready;
wire [3:0]m_axi_rresp;
wire [1:0]m_axi_rvalid;
wire [63:0]m_axi_wdata;
wire [1:0]m_axi_wlast;
wire [1:0]m_axi_wready;
wire [7:0]m_axi_wstrb;
wire [1:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
wire [1:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_PROTOCOL = "0" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "1" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *)
(* C_M_AXI_ADDR_WIDTH = "64'b0000000000000000000000000001000000000000000000000000000000010000" *)
(* C_M_AXI_BASE_ADDR = "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "64'b1111111111111111111111111111111111111111111111111111111111111111" *)
(* C_M_AXI_READ_ISSUING = "64'b0000000000000000000000000000100000000000000000000000000000001000" *)
(* C_M_AXI_SECURE = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "64'b1111111111111111111111111111111111111111111111111111111111111111" *)
(* C_M_AXI_WRITE_ISSUING = "64'b0000000000000000000000000000100000000000000000000000000000001000" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "2" *)
(* C_NUM_SLAVE_SLOTS = "1" *)
(* C_R_REGISTER = "0" *)
(* C_S_AXI_ARB_PRIORITY = "0" *)
(* C_S_AXI_BASE_ID = "0" *)
(* C_S_AXI_READ_ACCEPTANCE = "8" *)
(* C_S_AXI_SINGLE_THREAD = "0" *)
(* C_S_AXI_THREAD_ID_WIDTH = "12" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "8" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "2'b11" *)
(* P_M_AXI_SUPPORTS_WRITE = "2'b11" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000111111111111" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[1:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[1:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[23:0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[1:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_addr_arbiter" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter
(\s_axi_arready[0] ,
aa_mi_arvalid,
D,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
s_axi_rlast_i0,
\m_axi_arqos[7] ,
E,
\gen_axi.s_axi_rid_i_reg[11] ,
\gen_no_arbiter.m_valid_i_reg_0 ,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ,
\gen_no_arbiter.m_target_hot_i_reg[0]_0 ,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
m_axi_arvalid,
aresetn_d_reg,
aclk,
SR,
r_issuing_cnt,
\gen_axi.read_cnt_reg[5] ,
p_15_in,
mi_arready_2,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
s_axi_arvalid,
\chosen_reg[0] ,
\gen_multi_thread.accept_cnt_reg[3] ,
st_aa_artarget_hot,
\s_axi_arqos[3] ,
\s_axi_araddr[30] ,
\s_axi_araddr[28] ,
\s_axi_araddr[25] ,
\m_payload_i_reg[34] ,
m_axi_arready,
\m_payload_i_reg[34]_0 ,
s_axi_rready,
m_valid_i_reg,
Q,
m_valid_i,
aresetn_d,
aresetn_d_reg_0);
output \s_axi_arready[0] ;
output aa_mi_arvalid;
output [2:0]D;
output [2:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
output s_axi_rlast_i0;
output [68:0]\m_axi_arqos[7] ;
output [0:0]E;
output [0:0]\gen_axi.s_axi_rid_i_reg[11] ;
output \gen_no_arbiter.m_valid_i_reg_0 ;
output \gen_no_arbiter.s_ready_i_reg[0]_0 ;
output \gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ;
output [0:0]\gen_no_arbiter.m_target_hot_i_reg[0]_0 ;
output [0:0]\gen_master_slots[0].r_issuing_cnt_reg[0] ;
output [0:0]\gen_master_slots[1].r_issuing_cnt_reg[8] ;
output [1:0]m_axi_arvalid;
input aresetn_d_reg;
input aclk;
input [0:0]SR;
input [7:0]r_issuing_cnt;
input \gen_axi.read_cnt_reg[5] ;
input p_15_in;
input mi_arready_2;
input \gen_master_slots[2].r_issuing_cnt_reg[16] ;
input [0:0]s_axi_arvalid;
input \chosen_reg[0] ;
input \gen_multi_thread.accept_cnt_reg[3] ;
input [0:0]st_aa_artarget_hot;
input [68:0]\s_axi_arqos[3] ;
input \s_axi_araddr[30] ;
input \s_axi_araddr[28] ;
input \s_axi_araddr[25] ;
input \m_payload_i_reg[34] ;
input [1:0]m_axi_arready;
input \m_payload_i_reg[34]_0 ;
input [0:0]s_axi_rready;
input m_valid_i_reg;
input [0:0]Q;
input m_valid_i;
input aresetn_d;
input aresetn_d_reg_0;
wire [2:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [0:0]SR;
wire [1:0]aa_mi_artarget_hot;
wire aa_mi_arvalid;
wire aclk;
wire aresetn_d;
wire aresetn_d_reg;
wire aresetn_d_reg_0;
wire \chosen_reg[0] ;
wire \gen_axi.read_cnt_reg[5] ;
wire [0:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire \gen_axi.s_axi_rlast_i_i_6_n_0 ;
wire \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0 ;
wire \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ;
wire [0:0]\gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ;
wire \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ;
wire [2:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire [0:0]\gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].r_issuing_cnt_reg[16] ;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ;
wire \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ;
wire [0:0]\gen_no_arbiter.m_target_hot_i_reg[0]_0 ;
wire \gen_no_arbiter.m_valid_i_i_1__0_n_0 ;
wire \gen_no_arbiter.m_valid_i_reg_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire [68:0]\m_axi_arqos[7] ;
wire [1:0]m_axi_arready;
wire [1:0]m_axi_arvalid;
wire \m_payload_i_reg[34] ;
wire \m_payload_i_reg[34]_0 ;
wire m_valid_i;
wire m_valid_i_reg;
wire mi_arready_2;
wire p_15_in;
wire [7:0]r_issuing_cnt;
wire \s_axi_araddr[25] ;
wire \s_axi_araddr[28] ;
wire \s_axi_araddr[30] ;
wire [68:0]\s_axi_arqos[3] ;
wire \s_axi_arready[0] ;
wire [0:0]s_axi_arvalid;
wire s_axi_rlast_i0;
wire [0:0]s_axi_rready;
wire s_ready_i2;
wire [0:0]st_aa_artarget_hot;
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0080))
\gen_axi.s_axi_rid_i[11]_i_1
(.I0(aa_mi_arvalid),
.I1(\gen_axi.s_axi_rid_i_reg[11] ),
.I2(mi_arready_2),
.I3(p_15_in),
.O(E));
LUT6 #(
.INIT(64'h444444444444444F))
\gen_axi.s_axi_rlast_i_i_2
(.I0(\gen_axi.read_cnt_reg[5] ),
.I1(p_15_in),
.I2(\gen_axi.s_axi_rlast_i_i_6_n_0 ),
.I3(\m_axi_arqos[7] [44]),
.I4(\m_axi_arqos[7] [45]),
.I5(\m_axi_arqos[7] [47]),
.O(s_axi_rlast_i0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\gen_axi.s_axi_rlast_i_i_6
(.I0(\m_axi_arqos[7] [49]),
.I1(p_15_in),
.I2(\m_axi_arqos[7] [48]),
.I3(\m_axi_arqos[7] [46]),
.I4(\m_axi_arqos[7] [51]),
.I5(\m_axi_arqos[7] [50]),
.O(\gen_axi.s_axi_rlast_i_i_6_n_0 ));
LUT3 #(
.INIT(8'h69))
\gen_master_slots[0].r_issuing_cnt[1]_i_1
(.I0(r_issuing_cnt[0]),
.I1(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ),
.I2(r_issuing_cnt[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[0].r_issuing_cnt[2]_i_1
(.I0(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ),
.I1(r_issuing_cnt[0]),
.I2(r_issuing_cnt[1]),
.I3(r_issuing_cnt[2]),
.O(D[1]));
LUT6 #(
.INIT(64'h6666666666666662))
\gen_master_slots[0].r_issuing_cnt[3]_i_1
(.I0(\gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0 ),
.I1(\m_payload_i_reg[34] ),
.I2(r_issuing_cnt[0]),
.I3(r_issuing_cnt[1]),
.I4(r_issuing_cnt[2]),
.I5(r_issuing_cnt[3]),
.O(\gen_master_slots[0].r_issuing_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[0].r_issuing_cnt[3]_i_2
(.I0(r_issuing_cnt[3]),
.I1(r_issuing_cnt[2]),
.I2(r_issuing_cnt[1]),
.I3(r_issuing_cnt[0]),
.I4(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[0].r_issuing_cnt[3]_i_3
(.I0(m_axi_arready[0]),
.I1(aa_mi_artarget_hot[0]),
.I2(aa_mi_arvalid),
.O(\gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0080))
\gen_master_slots[0].r_issuing_cnt[3]_i_5
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[0]),
.I2(m_axi_arready[0]),
.I3(\m_payload_i_reg[34] ),
.O(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[1].r_issuing_cnt[10]_i_1
(.I0(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ),
.I1(r_issuing_cnt[4]),
.I2(r_issuing_cnt[5]),
.I3(r_issuing_cnt[6]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [1]));
LUT6 #(
.INIT(64'h6666666666666662))
\gen_master_slots[1].r_issuing_cnt[11]_i_1
(.I0(\gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ),
.I1(\m_payload_i_reg[34]_0 ),
.I2(r_issuing_cnt[4]),
.I3(r_issuing_cnt[5]),
.I4(r_issuing_cnt[6]),
.I5(r_issuing_cnt[7]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[8] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[1].r_issuing_cnt[11]_i_2
(.I0(r_issuing_cnt[7]),
.I1(r_issuing_cnt[6]),
.I2(r_issuing_cnt[5]),
.I3(r_issuing_cnt[4]),
.I4(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [2]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[1].r_issuing_cnt[11]_i_3
(.I0(m_axi_arready[1]),
.I1(aa_mi_artarget_hot[1]),
.I2(aa_mi_arvalid),
.O(\gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0080808080808080))
\gen_master_slots[1].r_issuing_cnt[11]_i_5
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[1]),
.I2(m_axi_arready[1]),
.I3(s_axi_rready),
.I4(m_valid_i_reg),
.I5(Q),
.O(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ));
LUT3 #(
.INIT(8'h69))
\gen_master_slots[1].r_issuing_cnt[9]_i_1
(.I0(r_issuing_cnt[4]),
.I1(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ),
.I2(r_issuing_cnt[5]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [0]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[2].r_issuing_cnt[16]_i_2
(.I0(mi_arready_2),
.I1(\gen_axi.s_axi_rid_i_reg[11] ),
.I2(aa_mi_arvalid),
.O(\gen_no_arbiter.m_valid_i_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'hE))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0
(.I0(st_aa_artarget_hot),
.I1(\gen_no_arbiter.m_target_hot_i_reg[0]_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_1__0
(.I0(aa_mi_arvalid),
.O(s_ready_i2));
FDRE \gen_no_arbiter.m_mesg_i_reg[0]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [0]),
.Q(\m_axi_arqos[7] [0]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[10]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [10]),
.Q(\m_axi_arqos[7] [10]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[11]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [11]),
.Q(\m_axi_arqos[7] [11]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[12]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [12]),
.Q(\m_axi_arqos[7] [12]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[13]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [13]),
.Q(\m_axi_arqos[7] [13]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[14]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [14]),
.Q(\m_axi_arqos[7] [14]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[15]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [15]),
.Q(\m_axi_arqos[7] [15]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[16]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [16]),
.Q(\m_axi_arqos[7] [16]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[17]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [17]),
.Q(\m_axi_arqos[7] [17]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[18]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [18]),
.Q(\m_axi_arqos[7] [18]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[19]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [19]),
.Q(\m_axi_arqos[7] [19]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[1]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [1]),
.Q(\m_axi_arqos[7] [1]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[20]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [20]),
.Q(\m_axi_arqos[7] [20]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[21]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [21]),
.Q(\m_axi_arqos[7] [21]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[22]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [22]),
.Q(\m_axi_arqos[7] [22]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[23]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [23]),
.Q(\m_axi_arqos[7] [23]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[24]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [24]),
.Q(\m_axi_arqos[7] [24]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[25]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [25]),
.Q(\m_axi_arqos[7] [25]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[26]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [26]),
.Q(\m_axi_arqos[7] [26]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[27]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [27]),
.Q(\m_axi_arqos[7] [27]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[28]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [28]),
.Q(\m_axi_arqos[7] [28]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[29]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [29]),
.Q(\m_axi_arqos[7] [29]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[2]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [2]),
.Q(\m_axi_arqos[7] [2]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[30]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [30]),
.Q(\m_axi_arqos[7] [30]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[31]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [31]),
.Q(\m_axi_arqos[7] [31]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[32]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [32]),
.Q(\m_axi_arqos[7] [32]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[33]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [33]),
.Q(\m_axi_arqos[7] [33]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[34]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [34]),
.Q(\m_axi_arqos[7] [34]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[35]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [35]),
.Q(\m_axi_arqos[7] [35]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[36]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [36]),
.Q(\m_axi_arqos[7] [36]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[37]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [37]),
.Q(\m_axi_arqos[7] [37]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[38]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [38]),
.Q(\m_axi_arqos[7] [38]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[39]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [39]),
.Q(\m_axi_arqos[7] [39]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[3]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [3]),
.Q(\m_axi_arqos[7] [3]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[40]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [40]),
.Q(\m_axi_arqos[7] [40]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[41]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [41]),
.Q(\m_axi_arqos[7] [41]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[42]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [42]),
.Q(\m_axi_arqos[7] [42]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[43]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [43]),
.Q(\m_axi_arqos[7] [43]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[44]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [44]),
.Q(\m_axi_arqos[7] [44]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[45]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [45]),
.Q(\m_axi_arqos[7] [45]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[46]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [46]),
.Q(\m_axi_arqos[7] [46]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[47]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [47]),
.Q(\m_axi_arqos[7] [47]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[48]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [48]),
.Q(\m_axi_arqos[7] [48]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[49]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [49]),
.Q(\m_axi_arqos[7] [49]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[4]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [4]),
.Q(\m_axi_arqos[7] [4]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[50]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [50]),
.Q(\m_axi_arqos[7] [50]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[51]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [51]),
.Q(\m_axi_arqos[7] [51]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[52]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [52]),
.Q(\m_axi_arqos[7] [52]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[53]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [53]),
.Q(\m_axi_arqos[7] [53]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[54]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [54]),
.Q(\m_axi_arqos[7] [54]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[55]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [55]),
.Q(\m_axi_arqos[7] [55]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[57]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [56]),
.Q(\m_axi_arqos[7] [56]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[58]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [57]),
.Q(\m_axi_arqos[7] [57]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[59]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [58]),
.Q(\m_axi_arqos[7] [58]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[5]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [5]),
.Q(\m_axi_arqos[7] [5]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[64]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [59]),
.Q(\m_axi_arqos[7] [59]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[65]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [60]),
.Q(\m_axi_arqos[7] [60]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[66]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [61]),
.Q(\m_axi_arqos[7] [61]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[67]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [62]),
.Q(\m_axi_arqos[7] [62]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[68]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [63]),
.Q(\m_axi_arqos[7] [63]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[69]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [64]),
.Q(\m_axi_arqos[7] [64]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[6]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [6]),
.Q(\m_axi_arqos[7] [6]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[70]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [65]),
.Q(\m_axi_arqos[7] [65]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[71]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [66]),
.Q(\m_axi_arqos[7] [66]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[72]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [67]),
.Q(\m_axi_arqos[7] [67]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[73]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [68]),
.Q(\m_axi_arqos[7] [68]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[7]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [7]),
.Q(\m_axi_arqos[7] [7]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[8]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [8]),
.Q(\m_axi_arqos[7] [8]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[9]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [9]),
.Q(\m_axi_arqos[7] [9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[0]_i_1
(.I0(\gen_no_arbiter.m_target_hot_i_reg[0]_0 ),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_artarget_hot[0]),
.O(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000080))
\gen_no_arbiter.m_target_hot_i[0]_i_2
(.I0(\s_axi_arqos[3] [33]),
.I1(\s_axi_arqos[3] [36]),
.I2(\s_axi_araddr[30] ),
.I3(\s_axi_araddr[28] ),
.I4(\s_axi_araddr[25] ),
.O(\gen_no_arbiter.m_target_hot_i_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[1]_i_1
(.I0(st_aa_artarget_hot),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_artarget_hot[1]),
.O(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ));
FDRE \gen_no_arbiter.m_target_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ),
.Q(aa_mi_artarget_hot[0]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ),
.Q(aa_mi_artarget_hot[1]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[2]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg_0),
.Q(\gen_axi.s_axi_rid_i_reg[11] ),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF0000002A))
\gen_no_arbiter.m_valid_i_i_1__0
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[0]),
.I2(m_axi_arready[0]),
.I3(\gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ),
.I4(\gen_no_arbiter.m_valid_i_reg_0 ),
.I5(m_valid_i),
.O(\gen_no_arbiter.m_valid_i_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1__0_n_0 ),
.Q(aa_mi_arvalid),
.R(SR));
LUT6 #(
.INIT(64'hFFEFFFEFFFEFFFFF))
\gen_no_arbiter.s_ready_i[0]_i_7__0
(.I0(\gen_master_slots[2].r_issuing_cnt_reg[16] ),
.I1(aa_mi_arvalid),
.I2(s_axi_arvalid),
.I3(\s_axi_arready[0] ),
.I4(\chosen_reg[0] ),
.I5(\gen_multi_thread.accept_cnt_reg[3] ),
.O(\gen_no_arbiter.s_ready_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg),
.Q(\s_axi_arready[0] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arvalid[0]_INST_0
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[0]),
.O(m_axi_arvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arvalid[1]_INST_0
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[1]),
.O(m_axi_arvalid[1]));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_addr_arbiter" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0
(ss_aa_awready,
aa_sa_awvalid,
\m_ready_d_reg[0] ,
\m_ready_d_reg[1] ,
aa_mi_awtarget_hot,
D,
\gen_master_slots[1].w_issuing_cnt_reg[9] ,
\gen_master_slots[0].w_issuing_cnt_reg[3] ,
\gen_master_slots[2].w_issuing_cnt_reg[16] ,
E,
\gen_master_slots[0].w_issuing_cnt_reg[0] ,
m_axi_awvalid,
st_aa_awtarget_hot,
\gen_no_arbiter.m_target_hot_i_reg[2]_0 ,
\m_ready_d_reg[1]_0 ,
Q,
aresetn_d_reg,
aclk,
SR,
m_ready_d,
aresetn_d,
w_issuing_cnt,
\chosen_reg[1] ,
m_axi_awready,
\chosen_reg[0] ,
mi_awready_2,
m_valid_i_reg,
s_axi_bready,
\s_axi_awaddr[26] ,
\s_axi_awaddr[20] ,
\s_axi_awqos[3] ,
m_ready_d_0,
m_valid_i,
st_aa_awtarget_enc,
aresetn_d_reg_0);
output ss_aa_awready;
output aa_sa_awvalid;
output \m_ready_d_reg[0] ;
output \m_ready_d_reg[1] ;
output [2:0]aa_mi_awtarget_hot;
output [2:0]D;
output \gen_master_slots[1].w_issuing_cnt_reg[9] ;
output [2:0]\gen_master_slots[0].w_issuing_cnt_reg[3] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16] ;
output [0:0]E;
output [0:0]\gen_master_slots[0].w_issuing_cnt_reg[0] ;
output [1:0]m_axi_awvalid;
output [0:0]st_aa_awtarget_hot;
output \gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
output \m_ready_d_reg[1]_0 ;
output [68:0]Q;
input aresetn_d_reg;
input aclk;
input [0:0]SR;
input [1:0]m_ready_d;
input aresetn_d;
input [7:0]w_issuing_cnt;
input \chosen_reg[1] ;
input [1:0]m_axi_awready;
input \chosen_reg[0] ;
input mi_awready_2;
input m_valid_i_reg;
input [0:0]s_axi_bready;
input \s_axi_awaddr[26] ;
input \s_axi_awaddr[20] ;
input [68:0]\s_axi_awqos[3] ;
input [0:0]m_ready_d_0;
input m_valid_i;
input [0:0]st_aa_awtarget_enc;
input aresetn_d_reg_0;
wire [2:0]D;
wire [0:0]E;
wire [68:0]Q;
wire [0:0]SR;
wire [2:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire aresetn_d_reg;
wire aresetn_d_reg_0;
wire \chosen_reg[0] ;
wire \chosen_reg[1] ;
wire \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 ;
wire \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ;
wire [0:0]\gen_master_slots[0].w_issuing_cnt_reg[0] ;
wire [2:0]\gen_master_slots[0].w_issuing_cnt_reg[3] ;
wire \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0 ;
wire \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ;
wire \gen_master_slots[1].w_issuing_cnt_reg[9] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16] ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
wire \gen_no_arbiter.m_valid_i_i_1_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_2_n_0 ;
wire [1:0]m_axi_awready;
wire [1:0]m_axi_awvalid;
wire [1:0]m_ready_d;
wire \m_ready_d[1]_i_4_n_0 ;
wire [0:0]m_ready_d_0;
wire \m_ready_d_reg[0] ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire m_valid_i;
wire m_valid_i_reg;
wire mi_awready_2;
wire \s_axi_awaddr[20] ;
wire \s_axi_awaddr[26] ;
wire [68:0]\s_axi_awqos[3] ;
wire [0:0]s_axi_bready;
wire s_ready_i2;
wire ss_aa_awready;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire [7:0]w_issuing_cnt;
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h4000))
\gen_axi.s_axi_wready_i_i_2
(.I0(m_ready_d[1]),
.I1(aa_sa_awvalid),
.I2(aa_mi_awtarget_hot[2]),
.I3(mi_awready_2),
.O(\gen_master_slots[2].w_issuing_cnt_reg[16] ));
LUT6 #(
.INIT(64'h6AAAAAAA95555555))
\gen_master_slots[0].w_issuing_cnt[1]_i_1
(.I0(w_issuing_cnt[0]),
.I1(\chosen_reg[0] ),
.I2(m_axi_awready[0]),
.I3(aa_mi_awtarget_hot[0]),
.I4(\gen_master_slots[1].w_issuing_cnt_reg[9] ),
.I5(w_issuing_cnt[1]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[0].w_issuing_cnt[2]_i_1
(.I0(w_issuing_cnt[0]),
.I1(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ),
.I2(w_issuing_cnt[1]),
.I3(w_issuing_cnt[2]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [1]));
LUT6 #(
.INIT(64'hAAAAAAAA55555554))
\gen_master_slots[0].w_issuing_cnt[3]_i_1
(.I0(\gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 ),
.I1(w_issuing_cnt[3]),
.I2(w_issuing_cnt[0]),
.I3(w_issuing_cnt[2]),
.I4(w_issuing_cnt[1]),
.I5(\chosen_reg[0] ),
.O(\gen_master_slots[0].w_issuing_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[0].w_issuing_cnt[3]_i_2
(.I0(w_issuing_cnt[3]),
.I1(w_issuing_cnt[0]),
.I2(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ),
.I3(w_issuing_cnt[1]),
.I4(w_issuing_cnt[2]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [2]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h4000))
\gen_master_slots[0].w_issuing_cnt[3]_i_3
(.I0(m_ready_d[1]),
.I1(aa_sa_awvalid),
.I2(aa_mi_awtarget_hot[0]),
.I3(m_axi_awready[0]),
.O(\gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00008000))
\gen_master_slots[0].w_issuing_cnt[3]_i_5
(.I0(\chosen_reg[0] ),
.I1(m_axi_awready[0]),
.I2(aa_mi_awtarget_hot[0]),
.I3(aa_sa_awvalid),
.I4(m_ready_d[1]),
.O(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[1].w_issuing_cnt[10]_i_1
(.I0(w_issuing_cnt[4]),
.I1(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ),
.I2(w_issuing_cnt[5]),
.I3(w_issuing_cnt[6]),
.O(D[1]));
LUT6 #(
.INIT(64'hAAAAAAAA55555554))
\gen_master_slots[1].w_issuing_cnt[11]_i_1
(.I0(\gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0 ),
.I1(w_issuing_cnt[7]),
.I2(w_issuing_cnt[4]),
.I3(w_issuing_cnt[6]),
.I4(w_issuing_cnt[5]),
.I5(\chosen_reg[1] ),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[1].w_issuing_cnt[11]_i_2
(.I0(w_issuing_cnt[7]),
.I1(w_issuing_cnt[4]),
.I2(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ),
.I3(w_issuing_cnt[5]),
.I4(w_issuing_cnt[6]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h4000))
\gen_master_slots[1].w_issuing_cnt[11]_i_3
(.I0(m_ready_d[1]),
.I1(aa_sa_awvalid),
.I2(aa_mi_awtarget_hot[1]),
.I3(m_axi_awready[1]),
.O(\gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000070000000))
\gen_master_slots[1].w_issuing_cnt[11]_i_5
(.I0(m_valid_i_reg),
.I1(s_axi_bready),
.I2(m_axi_awready[1]),
.I3(aa_mi_awtarget_hot[1]),
.I4(aa_sa_awvalid),
.I5(m_ready_d[1]),
.O(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6AAAAAAA95555555))
\gen_master_slots[1].w_issuing_cnt[9]_i_1
(.I0(w_issuing_cnt[4]),
.I1(\chosen_reg[1] ),
.I2(m_axi_awready[1]),
.I3(aa_mi_awtarget_hot[1]),
.I4(\gen_master_slots[1].w_issuing_cnt_reg[9] ),
.I5(w_issuing_cnt[5]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h2))
\gen_master_slots[1].w_issuing_cnt[9]_i_2
(.I0(aa_sa_awvalid),
.I1(m_ready_d[1]),
.O(\gen_master_slots[1].w_issuing_cnt_reg[9] ));
LUT5 #(
.INIT(32'h10000000))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0 ),
.I1(\s_axi_awaddr[26] ),
.I2(\s_axi_awaddr[20] ),
.I3(\s_axi_awqos[3] [33]),
.I4(\s_axi_awqos[3] [36]),
.O(st_aa_awtarget_hot));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9
(.I0(\s_axi_awqos[3] [35]),
.I1(\s_axi_awqos[3] [31]),
.I2(\s_axi_awqos[3] [28]),
.I3(\s_axi_awqos[3] [39]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_2
(.I0(aa_sa_awvalid),
.O(s_ready_i2));
FDRE \gen_no_arbiter.m_mesg_i_reg[0]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [0]),
.Q(Q[0]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[10]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [10]),
.Q(Q[10]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[11]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [11]),
.Q(Q[11]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[12]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [12]),
.Q(Q[12]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[13]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [13]),
.Q(Q[13]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[14]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [14]),
.Q(Q[14]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[15]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [15]),
.Q(Q[15]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[16]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [16]),
.Q(Q[16]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[17]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [17]),
.Q(Q[17]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[18]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [18]),
.Q(Q[18]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[19]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [19]),
.Q(Q[19]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[1]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [1]),
.Q(Q[1]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[20]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [20]),
.Q(Q[20]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[21]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [21]),
.Q(Q[21]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[22]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [22]),
.Q(Q[22]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[23]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [23]),
.Q(Q[23]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[24]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [24]),
.Q(Q[24]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[25]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [25]),
.Q(Q[25]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[26]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [26]),
.Q(Q[26]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[27]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [27]),
.Q(Q[27]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[28]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [28]),
.Q(Q[28]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[29]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [29]),
.Q(Q[29]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[2]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [2]),
.Q(Q[2]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[30]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [30]),
.Q(Q[30]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[31]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [31]),
.Q(Q[31]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[32]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [32]),
.Q(Q[32]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[33]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [33]),
.Q(Q[33]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[34]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [34]),
.Q(Q[34]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[35]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [35]),
.Q(Q[35]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[36]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [36]),
.Q(Q[36]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[37]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [37]),
.Q(Q[37]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[38]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [38]),
.Q(Q[38]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[39]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [39]),
.Q(Q[39]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[3]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [3]),
.Q(Q[3]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[40]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [40]),
.Q(Q[40]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[41]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [41]),
.Q(Q[41]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[42]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [42]),
.Q(Q[42]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[43]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [43]),
.Q(Q[43]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[44]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [44]),
.Q(Q[44]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[45]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [45]),
.Q(Q[45]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[46]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [46]),
.Q(Q[46]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[47]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [47]),
.Q(Q[47]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[48]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [48]),
.Q(Q[48]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[49]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [49]),
.Q(Q[49]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[4]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [4]),
.Q(Q[4]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[50]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [50]),
.Q(Q[50]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[51]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [51]),
.Q(Q[51]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[52]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [52]),
.Q(Q[52]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[53]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [53]),
.Q(Q[53]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[54]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [54]),
.Q(Q[54]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[55]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [55]),
.Q(Q[55]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[57]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [56]),
.Q(Q[56]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[58]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [57]),
.Q(Q[57]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[59]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [58]),
.Q(Q[58]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[5]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [5]),
.Q(Q[5]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[64]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [59]),
.Q(Q[59]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[65]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [60]),
.Q(Q[60]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[66]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [61]),
.Q(Q[61]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[67]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [62]),
.Q(Q[62]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[68]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [63]),
.Q(Q[63]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[69]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [64]),
.Q(Q[64]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[6]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [6]),
.Q(Q[6]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[70]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [65]),
.Q(Q[65]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[71]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [66]),
.Q(Q[66]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[72]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [67]),
.Q(Q[67]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[73]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [68]),
.Q(Q[68]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[7]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [7]),
.Q(Q[7]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[8]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [8]),
.Q(Q[8]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[9]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [9]),
.Q(Q[9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[0]_i_1
(.I0(st_aa_awtarget_hot),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_awtarget_hot[0]),
.O(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[1]_i_1
(.I0(st_aa_awtarget_enc),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_awtarget_hot[1]),
.O(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ));
FDRE \gen_no_arbiter.m_target_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ),
.Q(aa_mi_awtarget_hot[0]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ),
.Q(aa_mi_awtarget_hot[1]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[2]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg_0),
.Q(aa_mi_awtarget_hot[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hF2))
\gen_no_arbiter.m_valid_i_i_1
(.I0(aa_sa_awvalid),
.I1(\gen_no_arbiter.m_valid_i_i_2_n_0 ),
.I2(m_valid_i),
.O(\gen_no_arbiter.m_valid_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h0000FFFE))
\gen_no_arbiter.m_valid_i_i_2
(.I0(aa_mi_awtarget_hot[0]),
.I1(aa_mi_awtarget_hot[1]),
.I2(aa_mi_awtarget_hot[2]),
.I3(m_ready_d[0]),
.I4(\m_ready_d_reg[1] ),
.O(\gen_no_arbiter.m_valid_i_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1_n_0 ),
.Q(aa_sa_awvalid),
.R(SR));
LUT2 #(
.INIT(4'hE))
\gen_no_arbiter.s_ready_i[0]_i_29
(.I0(ss_aa_awready),
.I1(m_ready_d_0),
.O(\gen_no_arbiter.m_target_hot_i_reg[2]_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg),
.Q(ss_aa_awready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h20))
\m_axi_awvalid[0]_INST_0
(.I0(aa_mi_awtarget_hot[0]),
.I1(m_ready_d[1]),
.I2(aa_sa_awvalid),
.O(m_axi_awvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h20))
\m_axi_awvalid[1]_INST_0
(.I0(aa_mi_awtarget_hot[1]),
.I1(m_ready_d[1]),
.I2(aa_sa_awvalid),
.O(m_axi_awvalid[1]));
LUT6 #(
.INIT(64'h55555554FFFFFFFF))
\m_ready_d[0]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(m_ready_d[0]),
.I2(aa_mi_awtarget_hot[2]),
.I3(aa_mi_awtarget_hot[1]),
.I4(aa_mi_awtarget_hot[0]),
.I5(aresetn_d),
.O(\m_ready_d_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hFFFE))
\m_ready_d[1]_i_2
(.I0(m_ready_d[0]),
.I1(aa_mi_awtarget_hot[2]),
.I2(aa_mi_awtarget_hot[1]),
.I3(aa_mi_awtarget_hot[0]),
.O(\m_ready_d_reg[1]_0 ));
LUT6 #(
.INIT(64'h0000000000000777))
\m_ready_d[1]_i_3
(.I0(m_axi_awready[1]),
.I1(aa_mi_awtarget_hot[1]),
.I2(mi_awready_2),
.I3(aa_mi_awtarget_hot[2]),
.I4(\m_ready_d[1]_i_4_n_0 ),
.I5(m_ready_d[1]),
.O(\m_ready_d_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h8))
\m_ready_d[1]_i_4
(.I0(m_axi_awready[0]),
.I1(aa_mi_awtarget_hot[0]),
.O(\m_ready_d[1]_i_4_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_arbiter_resp" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
D,
\gen_master_slots[0].w_issuing_cnt_reg[1] ,
\chosen_reg[0]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
SR,
E,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
\gen_master_slots[2].w_issuing_cnt_reg[16] ,
s_axi_bvalid,
\chosen_reg[1]_0 ,
\gen_master_slots[1].w_issuing_cnt_reg[8] ,
\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ,
aresetn_d,
Q,
\m_ready_d_reg[1] ,
p_80_out,
s_axi_bready,
\s_axi_awaddr[26] ,
st_aa_awtarget_hot,
aa_mi_awtarget_hot,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ,
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ,
\gen_master_slots[1].w_issuing_cnt_reg[10] ,
\gen_master_slots[2].w_issuing_cnt_reg[16]_1 ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ,
CO,
\m_ready_d_reg[1]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ,
\m_ready_d_reg[1]_1 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ,
\m_ready_d_reg[1]_2 ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ,
cmd_push_3,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ,
\m_ready_d_reg[1]_3 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ,
\m_ready_d_reg[1]_4 ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ,
cmd_push_0,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ,
\gen_multi_thread.accept_cnt_reg[0] ,
aa_sa_awvalid,
s_axi_awvalid,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
m_valid_i_reg,
p_38_out,
p_60_out,
w_issuing_cnt,
\m_ready_d_reg[1]_5 ,
aclk);
output \gen_no_arbiter.s_ready_i_reg[0] ;
output m_valid_i;
output [2:0]D;
output \gen_master_slots[0].w_issuing_cnt_reg[1] ;
output \chosen_reg[0]_0 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [0:0]SR;
output [0:0]E;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16] ;
output [0:0]s_axi_bvalid;
output \chosen_reg[1]_0 ;
output \gen_master_slots[1].w_issuing_cnt_reg[8] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
input aresetn_d;
input [3:0]Q;
input \m_ready_d_reg[1] ;
input p_80_out;
input [0:0]s_axi_bready;
input [0:0]\s_axi_awaddr[26] ;
input [0:0]st_aa_awtarget_hot;
input [0:0]aa_mi_awtarget_hot;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
input \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input \gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ;
input \gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ;
input \gen_master_slots[1].w_issuing_cnt_reg[10] ;
input \gen_master_slots[2].w_issuing_cnt_reg[16]_1 ;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ;
input \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ;
input [0:0]CO;
input \m_ready_d_reg[1]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
input \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
input \m_ready_d_reg[1]_1 ;
input \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
input [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
input \m_ready_d_reg[1]_2 ;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ;
input [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
input cmd_push_3;
input \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
input [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ;
input \m_ready_d_reg[1]_3 ;
input \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
input [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
input \m_ready_d_reg[1]_4 ;
input \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
input [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
input cmd_push_0;
input \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
input [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
input \gen_multi_thread.accept_cnt_reg[0] ;
input aa_sa_awvalid;
input [0:0]s_axi_awvalid;
input \gen_no_arbiter.s_ready_i_reg[0]_0 ;
input m_valid_i_reg;
input p_38_out;
input p_60_out;
input [4:0]w_issuing_cnt;
input \m_ready_d_reg[1]_5 ;
input aclk;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [0:0]SR;
wire [0:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire \chosen[0]_i_1__0_n_0 ;
wire \chosen[1]_i_1__0_n_0 ;
wire \chosen[2]_i_1__0_n_0 ;
wire \chosen_reg[0]_0 ;
wire \chosen_reg[1]_0 ;
wire cmd_push_0;
wire cmd_push_3;
wire \gen_master_slots[0].w_issuing_cnt_reg[1] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[10] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16]_1 ;
wire \gen_multi_thread.accept_cnt_reg[0] ;
wire [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
wire \gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
wire \gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i[0]_i_24_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_25_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_7_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire \last_rr_hot[0]_i_1_n_0 ;
wire \last_rr_hot[1]_i_1_n_0 ;
wire \last_rr_hot[2]_i_1_n_0 ;
wire \last_rr_hot[2]_i_6_n_0 ;
wire \last_rr_hot_reg_n_0_[0] ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[1]_2 ;
wire \m_ready_d_reg[1]_3 ;
wire \m_ready_d_reg[1]_4 ;
wire \m_ready_d_reg[1]_5 ;
wire m_valid_i;
wire m_valid_i_reg;
wire need_arbitration;
wire [2:0]next_rr_hot;
wire p_38_out;
wire p_3_in;
wire p_4_in;
wire p_60_out;
wire p_80_out;
wire [0:0]\s_axi_awaddr[26] ;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_bvalid;
wire [0:0]st_aa_awtarget_hot;
wire [4:0]w_issuing_cnt;
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\chosen[0]_i_1__0
(.I0(next_rr_hot[0]),
.I1(need_arbitration),
.I2(\chosen_reg[0]_0 ),
.O(\chosen[0]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\chosen[1]_i_1__0
(.I0(next_rr_hot[1]),
.I1(need_arbitration),
.I2(\chosen_reg[1]_0 ),
.O(\chosen[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\chosen[2]_i_1__0
(.I0(next_rr_hot[2]),
.I1(need_arbitration),
.I2(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.O(\chosen[2]_i_1__0_n_0 ));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\chosen[0]_i_1__0_n_0 ),
.Q(\chosen_reg[0]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\chosen[1]_i_1__0_n_0 ),
.Q(\chosen_reg[1]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\chosen[2]_i_1__0_n_0 ),
.Q(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.R(SR));
LUT3 #(
.INIT(8'h7F))
\gen_master_slots[0].w_issuing_cnt[3]_i_4
(.I0(\chosen_reg[0]_0 ),
.I1(p_80_out),
.I2(s_axi_bready),
.O(\gen_master_slots[0].w_issuing_cnt_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'h7F))
\gen_master_slots[1].w_issuing_cnt[11]_i_4
(.I0(s_axi_bready),
.I1(\chosen_reg[1]_0 ),
.I2(p_60_out),
.O(\gen_master_slots[1].w_issuing_cnt_reg[8] ));
LUT5 #(
.INIT(32'h807F7F00))
\gen_master_slots[2].w_issuing_cnt[16]_i_1
(.I0(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.I1(p_38_out),
.I2(s_axi_bready),
.I3(\m_ready_d_reg[1]_5 ),
.I4(w_issuing_cnt[4]),
.O(\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hA956))
\gen_multi_thread.accept_cnt[1]_i_1
(.I0(Q[0]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\m_ready_d_reg[1] ),
.I3(Q[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT5 #(
.INIT(32'hEFF1100E))
\gen_multi_thread.accept_cnt[2]_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[2]),
.O(D[1]));
LUT6 #(
.INIT(64'hFFFE00000000FFFF))
\gen_multi_thread.accept_cnt[3]_i_1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[2]),
.I4(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I5(\m_ready_d_reg[1] ),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT6 #(
.INIT(64'hAAA6AAAAAAAA999A))
\gen_multi_thread.accept_cnt[3]_i_2
(.I0(Q[3]),
.I1(Q[0]),
.I2(\m_ready_d_reg[1] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I4(Q[1]),
.I5(Q[2]),
.O(D[2]));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1
(.I0(cmd_push_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1
(.I0(\m_ready_d_reg[1]_4 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1
(.I0(\m_ready_d_reg[1]_3 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1
(.I0(cmd_push_3),
.I1(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1
(.I0(\m_ready_d_reg[1]_2 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1
(.I0(\m_ready_d_reg[1]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1
(.I0(\m_ready_d_reg[1]_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ),
.I3(CO),
.O(E));
LUT6 #(
.INIT(64'h00AAAA80AA80AA80))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3
(.I0(s_axi_bready),
.I1(\chosen_reg[0]_0 ),
.I2(p_80_out),
.I3(m_valid_i_reg),
.I4(p_38_out),
.I5(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_1
(.I0(aresetn_d),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT5 #(
.INIT(32'h1FFF1000))
\gen_no_arbiter.m_target_hot_i[2]_i_1
(.I0(\s_axi_awaddr[26] ),
.I1(st_aa_awtarget_hot),
.I2(m_valid_i),
.I3(aresetn_d),
.I4(aa_mi_awtarget_hot),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT2 #(
.INIT(4'h8))
\gen_no_arbiter.s_ready_i[0]_i_1
(.I0(m_valid_i),
.I1(aresetn_d),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT6 #(
.INIT(64'h000000000000F022))
\gen_no_arbiter.s_ready_i[0]_i_2
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ),
.I3(\s_axi_awaddr[26] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_7_n_0 ),
.O(m_valid_i));
LUT6 #(
.INIT(64'hFFFFFFFFFF40FFFF))
\gen_no_arbiter.s_ready_i[0]_i_24
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I1(Q[3]),
.I2(\gen_multi_thread.accept_cnt_reg[0] ),
.I3(aa_sa_awvalid),
.I4(s_axi_awvalid),
.I5(\gen_no_arbiter.s_ready_i_reg[0]_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_24_n_0 ));
LUT5 #(
.INIT(32'h00020000))
\gen_no_arbiter.s_ready_i[0]_i_25
(.I0(\gen_master_slots[0].w_issuing_cnt_reg[1] ),
.I1(w_issuing_cnt[2]),
.I2(w_issuing_cnt[1]),
.I3(w_issuing_cnt[0]),
.I4(w_issuing_cnt[3]),
.O(\gen_no_arbiter.s_ready_i[0]_i_25_n_0 ));
LUT6 #(
.INIT(64'hEFAAEFEFEFAAEAEA))
\gen_no_arbiter.s_ready_i[0]_i_7
(.I0(\gen_no_arbiter.s_ready_i[0]_i_24_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_25_n_0 ),
.I2(st_aa_awtarget_hot),
.I3(\gen_master_slots[1].w_issuing_cnt_reg[10] ),
.I4(\s_axi_awaddr[26] ),
.I5(\gen_master_slots[2].w_issuing_cnt_reg[16]_1 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFF57AA00))
\last_rr_hot[0]_i_1
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(\last_rr_hot_reg_n_0_[0] ),
.O(\last_rr_hot[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF5F7A0A0))
\last_rr_hot[1]_i_1
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_3_in),
.O(\last_rr_hot[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hDDDF8888))
\last_rr_hot[2]_i_1
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_4_in),
.O(\last_rr_hot[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEE00000FEE))
\last_rr_hot[2]_i_2
(.I0(p_60_out),
.I1(p_38_out),
.I2(\chosen_reg[0]_0 ),
.I3(p_80_out),
.I4(\last_rr_hot[2]_i_6_n_0 ),
.I5(s_axi_bready),
.O(need_arbitration));
LUT6 #(
.INIT(64'hAAAAAAAA20222020))
\last_rr_hot[2]_i_3__0
(.I0(p_38_out),
.I1(p_60_out),
.I2(\last_rr_hot_reg_n_0_[0] ),
.I3(p_80_out),
.I4(p_4_in),
.I5(p_3_in),
.O(next_rr_hot[2]));
LUT6 #(
.INIT(64'hAAAAAAAA0A0A0008))
\last_rr_hot[2]_i_4__0
(.I0(p_60_out),
.I1(p_3_in),
.I2(p_80_out),
.I3(p_38_out),
.I4(p_4_in),
.I5(\last_rr_hot_reg_n_0_[0] ),
.O(next_rr_hot[1]));
LUT6 #(
.INIT(64'h8A8A8A8A88888A88))
\last_rr_hot[2]_i_5__0
(.I0(p_80_out),
.I1(p_4_in),
.I2(p_38_out),
.I3(\last_rr_hot_reg_n_0_[0] ),
.I4(p_60_out),
.I5(p_3_in),
.O(next_rr_hot[0]));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'hF888))
\last_rr_hot[2]_i_6
(.I0(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.I1(p_38_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_60_out),
.O(\last_rr_hot[2]_i_6_n_0 ));
FDRE \last_rr_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[0]_i_1_n_0 ),
.Q(\last_rr_hot_reg_n_0_[0] ),
.R(SR));
FDRE \last_rr_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[1]_i_1_n_0 ),
.Q(p_3_in),
.R(SR));
FDSE \last_rr_hot_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[2]_i_1_n_0 ),
.Q(p_4_in),
.S(SR));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\s_axi_bvalid[0]_INST_0
(.I0(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.I1(p_38_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_60_out),
.I4(p_80_out),
.I5(\chosen_reg[0]_0 ),
.O(s_axi_bvalid));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_arbiter_resp" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5
(D,
\gen_multi_thread.accept_cnt_reg[2] ,
E,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
s_axi_rlast,
s_axi_rvalid,
\chosen_reg[1]_0 ,
\m_payload_i_reg[34] ,
s_axi_rresp,
S,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
s_axi_rid,
s_axi_rdata,
\m_payload_i_reg[34]_0 ,
Q,
\gen_no_arbiter.s_ready_i_reg[0] ,
cmd_push_3,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ,
CO,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ,
\gen_no_arbiter.s_ready_i_reg[0]_1 ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ,
\gen_no_arbiter.s_ready_i_reg[0]_2 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ,
\gen_no_arbiter.s_ready_i_reg[0]_3 ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ,
\gen_no_arbiter.s_ready_i_reg[0]_4 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ,
\gen_no_arbiter.s_ready_i_reg[0]_5 ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ,
cmd_push_0,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ,
p_74_out,
s_axi_rready,
p_54_out,
p_32_out,
\m_payload_i_reg[46] ,
\m_payload_i_reg[46]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ,
\m_payload_i_reg[46]_1 ,
SR,
aclk);
output [2:0]D;
output \gen_multi_thread.accept_cnt_reg[2] ;
output [0:0]E;
output [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
output [0:0]\m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
output \chosen_reg[1]_0 ;
output \m_payload_i_reg[34] ;
output [0:0]s_axi_rresp;
output [3:0]S;
output [3:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [3:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
output [11:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [0:0]\m_payload_i_reg[34]_0 ;
input [3:0]Q;
input \gen_no_arbiter.s_ready_i_reg[0] ;
input cmd_push_3;
input \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
input [0:0]CO;
input \gen_no_arbiter.s_ready_i_reg[0]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ;
input \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ;
input \gen_no_arbiter.s_ready_i_reg[0]_1 ;
input [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
input \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
input \gen_no_arbiter.s_ready_i_reg[0]_2 ;
input \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
input [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
input \gen_no_arbiter.s_ready_i_reg[0]_3 ;
input [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ;
input \gen_no_arbiter.s_ready_i_reg[0]_4 ;
input \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
input [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
input \gen_no_arbiter.s_ready_i_reg[0]_5 ;
input \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
input [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
input cmd_push_0;
input \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
input [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
input p_74_out;
input [0:0]s_axi_rready;
input p_54_out;
input p_32_out;
input [25:0]\m_payload_i_reg[46] ;
input [25:0]\m_payload_i_reg[46]_0 ;
input [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ;
input [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ;
input [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ;
input [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ;
input [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ;
input [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ;
input [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ;
input [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ;
input [12:0]\m_payload_i_reg[46]_1 ;
input [0:0]SR;
input aclk;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]S;
wire [0:0]SR;
wire aclk;
wire \chosen[0]_i_1_n_0 ;
wire \chosen[1]_i_1_n_0 ;
wire \chosen[2]_i_1_n_0 ;
wire \chosen_reg[1]_0 ;
wire cmd_push_0;
wire cmd_push_3;
wire \gen_multi_thread.accept_cnt_reg[2] ;
wire [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_1 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_2 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_3 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_4 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_5 ;
wire i__carry_i_10_n_0;
wire i__carry_i_11_n_0;
wire i__carry_i_12_n_0;
wire i__carry_i_13_n_0;
wire i__carry_i_14_n_0;
wire i__carry_i_15_n_0;
wire i__carry_i_16_n_0;
wire i__carry_i_5_n_0;
wire i__carry_i_6_n_0;
wire i__carry_i_7_n_0;
wire i__carry_i_8_n_0;
wire i__carry_i_9_n_0;
wire \last_rr_hot[0]_i_1__0_n_0 ;
wire \last_rr_hot[1]_i_1__0_n_0 ;
wire \last_rr_hot[2]_i_1__0_n_0 ;
wire \last_rr_hot_reg_n_0_[0] ;
wire [0:0]\m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire \m_payload_i_reg[34] ;
wire [0:0]\m_payload_i_reg[34]_0 ;
wire [25:0]\m_payload_i_reg[46] ;
wire [25:0]\m_payload_i_reg[46]_0 ;
wire [12:0]\m_payload_i_reg[46]_1 ;
wire need_arbitration;
wire [2:0]next_rr_hot;
wire p_32_out;
wire p_3_in;
wire p_4_in;
wire p_54_out;
wire p_74_out;
wire [11:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire \s_axi_rid[11]_INST_0_i_1_n_0 ;
wire \s_axi_rid[11]_INST_0_i_2_n_0 ;
wire \s_axi_rid[11]_INST_0_i_3_n_0 ;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\chosen[0]_i_1
(.I0(next_rr_hot[0]),
.I1(need_arbitration),
.I2(\m_payload_i_reg[0]_0 ),
.O(\chosen[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\chosen[1]_i_1
(.I0(next_rr_hot[1]),
.I1(need_arbitration),
.I2(\chosen_reg[1]_0 ),
.O(\chosen[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\chosen[2]_i_1
(.I0(next_rr_hot[2]),
.I1(need_arbitration),
.I2(\m_payload_i_reg[34] ),
.O(\chosen[2]_i_1_n_0 ));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\chosen[0]_i_1_n_0 ),
.Q(\m_payload_i_reg[0]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\chosen[1]_i_1_n_0 ),
.Q(\chosen_reg[1]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\chosen[2]_i_1_n_0 ),
.Q(\m_payload_i_reg[34] ),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT4 #(
.INIT(16'hA659))
\gen_multi_thread.accept_cnt[1]_i_1__0
(.I0(Q[0]),
.I1(\gen_no_arbiter.s_ready_i_reg[0] ),
.I2(\gen_multi_thread.accept_cnt_reg[2] ),
.I3(Q[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'hBFF4400B))
\gen_multi_thread.accept_cnt[2]_i_1__0
(.I0(\gen_multi_thread.accept_cnt_reg[2] ),
.I1(\gen_no_arbiter.s_ready_i_reg[0] ),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[2]),
.O(D[1]));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_multi_thread.accept_cnt[3]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[2]),
.I4(\gen_multi_thread.accept_cnt_reg[2] ),
.I5(\gen_no_arbiter.s_ready_i_reg[0] ),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT6 #(
.INIT(64'hA6AAAAAAAAAA9A99))
\gen_multi_thread.accept_cnt[3]_i_2__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(\gen_multi_thread.accept_cnt_reg[2] ),
.I3(\gen_no_arbiter.s_ready_i_reg[0] ),
.I4(Q[1]),
.I5(Q[2]),
.O(D[2]));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0
(.I0(cmd_push_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ),
.I3(\gen_multi_thread.accept_cnt_reg[2] ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_5 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_4 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0
(.I0(cmd_push_3),
.I1(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ),
.I2(CO),
.I3(\gen_multi_thread.accept_cnt_reg[2] ),
.O(E));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_3 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_2 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_0 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT5 #(
.INIT(32'hA8880000))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0
(.I0(s_axi_rlast),
.I1(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I2(\m_payload_i_reg[0]_0 ),
.I3(p_74_out),
.I4(s_axi_rready),
.O(\gen_multi_thread.accept_cnt_reg[2] ));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_10
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [9]),
.I2(\m_payload_i_reg[46]_0 [22]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [22]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_10_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_11
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [5]),
.I2(\m_payload_i_reg[46]_0 [18]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [18]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_11_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_12
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [17]),
.I2(\m_payload_i_reg[46]_1 [4]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46]_0 [17]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(i__carry_i_12_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_13
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [19]),
.I2(\m_payload_i_reg[46]_1 [6]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [19]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_13_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_14
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [2]),
.I2(\m_payload_i_reg[46]_0 [15]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [15]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_14_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_15
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [14]),
.I2(\m_payload_i_reg[46]_1 [1]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [14]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_15_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_16
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [3]),
.I2(\m_payload_i_reg[46]_0 [16]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [16]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_16_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [10]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [7]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [4]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [1]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [0]));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_5
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [11]),
.I2(\m_payload_i_reg[46] [24]),
.I3(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I4(\m_payload_i_reg[46]_0 [24]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(i__carry_i_5_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_6
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [23]),
.I2(\m_payload_i_reg[46]_1 [10]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [23]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_6_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_7
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [25]),
.I2(\m_payload_i_reg[46]_1 [12]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [25]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_7_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_8
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [8]),
.I2(\m_payload_i_reg[46]_0 [21]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [21]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_8_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_9
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [7]),
.I2(\m_payload_i_reg[46]_0 [20]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [20]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_9_n_0));
LUT5 #(
.INIT(32'hFF57AA00))
\last_rr_hot[0]_i_1__0
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(\last_rr_hot_reg_n_0_[0] ),
.O(\last_rr_hot[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hF5F7A0A0))
\last_rr_hot[1]_i_1__0
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_3_in),
.O(\last_rr_hot[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hDDDF8888))
\last_rr_hot[2]_i_1__0
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_4_in),
.O(\last_rr_hot[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hABBBABBBABBBAB88))
\last_rr_hot[2]_i_2__0
(.I0(s_axi_rready),
.I1(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I2(\m_payload_i_reg[0]_0 ),
.I3(p_74_out),
.I4(p_54_out),
.I5(p_32_out),
.O(need_arbitration));
LUT6 #(
.INIT(64'hAAAAAAAA20222020))
\last_rr_hot[2]_i_3
(.I0(p_32_out),
.I1(p_54_out),
.I2(\last_rr_hot_reg_n_0_[0] ),
.I3(p_74_out),
.I4(p_4_in),
.I5(p_3_in),
.O(next_rr_hot[2]));
LUT6 #(
.INIT(64'hAAAAAAAA0A0A0008))
\last_rr_hot[2]_i_4
(.I0(p_54_out),
.I1(p_3_in),
.I2(p_74_out),
.I3(p_32_out),
.I4(p_4_in),
.I5(\last_rr_hot_reg_n_0_[0] ),
.O(next_rr_hot[1]));
LUT6 #(
.INIT(64'h8A8A8A8A88888A88))
\last_rr_hot[2]_i_5
(.I0(p_74_out),
.I1(p_4_in),
.I2(p_32_out),
.I3(\last_rr_hot_reg_n_0_[0] ),
.I4(p_54_out),
.I5(p_3_in),
.O(next_rr_hot[0]));
FDRE \last_rr_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[0]_i_1__0_n_0 ),
.Q(\last_rr_hot_reg_n_0_[0] ),
.R(SR));
FDRE \last_rr_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[1]_i_1__0_n_0 ),
.Q(p_3_in),
.R(SR));
FDSE \last_rr_hot_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[2]_i_1__0_n_0 ),
.Q(p_4_in),
.S(SR));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB3))
\m_payload_i[46]_i_1
(.I0(\m_payload_i_reg[0]_0 ),
.I1(p_74_out),
.I2(s_axi_rready),
.O(\m_payload_i_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'h8F))
\m_payload_i[46]_i_1__1
(.I0(s_axi_rready),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.O(\m_payload_i_reg[34]_0 ));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [10]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [7]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [4]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [1]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [10]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [7]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [4]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [1]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [10]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [11]),
.I5(i__carry_i_7_n_0),
.O(S[3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [7]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [8]),
.I5(i__carry_i_10_n_0),
.O(S[2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [4]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [5]),
.I5(i__carry_i_13_n_0),
.O(S[1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [1]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [2]),
.I5(i__carry_i_16_n_0),
.O(S[0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [10]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [7]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [4]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [1]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [10]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [7]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [4]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [1]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [10]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [7]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [4]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [1]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [10]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [7]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [4]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [1]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [0]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[0]_INST_0
(.I0(\m_payload_i_reg[46] [0]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [0]),
.O(s_axi_rdata[0]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[10]_INST_0
(.I0(\m_payload_i_reg[46] [5]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [5]),
.O(s_axi_rdata[5]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[11]_INST_0
(.I0(\m_payload_i_reg[46] [6]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [6]),
.O(s_axi_rdata[6]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[19]_INST_0
(.I0(\m_payload_i_reg[46] [7]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [7]),
.O(s_axi_rdata[7]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[20]_INST_0
(.I0(\m_payload_i_reg[46] [8]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [8]),
.O(s_axi_rdata[8]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[22]_INST_0
(.I0(\m_payload_i_reg[46] [9]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [9]),
.O(s_axi_rdata[9]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[27]_INST_0
(.I0(\m_payload_i_reg[46] [10]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [10]),
.O(s_axi_rdata[10]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[31]_INST_0
(.I0(\m_payload_i_reg[46] [11]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [11]),
.O(s_axi_rdata[11]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[4]_INST_0
(.I0(\m_payload_i_reg[46] [1]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [1]),
.O(s_axi_rdata[1]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[6]_INST_0
(.I0(\m_payload_i_reg[46] [2]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [2]),
.O(s_axi_rdata[2]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[8]_INST_0
(.I0(\m_payload_i_reg[46] [3]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [3]),
.O(s_axi_rdata[3]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[9]_INST_0
(.I0(\m_payload_i_reg[46] [4]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [4]),
.O(s_axi_rdata[4]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[0]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [14]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [1]),
.I4(\m_payload_i_reg[46]_0 [14]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[0]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[10]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [24]),
.I2(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I3(\m_payload_i_reg[46] [24]),
.I4(\m_payload_i_reg[46]_1 [11]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[10]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[11]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [25]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [12]),
.I4(\m_payload_i_reg[46]_0 [25]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[11]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT4 #(
.INIT(16'hF888))
\s_axi_rid[11]_INST_0_i_1
(.I0(\m_payload_i_reg[34] ),
.I1(p_32_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_54_out),
.O(\s_axi_rid[11]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT4 #(
.INIT(16'h8FFF))
\s_axi_rid[11]_INST_0_i_2
(.I0(\chosen_reg[1]_0 ),
.I1(p_54_out),
.I2(\m_payload_i_reg[34] ),
.I3(p_32_out),
.O(\s_axi_rid[11]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT4 #(
.INIT(16'h8FFF))
\s_axi_rid[11]_INST_0_i_3
(.I0(\m_payload_i_reg[34] ),
.I1(p_32_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_54_out),
.O(\s_axi_rid[11]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[1]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [15]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [15]),
.I4(\m_payload_i_reg[46]_1 [2]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[1]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[2]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [16]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [16]),
.I4(\m_payload_i_reg[46]_1 [3]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[2]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[3]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [17]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [4]),
.I4(\m_payload_i_reg[46] [17]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(s_axi_rid[3]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[4]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [18]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [18]),
.I4(\m_payload_i_reg[46]_1 [5]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[4]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[5]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [19]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [6]),
.I4(\m_payload_i_reg[46]_0 [19]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[5]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[6]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [20]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [20]),
.I4(\m_payload_i_reg[46]_1 [7]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[6]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[7]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [21]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [21]),
.I4(\m_payload_i_reg[46]_1 [8]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[7]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[8]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [22]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [22]),
.I4(\m_payload_i_reg[46]_1 [9]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[8]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[9]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [23]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [10]),
.I4(\m_payload_i_reg[46]_0 [23]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[9]));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\s_axi_rlast[0]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [0]),
.I2(\m_payload_i_reg[46] [13]),
.I3(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I4(\m_payload_i_reg[46]_0 [13]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rlast));
LUT6 #(
.INIT(64'h3FEAEAEA00EAEAEA))
\s_axi_rresp[1]_INST_0
(.I0(\m_payload_i_reg[46] [12]),
.I1(p_32_out),
.I2(\m_payload_i_reg[34] ),
.I3(p_54_out),
.I4(\chosen_reg[1]_0 ),
.I5(\m_payload_i_reg[46]_0 [12]),
.O(s_axi_rresp));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\s_axi_rvalid[0]_INST_0
(.I0(p_54_out),
.I1(\chosen_reg[1]_0 ),
.I2(p_32_out),
.I3(\m_payload_i_reg[34] ),
.I4(\m_payload_i_reg[0]_0 ),
.I5(p_74_out),
.O(s_axi_rvalid));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_PROTOCOL = "0" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "1" *) (* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *) (* C_M_AXI_ADDR_WIDTH = "64'b0000000000000000000000000001000000000000000000000000000000010000" *) (* C_M_AXI_BASE_ADDR = "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "64'b1111111111111111111111111111111111111111111111111111111111111111" *) (* C_M_AXI_READ_ISSUING = "64'b0000000000000000000000000000100000000000000000000000000000001000" *) (* C_M_AXI_SECURE = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "64'b1111111111111111111111111111111111111111111111111111111111111111" *) (* C_M_AXI_WRITE_ISSUING = "64'b0000000000000000000000000000100000000000000000000000000000001000" *) (* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "2" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "0" *)
(* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "8" *)
(* C_S_AXI_SINGLE_THREAD = "0" *) (* C_S_AXI_THREAD_ID_WIDTH = "12" *) (* C_S_AXI_WRITE_ACCEPTANCE = "8" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_crossbar_v2_1_14_axi_crossbar" *) (* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *) (* P_FAMILY = "zynq" *) (* P_INCR = "2'b01" *)
(* P_LEN = "8" *) (* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "2'b11" *) (* P_M_AXI_SUPPORTS_WRITE = "2'b11" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *) (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000111111111111" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *) (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wuser;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_ruser;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [23:0]m_axi_awid;
output [63:0]m_axi_awaddr;
output [15:0]m_axi_awlen;
output [5:0]m_axi_awsize;
output [3:0]m_axi_awburst;
output [1:0]m_axi_awlock;
output [7:0]m_axi_awcache;
output [5:0]m_axi_awprot;
output [7:0]m_axi_awregion;
output [7:0]m_axi_awqos;
output [1:0]m_axi_awuser;
output [1:0]m_axi_awvalid;
input [1:0]m_axi_awready;
output [23:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output [1:0]m_axi_wlast;
output [1:0]m_axi_wuser;
output [1:0]m_axi_wvalid;
input [1:0]m_axi_wready;
input [23:0]m_axi_bid;
input [3:0]m_axi_bresp;
input [1:0]m_axi_buser;
input [1:0]m_axi_bvalid;
output [1:0]m_axi_bready;
output [23:0]m_axi_arid;
output [63:0]m_axi_araddr;
output [15:0]m_axi_arlen;
output [5:0]m_axi_arsize;
output [3:0]m_axi_arburst;
output [1:0]m_axi_arlock;
output [7:0]m_axi_arcache;
output [5:0]m_axi_arprot;
output [7:0]m_axi_arregion;
output [7:0]m_axi_arqos;
output [1:0]m_axi_aruser;
output [1:0]m_axi_arvalid;
input [1:0]m_axi_arready;
input [23:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [3:0]m_axi_rresp;
input [1:0]m_axi_rlast;
input [1:0]m_axi_ruser;
input [1:0]m_axi_rvalid;
output [1:0]m_axi_rready;
wire \<const0> ;
wire aclk;
wire aresetn;
wire [63:32]\^m_axi_araddr ;
wire [3:2]\^m_axi_arburst ;
wire [7:4]\^m_axi_arcache ;
wire [11:0]\^m_axi_arid ;
wire [7:0]\^m_axi_arlen ;
wire [1:1]\^m_axi_arlock ;
wire [5:3]\^m_axi_arprot ;
wire [7:4]\^m_axi_arqos ;
wire [1:0]m_axi_arready;
wire [5:3]\^m_axi_arsize ;
wire [1:0]m_axi_arvalid;
wire [63:32]\^m_axi_awaddr ;
wire [3:2]\^m_axi_awburst ;
wire [7:4]\^m_axi_awcache ;
wire [11:0]\^m_axi_awid ;
wire [15:8]\^m_axi_awlen ;
wire [1:1]\^m_axi_awlock ;
wire [5:3]\^m_axi_awprot ;
wire [7:4]\^m_axi_awqos ;
wire [1:0]m_axi_awready;
wire [5:3]\^m_axi_awsize ;
wire [1:0]m_axi_awvalid;
wire [23:0]m_axi_bid;
wire [1:0]m_axi_bready;
wire [3:0]m_axi_bresp;
wire [1:0]m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [23:0]m_axi_rid;
wire [1:0]m_axi_rlast;
wire [1:0]m_axi_rready;
wire [3:0]m_axi_rresp;
wire [1:0]m_axi_rvalid;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
assign m_axi_araddr[63:32] = \^m_axi_araddr [63:32];
assign m_axi_araddr[31:0] = \^m_axi_araddr [63:32];
assign m_axi_arburst[3:2] = \^m_axi_arburst [3:2];
assign m_axi_arburst[1:0] = \^m_axi_arburst [3:2];
assign m_axi_arcache[7:4] = \^m_axi_arcache [7:4];
assign m_axi_arcache[3:0] = \^m_axi_arcache [7:4];
assign m_axi_arid[23:12] = \^m_axi_arid [11:0];
assign m_axi_arid[11:0] = \^m_axi_arid [11:0];
assign m_axi_arlen[15:8] = \^m_axi_arlen [7:0];
assign m_axi_arlen[7:0] = \^m_axi_arlen [7:0];
assign m_axi_arlock[1] = \^m_axi_arlock [1];
assign m_axi_arlock[0] = \^m_axi_arlock [1];
assign m_axi_arprot[5:3] = \^m_axi_arprot [5:3];
assign m_axi_arprot[2:0] = \^m_axi_arprot [5:3];
assign m_axi_arqos[7:4] = \^m_axi_arqos [7:4];
assign m_axi_arqos[3:0] = \^m_axi_arqos [7:4];
assign m_axi_arregion[7] = \<const0> ;
assign m_axi_arregion[6] = \<const0> ;
assign m_axi_arregion[5] = \<const0> ;
assign m_axi_arregion[4] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[5:3] = \^m_axi_arsize [5:3];
assign m_axi_arsize[2:0] = \^m_axi_arsize [5:3];
assign m_axi_aruser[1] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awaddr[63:32] = \^m_axi_awaddr [63:32];
assign m_axi_awaddr[31:0] = \^m_axi_awaddr [63:32];
assign m_axi_awburst[3:2] = \^m_axi_awburst [3:2];
assign m_axi_awburst[1:0] = \^m_axi_awburst [3:2];
assign m_axi_awcache[7:4] = \^m_axi_awcache [7:4];
assign m_axi_awcache[3:0] = \^m_axi_awcache [7:4];
assign m_axi_awid[23:12] = \^m_axi_awid [11:0];
assign m_axi_awid[11:0] = \^m_axi_awid [11:0];
assign m_axi_awlen[15:8] = \^m_axi_awlen [15:8];
assign m_axi_awlen[7:0] = \^m_axi_awlen [15:8];
assign m_axi_awlock[1] = \^m_axi_awlock [1];
assign m_axi_awlock[0] = \^m_axi_awlock [1];
assign m_axi_awprot[5:3] = \^m_axi_awprot [5:3];
assign m_axi_awprot[2:0] = \^m_axi_awprot [5:3];
assign m_axi_awqos[7:4] = \^m_axi_awqos [7:4];
assign m_axi_awqos[3:0] = \^m_axi_awqos [7:4];
assign m_axi_awregion[7] = \<const0> ;
assign m_axi_awregion[6] = \<const0> ;
assign m_axi_awregion[5] = \<const0> ;
assign m_axi_awregion[4] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[5:3] = \^m_axi_awsize [5:3];
assign m_axi_awsize[2:0] = \^m_axi_awsize [5:3];
assign m_axi_awuser[1] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[63:32] = s_axi_wdata;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[23] = \<const0> ;
assign m_axi_wid[22] = \<const0> ;
assign m_axi_wid[21] = \<const0> ;
assign m_axi_wid[20] = \<const0> ;
assign m_axi_wid[19] = \<const0> ;
assign m_axi_wid[18] = \<const0> ;
assign m_axi_wid[17] = \<const0> ;
assign m_axi_wid[16] = \<const0> ;
assign m_axi_wid[15] = \<const0> ;
assign m_axi_wid[14] = \<const0> ;
assign m_axi_wid[13] = \<const0> ;
assign m_axi_wid[12] = \<const0> ;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast[1] = s_axi_wlast;
assign m_axi_wlast[0] = s_axi_wlast;
assign m_axi_wstrb[7:4] = s_axi_wstrb;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[1] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar \gen_samd.crossbar_samd
(.D({s_axi_awqos,s_axi_awcache,s_axi_awburst,s_axi_awprot,s_axi_awlock,s_axi_awsize,s_axi_awlen,s_axi_awaddr}),
.M_AXI_RREADY(m_axi_rready),
.Q({\^m_axi_awqos ,\^m_axi_awcache ,\^m_axi_awburst ,\^m_axi_awprot ,\^m_axi_awlock ,\^m_axi_awsize ,\^m_axi_awlen ,\^m_axi_awaddr ,\^m_axi_awid }),
.S_AXI_ARREADY(s_axi_arready),
.aclk(aclk),
.aresetn(aresetn),
.\m_axi_arqos[7] ({\^m_axi_arqos ,\^m_axi_arcache ,\^m_axi_arburst ,\^m_axi_arprot ,\^m_axi_arlock ,\^m_axi_arsize ,\^m_axi_arlen ,\^m_axi_araddr ,\^m_axi_arid }),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_arid(s_axi_arid),
.\s_axi_arqos[3] ({s_axi_arqos,s_axi_arcache,s_axi_arburst,s_axi_arprot,s_axi_arlock,s_axi_arsize,s_axi_arlen,s_axi_araddr}),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_crossbar" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar
(S_AXI_ARREADY,
Q,
\m_axi_arqos[7] ,
m_axi_bready,
M_AXI_RREADY,
m_axi_awvalid,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_awready,
s_axi_rlast,
s_axi_rvalid,
s_axi_rresp,
s_axi_rid,
s_axi_rdata,
m_axi_arvalid,
m_axi_wvalid,
s_axi_wready,
m_axi_awready,
m_axi_bvalid,
s_axi_bready,
aclk,
s_axi_arid,
s_axi_awid,
s_axi_awvalid,
m_axi_bid,
m_axi_bresp,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
aresetn,
D,
\s_axi_arqos[3] ,
s_axi_arvalid,
m_axi_rvalid,
s_axi_rready,
m_axi_arready,
s_axi_wvalid,
s_axi_wlast,
m_axi_wready);
output [0:0]S_AXI_ARREADY;
output [68:0]Q;
output [68:0]\m_axi_arqos[7] ;
output [1:0]m_axi_bready;
output [1:0]M_AXI_RREADY;
output [1:0]m_axi_awvalid;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
output [0:0]s_axi_awready;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
output [1:0]s_axi_rresp;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]m_axi_arvalid;
output [1:0]m_axi_wvalid;
output [0:0]s_axi_wready;
input [1:0]m_axi_awready;
input [1:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input aclk;
input [11:0]s_axi_arid;
input [11:0]s_axi_awid;
input [0:0]s_axi_awvalid;
input [23:0]m_axi_bid;
input [3:0]m_axi_bresp;
input [23:0]m_axi_rid;
input [1:0]m_axi_rlast;
input [3:0]m_axi_rresp;
input [63:0]m_axi_rdata;
input aresetn;
input [56:0]D;
input [56:0]\s_axi_arqos[3] ;
input [0:0]s_axi_arvalid;
input [1:0]m_axi_rvalid;
input [0:0]s_axi_rready;
input [1:0]m_axi_arready;
input [0:0]s_axi_wvalid;
input [0:0]s_axi_wlast;
input [1:0]m_axi_wready;
wire [56:0]D;
wire [1:0]M_AXI_RREADY;
wire [68:0]Q;
wire [0:0]S_AXI_ARREADY;
wire [2:2]aa_mi_artarget_hot;
wire aa_mi_arvalid;
wire [2:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire addr_arbiter_ar_n_2;
wire addr_arbiter_ar_n_3;
wire addr_arbiter_ar_n_4;
wire addr_arbiter_ar_n_5;
wire addr_arbiter_ar_n_6;
wire addr_arbiter_ar_n_7;
wire addr_arbiter_ar_n_80;
wire addr_arbiter_ar_n_81;
wire addr_arbiter_ar_n_82;
wire addr_arbiter_ar_n_84;
wire addr_arbiter_ar_n_85;
wire addr_arbiter_aw_n_10;
wire addr_arbiter_aw_n_11;
wire addr_arbiter_aw_n_12;
wire addr_arbiter_aw_n_13;
wire addr_arbiter_aw_n_14;
wire addr_arbiter_aw_n_15;
wire addr_arbiter_aw_n_16;
wire addr_arbiter_aw_n_2;
wire addr_arbiter_aw_n_20;
wire addr_arbiter_aw_n_21;
wire addr_arbiter_aw_n_3;
wire addr_arbiter_aw_n_7;
wire addr_arbiter_aw_n_8;
wire addr_arbiter_aw_n_9;
wire aresetn;
wire aresetn_d;
wire \gen_decerr_slave.decerr_slave_inst_n_7 ;
wire \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ;
wire \gen_master_slots[0].reg_slice_mi_n_4 ;
wire \gen_master_slots[0].reg_slice_mi_n_5 ;
wire \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ;
wire \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ;
wire \gen_master_slots[1].reg_slice_mi_n_12 ;
wire \gen_master_slots[1].reg_slice_mi_n_20 ;
wire \gen_master_slots[1].reg_slice_mi_n_21 ;
wire \gen_master_slots[1].reg_slice_mi_n_22 ;
wire \gen_master_slots[1].reg_slice_mi_n_23 ;
wire \gen_master_slots[1].reg_slice_mi_n_26 ;
wire \gen_master_slots[1].reg_slice_mi_n_27 ;
wire \gen_master_slots[1].reg_slice_mi_n_5 ;
wire \gen_master_slots[1].reg_slice_mi_n_6 ;
wire \gen_master_slots[1].reg_slice_mi_n_75 ;
wire \gen_master_slots[1].reg_slice_mi_n_76 ;
wire \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ;
wire \gen_master_slots[2].reg_slice_mi_n_1 ;
wire \gen_master_slots[2].reg_slice_mi_n_13 ;
wire \gen_master_slots[2].reg_slice_mi_n_19 ;
wire \gen_master_slots[2].reg_slice_mi_n_20 ;
wire \gen_master_slots[2].reg_slice_mi_n_21 ;
wire \gen_master_slots[2].reg_slice_mi_n_22 ;
wire \gen_master_slots[2].reg_slice_mi_n_23 ;
wire \gen_master_slots[2].reg_slice_mi_n_24 ;
wire \gen_master_slots[2].reg_slice_mi_n_25 ;
wire \gen_master_slots[2].reg_slice_mi_n_26 ;
wire \gen_master_slots[2].reg_slice_mi_n_27 ;
wire \gen_master_slots[2].reg_slice_mi_n_28 ;
wire \gen_master_slots[2].reg_slice_mi_n_29 ;
wire \gen_master_slots[2].reg_slice_mi_n_30 ;
wire \gen_master_slots[2].reg_slice_mi_n_31 ;
wire \gen_master_slots[2].reg_slice_mi_n_45 ;
wire \gen_master_slots[2].reg_slice_mi_n_5 ;
wire [2:0]\gen_multi_thread.arbiter_resp_inst/chosen ;
wire [2:0]\gen_multi_thread.arbiter_resp_inst/chosen_1 ;
wire [8:6]\gen_multi_thread.gen_thread_loop[0].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[1].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[2].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[3].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[4].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[5].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[6].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[7].active_id_reg ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8 ;
wire \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3 ;
wire \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3 ;
wire [68:0]\m_axi_arqos[7] ;
wire [1:0]m_axi_arready;
wire [1:0]m_axi_arvalid;
wire [1:0]m_axi_awready;
wire [1:0]m_axi_awvalid;
wire [23:0]m_axi_bid;
wire [1:0]m_axi_bready;
wire [3:0]m_axi_bresp;
wire [1:0]m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [23:0]m_axi_rid;
wire [1:0]m_axi_rlast;
wire [3:0]m_axi_rresp;
wire [1:0]m_axi_rvalid;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [1:0]m_ready_d;
wire [1:0]m_ready_d_3;
wire m_valid_i;
wire m_valid_i_2;
wire mi_arready_2;
wire mi_awready_2;
wire mi_bready_2;
wire mi_rready_2;
wire p_14_in;
wire p_15_in;
wire p_17_in;
wire p_1_in;
wire [11:0]p_20_in;
wire p_21_in;
wire [11:0]p_24_in;
wire p_32_out;
wire p_34_out;
wire p_38_out;
wire p_54_out;
wire p_56_out;
wire p_60_out;
wire p_74_out;
wire p_76_out;
wire p_80_out;
wire [16:0]r_issuing_cnt;
wire \r_pipe/p_1_in ;
wire \r_pipe/p_1_in_0 ;
wire reset;
wire [11:0]s_axi_arid;
wire [56:0]\s_axi_arqos[3] ;
wire [0:0]s_axi_arvalid;
wire [11:0]s_axi_awid;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire s_axi_rlast_i0;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire s_axi_rvalid_i;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire ss_aa_awready;
wire ss_wr_awready;
wire ss_wr_awvalid;
wire [1:0]st_aa_artarget_hot;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire [34:0]st_mr_bid;
wire [1:0]st_mr_bmesg;
wire [35:0]st_mr_rid;
wire [69:0]st_mr_rmesg;
wire [16:0]w_issuing_cnt;
wire [1:1]write_cs;
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter addr_arbiter_ar
(.D({addr_arbiter_ar_n_2,addr_arbiter_ar_n_3,addr_arbiter_ar_n_4}),
.E(s_axi_rvalid_i),
.Q(p_56_out),
.SR(reset),
.aa_mi_arvalid(aa_mi_arvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.aresetn_d_reg(\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0 ),
.aresetn_d_reg_0(\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3 ),
.\chosen_reg[0] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2 ),
.\gen_axi.read_cnt_reg[5] (\gen_decerr_slave.decerr_slave_inst_n_7 ),
.\gen_axi.s_axi_rid_i_reg[11] (aa_mi_artarget_hot),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (addr_arbiter_ar_n_84),
.\gen_master_slots[1].r_issuing_cnt_reg[11] ({addr_arbiter_ar_n_5,addr_arbiter_ar_n_6,addr_arbiter_ar_n_7}),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (addr_arbiter_ar_n_85),
.\gen_master_slots[2].r_issuing_cnt_reg[16] (\gen_master_slots[2].reg_slice_mi_n_31 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8 ),
.\gen_multi_thread.gen_thread_loop[7].active_target_reg[57] (addr_arbiter_ar_n_82),
.\gen_no_arbiter.m_target_hot_i_reg[0]_0 (st_aa_artarget_hot[0]),
.\gen_no_arbiter.m_valid_i_reg_0 (addr_arbiter_ar_n_80),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (addr_arbiter_ar_n_81),
.\m_axi_arqos[7] (\m_axi_arqos[7] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[34] (\gen_master_slots[0].reg_slice_mi_n_5 ),
.\m_payload_i_reg[34]_0 (\gen_master_slots[1].reg_slice_mi_n_27 ),
.m_valid_i(m_valid_i),
.m_valid_i_reg(\gen_master_slots[1].reg_slice_mi_n_75 ),
.mi_arready_2(mi_arready_2),
.p_15_in(p_15_in),
.r_issuing_cnt({r_issuing_cnt[11:8],r_issuing_cnt[3:0]}),
.\s_axi_araddr[25] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7 ),
.\s_axi_araddr[28] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6 ),
.\s_axi_araddr[30] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5 ),
.\s_axi_arqos[3] ({\s_axi_arqos[3] ,s_axi_arid}),
.\s_axi_arready[0] (S_AXI_ARREADY),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rlast_i0(s_axi_rlast_i0),
.s_axi_rready(s_axi_rready),
.st_aa_artarget_hot(st_aa_artarget_hot[1]));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 addr_arbiter_aw
(.D({addr_arbiter_aw_n_7,addr_arbiter_aw_n_8,addr_arbiter_aw_n_9}),
.E(addr_arbiter_aw_n_15),
.Q(Q),
.SR(reset),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.aresetn_d_reg(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0 ),
.aresetn_d_reg_0(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6 ),
.\chosen_reg[0] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2 ),
.\chosen_reg[1] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37 ),
.\gen_master_slots[0].w_issuing_cnt_reg[0] (addr_arbiter_aw_n_16),
.\gen_master_slots[0].w_issuing_cnt_reg[3] ({addr_arbiter_aw_n_11,addr_arbiter_aw_n_12,addr_arbiter_aw_n_13}),
.\gen_master_slots[1].w_issuing_cnt_reg[9] (addr_arbiter_aw_n_10),
.\gen_master_slots[2].w_issuing_cnt_reg[16] (addr_arbiter_aw_n_14),
.\gen_no_arbiter.m_target_hot_i_reg[2]_0 (addr_arbiter_aw_n_20),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_ready_d(m_ready_d_3),
.m_ready_d_0(m_ready_d[0]),
.\m_ready_d_reg[0] (addr_arbiter_aw_n_2),
.\m_ready_d_reg[1] (addr_arbiter_aw_n_3),
.\m_ready_d_reg[1]_0 (addr_arbiter_aw_n_21),
.m_valid_i(m_valid_i_2),
.m_valid_i_reg(\gen_master_slots[1].reg_slice_mi_n_6 ),
.mi_awready_2(mi_awready_2),
.\s_axi_awaddr[20] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10 ),
.\s_axi_awaddr[26] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11 ),
.\s_axi_awqos[3] ({D,s_axi_awid}),
.s_axi_bready(s_axi_bready),
.ss_aa_awready(ss_aa_awready),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.w_issuing_cnt({w_issuing_cnt[11:8],w_issuing_cnt[3:0]}));
FDRE #(
.INIT(1'b0))
aresetn_d_reg
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(aresetn_d),
.R(1'b0));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave \gen_decerr_slave.decerr_slave_inst
(.E(s_axi_rvalid_i),
.Q(p_24_in),
.SR(reset),
.aa_mi_arvalid(aa_mi_arvalid),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot[2]),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axi.s_axi_arready_i_reg_0 (\gen_decerr_slave.decerr_slave_inst_n_7 ),
.\gen_axi.write_cs_reg[1]_0 (write_cs),
.\gen_no_arbiter.m_mesg_i_reg[11] (Q[11:0]),
.\gen_no_arbiter.m_mesg_i_reg[51] ({\m_axi_arqos[7] [51:44],\m_axi_arqos[7] [11:0]}),
.\gen_no_arbiter.m_target_hot_i_reg[2] (aa_mi_artarget_hot),
.\gen_no_arbiter.m_valid_i_reg (addr_arbiter_aw_n_10),
.m_ready_d(m_ready_d_3[1]),
.\m_ready_d_reg[1] (addr_arbiter_aw_n_14),
.mi_arready_2(mi_arready_2),
.mi_awready_2(mi_awready_2),
.mi_bready_2(mi_bready_2),
.mi_rready_2(mi_rready_2),
.p_14_in(p_14_in),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.p_21_in(p_21_in),
.s_axi_rlast_i0(s_axi_rlast_i0),
.\skid_buffer_reg[46] (p_20_in),
.\storage_data1_reg[0] (\gen_slave_slots[0].gen_si_write.wdata_router_w_n_3 ));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[0].r_issuing_cnt[0]_i_1
(.I0(r_issuing_cnt[0]),
.O(\gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[0]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(\gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ),
.Q(r_issuing_cnt[0]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[1]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(addr_arbiter_ar_n_4),
.Q(r_issuing_cnt[1]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[2]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(addr_arbiter_ar_n_3),
.Q(r_issuing_cnt[2]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[3]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(addr_arbiter_ar_n_2),
.Q(r_issuing_cnt[3]),
.R(reset));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice \gen_master_slots[0].reg_slice_mi
(.D({m_axi_bid[11:0],m_axi_bresp[1:0]}),
.E(\r_pipe/p_1_in_0 ),
.Q(r_issuing_cnt[3:0]),
.aclk(aclk),
.\aresetn_d_reg[1] (\gen_master_slots[2].reg_slice_mi_n_1 ),
.\aresetn_d_reg[1]_0 (\gen_master_slots[2].reg_slice_mi_n_5 ),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 [0]),
.chosen_0(\gen_multi_thread.arbiter_resp_inst/chosen [0]),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].reg_slice_mi_n_5 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ({st_mr_bid[11:0],st_mr_bmesg}),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ({st_mr_rid[11:0],p_76_out,st_mr_rmesg[1:0],st_mr_rmesg[34:3]}),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[0].reg_slice_mi_n_4 ),
.m_axi_bready(m_axi_bready[0]),
.m_axi_bvalid(m_axi_bvalid[0]),
.m_axi_rdata(m_axi_rdata[31:0]),
.m_axi_rid(m_axi_rid[11:0]),
.m_axi_rlast(m_axi_rlast[0]),
.\m_axi_rready[0] (M_AXI_RREADY[0]),
.m_axi_rresp(m_axi_rresp[1:0]),
.m_axi_rvalid(m_axi_rvalid[0]),
.p_1_in(p_1_in),
.p_74_out(p_74_out),
.p_80_out(p_80_out),
.s_axi_bready(s_axi_bready),
.s_axi_rready(s_axi_rready));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[0].w_issuing_cnt[0]_i_1
(.I0(w_issuing_cnt[0]),
.O(\gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[0]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(\gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ),
.Q(w_issuing_cnt[0]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[1]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(addr_arbiter_aw_n_13),
.Q(w_issuing_cnt[1]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[2]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(addr_arbiter_aw_n_12),
.Q(w_issuing_cnt[2]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[3]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(addr_arbiter_aw_n_11),
.Q(w_issuing_cnt[3]),
.R(reset));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[1].r_issuing_cnt[8]_i_1
(.I0(r_issuing_cnt[8]),
.O(\gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[10]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(addr_arbiter_ar_n_6),
.Q(r_issuing_cnt[10]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[11]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(addr_arbiter_ar_n_5),
.Q(r_issuing_cnt[11]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[8]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(\gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ),
.Q(r_issuing_cnt[8]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[9]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(addr_arbiter_ar_n_7),
.Q(r_issuing_cnt[9]),
.R(reset));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 \gen_master_slots[1].reg_slice_mi
(.D({m_axi_bid[23:12],m_axi_bresp[3:2]}),
.Q(w_issuing_cnt[11:8]),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1] (\gen_master_slots[1].reg_slice_mi_n_76 ),
.\aresetn_d_reg[1]_0 (\gen_master_slots[2].reg_slice_mi_n_1 ),
.\aresetn_d_reg[1]_1 (\gen_master_slots[2].reg_slice_mi_n_5 ),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 [2:1]),
.chosen_0(\gen_multi_thread.arbiter_resp_inst/chosen [2:1]),
.\gen_master_slots[1].r_issuing_cnt_reg[11] (\gen_master_slots[1].reg_slice_mi_n_75 ),
.\gen_master_slots[1].r_issuing_cnt_reg[11]_0 (r_issuing_cnt[11:8]),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].reg_slice_mi_n_27 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_master_slots[1].reg_slice_mi_n_6 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_master_slots[1].reg_slice_mi_n_12 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ({st_mr_bid[23],st_mr_bid[21:18],st_mr_bid[16],st_mr_bid[12]}),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_master_slots[1].reg_slice_mi_n_20 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_master_slots[1].reg_slice_mi_n_21 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 (\gen_master_slots[1].reg_slice_mi_n_22 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 (\gen_master_slots[1].reg_slice_mi_n_23 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ({st_mr_rid[23:12],p_56_out,st_mr_rmesg[36],st_mr_rmesg[69],st_mr_rmesg[65],st_mr_rmesg[60],st_mr_rmesg[58:57],st_mr_rmesg[49:46],st_mr_rmesg[44],st_mr_rmesg[42],st_mr_rmesg[38]}),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_master_slots[1].reg_slice_mi_n_5 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[1].reg_slice_mi_n_26 ),
.m_axi_bready(m_axi_bready[1]),
.m_axi_bvalid(m_axi_bvalid[1]),
.m_axi_rdata(m_axi_rdata[63:32]),
.m_axi_rid(m_axi_rid[23:12]),
.m_axi_rlast(m_axi_rlast[1]),
.\m_axi_rready[1] (M_AXI_RREADY[1]),
.m_axi_rresp(m_axi_rresp[3:2]),
.m_axi_rvalid(m_axi_rvalid[1]),
.\m_payload_i_reg[12] ({st_mr_bid[34],st_mr_bid[29],st_mr_bid[27:25],st_mr_bid[10],st_mr_bid[5],st_mr_bid[3:1]}),
.\m_payload_i_reg[1] (st_mr_bmesg),
.\m_payload_i_reg[32] ({st_mr_rmesg[0],st_mr_rmesg[33:31],st_mr_rmesg[29:26],st_mr_rmesg[24],st_mr_rmesg[21:15],st_mr_rmesg[10],st_mr_rmesg[8],st_mr_rmesg[6:4]}),
.p_1_in(p_1_in),
.p_32_out(p_32_out),
.p_38_out(p_38_out),
.p_54_out(p_54_out),
.p_60_out(p_60_out),
.s_axi_bid({s_axi_bid[10],s_axi_bid[5],s_axi_bid[3:1]}),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_rdata({s_axi_rdata[30:28],s_axi_rdata[26:23],s_axi_rdata[21],s_axi_rdata[18:12],s_axi_rdata[7],s_axi_rdata[5],s_axi_rdata[3:1]}),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp[0]));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[1].w_issuing_cnt[8]_i_1
(.I0(w_issuing_cnt[8]),
.O(\gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[10]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(addr_arbiter_aw_n_8),
.Q(w_issuing_cnt[10]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[11]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(addr_arbiter_aw_n_7),
.Q(w_issuing_cnt[11]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[8]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(\gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ),
.Q(w_issuing_cnt[8]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[9]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(addr_arbiter_aw_n_9),
.Q(w_issuing_cnt[9]),
.R(reset));
FDRE \gen_master_slots[2].r_issuing_cnt_reg[16]
(.C(aclk),
.CE(1'b1),
.D(\gen_master_slots[2].reg_slice_mi_n_45 ),
.Q(r_issuing_cnt[16]),
.R(reset));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 \gen_master_slots[2].reg_slice_mi
(.D(p_24_in),
.E(\r_pipe/p_1_in ),
.Q({st_mr_bid[34],st_mr_bid[29],st_mr_bid[27:25]}),
.S(\gen_master_slots[2].reg_slice_mi_n_20 ),
.aclk(aclk),
.\aresetn_d_reg[0] (\gen_master_slots[1].reg_slice_mi_n_76 ),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 [2]),
.chosen_0(\gen_multi_thread.arbiter_resp_inst/chosen [2]),
.\gen_axi.s_axi_arready_i_reg (addr_arbiter_ar_n_80),
.\gen_axi.s_axi_rid_i_reg[11] (p_20_in),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].reg_slice_mi_n_4 ),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].reg_slice_mi_n_26 ),
.\gen_master_slots[2].r_issuing_cnt_reg[16] (\gen_master_slots[2].reg_slice_mi_n_45 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_master_slots[2].reg_slice_mi_n_13 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 (\gen_master_slots[2].reg_slice_mi_n_19 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_master_slots[2].reg_slice_mi_n_28 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_master_slots[2].reg_slice_mi_n_29 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] (\gen_multi_thread.gen_thread_loop[0].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_master_slots[2].reg_slice_mi_n_21 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] (\gen_multi_thread.gen_thread_loop[1].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_master_slots[2].reg_slice_mi_n_22 ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] (\gen_multi_thread.gen_thread_loop[2].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] (\gen_master_slots[2].reg_slice_mi_n_23 ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] (\gen_multi_thread.gen_thread_loop[3].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_master_slots[2].reg_slice_mi_n_24 ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] (\gen_multi_thread.gen_thread_loop[4].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_master_slots[2].reg_slice_mi_n_25 ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] (\gen_multi_thread.gen_thread_loop[5].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_master_slots[2].reg_slice_mi_n_26 ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] (\gen_multi_thread.gen_thread_loop[6].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_master_slots[2].reg_slice_mi_n_27 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ({st_mr_rid[35:24],p_34_out}),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] (\gen_multi_thread.gen_thread_loop[7].active_id_reg ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_master_slots[2].reg_slice_mi_n_30 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[2].reg_slice_mi_n_31 ),
.\m_payload_i_reg[13] ({st_mr_bid[23],st_mr_bid[21:18],st_mr_bid[16],st_mr_bid[12:11],st_mr_bid[9:6],st_mr_bid[4],st_mr_bid[0]}),
.m_valid_i_reg(\gen_master_slots[2].reg_slice_mi_n_1 ),
.m_valid_i_reg_0(\gen_master_slots[1].reg_slice_mi_n_6 ),
.mi_bready_2(mi_bready_2),
.mi_rready_2(mi_rready_2),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.p_1_in(p_1_in),
.p_21_in(p_21_in),
.p_32_out(p_32_out),
.p_38_out(p_38_out),
.r_issuing_cnt(r_issuing_cnt[16]),
.s_axi_bid({s_axi_bid[11],s_axi_bid[9:6],s_axi_bid[4],s_axi_bid[0]}),
.s_axi_bready(s_axi_bready),
.s_axi_rready(s_axi_rready),
.s_ready_i_reg(\gen_master_slots[2].reg_slice_mi_n_5 ),
.st_aa_artarget_hot(st_aa_artarget_hot),
.w_issuing_cnt(w_issuing_cnt[16]));
FDRE \gen_master_slots[2].w_issuing_cnt_reg[16]
(.C(aclk),
.CE(1'b1),
.D(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38 ),
.Q(w_issuing_cnt[16]),
.R(reset));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor \gen_slave_slots[0].gen_si_read.si_transactor_ar
(.E(\r_pipe/p_1_in_0 ),
.SR(reset),
.aclk(aclk),
.aresetn_d(aresetn_d),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen ),
.\gen_multi_thread.accept_cnt_reg[2]_0 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2 ),
.\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5 ),
.\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6 ),
.\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3 ),
.\gen_no_arbiter.m_target_hot_i_reg[2]_0 (aa_mi_artarget_hot),
.\gen_no_arbiter.m_valid_i_reg (addr_arbiter_ar_n_81),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8 ),
.\gen_no_arbiter.s_ready_i_reg[0]_1 (S_AXI_ARREADY),
.\m_payload_i_reg[34] (\r_pipe/p_1_in ),
.\m_payload_i_reg[46] ({st_mr_rid[11:0],p_76_out,st_mr_rmesg[1],st_mr_rmesg[34],st_mr_rmesg[30],st_mr_rmesg[25],st_mr_rmesg[23:22],st_mr_rmesg[14:11],st_mr_rmesg[9],st_mr_rmesg[7],st_mr_rmesg[3]}),
.\m_payload_i_reg[46]_0 ({st_mr_rid[23:12],p_56_out,st_mr_rmesg[36],st_mr_rmesg[69],st_mr_rmesg[65],st_mr_rmesg[60],st_mr_rmesg[58:57],st_mr_rmesg[49:46],st_mr_rmesg[44],st_mr_rmesg[42],st_mr_rmesg[38]}),
.\m_payload_i_reg[46]_1 ({st_mr_rid[35:24],p_34_out}),
.m_valid_i(m_valid_i),
.p_32_out(p_32_out),
.p_54_out(p_54_out),
.p_74_out(p_74_out),
.\s_axi_araddr[25] (st_aa_artarget_hot[0]),
.\s_axi_araddr[25]_0 (addr_arbiter_ar_n_82),
.\s_axi_araddr[31] ({\s_axi_arqos[3] [31:16],s_axi_arid}),
.s_axi_rdata({s_axi_rdata[31],s_axi_rdata[27],s_axi_rdata[22],s_axi_rdata[20:19],s_axi_rdata[11:8],s_axi_rdata[6],s_axi_rdata[4],s_axi_rdata[0]}),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp[1]),
.s_axi_rvalid(s_axi_rvalid),
.st_aa_artarget_hot(st_aa_artarget_hot[1]));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0 \gen_slave_slots[0].gen_si_write.si_transactor_aw
(.D(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8 ),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg ),
.S(\gen_master_slots[2].reg_slice_mi_n_20 ),
.SR(reset),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot[2]),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 ),
.\gen_master_slots[0].w_issuing_cnt_reg[1] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2 ),
.\gen_master_slots[1].w_issuing_cnt_reg[10] (\gen_master_slots[1].reg_slice_mi_n_5 ),
.\gen_master_slots[1].w_issuing_cnt_reg[8] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37 ),
.\gen_master_slots[2].w_issuing_cnt_reg[16] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38 ),
.\gen_master_slots[2].w_issuing_cnt_reg[16]_0 (\gen_master_slots[2].reg_slice_mi_n_30 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 (\gen_multi_thread.gen_thread_loop[1].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 (\gen_master_slots[2].reg_slice_mi_n_21 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 (\gen_multi_thread.gen_thread_loop[2].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 (\gen_master_slots[2].reg_slice_mi_n_22 ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 (\gen_multi_thread.gen_thread_loop[3].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 (\gen_master_slots[2].reg_slice_mi_n_23 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 (\gen_multi_thread.gen_thread_loop[4].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 (\gen_master_slots[2].reg_slice_mi_n_24 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 (\gen_multi_thread.gen_thread_loop[5].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 (\gen_master_slots[2].reg_slice_mi_n_25 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 (\gen_multi_thread.gen_thread_loop[6].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 (\gen_master_slots[2].reg_slice_mi_n_26 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 (\gen_multi_thread.gen_thread_loop[7].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 (\gen_master_slots[2].reg_slice_mi_n_27 ),
.\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10 ),
.\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (addr_arbiter_aw_n_20),
.\m_payload_i_reg[11] (\gen_master_slots[2].reg_slice_mi_n_28 ),
.\m_payload_i_reg[12] (\gen_master_slots[1].reg_slice_mi_n_23 ),
.\m_payload_i_reg[13] (\gen_master_slots[2].reg_slice_mi_n_29 ),
.\m_payload_i_reg[2] (\gen_master_slots[2].reg_slice_mi_n_13 ),
.\m_payload_i_reg[3] (\gen_master_slots[1].reg_slice_mi_n_12 ),
.\m_payload_i_reg[4] (\gen_master_slots[1].reg_slice_mi_n_20 ),
.\m_payload_i_reg[5] (\gen_master_slots[1].reg_slice_mi_n_21 ),
.\m_payload_i_reg[6] (\gen_master_slots[2].reg_slice_mi_n_19 ),
.\m_payload_i_reg[7] (\gen_master_slots[1].reg_slice_mi_n_22 ),
.\m_ready_d_reg[1] (\gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3 ),
.\m_ready_d_reg[1]_0 (addr_arbiter_aw_n_14),
.m_valid_i(m_valid_i_2),
.m_valid_i_reg(\gen_master_slots[1].reg_slice_mi_n_6 ),
.p_38_out(p_38_out),
.p_60_out(p_60_out),
.p_80_out(p_80_out),
.\s_axi_awaddr[31] ({D[31:16],s_axi_awid}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.w_issuing_cnt({w_issuing_cnt[16],w_issuing_cnt[3:0]}));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter \gen_slave_slots[0].gen_si_write.splitter_aw_si
(.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3 ),
.m_ready_d(m_ready_d),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.ss_aa_awready(ss_aa_awready),
.ss_wr_awready(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router \gen_slave_slots[0].gen_si_write.wdata_router_w
(.D(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8 ),
.SR(reset),
.aclk(aclk),
.\gen_axi.write_cs_reg[1] (\gen_slave_slots[0].gen_si_write.wdata_router_w_n_3 ),
.\gen_axi.write_cs_reg[1]_0 (write_cs),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d[1]),
.p_14_in(p_14_in),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.ss_wr_awready(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 splitter_aw_mi
(.aa_mi_awtarget_hot(aa_mi_awtarget_hot),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_no_arbiter.m_target_hot_i_reg[1] (addr_arbiter_aw_n_3),
.m_ready_d(m_ready_d_3),
.\m_ready_d_reg[0]_0 (addr_arbiter_aw_n_21),
.\m_ready_d_reg[0]_1 (addr_arbiter_aw_n_2));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_decerr_slave" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave
(mi_awready_2,
p_14_in,
p_21_in,
p_15_in,
p_17_in,
\gen_axi.write_cs_reg[1]_0 ,
mi_arready_2,
\gen_axi.s_axi_arready_i_reg_0 ,
Q,
\skid_buffer_reg[46] ,
SR,
aclk,
aa_mi_awtarget_hot,
aa_sa_awvalid,
m_ready_d,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
aa_mi_arvalid,
mi_rready_2,
\gen_no_arbiter.m_mesg_i_reg[51] ,
\gen_no_arbiter.m_valid_i_reg ,
mi_bready_2,
\m_ready_d_reg[1] ,
\storage_data1_reg[0] ,
s_axi_rlast_i0,
E,
\gen_no_arbiter.m_mesg_i_reg[11] ,
aresetn_d);
output mi_awready_2;
output p_14_in;
output p_21_in;
output p_15_in;
output p_17_in;
output [0:0]\gen_axi.write_cs_reg[1]_0 ;
output mi_arready_2;
output \gen_axi.s_axi_arready_i_reg_0 ;
output [11:0]Q;
output [11:0]\skid_buffer_reg[46] ;
input [0:0]SR;
input aclk;
input [0:0]aa_mi_awtarget_hot;
input aa_sa_awvalid;
input [0:0]m_ready_d;
input [0:0]\gen_no_arbiter.m_target_hot_i_reg[2] ;
input aa_mi_arvalid;
input mi_rready_2;
input [19:0]\gen_no_arbiter.m_mesg_i_reg[51] ;
input \gen_no_arbiter.m_valid_i_reg ;
input mi_bready_2;
input \m_ready_d_reg[1] ;
input \storage_data1_reg[0] ;
input s_axi_rlast_i0;
input [0:0]E;
input [11:0]\gen_no_arbiter.m_mesg_i_reg[11] ;
input aresetn_d;
wire [0:0]E;
wire [11:0]Q;
wire [0:0]SR;
wire aa_mi_arvalid;
wire [0:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire \gen_axi.read_cnt[4]_i_2_n_0 ;
wire \gen_axi.read_cnt[7]_i_1_n_0 ;
wire \gen_axi.read_cnt[7]_i_3_n_0 ;
wire [0:0]\gen_axi.read_cnt_reg ;
wire [7:1]\gen_axi.read_cnt_reg__0 ;
wire \gen_axi.read_cs[0]_i_1_n_0 ;
wire \gen_axi.s_axi_arready_i_i_1_n_0 ;
wire \gen_axi.s_axi_arready_i_reg_0 ;
wire \gen_axi.s_axi_awready_i_i_1_n_0 ;
wire \gen_axi.s_axi_bid_i[11]_i_1_n_0 ;
wire \gen_axi.s_axi_bvalid_i_i_1_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_1_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_3_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_4_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_5_n_0 ;
wire \gen_axi.s_axi_wready_i_i_1_n_0 ;
wire \gen_axi.write_cs[0]_i_1_n_0 ;
wire \gen_axi.write_cs[1]_i_1_n_0 ;
wire [0:0]\gen_axi.write_cs_reg[1]_0 ;
wire [11:0]\gen_no_arbiter.m_mesg_i_reg[11] ;
wire [19:0]\gen_no_arbiter.m_mesg_i_reg[51] ;
wire [0:0]\gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.m_valid_i_reg ;
wire [0:0]m_ready_d;
wire \m_ready_d_reg[1] ;
wire mi_arready_2;
wire mi_awready_2;
wire mi_bready_2;
wire mi_rready_2;
wire [7:0]p_0_in;
wire p_14_in;
wire p_15_in;
wire p_17_in;
wire p_21_in;
wire s_axi_rlast_i0;
wire [11:0]\skid_buffer_reg[46] ;
wire \storage_data1_reg[0] ;
wire [0:0]write_cs;
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h74))
\gen_axi.read_cnt[0]_i_1
(.I0(\gen_axi.read_cnt_reg ),
.I1(p_15_in),
.I2(\gen_no_arbiter.m_mesg_i_reg[51] [12]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h9F90))
\gen_axi.read_cnt[1]_i_1
(.I0(\gen_axi.read_cnt_reg ),
.I1(\gen_axi.read_cnt_reg__0 [1]),
.I2(p_15_in),
.I3(\gen_no_arbiter.m_mesg_i_reg[51] [13]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'hA9FFA900))
\gen_axi.read_cnt[2]_i_1
(.I0(\gen_axi.read_cnt_reg__0 [2]),
.I1(\gen_axi.read_cnt_reg__0 [1]),
.I2(\gen_axi.read_cnt_reg ),
.I3(p_15_in),
.I4(\gen_no_arbiter.m_mesg_i_reg[51] [14]),
.O(p_0_in[2]));
LUT6 #(
.INIT(64'hAAA9FFFFAAA90000))
\gen_axi.read_cnt[3]_i_1
(.I0(\gen_axi.read_cnt_reg__0 [3]),
.I1(\gen_axi.read_cnt_reg__0 [2]),
.I2(\gen_axi.read_cnt_reg ),
.I3(\gen_axi.read_cnt_reg__0 [1]),
.I4(p_15_in),
.I5(\gen_no_arbiter.m_mesg_i_reg[51] [15]),
.O(p_0_in[3]));
LUT6 #(
.INIT(64'hFACAFAFACACACACA))
\gen_axi.read_cnt[4]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [16]),
.I1(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I2(p_15_in),
.I3(\gen_axi.read_cnt_reg__0 [3]),
.I4(\gen_axi.read_cnt[4]_i_2_n_0 ),
.I5(\gen_axi.read_cnt_reg__0 [4]),
.O(p_0_in[4]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h01))
\gen_axi.read_cnt[4]_i_2
(.I0(\gen_axi.read_cnt_reg__0 [1]),
.I1(\gen_axi.read_cnt_reg ),
.I2(\gen_axi.read_cnt_reg__0 [2]),
.O(\gen_axi.read_cnt[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h3CAA))
\gen_axi.read_cnt[5]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [17]),
.I1(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I2(\gen_axi.read_cnt_reg__0 [5]),
.I3(p_15_in),
.O(p_0_in[5]));
LUT5 #(
.INIT(32'hEE2E22E2))
\gen_axi.read_cnt[6]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [18]),
.I1(p_15_in),
.I2(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I3(\gen_axi.read_cnt_reg__0 [5]),
.I4(\gen_axi.read_cnt_reg__0 [6]),
.O(p_0_in[6]));
LUT6 #(
.INIT(64'h00800080FF800080))
\gen_axi.read_cnt[7]_i_1
(.I0(mi_arready_2),
.I1(\gen_no_arbiter.m_target_hot_i_reg[2] ),
.I2(aa_mi_arvalid),
.I3(p_15_in),
.I4(mi_rready_2),
.I5(\gen_axi.s_axi_arready_i_reg_0 ),
.O(\gen_axi.read_cnt[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B874B8))
\gen_axi.read_cnt[7]_i_2
(.I0(\gen_axi.read_cnt_reg__0 [7]),
.I1(p_15_in),
.I2(\gen_no_arbiter.m_mesg_i_reg[51] [19]),
.I3(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I4(\gen_axi.read_cnt_reg__0 [5]),
.I5(\gen_axi.read_cnt_reg__0 [6]),
.O(p_0_in[7]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'h00000001))
\gen_axi.read_cnt[7]_i_3
(.I0(\gen_axi.read_cnt_reg ),
.I1(\gen_axi.read_cnt_reg__0 [2]),
.I2(\gen_axi.read_cnt_reg__0 [1]),
.I3(\gen_axi.read_cnt_reg__0 [4]),
.I4(\gen_axi.read_cnt_reg__0 [3]),
.O(\gen_axi.read_cnt[7]_i_3_n_0 ));
FDRE \gen_axi.read_cnt_reg[0]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[0]),
.Q(\gen_axi.read_cnt_reg ),
.R(SR));
FDRE \gen_axi.read_cnt_reg[1]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[1]),
.Q(\gen_axi.read_cnt_reg__0 [1]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[2]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[2]),
.Q(\gen_axi.read_cnt_reg__0 [2]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[3]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[3]),
.Q(\gen_axi.read_cnt_reg__0 [3]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[4]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[4]),
.Q(\gen_axi.read_cnt_reg__0 [4]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[5]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[5]),
.Q(\gen_axi.read_cnt_reg__0 [5]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[6]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[6]),
.Q(\gen_axi.read_cnt_reg__0 [6]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[7]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[7]),
.Q(\gen_axi.read_cnt_reg__0 [7]),
.R(SR));
LUT6 #(
.INIT(64'h0080FF80FF80FF80))
\gen_axi.read_cs[0]_i_1
(.I0(mi_arready_2),
.I1(\gen_no_arbiter.m_target_hot_i_reg[2] ),
.I2(aa_mi_arvalid),
.I3(p_15_in),
.I4(mi_rready_2),
.I5(\gen_axi.s_axi_arready_i_reg_0 ),
.O(\gen_axi.read_cs[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.read_cs_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.read_cs[0]_i_1_n_0 ),
.Q(p_15_in),
.R(SR));
LUT6 #(
.INIT(64'h00000000FBBB0000))
\gen_axi.s_axi_arready_i_i_1
(.I0(mi_arready_2),
.I1(p_15_in),
.I2(mi_rready_2),
.I3(\gen_axi.s_axi_arready_i_reg_0 ),
.I4(aresetn_d),
.I5(E),
.O(\gen_axi.s_axi_arready_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h0002))
\gen_axi.s_axi_arready_i_i_2
(.I0(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I1(\gen_axi.read_cnt_reg__0 [5]),
.I2(\gen_axi.read_cnt_reg__0 [6]),
.I3(\gen_axi.read_cnt_reg__0 [7]),
.O(\gen_axi.s_axi_arready_i_reg_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_arready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_arready_i_i_1_n_0 ),
.Q(mi_arready_2),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFF7F70F000F0F))
\gen_axi.s_axi_awready_i_i_1
(.I0(\gen_no_arbiter.m_valid_i_reg ),
.I1(aa_mi_awtarget_hot),
.I2(write_cs),
.I3(mi_bready_2),
.I4(\gen_axi.write_cs_reg[1]_0 ),
.I5(mi_awready_2),
.O(\gen_axi.s_axi_awready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_awready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_awready_i_i_1_n_0 ),
.Q(mi_awready_2),
.R(SR));
LUT6 #(
.INIT(64'h0000000010000000))
\gen_axi.s_axi_bid_i[11]_i_1
(.I0(write_cs),
.I1(\gen_axi.write_cs_reg[1]_0 ),
.I2(mi_awready_2),
.I3(aa_mi_awtarget_hot),
.I4(aa_sa_awvalid),
.I5(m_ready_d),
.O(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ));
FDRE \gen_axi.s_axi_bid_i_reg[0]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [0]),
.Q(Q[0]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[10]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [10]),
.Q(Q[10]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[11]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [11]),
.Q(Q[11]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[1]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [1]),
.Q(Q[1]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[2]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [2]),
.Q(Q[2]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[3]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [3]),
.Q(Q[3]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[4]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [4]),
.Q(Q[4]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[5]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [5]),
.Q(Q[5]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[6]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [6]),
.Q(Q[6]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[7]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [7]),
.Q(Q[7]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[8]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [8]),
.Q(Q[8]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[9]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [9]),
.Q(Q[9]),
.R(SR));
LUT5 #(
.INIT(32'hEFFFA888))
\gen_axi.s_axi_bvalid_i_i_1
(.I0(\storage_data1_reg[0] ),
.I1(write_cs),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(mi_bready_2),
.I4(p_21_in),
.O(\gen_axi.s_axi_bvalid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_bvalid_i_i_1_n_0 ),
.Q(p_21_in),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[0]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [0]),
.Q(\skid_buffer_reg[46] [0]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[10]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [10]),
.Q(\skid_buffer_reg[46] [10]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[11]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [11]),
.Q(\skid_buffer_reg[46] [11]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[1]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [1]),
.Q(\skid_buffer_reg[46] [1]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[2]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [2]),
.Q(\skid_buffer_reg[46] [2]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[3]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [3]),
.Q(\skid_buffer_reg[46] [3]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[4]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [4]),
.Q(\skid_buffer_reg[46] [4]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[5]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [5]),
.Q(\skid_buffer_reg[46] [5]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[6]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [6]),
.Q(\skid_buffer_reg[46] [6]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[7]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [7]),
.Q(\skid_buffer_reg[46] [7]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[8]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [8]),
.Q(\skid_buffer_reg[46] [8]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[9]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [9]),
.Q(\skid_buffer_reg[46] [9]),
.R(SR));
LUT6 #(
.INIT(64'hBBBBBBBA8888888A))
\gen_axi.s_axi_rlast_i_i_1
(.I0(s_axi_rlast_i0),
.I1(E),
.I2(\gen_axi.s_axi_rlast_i_i_3_n_0 ),
.I3(\gen_axi.s_axi_rlast_i_i_4_n_0 ),
.I4(\gen_axi.s_axi_rlast_i_i_5_n_0 ),
.I5(p_17_in),
.O(\gen_axi.s_axi_rlast_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hFE))
\gen_axi.s_axi_rlast_i_i_3
(.I0(\gen_axi.read_cnt_reg__0 [7]),
.I1(\gen_axi.read_cnt_reg__0 [6]),
.I2(\gen_axi.read_cnt_reg__0 [5]),
.O(\gen_axi.s_axi_rlast_i_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h7))
\gen_axi.s_axi_rlast_i_i_4
(.I0(p_15_in),
.I1(mi_rready_2),
.O(\gen_axi.s_axi_rlast_i_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_axi.s_axi_rlast_i_i_5
(.I0(\gen_axi.read_cnt_reg__0 [3]),
.I1(\gen_axi.read_cnt_reg__0 [4]),
.I2(\gen_axi.read_cnt_reg__0 [1]),
.I3(\gen_axi.read_cnt_reg__0 [2]),
.O(\gen_axi.s_axi_rlast_i_i_5_n_0 ));
FDRE \gen_axi.s_axi_rlast_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_rlast_i_i_1_n_0 ),
.Q(p_17_in),
.R(SR));
LUT5 #(
.INIT(32'h0FFF0202))
\gen_axi.s_axi_wready_i_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_axi.write_cs_reg[1]_0 ),
.I2(write_cs),
.I3(\storage_data1_reg[0] ),
.I4(p_14_in),
.O(\gen_axi.s_axi_wready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_wready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_wready_i_i_1_n_0 ),
.Q(p_14_in),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h0252))
\gen_axi.write_cs[0]_i_1
(.I0(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.I1(\gen_axi.write_cs_reg[1]_0 ),
.I2(write_cs),
.I3(\storage_data1_reg[0] ),
.O(\gen_axi.write_cs[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hFF10FA10))
\gen_axi.write_cs[1]_i_1
(.I0(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.I1(mi_bready_2),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(write_cs),
.I4(\storage_data1_reg[0] ),
.O(\gen_axi.write_cs[1]_i_1_n_0 ));
FDRE \gen_axi.write_cs_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.write_cs[0]_i_1_n_0 ),
.Q(write_cs),
.R(SR));
FDRE \gen_axi.write_cs_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.write_cs[1]_i_1_n_0 ),
.Q(\gen_axi.write_cs_reg[1]_0 ),
.R(SR));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_si_transactor" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
\gen_multi_thread.accept_cnt_reg[2]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
st_aa_artarget_hot,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
E,
chosen,
s_axi_rlast,
s_axi_rvalid,
s_axi_rresp,
s_axi_rid,
s_axi_rdata,
\m_payload_i_reg[34] ,
aresetn_d,
\s_axi_araddr[25] ,
\gen_no_arbiter.s_ready_i_reg[0]_1 ,
\s_axi_araddr[25]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[2]_0 ,
\gen_no_arbiter.m_valid_i_reg ,
\s_axi_araddr[31] ,
p_74_out,
s_axi_rready,
p_54_out,
p_32_out,
\m_payload_i_reg[46] ,
\m_payload_i_reg[46]_0 ,
\m_payload_i_reg[46]_1 ,
SR,
aclk);
output \gen_no_arbiter.s_ready_i_reg[0] ;
output m_valid_i;
output \gen_multi_thread.accept_cnt_reg[2]_0 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [0:0]st_aa_artarget_hot;
output \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ;
output \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ;
output \gen_no_arbiter.s_ready_i_reg[0]_0 ;
output [0:0]E;
output [2:0]chosen;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
output [0:0]s_axi_rresp;
output [11:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [0:0]\m_payload_i_reg[34] ;
input aresetn_d;
input [0:0]\s_axi_araddr[25] ;
input \gen_no_arbiter.s_ready_i_reg[0]_1 ;
input \s_axi_araddr[25]_0 ;
input [0:0]\gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
input \gen_no_arbiter.m_valid_i_reg ;
input [27:0]\s_axi_araddr[31] ;
input p_74_out;
input [0:0]s_axi_rready;
input p_54_out;
input p_32_out;
input [25:0]\m_payload_i_reg[46] ;
input [25:0]\m_payload_i_reg[46]_0 ;
input [12:0]\m_payload_i_reg[46]_1 ;
input [0:0]SR;
input aclk;
wire [0:0]E;
wire [0:0]SR;
wire aclk;
wire [59:0]active_cnt;
wire [57:0]active_target;
wire aid_match_00;
wire aid_match_00_carry_i_1_n_0;
wire aid_match_00_carry_i_2_n_0;
wire aid_match_00_carry_i_3_n_0;
wire aid_match_00_carry_i_4_n_0;
wire aid_match_00_carry_n_1;
wire aid_match_00_carry_n_2;
wire aid_match_00_carry_n_3;
wire aid_match_10;
wire aid_match_10_carry_i_1_n_0;
wire aid_match_10_carry_i_2_n_0;
wire aid_match_10_carry_i_3_n_0;
wire aid_match_10_carry_i_4_n_0;
wire aid_match_10_carry_n_1;
wire aid_match_10_carry_n_2;
wire aid_match_10_carry_n_3;
wire aid_match_20;
wire aid_match_20_carry_i_1_n_0;
wire aid_match_20_carry_i_2_n_0;
wire aid_match_20_carry_i_3_n_0;
wire aid_match_20_carry_i_4_n_0;
wire aid_match_20_carry_n_1;
wire aid_match_20_carry_n_2;
wire aid_match_20_carry_n_3;
wire aid_match_30;
wire aid_match_30_carry_i_1_n_0;
wire aid_match_30_carry_i_2_n_0;
wire aid_match_30_carry_i_3_n_0;
wire aid_match_30_carry_i_4_n_0;
wire aid_match_30_carry_n_1;
wire aid_match_30_carry_n_2;
wire aid_match_30_carry_n_3;
wire aid_match_40;
wire aid_match_40_carry_i_1_n_0;
wire aid_match_40_carry_i_2_n_0;
wire aid_match_40_carry_i_3_n_0;
wire aid_match_40_carry_i_4_n_0;
wire aid_match_40_carry_n_1;
wire aid_match_40_carry_n_2;
wire aid_match_40_carry_n_3;
wire aid_match_50;
wire aid_match_50_carry_i_1_n_0;
wire aid_match_50_carry_i_2_n_0;
wire aid_match_50_carry_i_3_n_0;
wire aid_match_50_carry_i_4_n_0;
wire aid_match_50_carry_n_1;
wire aid_match_50_carry_n_2;
wire aid_match_50_carry_n_3;
wire aid_match_60;
wire aid_match_60_carry_i_1_n_0;
wire aid_match_60_carry_i_2_n_0;
wire aid_match_60_carry_i_3_n_0;
wire aid_match_60_carry_i_4_n_0;
wire aid_match_60_carry_n_1;
wire aid_match_60_carry_n_2;
wire aid_match_60_carry_n_3;
wire aid_match_70;
wire aid_match_70_carry_i_1_n_0;
wire aid_match_70_carry_i_2_n_0;
wire aid_match_70_carry_i_3_n_0;
wire aid_match_70_carry_i_4_n_0;
wire aid_match_70_carry_n_1;
wire aid_match_70_carry_n_2;
wire aid_match_70_carry_n_3;
wire aresetn_d;
wire [2:0]chosen;
wire cmd_push_0;
wire cmd_push_1;
wire cmd_push_2;
wire cmd_push_3;
wire cmd_push_4;
wire cmd_push_5;
wire cmd_push_6;
wire cmd_push_7;
wire \gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ;
wire \gen_multi_thread.accept_cnt_reg[2]_0 ;
wire [3:0]\gen_multi_thread.accept_cnt_reg__0 ;
wire \gen_multi_thread.arbiter_resp_inst_n_0 ;
wire \gen_multi_thread.arbiter_resp_inst_n_1 ;
wire \gen_multi_thread.arbiter_resp_inst_n_10 ;
wire \gen_multi_thread.arbiter_resp_inst_n_11 ;
wire \gen_multi_thread.arbiter_resp_inst_n_12 ;
wire \gen_multi_thread.arbiter_resp_inst_n_2 ;
wire \gen_multi_thread.arbiter_resp_inst_n_20 ;
wire \gen_multi_thread.arbiter_resp_inst_n_21 ;
wire \gen_multi_thread.arbiter_resp_inst_n_22 ;
wire \gen_multi_thread.arbiter_resp_inst_n_23 ;
wire \gen_multi_thread.arbiter_resp_inst_n_24 ;
wire \gen_multi_thread.arbiter_resp_inst_n_25 ;
wire \gen_multi_thread.arbiter_resp_inst_n_26 ;
wire \gen_multi_thread.arbiter_resp_inst_n_27 ;
wire \gen_multi_thread.arbiter_resp_inst_n_28 ;
wire \gen_multi_thread.arbiter_resp_inst_n_29 ;
wire \gen_multi_thread.arbiter_resp_inst_n_30 ;
wire \gen_multi_thread.arbiter_resp_inst_n_31 ;
wire \gen_multi_thread.arbiter_resp_inst_n_32 ;
wire \gen_multi_thread.arbiter_resp_inst_n_33 ;
wire \gen_multi_thread.arbiter_resp_inst_n_34 ;
wire \gen_multi_thread.arbiter_resp_inst_n_35 ;
wire \gen_multi_thread.arbiter_resp_inst_n_36 ;
wire \gen_multi_thread.arbiter_resp_inst_n_37 ;
wire \gen_multi_thread.arbiter_resp_inst_n_38 ;
wire \gen_multi_thread.arbiter_resp_inst_n_39 ;
wire \gen_multi_thread.arbiter_resp_inst_n_4 ;
wire \gen_multi_thread.arbiter_resp_inst_n_40 ;
wire \gen_multi_thread.arbiter_resp_inst_n_41 ;
wire \gen_multi_thread.arbiter_resp_inst_n_42 ;
wire \gen_multi_thread.arbiter_resp_inst_n_43 ;
wire \gen_multi_thread.arbiter_resp_inst_n_44 ;
wire \gen_multi_thread.arbiter_resp_inst_n_45 ;
wire \gen_multi_thread.arbiter_resp_inst_n_46 ;
wire \gen_multi_thread.arbiter_resp_inst_n_47 ;
wire \gen_multi_thread.arbiter_resp_inst_n_48 ;
wire \gen_multi_thread.arbiter_resp_inst_n_49 ;
wire \gen_multi_thread.arbiter_resp_inst_n_5 ;
wire \gen_multi_thread.arbiter_resp_inst_n_50 ;
wire \gen_multi_thread.arbiter_resp_inst_n_51 ;
wire \gen_multi_thread.arbiter_resp_inst_n_6 ;
wire \gen_multi_thread.arbiter_resp_inst_n_7 ;
wire \gen_multi_thread.arbiter_resp_inst_n_8 ;
wire \gen_multi_thread.arbiter_resp_inst_n_9 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire [0:0]\gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
wire \gen_no_arbiter.m_valid_i_reg ;
wire \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_11_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_13_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_8_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_9_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_1 ;
wire [0:0]\m_payload_i_reg[34] ;
wire [25:0]\m_payload_i_reg[46] ;
wire [25:0]\m_payload_i_reg[46]_0 ;
wire [12:0]\m_payload_i_reg[46]_1 ;
wire m_valid_i;
wire p_0_out;
wire \p_0_out_inferred__9/i__carry_n_1 ;
wire \p_0_out_inferred__9/i__carry_n_2 ;
wire \p_0_out_inferred__9/i__carry_n_3 ;
wire p_10_out;
wire p_10_out_carry_n_1;
wire p_10_out_carry_n_2;
wire p_10_out_carry_n_3;
wire p_12_out;
wire p_12_out_carry_n_1;
wire p_12_out_carry_n_2;
wire p_12_out_carry_n_3;
wire p_14_out;
wire p_14_out_carry_n_1;
wire p_14_out_carry_n_2;
wire p_14_out_carry_n_3;
wire p_2_out;
wire p_2_out_carry_n_1;
wire p_2_out_carry_n_2;
wire p_2_out_carry_n_3;
wire p_32_out;
wire p_4_out;
wire p_4_out_carry_n_1;
wire p_4_out_carry_n_2;
wire p_4_out_carry_n_3;
wire p_54_out;
wire p_6_out;
wire p_6_out_carry_n_1;
wire p_6_out_carry_n_2;
wire p_6_out_carry_n_3;
wire p_74_out;
wire p_8_out;
wire p_8_out_carry_n_1;
wire p_8_out_carry_n_2;
wire p_8_out_carry_n_3;
wire [0:0]\s_axi_araddr[25] ;
wire \s_axi_araddr[25]_0 ;
wire [27:0]\s_axi_araddr[31] ;
wire [11:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [0:0]st_aa_artarget_hot;
wire [3:0]NLW_aid_match_00_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_10_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_20_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_30_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_40_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_50_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_60_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_70_carry_O_UNCONNECTED;
wire [3:0]\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED ;
wire [3:0]NLW_p_10_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_12_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_14_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_2_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_4_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_6_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_8_out_carry_O_UNCONNECTED;
CARRY4 aid_match_00_carry
(.CI(1'b0),
.CO({aid_match_00,aid_match_00_carry_n_1,aid_match_00_carry_n_2,aid_match_00_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_00_carry_O_UNCONNECTED[3:0]),
.S({aid_match_00_carry_i_1_n_0,aid_match_00_carry_i_2_n_0,aid_match_00_carry_i_3_n_0,aid_match_00_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [11]),
.O(aid_match_00_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [7]),
.I1(\s_axi_araddr[31] [7]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [6]),
.O(aid_match_00_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [4]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [4]),
.I4(\s_axi_araddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [5]),
.O(aid_match_00_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [0]),
.I1(\s_axi_araddr[31] [0]),
.I2(\s_axi_araddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [2]),
.I4(\s_axi_araddr[31] [1]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [1]),
.O(aid_match_00_carry_i_4_n_0));
CARRY4 aid_match_10_carry
(.CI(1'b0),
.CO({aid_match_10,aid_match_10_carry_n_1,aid_match_10_carry_n_2,aid_match_10_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_10_carry_O_UNCONNECTED[3:0]),
.S({aid_match_10_carry_i_1_n_0,aid_match_10_carry_i_2_n_0,aid_match_10_carry_i_3_n_0,aid_match_10_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_1
(.I0(\s_axi_araddr[31] [10]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [10]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [9]),
.I3(\s_axi_araddr[31] [9]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [11]),
.I5(\s_axi_araddr[31] [11]),
.O(aid_match_10_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_2
(.I0(\s_axi_araddr[31] [7]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [7]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [8]),
.I3(\s_axi_araddr[31] [8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [6]),
.I5(\s_axi_araddr[31] [6]),
.O(aid_match_10_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_3
(.I0(\s_axi_araddr[31] [3]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [3]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [5]),
.I3(\s_axi_araddr[31] [5]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [4]),
.I5(\s_axi_araddr[31] [4]),
.O(aid_match_10_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_4
(.I0(\s_axi_araddr[31] [0]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [0]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [2]),
.I3(\s_axi_araddr[31] [2]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [1]),
.I5(\s_axi_araddr[31] [1]),
.O(aid_match_10_carry_i_4_n_0));
CARRY4 aid_match_20_carry
(.CI(1'b0),
.CO({aid_match_20,aid_match_20_carry_n_1,aid_match_20_carry_n_2,aid_match_20_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_20_carry_O_UNCONNECTED[3:0]),
.S({aid_match_20_carry_i_1_n_0,aid_match_20_carry_i_2_n_0,aid_match_20_carry_i_3_n_0,aid_match_20_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [11]),
.O(aid_match_20_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [7]),
.I1(\s_axi_araddr[31] [7]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [6]),
.O(aid_match_20_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [5]),
.I4(\s_axi_araddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [4]),
.O(aid_match_20_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [2]),
.I4(\s_axi_araddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [0]),
.O(aid_match_20_carry_i_4_n_0));
CARRY4 aid_match_30_carry
(.CI(1'b0),
.CO({aid_match_30,aid_match_30_carry_n_1,aid_match_30_carry_n_2,aid_match_30_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_30_carry_O_UNCONNECTED[3:0]),
.S({aid_match_30_carry_i_1_n_0,aid_match_30_carry_i_2_n_0,aid_match_30_carry_i_3_n_0,aid_match_30_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [10]),
.I1(\s_axi_araddr[31] [10]),
.I2(\s_axi_araddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [11]),
.I4(\s_axi_araddr[31] [9]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [9]),
.O(aid_match_30_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [7]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [7]),
.O(aid_match_30_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [5]),
.I4(\s_axi_araddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [4]),
.O(aid_match_30_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [0]),
.I1(\s_axi_araddr[31] [0]),
.I2(\s_axi_araddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [2]),
.I4(\s_axi_araddr[31] [1]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [1]),
.O(aid_match_30_carry_i_4_n_0));
CARRY4 aid_match_40_carry
(.CI(1'b0),
.CO({aid_match_40,aid_match_40_carry_n_1,aid_match_40_carry_n_2,aid_match_40_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_40_carry_O_UNCONNECTED[3:0]),
.S({aid_match_40_carry_i_1_n_0,aid_match_40_carry_i_2_n_0,aid_match_40_carry_i_3_n_0,aid_match_40_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [11]),
.O(aid_match_40_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [7]),
.I4(\s_axi_araddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [8]),
.O(aid_match_40_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_3
(.I0(\s_axi_araddr[31] [5]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [5]),
.I2(\s_axi_araddr[31] [3]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [3]),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [4]),
.I5(\s_axi_araddr[31] [4]),
.O(aid_match_40_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [0]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [2]),
.O(aid_match_40_carry_i_4_n_0));
CARRY4 aid_match_50_carry
(.CI(1'b0),
.CO({aid_match_50,aid_match_50_carry_n_1,aid_match_50_carry_n_2,aid_match_50_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_50_carry_O_UNCONNECTED[3:0]),
.S({aid_match_50_carry_i_1_n_0,aid_match_50_carry_i_2_n_0,aid_match_50_carry_i_3_n_0,aid_match_50_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [11]),
.O(aid_match_50_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [7]),
.I4(\s_axi_araddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [8]),
.O(aid_match_50_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [4]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [4]),
.I4(\s_axi_araddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [5]),
.O(aid_match_50_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [0]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [2]),
.O(aid_match_50_carry_i_4_n_0));
CARRY4 aid_match_60_carry
(.CI(1'b0),
.CO({aid_match_60,aid_match_60_carry_n_1,aid_match_60_carry_n_2,aid_match_60_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_60_carry_O_UNCONNECTED[3:0]),
.S({aid_match_60_carry_i_1_n_0,aid_match_60_carry_i_2_n_0,aid_match_60_carry_i_3_n_0,aid_match_60_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [11]),
.I4(\s_axi_araddr[31] [10]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [10]),
.O(aid_match_60_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [7]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [7]),
.O(aid_match_60_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [5]),
.I4(\s_axi_araddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [4]),
.O(aid_match_60_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [0]),
.I1(\s_axi_araddr[31] [0]),
.I2(\s_axi_araddr[31] [1]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [1]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [2]),
.O(aid_match_60_carry_i_4_n_0));
CARRY4 aid_match_70_carry
(.CI(1'b0),
.CO({aid_match_70,aid_match_70_carry_n_1,aid_match_70_carry_n_2,aid_match_70_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_70_carry_O_UNCONNECTED[3:0]),
.S({aid_match_70_carry_i_1_n_0,aid_match_70_carry_i_2_n_0,aid_match_70_carry_i_3_n_0,aid_match_70_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [10]),
.I1(\s_axi_araddr[31] [10]),
.I2(\s_axi_araddr[31] [9]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [9]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [11]),
.O(aid_match_70_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [7]),
.I4(\s_axi_araddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [8]),
.O(aid_match_70_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [4]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [4]),
.I4(\s_axi_araddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [5]),
.O(aid_match_70_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [0]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [2]),
.O(aid_match_70_carry_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.accept_cnt[0]_i_1__0
(.I0(\gen_multi_thread.accept_cnt_reg__0 [0]),
.O(\gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_2 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_1 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_0 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [3]),
.R(SR));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 \gen_multi_thread.arbiter_resp_inst
(.CO(p_8_out),
.D({\gen_multi_thread.arbiter_resp_inst_n_0 ,\gen_multi_thread.arbiter_resp_inst_n_1 ,\gen_multi_thread.arbiter_resp_inst_n_2 }),
.E(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 ),
.S({\gen_multi_thread.arbiter_resp_inst_n_20 ,\gen_multi_thread.arbiter_resp_inst_n_21 ,\gen_multi_thread.arbiter_resp_inst_n_22 ,\gen_multi_thread.arbiter_resp_inst_n_23 }),
.SR(SR),
.aclk(aclk),
.\chosen_reg[1]_0 (chosen[1]),
.cmd_push_0(cmd_push_0),
.cmd_push_3(cmd_push_3),
.\gen_multi_thread.accept_cnt_reg[2] (\gen_multi_thread.accept_cnt_reg[2]_0 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.arbiter_resp_inst_n_12 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.arbiter_resp_inst_n_11 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] (p_14_out),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] (\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_multi_thread.arbiter_resp_inst_n_10 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ({\gen_multi_thread.arbiter_resp_inst_n_24 ,\gen_multi_thread.arbiter_resp_inst_n_25 ,\gen_multi_thread.arbiter_resp_inst_n_26 ,\gen_multi_thread.arbiter_resp_inst_n_27 }),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] (p_12_out),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] (\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] (\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_multi_thread.arbiter_resp_inst_n_9 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ({\gen_multi_thread.arbiter_resp_inst_n_28 ,\gen_multi_thread.arbiter_resp_inst_n_29 ,\gen_multi_thread.arbiter_resp_inst_n_30 ,\gen_multi_thread.arbiter_resp_inst_n_31 }),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] (p_10_out),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] (\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] (\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ({\gen_multi_thread.arbiter_resp_inst_n_32 ,\gen_multi_thread.arbiter_resp_inst_n_33 ,\gen_multi_thread.arbiter_resp_inst_n_34 ,\gen_multi_thread.arbiter_resp_inst_n_35 }),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] (\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_multi_thread.arbiter_resp_inst_n_8 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ({\gen_multi_thread.arbiter_resp_inst_n_36 ,\gen_multi_thread.arbiter_resp_inst_n_37 ,\gen_multi_thread.arbiter_resp_inst_n_38 ,\gen_multi_thread.arbiter_resp_inst_n_39 }),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] (\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] (p_6_out),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] (\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] (\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_multi_thread.arbiter_resp_inst_n_7 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ({\gen_multi_thread.arbiter_resp_inst_n_40 ,\gen_multi_thread.arbiter_resp_inst_n_41 ,\gen_multi_thread.arbiter_resp_inst_n_42 ,\gen_multi_thread.arbiter_resp_inst_n_43 }),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] (p_4_out),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] (\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_multi_thread.arbiter_resp_inst_n_6 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ({\gen_multi_thread.arbiter_resp_inst_n_44 ,\gen_multi_thread.arbiter_resp_inst_n_45 ,\gen_multi_thread.arbiter_resp_inst_n_46 ,\gen_multi_thread.arbiter_resp_inst_n_47 }),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] (\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] (p_2_out),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] (\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.arbiter_resp_inst_n_5 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ({\gen_multi_thread.arbiter_resp_inst_n_48 ,\gen_multi_thread.arbiter_resp_inst_n_49 ,\gen_multi_thread.arbiter_resp_inst_n_50 ,\gen_multi_thread.arbiter_resp_inst_n_51 }),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] (\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] (p_0_out),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] (\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_1 (\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_2 (\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_3 (\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_4 (\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_5 (\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.\m_payload_i_reg[0] (E),
.\m_payload_i_reg[0]_0 (chosen[0]),
.\m_payload_i_reg[34] (chosen[2]),
.\m_payload_i_reg[34]_0 (\m_payload_i_reg[34] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[46]_0 (\m_payload_i_reg[46]_0 ),
.\m_payload_i_reg[46]_1 (\m_payload_i_reg[46]_1 ),
.p_32_out(p_32_out),
.p_54_out(p_54_out),
.p_74_out(p_74_out),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1
(.I0(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0
(.I0(cmd_push_0),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0
(.I0(active_cnt[2]),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.I3(cmd_push_0),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0
(.I0(active_cnt[3]),
.I1(active_cnt[2]),
.I2(cmd_push_0),
.I3(active_cnt[1]),
.I4(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ),
.Q(active_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ),
.Q(active_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ),
.Q(active_cnt[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ),
.Q(active_cnt[3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [11]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[2]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[3]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[4]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[5]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[6]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[7]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[9]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [9]),
.R(SR));
LUT6 #(
.INIT(64'h00000F0088888888))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1__0
(.I0(aid_match_00),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.O(cmd_push_0));
LUT6 #(
.INIT(64'hAAAAAAA8FFFFFFFF))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0
(.I0(aid_match_30),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(active_cnt[27]),
.I4(active_cnt[26]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(st_aa_artarget_hot),
.Q(active_target[0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[1]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0
(.I0(active_cnt[10]),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0
(.I0(active_cnt[11]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFF55FF55CF55FF55))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I1(active_cnt[10]),
.I2(active_cnt[11]),
.I3(active_cnt[9]),
.I4(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1
(.I0(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ),
.Q(active_cnt[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ),
.Q(active_cnt[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ),
.Q(active_cnt[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ),
.Q(active_cnt[9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[13]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[14]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[15]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[16]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[17]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[18]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[21]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [11]),
.R(SR));
LUT5 #(
.INIT(32'h3B080808))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I3(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I4(aid_match_10),
.O(cmd_push_1));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT4 #(
.INIT(16'h0080))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0
(.I0(active_cnt[8]),
.I1(active_cnt[9]),
.I2(active_cnt[11]),
.I3(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0
(.I0(active_cnt[0]),
.I1(active_cnt[1]),
.I2(active_cnt[3]),
.I3(active_cnt[2]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]
(.C(aclk),
.CE(cmd_push_1),
.D(st_aa_artarget_hot),
.Q(active_target[8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]
(.C(aclk),
.CE(cmd_push_1),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1
(.I0(active_cnt[16]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0
(.I0(active_cnt[18]),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0
(.I0(active_cnt[19]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0
(.I0(active_cnt[16]),
.I1(active_cnt[17]),
.I2(active_cnt[19]),
.I3(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ),
.Q(active_cnt[16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ),
.Q(active_cnt[17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ),
.Q(active_cnt[18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ),
.Q(active_cnt[19]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[24]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[25]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[26]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[27]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[28]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[29]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[30]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[33]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.O(cmd_push_2));
LUT6 #(
.INIT(64'hFF77FF77F077FF77))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0
(.I0(aid_match_20),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0
(.I0(active_cnt[10]),
.I1(active_cnt[11]),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[16]
(.C(aclk),
.CE(cmd_push_2),
.D(st_aa_artarget_hot),
.Q(active_target[16]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]
(.C(aclk),
.CE(cmd_push_2),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[17]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1
(.I0(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0
(.I0(cmd_push_3),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0
(.I0(active_cnt[26]),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(cmd_push_3),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0
(.I0(active_cnt[27]),
.I1(active_cnt[26]),
.I2(cmd_push_3),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3
(.I0(active_cnt[24]),
.I1(active_cnt[25]),
.I2(active_cnt[27]),
.I3(active_cnt[26]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ),
.Q(active_cnt[24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ),
.Q(active_cnt[25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ),
.Q(active_cnt[26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ),
.Q(active_cnt[27]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[37]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[38]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[39]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[40]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[41]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[42]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[45]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [11]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10
(.I0(active_cnt[2]),
.I1(active_cnt[3]),
.I2(active_cnt[1]),
.I3(active_cnt[0]),
.I4(aid_match_00),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11
(.I0(aid_match_60),
.I1(active_cnt[49]),
.I2(active_cnt[48]),
.I3(active_cnt[50]),
.I4(active_cnt[51]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(aid_match_20),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ));
LUT6 #(
.INIT(64'h0A0A0A0A3A0A0A0A))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(cmd_push_3));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ),
.I1(active_cnt[26]),
.I2(active_cnt[27]),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0
(.I0(active_cnt[26]),
.I1(active_cnt[27]),
.I2(active_cnt[25]),
.I3(active_cnt[24]),
.I4(aid_match_30),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0
(.I0(active_cnt[10]),
.I1(active_cnt[11]),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(aid_match_10),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0
(.I0(aid_match_70),
.I1(active_cnt[57]),
.I2(active_cnt[56]),
.I3(active_cnt[58]),
.I4(active_cnt[59]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF0001))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0
(.I0(aid_match_40),
.I1(active_cnt[33]),
.I2(active_cnt[32]),
.I3(active_cnt[34]),
.I4(active_cnt[35]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0
(.I0(active_cnt[42]),
.I1(active_cnt[43]),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(aid_match_50),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]
(.C(aclk),
.CE(cmd_push_3),
.D(st_aa_artarget_hot),
.Q(active_target[24]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]
(.C(aclk),
.CE(cmd_push_3),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[25]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1
(.I0(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0
(.I0(active_cnt[34]),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0
(.I0(active_cnt[35]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.I2(active_cnt[33]),
.I3(active_cnt[32]),
.I4(active_cnt[34]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0
(.I0(active_cnt[35]),
.I1(active_cnt[34]),
.I2(active_cnt[32]),
.I3(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ),
.Q(active_cnt[32]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ),
.Q(active_cnt[33]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ),
.Q(active_cnt[34]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ),
.Q(active_cnt[35]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[48]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[49]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[50]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[51]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[52]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[53]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[54]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[57]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.O(cmd_push_4));
LUT6 #(
.INIT(64'h5545FFFFFFEFFFFF))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I5(aid_match_40),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3
(.I0(active_cnt[26]),
.I1(active_cnt[27]),
.I2(active_cnt[25]),
.I3(active_cnt[24]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[32]
(.C(aclk),
.CE(cmd_push_4),
.D(st_aa_artarget_hot),
.Q(active_target[32]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[33]
(.C(aclk),
.CE(cmd_push_4),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[33]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1
(.I0(active_cnt[40]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0
(.I0(active_cnt[42]),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0
(.I0(active_cnt[43]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0
(.I0(active_cnt[40]),
.I1(active_cnt[41]),
.I2(active_cnt[43]),
.I3(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ),
.Q(active_cnt[40]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ),
.Q(active_cnt[41]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ),
.Q(active_cnt[42]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ),
.Q(active_cnt[43]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[60]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[61]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[62]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[63]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[64]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[65]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[66]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[69]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.O(cmd_push_5));
LUT6 #(
.INIT(64'hFF77FF77F077FF77))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0
(.I0(aid_match_50),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAABFFFFFFFF))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(active_cnt[27]),
.I4(active_cnt[26]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'h80))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]
(.C(aclk),
.CE(cmd_push_5),
.D(st_aa_artarget_hot),
.Q(active_target[40]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]
(.C(aclk),
.CE(cmd_push_5),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[41]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1
(.I0(active_cnt[48]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0
(.I0(active_cnt[50]),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0
(.I0(active_cnt[51]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.I2(active_cnt[49]),
.I3(active_cnt[48]),
.I4(active_cnt[50]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0
(.I0(active_cnt[51]),
.I1(active_cnt[50]),
.I2(active_cnt[48]),
.I3(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ),
.Q(active_cnt[48]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ),
.Q(active_cnt[49]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ),
.Q(active_cnt[50]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ),
.Q(active_cnt[51]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[72]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[73]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[74]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[75]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[76]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[77]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[78]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[81]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.O(cmd_push_6));
LUT6 #(
.INIT(64'h5555555545555555))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA800000000))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(active_cnt[51]),
.I2(active_cnt[50]),
.I3(active_cnt[48]),
.I4(active_cnt[49]),
.I5(aid_match_60),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ),
.I1(active_cnt[51]),
.I2(active_cnt[50]),
.I3(active_cnt[48]),
.I4(active_cnt[49]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]
(.C(aclk),
.CE(cmd_push_6),
.D(st_aa_artarget_hot),
.Q(active_target[48]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]
(.C(aclk),
.CE(cmd_push_6),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[49]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1
(.I0(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0
(.I0(active_cnt[58]),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0
(.I0(active_cnt[59]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.I2(active_cnt[57]),
.I3(active_cnt[56]),
.I4(active_cnt[58]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0
(.I0(active_cnt[59]),
.I1(active_cnt[58]),
.I2(active_cnt[56]),
.I3(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ),
.Q(active_cnt[56]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ),
.Q(active_cnt[57]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ),
.Q(active_cnt[58]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ),
.Q(active_cnt[59]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[84]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[85]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[86]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[87]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[88]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[89]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[90]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[93]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [11]),
.R(SR));
LUT5 #(
.INIT(32'h00000010))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0
(.I0(\s_axi_araddr[31] [17]),
.I1(\s_axi_araddr[31] [20]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ),
.I3(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ),
.O(st_aa_artarget_hot));
LUT6 #(
.INIT(64'h0000000100000000))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2__0
(.I0(\s_axi_araddr[31] [13]),
.I1(\s_axi_araddr[31] [22]),
.I2(\s_axi_araddr[31] [15]),
.I3(\s_axi_araddr[31] [12]),
.I4(\s_axi_araddr[31] [14]),
.I5(\s_axi_araddr[31] [26]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_3
(.I0(\s_axi_araddr[31] [25]),
.I1(\s_axi_araddr[31] [27]),
.I2(\s_axi_araddr[31] [23]),
.I3(\s_axi_araddr[31] [24]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_4
(.I0(\s_axi_araddr[31] [18]),
.I1(\s_axi_araddr[31] [19]),
.I2(\s_axi_araddr[31] [16]),
.I3(\s_axi_araddr[31] [21]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.O(cmd_push_7));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2
(.I0(\s_axi_araddr[25]_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFF5555CFFF5555))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'hFFEF))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]
(.C(aclk),
.CE(cmd_push_7),
.D(st_aa_artarget_hot),
.Q(active_target[56]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]
(.C(aclk),
.CE(cmd_push_7),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[57]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT4 #(
.INIT(16'h7F40))
\gen_no_arbiter.m_target_hot_i[2]_i_1__0
(.I0(\s_axi_araddr[25]_0 ),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(\gen_no_arbiter.m_target_hot_i_reg[2]_0 ),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
LUT5 #(
.INIT(32'hDDDDFFFD))
\gen_no_arbiter.s_ready_i[0]_i_10__0
(.I0(aid_match_30),
.I1(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.I2(\s_axi_araddr[25] ),
.I3(active_target[25]),
.I4(active_target[24]),
.O(\gen_no_arbiter.s_ready_i[0]_i_10__0_n_0 ));
LUT5 #(
.INIT(32'h88880008))
\gen_no_arbiter.s_ready_i[0]_i_11
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I2(\s_axi_araddr[25] ),
.I3(active_target[49]),
.I4(active_target[48]),
.O(\gen_no_arbiter.s_ready_i[0]_i_11_n_0 ));
LUT5 #(
.INIT(32'h22220002))
\gen_no_arbiter.s_ready_i[0]_i_12__0
(.I0(aid_match_50),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I2(\s_axi_araddr[25] ),
.I3(active_target[41]),
.I4(active_target[40]),
.O(\gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ));
LUT6 #(
.INIT(64'h40FF404040404040))
\gen_no_arbiter.s_ready_i[0]_i_13
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I1(aid_match_10),
.I2(active_target[8]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I4(aid_match_00),
.I5(active_target[0]),
.O(\gen_no_arbiter.s_ready_i[0]_i_13_n_0 ));
LUT6 #(
.INIT(64'h0404040404FF0404))
\gen_no_arbiter.s_ready_i[0]_i_14__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I1(aid_match_50),
.I2(active_target[40]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I4(aid_match_10),
.I5(active_target[8]),
.O(\gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ));
LUT6 #(
.INIT(64'h1010101010FF1010))
\gen_no_arbiter.s_ready_i[0]_i_15__0
(.I0(active_target[16]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I2(aid_match_20),
.I3(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.I4(aid_match_30),
.I5(active_target[24]),
.O(\gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ));
LUT6 #(
.INIT(64'h00000000AAAAAAA8))
\gen_no_arbiter.s_ready_i[0]_i_16__0
(.I0(aid_match_00),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.I3(active_cnt[3]),
.I4(active_cnt[2]),
.I5(active_target[0]),
.O(\gen_no_arbiter.s_ready_i[0]_i_16__0_n_0 ));
LUT6 #(
.INIT(64'h08080808FF080808))
\gen_no_arbiter.s_ready_i[0]_i_17__0
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I2(active_target[48]),
.I3(aid_match_40),
.I4(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I5(active_target[32]),
.O(\gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ));
LUT6 #(
.INIT(64'h00000000F1000000))
\gen_no_arbiter.s_ready_i[0]_i_18__0
(.I0(active_target[33]),
.I1(\s_axi_araddr[25] ),
.I2(active_target[32]),
.I3(aid_match_40),
.I4(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I5(st_aa_artarget_hot),
.O(\gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ));
LUT6 #(
.INIT(64'h80FF808080808080))
\gen_no_arbiter.s_ready_i[0]_i_19__0
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I2(active_target[49]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I4(aid_match_20),
.I5(active_target[17]),
.O(\gen_no_arbiter.s_ready_i[0]_i_19__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT2 #(
.INIT(4'h8))
\gen_no_arbiter.s_ready_i[0]_i_1__0
(.I0(m_valid_i),
.I1(aresetn_d),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT6 #(
.INIT(64'h7F007F7F7F7F7F7F))
\gen_no_arbiter.s_ready_i[0]_i_20__0
(.I0(active_target[33]),
.I1(aid_match_40),
.I2(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I4(aid_match_50),
.I5(active_target[41]),
.O(\gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ));
LUT6 #(
.INIT(64'h80FF808080808080))
\gen_no_arbiter.s_ready_i[0]_i_21__0
(.I0(aid_match_70),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.I2(active_target[57]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.I4(aid_match_30),
.I5(active_target[25]),
.O(\gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ));
LUT6 #(
.INIT(64'h40FF404040404040))
\gen_no_arbiter.s_ready_i[0]_i_22__0
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I1(aid_match_10),
.I2(active_target[9]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I4(aid_match_00),
.I5(active_target[1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT4 #(
.INIT(16'hFFFD))
\gen_no_arbiter.s_ready_i[0]_i_24__0
(.I0(\gen_multi_thread.accept_cnt_reg__0 [3]),
.I1(\gen_multi_thread.accept_cnt_reg__0 [2]),
.I2(\gen_multi_thread.accept_cnt_reg__0 [1]),
.I3(\gen_multi_thread.accept_cnt_reg__0 [0]),
.O(\gen_no_arbiter.s_ready_i_reg[0]_0 ));
LUT6 #(
.INIT(64'h00000000000002F2))
\gen_no_arbiter.s_ready_i[0]_i_2__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ),
.I2(st_aa_artarget_hot),
.I3(\gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ),
.I5(\gen_no_arbiter.m_valid_i_reg ),
.O(m_valid_i));
LUT6 #(
.INIT(64'h0000000000000E00))
\gen_no_arbiter.s_ready_i[0]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_8_n_0 ),
.I1(\s_axi_araddr[25] ),
.I2(\gen_no_arbiter.s_ready_i[0]_i_9_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_10__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_11_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF0000111F))
\gen_no_arbiter.s_ready_i[0]_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I1(active_target[9]),
.I2(active_target[1]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ),
.I4(\s_axi_araddr[25] ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_13_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEEEF))
\gen_no_arbiter.s_ready_i[0]_i_5__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I3(active_target[56]),
.I4(\gen_no_arbiter.s_ready_i[0]_i_16__0_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEFAAAAAAAA))
\gen_no_arbiter.s_ready_i[0]_i_6__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_19__0_n_0 ),
.I2(\gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ),
.I5(\s_axi_araddr[25]_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ));
LUT6 #(
.INIT(64'hF7F7F700F7F7F7F7))
\gen_no_arbiter.s_ready_i[0]_i_8
(.I0(aid_match_70),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.I2(active_target[57]),
.I3(active_target[17]),
.I4(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I5(aid_match_20),
.O(\gen_no_arbiter.s_ready_i[0]_i_8_n_0 ));
LUT6 #(
.INIT(64'h80FF808080808080))
\gen_no_arbiter.s_ready_i[0]_i_9
(.I0(aid_match_70),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.I2(active_target[56]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I4(aid_match_20),
.I5(active_target[16]),
.O(\gen_no_arbiter.s_ready_i[0]_i_9_n_0 ));
CARRY4 \p_0_out_inferred__9/i__carry
(.CI(1'b0),
.CO({p_0_out,\p_0_out_inferred__9/i__carry_n_1 ,\p_0_out_inferred__9/i__carry_n_2 ,\p_0_out_inferred__9/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED [3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_48 ,\gen_multi_thread.arbiter_resp_inst_n_49 ,\gen_multi_thread.arbiter_resp_inst_n_50 ,\gen_multi_thread.arbiter_resp_inst_n_51 }));
CARRY4 p_10_out_carry
(.CI(1'b0),
.CO({p_10_out,p_10_out_carry_n_1,p_10_out_carry_n_2,p_10_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_10_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_28 ,\gen_multi_thread.arbiter_resp_inst_n_29 ,\gen_multi_thread.arbiter_resp_inst_n_30 ,\gen_multi_thread.arbiter_resp_inst_n_31 }));
CARRY4 p_12_out_carry
(.CI(1'b0),
.CO({p_12_out,p_12_out_carry_n_1,p_12_out_carry_n_2,p_12_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_12_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_24 ,\gen_multi_thread.arbiter_resp_inst_n_25 ,\gen_multi_thread.arbiter_resp_inst_n_26 ,\gen_multi_thread.arbiter_resp_inst_n_27 }));
CARRY4 p_14_out_carry
(.CI(1'b0),
.CO({p_14_out,p_14_out_carry_n_1,p_14_out_carry_n_2,p_14_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_14_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_20 ,\gen_multi_thread.arbiter_resp_inst_n_21 ,\gen_multi_thread.arbiter_resp_inst_n_22 ,\gen_multi_thread.arbiter_resp_inst_n_23 }));
CARRY4 p_2_out_carry
(.CI(1'b0),
.CO({p_2_out,p_2_out_carry_n_1,p_2_out_carry_n_2,p_2_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_2_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_44 ,\gen_multi_thread.arbiter_resp_inst_n_45 ,\gen_multi_thread.arbiter_resp_inst_n_46 ,\gen_multi_thread.arbiter_resp_inst_n_47 }));
CARRY4 p_4_out_carry
(.CI(1'b0),
.CO({p_4_out,p_4_out_carry_n_1,p_4_out_carry_n_2,p_4_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_4_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_40 ,\gen_multi_thread.arbiter_resp_inst_n_41 ,\gen_multi_thread.arbiter_resp_inst_n_42 ,\gen_multi_thread.arbiter_resp_inst_n_43 }));
CARRY4 p_6_out_carry
(.CI(1'b0),
.CO({p_6_out,p_6_out_carry_n_1,p_6_out_carry_n_2,p_6_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_6_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_36 ,\gen_multi_thread.arbiter_resp_inst_n_37 ,\gen_multi_thread.arbiter_resp_inst_n_38 ,\gen_multi_thread.arbiter_resp_inst_n_39 }));
CARRY4 p_8_out_carry
(.CI(1'b0),
.CO({p_8_out,p_8_out_carry_n_1,p_8_out_carry_n_2,p_8_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_8_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_32 ,\gen_multi_thread.arbiter_resp_inst_n_33 ,\gen_multi_thread.arbiter_resp_inst_n_34 ,\gen_multi_thread.arbiter_resp_inst_n_35 }));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_si_transactor" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
\gen_master_slots[0].w_issuing_cnt_reg[1] ,
chosen,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
st_aa_awtarget_enc,
D,
SR,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ,
Q,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
s_axi_bvalid,
\gen_master_slots[1].w_issuing_cnt_reg[8] ,
\gen_master_slots[2].w_issuing_cnt_reg[16] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ,
S,
aresetn_d,
st_aa_awtarget_hot,
\m_ready_d_reg[1] ,
p_80_out,
s_axi_bready,
aa_mi_awtarget_hot,
\gen_master_slots[1].w_issuing_cnt_reg[10] ,
\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ,
\s_axi_awaddr[31] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[2] ,
\m_payload_i_reg[4] ,
\m_payload_i_reg[6] ,
\m_payload_i_reg[5] ,
\m_payload_i_reg[7] ,
\m_payload_i_reg[12] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[13] ,
aa_sa_awvalid,
s_axi_awvalid,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
m_valid_i_reg,
p_38_out,
p_60_out,
w_issuing_cnt,
\m_ready_d_reg[1]_0 ,
aclk);
output \gen_no_arbiter.s_ready_i_reg[0] ;
output m_valid_i;
output \gen_master_slots[0].w_issuing_cnt_reg[1] ;
output [2:0]chosen;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [0:0]st_aa_awtarget_enc;
output [0:0]D;
output [0:0]SR;
output \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ;
output \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ;
output [2:0]Q;
output [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
output [0:0]s_axi_bvalid;
output \gen_master_slots[1].w_issuing_cnt_reg[8] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16] ;
input [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ;
input [0:0]S;
input aresetn_d;
input [0:0]st_aa_awtarget_hot;
input \m_ready_d_reg[1] ;
input p_80_out;
input [0:0]s_axi_bready;
input [0:0]aa_mi_awtarget_hot;
input \gen_master_slots[1].w_issuing_cnt_reg[10] ;
input \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
input [27:0]\s_axi_awaddr[31] ;
input \m_payload_i_reg[3] ;
input \m_payload_i_reg[2] ;
input \m_payload_i_reg[4] ;
input \m_payload_i_reg[6] ;
input \m_payload_i_reg[5] ;
input \m_payload_i_reg[7] ;
input \m_payload_i_reg[12] ;
input \m_payload_i_reg[11] ;
input \m_payload_i_reg[13] ;
input aa_sa_awvalid;
input [0:0]s_axi_awvalid;
input \gen_no_arbiter.s_ready_i_reg[0]_0 ;
input m_valid_i_reg;
input p_38_out;
input p_60_out;
input [4:0]w_issuing_cnt;
input \m_ready_d_reg[1]_0 ;
input aclk;
wire [0:0]D;
wire [2:0]Q;
wire [0:0]S;
wire [0:0]SR;
wire [0:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire [59:0]active_cnt;
wire [57:0]active_target;
wire aid_match_00;
wire aid_match_00_carry_i_1__0_n_0;
wire aid_match_00_carry_i_2__0_n_0;
wire aid_match_00_carry_i_3__0_n_0;
wire aid_match_00_carry_i_4__0_n_0;
wire aid_match_00_carry_n_1;
wire aid_match_00_carry_n_2;
wire aid_match_00_carry_n_3;
wire aid_match_10;
wire aid_match_10_carry_i_1__0_n_0;
wire aid_match_10_carry_i_2__0_n_0;
wire aid_match_10_carry_i_3__0_n_0;
wire aid_match_10_carry_i_4__0_n_0;
wire aid_match_10_carry_n_1;
wire aid_match_10_carry_n_2;
wire aid_match_10_carry_n_3;
wire aid_match_20;
wire aid_match_20_carry_i_1__0_n_0;
wire aid_match_20_carry_i_2__0_n_0;
wire aid_match_20_carry_i_3__0_n_0;
wire aid_match_20_carry_i_4__0_n_0;
wire aid_match_20_carry_n_1;
wire aid_match_20_carry_n_2;
wire aid_match_20_carry_n_3;
wire aid_match_30;
wire aid_match_30_carry_i_1__0_n_0;
wire aid_match_30_carry_i_2__0_n_0;
wire aid_match_30_carry_i_3__0_n_0;
wire aid_match_30_carry_i_4__0_n_0;
wire aid_match_30_carry_n_1;
wire aid_match_30_carry_n_2;
wire aid_match_30_carry_n_3;
wire aid_match_40;
wire aid_match_40_carry_i_1__0_n_0;
wire aid_match_40_carry_i_2__0_n_0;
wire aid_match_40_carry_i_3__0_n_0;
wire aid_match_40_carry_i_4__0_n_0;
wire aid_match_40_carry_n_1;
wire aid_match_40_carry_n_2;
wire aid_match_40_carry_n_3;
wire aid_match_50;
wire aid_match_50_carry_i_1__0_n_0;
wire aid_match_50_carry_i_2__0_n_0;
wire aid_match_50_carry_i_3__0_n_0;
wire aid_match_50_carry_i_4__0_n_0;
wire aid_match_50_carry_n_1;
wire aid_match_50_carry_n_2;
wire aid_match_50_carry_n_3;
wire aid_match_60;
wire aid_match_60_carry_i_1__0_n_0;
wire aid_match_60_carry_i_2__0_n_0;
wire aid_match_60_carry_i_3__0_n_0;
wire aid_match_60_carry_i_4__0_n_0;
wire aid_match_60_carry_n_1;
wire aid_match_60_carry_n_2;
wire aid_match_60_carry_n_3;
wire aid_match_70;
wire aid_match_70_carry_i_1__0_n_0;
wire aid_match_70_carry_i_2__0_n_0;
wire aid_match_70_carry_i_3__0_n_0;
wire aid_match_70_carry_i_4__0_n_0;
wire aid_match_70_carry_n_1;
wire aid_match_70_carry_n_2;
wire aid_match_70_carry_n_3;
wire aresetn_d;
wire [2:0]chosen;
wire cmd_push_0;
wire cmd_push_1;
wire cmd_push_2;
wire cmd_push_3;
wire cmd_push_4;
wire cmd_push_5;
wire cmd_push_6;
wire cmd_push_7;
wire \gen_master_slots[0].w_issuing_cnt_reg[1] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[10] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
wire \gen_multi_thread.accept_cnt[0]_i_1_n_0 ;
wire [3:0]\gen_multi_thread.accept_cnt_reg ;
wire \gen_multi_thread.arbiter_resp_inst_n_10 ;
wire \gen_multi_thread.arbiter_resp_inst_n_11 ;
wire \gen_multi_thread.arbiter_resp_inst_n_12 ;
wire \gen_multi_thread.arbiter_resp_inst_n_13 ;
wire \gen_multi_thread.arbiter_resp_inst_n_14 ;
wire \gen_multi_thread.arbiter_resp_inst_n_15 ;
wire \gen_multi_thread.arbiter_resp_inst_n_16 ;
wire \gen_multi_thread.arbiter_resp_inst_n_17 ;
wire \gen_multi_thread.arbiter_resp_inst_n_2 ;
wire \gen_multi_thread.arbiter_resp_inst_n_3 ;
wire \gen_multi_thread.arbiter_resp_inst_n_4 ;
wire \gen_multi_thread.arbiter_resp_inst_n_9 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg ;
wire \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg ;
wire [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg ;
wire [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i[0]_i_10_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_12_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_14_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_15_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_16_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_17_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_18_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_19_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_20_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_21_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_22_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_23_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_28_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_3_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_4_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_5_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_6_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire i__carry_i_1_n_0;
wire i__carry_i_3_n_0;
wire i__carry_i_4_n_0;
wire \m_payload_i_reg[11] ;
wire \m_payload_i_reg[12] ;
wire \m_payload_i_reg[13] ;
wire \m_payload_i_reg[2] ;
wire \m_payload_i_reg[3] ;
wire \m_payload_i_reg[4] ;
wire \m_payload_i_reg[5] ;
wire \m_payload_i_reg[6] ;
wire \m_payload_i_reg[7] ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire m_valid_i;
wire m_valid_i_reg;
wire p_0_out;
wire \p_0_out_inferred__9/i__carry_n_1 ;
wire \p_0_out_inferred__9/i__carry_n_2 ;
wire \p_0_out_inferred__9/i__carry_n_3 ;
wire p_10_out;
wire p_10_out_carry_i_1_n_0;
wire p_10_out_carry_i_3_n_0;
wire p_10_out_carry_i_4_n_0;
wire p_10_out_carry_n_1;
wire p_10_out_carry_n_2;
wire p_10_out_carry_n_3;
wire p_12_out;
wire p_12_out_carry_i_1_n_0;
wire p_12_out_carry_i_3_n_0;
wire p_12_out_carry_i_4_n_0;
wire p_12_out_carry_n_1;
wire p_12_out_carry_n_2;
wire p_12_out_carry_n_3;
wire p_14_out;
wire p_14_out_carry_i_1_n_0;
wire p_14_out_carry_i_3_n_0;
wire p_14_out_carry_i_4_n_0;
wire p_14_out_carry_n_1;
wire p_14_out_carry_n_2;
wire p_14_out_carry_n_3;
wire p_2_out;
wire p_2_out_carry_i_1_n_0;
wire p_2_out_carry_i_3_n_0;
wire p_2_out_carry_i_4_n_0;
wire p_2_out_carry_n_1;
wire p_2_out_carry_n_2;
wire p_2_out_carry_n_3;
wire p_38_out;
wire p_4_out;
wire p_4_out_carry_i_1_n_0;
wire p_4_out_carry_i_3_n_0;
wire p_4_out_carry_i_4_n_0;
wire p_4_out_carry_n_1;
wire p_4_out_carry_n_2;
wire p_4_out_carry_n_3;
wire p_60_out;
wire p_6_out;
wire p_6_out_carry_i_1_n_0;
wire p_6_out_carry_i_3_n_0;
wire p_6_out_carry_i_4_n_0;
wire p_6_out_carry_n_1;
wire p_6_out_carry_n_2;
wire p_6_out_carry_n_3;
wire p_80_out;
wire p_8_out;
wire p_8_out_carry_i_1_n_0;
wire p_8_out_carry_i_3_n_0;
wire p_8_out_carry_i_4_n_0;
wire p_8_out_carry_n_1;
wire p_8_out_carry_n_2;
wire p_8_out_carry_n_3;
wire [27:0]\s_axi_awaddr[31] ;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_bvalid;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire [4:0]w_issuing_cnt;
wire [3:0]NLW_aid_match_00_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_10_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_20_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_30_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_40_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_50_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_60_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_70_carry_O_UNCONNECTED;
wire [3:0]\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED ;
wire [3:0]NLW_p_10_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_12_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_14_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_2_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_4_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_6_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_8_out_carry_O_UNCONNECTED;
CARRY4 aid_match_00_carry
(.CI(1'b0),
.CO({aid_match_00,aid_match_00_carry_n_1,aid_match_00_carry_n_2,aid_match_00_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_00_carry_O_UNCONNECTED[3:0]),
.S({aid_match_00_carry_i_1__0_n_0,aid_match_00_carry_i_2__0_n_0,aid_match_00_carry_i_3__0_n_0,aid_match_00_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [11]),
.I4(\s_axi_awaddr[31] [10]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [10]),
.O(aid_match_00_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_2__0
(.I0(Q[0]),
.I1(\s_axi_awaddr[31] [6]),
.I2(\s_axi_awaddr[31] [7]),
.I3(Q[1]),
.I4(\s_axi_awaddr[31] [8]),
.I5(Q[2]),
.O(aid_match_00_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [3]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [3]),
.I4(\s_axi_awaddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [5]),
.O(aid_match_00_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg [0]),
.I1(\s_axi_awaddr[31] [0]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [1]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [1]),
.O(aid_match_00_carry_i_4__0_n_0));
CARRY4 aid_match_10_carry
(.CI(1'b0),
.CO({aid_match_10,aid_match_10_carry_n_1,aid_match_10_carry_n_2,aid_match_10_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_10_carry_O_UNCONNECTED[3:0]),
.S({aid_match_10_carry_i_1__0_n_0,aid_match_10_carry_i_2__0_n_0,aid_match_10_carry_i_3__0_n_0,aid_match_10_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_1__0
(.I0(\s_axi_awaddr[31] [9]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [9]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [10]),
.I3(\s_axi_awaddr[31] [10]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [11]),
.I5(\s_axi_awaddr[31] [11]),
.O(aid_match_10_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_2__0
(.I0(\s_axi_awaddr[31] [6]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [0]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [2]),
.I3(\s_axi_awaddr[31] [8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [1]),
.I5(\s_axi_awaddr[31] [7]),
.O(aid_match_10_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_3__0
(.I0(\s_axi_awaddr[31] [3]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [3]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [4]),
.I3(\s_axi_awaddr[31] [4]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [5]),
.I5(\s_axi_awaddr[31] [5]),
.O(aid_match_10_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_4__0
(.I0(\s_axi_awaddr[31] [0]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [0]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [2]),
.I3(\s_axi_awaddr[31] [2]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [1]),
.I5(\s_axi_awaddr[31] [1]),
.O(aid_match_10_carry_i_4__0_n_0));
CARRY4 aid_match_20_carry
(.CI(1'b0),
.CO({aid_match_20,aid_match_20_carry_n_1,aid_match_20_carry_n_2,aid_match_20_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_20_carry_O_UNCONNECTED[3:0]),
.S({aid_match_20_carry_i_1__0_n_0,aid_match_20_carry_i_2__0_n_0,aid_match_20_carry_i_3__0_n_0,aid_match_20_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [10]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [11]),
.O(aid_match_20_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [2]),
.I4(\s_axi_awaddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [0]),
.O(aid_match_20_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [3]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [3]),
.O(aid_match_20_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [0]),
.I4(\s_axi_awaddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [2]),
.O(aid_match_20_carry_i_4__0_n_0));
CARRY4 aid_match_30_carry
(.CI(1'b0),
.CO({aid_match_30,aid_match_30_carry_n_1,aid_match_30_carry_n_2,aid_match_30_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_30_carry_O_UNCONNECTED[3:0]),
.S({aid_match_30_carry_i_1__0_n_0,aid_match_30_carry_i_2__0_n_0,aid_match_30_carry_i_3__0_n_0,aid_match_30_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg [10]),
.I1(\s_axi_awaddr[31] [10]),
.I2(\s_axi_awaddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [11]),
.I4(\s_axi_awaddr[31] [9]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [9]),
.O(aid_match_30_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [0]),
.I1(\s_axi_awaddr[31] [6]),
.I2(\s_axi_awaddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [1]),
.I4(\s_axi_awaddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [2]),
.O(aid_match_30_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg [3]),
.I1(\s_axi_awaddr[31] [3]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [4]),
.O(aid_match_30_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [0]),
.O(aid_match_30_carry_i_4__0_n_0));
CARRY4 aid_match_40_carry
(.CI(1'b0),
.CO({aid_match_40,aid_match_40_carry_n_1,aid_match_40_carry_n_2,aid_match_40_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_40_carry_O_UNCONNECTED[3:0]),
.S({aid_match_40_carry_i_1__0_n_0,aid_match_40_carry_i_2__0_n_0,aid_match_40_carry_i_3__0_n_0,aid_match_40_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [10]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [11]),
.O(aid_match_40_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [6]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [0]),
.I4(\s_axi_awaddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [2]),
.O(aid_match_40_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [3]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [3]),
.I4(\s_axi_awaddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [5]),
.O(aid_match_40_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [0]),
.O(aid_match_40_carry_i_4__0_n_0));
CARRY4 aid_match_50_carry
(.CI(1'b0),
.CO({aid_match_50,aid_match_50_carry_n_1,aid_match_50_carry_n_2,aid_match_50_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_50_carry_O_UNCONNECTED[3:0]),
.S({aid_match_50_carry_i_1__0_n_0,aid_match_50_carry_i_2__0_n_0,aid_match_50_carry_i_3__0_n_0,aid_match_50_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg [10]),
.I1(\s_axi_awaddr[31] [10]),
.I2(\s_axi_awaddr[31] [9]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [9]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [11]),
.O(aid_match_50_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [2]),
.I4(\s_axi_awaddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [0]),
.O(aid_match_50_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [3]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [3]),
.O(aid_match_50_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg [0]),
.I1(\s_axi_awaddr[31] [0]),
.I2(\s_axi_awaddr[31] [1]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [1]),
.I4(\s_axi_awaddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [2]),
.O(aid_match_50_carry_i_4__0_n_0));
CARRY4 aid_match_60_carry
(.CI(1'b0),
.CO({aid_match_60,aid_match_60_carry_n_1,aid_match_60_carry_n_2,aid_match_60_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_60_carry_O_UNCONNECTED[3:0]),
.S({aid_match_60_carry_i_1__0_n_0,aid_match_60_carry_i_2__0_n_0,aid_match_60_carry_i_3__0_n_0,aid_match_60_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [11]),
.I4(\s_axi_awaddr[31] [10]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [10]),
.O(aid_match_60_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [0]),
.I1(\s_axi_awaddr[31] [6]),
.I2(\s_axi_awaddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [2]),
.I4(\s_axi_awaddr[31] [7]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [1]),
.O(aid_match_60_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg [3]),
.I1(\s_axi_awaddr[31] [3]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [4]),
.O(aid_match_60_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg [0]),
.I1(\s_axi_awaddr[31] [0]),
.I2(\s_axi_awaddr[31] [1]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [1]),
.I4(\s_axi_awaddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [2]),
.O(aid_match_60_carry_i_4__0_n_0));
CARRY4 aid_match_70_carry
(.CI(1'b0),
.CO({aid_match_70,aid_match_70_carry_n_1,aid_match_70_carry_n_2,aid_match_70_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_70_carry_O_UNCONNECTED[3:0]),
.S({aid_match_70_carry_i_1__0_n_0,aid_match_70_carry_i_2__0_n_0,aid_match_70_carry_i_3__0_n_0,aid_match_70_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [10]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [11]),
.O(aid_match_70_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [6]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [0]),
.I4(\s_axi_awaddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [2]),
.O(aid_match_70_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [3]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [3]),
.O(aid_match_70_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [0]),
.O(aid_match_70_carry_i_4__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair136" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.accept_cnt[0]_i_1
(.I0(\gen_multi_thread.accept_cnt_reg [0]),
.O(\gen_multi_thread.accept_cnt[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.accept_cnt[0]_i_1_n_0 ),
.Q(\gen_multi_thread.accept_cnt_reg [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.Q(\gen_multi_thread.accept_cnt_reg [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_3 ),
.Q(\gen_multi_thread.accept_cnt_reg [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_2 ),
.Q(\gen_multi_thread.accept_cnt_reg [3]),
.R(SR));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp \gen_multi_thread.arbiter_resp_inst
(.CO(p_0_out),
.D({\gen_multi_thread.arbiter_resp_inst_n_2 ,\gen_multi_thread.arbiter_resp_inst_n_3 ,\gen_multi_thread.arbiter_resp_inst_n_4 }),
.E(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.Q(\gen_multi_thread.accept_cnt_reg ),
.SR(SR),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\chosen_reg[0]_0 (chosen[0]),
.\chosen_reg[1]_0 (chosen[1]),
.cmd_push_0(cmd_push_0),
.cmd_push_3(cmd_push_3),
.\gen_master_slots[0].w_issuing_cnt_reg[1] (\gen_master_slots[0].w_issuing_cnt_reg[1] ),
.\gen_master_slots[1].w_issuing_cnt_reg[10] (\gen_master_slots[1].w_issuing_cnt_reg[10] ),
.\gen_master_slots[1].w_issuing_cnt_reg[8] (\gen_master_slots[1].w_issuing_cnt_reg[8] ),
.\gen_master_slots[2].w_issuing_cnt_reg[16] (chosen[2]),
.\gen_master_slots[2].w_issuing_cnt_reg[16]_0 (\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.\gen_master_slots[2].w_issuing_cnt_reg[16]_1 (\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ),
.\gen_multi_thread.accept_cnt_reg[0] (\gen_no_arbiter.s_ready_i[0]_i_28_n_0 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.arbiter_resp_inst_n_17 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.arbiter_resp_inst_n_16 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] (p_14_out),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_multi_thread.arbiter_resp_inst_n_15 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] (p_12_out),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] (\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_multi_thread.arbiter_resp_inst_n_14 ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] (p_10_out),
.\gen_multi_thread.gen_thread_loop[2].active_target_reg[17] (\gen_no_arbiter.s_ready_i[0]_i_6_n_0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] (\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] (\gen_multi_thread.arbiter_resp_inst_n_13 ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] (p_8_out),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] (\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_multi_thread.arbiter_resp_inst_n_12 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 (\gen_no_arbiter.s_ready_i[0]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 (\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] (p_6_out),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] (\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_multi_thread.arbiter_resp_inst_n_11 ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] (p_4_out),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_multi_thread.arbiter_resp_inst_n_10 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] (\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] (p_2_out),
.\gen_multi_thread.gen_thread_loop[6].active_target_reg[48] (\gen_no_arbiter.s_ready_i[0]_i_5_n_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] (\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_no_arbiter.s_ready_i[0]_i_4_n_0 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_no_arbiter.m_target_hot_i_reg[2] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (\gen_no_arbiter.s_ready_i_reg[0]_0 ),
.\m_ready_d_reg[1] (\m_ready_d_reg[1] ),
.\m_ready_d_reg[1]_0 (\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.\m_ready_d_reg[1]_1 (\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.\m_ready_d_reg[1]_2 (\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.\m_ready_d_reg[1]_3 (\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.\m_ready_d_reg[1]_4 (\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.\m_ready_d_reg[1]_5 (\m_ready_d_reg[1]_0 ),
.m_valid_i(m_valid_i),
.m_valid_i_reg(m_valid_i_reg),
.p_38_out(p_38_out),
.p_60_out(p_60_out),
.p_80_out(p_80_out),
.\s_axi_awaddr[26] (st_aa_awtarget_enc),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.w_issuing_cnt(w_issuing_cnt));
(* SOFT_HLUTNM = "soft_lutpair138" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0
(.I0(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair138" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1
(.I0(cmd_push_0),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1
(.I0(active_cnt[2]),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.I3(cmd_push_0),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2
(.I0(active_cnt[3]),
.I1(active_cnt[2]),
.I2(cmd_push_0),
.I3(active_cnt[1]),
.I4(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ),
.Q(active_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ),
.Q(active_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ),
.Q(active_cnt[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ),
.Q(active_cnt[3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [11]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[2]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[3]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[4]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[5]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[6]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [6]),
.Q(Q[0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[7]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [7]),
.Q(Q[1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [8]),
.Q(Q[2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[9]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [9]),
.R(SR));
LUT6 #(
.INIT(64'h0500050035300500))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I3(aid_match_00),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(cmd_push_0));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2
(.I0(aid_match_40),
.I1(active_cnt[34]),
.I2(active_cnt[35]),
.I3(active_cnt[33]),
.I4(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3
(.I0(active_cnt[42]),
.I1(active_cnt[43]),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(aid_match_50),
.O(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(st_aa_awtarget_enc),
.Q(active_target[0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(D),
.Q(active_target[1]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1
(.I0(active_cnt[10]),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2
(.I0(active_cnt[11]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFBBFFBBF0BBFFBB))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3
(.I0(\m_ready_d_reg[1] ),
.I1(aid_match_10),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0
(.I0(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ),
.Q(active_cnt[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ),
.Q(active_cnt[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ),
.Q(active_cnt[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ),
.Q(active_cnt[9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[13]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[14]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[15]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[16]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[17]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[18]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[21]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [11]),
.R(SR));
LUT5 #(
.INIT(32'h08083B08))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I3(aid_match_10),
.I4(\m_ready_d_reg[1] ),
.O(cmd_push_1));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT4 #(
.INIT(16'h0010))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2
(.I0(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3
(.I0(active_cnt[8]),
.I1(active_cnt[9]),
.I2(active_cnt[11]),
.I3(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4
(.I0(active_cnt[0]),
.I1(active_cnt[1]),
.I2(active_cnt[3]),
.I3(active_cnt[2]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]
(.C(aclk),
.CE(cmd_push_1),
.D(st_aa_awtarget_enc),
.Q(active_target[8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]
(.C(aclk),
.CE(cmd_push_1),
.D(D),
.Q(active_target[9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair135" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0
(.I0(active_cnt[16]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair135" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1
(.I0(active_cnt[18]),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2
(.I0(active_cnt[19]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3
(.I0(active_cnt[16]),
.I1(active_cnt[17]),
.I2(active_cnt[19]),
.I3(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ),
.Q(active_cnt[16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ),
.Q(active_cnt[17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ),
.Q(active_cnt[18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ),
.Q(active_cnt[19]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[24]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[25]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[26]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[27]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[28]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[29]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[30]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[33]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.O(cmd_push_2));
LUT6 #(
.INIT(64'hFFDDFFDDF0DDFFDD))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2
(.I0(aid_match_20),
.I1(\m_ready_d_reg[1] ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3
(.I0(active_cnt[10]),
.I1(active_cnt[11]),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[16]
(.C(aclk),
.CE(cmd_push_2),
.D(st_aa_awtarget_enc),
.Q(active_target[16]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]
(.C(aclk),
.CE(cmd_push_2),
.D(D),
.Q(active_target[17]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0
(.I0(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1
(.I0(cmd_push_3),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1
(.I0(active_cnt[26]),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(cmd_push_3),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2
(.I0(active_cnt[27]),
.I1(active_cnt[26]),
.I2(cmd_push_3),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ),
.Q(active_cnt[24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ),
.Q(active_cnt[25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ),
.Q(active_cnt[26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ),
.Q(active_cnt[27]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[37]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[38]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[39]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[40]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[41]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[42]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[45]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [11]),
.R(SR));
LUT6 #(
.INIT(64'h004400440F440044))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(aid_match_30),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(cmd_push_3));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF0001))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4
(.I0(active_cnt[24]),
.I1(active_cnt[25]),
.I2(active_cnt[27]),
.I3(active_cnt[26]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT3 #(
.INIT(8'h02))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5
(.I0(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(aid_match_20),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8
(.I0(aid_match_10),
.I1(active_cnt[10]),
.I2(active_cnt[11]),
.I3(active_cnt[9]),
.I4(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9
(.I0(aid_match_30),
.I1(active_cnt[26]),
.I2(active_cnt[27]),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]
(.C(aclk),
.CE(cmd_push_3),
.D(st_aa_awtarget_enc),
.Q(active_target[24]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]
(.C(aclk),
.CE(cmd_push_3),
.D(D),
.Q(active_target[25]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0
(.I0(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1
(.I0(active_cnt[34]),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2
(.I0(active_cnt[35]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.I2(active_cnt[33]),
.I3(active_cnt[32]),
.I4(active_cnt[34]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3
(.I0(active_cnt[32]),
.I1(active_cnt[33]),
.I2(active_cnt[35]),
.I3(active_cnt[34]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ),
.Q(active_cnt[32]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ),
.Q(active_cnt[33]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ),
.Q(active_cnt[34]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ),
.Q(active_cnt[35]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[48]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[49]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[50]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[51]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[52]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[53]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[54]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[57]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.O(cmd_push_4));
LUT6 #(
.INIT(64'hAFAFAFAFAFACAFAF))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0 ),
.I1(active_cnt[34]),
.I2(active_cnt[35]),
.I3(active_cnt[33]),
.I4(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4
(.I0(aid_match_00),
.I1(active_cnt[2]),
.I2(active_cnt[3]),
.I3(active_cnt[1]),
.I4(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5
(.I0(active_cnt[26]),
.I1(active_cnt[27]),
.I2(active_cnt[25]),
.I3(active_cnt[24]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[32]
(.C(aclk),
.CE(cmd_push_4),
.D(st_aa_awtarget_enc),
.Q(active_target[32]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[33]
(.C(aclk),
.CE(cmd_push_4),
.D(D),
.Q(active_target[33]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair133" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0
(.I0(active_cnt[40]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair133" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1
(.I0(active_cnt[42]),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2
(.I0(active_cnt[43]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3
(.I0(active_cnt[40]),
.I1(active_cnt[41]),
.I2(active_cnt[43]),
.I3(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ),
.Q(active_cnt[40]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ),
.Q(active_cnt[41]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ),
.Q(active_cnt[42]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ),
.Q(active_cnt[43]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[60]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[61]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[62]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[63]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[64]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[65]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[66]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[69]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.O(cmd_push_5));
LUT6 #(
.INIT(64'hFAFAFFFFFACAFFCF))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ),
.I4(aid_match_50),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]
(.C(aclk),
.CE(cmd_push_5),
.D(st_aa_awtarget_enc),
.Q(active_target[40]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]
(.C(aclk),
.CE(cmd_push_5),
.D(D),
.Q(active_target[41]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair134" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0
(.I0(active_cnt[48]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair134" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1
(.I0(active_cnt[50]),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2
(.I0(active_cnt[51]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.I2(active_cnt[49]),
.I3(active_cnt[48]),
.I4(active_cnt[50]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3
(.I0(active_cnt[51]),
.I1(active_cnt[50]),
.I2(active_cnt[48]),
.I3(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ),
.Q(active_cnt[48]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ),
.Q(active_cnt[49]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ),
.Q(active_cnt[50]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ),
.Q(active_cnt[51]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[72]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[73]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[74]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[75]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[76]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[77]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[78]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[81]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.O(cmd_push_6));
LUT6 #(
.INIT(64'hEEEEEEEEEEE0EEEE))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3
(.I0(aid_match_60),
.I1(active_cnt[49]),
.I2(active_cnt[48]),
.I3(active_cnt[50]),
.I4(active_cnt[51]),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I2(active_cnt[51]),
.I3(active_cnt[50]),
.I4(active_cnt[48]),
.I5(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5
(.I0(active_cnt[32]),
.I1(active_cnt[33]),
.I2(active_cnt[35]),
.I3(active_cnt[34]),
.I4(aid_match_40),
.I5(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]
(.C(aclk),
.CE(cmd_push_6),
.D(st_aa_awtarget_enc),
.Q(active_target[48]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]
(.C(aclk),
.CE(cmd_push_6),
.D(D),
.Q(active_target[49]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair137" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0
(.I0(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair137" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1
(.I0(active_cnt[58]),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2
(.I0(active_cnt[59]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.I2(active_cnt[57]),
.I3(active_cnt[56]),
.I4(active_cnt[58]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4
(.I0(active_cnt[56]),
.I1(active_cnt[57]),
.I2(active_cnt[59]),
.I3(active_cnt[58]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ),
.Q(active_cnt[56]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ),
.Q(active_cnt[57]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ),
.Q(active_cnt[58]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ),
.Q(active_cnt[59]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[84]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[85]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[86]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[87]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[88]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[89]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[90]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[93]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [11]),
.R(SR));
LUT3 #(
.INIT(8'h02))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0 ),
.I1(\s_axi_awaddr[31] [17]),
.I2(\s_axi_awaddr[31] [20]),
.O(st_aa_awtarget_enc));
LUT6 #(
.INIT(64'h0000000000000002))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ),
.I2(\s_axi_awaddr[31] [19]),
.I3(\s_axi_awaddr[31] [15]),
.I4(\s_axi_awaddr[31] [12]),
.I5(\s_axi_awaddr[31] [23]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.O(cmd_push_7));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_10
(.I0(\s_axi_awaddr[31] [14]),
.I1(\s_axi_awaddr[31] [25]),
.I2(\s_axi_awaddr[31] [21]),
.I3(\s_axi_awaddr[31] [22]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ));
LUT6 #(
.INIT(64'h0000000000000100))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_11
(.I0(\s_axi_awaddr[31] [24]),
.I1(\s_axi_awaddr[31] [27]),
.I2(\s_axi_awaddr[31] [13]),
.I3(\s_axi_awaddr[31] [26]),
.I4(\s_axi_awaddr[31] [18]),
.I5(\s_axi_awaddr[31] [16]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ));
LUT2 #(
.INIT(4'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2__0
(.I0(st_aa_awtarget_enc),
.I1(st_aa_awtarget_hot),
.O(D));
LUT6 #(
.INIT(64'hFFFFFFFF0000FFEF))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ),
.I5(\m_ready_d_reg[1] ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF0001))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5
(.I0(active_cnt[34]),
.I1(active_cnt[35]),
.I2(active_cnt[33]),
.I3(active_cnt[32]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFD))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6
(.I0(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I2(active_cnt[58]),
.I3(active_cnt[59]),
.I4(active_cnt[57]),
.I5(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0 ));
LUT4 #(
.INIT(16'hEFFF))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8
(.I0(aid_match_70),
.I1(active_cnt[58]),
.I2(active_cnt[59]),
.I3(active_cnt[57]),
.I4(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]
(.C(aclk),
.CE(cmd_push_7),
.D(st_aa_awtarget_enc),
.Q(active_target[56]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]
(.C(aclk),
.CE(cmd_push_7),
.D(D),
.Q(active_target[57]),
.R(SR));
LUT5 #(
.INIT(32'h0000F100))
\gen_no_arbiter.s_ready_i[0]_i_10
(.I0(active_target[41]),
.I1(st_aa_awtarget_hot),
.I2(active_target[40]),
.I3(aid_match_50),
.I4(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_10_n_0 ));
LUT5 #(
.INIT(32'h22220002))
\gen_no_arbiter.s_ready_i[0]_i_11__0
(.I0(aid_match_20),
.I1(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I2(active_target[17]),
.I3(st_aa_awtarget_hot),
.I4(active_target[16]),
.O(\gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair139" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_12
(.I0(active_target[56]),
.I1(st_aa_awtarget_hot),
.I2(active_target[57]),
.O(\gen_no_arbiter.s_ready_i[0]_i_12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair139" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_13__0
(.I0(active_target[8]),
.I1(st_aa_awtarget_hot),
.I2(active_target[9]),
.O(\gen_no_arbiter.s_ready_i[0]_i_13__0_n_0 ));
LUT5 #(
.INIT(32'h44440004))
\gen_no_arbiter.s_ready_i[0]_i_14
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I1(aid_match_00),
.I2(active_target[1]),
.I3(st_aa_awtarget_hot),
.I4(active_target[0]),
.O(\gen_no_arbiter.s_ready_i[0]_i_14_n_0 ));
LUT5 #(
.INIT(32'h44440004))
\gen_no_arbiter.s_ready_i[0]_i_15
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.I1(aid_match_30),
.I2(active_target[25]),
.I3(st_aa_awtarget_hot),
.I4(active_target[24]),
.O(\gen_no_arbiter.s_ready_i[0]_i_15_n_0 ));
LUT6 #(
.INIT(64'h0404040404FF0404))
\gen_no_arbiter.s_ready_i[0]_i_16
(.I0(active_target[32]),
.I1(aid_match_40),
.I2(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ),
.I3(active_target[8]),
.I4(aid_match_10),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_16_n_0 ));
LUT6 #(
.INIT(64'hFBFBFBFBFB00FBFB))
\gen_no_arbiter.s_ready_i[0]_i_17
(.I0(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I1(aid_match_50),
.I2(active_target[40]),
.I3(active_target[24]),
.I4(aid_match_30),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_17_n_0 ));
LUT6 #(
.INIT(64'h0404040404FF0404))
\gen_no_arbiter.s_ready_i[0]_i_18
(.I0(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I1(aid_match_20),
.I2(active_target[16]),
.I3(active_target[0]),
.I4(aid_match_00),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_18_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_19
(.I0(active_cnt[56]),
.I1(active_cnt[57]),
.I2(active_cnt[59]),
.I3(active_cnt[58]),
.I4(aid_match_70),
.I5(active_target[56]),
.O(\gen_no_arbiter.s_ready_i[0]_i_19_n_0 ));
LUT6 #(
.INIT(64'h4040FF4040404040))
\gen_no_arbiter.s_ready_i[0]_i_20
(.I0(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I1(aid_match_20),
.I2(active_target[17]),
.I3(aid_match_00),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I5(active_target[1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_20_n_0 ));
LUT6 #(
.INIT(64'h2020FF2020202020))
\gen_no_arbiter.s_ready_i[0]_i_21
(.I0(aid_match_40),
.I1(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ),
.I2(active_target[33]),
.I3(aid_match_70),
.I4(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ),
.I5(active_target[57]),
.O(\gen_no_arbiter.s_ready_i[0]_i_21_n_0 ));
LUT6 #(
.INIT(64'hDFDF00DFDFDFDFDF))
\gen_no_arbiter.s_ready_i[0]_i_22
(.I0(active_target[41]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I2(aid_match_50),
.I3(aid_match_10),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.I5(active_target[9]),
.O(\gen_no_arbiter.s_ready_i[0]_i_22_n_0 ));
LUT6 #(
.INIT(64'h8080FF8080808080))
\gen_no_arbiter.s_ready_i[0]_i_23
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ),
.I2(active_target[49]),
.I3(aid_match_30),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.I5(active_target[25]),
.O(\gen_no_arbiter.s_ready_i[0]_i_23_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair136" *)
LUT3 #(
.INIT(8'h01))
\gen_no_arbiter.s_ready_i[0]_i_28
(.I0(\gen_multi_thread.accept_cnt_reg [0]),
.I1(\gen_multi_thread.accept_cnt_reg [1]),
.I2(\gen_multi_thread.accept_cnt_reg [2]),
.O(\gen_no_arbiter.s_ready_i[0]_i_28_n_0 ));
LUT6 #(
.INIT(64'h000000000000DDD0))
\gen_no_arbiter.s_ready_i[0]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_10_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF22F2))
\gen_no_arbiter.s_ready_i[0]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_12_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_13__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_14_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_15_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000004040400))
\gen_no_arbiter.s_ready_i[0]_i_5
(.I0(\gen_no_arbiter.s_ready_i[0]_i_16_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_17_n_0 ),
.I2(\gen_no_arbiter.s_ready_i[0]_i_18_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I4(active_target[48]),
.I5(\gen_no_arbiter.s_ready_i[0]_i_19_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'hEEEEEEEEEEE0EEEE))
\gen_no_arbiter.s_ready_i[0]_i_6
(.I0(st_aa_awtarget_hot),
.I1(st_aa_awtarget_enc),
.I2(\gen_no_arbiter.s_ready_i[0]_i_20_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_21_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_22_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_23_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair140" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_8__0
(.I0(active_target[32]),
.I1(st_aa_awtarget_hot),
.I2(active_target[33]),
.O(\gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair140" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_9__0
(.I0(active_target[48]),
.I1(st_aa_awtarget_hot),
.I2(active_target[49]),
.O(\gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(i__carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(i__carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(i__carry_i_4_n_0));
CARRY4 \p_0_out_inferred__9/i__carry
(.CI(1'b0),
.CO({p_0_out,\p_0_out_inferred__9/i__carry_n_1 ,\p_0_out_inferred__9/i__carry_n_2 ,\p_0_out_inferred__9/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED [3:0]),
.S({i__carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ,i__carry_i_3_n_0,i__carry_i_4_n_0}));
CARRY4 p_10_out_carry
(.CI(1'b0),
.CO({p_10_out,p_10_out_carry_n_1,p_10_out_carry_n_2,p_10_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_10_out_carry_O_UNCONNECTED[3:0]),
.S({p_10_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ,p_10_out_carry_i_3_n_0,p_10_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_10_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_10_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_10_out_carry_i_4_n_0));
CARRY4 p_12_out_carry
(.CI(1'b0),
.CO({p_12_out,p_12_out_carry_n_1,p_12_out_carry_n_2,p_12_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_12_out_carry_O_UNCONNECTED[3:0]),
.S({p_12_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ,p_12_out_carry_i_3_n_0,p_12_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_12_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_12_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_12_out_carry_i_4_n_0));
CARRY4 p_14_out_carry
(.CI(1'b0),
.CO({p_14_out,p_14_out_carry_n_1,p_14_out_carry_n_2,p_14_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_14_out_carry_O_UNCONNECTED[3:0]),
.S({p_14_out_carry_i_1_n_0,S,p_14_out_carry_i_3_n_0,p_14_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_14_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_14_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_14_out_carry_i_4_n_0));
CARRY4 p_2_out_carry
(.CI(1'b0),
.CO({p_2_out,p_2_out_carry_n_1,p_2_out_carry_n_2,p_2_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_2_out_carry_O_UNCONNECTED[3:0]),
.S({p_2_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ,p_2_out_carry_i_3_n_0,p_2_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_2_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_2_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_2_out_carry_i_4_n_0));
CARRY4 p_4_out_carry
(.CI(1'b0),
.CO({p_4_out,p_4_out_carry_n_1,p_4_out_carry_n_2,p_4_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_4_out_carry_O_UNCONNECTED[3:0]),
.S({p_4_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ,p_4_out_carry_i_3_n_0,p_4_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_4_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_4_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_4_out_carry_i_4_n_0));
CARRY4 p_6_out_carry
(.CI(1'b0),
.CO({p_6_out,p_6_out_carry_n_1,p_6_out_carry_n_2,p_6_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_6_out_carry_O_UNCONNECTED[3:0]),
.S({p_6_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ,p_6_out_carry_i_3_n_0,p_6_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_6_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_6_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_6_out_carry_i_4_n_0));
CARRY4 p_8_out_carry
(.CI(1'b0),
.CO({p_8_out,p_8_out_carry_n_1,p_8_out_carry_n_2,p_8_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_8_out_carry_O_UNCONNECTED[3:0]),
.S({p_8_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ,p_8_out_carry_i_3_n_0,p_8_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_8_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_8_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_8_out_carry_i_4_n_0));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_splitter" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter
(s_axi_awready,
m_ready_d,
\gen_multi_thread.accept_cnt_reg[3] ,
ss_wr_awvalid,
ss_aa_awready,
ss_wr_awready,
s_axi_awvalid,
aresetn_d,
aclk);
output [0:0]s_axi_awready;
output [1:0]m_ready_d;
output \gen_multi_thread.accept_cnt_reg[3] ;
output ss_wr_awvalid;
input ss_aa_awready;
input ss_wr_awready;
input [0:0]s_axi_awvalid;
input aresetn_d;
input aclk;
wire aclk;
wire aresetn_d;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire [1:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire ss_aa_awready;
wire ss_wr_awready;
wire ss_wr_awvalid;
LUT2 #(
.INIT(4'h2))
\FSM_onehot_state[3]_i_4
(.I0(s_axi_awvalid),
.I1(m_ready_d[1]),
.O(ss_wr_awvalid));
(* SOFT_HLUTNM = "soft_lutpair141" *)
LUT4 #(
.INIT(16'h111F))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2
(.I0(m_ready_d[1]),
.I1(ss_wr_awready),
.I2(m_ready_d[0]),
.I3(ss_aa_awready),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT6 #(
.INIT(64'h0302030000000000))
\m_ready_d[0]_i_1
(.I0(s_axi_awvalid),
.I1(m_ready_d[1]),
.I2(ss_wr_awready),
.I3(m_ready_d[0]),
.I4(ss_aa_awready),
.I5(aresetn_d),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000EC00000000))
\m_ready_d[1]_i_1
(.I0(s_axi_awvalid),
.I1(m_ready_d[1]),
.I2(ss_wr_awready),
.I3(m_ready_d[0]),
.I4(ss_aa_awready),
.I5(aresetn_d),
.O(\m_ready_d[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair141" *)
LUT4 #(
.INIT(16'hEEE0))
\s_axi_awready[0]_INST_0
(.I0(ss_aa_awready),
.I1(m_ready_d[0]),
.I2(ss_wr_awready),
.I3(m_ready_d[1]),
.O(s_axi_awready));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_splitter" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3
(m_ready_d,
aa_sa_awvalid,
aresetn_d,
\m_ready_d_reg[0]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[1] ,
aa_mi_awtarget_hot,
\m_ready_d_reg[0]_1 ,
aclk);
output [1:0]m_ready_d;
input aa_sa_awvalid;
input aresetn_d;
input \m_ready_d_reg[0]_0 ;
input \gen_no_arbiter.m_target_hot_i_reg[1] ;
input [2:0]aa_mi_awtarget_hot;
input \m_ready_d_reg[0]_1 ;
input aclk;
wire [2:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire \gen_no_arbiter.m_target_hot_i_reg[1] ;
wire [1:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[0]_1 ;
LUT6 #(
.INIT(64'h00000000EEEEEEEC))
\m_ready_d[0]_i_1
(.I0(aa_sa_awvalid),
.I1(m_ready_d[0]),
.I2(aa_mi_awtarget_hot[2]),
.I3(aa_mi_awtarget_hot[1]),
.I4(aa_mi_awtarget_hot[0]),
.I5(\m_ready_d_reg[0]_1 ),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000E0))
\m_ready_d[1]_i_1
(.I0(aa_sa_awvalid),
.I1(m_ready_d[1]),
.I2(aresetn_d),
.I3(\m_ready_d_reg[0]_0 ),
.I4(\gen_no_arbiter.m_target_hot_i_reg[1] ),
.O(\m_ready_d[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_wdata_router" *)
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router
(ss_wr_awready,
m_axi_wvalid,
\gen_axi.write_cs_reg[1] ,
s_axi_wready,
st_aa_awtarget_enc,
aclk,
D,
SR,
st_aa_awtarget_hot,
m_ready_d,
s_axi_awvalid,
s_axi_wvalid,
\gen_axi.write_cs_reg[1]_0 ,
s_axi_wlast,
m_axi_wready,
p_14_in,
ss_wr_awvalid);
output ss_wr_awready;
output [1:0]m_axi_wvalid;
output \gen_axi.write_cs_reg[1] ;
output [0:0]s_axi_wready;
input [0:0]st_aa_awtarget_enc;
input aclk;
input [0:0]D;
input [0:0]SR;
input [0:0]st_aa_awtarget_hot;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_wvalid;
input [0:0]\gen_axi.write_cs_reg[1]_0 ;
input [0:0]s_axi_wlast;
input [1:0]m_axi_wready;
input p_14_in;
input ss_wr_awvalid;
wire [0:0]D;
wire [0:0]SR;
wire aclk;
wire \gen_axi.write_cs_reg[1] ;
wire [0:0]\gen_axi.write_cs_reg[1]_0 ;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [0:0]m_ready_d;
wire p_14_in;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire ss_wr_awready;
wire ss_wr_awvalid;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo wrouter_aw_fifo
(.D(D),
.SR(SR),
.aclk(aclk),
.\gen_axi.write_cs_reg[1] (\gen_axi.write_cs_reg[1] ),
.\gen_axi.write_cs_reg[1]_0 (\gen_axi.write_cs_reg[1]_0 ),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d),
.p_14_in(p_14_in),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg_0(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot));
endmodule
(* ORIG_REF_NAME = "axi_data_fifo_v2_1_12_axic_reg_srl_fifo" *)
module zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
(s_ready_i_reg_0,
m_axi_wvalid,
\gen_axi.write_cs_reg[1] ,
s_axi_wready,
st_aa_awtarget_enc,
aclk,
D,
SR,
st_aa_awtarget_hot,
m_ready_d,
s_axi_awvalid,
s_axi_wvalid,
\gen_axi.write_cs_reg[1]_0 ,
s_axi_wlast,
m_axi_wready,
p_14_in,
ss_wr_awvalid);
output s_ready_i_reg_0;
output [1:0]m_axi_wvalid;
output \gen_axi.write_cs_reg[1] ;
output [0:0]s_axi_wready;
input [0:0]st_aa_awtarget_enc;
input aclk;
input [0:0]D;
input [0:0]SR;
input [0:0]st_aa_awtarget_hot;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_wvalid;
input [0:0]\gen_axi.write_cs_reg[1]_0 ;
input [0:0]s_axi_wlast;
input [1:0]m_axi_wready;
input p_14_in;
input ss_wr_awvalid;
wire \/FSM_onehot_state[0]_i_1_n_0 ;
wire \/FSM_onehot_state[1]_i_1_n_0 ;
wire \/FSM_onehot_state[2]_i_1_n_0 ;
wire \/FSM_onehot_state[3]_i_2_n_0 ;
wire [0:0]D;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[2] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[3] ;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire [2:0]fifoaddr;
wire \gen_axi.write_cs_reg[1] ;
wire [0:0]\gen_axi.write_cs_reg[1]_0 ;
wire \gen_rep[0].fifoaddr[0]_i_1_n_0 ;
wire \gen_rep[0].fifoaddr[1]_i_1_n_0 ;
wire \gen_rep[0].fifoaddr[2]_i_1_n_0 ;
wire \gen_srls[0].gen_rep[0].srl_nx1_n_0 ;
wire \gen_srls[0].gen_rep[1].srl_nx1_n_1 ;
wire \gen_srls[0].gen_rep[1].srl_nx1_n_2 ;
wire \gen_srls[0].gen_rep[1].srl_nx1_n_3 ;
wire load_s1;
wire m_avalid;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [0:0]m_ready_d;
wire m_valid_i;
wire m_valid_i_i_1_n_0;
wire p_0_in5_out;
(* RTL_KEEP = "yes" *) wire p_0_in8_in;
wire p_14_in;
(* RTL_KEEP = "yes" *) wire p_9_in;
wire push;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire s_ready_i_i_1__2_n_0;
wire s_ready_i_i_2_n_0;
wire s_ready_i_reg_0;
wire ss_wr_awvalid;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire \storage_data1[0]_i_1_n_0 ;
wire \storage_data1_reg_n_0_[0] ;
wire \storage_data1_reg_n_0_[1] ;
LUT5 #(
.INIT(32'h40440000))
\/FSM_onehot_state[0]_i_1
(.I0(p_9_in),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(m_ready_d),
.I3(s_axi_awvalid),
.I4(p_0_in8_in),
.O(\/FSM_onehot_state[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h20202F20))
\/FSM_onehot_state[1]_i_1
(.I0(s_axi_awvalid),
.I1(m_ready_d),
.I2(p_9_in),
.I3(p_0_in5_out),
.I4(p_0_in8_in),
.O(\/FSM_onehot_state[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB0B0B0BF))
\/FSM_onehot_state[2]_i_1
(.I0(m_ready_d),
.I1(s_axi_awvalid),
.I2(p_9_in),
.I3(p_0_in5_out),
.I4(p_0_in8_in),
.O(\/FSM_onehot_state[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00002A22))
\/FSM_onehot_state[3]_i_2
(.I0(p_0_in8_in),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(m_ready_d),
.I3(s_axi_awvalid),
.I4(p_9_in),
.O(\/FSM_onehot_state[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFF488F488F488))
\FSM_onehot_state[3]_i_1
(.I0(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I1(p_0_in8_in),
.I2(p_9_in),
.I3(ss_wr_awvalid),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(p_0_in5_out),
.O(m_valid_i));
LUT6 #(
.INIT(64'h0000000010000000))
\FSM_onehot_state[3]_i_5
(.I0(fifoaddr[1]),
.I1(fifoaddr[0]),
.I2(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I3(\FSM_onehot_state_reg_n_0_[3] ),
.I4(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I5(fifoaddr[2]),
.O(p_0_in5_out));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_state_reg[0]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[0]_i_1_n_0 ),
.Q(p_9_in),
.S(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[1]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[1]_i_1_n_0 ),
.Q(p_0_in8_in),
.R(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[2]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[2]_i_1_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[2] ),
.R(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[3]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[3]_i_2_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[3] ),
.R(areset_d1));
FDRE areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(SR),
.Q(areset_d1),
.R(1'b0));
LUT6 #(
.INIT(64'h0400000000000000))
\gen_axi.write_cs[1]_i_2
(.I0(\storage_data1_reg_n_0_[0] ),
.I1(\storage_data1_reg_n_0_[1] ),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(s_axi_wlast),
.I4(s_axi_wvalid),
.I5(m_avalid),
.O(\gen_axi.write_cs_reg[1] ));
LUT6 #(
.INIT(64'hC133DDFF3ECC2200))
\gen_rep[0].fifoaddr[0]_i_1
(.I0(p_0_in8_in),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(s_ready_i_reg_0),
.I3(ss_wr_awvalid),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(fifoaddr[0]),
.O(\gen_rep[0].fifoaddr[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hBFD5402A))
\gen_rep[0].fifoaddr[1]_i_1
(.I0(fifoaddr[0]),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(\FSM_onehot_state_reg_n_0_[3] ),
.I3(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I4(fifoaddr[1]),
.O(\gen_rep[0].fifoaddr[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEFFFF77710000888))
\gen_rep[0].fifoaddr[2]_i_1
(.I0(fifoaddr[0]),
.I1(fifoaddr[1]),
.I2(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I3(\FSM_onehot_state_reg_n_0_[3] ),
.I4(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I5(fifoaddr[2]),
.O(\gen_rep[0].fifoaddr[2]_i_1_n_0 ));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[0]_i_1_n_0 ),
.Q(fifoaddr[0]),
.S(SR));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[1]_i_1_n_0 ),
.Q(fifoaddr[1]),
.S(SR));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[2]_i_1_n_0 ),
.Q(fifoaddr[2]),
.S(SR));
zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0 \gen_srls[0].gen_rep[0].srl_nx1
(.aclk(aclk),
.fifoaddr(fifoaddr),
.push(push),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.\storage_data1_reg[0] (\gen_srls[0].gen_rep[0].srl_nx1_n_0 ));
zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4 \gen_srls[0].gen_rep[1].srl_nx1
(.D(D),
.aclk(aclk),
.fifoaddr(fifoaddr),
.\gen_rep[0].fifoaddr_reg[0] (\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.load_s1(load_s1),
.m_avalid(m_avalid),
.m_axi_wready(m_axi_wready),
.m_ready_d(m_ready_d),
.out0({p_0_in8_in,\FSM_onehot_state_reg_n_0_[3] }),
.p_14_in(p_14_in),
.push(push),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.s_ready_i_reg_0(s_ready_i_reg_0),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.\storage_data1_reg[0] (\storage_data1_reg_n_0_[0] ),
.\storage_data1_reg[1] (\gen_srls[0].gen_rep[1].srl_nx1_n_1 ),
.\storage_data1_reg[1]_0 (\storage_data1_reg_n_0_[1] ));
(* SOFT_HLUTNM = "soft_lutpair142" *)
LUT4 #(
.INIT(16'h1000))
\m_axi_wvalid[0]_INST_0
(.I0(\storage_data1_reg_n_0_[0] ),
.I1(\storage_data1_reg_n_0_[1] ),
.I2(m_avalid),
.I3(s_axi_wvalid),
.O(m_axi_wvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair142" *)
LUT4 #(
.INIT(16'h2000))
\m_axi_wvalid[1]_INST_0
(.I0(\storage_data1_reg_n_0_[0] ),
.I1(\storage_data1_reg_n_0_[1] ),
.I2(m_avalid),
.I3(s_axi_wvalid),
.O(m_axi_wvalid[1]));
LUT6 #(
.INIT(64'hFFFFF400F400F400))
m_valid_i_i_1
(.I0(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I1(p_0_in8_in),
.I2(p_9_in),
.I3(ss_wr_awvalid),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(p_0_in5_out),
.O(m_valid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(m_valid_i),
.D(m_valid_i_i_1_n_0),
.Q(m_avalid),
.R(areset_d1));
LUT6 #(
.INIT(64'h0A8A008A0A800080))
\s_axi_wready[0]_INST_0
(.I0(m_avalid),
.I1(m_axi_wready[1]),
.I2(\storage_data1_reg_n_0_[0] ),
.I3(\storage_data1_reg_n_0_[1] ),
.I4(p_14_in),
.I5(m_axi_wready[0]),
.O(s_axi_wready));
LUT6 #(
.INIT(64'hFEFFFFFFAAAAAAAA))
s_ready_i_i_1__2
(.I0(s_ready_i_i_2_n_0),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I2(fifoaddr[0]),
.I3(fifoaddr[1]),
.I4(fifoaddr[2]),
.I5(s_ready_i_reg_0),
.O(s_ready_i_i_1__2_n_0));
LUT3 #(
.INIT(8'hEA))
s_ready_i_i_2
(.I0(areset_d1),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(\FSM_onehot_state_reg_n_0_[3] ),
.O(s_ready_i_i_2_n_0));
FDRE s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(s_ready_i_reg_0),
.R(SR));
LUT5 #(
.INIT(32'hB8FFB800))
\storage_data1[0]_i_1
(.I0(\gen_srls[0].gen_rep[0].srl_nx1_n_0 ),
.I1(\FSM_onehot_state_reg_n_0_[3] ),
.I2(st_aa_awtarget_enc),
.I3(load_s1),
.I4(\storage_data1_reg_n_0_[0] ),
.O(\storage_data1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h88888888FFC88888))
\storage_data1[1]_i_2
(.I0(\FSM_onehot_state_reg_n_0_[3] ),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(p_0_in8_in),
.I3(p_9_in),
.I4(s_axi_awvalid),
.I5(m_ready_d),
.O(load_s1));
FDRE \storage_data1_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\storage_data1[0]_i_1_n_0 ),
.Q(\storage_data1_reg_n_0_[0] ),
.R(1'b0));
FDRE \storage_data1_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_srls[0].gen_rep[1].srl_nx1_n_1 ),
.Q(\storage_data1_reg_n_0_[1] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_data_fifo_v2_1_12_ndeep_srl" *)
module zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0
(\storage_data1_reg[0] ,
push,
st_aa_awtarget_enc,
fifoaddr,
aclk);
output \storage_data1_reg[0] ;
input push;
input [0:0]st_aa_awtarget_enc;
input [2:0]fifoaddr;
input aclk;
wire aclk;
wire [2:0]fifoaddr;
wire push;
wire [0:0]st_aa_awtarget_enc;
wire \storage_data1_reg[0] ;
wire \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls " *)
(* srl_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\gen_primitive_shifter.gen_srls[0].srl_inst
(.A({1'b0,1'b0,fifoaddr}),
.CE(push),
.CLK(aclk),
.D(st_aa_awtarget_enc),
.Q(\storage_data1_reg[0] ),
.Q31(\NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ));
endmodule
(* ORIG_REF_NAME = "axi_data_fifo_v2_1_12_ndeep_srl" *)
module zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4
(push,
\storage_data1_reg[1] ,
s_ready_i_reg,
\gen_rep[0].fifoaddr_reg[0] ,
D,
fifoaddr,
aclk,
st_aa_awtarget_enc,
st_aa_awtarget_hot,
out0,
load_s1,
\storage_data1_reg[1]_0 ,
s_ready_i_reg_0,
m_ready_d,
s_axi_awvalid,
s_axi_wlast,
s_axi_wvalid,
m_avalid,
m_axi_wready,
p_14_in,
\storage_data1_reg[0] );
output push;
output \storage_data1_reg[1] ;
output s_ready_i_reg;
output \gen_rep[0].fifoaddr_reg[0] ;
input [0:0]D;
input [2:0]fifoaddr;
input aclk;
input [0:0]st_aa_awtarget_enc;
input [0:0]st_aa_awtarget_hot;
input [1:0]out0;
input load_s1;
input \storage_data1_reg[1]_0 ;
input s_ready_i_reg_0;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
input m_avalid;
input [1:0]m_axi_wready;
input p_14_in;
input \storage_data1_reg[0] ;
wire [0:0]D;
wire \FSM_onehot_state[3]_i_6_n_0 ;
wire aclk;
wire [2:0]fifoaddr;
wire \gen_rep[0].fifoaddr_reg[0] ;
wire load_s1;
wire m_avalid;
wire [1:0]m_axi_wready;
wire [0:0]m_ready_d;
wire [1:0]out0;
wire p_14_in;
wire p_2_out;
wire push;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wvalid;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire \storage_data1_reg[0] ;
wire \storage_data1_reg[1] ;
wire \storage_data1_reg[1]_0 ;
wire \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ;
LUT4 #(
.INIT(16'h4000))
\FSM_onehot_state[3]_i_3
(.I0(\FSM_onehot_state[3]_i_6_n_0 ),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.I3(m_avalid),
.O(\gen_rep[0].fifoaddr_reg[0] ));
LUT5 #(
.INIT(32'hF035FF35))
\FSM_onehot_state[3]_i_6
(.I0(m_axi_wready[0]),
.I1(p_14_in),
.I2(\storage_data1_reg[1]_0 ),
.I3(\storage_data1_reg[0] ),
.I4(m_axi_wready[1]),
.O(\FSM_onehot_state[3]_i_6_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls " *)
(* srl_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\gen_primitive_shifter.gen_srls[0].srl_inst
(.A({1'b0,1'b0,fifoaddr}),
.CE(push),
.CLK(aclk),
.D(D),
.Q(p_2_out),
.Q31(\NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ));
LUT1 #(
.INIT(2'h1))
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1
(.I0(s_ready_i_reg),
.O(push));
LUT6 #(
.INIT(64'hFF0DFFFFFFDDFFFF))
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2
(.I0(out0[1]),
.I1(\gen_rep[0].fifoaddr_reg[0] ),
.I2(s_ready_i_reg_0),
.I3(m_ready_d),
.I4(s_axi_awvalid),
.I5(out0[0]),
.O(s_ready_i_reg));
LUT6 #(
.INIT(64'hF011FFFFF0110000))
\storage_data1[1]_i_1
(.I0(st_aa_awtarget_enc),
.I1(st_aa_awtarget_hot),
.I2(p_2_out),
.I3(out0[0]),
.I4(load_s1),
.I5(\storage_data1_reg[1]_0 ),
.O(\storage_data1_reg[1] ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axi_register_slice" *)
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice
(p_80_out,
m_axi_bready,
p_74_out,
\m_axi_rready[0] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
chosen,
s_axi_bready,
\aresetn_d_reg[1]_0 ,
m_axi_rvalid,
chosen_0,
s_axi_rready,
Q,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
D,
E);
output p_80_out;
output [0:0]m_axi_bready;
output p_74_out;
output \m_axi_rready[0] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[0].r_issuing_cnt_reg[0] ;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]chosen;
input [0:0]s_axi_bready;
input \aresetn_d_reg[1]_0 ;
input [0:0]m_axi_rvalid;
input [0:0]chosen_0;
input [0:0]s_axi_rready;
input [3:0]Q;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [13:0]D;
input [0:0]E;
wire [13:0]D;
wire [0:0]E;
wire [3:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire [0:0]chosen;
wire [0:0]chosen_0;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[0] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire p_1_in;
wire p_74_out;
wire p_80_out;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_rready;
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8 b_pipe
(.D(D),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1]_0 ),
.chosen(chosen),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.\m_payload_i_reg[0]_0 (p_80_out),
.p_1_in(p_1_in),
.s_axi_bready(s_axi_bready));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9 r_pipe
(.E(E),
.Q(Q),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.chosen_0(chosen_0),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.\m_axi_rready[0] (\m_axi_rready[0] ),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg_0(p_74_out),
.p_1_in(p_1_in),
.s_axi_rready(s_axi_rready));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axi_register_slice" *)
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1
(p_60_out,
m_axi_bready,
p_1_in,
p_54_out,
\m_axi_rready[1] ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ,
s_axi_bresp,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
s_axi_rresp,
s_axi_rdata,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
\aresetn_d_reg[1] ,
\aresetn_d_reg[1]_0 ,
aclk,
aresetn,
m_axi_bvalid,
s_axi_bready,
chosen,
\aresetn_d_reg[1]_1 ,
Q,
\m_payload_i_reg[12] ,
p_38_out,
\m_payload_i_reg[1] ,
s_axi_rready,
chosen_0,
m_axi_rvalid,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ,
\m_payload_i_reg[32] ,
p_32_out,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
D);
output p_60_out;
output [0:0]m_axi_bready;
output p_1_in;
output p_54_out;
output \m_axi_rready[1] ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output \gen_multi_thread.accept_cnt_reg[3] ;
output [4:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
output [1:0]s_axi_bresp;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[1].r_issuing_cnt_reg[8] ;
output [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [0:0]s_axi_rresp;
output [19:0]s_axi_rdata;
output \gen_master_slots[1].r_issuing_cnt_reg[11] ;
output \aresetn_d_reg[1] ;
input \aresetn_d_reg[1]_0 ;
input aclk;
input aresetn;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [1:0]chosen;
input \aresetn_d_reg[1]_1 ;
input [3:0]Q;
input [9:0]\m_payload_i_reg[12] ;
input p_38_out;
input [1:0]\m_payload_i_reg[1] ;
input [0:0]s_axi_rready;
input [1:0]chosen_0;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
input [20:0]\m_payload_i_reg[32] ;
input p_32_out;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [13:0]D;
wire [13:0]D;
wire [3:0]Q;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire \aresetn_d_reg[1]_1 ;
wire [1:0]chosen;
wire [1:0]chosen_0;
wire \gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
wire [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[1] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire [9:0]\m_payload_i_reg[12] ;
wire [1:0]\m_payload_i_reg[1] ;
wire [20:0]\m_payload_i_reg[32] ;
wire p_1_in;
wire p_32_out;
wire p_38_out;
wire p_54_out;
wire p_60_out;
wire [4:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [19:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6 b_pipe
(.D(D),
.Q(Q),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1]_0 ),
.\aresetn_d_reg[1]_1 (\aresetn_d_reg[1]_1 ),
.chosen(chosen),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.accept_cnt_reg[3] ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_no_arbiter.m_target_hot_i_reg[2] ),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.\m_payload_i_reg[0]_0 (p_60_out),
.\m_payload_i_reg[12]_0 (\m_payload_i_reg[12] ),
.\m_payload_i_reg[1]_0 (\m_payload_i_reg[1] ),
.p_1_in(p_1_in),
.p_38_out(p_38_out),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7 r_pipe
(.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1]_0 ),
.chosen_0(chosen_0),
.\gen_master_slots[1].r_issuing_cnt_reg[11] (\gen_master_slots[1].r_issuing_cnt_reg[11] ),
.\gen_master_slots[1].r_issuing_cnt_reg[11]_0 (\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.\m_axi_rready[1] (\m_axi_rready[1] ),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.\m_payload_i_reg[32]_0 (\m_payload_i_reg[32] ),
.p_1_in(p_1_in),
.p_32_out(p_32_out),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_ready_i_reg_0(p_54_out));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axi_register_slice" *)
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2
(p_38_out,
m_valid_i_reg,
mi_bready_2,
p_32_out,
mi_rready_2,
s_ready_i_reg,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
Q,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
S,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
aclk,
p_1_in,
\aresetn_d_reg[0] ,
p_21_in,
chosen,
s_axi_bready,
\m_payload_i_reg[13] ,
m_valid_i_reg_0,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ,
w_issuing_cnt,
r_issuing_cnt,
st_aa_artarget_hot,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
p_15_in,
s_axi_rready,
chosen_0,
\gen_axi.s_axi_rid_i_reg[11] ,
p_17_in,
\gen_axi.s_axi_arready_i_reg ,
D,
E);
output p_38_out;
output m_valid_i_reg;
output mi_bready_2;
output p_32_out;
output mi_rready_2;
output s_ready_i_reg;
output [6:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [4:0]Q;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output [0:0]S;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
output \gen_master_slots[2].r_issuing_cnt_reg[16] ;
input aclk;
input p_1_in;
input \aresetn_d_reg[0] ;
input p_21_in;
input [0:0]chosen;
input [0:0]s_axi_bready;
input [13:0]\m_payload_i_reg[13] ;
input m_valid_i_reg_0;
input [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
input [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
input [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
input [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
input [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
input [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
input [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
input [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
input [0:0]w_issuing_cnt;
input [0:0]r_issuing_cnt;
input [1:0]st_aa_artarget_hot;
input \gen_master_slots[0].r_issuing_cnt_reg[0] ;
input \gen_master_slots[1].r_issuing_cnt_reg[8] ;
input p_15_in;
input [0:0]s_axi_rready;
input [0:0]chosen_0;
input [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
input p_17_in;
input \gen_axi.s_axi_arready_i_reg ;
input [11:0]D;
input [0:0]E;
wire [11:0]D;
wire [0:0]E;
wire [4:0]Q;
wire [0:0]S;
wire aclk;
wire \aresetn_d_reg[0] ;
wire [0:0]chosen;
wire [0:0]chosen_0;
wire \gen_axi.s_axi_arready_i_reg ;
wire [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].r_issuing_cnt_reg[16] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [13:0]\m_payload_i_reg[13] ;
wire m_valid_i_reg;
wire m_valid_i_reg_0;
wire mi_bready_2;
wire mi_rready_2;
wire p_15_in;
wire p_17_in;
wire p_1_in;
wire p_21_in;
wire p_32_out;
wire p_38_out;
wire [0:0]r_issuing_cnt;
wire [6:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_rready;
wire s_ready_i_reg;
wire [1:0]st_aa_artarget_hot;
wire [0:0]w_issuing_cnt;
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1 b_pipe
(.D(D),
.Q(Q),
.S(S),
.aclk(aclk),
.\aresetn_d_reg[0] (\aresetn_d_reg[0] ),
.chosen(chosen),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] (\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] (\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] (\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] (\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] (\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] (\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] (\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] (\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] (\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_no_arbiter.m_target_hot_i_reg[2] ),
.\m_payload_i_reg[13]_0 (\m_payload_i_reg[13] ),
.\m_payload_i_reg[2]_0 (p_38_out),
.m_valid_i_reg_0(m_valid_i_reg),
.m_valid_i_reg_1(m_valid_i_reg_0),
.mi_bready_2(mi_bready_2),
.p_1_in(p_1_in),
.p_21_in(p_21_in),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_ready_i_reg_0(s_ready_i_reg),
.w_issuing_cnt(w_issuing_cnt));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2 r_pipe
(.E(E),
.aclk(aclk),
.\aresetn_d_reg[1] (m_valid_i_reg),
.chosen_0(chosen_0),
.\gen_axi.s_axi_arready_i_reg (\gen_axi.s_axi_arready_i_reg ),
.\gen_axi.s_axi_rid_i_reg[11] (\gen_axi.s_axi_rid_i_reg[11] ),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.\gen_master_slots[2].r_issuing_cnt_reg[16] (\gen_master_slots[2].r_issuing_cnt_reg[16] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_valid_i_reg_0(p_32_out),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.p_1_in(p_1_in),
.r_issuing_cnt(r_issuing_cnt),
.s_axi_rready(s_axi_rready),
.\skid_buffer_reg[34]_0 (mi_rready_2),
.st_aa_artarget_hot(st_aa_artarget_hot));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1
(\m_payload_i_reg[2]_0 ,
m_valid_i_reg_0,
mi_bready_2,
s_ready_i_reg_0,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
S,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
Q,
aclk,
p_1_in,
\aresetn_d_reg[0] ,
p_21_in,
chosen,
s_axi_bready,
\m_payload_i_reg[13]_0 ,
m_valid_i_reg_1,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ,
w_issuing_cnt,
D);
output \m_payload_i_reg[2]_0 ;
output m_valid_i_reg_0;
output mi_bready_2;
output s_ready_i_reg_0;
output [6:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output [0:0]S;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [4:0]Q;
input aclk;
input p_1_in;
input \aresetn_d_reg[0] ;
input p_21_in;
input [0:0]chosen;
input [0:0]s_axi_bready;
input [13:0]\m_payload_i_reg[13]_0 ;
input m_valid_i_reg_1;
input [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
input [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
input [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
input [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
input [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
input [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
input [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
input [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
input [0:0]w_issuing_cnt;
input [11:0]D;
wire [11:0]D;
wire [4:0]Q;
wire [0:0]S;
wire aclk;
wire \aresetn_d_reg[0] ;
wire [0:0]chosen;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ;
wire [13:0]\m_payload_i_reg[13]_0 ;
wire \m_payload_i_reg[2]_0 ;
wire m_valid_i_i_1__1_n_0;
wire m_valid_i_reg_0;
wire m_valid_i_reg_1;
wire mi_bready_2;
wire p_1_in;
wire p_21_in;
wire [6:0]s_axi_bid;
wire \s_axi_bid[6]_INST_0_i_1_n_0 ;
wire \s_axi_bid[7]_INST_0_i_1_n_0 ;
wire \s_axi_bid[8]_INST_0_i_1_n_0 ;
wire [0:0]s_axi_bready;
wire s_ready_i_i_1__5_n_0;
wire s_ready_i_reg_0;
wire [35:24]st_mr_bid;
wire [0:0]w_issuing_cnt;
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0] ),
.Q(s_ready_i_reg_0),
.R(1'b0));
LUT4 #(
.INIT(16'h2AAA))
\gen_no_arbiter.s_ready_i[0]_i_27
(.I0(w_issuing_cnt),
.I1(s_axi_bready),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] [1]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ));
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1__0
(.I0(\m_payload_i_reg[2]_0 ),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[8]),
.Q(st_mr_bid[32]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[9]),
.Q(st_mr_bid[33]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[10]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[11]),
.Q(st_mr_bid[35]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[0]),
.Q(st_mr_bid[24]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[1]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[2]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[3]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[4]),
.Q(st_mr_bid[28]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[5]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[6]),
.Q(st_mr_bid[30]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[7]),
.Q(st_mr_bid[31]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_1__1
(.I0(p_21_in),
.I1(mi_bready_2),
.I2(s_axi_bready),
.I3(\m_payload_i_reg[2]_0 ),
.I4(chosen),
.O(m_valid_i_i_1__1_n_0));
LUT1 #(
.INIT(2'h1))
m_valid_i_i_1__5
(.I0(s_ready_i_reg_0),
.O(m_valid_i_reg_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__1_n_0),
.Q(\m_payload_i_reg[2]_0 ),
.R(m_valid_i_reg_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] [1]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] [1]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] [1]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(S));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] [1]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] [1]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] [1]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] [1]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[0]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.O(s_axi_bid[0]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[0]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [0]),
.I1(st_mr_bid[24]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [7]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[11]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.O(s_axi_bid[6]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[11]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [6]),
.I1(st_mr_bid[35]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [13]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[4]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.O(s_axi_bid[1]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[4]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [1]),
.I1(st_mr_bid[28]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [8]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[6]_INST_0
(.I0(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.O(s_axi_bid[2]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[6]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [2]),
.I1(st_mr_bid[30]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [9]),
.O(\s_axi_bid[6]_INST_0_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[7]_INST_0
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.O(s_axi_bid[3]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[7]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [3]),
.I1(st_mr_bid[31]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [10]),
.O(\s_axi_bid[7]_INST_0_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[8]_INST_0
(.I0(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(s_axi_bid[4]));
LUT6 #(
.INIT(64'hF5303030F53F3F3F))
\s_axi_bid[8]_INST_0_i_1
(.I0(st_mr_bid[32]),
.I1(\m_payload_i_reg[13]_0 [11]),
.I2(m_valid_i_reg_1),
.I3(\m_payload_i_reg[2]_0 ),
.I4(chosen),
.I5(\m_payload_i_reg[13]_0 [4]),
.O(\s_axi_bid[8]_INST_0_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[9]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.O(s_axi_bid[5]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[9]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [5]),
.I1(st_mr_bid[33]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [12]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ));
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_1__5
(.I0(\m_payload_i_reg[2]_0 ),
.I1(p_21_in),
.I2(chosen),
.I3(s_axi_bready),
.I4(s_ready_i_reg_0),
.O(s_ready_i_i_1__5_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__5_n_0),
.Q(mi_bready_2),
.R(p_1_in));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
p_1_in,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ,
s_axi_bresp,
\aresetn_d_reg[1] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ,
\aresetn_d_reg[1]_0 ,
aclk,
aresetn,
m_axi_bvalid,
s_axi_bready,
chosen,
\aresetn_d_reg[1]_1 ,
Q,
\m_payload_i_reg[12]_0 ,
p_38_out,
\m_payload_i_reg[1]_0 ,
D);
output \m_payload_i_reg[0]_0 ;
output [0:0]m_axi_bready;
output p_1_in;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output \gen_multi_thread.accept_cnt_reg[3] ;
output [4:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
output [1:0]s_axi_bresp;
output \aresetn_d_reg[1] ;
output [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
input \aresetn_d_reg[1]_0 ;
input aclk;
input aresetn;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [1:0]chosen;
input \aresetn_d_reg[1]_1 ;
input [3:0]Q;
input [9:0]\m_payload_i_reg[12]_0 ;
input p_38_out;
input [1:0]\m_payload_i_reg[1]_0 ;
input [13:0]D;
wire [13:0]D;
wire [3:0]Q;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire \aresetn_d_reg[1]_1 ;
wire [1:0]chosen;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
wire [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire \m_payload_i_reg[0]_0 ;
wire [9:0]\m_payload_i_reg[12]_0 ;
wire [1:0]\m_payload_i_reg[1]_0 ;
wire m_valid_i_i_1__0_n_0;
wire [1:1]p_0_in;
wire p_1_in;
wire p_38_out;
wire [4:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_ready_i_i_2__0_n_0;
wire [22:13]st_mr_bid;
wire [4:3]st_mr_bmesg;
LUT2 #(
.INIT(4'h8))
\aresetn_d[1]_i_1
(.I0(p_0_in),
.I1(aresetn),
.O(\aresetn_d_reg[1] ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(p_0_in),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000700000000))
\gen_no_arbiter.s_ready_i[0]_i_26
(.I0(\gen_multi_thread.accept_cnt_reg[3] ),
.I1(s_axi_bready),
.I2(Q[2]),
.I3(Q[1]),
.I4(Q[0]),
.I5(Q[3]),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1
(.I0(\m_payload_i_reg[0]_0 ),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[0]),
.Q(st_mr_bmesg[3]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [4]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [5]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[12]),
.Q(st_mr_bid[22]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[13]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [6]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[1]),
.Q(st_mr_bmesg[4]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [0]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[3]),
.Q(st_mr_bid[13]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[4]),
.Q(st_mr_bid[14]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[5]),
.Q(st_mr_bid[15]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[6]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [1]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[7]),
.Q(st_mr_bid[17]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[8]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [2]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_1__0
(.I0(m_axi_bvalid),
.I1(m_axi_bready),
.I2(s_axi_bready),
.I3(chosen[0]),
.I4(\m_payload_i_reg[0]_0 ),
.O(m_valid_i_i_1__0_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__0_n_0),
.Q(\m_payload_i_reg[0]_0 ),
.R(\aresetn_d_reg[1]_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[10]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ),
.O(s_axi_bid[4]));
LUT6 #(
.INIT(64'hF0353535FF353535))
\s_axi_bid[10]_INST_0_i_1
(.I0(\m_payload_i_reg[12]_0 [4]),
.I1(st_mr_bid[22]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [9]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT2 #(
.INIT(4'h8))
\s_axi_bid[11]_INST_0_i_2
(.I0(\m_payload_i_reg[0]_0 ),
.I1(chosen[0]),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[1]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.O(s_axi_bid[0]));
LUT6 #(
.INIT(64'hF0353535FF353535))
\s_axi_bid[1]_INST_0_i_1
(.I0(\m_payload_i_reg[12]_0 [0]),
.I1(st_mr_bid[13]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [5]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[2]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.O(s_axi_bid[1]));
LUT6 #(
.INIT(64'hF0535353FF535353))
\s_axi_bid[2]_INST_0_i_1
(.I0(st_mr_bid[14]),
.I1(\m_payload_i_reg[12]_0 [1]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [6]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[3]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.O(s_axi_bid[2]));
LUT6 #(
.INIT(64'hF0535353FF535353))
\s_axi_bid[3]_INST_0_i_1
(.I0(st_mr_bid[15]),
.I1(\m_payload_i_reg[12]_0 [2]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [7]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[5]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.O(s_axi_bid[3]));
LUT6 #(
.INIT(64'hF0353535FF353535))
\s_axi_bid[5]_INST_0_i_1
(.I0(\m_payload_i_reg[12]_0 [3]),
.I1(st_mr_bid[17]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [8]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ));
LUT6 #(
.INIT(64'h3FBFBFBF3F808080))
\s_axi_bresp[0]_INST_0
(.I0(st_mr_bmesg[3]),
.I1(chosen[0]),
.I2(\m_payload_i_reg[0]_0 ),
.I3(chosen[1]),
.I4(p_38_out),
.I5(\m_payload_i_reg[1]_0 [0]),
.O(s_axi_bresp[0]));
LUT6 #(
.INIT(64'h0CCCFAAAFAAAFAAA))
\s_axi_bresp[1]_INST_0
(.I0(\m_payload_i_reg[1]_0 [1]),
.I1(st_mr_bmesg[4]),
.I2(chosen[1]),
.I3(p_38_out),
.I4(\m_payload_i_reg[0]_0 ),
.I5(chosen[0]),
.O(s_axi_bresp[1]));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__3
(.I0(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_2__0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(m_axi_bvalid),
.I2(s_axi_bready),
.I3(chosen[0]),
.I4(\aresetn_d_reg[1]_1 ),
.O(s_ready_i_i_2__0_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_2__0_n_0),
.Q(m_axi_bready),
.R(p_1_in));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
chosen,
s_axi_bready,
\aresetn_d_reg[1]_0 ,
D);
output \m_payload_i_reg[0]_0 ;
output [0:0]m_axi_bready;
output [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]chosen;
input [0:0]s_axi_bready;
input \aresetn_d_reg[1]_0 ;
input [13:0]D;
wire [13:0]D;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire [0:0]chosen;
wire [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i_reg[0]_0 ;
wire m_valid_i_i_2_n_0;
wire p_1_in;
wire [0:0]s_axi_bready;
wire s_ready_i_i_1__4_n_0;
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1__1
(.I0(\m_payload_i_reg[0]_0 ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[0]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[12]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[13]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[1]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[3]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[4]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[5]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[6]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[7]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[8]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_2
(.I0(m_axi_bvalid),
.I1(m_axi_bready),
.I2(chosen),
.I3(\m_payload_i_reg[0]_0 ),
.I4(s_axi_bready),
.O(m_valid_i_i_2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_2_n_0),
.Q(\m_payload_i_reg[0]_0 ),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_1__4
(.I0(\m_payload_i_reg[0]_0 ),
.I1(m_axi_bvalid),
.I2(chosen),
.I3(s_axi_bready),
.I4(\aresetn_d_reg[1]_0 ),
.O(s_ready_i_i_1__4_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__4_n_0),
.Q(m_axi_bready),
.R(p_1_in));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2
(m_valid_i_reg_0,
\skid_buffer_reg[34]_0 ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
r_issuing_cnt,
st_aa_artarget_hot,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
p_15_in,
s_axi_rready,
chosen_0,
\gen_axi.s_axi_rid_i_reg[11] ,
p_17_in,
\gen_axi.s_axi_arready_i_reg ,
E);
output m_valid_i_reg_0;
output \skid_buffer_reg[34]_0 ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_master_slots[2].r_issuing_cnt_reg[16] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]r_issuing_cnt;
input [1:0]st_aa_artarget_hot;
input \gen_master_slots[0].r_issuing_cnt_reg[0] ;
input \gen_master_slots[1].r_issuing_cnt_reg[8] ;
input p_15_in;
input [0:0]s_axi_rready;
input [0:0]chosen_0;
input [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
input p_17_in;
input \gen_axi.s_axi_arready_i_reg ;
input [0:0]E;
wire [0:0]E;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [0:0]chosen_0;
wire \gen_axi.s_axi_arready_i_reg ;
wire [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].r_issuing_cnt_reg[16] ;
wire [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire p_15_in;
wire p_17_in;
wire p_1_in;
wire [0:0]r_issuing_cnt;
wire [0:0]s_axi_rready;
wire s_ready_i0;
wire [46:34]skid_buffer;
wire \skid_buffer_reg[34]_0 ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire [1:0]st_aa_artarget_hot;
LUT6 #(
.INIT(64'h955555552AAAAAAA))
\gen_master_slots[2].r_issuing_cnt[16]_i_1
(.I0(\gen_axi.s_axi_arready_i_reg ),
.I1(s_axi_rready),
.I2(chosen_0),
.I3(m_valid_i_reg_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.I5(r_issuing_cnt),
.O(\gen_master_slots[2].r_issuing_cnt_reg[16] ));
LUT6 #(
.INIT(64'hFF0FF2020000F202))
\gen_no_arbiter.s_ready_i[0]_i_23__0
(.I0(r_issuing_cnt),
.I1(\gen_no_arbiter.s_ready_i[0]_i_25__0_n_0 ),
.I2(st_aa_artarget_hot[0]),
.I3(\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.I4(st_aa_artarget_hot[1]),
.I5(\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT4 #(
.INIT(16'h8000))
\gen_no_arbiter.s_ready_i[0]_i_25__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.I1(m_valid_i_reg_0),
.I2(chosen_0),
.I3(s_axi_rready),
.O(\gen_no_arbiter.s_ready_i[0]_i_25__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(p_17_in),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [0]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [1]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [2]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [3]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [4]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [5]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [6]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [7]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [8]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [9]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [10]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [11]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(E),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(E),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(E),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(E),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(E),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
LUT5 #(
.INIT(32'hFF70FFFF))
m_valid_i_i_1__4
(.I0(s_axi_rready),
.I1(chosen_0),
.I2(m_valid_i_reg_0),
.I3(p_15_in),
.I4(\skid_buffer_reg[34]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__1
(.I0(p_15_in),
.I1(\skid_buffer_reg[34]_0 ),
.I2(s_axi_rready),
.I3(chosen_0),
.I4(m_valid_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[34]_0 ),
.R(p_1_in));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(p_17_in),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7
(s_ready_i_reg_0,
\m_axi_rready[1] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
s_axi_rresp,
s_axi_rdata,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
s_axi_rready,
chosen_0,
m_axi_rvalid,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ,
\m_payload_i_reg[32]_0 ,
p_32_out,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata);
output s_ready_i_reg_0;
output \m_axi_rready[1] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[1].r_issuing_cnt_reg[8] ;
output [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [0:0]s_axi_rresp;
output [19:0]s_axi_rdata;
output \gen_master_slots[1].r_issuing_cnt_reg[11] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]s_axi_rready;
input [1:0]chosen_0;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
input [20:0]\m_payload_i_reg[32]_0 ;
input p_32_out;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [1:0]chosen_0;
wire \gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[1] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire [20:0]\m_payload_i_reg[32]_0 ;
wire m_valid_i0;
wire p_1_in;
wire p_1_in_0;
wire p_32_out;
wire [19:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire [46:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire [68:35]st_mr_rmesg;
LUT4 #(
.INIT(16'h8000))
\gen_master_slots[1].r_issuing_cnt[11]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.I1(s_ready_i_reg_0),
.I2(chosen_0[0]),
.I3(s_axi_rready),
.O(\gen_master_slots[1].r_issuing_cnt_reg[8] ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'h8))
\gen_master_slots[1].r_issuing_cnt[11]_i_6
(.I0(s_ready_i_reg_0),
.I1(chosen_0[0]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] ));
LUT5 #(
.INIT(32'h00000100))
\gen_no_arbiter.s_ready_i[0]_i_27__0
(.I0(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [0]),
.I1(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [1]),
.I2(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [2]),
.I3(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [3]),
.I4(\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(m_axi_rdata[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(m_axi_rdata[10]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(m_axi_rdata[11]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(m_axi_rdata[12]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__3
(.I0(m_axi_rdata[13]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(m_axi_rdata[14]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(m_axi_rdata[15]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(m_axi_rdata[16]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(m_axi_rdata[17]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(m_axi_rdata[18]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(m_axi_rdata[19]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(m_axi_rdata[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(m_axi_rdata[20]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(m_axi_rdata[21]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(m_axi_rdata[22]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(m_axi_rdata[23]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(m_axi_rdata[24]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(m_axi_rdata[25]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(m_axi_rdata[26]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(m_axi_rdata[27]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(m_axi_rdata[28]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(m_axi_rdata[29]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(m_axi_rdata[2]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(m_axi_rdata[30]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__0
(.I0(m_axi_rdata[31]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(m_axi_rresp[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(m_axi_rresp[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(m_axi_rlast),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(m_axi_rid[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(m_axi_rid[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1__0
(.I0(m_axi_rid[2]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(m_axi_rid[3]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(m_axi_rid[4]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(m_axi_rdata[3]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1__0
(.I0(m_axi_rid[5]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1__0
(.I0(m_axi_rid[6]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1__0
(.I0(m_axi_rid[7]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1__0
(.I0(m_axi_rid[8]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(m_axi_rid[9]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(m_axi_rid[10]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
LUT3 #(
.INIT(8'hD5))
\m_payload_i[46]_i_1__0
(.I0(s_ready_i_reg_0),
.I1(s_axi_rready),
.I2(chosen_0[0]),
.O(p_1_in_0));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2__0
(.I0(m_axi_rid[11]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(m_axi_rdata[4]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(m_axi_rdata[5]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(m_axi_rdata[6]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(m_axi_rdata[7]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(m_axi_rdata[8]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(m_axi_rdata[9]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[12]),
.Q(st_mr_rmesg[50]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[13]),
.Q(st_mr_rmesg[51]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[14]),
.Q(st_mr_rmesg[52]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[15]),
.Q(st_mr_rmesg[53]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[16]),
.Q(st_mr_rmesg[54]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[17]),
.Q(st_mr_rmesg[55]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[18]),
.Q(st_mr_rmesg[56]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[19]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[1]),
.Q(st_mr_rmesg[39]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[20]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[21]),
.Q(st_mr_rmesg[59]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[22]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[23]),
.Q(st_mr_rmesg[61]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[24]),
.Q(st_mr_rmesg[62]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[25]),
.Q(st_mr_rmesg[63]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[26]),
.Q(st_mr_rmesg[64]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[27]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[28]),
.Q(st_mr_rmesg[66]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[29]),
.Q(st_mr_rmesg[67]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[2]),
.Q(st_mr_rmesg[40]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[30]),
.Q(st_mr_rmesg[68]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[31]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[32]),
.Q(st_mr_rmesg[35]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[33]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[3]),
.Q(st_mr_rmesg[41]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[5]),
.Q(st_mr_rmesg[43]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[7]),
.Q(st_mr_rmesg[45]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'hFF2AFFFF))
m_valid_i_i_1__3
(.I0(s_ready_i_reg_0),
.I1(s_axi_rready),
.I2(chosen_0[0]),
.I3(m_axi_rvalid),
.I4(\m_axi_rready[1] ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[12]_INST_0
(.I0(st_mr_rmesg[50]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [5]),
.O(s_axi_rdata[5]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[13]_INST_0
(.I0(st_mr_rmesg[51]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [6]),
.O(s_axi_rdata[6]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[14]_INST_0
(.I0(st_mr_rmesg[52]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [7]),
.O(s_axi_rdata[7]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[15]_INST_0
(.I0(st_mr_rmesg[53]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [8]),
.O(s_axi_rdata[8]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[16]_INST_0
(.I0(st_mr_rmesg[54]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [9]),
.O(s_axi_rdata[9]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[17]_INST_0
(.I0(st_mr_rmesg[55]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [10]),
.O(s_axi_rdata[10]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[18]_INST_0
(.I0(st_mr_rmesg[56]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [11]),
.O(s_axi_rdata[11]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[1]_INST_0
(.I0(st_mr_rmesg[39]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [0]),
.O(s_axi_rdata[0]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[21]_INST_0
(.I0(st_mr_rmesg[59]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [12]),
.O(s_axi_rdata[12]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[23]_INST_0
(.I0(st_mr_rmesg[61]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [13]),
.O(s_axi_rdata[13]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[24]_INST_0
(.I0(st_mr_rmesg[62]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [14]),
.O(s_axi_rdata[14]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[25]_INST_0
(.I0(st_mr_rmesg[63]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [15]),
.O(s_axi_rdata[15]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[26]_INST_0
(.I0(st_mr_rmesg[64]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [16]),
.O(s_axi_rdata[16]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[28]_INST_0
(.I0(st_mr_rmesg[66]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [17]),
.O(s_axi_rdata[17]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[29]_INST_0
(.I0(st_mr_rmesg[67]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [18]),
.O(s_axi_rdata[18]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[2]_INST_0
(.I0(st_mr_rmesg[40]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [1]),
.O(s_axi_rdata[1]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[30]_INST_0
(.I0(st_mr_rmesg[68]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [19]),
.O(s_axi_rdata[19]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[3]_INST_0
(.I0(st_mr_rmesg[41]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [2]),
.O(s_axi_rdata[2]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[5]_INST_0
(.I0(st_mr_rmesg[43]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [3]),
.O(s_axi_rdata[3]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[7]_INST_0
(.I0(st_mr_rmesg[45]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [4]),
.O(s_axi_rdata[4]));
LUT6 #(
.INIT(64'h0FFFACCCACCCACCC))
\s_axi_rresp[0]_INST_0
(.I0(st_mr_rmesg[35]),
.I1(\m_payload_i_reg[32]_0 [20]),
.I2(s_ready_i_reg_0),
.I3(chosen_0[0]),
.I4(p_32_out),
.I5(chosen_0[1]),
.O(s_axi_rresp));
LUT5 #(
.INIT(32'hFF4F4F4F))
s_ready_i_i_1__0
(.I0(m_axi_rvalid),
.I1(\m_axi_rready[1] ),
.I2(s_ready_i_reg_0),
.I3(s_axi_rready),
.I4(chosen_0[0]),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\m_axi_rready[1] ),
.R(p_1_in));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9
(m_valid_i_reg_0,
\m_axi_rready[0] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_rvalid,
chosen_0,
s_axi_rready,
Q,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
E);
output m_valid_i_reg_0;
output \m_axi_rready[0] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[0].r_issuing_cnt_reg[0] ;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_rvalid;
input [0:0]chosen_0;
input [0:0]s_axi_rready;
input [3:0]Q;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [0:0]E;
wire [0:0]E;
wire [3:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [0:0]chosen_0;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[0] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire p_1_in;
wire [0:0]s_axi_rready;
wire s_ready_i0;
wire [46:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
LUT4 #(
.INIT(16'h8000))
\gen_master_slots[0].r_issuing_cnt[3]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.I1(s_axi_rready),
.I2(m_valid_i_reg_0),
.I3(chosen_0),
.O(\gen_master_slots[0].r_issuing_cnt_reg[0] ));
LUT5 #(
.INIT(32'h00000100))
\gen_no_arbiter.s_ready_i[0]_i_26__0
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.I3(Q[3]),
.I4(\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(m_axi_rdata[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(m_axi_rdata[10]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(m_axi_rdata[11]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(m_axi_rdata[12]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(m_axi_rdata[13]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(m_axi_rdata[14]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(m_axi_rdata[15]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(m_axi_rdata[16]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(m_axi_rdata[17]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(m_axi_rdata[18]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(m_axi_rdata[19]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(m_axi_rdata[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(m_axi_rdata[20]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(m_axi_rdata[21]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(m_axi_rdata[22]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(m_axi_rdata[23]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(m_axi_rdata[24]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(m_axi_rdata[25]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(m_axi_rdata[26]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(m_axi_rdata[27]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(m_axi_rdata[28]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(m_axi_rdata[29]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(m_axi_rdata[2]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(m_axi_rdata[30]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1
(.I0(m_axi_rdata[31]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(m_axi_rresp[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(m_axi_rresp[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(m_axi_rlast),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(m_axi_rid[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(m_axi_rid[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(m_axi_rid[2]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(m_axi_rid[3]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(m_axi_rid[4]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(m_axi_rdata[3]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(m_axi_rid[5]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(m_axi_rid[6]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(m_axi_rid[7]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(m_axi_rid[8]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(m_axi_rid[9]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(m_axi_rid[10]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(m_axi_rid[11]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(m_axi_rdata[4]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(m_axi_rdata[5]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(m_axi_rdata[6]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(m_axi_rdata[7]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(m_axi_rdata[8]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(m_axi_rdata[9]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(E),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(E),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(E),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(E),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(E),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'hFF4CFFFF))
m_valid_i_i_1__2
(.I0(chosen_0),
.I1(m_valid_i_reg_0),
.I2(s_axi_rready),
.I3(m_axi_rvalid),
.I4(\m_axi_rready[0] ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hF4FF44FF))
s_ready_i_i_1
(.I0(m_axi_rvalid),
.I1(\m_axi_rready[0] ),
.I2(chosen_0),
.I3(m_valid_i_reg_0),
.I4(s_axi_rready),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\m_axi_rready[0] ),
.R(p_1_in));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014
// Date : Sun Nov 2 20:42:28 2014
// Host : ubuntu-imac running 64-bit Ubuntu 14.04.1 LTS
// Command : write_verilog -force -mode funcsim
// /home/john/parallella-hw/fpga/projects/vivado_parallella_7010_headless/parallela_7010_headless/parallela_7010_headless.srcs/sources_1/ip/processing_system7_0/processing_system7_0_funcsim.v
// Design : processing_system7_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2014.3" *) (* CHECK_LICENSE_TYPE = "processing_system7_0,processing_system7_v5_5_processing_system7,{}" *) (* CORE_GENERATION_INFO = "processing_system7_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2014.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=0,x_ipLanguage=VERILOG,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=48,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=32,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=true,C_PACKAGE_NAME=clg400}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* NotValidForBitStream *)
module processing_system7_0
(ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
FCLK_CLK0,
FCLK_CLK3,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX" *) output ENET0_PTP_DELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_TX" *) output ENET0_PTP_DELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_RX" *) output ENET0_PTP_PDELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_TX" *) output ENET0_PTP_PDELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_RX" *) output ENET0_PTP_PDELAY_RESP_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_TX" *) output ENET0_PTP_PDELAY_RESP_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_RX" *) output ENET0_PTP_SYNC_FRAME_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_TX" *) output ENET0_PTP_SYNC_FRAME_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_RX" *) output ENET0_SOF_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_TX" *) output ENET0_SOF_TX;
input [47:0]GPIO_I;
output [47:0]GPIO_O;
output [47:0]GPIO_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *) input I2C0_SDA_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *) output I2C0_SDA_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *) output I2C0_SDA_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *) input I2C0_SCL_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *) output I2C0_SCL_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *) output I2C0_SCL_T;
output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_1 VBUS_PWRSELECT" *) output USB1_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_1 VBUS_PWRFAULT" *) input USB1_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARVALID" *) output M_AXI_GP1_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWVALID" *) output M_AXI_GP1_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 BREADY" *) output M_AXI_GP1_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RREADY" *) output M_AXI_GP1_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WLAST" *) output M_AXI_GP1_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WVALID" *) output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP1_ACLK CLK" *) input M_AXI_GP1_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARREADY" *) input M_AXI_GP1_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWREADY" *) input M_AXI_GP1_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 BVALID" *) input M_AXI_GP1_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RLAST" *) input M_AXI_GP1_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RVALID" *) input M_AXI_GP1_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WREADY" *) input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARREADY" *) output S_AXI_HP1_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWREADY" *) output S_AXI_HP1_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 BVALID" *) output S_AXI_HP1_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 RLAST" *) output S_AXI_HP1_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 RVALID" *) output S_AXI_HP1_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 WREADY" *) output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP1_ACLK CLK" *) input S_AXI_HP1_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARVALID" *) input S_AXI_HP1_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWVALID" *) input S_AXI_HP1_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 BREADY" *) input S_AXI_HP1_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP1_FIFO_CTRL RDISSUECAPEN" *) input S_AXI_HP1_RDISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 RREADY" *) input S_AXI_HP1_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 WLAST" *) input S_AXI_HP1_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP1_FIFO_CTRL WRISSUECAPEN" *) input S_AXI_HP1_WRISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 WVALID" *) input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *) output FCLK_CLK3;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire FCLK_CLK0;
wire FCLK_CLK3;
wire FCLK_RESET0_N;
wire [47:0]GPIO_I;
wire [47:0]GPIO_O;
wire [47:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire [53:0]MIO;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]M_AXI_GP1_ARCACHE;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [2:0]M_AXI_GP1_ARSIZE;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]M_AXI_GP1_AWCACHE;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [2:0]M_AXI_GP1_AWSIZE;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP0_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP0_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP0_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=400, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=9, PCW_UIPARAM_DDR_CWL=9, PCW_UIPARAM_DDR_T_RCD=9, PCW_UIPARAM_DDR_T_RP=9, PCW_UIPARAM_DDR_T_RC=60, PCW_UIPARAM_DDR_T_RAS_MIN=40, PCW_UIPARAM_DDR_T_FAW=50, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.315, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.391, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.374, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.271, PCW_UIPARAM_DDR_BOARD_DELAY0=0.434, PCW_UIPARAM_DDR_BOARD_DELAY1=0.398, PCW_UIPARAM_DDR_BOARD_DELAY2=0.41, PCW_UIPARAM_DDR_BOARD_DELAY3=0.455, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA3_PERIPHERAL_FREQMHZ=40.000000, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=48, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1600.000, PCW_USE_M_AXI_GP0=0, PCW_USE_M_AXI_GP1=1, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=1, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=32, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=Custom, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=1, PCW_SD1_SD1_IO=MIO 10 .. 15, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 8 .. 9, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=1, PCW_USB1_USB1_IO=MIO 40 .. 51, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=1, PCW_GPIO_EMIO_GPIO_IO=48, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=1, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *)
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "48" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "true" *)
(* C_FCLK_CLK1_BUF = "false" *)
(* C_FCLK_CLK2_BUF = "false" *)
(* C_FCLK_CLK3_BUF = "true" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "32" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1600.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP1} dataWidth={64} clockFreq={10} usageRate={0.5} /><AXI interface={M_AXI_GP1} dataWidth={32} clockFreq={10} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX" *)
processing_system7_0_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX),
.ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX),
.ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX),
.ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX),
.ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX),
.ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX),
.ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX),
.ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX),
.ENET0_SOF_RX(ENET0_SOF_RX),
.ENET0_SOF_TX(ENET0_SOF_TX),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(FCLK_CLK3),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I(GPIO_I),
.GPIO_O(GPIO_O),
.GPIO_T(GPIO_T),
.I2C0_SCL_I(I2C0_SCL_I),
.I2C0_SCL_O(I2C0_SCL_O),
.I2C0_SCL_T(I2C0_SCL_T),
.I2C0_SDA_I(I2C0_SDA_I),
.I2C0_SDA_O(I2C0_SDA_O),
.I2C0_SDA_T(I2C0_SDA_T),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(1'b0),
.M_AXI_GP0_ARADDR(NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP0_ARBURST(NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP0_ARCACHE(NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(NLW_inst_M_AXI_GP0_ARID_UNCONNECTED[11:0]),
.M_AXI_GP0_ARLEN(NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP0_ARLOCK(NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP0_ARPROT(NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP0_ARQOS(NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP0_ARREADY(1'b0),
.M_AXI_GP0_ARSIZE(NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP0_ARVALID(NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED),
.M_AXI_GP0_AWADDR(NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP0_AWBURST(NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP0_AWCACHE(NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP0_AWID(NLW_inst_M_AXI_GP0_AWID_UNCONNECTED[11:0]),
.M_AXI_GP0_AWLEN(NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP0_AWLOCK(NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP0_AWPROT(NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP0_AWQOS(NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP0_AWREADY(1'b0),
.M_AXI_GP0_AWSIZE(NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP0_AWVALID(NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED),
.M_AXI_GP0_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP0_BREADY(NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED),
.M_AXI_GP0_BRESP({1'b0,1'b0}),
.M_AXI_GP0_BVALID(1'b0),
.M_AXI_GP0_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP0_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP0_RLAST(1'b0),
.M_AXI_GP0_RREADY(NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED),
.M_AXI_GP0_RRESP({1'b0,1'b0}),
.M_AXI_GP0_RVALID(1'b0),
.M_AXI_GP0_WDATA(NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP0_WID(NLW_inst_M_AXI_GP0_WID_UNCONNECTED[11:0]),
.M_AXI_GP0_WLAST(NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED),
.M_AXI_GP0_WREADY(1'b0),
.M_AXI_GP0_WSTRB(NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP0_WVALID(NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED),
.M_AXI_GP1_ACLK(M_AXI_GP1_ACLK),
.M_AXI_GP1_ARADDR(M_AXI_GP1_ARADDR),
.M_AXI_GP1_ARBURST(M_AXI_GP1_ARBURST),
.M_AXI_GP1_ARCACHE(M_AXI_GP1_ARCACHE),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(M_AXI_GP1_ARID),
.M_AXI_GP1_ARLEN(M_AXI_GP1_ARLEN),
.M_AXI_GP1_ARLOCK(M_AXI_GP1_ARLOCK),
.M_AXI_GP1_ARPROT(M_AXI_GP1_ARPROT),
.M_AXI_GP1_ARQOS(M_AXI_GP1_ARQOS),
.M_AXI_GP1_ARREADY(M_AXI_GP1_ARREADY),
.M_AXI_GP1_ARSIZE(M_AXI_GP1_ARSIZE),
.M_AXI_GP1_ARVALID(M_AXI_GP1_ARVALID),
.M_AXI_GP1_AWADDR(M_AXI_GP1_AWADDR),
.M_AXI_GP1_AWBURST(M_AXI_GP1_AWBURST),
.M_AXI_GP1_AWCACHE(M_AXI_GP1_AWCACHE),
.M_AXI_GP1_AWID(M_AXI_GP1_AWID),
.M_AXI_GP1_AWLEN(M_AXI_GP1_AWLEN),
.M_AXI_GP1_AWLOCK(M_AXI_GP1_AWLOCK),
.M_AXI_GP1_AWPROT(M_AXI_GP1_AWPROT),
.M_AXI_GP1_AWQOS(M_AXI_GP1_AWQOS),
.M_AXI_GP1_AWREADY(M_AXI_GP1_AWREADY),
.M_AXI_GP1_AWSIZE(M_AXI_GP1_AWSIZE),
.M_AXI_GP1_AWVALID(M_AXI_GP1_AWVALID),
.M_AXI_GP1_BID(M_AXI_GP1_BID),
.M_AXI_GP1_BREADY(M_AXI_GP1_BREADY),
.M_AXI_GP1_BRESP(M_AXI_GP1_BRESP),
.M_AXI_GP1_BVALID(M_AXI_GP1_BVALID),
.M_AXI_GP1_RDATA(M_AXI_GP1_RDATA),
.M_AXI_GP1_RID(M_AXI_GP1_RID),
.M_AXI_GP1_RLAST(M_AXI_GP1_RLAST),
.M_AXI_GP1_RREADY(M_AXI_GP1_RREADY),
.M_AXI_GP1_RRESP(M_AXI_GP1_RRESP),
.M_AXI_GP1_RVALID(M_AXI_GP1_RVALID),
.M_AXI_GP1_WDATA(M_AXI_GP1_WDATA),
.M_AXI_GP1_WID(M_AXI_GP1_WID),
.M_AXI_GP1_WLAST(M_AXI_GP1_WLAST),
.M_AXI_GP1_WREADY(M_AXI_GP1_WREADY),
.M_AXI_GP1_WSTRB(M_AXI_GP1_WSTRB),
.M_AXI_GP1_WVALID(M_AXI_GP1_WVALID),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(S_AXI_HP1_ACLK),
.S_AXI_HP1_ARADDR(S_AXI_HP1_ARADDR),
.S_AXI_HP1_ARBURST(S_AXI_HP1_ARBURST),
.S_AXI_HP1_ARCACHE(S_AXI_HP1_ARCACHE),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID(S_AXI_HP1_ARID),
.S_AXI_HP1_ARLEN(S_AXI_HP1_ARLEN),
.S_AXI_HP1_ARLOCK(S_AXI_HP1_ARLOCK),
.S_AXI_HP1_ARPROT(S_AXI_HP1_ARPROT),
.S_AXI_HP1_ARQOS(S_AXI_HP1_ARQOS),
.S_AXI_HP1_ARREADY(S_AXI_HP1_ARREADY),
.S_AXI_HP1_ARSIZE(S_AXI_HP1_ARSIZE),
.S_AXI_HP1_ARVALID(S_AXI_HP1_ARVALID),
.S_AXI_HP1_AWADDR(S_AXI_HP1_AWADDR),
.S_AXI_HP1_AWBURST(S_AXI_HP1_AWBURST),
.S_AXI_HP1_AWCACHE(S_AXI_HP1_AWCACHE),
.S_AXI_HP1_AWID(S_AXI_HP1_AWID),
.S_AXI_HP1_AWLEN(S_AXI_HP1_AWLEN),
.S_AXI_HP1_AWLOCK(S_AXI_HP1_AWLOCK),
.S_AXI_HP1_AWPROT(S_AXI_HP1_AWPROT),
.S_AXI_HP1_AWQOS(S_AXI_HP1_AWQOS),
.S_AXI_HP1_AWREADY(S_AXI_HP1_AWREADY),
.S_AXI_HP1_AWSIZE(S_AXI_HP1_AWSIZE),
.S_AXI_HP1_AWVALID(S_AXI_HP1_AWVALID),
.S_AXI_HP1_BID(S_AXI_HP1_BID),
.S_AXI_HP1_BREADY(S_AXI_HP1_BREADY),
.S_AXI_HP1_BRESP(S_AXI_HP1_BRESP),
.S_AXI_HP1_BVALID(S_AXI_HP1_BVALID),
.S_AXI_HP1_RACOUNT(S_AXI_HP1_RACOUNT),
.S_AXI_HP1_RCOUNT(S_AXI_HP1_RCOUNT),
.S_AXI_HP1_RDATA(S_AXI_HP1_RDATA),
.S_AXI_HP1_RDISSUECAP1_EN(S_AXI_HP1_RDISSUECAP1_EN),
.S_AXI_HP1_RID(S_AXI_HP1_RID),
.S_AXI_HP1_RLAST(S_AXI_HP1_RLAST),
.S_AXI_HP1_RREADY(S_AXI_HP1_RREADY),
.S_AXI_HP1_RRESP(S_AXI_HP1_RRESP),
.S_AXI_HP1_RVALID(S_AXI_HP1_RVALID),
.S_AXI_HP1_WACOUNT(S_AXI_HP1_WACOUNT),
.S_AXI_HP1_WCOUNT(S_AXI_HP1_WCOUNT),
.S_AXI_HP1_WDATA(S_AXI_HP1_WDATA),
.S_AXI_HP1_WID(S_AXI_HP1_WID),
.S_AXI_HP1_WLAST(S_AXI_HP1_WLAST),
.S_AXI_HP1_WREADY(S_AXI_HP1_WREADY),
.S_AXI_HP1_WRISSUECAP1_EN(S_AXI_HP1_WRISSUECAP1_EN),
.S_AXI_HP1_WSTRB(S_AXI_HP1_WSTRB),
.S_AXI_HP1_WVALID(S_AXI_HP1_WVALID),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED),
.TTC0_WAVE1_OUT(NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED),
.TTC0_WAVE2_OUT(NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(USB1_PORT_INDCTL),
.USB1_VBUS_PWRFAULT(USB1_VBUS_PWRFAULT),
.USB1_VBUS_PWRSELECT(USB1_VBUS_PWRSELECT),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1600.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP1} dataWidth={64} clockFreq={10} usageRate={0.5} /><AXI interface={M_AXI_GP1} dataWidth={32} clockFreq={10} usageRate={0.5} />/>" *) (* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=400, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=9, PCW_UIPARAM_DDR_CWL=9, PCW_UIPARAM_DDR_T_RCD=9, PCW_UIPARAM_DDR_T_RP=9, PCW_UIPARAM_DDR_T_RC=60, PCW_UIPARAM_DDR_T_RAS_MIN=40, PCW_UIPARAM_DDR_T_FAW=50, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.315, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.391, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.374, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.271, PCW_UIPARAM_DDR_BOARD_DELAY0=0.434, PCW_UIPARAM_DDR_BOARD_DELAY1=0.398, PCW_UIPARAM_DDR_BOARD_DELAY2=0.41, PCW_UIPARAM_DDR_BOARD_DELAY3=0.455, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA3_PERIPHERAL_FREQMHZ=40.000000, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=48, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1600.000, PCW_USE_M_AXI_GP0=0, PCW_USE_M_AXI_GP1=1, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=1, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=32, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=Custom, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=1, PCW_SD1_SD1_IO=MIO 10 .. 15, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 8 .. 9, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=1, PCW_USB1_USB1_IO=MIO 40 .. 51, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=1, PCW_GPIO_EMIO_GPIO_IO=48, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=1, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *) (* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *) (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_HP0_DATA_WIDTH = "32" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *) (* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_FCLK_CLK0_BUF = "true" *) (* C_FCLK_CLK1_BUF = "false" *) (* C_FCLK_CLK2_BUF = "false" *)
(* C_FCLK_CLK3_BUF = "true" *) (* C_EMIO_GPIO_WIDTH = "48" *) (* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_PS7_SI_REV = "PRODUCTION" *) (* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_DQ_WIDTH = "32" *)
(* C_DQS_WIDTH = "4" *) (* C_DM_WIDTH = "4" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_PACKAGE_NAME = "clg400" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_EN_EMIO_PJTAG = "0" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *)
module processing_system7_0_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [47:0]GPIO_I;
output [47:0]GPIO_O;
output [47:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [31:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [31:0]S_AXI_HP0_WDATA;
input [3:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [3:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [47:0]GPIO_I;
wire [47:0]GPIO_O;
wire [47:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]M_AXI_GP1_ARCACHE;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]M_AXI_GP1_AWCACHE;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [31:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [31:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [3:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire n_1000_PS7_i;
wire n_701_PS7_i;
wire n_702_PS7_i;
wire n_703_PS7_i;
wire n_704_PS7_i;
wire n_953_PS7_i;
wire n_954_PS7_i;
wire n_955_PS7_i;
wire n_956_PS7_i;
wire n_957_PS7_i;
wire n_958_PS7_i;
wire n_959_PS7_i;
wire n_960_PS7_i;
wire n_961_PS7_i;
wire n_962_PS7_i;
wire n_963_PS7_i;
wire n_964_PS7_i;
wire n_965_PS7_i;
wire n_966_PS7_i;
wire n_967_PS7_i;
wire n_968_PS7_i;
wire n_969_PS7_i;
wire n_970_PS7_i;
wire n_971_PS7_i;
wire n_972_PS7_i;
wire n_973_PS7_i;
wire n_974_PS7_i;
wire n_975_PS7_i;
wire n_976_PS7_i;
wire n_977_PS7_i;
wire n_978_PS7_i;
wire n_979_PS7_i;
wire n_980_PS7_i;
wire n_981_PS7_i;
wire n_982_PS7_i;
wire n_983_PS7_i;
wire n_984_PS7_i;
wire n_985_PS7_i;
wire n_986_PS7_i;
wire n_987_PS7_i;
wire n_988_PS7_i;
wire n_989_PS7_i;
wire n_990_PS7_i;
wire n_991_PS7_i;
wire n_992_PS7_i;
wire n_993_PS7_i;
wire n_994_PS7_i;
wire n_995_PS7_i;
wire n_996_PS7_i;
wire n_997_PS7_i;
wire n_998_PS7_i;
wire n_999_PS7_i;
wire [3:0]p_0_in;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [63:48]NLW_PS7_i_EMIOGPIOO_UNCONNECTED;
wire [63:48]NLW_PS7_i_EMIOGPIOTN_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [63:32]NLW_PS7_i_SAXIHP0RDATA_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \<const0> ;
assign TRACE_DATA[1] = \<const0> ;
assign TRACE_DATA[0] = \<const0> ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(n_1000_PS7_i),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(n_990_PS7_i),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(n_989_PS7_i),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(n_988_PS7_i),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(n_987_PS7_i),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(n_986_PS7_i),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(n_985_PS7_i),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(n_984_PS7_i),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(n_983_PS7_i),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(n_982_PS7_i),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(n_981_PS7_i),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(n_999_PS7_i),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(n_980_PS7_i),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(n_979_PS7_i),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(n_978_PS7_i),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(n_977_PS7_i),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(n_976_PS7_i),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(n_975_PS7_i),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(n_974_PS7_i),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(n_973_PS7_i),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(n_972_PS7_i),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(n_971_PS7_i),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(n_998_PS7_i),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(n_970_PS7_i),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(n_969_PS7_i),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(n_968_PS7_i),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(n_967_PS7_i),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(n_966_PS7_i),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(n_965_PS7_i),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(n_964_PS7_i),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(n_963_PS7_i),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(n_962_PS7_i),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(n_961_PS7_i),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(n_997_PS7_i),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(n_960_PS7_i),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(n_959_PS7_i),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(n_958_PS7_i),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(n_957_PS7_i),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(n_956_PS7_i),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(n_955_PS7_i),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(n_954_PS7_i),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(n_953_PS7_i),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(n_996_PS7_i),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(n_995_PS7_i),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(n_994_PS7_i),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(n_993_PS7_i),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(n_992_PS7_i),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(n_991_PS7_i),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,GPIO_I}),
.EMIOGPIOO({NLW_PS7_i_EMIOGPIOO_UNCONNECTED[63:48],GPIO_O}),
.EMIOGPIOTN({NLW_PS7_i_EMIOGPIOTN_UNCONNECTED[63:48],n_953_PS7_i,n_954_PS7_i,n_955_PS7_i,n_956_PS7_i,n_957_PS7_i,n_958_PS7_i,n_959_PS7_i,n_960_PS7_i,n_961_PS7_i,n_962_PS7_i,n_963_PS7_i,n_964_PS7_i,n_965_PS7_i,n_966_PS7_i,n_967_PS7_i,n_968_PS7_i,n_969_PS7_i,n_970_PS7_i,n_971_PS7_i,n_972_PS7_i,n_973_PS7_i,n_974_PS7_i,n_975_PS7_i,n_976_PS7_i,n_977_PS7_i,n_978_PS7_i,n_979_PS7_i,n_980_PS7_i,n_981_PS7_i,n_982_PS7_i,n_983_PS7_i,n_984_PS7_i,n_985_PS7_i,n_986_PS7_i,n_987_PS7_i,n_988_PS7_i,n_989_PS7_i,n_990_PS7_i,n_991_PS7_i,n_992_PS7_i,n_993_PS7_i,n_994_PS7_i,n_995_PS7_i,n_996_PS7_i,n_997_PS7_i,n_998_PS7_i,n_999_PS7_i,n_1000_PS7_i}),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(p_0_in),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN({n_701_PS7_i,n_702_PS7_i,n_703_PS7_i,n_704_PS7_i}),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK_unbuffered[3],FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered[0]}),
.FCLKCLKTRIGN({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA({NLW_PS7_i_SAXIHP0RDATA_UNCONNECTED[63:32],S_AXI_HP0_RDATA}),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,S_AXI_HP0_WDATA}),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB({\<const0> ,\<const0> ,\<const0> ,\<const0> ,S_AXI_HP0_WSTRB}),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(p_0_in[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(p_0_in[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(p_0_in[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(p_0_in[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(n_704_PS7_i),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(n_703_PS7_i),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(n_702_PS7_i),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(n_701_PS7_i),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered[0]),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_3.FCLK_CLK_3_BUFG
(.I(FCLK_CLK_unbuffered[3]),
.O(FCLK_CLK3));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 256 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Stage of FFT 256 processor
// FUNCTION: 16-point FFT
// FILES: FFT16.v - stage, contains
// MPUC707.v - multiplier to the factor 0.707.
// PROPERTIES: 1) Fully pipelined
// 2) Each clock cycle complex datum is entered
// and complex result is outputted
// 3) Has 16-clock cycle period starting with the START impulse
// and continuing forever
// 4) rounding is not used
// 5)Algorithm is from the book "H.J.Nussbaumer FFT and convolution algorithms".
// 6)IFFT is performed by substituting the output result order to the reversed one
// (by exchanging - to + and + to -)
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Algorithm:
///procedure FFT16(
// X: in MEMOC; -- âõîäíîé ìàññèâ äàííûõ
// y:out MEMOC) -- âûõîäíîé ìàññèâ ñïåêòðîâ
// is
// variable t1,t2,t3,t4,t5,t6,t7,t8,t9,t10: complex;
// variable t11,t12,t13,t14,t15,t16,t17,t18,t19,t20: complex;
// variable t21,t22,t23,t24,t25,t26: complex;
// variable m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10: complex;
// variable m11,m12,m13,m14,m15,m16,m17: complex;
// variable s1,s2,s3,s4,s5,s6,s7,s8,s9,s10: complex;
// variable s11,s12,s13,s14,s15,s16,s17,s18,s19,s20: complex;
// begin
// t1:=x(0) + x(8); m4:=x(0) - x(8);
// t2:=x(4) + x(12); m12:=-CBASE_j*(x(4)-x(12));
// t3:=x(2) + x(10); t4:=x(2) - x(10);
// t5:=x(6) + x(14); t6:=x(6) - x(14);
// t7:=x(1) + x(9); t8:=x(1) - x(9);
// t9:=x(3) + x(11); t10:=x(3) - x(11);
// t11:=x(5) + x(13); t12:=x(5) - x(13);
// t13:=x(7) + x(15); t14:=x(7) - x(15);
// t15:=t1 + t2; m3:= t1 - t2;
// t16:=t3 + t5; m11:= -CBASE_j*(t3 - t5);
// t17:=t15 + t16; m2:= t15 - t16;
// t18:=t7 + t11; t19:= t7 - t11;
// t20:=t9 + t13; t21:= t9 - t13;
// t22:=t18 + t20; m10:= -CBASE_j*(t18 - t20);
// t23:=t8 + t14; t24:= t8 - t14;
// t25:=t12 + t10; t26:= t12 - t10;
//
// m0:=t17 + t22; m1:=t17 - t22;
// m13:=-CBASE_j*c707*(t19 + t21); m5:=c707*(t19 - t21);
// m6:=c707*(t4 - t6); m14:=-CBASE_j*c707*(t4 + t6);
//
// m7:=c3*(t24+t26);
// m8:=c13*(t24);
// m9:=-s1_3*(t26);
// s7:= m8 - m7;
// s8:= m9 - m7;
//
// m15:=-CBASE_j*c1*(t23 + t25);
// m16:= -CBASE_j*s1_3*(t23);
// m17:=-CBASE_j*c13*(t25);
// s15:= m15 - m16;
// s16:= m15 - m17;
//
// s1:=m3 + m5; s2:=m3 - m5;
// s3:=m13 + m11; s4:=m13 - m11;
// s5:=m4 + m6; s6:=m4 - m6;
// s9:=s5 + s7; s10:=s5 - s7;
// s11:=s6 + s8; s12:=s6 - s8;
// s13:=m12 + m14; s14:=m12 - m14;
// s17:=s13 + s15; s18:=s13 - s15;
// s19:=s14 + s16; s20:=s14 - s16;
//
// y(0):=m0; y(8):=m1;
// y(1):=s9 + s17; y(15):=s9 - s17;
// y(2):=s1 + s3; y(14):=s1 - s3;
// y(3):=s12 - s20; y(13):=s12 + s20;
// y(4):=m2 + m10; y(12):=m2 - m10;
// y(5):=s11 + s19; y(11):=s11 - s19;
// y(6):=s2 + s4; y(10):=s2 - s4;
// y(7):=s10 - s18; y(9):=s10 + s18;
// end procedure;
//
`timescale 1ns / 1ps
`include "FFT256_CONFIG.inc"
module FFT16 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY );
`FFT256paramnb
input ED ; //slowdown impulse
wire ED ;
input RST ;
wire RST ;
input CLK ;
wire CLK ;
input [nb-1:0] DII ;
wire [nb-1:0] DII ;
input START ;
wire START ;
input [nb-1:0] DIR ;
wire [nb-1:0] DIR ;
output [nb+3:0] DOI ;
wire [nb+3:0] DOI ;
output [nb+3:0] DOR ;
wire [nb+3:0] DOR ;
output RDY ;
reg RDY ;
reg [3:0] ct; //main phase counter
reg [5:0] ctd; //delay counter
always @( posedge CLK) begin //Control counter
//
if (RST) begin
ct<=0;
ctd<=63;
RDY<=0; end
else if (START) begin
ct<=0;
ctd<=0;
RDY<=0; end
else if (ED) begin
RDY<=0;
ct<=ct+1;
if (ctd !=6'b111111)
ctd<=ctd+1;
if (ctd==44-16 )
RDY<=1;
end
end
reg signed [nb-1: 0] dr,d1r,d2r,d3r,d4r,d5r,d6r,d7r,d8r,di,d1i,d2i,d3i,d4i,d5i,d6i,d7i,d8i;
always @(posedge CLK) // input register file
begin
if (ED) begin
dr<=DIR;
d1r<=dr; d2r<=d1r; d3r<=d2r;d4r<=d3r;
d5r<=d4r;d6r<=d5r; d7r<=d6r; d8r<=d7r;
di<=DII;
d1i<=di; d2i<=d1i; d3i<=d2i; d4i<=d3i;
d5i<=d4i; d6i<=d5i;d7i<=d6i; d8i<=d7i;
end
end
reg signed [nb:0] s1r,s1d1r,s1d2r,s1d3r,s1d4r,s1d5r,s1d6r,s1d7r,s1d8r; //even result sums
reg signed [nb:0] s1i,s1d1i,s1d2i,s1d3i,s1d4i,s1d5i,s1d6i,s1d7i,s1d8i; //even result sums
reg signed [nb:0] s2r,s2d1r,s2d2r,s2d3r,s2d4r,s2d5r,s2d6r,s2d7r,s2d8r,m4_12r; //odd result sums
reg signed [nb:0] s2i,s2d1i,s2d2i,s2d3i,s2d4i,s2d5i,s2d6i,s2d7i,s2d8i,m4_12i; //odd result sums
always @(posedge CLK) begin // S1,S2 =t1-t14,m4,m12' and delayed
if (ED && ((ct==9) || (ct==10) || (ct==11) ||(ct==12) ||
(ct==13) || (ct==14) ||(ct==15) || (ct==0))) begin
s1r<=d8r + dr ;
s1i<=d8i + di ;
s2r<=d8r - dr ;
s2i<= d8i - di;
end
if (ED) begin //delayed results
s1d1r<=s1r; s1d2r<=s1d1r; s1d1i<=s1i; s1d2i<=s1d1i;
s1d3r<=s1d2r; s1d3i<=s1d2i; s1d4r<=s1d3r; s1d4i<=s1d3i;
s1d5r<=s1d4r; s1d5i<=s1d4i; s1d6r<=s1d5r; s1d6i<=s1d5i;
s1d7r<=s1d6r; s1d7i<=s1d6i; s1d8r<=s1d7r; s1d8i<=s1d7i;
s2d1r<=s2r; s2d2r<=s2d1r; s2d1i<=s2i; s2d2i<=s2d1i;
s2d3r<=s2d2r; s2d3i<=s2d2i; s2d4r<=s2d3r; s2d4i<=s2d3i;
s2d5r<=s2d4r; s2d5i<=s2d4i; s2d6r<=s2d5r; s2d6i<=s2d5i;
s2d7r<=s2d6r; s2d7i<=s2d6i; s2d8r<=s2d7r; s2d8i<=s2d7i;
if (ct==2) begin
m4_12r<=s2d8r; m4_12i<=s2d8i; end
else if (ct==6) begin
m4_12r<=s2d8i; m4_12i<= 0 - s2d8r;
end
end
end
///////////////////////////////////////////
//arm of even result calculations
////////////////////////////////////////////
reg signed [nb+1:0] s3r,s3d1r,s3d2r,s3d3r,s3d4r,s3d5r,s3d6r;
reg signed [nb+1:0] s3i,s3d1i,s3d2i,s3d3i,s3d4i,s3d5i,s3d6i;
always @(posedge CLK) begin //ALU S3:
if (ED) begin
case (ct)
14 ,15 : begin s3r<= s1d4r+s1r; //t15 //t18
s3i<= s1d4i+ s1i ;end
0 ,1 : begin s3r<= s1d6r - s1d2r; //m3, t19
s3i<= s1d6i - s1d2i ;end
2 ,3 : begin s3r<= s1d6r +s1d2r; //t16 ,t20
s3i<= s1d6i+ s1d2i ; end
4 ,5 : begin s3r<= s1d8r - s1d4r; // m11',t21
s3i<= s1d8i - s1d4i ; end
endcase
s3d1r<=s3r; s3d1i<=s3i; s3d2r<=s3d1r; s3d2i<=s3d1i;
s3d3r<=s3d2r; s3d3i<=s3d2i; s3d4r<=s3d3r; s3d4i<=s3d3i;
s3d5r<=s3d4r; s3d5i<=s3d4i; s3d6r<=s3d5r; s3d6i<=s3d5i;
end
end
reg signed [nb+2:0] s4r,s4d1r,s4d2r,s4d3r,s4d4r,s4d5r,s4d6r,s4d7r,m3r;
reg signed [nb+2:0] s4i,s4d1i,s4d2i,s4d3i,s4d4i,s4d5i,s4d6i,s4d7i,m3i;
always @ (posedge CLK) begin // S4
if (ED) begin
if ((ct==3) | (ct==4)) begin
s4r<= s3d4r + s3r; //t17 ,t22
s4i<= s3d4i + s3i; end
else if ((ct==5) | (ct==6) | (ct==8) ) begin
s4r<=s3d6r - s3d2r; //m2,m10', m5'
s4i<= s3d6i - s3d2i; end
else if (ct==7) begin
s4r<=s3d1r + s3d5r; //m13
s4i<= s3d1i + s3d5i;
end
s4d1r<=s4r; s4d1i<=s4i; s4d2r<=s4d1r; s4d2i<=s4d1i;
s4d3r<=s4d2r; s4d3i<=s4d2i; s4d4r<=s4d3r; s4d4i<=s4d3i;
s4d5r<=s4d4r; s4d5i<=s4d4i; s4d6r<=s4d5r; s4d6i<=s4d5i;
s4d7r<=s4d6r; s4d7i<=s4d6i;
if (ct==7) begin
m3r<=s3d6r; //m3
m3i<=s3d6i; end
end
end
wire em707,mpyj7;
assign em707 = ((ct==8) || (ct==10 )||(ct==1) || (ct==5)); //control signals for the multiplier
assign mpyj7 = ((ct==8) || (ct==5));
reg signed [nb+2:0] s7r,s7d1r;
reg signed [nb+2:0] s7i,s7d1i;
wire signed [nb+2:0] m707r,m707i,m70r,m70i;
assign m70r = ((ct==1) || (ct==5))? s7r :s4r; //multiplexor at the multiplier input
assign m70i = ((ct==1) || (ct==5))? s7i :s4i;
MPUC707 #(nb+3) UM707( .CLK(CLK),.EI(ED),.ED(em707), .MPYJ(mpyj7), //multiplier by 0.707
.DR(m70r),.DI(m70i) ,.DOR(m707r) ,.DOI(m707i));
reg signed [nb+2:0] s3jr,s3ji, m10r,m10i;
always @ (posedge CLK) begin //multiply by J
if (ED) begin
case (ct)
11: begin s3jr<= s3d6i; //m11
s3ji<=0 - s3d6r; end
14: begin s3jr<= s4d7i; //m10
s3ji<=0 - s4d7r; end
endcase
if (ct==1) begin
m10r<=s3jr; //m10
m10i<=s3ji;
end
end
end
reg signed [nb+3:0] s5r,s5d1r,s5d2r,s5d3r,s5d4r,s5d5r,s5d6r,s5d7r,s5d8r,s5d9r, s5d10r,m2r,m2dr;
reg signed [nb+3:0] s5i,s5d1i,s5d2i,s5d3i,s5d4i,s5d5i,s5d6i,s5d7i,s5d8i,s5d9i,s5d10i,m2i,m2di;
always @ (posedge CLK) // S5:
if (ED) begin
case (ct)
10: begin s5r<=s4d5r + s4d6r; //m0
s5i<=s4d5i + s4d6i; end
11: begin s5r<=s4d7r - s4d6r; //m1
s5i<=s4d7i - s4d6i; end
12: begin s5r<=m707r + s3jr; //S3
s5i<= m707i+s3ji;end
13: begin s5r<=m707r - s3jr; //S4
s5i<= m707i - s3ji;end
14: begin s5r<= m3r+m707r; //S1
s5i<= m3i+m707i ;end
15: begin s5r<=m3r-m707r ; //S2
s5i<= m3i -m707i ;end
6: begin //S2
s5d10r<=s5d9r ; //S2
s5d10i<=s5d9i ;end
endcase
if ((ct==4)||(ct==5)||(ct==6)||(ct==7)) begin
s5d9r<=s5d8r ; s5d9i<=s5d8i ; end
s5d1r<=s5r; s5d1i<=s5i; s5d2r<=s5d1r; s5d2i<=s5d1i;
s5d3r<=s5d2r; s5d3i<=s5d2i; s5d4r<=s5d3r; s5d4i<=s5d3i;
s5d5r<=s5d4r; s5d5i<=s5d4i; s5d6r<=s5d5r; s5d6i<=s5d5i;
s5d7r<=s5d6r; s5d7i<=s5d6i; s5d8r<=s5d7r; s5d8i<=s5d7i;
if (ct==13) begin
m2r<=s4d7r; m2i<=s4d7i; end
if (ct==1) begin
m2dr<=m2r; m2di<=m2i; end
end
reg signed [nb+3:0] s6r,s6i ;
`ifdef FFT256paramifft // For IFFT
always @ (posedge CLK) begin // S6-- result adder
if (ED)
case (ct)
13: begin s6r<=s5d2r; // -- Y0
s6i<=(s5d2i);end //-- Y0
15: begin
s6r<=s5d2r - s5r ; //Y2
s6i<=s5d2i - s5i ; end
1: begin
s6r<=m2r - s3jr ; //Y4
s6i<=m2i - s3ji ; end
3: begin
s6r<=s5d3r - s5d5r ; //Y6
s6i<= s5d3i -s5d5i ; end
5:begin s6r<=(s5d9r) ; //-- Y8
s6i<=(s5d9i) ; end
7: begin
s6r<= s5d7r + s5d9r ; // Y10
s6i<= s5d7i + s5d9i ; end
9: begin // Y12
s6r<=m2dr +m10r ;
s6i<=m2di + m10i ;
end
11: begin // Y14
s6r<= s5d9r + s5d10r ;
s6i<= s5d9i + s5d10i ;
end
endcase
end
`else
always @ (posedge CLK) begin // S6-- result adder
if (ED)
case (ct)
13: begin s6r<=s5d2r; // -- Y0
s6i<=s5d2i;end //-- Y0
15: begin
s6r<=s5d2r + s5r ; //Y2
s6i<=s5d2i + s5i ; end
1: begin
s6r<=m2r + s3jr ; //Y4
s6i<=m2i + s3ji ; end
3: begin
s6r<=s5d3r + s5d5r ; //Y6
s6i<= s5d3i +s5d5i ; end
5:begin s6r<=s5d9r; //-- Y8
s6i<=s5d9i; end
7: begin
s6r<= s5d7r - s5d9r ; // Y10
s6i<= s5d7i - s5d9i ; end
9: begin // Y12
s6r<=m2dr -m10r ;
s6i<=m2di - m10i ;
end
11: begin // Y14
s6r<= s5d9r - s5d10r ;
s6i<= s5d9i - s5d10i ;
end
endcase
end
`endif
///////////////////////////////////////////////////////////
//arm of odd result calculations
//////////////////////////////////////////////////////////
always @(posedge CLK) begin //ALU S7:
if (ED)
case (ct)
15:begin s7r<= s2d2r-s2r; //t26
s7i<= s2d2i- s2i ;end
0: begin s7r<= s2d4r-s2r; //m6'
s7i<= s2d4i- s2i ;
s7d1r<=s7r;
s7d1i<=s7i;end
1: begin s7r<= s2d6r - s2r; //t24
s7i<= s2d6i - s2i; end
2: begin s7r<= s7r -s7d1r; //m7'
s7i<= s7i- s7d1i ; end
3: begin s7r<= s2d8r + s2d2r; // t23
s7i<= s2d8i + s2d2i ; end
4: begin s7r<= s2d8r + s2d4r; // m14'
s7i<= s2d8i + s2d4i ;
s7d1r<=s7r;
s7d1i<=s7i;end
5: begin s7r<= s2d8r + s2d6r; // t25
s7i<= s2d8i + s2d6i ; end
6: begin s7r<= s7r + s7d1r; //m15'
s7i<= s7i + s7d1i ; end
endcase
end
wire em541,mpyj541;
wire signed [nb+2:0] m541r,m541i;
assign em541 = ((ct==0) || (ct==4)); //control signals for the multiplier
assign mpyj541 = ((ct==4));
MPUC541 #(nb+3) UM541( .CLK(CLK),.EI(ED),.ED(em541), .MPYJ(mpyj541), //multiplier by 0.383
.DR(s7r),.DI(s7i) ,.DOR(m541r) ,.DOI(m541i));
wire em1307,mpyj1307;
wire signed [nb+2:0] m1307r,m1307i;
assign em1307 = ((ct==2) || (ct==6)); //control signals for the multiplier
assign mpyj1307 = ((ct==6));
MPUC1307 #(nb+3) UM1307( .CLK(CLK),.EI(ED),.ED(em1307), .MPYJ(mpyj1307), //multiplier by 1.306
.DR(s7r),.DI(s7i) ,.DOR(m1307r) ,.DOI(m1307i));
wire em383,mpyj383,c383;
wire signed [nb+2:0] m383r,m383i;
assign em383 = ((ct==3) || (ct==7)); //control signals for the multiplier
assign mpyj383 = ((ct==7));
assign c383 = (ct==3);
MPUC924_383 #(nb+3) UM383(.CLK(CLK),.EI(ED),.ED(em383),.MPYJ(mpyj383),.C383(c383), //multiplier by 0.383
.DR(s7r),.DI(s7i) ,.DOR(m383r) ,.DOI(m383i));
reg signed [nb+2:0] m8_17r,m8_17i,m9_16r,m9_16i;
always @(posedge CLK) begin //Reg-s
if (ED) begin
if (ct==4 || ct==8) begin
m9_16r<=m541r; //M9_ M16
m9_16i<=m541i;
end
if ( ct==6 || ct==10) begin
m8_17r<=m1307r; //M8_ M17
m8_17i<=m1307i;
end
end
end
reg signed [nb+2:0] s8r,s8i,s8d1r,s8d2r,s8d3r,s8d4r,s8d1i,s8d2i,s8d3i,s8d4i ;
always @ (posedge CLK) begin // S8-- adder
if (ED)
case (ct)
5,9: begin s8r<=m4_12r +m707r ; // -- S5 S13
s8i<=m4_12i +m707i ;end //--
6,10: begin
s8r<=m4_12r - m707r ; // -- S6 , S14
s8i<=m4_12i - m707i ; end
7: begin
s8r<=m8_17r - m383r ; // -- S7 ,S15
s8i<=m8_17i -m383i ; end
8: begin
s8r<=m9_16r - m383r ; // -- S8 , S16
s8i<=m9_16i -m383i ; end
11: begin
s8r<=m383r - m9_16r ; // -- S7 ,S15
s8i<=m383i - m9_16i; end
12: begin
s8r<=m383r - m8_17r; // -- S8 , S16
s8i<=m383i - m8_17i; end
endcase
s8d1r<=s8r; s8d1i<=s8i; s8d2r<=s8d1r; s8d2i<=s8d1i;
s8d3r<=s8d2r; s8d3i<=s8d2i; s8d4r<=s8d3r; s8d4i<=s8d3i;
end
reg signed [nb+3:0] s9r,s9d1r,s9d2r,s9d3r,s9d4r,s9d5r,s9d6r,s9d7r,s9d8r,s9d9r, s9d10r,s9d11r,s9d12r,s9d13r;
reg signed [nb+3:0] s9i,s9d1i,s9d2i,s9d3i,s9d4i,s9d5i,s9d6i,s9d7i,s9d8i,s9d9i,s9d10i,s9d11i,s9d12i,s9d13i;
always @ (posedge CLK) // ALU s9:
if (ED) begin
case (ct)
8,9,12: begin s9r<= s8r + s8d2r; // S9,S11 , S17
s9i<=s8i + s8d2i ; end
13: begin s9r<= s8d2r - s8r; // S20
s9i<=s8d2i - s8i ; end
10,11,14: begin s9r<=s8d4r - s8d2r; //S10, S12,S18
s9i<=s8d4i - s8d2i; end
15: begin s9r<=s8d4r + s8d2r; //S19
s9i<=s8d4i + s8d2i; end
endcase
s9d1r<=s9r; s9d1i<=s9i; s9d2r<=s9d1r; s9d2i<=s9d1i;
s9d3r<=s9d2r; s9d3i<=s9d2i; s9d4r<=s9d3r; s9d4i<=s9d3i;
s9d5r<=s9d4r; s9d5i<=s9d4i; s9d6r<=s9d5r; s9d6i<=s9d5i;
s9d7r<=s9d6r; s9d7i<=s9d6i; s9d8r<=s9d7r; s9d8i<=s9d7i;
s9d9r<=s9d8r ; s9d9i<=s9d8i ;
if ((ct!=8)) begin
s9d10r<=s9d9r ; s9d10i<=s9d9i ;
s9d11r<=s9d10r ; s9d11i<=s9d10i ; end
if ((ct==4) ||(ct==5) ||(ct==7) ||(ct==9) ) begin
s9d12r<=s9d11r ; s9d12i<=s9d11i ; end
if ((ct==5))begin
s9d13r<=s9d12r ; s9d13i<=s9d12i ; end
end
reg signed [nb+3:0] s10r,s10i;
reg signed [nb+3:0] s10dr,s10di;
`ifdef FFT256paramifft //For IFFT
always @ (posedge CLK) begin // S10-- result adder
if (ED)
case (ct)
13: begin s10r<=s9d4r -s9r ; // -- Y1
s10i<=s9d4i -s9i ;end //
15: begin
s10r<=s9d3r + s9d1r ; //-- Y3
s10i<=s9d3i + s9d1i ; end
1: begin
s10r<=s9d7r - s9d1r ; //-- Y5
s10i<=s9d7i - s9d1i ; end
3: begin
s10r<=s9d8r + s9d4r ; // -- Y7
s10i<= s9d8i + s9d4i ;end
5:begin s10r<=s9d10r - s9d6r ; //-- Y9
s10i<=s9d10i - s9d6i ; end
7: begin
s10r<=s9d12r + s9d7r ; //-- Y11
s10i<=s9d12i + s9d7i ; end
9: begin
s10r<= s9d12r - s9d10r ; // Y13
s10i<=s9d12i - s9d10i ; end
11: begin
s10r<= s9d13r + s9d12r ; // Y15
s10i<= s9d13i + s9d12i ; end
endcase
s10dr<=s10r; s10di<=s10i;
end
`else
// reg signed [nb+3:0] s10r,s10i,s10dr,s10di;
always @ (posedge CLK) begin // S10-- result adder
if (ED)
case (ct)
13: begin s10r<=s9d4r +s9r ; // -- Y0
s10i<=s9d4i +s9i ;end //
15: begin
s10r<=s9d3r - s9d1r ; //-- Y3
s10i<=s9d3i - s9d1i ; end
1: begin
s10r<=s9d7r +s9d1r ; //-- Y5
s10i<=s9d7i +s9d1i ; end
3: begin
s10r<=s9d8r - s9d4r ; // -- Y7
s10i<= s9d8i - s9d4i ;end
5:begin s10r<=s9d10r + s9d6r ; //-- Y9
s10i<=s9d10i + s9d6i ; end
7: begin
s10r<=s9d12r - s9d7r ; //-- Y11
s10i<=s9d12i - s9d7i ; end
9: begin
s10r<= s9d12r + s9d10r ; // Y13
s10i<=s9d12i + s9d10i ; end
11: begin
s10r<= s9d13r - s9d12r ; // Y15
s10i<= s9d13i - s9d12i ; end
endcase
s10dr<=s10r; s10di<=s10i;
end
`endif
//wire signed [nb+3:0] s6sr,s6si; //saturation of results
// assign s6sr = (~s6r[nb+4]&&s6r[nb+3])? ((1'b1 <<(nb+3))-1) : s6r[nb+3:0];
// assign s6si = (~s6i[nb+4]&&s6i[nb+3])? ((1'b1<<(nb+3))-1) : s6i[nb+3:0];
//
wire selo;
assign selo = ct-(ct/2)*2;
assign #1 DOR=selo? s10dr:s6r;
assign #1 DOI= selo? s10di:s6i;
endmodule
|
//-----------------------------------------------------------------------------
// system_axi4lite_0_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "axi_interconnect_v1_06_a" *)
module system_axi4lite_0_wrapper
(
INTERCONNECT_ACLK,
INTERCONNECT_ARESETN,
S_AXI_ARESET_OUT_N,
M_AXI_ARESET_OUT_N,
IRQ,
S_AXI_ACLK,
S_AXI_AWID,
S_AXI_AWADDR,
S_AXI_AWLEN,
S_AXI_AWSIZE,
S_AXI_AWBURST,
S_AXI_AWLOCK,
S_AXI_AWCACHE,
S_AXI_AWPROT,
S_AXI_AWQOS,
S_AXI_AWUSER,
S_AXI_AWVALID,
S_AXI_AWREADY,
S_AXI_WID,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WLAST,
S_AXI_WUSER,
S_AXI_WVALID,
S_AXI_WREADY,
S_AXI_BID,
S_AXI_BRESP,
S_AXI_BUSER,
S_AXI_BVALID,
S_AXI_BREADY,
S_AXI_ARID,
S_AXI_ARADDR,
S_AXI_ARLEN,
S_AXI_ARSIZE,
S_AXI_ARBURST,
S_AXI_ARLOCK,
S_AXI_ARCACHE,
S_AXI_ARPROT,
S_AXI_ARQOS,
S_AXI_ARUSER,
S_AXI_ARVALID,
S_AXI_ARREADY,
S_AXI_RID,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RLAST,
S_AXI_RUSER,
S_AXI_RVALID,
S_AXI_RREADY,
M_AXI_ACLK,
M_AXI_AWID,
M_AXI_AWADDR,
M_AXI_AWLEN,
M_AXI_AWSIZE,
M_AXI_AWBURST,
M_AXI_AWLOCK,
M_AXI_AWCACHE,
M_AXI_AWPROT,
M_AXI_AWREGION,
M_AXI_AWQOS,
M_AXI_AWUSER,
M_AXI_AWVALID,
M_AXI_AWREADY,
M_AXI_WID,
M_AXI_WDATA,
M_AXI_WSTRB,
M_AXI_WLAST,
M_AXI_WUSER,
M_AXI_WVALID,
M_AXI_WREADY,
M_AXI_BID,
M_AXI_BRESP,
M_AXI_BUSER,
M_AXI_BVALID,
M_AXI_BREADY,
M_AXI_ARID,
M_AXI_ARADDR,
M_AXI_ARLEN,
M_AXI_ARSIZE,
M_AXI_ARBURST,
M_AXI_ARLOCK,
M_AXI_ARCACHE,
M_AXI_ARPROT,
M_AXI_ARREGION,
M_AXI_ARQOS,
M_AXI_ARUSER,
M_AXI_ARVALID,
M_AXI_ARREADY,
M_AXI_RID,
M_AXI_RDATA,
M_AXI_RRESP,
M_AXI_RLAST,
M_AXI_RUSER,
M_AXI_RVALID,
M_AXI_RREADY,
S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA,
S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY,
INTERCONNECT_ARESET_OUT_N,
DEBUG_AW_TRANS_SEQ,
DEBUG_AW_ARB_GRANT,
DEBUG_AR_TRANS_SEQ,
DEBUG_AR_ARB_GRANT,
DEBUG_AW_TRANS_QUAL,
DEBUG_AW_ACCEPT_CNT,
DEBUG_AW_ACTIVE_THREAD,
DEBUG_AW_ACTIVE_TARGET,
DEBUG_AW_ACTIVE_REGION,
DEBUG_AW_ERROR,
DEBUG_AW_TARGET,
DEBUG_AR_TRANS_QUAL,
DEBUG_AR_ACCEPT_CNT,
DEBUG_AR_ACTIVE_THREAD,
DEBUG_AR_ACTIVE_TARGET,
DEBUG_AR_ACTIVE_REGION,
DEBUG_AR_ERROR,
DEBUG_AR_TARGET,
DEBUG_B_TRANS_SEQ,
DEBUG_R_BEAT_CNT,
DEBUG_R_TRANS_SEQ,
DEBUG_AW_ISSUING_CNT,
DEBUG_AR_ISSUING_CNT,
DEBUG_W_BEAT_CNT,
DEBUG_W_TRANS_SEQ,
DEBUG_BID_TARGET,
DEBUG_BID_ERROR,
DEBUG_RID_TARGET,
DEBUG_RID_ERROR,
DEBUG_SR_SC_ARADDR,
DEBUG_SR_SC_ARADDRCONTROL,
DEBUG_SR_SC_AWADDR,
DEBUG_SR_SC_AWADDRCONTROL,
DEBUG_SR_SC_BRESP,
DEBUG_SR_SC_RDATA,
DEBUG_SR_SC_RDATACONTROL,
DEBUG_SR_SC_WDATA,
DEBUG_SR_SC_WDATACONTROL,
DEBUG_SC_SF_ARADDR,
DEBUG_SC_SF_ARADDRCONTROL,
DEBUG_SC_SF_AWADDR,
DEBUG_SC_SF_AWADDRCONTROL,
DEBUG_SC_SF_BRESP,
DEBUG_SC_SF_RDATA,
DEBUG_SC_SF_RDATACONTROL,
DEBUG_SC_SF_WDATA,
DEBUG_SC_SF_WDATACONTROL,
DEBUG_SF_CB_ARADDR,
DEBUG_SF_CB_ARADDRCONTROL,
DEBUG_SF_CB_AWADDR,
DEBUG_SF_CB_AWADDRCONTROL,
DEBUG_SF_CB_BRESP,
DEBUG_SF_CB_RDATA,
DEBUG_SF_CB_RDATACONTROL,
DEBUG_SF_CB_WDATA,
DEBUG_SF_CB_WDATACONTROL,
DEBUG_CB_MF_ARADDR,
DEBUG_CB_MF_ARADDRCONTROL,
DEBUG_CB_MF_AWADDR,
DEBUG_CB_MF_AWADDRCONTROL,
DEBUG_CB_MF_BRESP,
DEBUG_CB_MF_RDATA,
DEBUG_CB_MF_RDATACONTROL,
DEBUG_CB_MF_WDATA,
DEBUG_CB_MF_WDATACONTROL,
DEBUG_MF_MC_ARADDR,
DEBUG_MF_MC_ARADDRCONTROL,
DEBUG_MF_MC_AWADDR,
DEBUG_MF_MC_AWADDRCONTROL,
DEBUG_MF_MC_BRESP,
DEBUG_MF_MC_RDATA,
DEBUG_MF_MC_RDATACONTROL,
DEBUG_MF_MC_WDATA,
DEBUG_MF_MC_WDATACONTROL,
DEBUG_MC_MP_ARADDR,
DEBUG_MC_MP_ARADDRCONTROL,
DEBUG_MC_MP_AWADDR,
DEBUG_MC_MP_AWADDRCONTROL,
DEBUG_MC_MP_BRESP,
DEBUG_MC_MP_RDATA,
DEBUG_MC_MP_RDATACONTROL,
DEBUG_MC_MP_WDATA,
DEBUG_MC_MP_WDATACONTROL,
DEBUG_MP_MR_ARADDR,
DEBUG_MP_MR_ARADDRCONTROL,
DEBUG_MP_MR_AWADDR,
DEBUG_MP_MR_AWADDRCONTROL,
DEBUG_MP_MR_BRESP,
DEBUG_MP_MR_RDATA,
DEBUG_MP_MR_RDATACONTROL,
DEBUG_MP_MR_WDATA,
DEBUG_MP_MR_WDATACONTROL
);
input INTERCONNECT_ACLK;
input INTERCONNECT_ARESETN;
output [0:0] S_AXI_ARESET_OUT_N;
output [5:0] M_AXI_ARESET_OUT_N;
output IRQ;
input [0:0] S_AXI_ACLK;
input [11:0] S_AXI_AWID;
input [31:0] S_AXI_AWADDR;
input [7:0] S_AXI_AWLEN;
input [2:0] S_AXI_AWSIZE;
input [1:0] S_AXI_AWBURST;
input [1:0] S_AXI_AWLOCK;
input [3:0] S_AXI_AWCACHE;
input [2:0] S_AXI_AWPROT;
input [3:0] S_AXI_AWQOS;
input [0:0] S_AXI_AWUSER;
input [0:0] S_AXI_AWVALID;
output [0:0] S_AXI_AWREADY;
input [11:0] S_AXI_WID;
input [31:0] S_AXI_WDATA;
input [3:0] S_AXI_WSTRB;
input [0:0] S_AXI_WLAST;
input [0:0] S_AXI_WUSER;
input [0:0] S_AXI_WVALID;
output [0:0] S_AXI_WREADY;
output [11:0] S_AXI_BID;
output [1:0] S_AXI_BRESP;
output [0:0] S_AXI_BUSER;
output [0:0] S_AXI_BVALID;
input [0:0] S_AXI_BREADY;
input [11:0] S_AXI_ARID;
input [31:0] S_AXI_ARADDR;
input [7:0] S_AXI_ARLEN;
input [2:0] S_AXI_ARSIZE;
input [1:0] S_AXI_ARBURST;
input [1:0] S_AXI_ARLOCK;
input [3:0] S_AXI_ARCACHE;
input [2:0] S_AXI_ARPROT;
input [3:0] S_AXI_ARQOS;
input [0:0] S_AXI_ARUSER;
input [0:0] S_AXI_ARVALID;
output [0:0] S_AXI_ARREADY;
output [11:0] S_AXI_RID;
output [31:0] S_AXI_RDATA;
output [1:0] S_AXI_RRESP;
output [0:0] S_AXI_RLAST;
output [0:0] S_AXI_RUSER;
output [0:0] S_AXI_RVALID;
input [0:0] S_AXI_RREADY;
input [5:0] M_AXI_ACLK;
output [71:0] M_AXI_AWID;
output [191:0] M_AXI_AWADDR;
output [47:0] M_AXI_AWLEN;
output [17:0] M_AXI_AWSIZE;
output [11:0] M_AXI_AWBURST;
output [11:0] M_AXI_AWLOCK;
output [23:0] M_AXI_AWCACHE;
output [17:0] M_AXI_AWPROT;
output [23:0] M_AXI_AWREGION;
output [23:0] M_AXI_AWQOS;
output [5:0] M_AXI_AWUSER;
output [5:0] M_AXI_AWVALID;
input [5:0] M_AXI_AWREADY;
output [71:0] M_AXI_WID;
output [191:0] M_AXI_WDATA;
output [23:0] M_AXI_WSTRB;
output [5:0] M_AXI_WLAST;
output [5:0] M_AXI_WUSER;
output [5:0] M_AXI_WVALID;
input [5:0] M_AXI_WREADY;
input [71:0] M_AXI_BID;
input [11:0] M_AXI_BRESP;
input [5:0] M_AXI_BUSER;
input [5:0] M_AXI_BVALID;
output [5:0] M_AXI_BREADY;
output [71:0] M_AXI_ARID;
output [191:0] M_AXI_ARADDR;
output [47:0] M_AXI_ARLEN;
output [17:0] M_AXI_ARSIZE;
output [11:0] M_AXI_ARBURST;
output [11:0] M_AXI_ARLOCK;
output [23:0] M_AXI_ARCACHE;
output [17:0] M_AXI_ARPROT;
output [23:0] M_AXI_ARREGION;
output [23:0] M_AXI_ARQOS;
output [5:0] M_AXI_ARUSER;
output [5:0] M_AXI_ARVALID;
input [5:0] M_AXI_ARREADY;
input [71:0] M_AXI_RID;
input [191:0] M_AXI_RDATA;
input [11:0] M_AXI_RRESP;
input [5:0] M_AXI_RLAST;
input [5:0] M_AXI_RUSER;
input [5:0] M_AXI_RVALID;
output [5:0] M_AXI_RREADY;
input [31:0] S_AXI_CTRL_AWADDR;
input S_AXI_CTRL_AWVALID;
output S_AXI_CTRL_AWREADY;
input [31:0] S_AXI_CTRL_WDATA;
input S_AXI_CTRL_WVALID;
output S_AXI_CTRL_WREADY;
output [1:0] S_AXI_CTRL_BRESP;
output S_AXI_CTRL_BVALID;
input S_AXI_CTRL_BREADY;
input [31:0] S_AXI_CTRL_ARADDR;
input S_AXI_CTRL_ARVALID;
output S_AXI_CTRL_ARREADY;
output [31:0] S_AXI_CTRL_RDATA;
output [1:0] S_AXI_CTRL_RRESP;
output S_AXI_CTRL_RVALID;
input S_AXI_CTRL_RREADY;
output INTERCONNECT_ARESET_OUT_N;
output [7:0] DEBUG_AW_TRANS_SEQ;
output [7:0] DEBUG_AW_ARB_GRANT;
output [7:0] DEBUG_AR_TRANS_SEQ;
output [7:0] DEBUG_AR_ARB_GRANT;
output [0:0] DEBUG_AW_TRANS_QUAL;
output [7:0] DEBUG_AW_ACCEPT_CNT;
output [15:0] DEBUG_AW_ACTIVE_THREAD;
output [7:0] DEBUG_AW_ACTIVE_TARGET;
output [7:0] DEBUG_AW_ACTIVE_REGION;
output [7:0] DEBUG_AW_ERROR;
output [7:0] DEBUG_AW_TARGET;
output [0:0] DEBUG_AR_TRANS_QUAL;
output [7:0] DEBUG_AR_ACCEPT_CNT;
output [15:0] DEBUG_AR_ACTIVE_THREAD;
output [7:0] DEBUG_AR_ACTIVE_TARGET;
output [7:0] DEBUG_AR_ACTIVE_REGION;
output [7:0] DEBUG_AR_ERROR;
output [7:0] DEBUG_AR_TARGET;
output [7:0] DEBUG_B_TRANS_SEQ;
output [7:0] DEBUG_R_BEAT_CNT;
output [7:0] DEBUG_R_TRANS_SEQ;
output [7:0] DEBUG_AW_ISSUING_CNT;
output [7:0] DEBUG_AR_ISSUING_CNT;
output [7:0] DEBUG_W_BEAT_CNT;
output [7:0] DEBUG_W_TRANS_SEQ;
output [7:0] DEBUG_BID_TARGET;
output DEBUG_BID_ERROR;
output [7:0] DEBUG_RID_TARGET;
output DEBUG_RID_ERROR;
output [31:0] DEBUG_SR_SC_ARADDR;
output [34:0] DEBUG_SR_SC_ARADDRCONTROL;
output [31:0] DEBUG_SR_SC_AWADDR;
output [34:0] DEBUG_SR_SC_AWADDRCONTROL;
output [15:0] DEBUG_SR_SC_BRESP;
output [31:0] DEBUG_SR_SC_RDATA;
output [16:0] DEBUG_SR_SC_RDATACONTROL;
output [31:0] DEBUG_SR_SC_WDATA;
output [6:0] DEBUG_SR_SC_WDATACONTROL;
output [31:0] DEBUG_SC_SF_ARADDR;
output [34:0] DEBUG_SC_SF_ARADDRCONTROL;
output [31:0] DEBUG_SC_SF_AWADDR;
output [34:0] DEBUG_SC_SF_AWADDRCONTROL;
output [15:0] DEBUG_SC_SF_BRESP;
output [31:0] DEBUG_SC_SF_RDATA;
output [16:0] DEBUG_SC_SF_RDATACONTROL;
output [31:0] DEBUG_SC_SF_WDATA;
output [6:0] DEBUG_SC_SF_WDATACONTROL;
output [31:0] DEBUG_SF_CB_ARADDR;
output [34:0] DEBUG_SF_CB_ARADDRCONTROL;
output [31:0] DEBUG_SF_CB_AWADDR;
output [34:0] DEBUG_SF_CB_AWADDRCONTROL;
output [15:0] DEBUG_SF_CB_BRESP;
output [31:0] DEBUG_SF_CB_RDATA;
output [16:0] DEBUG_SF_CB_RDATACONTROL;
output [31:0] DEBUG_SF_CB_WDATA;
output [6:0] DEBUG_SF_CB_WDATACONTROL;
output [31:0] DEBUG_CB_MF_ARADDR;
output [34:0] DEBUG_CB_MF_ARADDRCONTROL;
output [31:0] DEBUG_CB_MF_AWADDR;
output [34:0] DEBUG_CB_MF_AWADDRCONTROL;
output [15:0] DEBUG_CB_MF_BRESP;
output [31:0] DEBUG_CB_MF_RDATA;
output [16:0] DEBUG_CB_MF_RDATACONTROL;
output [31:0] DEBUG_CB_MF_WDATA;
output [6:0] DEBUG_CB_MF_WDATACONTROL;
output [31:0] DEBUG_MF_MC_ARADDR;
output [34:0] DEBUG_MF_MC_ARADDRCONTROL;
output [31:0] DEBUG_MF_MC_AWADDR;
output [34:0] DEBUG_MF_MC_AWADDRCONTROL;
output [15:0] DEBUG_MF_MC_BRESP;
output [31:0] DEBUG_MF_MC_RDATA;
output [16:0] DEBUG_MF_MC_RDATACONTROL;
output [31:0] DEBUG_MF_MC_WDATA;
output [6:0] DEBUG_MF_MC_WDATACONTROL;
output [31:0] DEBUG_MC_MP_ARADDR;
output [34:0] DEBUG_MC_MP_ARADDRCONTROL;
output [31:0] DEBUG_MC_MP_AWADDR;
output [34:0] DEBUG_MC_MP_AWADDRCONTROL;
output [15:0] DEBUG_MC_MP_BRESP;
output [31:0] DEBUG_MC_MP_RDATA;
output [16:0] DEBUG_MC_MP_RDATACONTROL;
output [31:0] DEBUG_MC_MP_WDATA;
output [6:0] DEBUG_MC_MP_WDATACONTROL;
output [31:0] DEBUG_MP_MR_ARADDR;
output [34:0] DEBUG_MP_MR_ARADDRCONTROL;
output [31:0] DEBUG_MP_MR_AWADDR;
output [34:0] DEBUG_MP_MR_AWADDRCONTROL;
output [15:0] DEBUG_MP_MR_BRESP;
output [31:0] DEBUG_MP_MR_RDATA;
output [16:0] DEBUG_MP_MR_RDATACONTROL;
output [31:0] DEBUG_MP_MR_WDATA;
output [6:0] DEBUG_MP_MR_WDATACONTROL;
axi_interconnect
#(
.C_BASEFAMILY ( "zynq" ),
.C_NUM_SLAVE_SLOTS ( 1 ),
.C_NUM_MASTER_SLOTS ( 6 ),
.C_AXI_ID_WIDTH ( 12 ),
.C_AXI_ADDR_WIDTH ( 32 ),
.C_AXI_DATA_MAX_WIDTH ( 32 ),
.C_S_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 ),
.C_M_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 ),
.C_INTERCONNECT_DATA_WIDTH ( 32 ),
.C_S_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ),
.C_M_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000200000002000000020000000200000002 ),
.C_M_AXI_BASE_ADDR ( 16384'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076800000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000043000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040400000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041240000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041220000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000 ),
.C_M_AXI_HIGH_ADDR ( 16384'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007680ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004300ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004040ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004124ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004122ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff ),
.C_S_AXI_BASE_ID ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_THREAD_ID_WIDTH ( 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c ),
.C_S_AXI_IS_INTERCONNECT ( 16'b0000000000000000 ),
.C_S_AXI_ACLK_RATIO ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100 ),
.C_S_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_M_AXI_ACLK_RATIO ( 512'h0000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e10005f5e10005f5e10005f5e10005f5e100 ),
.C_M_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_INTERCONNECT_ACLK_RATIO ( 100000000 ),
.C_S_AXI_SUPPORTS_WRITE ( 16'b1111111111111111 ),
.C_S_AXI_SUPPORTS_READ ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_WRITE ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_READ ( 16'b1111111111111111 ),
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ),
.C_AXI_AWUSER_WIDTH ( 1 ),
.C_AXI_ARUSER_WIDTH ( 1 ),
.C_AXI_WUSER_WIDTH ( 1 ),
.C_AXI_RUSER_WIDTH ( 1 ),
.C_AXI_BUSER_WIDTH ( 1 ),
.C_AXI_CONNECTIVITY ( 512'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ),
.C_S_AXI_SINGLE_THREAD ( 16'b0000000000000000 ),
.C_M_AXI_SUPPORTS_REORDERING ( 16'b1111111111111111 ),
.C_S_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111111110 ),
.C_M_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008 ),
.C_S_AXI_READ_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008 ),
.C_M_AXI_WRITE_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_M_AXI_READ_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_S_AXI_ARB_PRIORITY ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_SECURE ( 16'b0000000000000000 ),
.C_S_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_INTERCONNECT_R_REGISTER ( 0 ),
.C_INTERCONNECT_CONNECTIVITY_MODE ( 0 ),
.C_USE_CTRL_PORT ( 0 ),
.C_USE_INTERRUPT ( 1 ),
.C_RANGE_CHECK ( 1 ),
.C_S_AXI_CTRL_ADDR_WIDTH ( 32 ),
.C_S_AXI_CTRL_DATA_WIDTH ( 32 ),
.C_DEBUG ( 0 ),
.C_S_AXI_DEBUG_SLOT ( 0 ),
.C_M_AXI_DEBUG_SLOT ( 0 ),
.C_MAX_DEBUG_THREADS ( 1 )
)
axi4lite_0 (
.INTERCONNECT_ACLK ( INTERCONNECT_ACLK ),
.INTERCONNECT_ARESETN ( INTERCONNECT_ARESETN ),
.S_AXI_ARESET_OUT_N ( S_AXI_ARESET_OUT_N ),
.M_AXI_ARESET_OUT_N ( M_AXI_ARESET_OUT_N ),
.IRQ ( IRQ ),
.S_AXI_ACLK ( S_AXI_ACLK ),
.S_AXI_AWID ( S_AXI_AWID ),
.S_AXI_AWADDR ( S_AXI_AWADDR ),
.S_AXI_AWLEN ( S_AXI_AWLEN ),
.S_AXI_AWSIZE ( S_AXI_AWSIZE ),
.S_AXI_AWBURST ( S_AXI_AWBURST ),
.S_AXI_AWLOCK ( S_AXI_AWLOCK ),
.S_AXI_AWCACHE ( S_AXI_AWCACHE ),
.S_AXI_AWPROT ( S_AXI_AWPROT ),
.S_AXI_AWQOS ( S_AXI_AWQOS ),
.S_AXI_AWUSER ( S_AXI_AWUSER ),
.S_AXI_AWVALID ( S_AXI_AWVALID ),
.S_AXI_AWREADY ( S_AXI_AWREADY ),
.S_AXI_WID ( S_AXI_WID ),
.S_AXI_WDATA ( S_AXI_WDATA ),
.S_AXI_WSTRB ( S_AXI_WSTRB ),
.S_AXI_WLAST ( S_AXI_WLAST ),
.S_AXI_WUSER ( S_AXI_WUSER ),
.S_AXI_WVALID ( S_AXI_WVALID ),
.S_AXI_WREADY ( S_AXI_WREADY ),
.S_AXI_BID ( S_AXI_BID ),
.S_AXI_BRESP ( S_AXI_BRESP ),
.S_AXI_BUSER ( S_AXI_BUSER ),
.S_AXI_BVALID ( S_AXI_BVALID ),
.S_AXI_BREADY ( S_AXI_BREADY ),
.S_AXI_ARID ( S_AXI_ARID ),
.S_AXI_ARADDR ( S_AXI_ARADDR ),
.S_AXI_ARLEN ( S_AXI_ARLEN ),
.S_AXI_ARSIZE ( S_AXI_ARSIZE ),
.S_AXI_ARBURST ( S_AXI_ARBURST ),
.S_AXI_ARLOCK ( S_AXI_ARLOCK ),
.S_AXI_ARCACHE ( S_AXI_ARCACHE ),
.S_AXI_ARPROT ( S_AXI_ARPROT ),
.S_AXI_ARQOS ( S_AXI_ARQOS ),
.S_AXI_ARUSER ( S_AXI_ARUSER ),
.S_AXI_ARVALID ( S_AXI_ARVALID ),
.S_AXI_ARREADY ( S_AXI_ARREADY ),
.S_AXI_RID ( S_AXI_RID ),
.S_AXI_RDATA ( S_AXI_RDATA ),
.S_AXI_RRESP ( S_AXI_RRESP ),
.S_AXI_RLAST ( S_AXI_RLAST ),
.S_AXI_RUSER ( S_AXI_RUSER ),
.S_AXI_RVALID ( S_AXI_RVALID ),
.S_AXI_RREADY ( S_AXI_RREADY ),
.M_AXI_ACLK ( M_AXI_ACLK ),
.M_AXI_AWID ( M_AXI_AWID ),
.M_AXI_AWADDR ( M_AXI_AWADDR ),
.M_AXI_AWLEN ( M_AXI_AWLEN ),
.M_AXI_AWSIZE ( M_AXI_AWSIZE ),
.M_AXI_AWBURST ( M_AXI_AWBURST ),
.M_AXI_AWLOCK ( M_AXI_AWLOCK ),
.M_AXI_AWCACHE ( M_AXI_AWCACHE ),
.M_AXI_AWPROT ( M_AXI_AWPROT ),
.M_AXI_AWREGION ( M_AXI_AWREGION ),
.M_AXI_AWQOS ( M_AXI_AWQOS ),
.M_AXI_AWUSER ( M_AXI_AWUSER ),
.M_AXI_AWVALID ( M_AXI_AWVALID ),
.M_AXI_AWREADY ( M_AXI_AWREADY ),
.M_AXI_WID ( M_AXI_WID ),
.M_AXI_WDATA ( M_AXI_WDATA ),
.M_AXI_WSTRB ( M_AXI_WSTRB ),
.M_AXI_WLAST ( M_AXI_WLAST ),
.M_AXI_WUSER ( M_AXI_WUSER ),
.M_AXI_WVALID ( M_AXI_WVALID ),
.M_AXI_WREADY ( M_AXI_WREADY ),
.M_AXI_BID ( M_AXI_BID ),
.M_AXI_BRESP ( M_AXI_BRESP ),
.M_AXI_BUSER ( M_AXI_BUSER ),
.M_AXI_BVALID ( M_AXI_BVALID ),
.M_AXI_BREADY ( M_AXI_BREADY ),
.M_AXI_ARID ( M_AXI_ARID ),
.M_AXI_ARADDR ( M_AXI_ARADDR ),
.M_AXI_ARLEN ( M_AXI_ARLEN ),
.M_AXI_ARSIZE ( M_AXI_ARSIZE ),
.M_AXI_ARBURST ( M_AXI_ARBURST ),
.M_AXI_ARLOCK ( M_AXI_ARLOCK ),
.M_AXI_ARCACHE ( M_AXI_ARCACHE ),
.M_AXI_ARPROT ( M_AXI_ARPROT ),
.M_AXI_ARREGION ( M_AXI_ARREGION ),
.M_AXI_ARQOS ( M_AXI_ARQOS ),
.M_AXI_ARUSER ( M_AXI_ARUSER ),
.M_AXI_ARVALID ( M_AXI_ARVALID ),
.M_AXI_ARREADY ( M_AXI_ARREADY ),
.M_AXI_RID ( M_AXI_RID ),
.M_AXI_RDATA ( M_AXI_RDATA ),
.M_AXI_RRESP ( M_AXI_RRESP ),
.M_AXI_RLAST ( M_AXI_RLAST ),
.M_AXI_RUSER ( M_AXI_RUSER ),
.M_AXI_RVALID ( M_AXI_RVALID ),
.M_AXI_RREADY ( M_AXI_RREADY ),
.S_AXI_CTRL_AWADDR ( S_AXI_CTRL_AWADDR ),
.S_AXI_CTRL_AWVALID ( S_AXI_CTRL_AWVALID ),
.S_AXI_CTRL_AWREADY ( S_AXI_CTRL_AWREADY ),
.S_AXI_CTRL_WDATA ( S_AXI_CTRL_WDATA ),
.S_AXI_CTRL_WVALID ( S_AXI_CTRL_WVALID ),
.S_AXI_CTRL_WREADY ( S_AXI_CTRL_WREADY ),
.S_AXI_CTRL_BRESP ( S_AXI_CTRL_BRESP ),
.S_AXI_CTRL_BVALID ( S_AXI_CTRL_BVALID ),
.S_AXI_CTRL_BREADY ( S_AXI_CTRL_BREADY ),
.S_AXI_CTRL_ARADDR ( S_AXI_CTRL_ARADDR ),
.S_AXI_CTRL_ARVALID ( S_AXI_CTRL_ARVALID ),
.S_AXI_CTRL_ARREADY ( S_AXI_CTRL_ARREADY ),
.S_AXI_CTRL_RDATA ( S_AXI_CTRL_RDATA ),
.S_AXI_CTRL_RRESP ( S_AXI_CTRL_RRESP ),
.S_AXI_CTRL_RVALID ( S_AXI_CTRL_RVALID ),
.S_AXI_CTRL_RREADY ( S_AXI_CTRL_RREADY ),
.INTERCONNECT_ARESET_OUT_N ( INTERCONNECT_ARESET_OUT_N ),
.DEBUG_AW_TRANS_SEQ ( DEBUG_AW_TRANS_SEQ ),
.DEBUG_AW_ARB_GRANT ( DEBUG_AW_ARB_GRANT ),
.DEBUG_AR_TRANS_SEQ ( DEBUG_AR_TRANS_SEQ ),
.DEBUG_AR_ARB_GRANT ( DEBUG_AR_ARB_GRANT ),
.DEBUG_AW_TRANS_QUAL ( DEBUG_AW_TRANS_QUAL ),
.DEBUG_AW_ACCEPT_CNT ( DEBUG_AW_ACCEPT_CNT ),
.DEBUG_AW_ACTIVE_THREAD ( DEBUG_AW_ACTIVE_THREAD ),
.DEBUG_AW_ACTIVE_TARGET ( DEBUG_AW_ACTIVE_TARGET ),
.DEBUG_AW_ACTIVE_REGION ( DEBUG_AW_ACTIVE_REGION ),
.DEBUG_AW_ERROR ( DEBUG_AW_ERROR ),
.DEBUG_AW_TARGET ( DEBUG_AW_TARGET ),
.DEBUG_AR_TRANS_QUAL ( DEBUG_AR_TRANS_QUAL ),
.DEBUG_AR_ACCEPT_CNT ( DEBUG_AR_ACCEPT_CNT ),
.DEBUG_AR_ACTIVE_THREAD ( DEBUG_AR_ACTIVE_THREAD ),
.DEBUG_AR_ACTIVE_TARGET ( DEBUG_AR_ACTIVE_TARGET ),
.DEBUG_AR_ACTIVE_REGION ( DEBUG_AR_ACTIVE_REGION ),
.DEBUG_AR_ERROR ( DEBUG_AR_ERROR ),
.DEBUG_AR_TARGET ( DEBUG_AR_TARGET ),
.DEBUG_B_TRANS_SEQ ( DEBUG_B_TRANS_SEQ ),
.DEBUG_R_BEAT_CNT ( DEBUG_R_BEAT_CNT ),
.DEBUG_R_TRANS_SEQ ( DEBUG_R_TRANS_SEQ ),
.DEBUG_AW_ISSUING_CNT ( DEBUG_AW_ISSUING_CNT ),
.DEBUG_AR_ISSUING_CNT ( DEBUG_AR_ISSUING_CNT ),
.DEBUG_W_BEAT_CNT ( DEBUG_W_BEAT_CNT ),
.DEBUG_W_TRANS_SEQ ( DEBUG_W_TRANS_SEQ ),
.DEBUG_BID_TARGET ( DEBUG_BID_TARGET ),
.DEBUG_BID_ERROR ( DEBUG_BID_ERROR ),
.DEBUG_RID_TARGET ( DEBUG_RID_TARGET ),
.DEBUG_RID_ERROR ( DEBUG_RID_ERROR ),
.DEBUG_SR_SC_ARADDR ( DEBUG_SR_SC_ARADDR ),
.DEBUG_SR_SC_ARADDRCONTROL ( DEBUG_SR_SC_ARADDRCONTROL ),
.DEBUG_SR_SC_AWADDR ( DEBUG_SR_SC_AWADDR ),
.DEBUG_SR_SC_AWADDRCONTROL ( DEBUG_SR_SC_AWADDRCONTROL ),
.DEBUG_SR_SC_BRESP ( DEBUG_SR_SC_BRESP ),
.DEBUG_SR_SC_RDATA ( DEBUG_SR_SC_RDATA ),
.DEBUG_SR_SC_RDATACONTROL ( DEBUG_SR_SC_RDATACONTROL ),
.DEBUG_SR_SC_WDATA ( DEBUG_SR_SC_WDATA ),
.DEBUG_SR_SC_WDATACONTROL ( DEBUG_SR_SC_WDATACONTROL ),
.DEBUG_SC_SF_ARADDR ( DEBUG_SC_SF_ARADDR ),
.DEBUG_SC_SF_ARADDRCONTROL ( DEBUG_SC_SF_ARADDRCONTROL ),
.DEBUG_SC_SF_AWADDR ( DEBUG_SC_SF_AWADDR ),
.DEBUG_SC_SF_AWADDRCONTROL ( DEBUG_SC_SF_AWADDRCONTROL ),
.DEBUG_SC_SF_BRESP ( DEBUG_SC_SF_BRESP ),
.DEBUG_SC_SF_RDATA ( DEBUG_SC_SF_RDATA ),
.DEBUG_SC_SF_RDATACONTROL ( DEBUG_SC_SF_RDATACONTROL ),
.DEBUG_SC_SF_WDATA ( DEBUG_SC_SF_WDATA ),
.DEBUG_SC_SF_WDATACONTROL ( DEBUG_SC_SF_WDATACONTROL ),
.DEBUG_SF_CB_ARADDR ( DEBUG_SF_CB_ARADDR ),
.DEBUG_SF_CB_ARADDRCONTROL ( DEBUG_SF_CB_ARADDRCONTROL ),
.DEBUG_SF_CB_AWADDR ( DEBUG_SF_CB_AWADDR ),
.DEBUG_SF_CB_AWADDRCONTROL ( DEBUG_SF_CB_AWADDRCONTROL ),
.DEBUG_SF_CB_BRESP ( DEBUG_SF_CB_BRESP ),
.DEBUG_SF_CB_RDATA ( DEBUG_SF_CB_RDATA ),
.DEBUG_SF_CB_RDATACONTROL ( DEBUG_SF_CB_RDATACONTROL ),
.DEBUG_SF_CB_WDATA ( DEBUG_SF_CB_WDATA ),
.DEBUG_SF_CB_WDATACONTROL ( DEBUG_SF_CB_WDATACONTROL ),
.DEBUG_CB_MF_ARADDR ( DEBUG_CB_MF_ARADDR ),
.DEBUG_CB_MF_ARADDRCONTROL ( DEBUG_CB_MF_ARADDRCONTROL ),
.DEBUG_CB_MF_AWADDR ( DEBUG_CB_MF_AWADDR ),
.DEBUG_CB_MF_AWADDRCONTROL ( DEBUG_CB_MF_AWADDRCONTROL ),
.DEBUG_CB_MF_BRESP ( DEBUG_CB_MF_BRESP ),
.DEBUG_CB_MF_RDATA ( DEBUG_CB_MF_RDATA ),
.DEBUG_CB_MF_RDATACONTROL ( DEBUG_CB_MF_RDATACONTROL ),
.DEBUG_CB_MF_WDATA ( DEBUG_CB_MF_WDATA ),
.DEBUG_CB_MF_WDATACONTROL ( DEBUG_CB_MF_WDATACONTROL ),
.DEBUG_MF_MC_ARADDR ( DEBUG_MF_MC_ARADDR ),
.DEBUG_MF_MC_ARADDRCONTROL ( DEBUG_MF_MC_ARADDRCONTROL ),
.DEBUG_MF_MC_AWADDR ( DEBUG_MF_MC_AWADDR ),
.DEBUG_MF_MC_AWADDRCONTROL ( DEBUG_MF_MC_AWADDRCONTROL ),
.DEBUG_MF_MC_BRESP ( DEBUG_MF_MC_BRESP ),
.DEBUG_MF_MC_RDATA ( DEBUG_MF_MC_RDATA ),
.DEBUG_MF_MC_RDATACONTROL ( DEBUG_MF_MC_RDATACONTROL ),
.DEBUG_MF_MC_WDATA ( DEBUG_MF_MC_WDATA ),
.DEBUG_MF_MC_WDATACONTROL ( DEBUG_MF_MC_WDATACONTROL ),
.DEBUG_MC_MP_ARADDR ( DEBUG_MC_MP_ARADDR ),
.DEBUG_MC_MP_ARADDRCONTROL ( DEBUG_MC_MP_ARADDRCONTROL ),
.DEBUG_MC_MP_AWADDR ( DEBUG_MC_MP_AWADDR ),
.DEBUG_MC_MP_AWADDRCONTROL ( DEBUG_MC_MP_AWADDRCONTROL ),
.DEBUG_MC_MP_BRESP ( DEBUG_MC_MP_BRESP ),
.DEBUG_MC_MP_RDATA ( DEBUG_MC_MP_RDATA ),
.DEBUG_MC_MP_RDATACONTROL ( DEBUG_MC_MP_RDATACONTROL ),
.DEBUG_MC_MP_WDATA ( DEBUG_MC_MP_WDATA ),
.DEBUG_MC_MP_WDATACONTROL ( DEBUG_MC_MP_WDATACONTROL ),
.DEBUG_MP_MR_ARADDR ( DEBUG_MP_MR_ARADDR ),
.DEBUG_MP_MR_ARADDRCONTROL ( DEBUG_MP_MR_ARADDRCONTROL ),
.DEBUG_MP_MR_AWADDR ( DEBUG_MP_MR_AWADDR ),
.DEBUG_MP_MR_AWADDRCONTROL ( DEBUG_MP_MR_AWADDRCONTROL ),
.DEBUG_MP_MR_BRESP ( DEBUG_MP_MR_BRESP ),
.DEBUG_MP_MR_RDATA ( DEBUG_MP_MR_RDATA ),
.DEBUG_MP_MR_RDATACONTROL ( DEBUG_MP_MR_RDATACONTROL ),
.DEBUG_MP_MR_WDATA ( DEBUG_MP_MR_WDATA ),
.DEBUG_MP_MR_WDATACONTROL ( DEBUG_MP_MR_WDATACONTROL )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V |
/*
ORSoC GFX accelerator core
Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
Bresenham line algarithm
This file is part of orgfx.
orgfx is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
orgfx is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with orgfx. If not, see <http://www.gnu.org/licenses/>.
*/
// trigger on high
module bresenham_line(clk_i, rst_i,
pixel0_x_i, pixel0_y_i, pixel1_x_i, pixel1_y_i,
draw_line_i, read_pixel_i,
busy_o, x_major_o, major_o, minor_o, valid_o
);
parameter point_width = 16;
parameter subpixel_width = 16;
input clk_i;
input rst_i;
input signed [point_width-1:-subpixel_width] pixel0_x_i;
input signed [point_width-1:-subpixel_width] pixel1_x_i;
input signed [point_width-1:-subpixel_width] pixel0_y_i;
input signed [point_width-1:-subpixel_width] pixel1_y_i;
input draw_line_i;
input read_pixel_i;
output reg busy_o;
output reg valid_o;
output reg signed [point_width-1:0] major_o;
output reg signed [point_width-1:0] minor_o;
//line drawing reg & wires
reg [point_width-1:-subpixel_width] xdiff; // dx
reg [point_width-1:-subpixel_width] ydiff; // dy
output reg x_major_o; // if x is the major axis (for each x, y changes less then x)
reg signed [point_width-1:-subpixel_width] left_pixel_x; // this is the left most pixel of the two input pixels
reg signed [point_width-1:-subpixel_width] left_pixel_y;
reg signed [point_width-1:-subpixel_width] right_pixel_x; // this is the right most pixel of the two input pixels
reg signed [point_width-1:-subpixel_width] right_pixel_y;
reg [point_width-1:-subpixel_width] delta_major; // if x is major this value is xdiff, else ydiff
reg [point_width-1:-subpixel_width] delta_minor; // if x is minor this value is xdiff, else ydiff
reg minor_slope_positive; // true if slope is in first quadrant
reg signed [point_width-1:0] major_goal;
reg signed [2*point_width-1:-subpixel_width] eps;
wire signed [2*point_width-1:-subpixel_width] eps_delta_minor;
wire done;
// State machine
reg [2:0] state;
parameter wait_state = 0, line_prep_state = 1, line_state = 2, raster_state = 3;
assign eps_delta_minor = eps+delta_minor;
always@(posedge clk_i or posedge rst_i)
if(rst_i)
state <= wait_state;
else
case (state)
wait_state:
if(draw_line_i)
state <= line_prep_state; // if request for drawing a line, go to line drawing state
line_prep_state:
state <= line_state;
line_state:
state <= raster_state;
raster_state:
if(!busy_o)
state <= wait_state;
endcase
wire is_inside_screen = (minor_o >= 0) & (major_o >= -1);
reg previously_outside_screen;
always@(posedge clk_i or posedge rst_i)
begin
if(rst_i)
begin
minor_slope_positive <= 1'b0;
eps <= 1'b0;
major_o <= 1'b0;
minor_o <= 1'b0;
busy_o <= 1'b0;
major_goal <= 1'b0;
x_major_o <= 1'b0;
delta_minor <= 1'b0;
delta_major <= 1'b0;
valid_o <= 1'b0;
left_pixel_x <= 1'b0;
left_pixel_y <= 1'b0;
right_pixel_x <= 1'b0;
right_pixel_y <= 1'b0;
xdiff <= 1'b0;
ydiff <= 1'b0;
previously_outside_screen <= 1'b0;
end
else
begin
// ## new magic
// Start a raster line operation
case (state)
wait_state:
if(draw_line_i)
begin
// set busy!
previously_outside_screen <= 1'b0;
busy_o <= 1'b1;
valid_o <= 1'b0;
// check diff in x and y
if(pixel0_x_i > pixel1_x_i)
begin
xdiff <= pixel0_x_i - pixel1_x_i;
// pixel0 is greater then pixel1, pixel1 is left of pixel0.
left_pixel_x <= pixel1_x_i;
left_pixel_y <= pixel1_y_i;
right_pixel_x <= pixel0_x_i;
right_pixel_y <= pixel0_y_i;
// check diff for y axis (swapped)
if(pixel1_y_i > pixel0_y_i)
begin
ydiff <= pixel1_y_i - pixel0_y_i;
minor_slope_positive <= 1'b0;
end
else
begin
ydiff <= pixel0_y_i - pixel1_y_i;
minor_slope_positive <= 1'b1;
end
end
else
begin
xdiff <= pixel1_x_i - pixel0_x_i;
// pixel1 is greater then pixel0, pixel0 is left of pixel1.
left_pixel_x <= pixel0_x_i;
left_pixel_y <= pixel0_y_i;
right_pixel_x <= pixel1_x_i;
right_pixel_y <= pixel1_y_i;
// check diff for y axis
if(pixel0_y_i > pixel1_y_i)
begin
ydiff <= pixel0_y_i - pixel1_y_i;
minor_slope_positive <= 1'b0; // the slope is "\" negative
end
else
begin
ydiff <= pixel1_y_i - pixel0_y_i;
minor_slope_positive <= 1'b1; // the slope is "/" positive
end
end
end
// Prepare linedrawing
line_prep_state:
begin
if(xdiff > ydiff)
begin // x major axis
x_major_o <= 1'b1;
delta_major <= xdiff;
delta_minor <= ydiff;
end
else
begin // y major axis
x_major_o <= 1'b0;
delta_major <= ydiff;
delta_minor <= xdiff;
end
end
// Rasterize a line between dest_pixel0 and dest_pixel1 (rasterize = generate the pixels)
line_state:
begin
if(x_major_o)
begin
major_o <= $signed(left_pixel_x[point_width-1:0]);
minor_o <= $signed(left_pixel_y[point_width-1:0]);
major_goal <= $signed(right_pixel_x[point_width-1:0]);
end
else
begin
major_o <= $signed(left_pixel_y[point_width-1:0]);
minor_o <= $signed(left_pixel_x[point_width-1:0]);
major_goal <= $signed(right_pixel_y[point_width-1:0]);
end
eps <= 1'b0;
busy_o <= 1'b1;
valid_o <= (left_pixel_x >= 0 && left_pixel_y >= 0);
previously_outside_screen <= ~(left_pixel_x >= 0 && left_pixel_y >= 0);
end
raster_state:
begin
// pixels is now valid!
valid_o <= (previously_outside_screen | read_pixel_i) & is_inside_screen;
previously_outside_screen <= ~is_inside_screen;
//bresenham magic
if((read_pixel_i & is_inside_screen) | previously_outside_screen)
begin
if((major_o < major_goal) & minor_slope_positive & x_major_o & busy_o) // if we are between endpoints and want to draw a line, continue
begin
major_o <= major_o + 1'b1; // major axis increeses
if((eps_delta_minor*2) >= $signed(delta_major))
begin
eps <= eps_delta_minor - delta_major;
minor_o <= minor_o + 1'b1; // minor axis increeses
end
else
eps <= eps_delta_minor;
end
else if((major_o < major_goal) & minor_slope_positive & !x_major_o & busy_o)
begin
major_o <= major_o + 1'b1; // major axis increeses
if((eps_delta_minor*2) >= $signed(delta_major))
begin
eps <= eps_delta_minor - delta_major;
minor_o <= minor_o + 1'b1; // minor axis increeses
end
else
eps <= eps_delta_minor;
end
else if((major_o > major_goal) & !minor_slope_positive & !x_major_o & busy_o)// the slope is negative
begin
major_o <= major_o - 1'b1; // major axis decreeses
if((eps_delta_minor*2) >= $signed(delta_major))
begin
eps <= eps_delta_minor - delta_major;
minor_o <= minor_o + 1'b1; // minor axis increeses
end
else
eps <= eps_delta_minor;
end
else if((major_o < major_goal) & !minor_slope_positive & x_major_o & busy_o)// special to fix ocant 4 & 8.
begin
major_o <= major_o + 1'b1; // major axis increeses
if((eps_delta_minor*2) >= $signed(delta_major))
begin
eps <= eps_delta_minor - delta_major;
minor_o <= minor_o - 1'b1; // minor axis decreeses
end
else
eps <= eps_delta_minor;
end
// if we have reached tho goal and are busy, stop being busy.
else if(busy_o)
begin
busy_o <= 1'b0;
valid_o <= 1'b0;
end
end
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BO_4_V
`define SKY130_FD_SC_HS__A21BO_4_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BO_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/02/2013 08:41:31 PM
// Design Name:
// Module Name: saxis_controller
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module saxis_controller # (
parameter TCQ = 1,
parameter S_AXIS_TDATA_WIDTH = 64,
parameter OUTSTANDING_READS = 5
) (
input axis_clk,
input axis_aresetn,
input [S_AXIS_TDATA_WIDTH-1:0] s_axis_cq_tdata,
input [84:0] s_axis_cq_tuser,
input s_axis_cq_tlast,
input [S_AXIS_TDATA_WIDTH/32-1:0] s_axis_cq_tkeep,
input s_axis_cq_tvalid,
output [21:0] s_axis_cq_tready,
//TLP Information to AXI
output mem_req_valid,
input mem_req_ready,
output [2:0] mem_req_bar_hit,
output [31:0] mem_req_pcie_address,
output [3:0] mem_req_byte_enable,
output mem_req_write_readn,
output mem_req_phys_func,
output [31:0] mem_req_write_data,
//Memory Reads Records
output tag_mang_write_en,
output [2:0] tag_mang_tc_wr,
output [2:0] tag_mang_attr_wr,
output [15:0] tag_mang_requester_id_wr,
output [6:0] tag_mang_lower_addr_wr,
output tag_mang_completer_func_wr,
output [7:0] tag_mang_tag_wr,
output [3:0] tag_mang_first_be_wr,
output reg completion_ur_req,
output [7:0] completion_ur_tag,
output [6:0] completion_ur_lower_addr,
output [3:0] completion_ur_first_be,
output [15:0] completion_ur_requester_id,
output [2:0] completion_ur_tc,
output [2:0] completion_ur_attr,
input completion_ur_done
);
localparam IDLE = 7'b0000001;
localparam DW2_PROCESS_64 = 7'b0000010;
localparam READ_PROCESS_64 = 7'b0000100;
localparam READ_PROCESS_128 = 7'b0000010;
localparam READ_PROCESS_256 = 7'b0000010;
localparam WRITE_DATA_64 = 7'b0001000;
localparam WRITE_DATA_128 = 7'b0000100;
localparam WRITE_DATA_256 = 7'b0000100;
localparam HOLD_VALID = 7'b0010000;
localparam COMPLETION_UR = 7'b0100000;
localparam WAIT_FOR_LAST = 7'b1000000;
reg [6:0] saxis_sm = IDLE;
reg [6:0] saxis_sm_r = IDLE;
reg [255:0] s_axis_cq_tdata_wide_r;
reg [3:0] first_be_r;
reg mem_req_write_readn_r;
reg mem_read_pulse;
reg s_axis_cq_tready_r;
reg mem_req_valid_r;
always @(posedge axis_clk)
saxis_sm_r <= saxis_sm;
generate
if ( S_AXIS_TDATA_WIDTH == 64 ) begin: S_AXIS_TDATA_WIDTH_64
always @(posedge axis_clk)
if (!axis_aresetn) begin
saxis_sm <= #TCQ IDLE;
mem_read_pulse <= #TCQ 1'b0;
s_axis_cq_tready_r <= #TCQ 1'b0;
mem_req_valid_r <= #TCQ 1'b0;
completion_ur_req <= #TCQ 1'b0;
end
else
case (saxis_sm)
IDLE : begin
if (s_axis_cq_tvalid & s_axis_cq_tready[0] ) begin
saxis_sm <= #TCQ DW2_PROCESS_64;
s_axis_cq_tdata_wide_r[63:0] <= #TCQ s_axis_cq_tdata[63:0];
first_be_r <= #TCQ s_axis_cq_tuser[3:0];
end
s_axis_cq_tready_r <= #TCQ 1'b1;
mem_req_valid_r <= #TCQ 1'b0;
end
DW2_PROCESS_64 : begin
if (s_axis_cq_tvalid & s_axis_cq_tready[0] ) begin
if ( s_axis_cq_tdata[14:11] == 4'h0 ) begin //If Memory Read
if ( s_axis_cq_tdata[10:0] == 11'd1 ) begin // Only 1DW Reads are Supported
saxis_sm <= #TCQ READ_PROCESS_64;
mem_req_write_readn_r <= #TCQ 1'b0;
mem_read_pulse <= #TCQ 1'b1;
mem_req_valid_r <= #TCQ 1'b1;
s_axis_cq_tready_r <= #TCQ 1'b0;
end else begin // Only 1DW packets are supported. Larger reads will get a completion with UR.
saxis_sm <= #TCQ COMPLETION_UR;
s_axis_cq_tready_r <= #TCQ 1'b0;
end
end else if ( (s_axis_cq_tdata[14:11] == 4'h1) ) begin //If Memory Write
if ( s_axis_cq_tdata[10:0] == 11'd1 ) begin // Only 1DW Reads are Supported
saxis_sm <= #TCQ WRITE_DATA_64;
mem_req_write_readn_r <= #TCQ 1'b1;
mem_req_valid_r <= #TCQ 1'b0;
end else begin // Only 1DW packets are supported. Larger packets are ignored.
if (s_axis_cq_tlast) begin
saxis_sm <= #TCQ IDLE;
end else begin
saxis_sm <= #TCQ WAIT_FOR_LAST;
end
end
end
s_axis_cq_tdata_wide_r[127:64] <= #TCQ s_axis_cq_tdata[63:0];
end
end
READ_PROCESS_64 : begin
if (mem_req_ready) begin
saxis_sm <= #TCQ IDLE;
s_axis_cq_tready_r <= #TCQ 1'b1;
mem_req_valid_r <= #TCQ 1'b0;
end else begin
s_axis_cq_tready_r <= #TCQ 1'b0;
end
mem_read_pulse <= #TCQ 1'b0;
end
WRITE_DATA_64: begin
if (s_axis_cq_tvalid) begin
s_axis_cq_tdata_wide_r [159:128] = #TCQ s_axis_cq_tdata[31:0];
if (mem_req_ready) begin
saxis_sm <= #TCQ IDLE;
mem_req_valid_r <= #TCQ 1'b1;
s_axis_cq_tready_r <= #TCQ 1'b1;
end else begin
s_axis_cq_tready_r <= #TCQ 1'b0;
saxis_sm <= #TCQ HOLD_VALID;
mem_req_valid_r <= #TCQ 1'b1;
end
end
end
WAIT_FOR_LAST: begin
if (s_axis_cq_tlast) begin
saxis_sm <= #TCQ IDLE;
end
end
COMPLETION_UR: begin
if (completion_ur_done) begin
saxis_sm <= #TCQ IDLE;
completion_ur_req <= 1'b0;
end else begin
completion_ur_req <= 1'b1;
end
end
HOLD_VALID: begin
if (mem_req_ready) begin
saxis_sm <= #TCQ IDLE;
mem_req_valid_r <= #TCQ 1'b0;
s_axis_cq_tready_r <= #TCQ 1'b1;
end
end
default: begin // Fault Recovery
saxis_sm <= #TCQ IDLE;
end
endcase
end else if (S_AXIS_TDATA_WIDTH == 128) begin: S_AXIS_TDATA_WIDTH_128
always @(posedge axis_clk)
if (!axis_aresetn) begin
saxis_sm <= #TCQ IDLE;
mem_read_pulse <= #TCQ 1'b0;
s_axis_cq_tready_r <= #TCQ 1'b0;
mem_req_valid_r <= #TCQ 1'b0;
completion_ur_req <= #TCQ 1'b0;
end
else
case ( saxis_sm )
IDLE : begin
if ( s_axis_cq_tvalid & s_axis_cq_tready[0] & (s_axis_cq_tdata[78:75] == 4'h0) ) begin // If Memory Read
if ( s_axis_cq_tdata[10+64:0+64] == 11'd1 ) begin // Only 1DW Reads are Supported
saxis_sm <= #TCQ READ_PROCESS_128;
mem_req_write_readn_r <= #TCQ 1'b0;
mem_read_pulse <= #TCQ 1'b1;
mem_req_valid_r <= #TCQ 1'b1;
s_axis_cq_tdata_wide_r[127:0] <= #TCQ s_axis_cq_tdata[127:0];
first_be_r <= #TCQ s_axis_cq_tuser[3:0];
s_axis_cq_tready_r <= #TCQ 1'b0;
end else begin
s_axis_cq_tdata_wide_r[127:0] <= #TCQ s_axis_cq_tdata[127:0];
first_be_r <= #TCQ s_axis_cq_tuser[3:0];
saxis_sm <= #TCQ COMPLETION_UR;
s_axis_cq_tready_r <= #TCQ 1'b0;
end
end else if (s_axis_cq_tvalid & s_axis_cq_tready[0] & (s_axis_cq_tdata[78:75] == 4'h1)) begin // If Memory Write
if ( s_axis_cq_tdata[10+64:0+64] == 11'd1 ) begin // Only 1DW Writes are Supported
saxis_sm <= #TCQ WRITE_DATA_128;
mem_req_write_readn_r <= #TCQ 1'b1;
mem_req_valid_r <= #TCQ 1'b0;
s_axis_cq_tdata_wide_r[127:0] <= #TCQ s_axis_cq_tdata[127:0];
first_be_r <= #TCQ s_axis_cq_tuser[3:0];
s_axis_cq_tready_r <= #TCQ 1'b1;
end else begin
if (s_axis_cq_tlast) begin
saxis_sm <= #TCQ IDLE;
end else begin
saxis_sm <= #TCQ WAIT_FOR_LAST;
end
end
end else begin
s_axis_cq_tready_r <= #TCQ 1'b1;
end
end
READ_PROCESS_128 : begin
if (mem_req_ready) begin
saxis_sm <= #TCQ IDLE;
s_axis_cq_tready_r <= #TCQ 1'b1;
mem_req_valid_r <= #TCQ 1'b0;
end else begin
s_axis_cq_tready_r <= #TCQ 1'b0;
end
mem_read_pulse <= #TCQ 1'b0;
end
WRITE_DATA_128: begin
if (s_axis_cq_tvalid) begin
s_axis_cq_tdata_wide_r [159:128] = #TCQ s_axis_cq_tdata[31:0];
if (mem_req_ready) begin
saxis_sm <= #TCQ IDLE;
mem_req_valid_r <= #TCQ 1'b1;
s_axis_cq_tready_r <= #TCQ 1'b1;
end else begin
s_axis_cq_tready_r <= #TCQ 1'b0;
saxis_sm <= #TCQ HOLD_VALID;
mem_req_valid_r <= #TCQ 1'b1;
end
end
end
WAIT_FOR_LAST: begin
if ( s_axis_cq_tlast ) begin
saxis_sm <= #TCQ IDLE;
end
end
COMPLETION_UR: begin
if ( completion_ur_done ) begin
saxis_sm <= #TCQ IDLE;
completion_ur_req <= 1'b0;
end else begin
completion_ur_req <= 1'b1;
end
end
HOLD_VALID: begin
if (mem_req_ready) begin
saxis_sm <= #TCQ IDLE;
mem_req_valid_r <= #TCQ 1'b0;
s_axis_cq_tready_r <= #TCQ 1'b1;
end
end
default: begin // Fault Recovery
saxis_sm <= #TCQ IDLE;
end
endcase
end else if (S_AXIS_TDATA_WIDTH == 256) begin: S_AXIS_TDATA_WIDTH_256 // This is going to look similar to the 128-bit interface
always @(posedge axis_clk)
if (!axis_aresetn) begin
saxis_sm <= #TCQ IDLE;
mem_read_pulse <= #TCQ 1'b0;
s_axis_cq_tready_r <= #TCQ 1'b0;
mem_req_valid_r <= #TCQ 1'b0;
completion_ur_req <= #TCQ 1'b0;
end
else
case ( saxis_sm )
IDLE : begin
if ( s_axis_cq_tvalid & s_axis_cq_tready[0] & (s_axis_cq_tdata[78:75] == 4'h0) ) begin // If Memory Read
if ( s_axis_cq_tdata[10+64:0+64] == 11'd1 ) begin // Only 1DW Reads are Supported
saxis_sm <= #TCQ READ_PROCESS_256;
mem_req_write_readn_r <= #TCQ 1'b0;
mem_read_pulse <= #TCQ 1'b1;
mem_req_valid_r <= #TCQ 1'b1;
s_axis_cq_tdata_wide_r[127:0] <= #TCQ s_axis_cq_tdata[127:0];
first_be_r <= #TCQ s_axis_cq_tuser[3:0];
s_axis_cq_tready_r <= #TCQ 1'b0;
end else begin
s_axis_cq_tdata_wide_r[127:0] <= #TCQ s_axis_cq_tdata[127:0];
first_be_r <= #TCQ s_axis_cq_tuser[3:0];
saxis_sm <= #TCQ COMPLETION_UR;
s_axis_cq_tready_r <= #TCQ 1'b0;
end
end else if (s_axis_cq_tvalid & s_axis_cq_tready[0] & (s_axis_cq_tdata[78:75] == 4'h1)) begin // If Memory Write
if ( s_axis_cq_tdata[10+64:0+64] == 11'd1 ) begin // Only 1DW Writes are Supported
saxis_sm <= #TCQ WRITE_DATA_256;
mem_req_write_readn_r <= #TCQ 1'b1;
mem_req_valid_r <= #TCQ 1'b1;
s_axis_cq_tdata_wide_r[159:0] <= #TCQ s_axis_cq_tdata[159:0];
first_be_r <= #TCQ s_axis_cq_tuser[3:0];
s_axis_cq_tready_r <= #TCQ 1'b0;
end else begin
if (s_axis_cq_tlast) begin
saxis_sm <= #TCQ IDLE;
end else begin
saxis_sm <= #TCQ WAIT_FOR_LAST;
end
end
end else begin
s_axis_cq_tready_r <= #TCQ 1'b1;
end
end
READ_PROCESS_256 : begin
if (mem_req_ready) begin
saxis_sm <= #TCQ IDLE;
s_axis_cq_tready_r <= #TCQ 1'b1;
mem_req_valid_r <= #TCQ 1'b0;
end else begin
s_axis_cq_tready_r <= #TCQ 1'b0;
end
mem_read_pulse <= #TCQ 1'b0;
end
WRITE_DATA_256: begin
if (mem_req_ready) begin
saxis_sm <= #TCQ IDLE;
mem_req_valid_r <= #TCQ 1'b0;
s_axis_cq_tready_r <= #TCQ 1'b1;
end else begin
s_axis_cq_tready_r <= #TCQ 1'b0;
saxis_sm <= #TCQ HOLD_VALID;
mem_req_valid_r <= #TCQ 1'b1;
end
end
WAIT_FOR_LAST: begin
if ( s_axis_cq_tlast ) begin
saxis_sm <= #TCQ IDLE;
end
end
COMPLETION_UR: begin
if ( completion_ur_done ) begin
saxis_sm <= #TCQ IDLE;
completion_ur_req <= 1'b0;
end else begin
completion_ur_req <= 1'b1;
end
end
HOLD_VALID: begin
if (mem_req_ready) begin
saxis_sm <= #TCQ IDLE;
mem_req_valid_r <= #TCQ 1'b0;
s_axis_cq_tready_r <= #TCQ 1'b1;
end
end
default: begin // Fault Recovery
saxis_sm <= #TCQ IDLE;
end
endcase
end
endgenerate
assign mem_req_valid = mem_req_valid_r;
assign mem_req_bar_hit = s_axis_cq_tdata_wide_r[114:112];
assign mem_req_pcie_address = s_axis_cq_tdata_wide_r[31:0];
assign mem_req_byte_enable = first_be_r;
assign mem_req_write_readn = mem_req_write_readn_r;
assign mem_req_phys_func = s_axis_cq_tdata_wide_r[64];
assign mem_req_write_data = s_axis_cq_tdata_wide_r[159:128];
//Memory Reads Records
assign tag_mang_write_en = mem_read_pulse;
assign tag_mang_tc_wr = s_axis_cq_tdata_wide_r[123:121];
assign tag_mang_attr_wr = s_axis_cq_tdata_wide_r[126:124];
assign tag_mang_requester_id_wr = s_axis_cq_tdata_wide_r[95:80];
assign tag_mang_lower_addr_wr = s_axis_cq_tdata_wide_r[6:0];
assign tag_mang_completer_func_wr = s_axis_cq_tdata_wide_r[104];
assign tag_mang_tag_wr = s_axis_cq_tdata_wide_r[103:96];
assign tag_mang_first_be_wr = first_be_r;
assign completion_ur_tag = s_axis_cq_tdata_wide_r[103:96];
assign completion_ur_lower_addr = s_axis_cq_tdata_wide_r[6:0];
assign completion_ur_first_be = first_be_r;
assign completion_ur_requester_id = s_axis_cq_tdata_wide_r[95:80];
assign completion_ur_tc = s_axis_cq_tdata_wide_r[123:121];
assign completion_ur_attr = s_axis_cq_tdata_wide_r[126:124];
assign s_axis_cq_tready = {22{s_axis_cq_tready_r}};
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 10 01:23:39 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, Sgf_operation_RECURSIVE_EVEN1_left_N23,
Sgf_operation_RECURSIVE_EVEN1_left_N22,
Sgf_operation_RECURSIVE_EVEN1_left_N21,
Sgf_operation_RECURSIVE_EVEN1_left_N20,
Sgf_operation_RECURSIVE_EVEN1_left_N19,
Sgf_operation_RECURSIVE_EVEN1_left_N18,
Sgf_operation_RECURSIVE_EVEN1_left_N17,
Sgf_operation_RECURSIVE_EVEN1_left_N16,
Sgf_operation_RECURSIVE_EVEN1_left_N15,
Sgf_operation_RECURSIVE_EVEN1_left_N14,
Sgf_operation_RECURSIVE_EVEN1_left_N13,
Sgf_operation_RECURSIVE_EVEN1_left_N12,
Sgf_operation_RECURSIVE_EVEN1_left_N11,
Sgf_operation_RECURSIVE_EVEN1_left_N10,
Sgf_operation_RECURSIVE_EVEN1_left_N9,
Sgf_operation_RECURSIVE_EVEN1_left_N8,
Sgf_operation_RECURSIVE_EVEN1_left_N7,
Sgf_operation_RECURSIVE_EVEN1_left_N6,
Sgf_operation_RECURSIVE_EVEN1_left_N5,
Sgf_operation_RECURSIVE_EVEN1_left_N4,
Sgf_operation_RECURSIVE_EVEN1_left_N3,
Sgf_operation_RECURSIVE_EVEN1_left_N2,
Sgf_operation_RECURSIVE_EVEN1_left_N1,
Sgf_operation_RECURSIVE_EVEN1_left_N0,
Sgf_operation_RECURSIVE_EVEN1_middle_N25,
Sgf_operation_RECURSIVE_EVEN1_middle_N24,
Sgf_operation_RECURSIVE_EVEN1_middle_N23,
Sgf_operation_RECURSIVE_EVEN1_middle_N22,
Sgf_operation_RECURSIVE_EVEN1_middle_N21,
Sgf_operation_RECURSIVE_EVEN1_middle_N20,
Sgf_operation_RECURSIVE_EVEN1_middle_N19,
Sgf_operation_RECURSIVE_EVEN1_middle_N18,
Sgf_operation_RECURSIVE_EVEN1_middle_N17,
Sgf_operation_RECURSIVE_EVEN1_middle_N16,
Sgf_operation_RECURSIVE_EVEN1_middle_N15,
Sgf_operation_RECURSIVE_EVEN1_middle_N14,
Sgf_operation_RECURSIVE_EVEN1_middle_N13,
Sgf_operation_RECURSIVE_EVEN1_middle_N12,
Sgf_operation_RECURSIVE_EVEN1_middle_N11,
Sgf_operation_RECURSIVE_EVEN1_middle_N10,
Sgf_operation_RECURSIVE_EVEN1_middle_N9,
Sgf_operation_RECURSIVE_EVEN1_middle_N8,
Sgf_operation_RECURSIVE_EVEN1_middle_N7,
Sgf_operation_RECURSIVE_EVEN1_middle_N6,
Sgf_operation_RECURSIVE_EVEN1_middle_N5,
Sgf_operation_RECURSIVE_EVEN1_middle_N4,
Sgf_operation_RECURSIVE_EVEN1_middle_N3,
Sgf_operation_RECURSIVE_EVEN1_middle_N2,
Sgf_operation_RECURSIVE_EVEN1_middle_N1,
Sgf_operation_RECURSIVE_EVEN1_middle_N0,
Sgf_operation_RECURSIVE_EVEN1_right_N23,
Sgf_operation_RECURSIVE_EVEN1_right_N22,
Sgf_operation_RECURSIVE_EVEN1_right_N21,
Sgf_operation_RECURSIVE_EVEN1_right_N20,
Sgf_operation_RECURSIVE_EVEN1_right_N19,
Sgf_operation_RECURSIVE_EVEN1_right_N18,
Sgf_operation_RECURSIVE_EVEN1_right_N17,
Sgf_operation_RECURSIVE_EVEN1_right_N16,
Sgf_operation_RECURSIVE_EVEN1_right_N15,
Sgf_operation_RECURSIVE_EVEN1_right_N14,
Sgf_operation_RECURSIVE_EVEN1_right_N13,
Sgf_operation_RECURSIVE_EVEN1_right_N12,
Sgf_operation_RECURSIVE_EVEN1_right_N11,
Sgf_operation_RECURSIVE_EVEN1_right_N10,
Sgf_operation_RECURSIVE_EVEN1_right_N9,
Sgf_operation_RECURSIVE_EVEN1_right_N8,
Sgf_operation_RECURSIVE_EVEN1_right_N7,
Sgf_operation_RECURSIVE_EVEN1_right_N6,
Sgf_operation_RECURSIVE_EVEN1_right_N5,
Sgf_operation_RECURSIVE_EVEN1_right_N4,
Sgf_operation_RECURSIVE_EVEN1_right_N3,
Sgf_operation_RECURSIVE_EVEN1_right_N2,
Sgf_operation_RECURSIVE_EVEN1_right_N1,
Sgf_operation_RECURSIVE_EVEN1_right_N0, n167, n169, n170, n171, n172,
n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194,
n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205,
n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216,
n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227,
n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238,
n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249,
n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260,
n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271,
n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282,
n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370,
n371, n372, n373, n374, n375, n376, n377, n378, n379, n380,
DP_OP_111J144_123_4462_n252, DP_OP_111J144_123_4462_n251,
DP_OP_111J144_123_4462_n250, DP_OP_111J144_123_4462_n249,
DP_OP_111J144_123_4462_n248, DP_OP_111J144_123_4462_n247,
DP_OP_111J144_123_4462_n246, DP_OP_111J144_123_4462_n245,
DP_OP_111J144_123_4462_n240, DP_OP_111J144_123_4462_n236,
DP_OP_111J144_123_4462_n235, DP_OP_111J144_123_4462_n234,
DP_OP_111J144_123_4462_n233, DP_OP_111J144_123_4462_n232,
DP_OP_111J144_123_4462_n231, DP_OP_111J144_123_4462_n227,
DP_OP_111J144_123_4462_n223, DP_OP_111J144_123_4462_n219,
DP_OP_111J144_123_4462_n218, DP_OP_111J144_123_4462_n217,
DP_OP_111J144_123_4462_n216, DP_OP_111J144_123_4462_n215,
DP_OP_111J144_123_4462_n214, DP_OP_111J144_123_4462_n213,
DP_OP_111J144_123_4462_n212, DP_OP_111J144_123_4462_n210,
DP_OP_111J144_123_4462_n204, DP_OP_111J144_123_4462_n203,
DP_OP_111J144_123_4462_n202, DP_OP_111J144_123_4462_n200,
DP_OP_111J144_123_4462_n199, DP_OP_111J144_123_4462_n198,
DP_OP_111J144_123_4462_n197, DP_OP_111J144_123_4462_n196,
DP_OP_111J144_123_4462_n195, DP_OP_111J144_123_4462_n191,
DP_OP_111J144_123_4462_n188, DP_OP_111J144_123_4462_n187,
DP_OP_111J144_123_4462_n186, DP_OP_111J144_123_4462_n185,
DP_OP_111J144_123_4462_n184, DP_OP_111J144_123_4462_n183,
DP_OP_111J144_123_4462_n182, DP_OP_111J144_123_4462_n181,
DP_OP_111J144_123_4462_n180, DP_OP_111J144_123_4462_n179,
DP_OP_111J144_123_4462_n178, DP_OP_111J144_123_4462_n177,
DP_OP_111J144_123_4462_n176, DP_OP_111J144_123_4462_n175,
DP_OP_111J144_123_4462_n172, DP_OP_111J144_123_4462_n171,
DP_OP_111J144_123_4462_n170, DP_OP_111J144_123_4462_n169,
DP_OP_111J144_123_4462_n168, DP_OP_111J144_123_4462_n167,
DP_OP_111J144_123_4462_n166, DP_OP_111J144_123_4462_n165,
DP_OP_111J144_123_4462_n164, DP_OP_111J144_123_4462_n163,
DP_OP_111J144_123_4462_n162, DP_OP_111J144_123_4462_n156,
DP_OP_111J144_123_4462_n155, DP_OP_111J144_123_4462_n148,
DP_OP_111J144_123_4462_n145, DP_OP_111J144_123_4462_n144,
DP_OP_111J144_123_4462_n143, DP_OP_111J144_123_4462_n142,
DP_OP_111J144_123_4462_n140, DP_OP_111J144_123_4462_n139,
DP_OP_111J144_123_4462_n138, DP_OP_111J144_123_4462_n137,
DP_OP_111J144_123_4462_n135, DP_OP_111J144_123_4462_n134,
DP_OP_111J144_123_4462_n133, DP_OP_111J144_123_4462_n131,
DP_OP_111J144_123_4462_n130, DP_OP_111J144_123_4462_n129,
DP_OP_111J144_123_4462_n128, DP_OP_111J144_123_4462_n127,
DP_OP_111J144_123_4462_n126, DP_OP_111J144_123_4462_n125,
DP_OP_111J144_123_4462_n124, DP_OP_111J144_123_4462_n123,
DP_OP_111J144_123_4462_n122, DP_OP_111J144_123_4462_n121,
DP_OP_111J144_123_4462_n120, DP_OP_111J144_123_4462_n119,
DP_OP_111J144_123_4462_n117, DP_OP_111J144_123_4462_n116,
DP_OP_111J144_123_4462_n115, DP_OP_111J144_123_4462_n114,
DP_OP_111J144_123_4462_n113, DP_OP_111J144_123_4462_n112,
DP_OP_111J144_123_4462_n111, DP_OP_111J144_123_4462_n109,
DP_OP_111J144_123_4462_n108, DP_OP_111J144_123_4462_n107,
DP_OP_111J144_123_4462_n106, DP_OP_111J144_123_4462_n105,
DP_OP_111J144_123_4462_n104, DP_OP_111J144_123_4462_n103,
DP_OP_111J144_123_4462_n102, DP_OP_111J144_123_4462_n101,
DP_OP_111J144_123_4462_n100, DP_OP_111J144_123_4462_n99,
DP_OP_111J144_123_4462_n98, DP_OP_111J144_123_4462_n97,
DP_OP_111J144_123_4462_n96, DP_OP_111J144_123_4462_n94,
DP_OP_111J144_123_4462_n93, DP_OP_111J144_123_4462_n92,
DP_OP_111J144_123_4462_n91, DP_OP_111J144_123_4462_n90,
DP_OP_111J144_123_4462_n89, DP_OP_111J144_123_4462_n88,
DP_OP_111J144_123_4462_n87, DP_OP_111J144_123_4462_n84,
DP_OP_111J144_123_4462_n83, DP_OP_111J144_123_4462_n82,
DP_OP_111J144_123_4462_n81, DP_OP_111J144_123_4462_n80,
DP_OP_111J144_123_4462_n79, DP_OP_111J144_123_4462_n78,
DP_OP_111J144_123_4462_n77, DP_OP_111J144_123_4462_n76,
DP_OP_111J144_123_4462_n75, DP_OP_111J144_123_4462_n74,
DP_OP_111J144_123_4462_n73, DP_OP_111J144_123_4462_n72,
DP_OP_111J144_123_4462_n71, DP_OP_111J144_123_4462_n70,
DP_OP_111J144_123_4462_n69, DP_OP_111J144_123_4462_n68,
DP_OP_111J144_123_4462_n67, DP_OP_111J144_123_4462_n66,
DP_OP_111J144_123_4462_n65, DP_OP_111J144_123_4462_n64,
DP_OP_111J144_123_4462_n63, DP_OP_111J144_123_4462_n62,
DP_OP_111J144_123_4462_n61, DP_OP_111J144_123_4462_n60,
DP_OP_111J144_123_4462_n59, DP_OP_111J144_123_4462_n58,
DP_OP_111J144_123_4462_n57, DP_OP_111J144_123_4462_n56,
DP_OP_111J144_123_4462_n55, DP_OP_111J144_123_4462_n52,
DP_OP_111J144_123_4462_n51, DP_OP_111J144_123_4462_n50,
DP_OP_111J144_123_4462_n49, DP_OP_111J144_123_4462_n48,
DP_OP_111J144_123_4462_n47, DP_OP_111J144_123_4462_n46,
DP_OP_111J144_123_4462_n45, DP_OP_111J144_123_4462_n44,
DP_OP_111J144_123_4462_n43, DP_OP_111J144_123_4462_n42,
DP_OP_111J144_123_4462_n41, DP_OP_111J144_123_4462_n40,
DP_OP_111J144_123_4462_n39, DP_OP_111J144_123_4462_n38,
DP_OP_111J144_123_4462_n37, DP_OP_111J144_123_4462_n36,
DP_OP_111J144_123_4462_n35, mult_x_55_n232, mult_x_55_n228,
mult_x_55_n220, mult_x_55_n219, mult_x_55_n216, mult_x_55_n215,
mult_x_55_n213, mult_x_55_n212, mult_x_55_n211, mult_x_55_n208,
mult_x_55_n207, mult_x_55_n206, mult_x_55_n205, mult_x_55_n204,
mult_x_55_n203, mult_x_55_n202, mult_x_55_n200, mult_x_55_n199,
mult_x_55_n198, mult_x_55_n197, mult_x_55_n196, mult_x_55_n195,
mult_x_55_n194, mult_x_55_n192, mult_x_55_n191, mult_x_55_n190,
mult_x_55_n189, mult_x_55_n186, mult_x_55_n185, mult_x_55_n183,
mult_x_55_n180, mult_x_55_n179, mult_x_55_n178, mult_x_55_n176,
mult_x_55_n175, mult_x_55_n174, mult_x_55_n173, mult_x_55_n170,
mult_x_55_n169, mult_x_55_n168, mult_x_55_n167, mult_x_55_n166,
mult_x_55_n165, mult_x_55_n164, mult_x_55_n163, mult_x_55_n162,
mult_x_55_n161, mult_x_55_n160, mult_x_55_n159, mult_x_55_n158,
mult_x_55_n157, mult_x_55_n151, mult_x_55_n149, mult_x_55_n136,
mult_x_55_n133, mult_x_55_n132, mult_x_55_n131, mult_x_55_n130,
mult_x_55_n129, mult_x_55_n128, mult_x_55_n127, mult_x_55_n126,
mult_x_55_n125, mult_x_55_n124, mult_x_55_n123, mult_x_55_n122,
mult_x_55_n121, mult_x_55_n120, mult_x_55_n119, mult_x_55_n118,
mult_x_55_n117, mult_x_55_n116, mult_x_55_n115, mult_x_55_n114,
mult_x_55_n113, mult_x_55_n112, mult_x_55_n111, mult_x_55_n110,
mult_x_55_n109, mult_x_55_n108, mult_x_55_n107, mult_x_55_n106,
mult_x_55_n105, mult_x_55_n104, mult_x_55_n103, mult_x_55_n102,
mult_x_55_n101, mult_x_55_n100, mult_x_55_n99, mult_x_55_n98,
mult_x_55_n97, mult_x_55_n96, mult_x_55_n95, mult_x_55_n94,
mult_x_55_n93, mult_x_55_n92, mult_x_55_n90, mult_x_55_n89,
mult_x_55_n88, mult_x_55_n87, mult_x_55_n86, mult_x_55_n85,
mult_x_55_n84, mult_x_55_n83, mult_x_55_n80, mult_x_55_n79,
mult_x_55_n78, mult_x_55_n77, mult_x_55_n76, mult_x_55_n75,
mult_x_55_n74, mult_x_55_n73, mult_x_55_n72, mult_x_55_n71,
mult_x_55_n70, mult_x_55_n69, mult_x_55_n68, mult_x_55_n67,
mult_x_55_n66, mult_x_55_n65, mult_x_55_n64, mult_x_55_n63,
mult_x_55_n62, mult_x_55_n61, mult_x_55_n60, mult_x_55_n59,
mult_x_55_n58, mult_x_55_n57, mult_x_55_n56, mult_x_55_n55,
mult_x_55_n54, mult_x_55_n53, mult_x_55_n52, mult_x_55_n51,
mult_x_55_n48, mult_x_55_n47, mult_x_55_n46, mult_x_55_n45,
mult_x_55_n44, mult_x_55_n43, mult_x_55_n42, mult_x_55_n41,
mult_x_55_n40, mult_x_55_n39, mult_x_55_n38, mult_x_55_n37,
mult_x_55_n36, mult_x_55_n35, mult_x_55_n34, mult_x_55_n33,
mult_x_55_n32, mult_x_55_n31, mult_x_23_n226, mult_x_23_n222,
mult_x_23_n214, mult_x_23_n213, mult_x_23_n210, mult_x_23_n209,
mult_x_23_n207, mult_x_23_n206, mult_x_23_n205, mult_x_23_n202,
mult_x_23_n201, mult_x_23_n200, mult_x_23_n199, mult_x_23_n198,
mult_x_23_n197, mult_x_23_n196, mult_x_23_n194, mult_x_23_n193,
mult_x_23_n192, mult_x_23_n191, mult_x_23_n190, mult_x_23_n189,
mult_x_23_n188, mult_x_23_n186, mult_x_23_n185, mult_x_23_n184,
mult_x_23_n183, mult_x_23_n180, mult_x_23_n179, mult_x_23_n177,
mult_x_23_n174, mult_x_23_n173, mult_x_23_n172, mult_x_23_n170,
mult_x_23_n169, mult_x_23_n168, mult_x_23_n167, mult_x_23_n164,
mult_x_23_n163, mult_x_23_n162, mult_x_23_n161, mult_x_23_n160,
mult_x_23_n159, mult_x_23_n158, mult_x_23_n157, mult_x_23_n156,
mult_x_23_n155, mult_x_23_n154, mult_x_23_n153, mult_x_23_n152,
mult_x_23_n151, mult_x_23_n136, mult_x_23_n133, mult_x_23_n132,
mult_x_23_n131, mult_x_23_n130, mult_x_23_n129, mult_x_23_n128,
mult_x_23_n127, mult_x_23_n126, mult_x_23_n125, mult_x_23_n124,
mult_x_23_n123, mult_x_23_n122, mult_x_23_n121, mult_x_23_n120,
mult_x_23_n119, mult_x_23_n118, mult_x_23_n117, mult_x_23_n116,
mult_x_23_n115, mult_x_23_n114, mult_x_23_n113, mult_x_23_n112,
mult_x_23_n111, mult_x_23_n110, mult_x_23_n109, mult_x_23_n108,
mult_x_23_n107, mult_x_23_n106, mult_x_23_n105, mult_x_23_n104,
mult_x_23_n103, mult_x_23_n102, mult_x_23_n101, mult_x_23_n100,
mult_x_23_n99, mult_x_23_n98, mult_x_23_n97, mult_x_23_n96,
mult_x_23_n95, mult_x_23_n94, mult_x_23_n93, mult_x_23_n92,
mult_x_23_n90, mult_x_23_n89, mult_x_23_n88, mult_x_23_n87,
mult_x_23_n86, mult_x_23_n85, mult_x_23_n84, mult_x_23_n83,
mult_x_23_n80, mult_x_23_n79, mult_x_23_n78, mult_x_23_n77,
mult_x_23_n76, mult_x_23_n75, mult_x_23_n74, mult_x_23_n73,
mult_x_23_n72, mult_x_23_n71, mult_x_23_n70, mult_x_23_n69,
mult_x_23_n68, mult_x_23_n67, mult_x_23_n66, mult_x_23_n65,
mult_x_23_n62, mult_x_23_n61, mult_x_23_n60, mult_x_23_n59,
mult_x_23_n58, mult_x_23_n57, mult_x_23_n56, mult_x_23_n55,
mult_x_23_n54, mult_x_23_n53, mult_x_23_n52, mult_x_23_n51,
mult_x_23_n48, mult_x_23_n47, mult_x_23_n46, mult_x_23_n45,
mult_x_23_n44, mult_x_23_n43, mult_x_23_n42, mult_x_23_n41,
mult_x_23_n40, mult_x_23_n39, mult_x_23_n36, mult_x_23_n35,
mult_x_23_n34, mult_x_23_n33, mult_x_23_n32, mult_x_23_n31,
DP_OP_36J144_124_9196_n33, DP_OP_36J144_124_9196_n22,
DP_OP_36J144_124_9196_n21, DP_OP_36J144_124_9196_n20,
DP_OP_36J144_124_9196_n19, DP_OP_36J144_124_9196_n18,
DP_OP_36J144_124_9196_n17, DP_OP_36J144_124_9196_n16,
DP_OP_36J144_124_9196_n15, DP_OP_36J144_124_9196_n9,
DP_OP_36J144_124_9196_n8, DP_OP_36J144_124_9196_n7,
DP_OP_36J144_124_9196_n6, DP_OP_36J144_124_9196_n5,
DP_OP_36J144_124_9196_n4, DP_OP_36J144_124_9196_n3,
DP_OP_36J144_124_9196_n2, DP_OP_36J144_124_9196_n1, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414,
n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425,
n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436,
n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458,
n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480,
n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491,
n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502,
n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513,
n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535,
n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697,
n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737,
n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747,
n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757,
n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767,
n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777,
n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [11:0] Sgf_operation_Result;
wire [25:0] Sgf_operation_RECURSIVE_EVEN1_Q_middle;
wire [23:12] Sgf_operation_RECURSIVE_EVEN1_Q_right;
wire [23:0] Sgf_operation_RECURSIVE_EVEN1_Q_left;
CMPR42X1TS DP_OP_111J144_123_4462_U75 ( .A(DP_OP_111J144_123_4462_n240), .B(
DP_OP_111J144_123_4462_n227), .C(DP_OP_111J144_123_4462_n148), .D(
DP_OP_111J144_123_4462_n252), .ICI(DP_OP_111J144_123_4462_n214), .S(
DP_OP_111J144_123_4462_n145), .ICO(DP_OP_111J144_123_4462_n143), .CO(
DP_OP_111J144_123_4462_n144) );
CMPR42X1TS DP_OP_111J144_123_4462_U73 ( .A(DP_OP_111J144_123_4462_n143), .B(
DP_OP_111J144_123_4462_n251), .C(DP_OP_111J144_123_4462_n142), .D(
DP_OP_111J144_123_4462_n213), .ICI(DP_OP_111J144_123_4462_n156), .S(
DP_OP_111J144_123_4462_n140), .ICO(DP_OP_111J144_123_4462_n138), .CO(
DP_OP_111J144_123_4462_n139) );
CMPR42X1TS DP_OP_111J144_123_4462_U71 ( .A(DP_OP_111J144_123_4462_n212), .B(
DP_OP_111J144_123_4462_n137), .C(DP_OP_111J144_123_4462_n138), .D(
DP_OP_111J144_123_4462_n250), .ICI(DP_OP_111J144_123_4462_n200), .S(
DP_OP_111J144_123_4462_n135), .ICO(DP_OP_111J144_123_4462_n133), .CO(
DP_OP_111J144_123_4462_n134) );
CMPR42X1TS DP_OP_111J144_123_4462_U68 ( .A(DP_OP_111J144_123_4462_n133), .B(
DP_OP_111J144_123_4462_n249), .C(DP_OP_111J144_123_4462_n130), .D(
DP_OP_111J144_123_4462_n199), .ICI(DP_OP_111J144_123_4462_n155), .S(
DP_OP_111J144_123_4462_n128), .ICO(DP_OP_111J144_123_4462_n126), .CO(
DP_OP_111J144_123_4462_n127) );
CMPR42X1TS DP_OP_111J144_123_4462_U67 ( .A(DP_OP_111J144_123_4462_n223), .B(
DP_OP_111J144_123_4462_n210), .C(DP_OP_111J144_123_4462_n131), .D(
DP_OP_111J144_123_4462_n236), .ICI(DP_OP_111J144_123_4462_n129), .S(
DP_OP_111J144_123_4462_n125), .ICO(DP_OP_111J144_123_4462_n123), .CO(
DP_OP_111J144_123_4462_n124) );
CMPR42X1TS DP_OP_111J144_123_4462_U66 ( .A(DP_OP_111J144_123_4462_n198), .B(
DP_OP_111J144_123_4462_n248), .C(DP_OP_111J144_123_4462_n187), .D(
DP_OP_111J144_123_4462_n126), .ICI(DP_OP_111J144_123_4462_n125), .S(
DP_OP_111J144_123_4462_n122), .ICO(DP_OP_111J144_123_4462_n120), .CO(
DP_OP_111J144_123_4462_n121) );
CMPR42X1TS DP_OP_111J144_123_4462_U64 ( .A(DP_OP_111J144_123_4462_n123), .B(
DP_OP_111J144_123_4462_n235), .C(DP_OP_111J144_123_4462_n119), .D(
DP_OP_111J144_123_4462_n197), .ICI(DP_OP_111J144_123_4462_n124), .S(
DP_OP_111J144_123_4462_n117), .ICO(DP_OP_111J144_123_4462_n115), .CO(
DP_OP_111J144_123_4462_n116) );
CMPR42X1TS DP_OP_111J144_123_4462_U63 ( .A(DP_OP_111J144_123_4462_n120), .B(
DP_OP_111J144_123_4462_n117), .C(DP_OP_111J144_123_4462_n247), .D(
DP_OP_111J144_123_4462_n121), .ICI(DP_OP_111J144_123_4462_n186), .S(
DP_OP_111J144_123_4462_n114), .ICO(DP_OP_111J144_123_4462_n112), .CO(
DP_OP_111J144_123_4462_n113) );
CMPR42X1TS DP_OP_111J144_123_4462_U61 ( .A(DP_OP_111J144_123_4462_n196), .B(
DP_OP_111J144_123_4462_n111), .C(DP_OP_111J144_123_4462_n115), .D(
DP_OP_111J144_123_4462_n234), .ICI(DP_OP_111J144_123_4462_n116), .S(
DP_OP_111J144_123_4462_n109), .ICO(DP_OP_111J144_123_4462_n107), .CO(
DP_OP_111J144_123_4462_n108) );
CMPR42X1TS DP_OP_111J144_123_4462_U60 ( .A(DP_OP_111J144_123_4462_n246), .B(
DP_OP_111J144_123_4462_n172), .C(DP_OP_111J144_123_4462_n185), .D(
DP_OP_111J144_123_4462_n109), .ICI(DP_OP_111J144_123_4462_n112), .S(
DP_OP_111J144_123_4462_n106), .ICO(DP_OP_111J144_123_4462_n104), .CO(
DP_OP_111J144_123_4462_n105) );
CMPR42X1TS DP_OP_111J144_123_4462_U58 ( .A(DP_OP_111J144_123_4462_n195), .B(
DP_OP_111J144_123_4462_n245), .C(DP_OP_111J144_123_4462_n103), .D(
DP_OP_111J144_123_4462_n107), .ICI(DP_OP_111J144_123_4462_n233), .S(
DP_OP_111J144_123_4462_n101), .ICO(DP_OP_111J144_123_4462_n99), .CO(
DP_OP_111J144_123_4462_n100) );
CMPR42X1TS DP_OP_111J144_123_4462_U57 ( .A(DP_OP_111J144_123_4462_n108), .B(
DP_OP_111J144_123_4462_n171), .C(DP_OP_111J144_123_4462_n184), .D(
DP_OP_111J144_123_4462_n101), .ICI(DP_OP_111J144_123_4462_n104), .S(
DP_OP_111J144_123_4462_n98), .ICO(DP_OP_111J144_123_4462_n96), .CO(
DP_OP_111J144_123_4462_n97) );
CMPR42X1TS DP_OP_111J144_123_4462_U54 ( .A(DP_OP_111J144_123_4462_n219), .B(
DP_OP_111J144_123_4462_n102), .C(DP_OP_111J144_123_4462_n94), .D(
DP_OP_111J144_123_4462_n99), .ICI(DP_OP_111J144_123_4462_n232), .S(
DP_OP_111J144_123_4462_n92), .ICO(DP_OP_111J144_123_4462_n90), .CO(
DP_OP_111J144_123_4462_n91) );
CMPR42X1TS DP_OP_111J144_123_4462_U53 ( .A(DP_OP_111J144_123_4462_n170), .B(
DP_OP_111J144_123_4462_n183), .C(DP_OP_111J144_123_4462_n100), .D(
DP_OP_111J144_123_4462_n96), .ICI(DP_OP_111J144_123_4462_n92), .S(
DP_OP_111J144_123_4462_n89), .ICO(DP_OP_111J144_123_4462_n87), .CO(
DP_OP_111J144_123_4462_n88) );
CMPR42X1TS DP_OP_111J144_123_4462_U50 ( .A(DP_OP_111J144_123_4462_n231), .B(
DP_OP_111J144_123_4462_n93), .C(DP_OP_111J144_123_4462_n84), .D(
DP_OP_111J144_123_4462_n90), .ICI(DP_OP_111J144_123_4462_n218), .S(
DP_OP_111J144_123_4462_n82), .ICO(DP_OP_111J144_123_4462_n80), .CO(
DP_OP_111J144_123_4462_n81) );
CMPR42X1TS DP_OP_111J144_123_4462_U49 ( .A(DP_OP_111J144_123_4462_n169), .B(
DP_OP_111J144_123_4462_n182), .C(DP_OP_111J144_123_4462_n91), .D(
DP_OP_111J144_123_4462_n87), .ICI(DP_OP_111J144_123_4462_n82), .S(
DP_OP_111J144_123_4462_n79), .ICO(DP_OP_111J144_123_4462_n77), .CO(
DP_OP_111J144_123_4462_n78) );
CMPR42X1TS DP_OP_111J144_123_4462_U47 ( .A(DP_OP_111J144_123_4462_n204), .B(
DP_OP_111J144_123_4462_n83), .C(DP_OP_111J144_123_4462_n76), .D(
DP_OP_111J144_123_4462_n80), .ICI(DP_OP_111J144_123_4462_n217), .S(
DP_OP_111J144_123_4462_n74), .ICO(DP_OP_111J144_123_4462_n72), .CO(
DP_OP_111J144_123_4462_n73) );
CMPR42X1TS DP_OP_111J144_123_4462_U46 ( .A(DP_OP_111J144_123_4462_n168), .B(
DP_OP_111J144_123_4462_n181), .C(DP_OP_111J144_123_4462_n81), .D(
DP_OP_111J144_123_4462_n74), .ICI(DP_OP_111J144_123_4462_n77), .S(
DP_OP_111J144_123_4462_n71), .ICO(DP_OP_111J144_123_4462_n69), .CO(
DP_OP_111J144_123_4462_n70) );
CMPR42X1TS DP_OP_111J144_123_4462_U44 ( .A(DP_OP_111J144_123_4462_n68), .B(
DP_OP_111J144_123_4462_n216), .C(DP_OP_111J144_123_4462_n75), .D(
DP_OP_111J144_123_4462_n72), .ICI(DP_OP_111J144_123_4462_n203), .S(
DP_OP_111J144_123_4462_n66), .ICO(DP_OP_111J144_123_4462_n64), .CO(
DP_OP_111J144_123_4462_n65) );
CMPR42X1TS DP_OP_111J144_123_4462_U43 ( .A(DP_OP_111J144_123_4462_n167), .B(
DP_OP_111J144_123_4462_n180), .C(DP_OP_111J144_123_4462_n73), .D(
DP_OP_111J144_123_4462_n66), .ICI(DP_OP_111J144_123_4462_n69), .S(
DP_OP_111J144_123_4462_n63), .ICO(DP_OP_111J144_123_4462_n61), .CO(
DP_OP_111J144_123_4462_n62) );
CMPR42X1TS DP_OP_111J144_123_4462_U42 ( .A(DP_OP_111J144_123_4462_n215), .B(
DP_OP_111J144_123_4462_n67), .C(DP_OP_111J144_123_4462_n191), .D(
DP_OP_111J144_123_4462_n64), .ICI(DP_OP_111J144_123_4462_n202), .S(
DP_OP_111J144_123_4462_n60), .ICO(DP_OP_111J144_123_4462_n58), .CO(
DP_OP_111J144_123_4462_n59) );
CMPR42X1TS DP_OP_111J144_123_4462_U41 ( .A(DP_OP_111J144_123_4462_n166), .B(
DP_OP_111J144_123_4462_n179), .C(DP_OP_111J144_123_4462_n65), .D(
DP_OP_111J144_123_4462_n60), .ICI(DP_OP_111J144_123_4462_n61), .S(
DP_OP_111J144_123_4462_n57), .ICO(DP_OP_111J144_123_4462_n55), .CO(
DP_OP_111J144_123_4462_n56) );
CMPR42X1TS DP_OP_111J144_123_4462_U38 ( .A(DP_OP_111J144_123_4462_n165), .B(
DP_OP_111J144_123_4462_n178), .C(DP_OP_111J144_123_4462_n52), .D(
DP_OP_111J144_123_4462_n59), .ICI(DP_OP_111J144_123_4462_n55), .S(
DP_OP_111J144_123_4462_n50), .ICO(DP_OP_111J144_123_4462_n48), .CO(
DP_OP_111J144_123_4462_n49) );
CMPR42X1TS DP_OP_111J144_123_4462_U36 ( .A(DP_OP_111J144_123_4462_n164), .B(
DP_OP_111J144_123_4462_n177), .C(DP_OP_111J144_123_4462_n51), .D(
DP_OP_111J144_123_4462_n47), .ICI(DP_OP_111J144_123_4462_n48), .S(
DP_OP_111J144_123_4462_n45), .ICO(DP_OP_111J144_123_4462_n43), .CO(
DP_OP_111J144_123_4462_n44) );
CMPR42X1TS DP_OP_111J144_123_4462_U34 ( .A(DP_OP_111J144_123_4462_n42), .B(
DP_OP_111J144_123_4462_n163), .C(DP_OP_111J144_123_4462_n176), .D(
DP_OP_111J144_123_4462_n46), .ICI(DP_OP_111J144_123_4462_n43), .S(
DP_OP_111J144_123_4462_n40), .ICO(DP_OP_111J144_123_4462_n38), .CO(
DP_OP_111J144_123_4462_n39) );
CMPR42X1TS DP_OP_111J144_123_4462_U33 ( .A(DP_OP_111J144_123_4462_n188), .B(
DP_OP_111J144_123_4462_n41), .C(DP_OP_111J144_123_4462_n162), .D(
DP_OP_111J144_123_4462_n175), .ICI(DP_OP_111J144_123_4462_n38), .S(
DP_OP_111J144_123_4462_n37), .ICO(DP_OP_111J144_123_4462_n35), .CO(
DP_OP_111J144_123_4462_n36) );
CMPR42X1TS mult_x_55_U69 ( .A(mult_x_55_n196), .B(mult_x_55_n232), .C(
mult_x_55_n220), .D(mult_x_55_n208), .ICI(mult_x_55_n136), .S(
mult_x_55_n133), .ICO(mult_x_55_n131), .CO(mult_x_55_n132) );
CMPR42X1TS mult_x_55_U67 ( .A(mult_x_55_n219), .B(mult_x_55_n195), .C(
mult_x_55_n207), .D(mult_x_55_n131), .ICI(mult_x_55_n130), .S(
mult_x_55_n128), .ICO(mult_x_55_n126), .CO(mult_x_55_n127) );
CMPR42X1TS mult_x_55_U65 ( .A(mult_x_55_n206), .B(mult_x_55_n194), .C(
mult_x_55_n129), .D(mult_x_55_n126), .ICI(mult_x_55_n125), .S(
mult_x_55_n123), .ICO(mult_x_55_n121), .CO(mult_x_55_n122) );
CMPR42X1TS mult_x_55_U62 ( .A(mult_x_55_n205), .B(mult_x_55_n124), .C(
mult_x_55_n120), .D(mult_x_55_n118), .ICI(mult_x_55_n121), .S(
mult_x_55_n116), .ICO(mult_x_55_n114), .CO(mult_x_55_n115) );
CMPR42X1TS mult_x_55_U61 ( .A(mult_x_55_n168), .B(mult_x_55_n228), .C(
mult_x_55_n216), .D(mult_x_55_n204), .ICI(mult_x_55_n180), .S(
mult_x_55_n113), .ICO(mult_x_55_n111), .CO(mult_x_55_n112) );
CMPR42X1TS mult_x_55_U60 ( .A(mult_x_55_n192), .B(mult_x_55_n119), .C(
mult_x_55_n117), .D(mult_x_55_n114), .ICI(mult_x_55_n113), .S(
mult_x_55_n110), .ICO(mult_x_55_n108), .CO(mult_x_55_n109) );
CMPR42X1TS mult_x_55_U58 ( .A(mult_x_55_n215), .B(mult_x_55_n167), .C(
mult_x_55_n203), .D(mult_x_55_n179), .ICI(mult_x_55_n107), .S(
mult_x_55_n105), .ICO(mult_x_55_n103), .CO(mult_x_55_n104) );
CMPR42X1TS mult_x_55_U57 ( .A(mult_x_55_n191), .B(mult_x_55_n111), .C(
mult_x_55_n108), .D(mult_x_55_n112), .ICI(mult_x_55_n105), .S(
mult_x_55_n102), .ICO(mult_x_55_n100), .CO(mult_x_55_n101) );
CMPR42X1TS mult_x_55_U55 ( .A(mult_x_55_n202), .B(mult_x_55_n166), .C(
mult_x_55_n190), .D(mult_x_55_n178), .ICI(mult_x_55_n99), .S(
mult_x_55_n97), .ICO(mult_x_55_n95), .CO(mult_x_55_n96) );
CMPR42X1TS mult_x_55_U54 ( .A(mult_x_55_n106), .B(mult_x_55_n103), .C(
mult_x_55_n104), .D(mult_x_55_n97), .ICI(mult_x_55_n100), .S(
mult_x_55_n94), .ICO(mult_x_55_n92), .CO(mult_x_55_n93) );
CMPR42X1TS mult_x_55_U51 ( .A(mult_x_55_n189), .B(mult_x_55_n165), .C(
mult_x_55_n213), .D(n650), .ICI(mult_x_55_n90), .S(mult_x_55_n88),
.ICO(mult_x_55_n86), .CO(mult_x_55_n87) );
CMPR42X1TS mult_x_55_U50 ( .A(mult_x_55_n95), .B(mult_x_55_n98), .C(
mult_x_55_n96), .D(mult_x_55_n88), .ICI(mult_x_55_n92), .S(
mult_x_55_n85), .ICO(mult_x_55_n83), .CO(mult_x_55_n84) );
CMPR42X1TS mult_x_55_U47 ( .A(mult_x_55_n176), .B(mult_x_55_n212), .C(
mult_x_55_n200), .D(mult_x_55_n164), .ICI(mult_x_55_n89), .S(
mult_x_55_n78), .ICO(mult_x_55_n76), .CO(mult_x_55_n77) );
CMPR42X1TS mult_x_55_U46 ( .A(mult_x_55_n86), .B(mult_x_55_n80), .C(
mult_x_55_n87), .D(mult_x_55_n78), .ICI(mult_x_55_n83), .S(
mult_x_55_n75), .ICO(mult_x_55_n73), .CO(mult_x_55_n74) );
CMPR42X1TS mult_x_55_U44 ( .A(mult_x_55_n175), .B(mult_x_55_n163), .C(
mult_x_55_n199), .D(mult_x_55_n211), .ICI(mult_x_55_n72), .S(
mult_x_55_n70), .ICO(mult_x_55_n68), .CO(mult_x_55_n69) );
CMPR42X1TS mult_x_55_U43 ( .A(mult_x_55_n76), .B(mult_x_55_n79), .C(
mult_x_55_n77), .D(mult_x_55_n70), .ICI(mult_x_55_n73), .S(
mult_x_55_n67), .ICO(mult_x_55_n65), .CO(mult_x_55_n66) );
CMPR42X1TS mult_x_55_U41 ( .A(mult_x_55_n64), .B(mult_x_55_n174), .C(
mult_x_55_n186), .D(mult_x_55_n162), .ICI(mult_x_55_n198), .S(
mult_x_55_n62), .ICO(mult_x_55_n60), .CO(mult_x_55_n61) );
CMPR42X1TS mult_x_55_U40 ( .A(mult_x_55_n68), .B(mult_x_55_n71), .C(
mult_x_55_n69), .D(mult_x_55_n62), .ICI(mult_x_55_n65), .S(
mult_x_55_n59), .ICO(mult_x_55_n57), .CO(mult_x_55_n58) );
CMPR42X1TS mult_x_55_U39 ( .A(mult_x_55_n63), .B(mult_x_55_n151), .C(
mult_x_55_n185), .D(mult_x_55_n173), .ICI(mult_x_55_n161), .S(
mult_x_55_n56), .ICO(mult_x_55_n54), .CO(mult_x_55_n55) );
CMPR42X1TS mult_x_55_U38 ( .A(mult_x_55_n197), .B(mult_x_55_n60), .C(
mult_x_55_n61), .D(mult_x_55_n56), .ICI(mult_x_55_n57), .S(
mult_x_55_n53), .ICO(mult_x_55_n51), .CO(mult_x_55_n52) );
CMPR42X1TS mult_x_55_U35 ( .A(mult_x_55_n160), .B(mult_x_55_n54), .C(
mult_x_55_n48), .D(mult_x_55_n55), .ICI(mult_x_55_n51), .S(
mult_x_55_n46), .ICO(mult_x_55_n44), .CO(mult_x_55_n45) );
CMPR42X1TS mult_x_55_U33 ( .A(mult_x_55_n159), .B(mult_x_55_n183), .C(
mult_x_55_n43), .D(mult_x_55_n47), .ICI(mult_x_55_n44), .S(
mult_x_55_n41), .ICO(mult_x_55_n39), .CO(mult_x_55_n40) );
CMPR42X1TS mult_x_55_U31 ( .A(mult_x_55_n38), .B(mult_x_55_n170), .C(
mult_x_55_n158), .D(mult_x_55_n42), .ICI(mult_x_55_n39), .S(
mult_x_55_n36), .ICO(mult_x_55_n34), .CO(mult_x_55_n35) );
CMPR42X1TS mult_x_55_U30 ( .A(mult_x_55_n37), .B(mult_x_55_n149), .C(
mult_x_55_n157), .D(mult_x_55_n169), .ICI(mult_x_55_n34), .S(
mult_x_55_n33), .ICO(mult_x_55_n31), .CO(mult_x_55_n32) );
CMPR42X1TS mult_x_23_U69 ( .A(mult_x_23_n190), .B(mult_x_23_n226), .C(
mult_x_23_n214), .D(mult_x_23_n202), .ICI(mult_x_23_n136), .S(
mult_x_23_n133), .ICO(mult_x_23_n131), .CO(mult_x_23_n132) );
CMPR42X1TS mult_x_23_U67 ( .A(mult_x_23_n213), .B(mult_x_23_n189), .C(
mult_x_23_n201), .D(mult_x_23_n131), .ICI(mult_x_23_n130), .S(
mult_x_23_n128), .ICO(mult_x_23_n126), .CO(mult_x_23_n127) );
CMPR42X1TS mult_x_23_U65 ( .A(mult_x_23_n200), .B(mult_x_23_n188), .C(
mult_x_23_n129), .D(mult_x_23_n126), .ICI(mult_x_23_n125), .S(
mult_x_23_n123), .ICO(mult_x_23_n121), .CO(mult_x_23_n122) );
CMPR42X1TS mult_x_23_U62 ( .A(mult_x_23_n199), .B(mult_x_23_n124), .C(
mult_x_23_n120), .D(mult_x_23_n118), .ICI(mult_x_23_n121), .S(
mult_x_23_n116), .ICO(mult_x_23_n114), .CO(mult_x_23_n115) );
CMPR42X1TS mult_x_23_U61 ( .A(mult_x_23_n162), .B(mult_x_23_n222), .C(
mult_x_23_n210), .D(mult_x_23_n198), .ICI(mult_x_23_n174), .S(
mult_x_23_n113), .ICO(mult_x_23_n111), .CO(mult_x_23_n112) );
CMPR42X1TS mult_x_23_U60 ( .A(mult_x_23_n186), .B(mult_x_23_n119), .C(
mult_x_23_n117), .D(mult_x_23_n114), .ICI(mult_x_23_n113), .S(
mult_x_23_n110), .ICO(mult_x_23_n108), .CO(mult_x_23_n109) );
CMPR42X1TS mult_x_23_U58 ( .A(mult_x_23_n209), .B(mult_x_23_n161), .C(
mult_x_23_n197), .D(mult_x_23_n173), .ICI(mult_x_23_n107), .S(
mult_x_23_n105), .ICO(mult_x_23_n103), .CO(mult_x_23_n104) );
CMPR42X1TS mult_x_23_U57 ( .A(mult_x_23_n185), .B(mult_x_23_n111), .C(
mult_x_23_n108), .D(mult_x_23_n112), .ICI(mult_x_23_n105), .S(
mult_x_23_n102), .ICO(mult_x_23_n100), .CO(mult_x_23_n101) );
CMPR42X1TS mult_x_23_U55 ( .A(mult_x_23_n196), .B(mult_x_23_n160), .C(
mult_x_23_n184), .D(mult_x_23_n172), .ICI(mult_x_23_n99), .S(
mult_x_23_n97), .ICO(mult_x_23_n95), .CO(mult_x_23_n96) );
CMPR42X1TS mult_x_23_U54 ( .A(mult_x_23_n106), .B(mult_x_23_n103), .C(
mult_x_23_n104), .D(mult_x_23_n97), .ICI(mult_x_23_n100), .S(
mult_x_23_n94), .ICO(mult_x_23_n92), .CO(mult_x_23_n93) );
CMPR42X1TS mult_x_23_U51 ( .A(mult_x_23_n183), .B(mult_x_23_n159), .C(
mult_x_23_n207), .D(n1884), .ICI(mult_x_23_n90), .S(mult_x_23_n88),
.ICO(mult_x_23_n86), .CO(mult_x_23_n87) );
CMPR42X1TS mult_x_23_U50 ( .A(mult_x_23_n95), .B(mult_x_23_n98), .C(
mult_x_23_n96), .D(mult_x_23_n88), .ICI(mult_x_23_n92), .S(
mult_x_23_n85), .ICO(mult_x_23_n83), .CO(mult_x_23_n84) );
CMPR42X1TS mult_x_23_U47 ( .A(mult_x_23_n170), .B(mult_x_23_n206), .C(
mult_x_23_n194), .D(mult_x_23_n158), .ICI(mult_x_23_n89), .S(
mult_x_23_n78), .ICO(mult_x_23_n76), .CO(mult_x_23_n77) );
CMPR42X1TS mult_x_23_U46 ( .A(mult_x_23_n86), .B(mult_x_23_n80), .C(
mult_x_23_n87), .D(mult_x_23_n78), .ICI(mult_x_23_n83), .S(
mult_x_23_n75), .ICO(mult_x_23_n73), .CO(mult_x_23_n74) );
CMPR42X1TS mult_x_23_U44 ( .A(mult_x_23_n169), .B(mult_x_23_n157), .C(
mult_x_23_n193), .D(mult_x_23_n205), .ICI(mult_x_23_n72), .S(
mult_x_23_n70), .ICO(mult_x_23_n68), .CO(mult_x_23_n69) );
CMPR42X1TS mult_x_23_U43 ( .A(mult_x_23_n76), .B(mult_x_23_n79), .C(
mult_x_23_n77), .D(mult_x_23_n70), .ICI(mult_x_23_n73), .S(
mult_x_23_n67), .ICO(mult_x_23_n65), .CO(mult_x_23_n66) );
CMPR42X1TS mult_x_23_U41 ( .A(n1864), .B(mult_x_23_n168), .C(mult_x_23_n180),
.D(mult_x_23_n156), .ICI(mult_x_23_n192), .S(mult_x_23_n62), .ICO(
mult_x_23_n60), .CO(mult_x_23_n61) );
CMPR42X1TS mult_x_23_U40 ( .A(mult_x_23_n68), .B(mult_x_23_n71), .C(
mult_x_23_n69), .D(mult_x_23_n62), .ICI(mult_x_23_n65), .S(
mult_x_23_n59), .ICO(mult_x_23_n57), .CO(mult_x_23_n58) );
CMPR42X1TS mult_x_23_U39 ( .A(Op_MY[16]), .B(n582), .C(mult_x_23_n179), .D(
mult_x_23_n167), .ICI(mult_x_23_n155), .S(mult_x_23_n56), .ICO(
mult_x_23_n54), .CO(mult_x_23_n55) );
CMPR42X1TS mult_x_23_U38 ( .A(mult_x_23_n191), .B(mult_x_23_n60), .C(
mult_x_23_n61), .D(mult_x_23_n56), .ICI(mult_x_23_n57), .S(
mult_x_23_n53), .ICO(mult_x_23_n51), .CO(mult_x_23_n52) );
CMPR42X1TS mult_x_23_U35 ( .A(mult_x_23_n154), .B(mult_x_23_n54), .C(
mult_x_23_n48), .D(mult_x_23_n55), .ICI(mult_x_23_n51), .S(
mult_x_23_n46), .ICO(mult_x_23_n44), .CO(mult_x_23_n45) );
CMPR42X1TS mult_x_23_U33 ( .A(mult_x_23_n153), .B(mult_x_23_n177), .C(
mult_x_23_n43), .D(mult_x_23_n47), .ICI(mult_x_23_n44), .S(
mult_x_23_n41), .ICO(mult_x_23_n39), .CO(mult_x_23_n40) );
CMPR42X1TS mult_x_23_U31 ( .A(n1860), .B(mult_x_23_n164), .C(mult_x_23_n152),
.D(mult_x_23_n42), .ICI(mult_x_23_n39), .S(mult_x_23_n36), .ICO(
mult_x_23_n34), .CO(mult_x_23_n35) );
CMPR42X1TS mult_x_23_U30 ( .A(Op_MY[20]), .B(n583), .C(mult_x_23_n151), .D(
mult_x_23_n163), .ICI(mult_x_23_n34), .S(mult_x_23_n33), .ICO(
mult_x_23_n31), .CO(mult_x_23_n32) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n378), .CK(n1951), .RN(n1926), .Q(
FS_Module_state_reg[0]), .QN(n1921) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n309), .CK(n1964), .RN(n1934), .Q(
FSM_selector_B[0]), .QN(n1920) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n262),
.CK(n1969), .RN(n1930), .Q(final_result_ieee[31]), .QN(n1919) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n379), .CK(n1949), .RN(n1972), .Q(
FS_Module_state_reg[3]), .QN(n1918) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n304), .CK(n1954), .RN(n1937),
.Q(Add_result[2]), .QN(n1917) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n307), .CK(n1971),
.RN(n1932), .Q(Sgf_normalized_result[23]), .QN(n1916) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n375), .CK(n1948), .RN(n1927), .Q(
FSM_selector_A), .QN(n1915) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_24_ ( .D(n239), .CK(
n1963), .RN(n1923), .Q(P_Sgf[24]), .QN(n1914) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_26_ ( .D(n241), .CK(
n1961), .RN(n1923), .Q(P_Sgf[26]), .QN(n1913) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_28_ ( .D(n243), .CK(
n1960), .RN(n1923), .Q(P_Sgf[28]), .QN(n1912) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_32_ ( .D(n247), .CK(
n1965), .RN(n1922), .Q(P_Sgf[32]), .QN(n1910) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_34_ ( .D(n249), .CK(
n1964), .RN(n1922), .Q(P_Sgf[34]), .QN(n1909) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_36_ ( .D(n251), .CK(
n1965), .RN(n1922), .Q(P_Sgf[36]), .QN(n1908) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(n620), .RN(
n1942), .Q(Op_MX[21]), .QN(n1906) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(n1956), .RN(
n1936), .Q(Op_MY[24]), .QN(n1899) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n213), .CK(n1971),
.RN(n1932), .Q(Sgf_normalized_result[22]), .QN(n1898) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n211), .CK(n1969),
.RN(n1932), .Q(Sgf_normalized_result[20]), .QN(n1897) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n209), .CK(n1968),
.RN(n1932), .Q(Sgf_normalized_result[18]), .QN(n1896) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n207), .CK(n1966),
.RN(n1932), .Q(Sgf_normalized_result[16]), .QN(n1895) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n205), .CK(n1967),
.RN(n1931), .Q(Sgf_normalized_result[14]), .QN(n1894) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n203), .CK(n1971),
.RN(n1931), .Q(Sgf_normalized_result[12]), .QN(n1893) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n201), .CK(n1966),
.RN(n1931), .Q(Sgf_normalized_result[10]), .QN(n1892) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n199), .CK(n1969),
.RN(n1931), .Q(Sgf_normalized_result[8]), .QN(n1891) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n197), .CK(n1968),
.RN(n1931), .Q(Sgf_normalized_result[6]), .QN(n1890) );
DFFRX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(n1954),
.RN(n1934), .Q(zero_flag), .QN(n1889) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_38_ ( .D(n253), .CK(
n1962), .RN(n1922), .QN(n1888) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_40_ ( .D(n255), .CK(
n1963), .RN(n1922), .QN(n1887) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_42_ ( .D(n257), .CK(
n1965), .RN(n1926), .QN(n1886) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_44_ ( .D(n259), .CK(
n1964), .RN(n1972), .QN(n1885) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n308), .CK(n1963), .RN(n1933), .Q(
FSM_selector_B[1]), .QN(n1883) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(n1957), .RN(
n1940), .Q(Op_MX[0]), .QN(n1882) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(n1954), .RN(
n1936), .Q(Op_MY[25]), .QN(n1871) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n377), .CK(n620), .RN(n1926), .Q(
FS_Module_state_reg[1]), .QN(n1870) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(n1953), .RN(
n1941), .Q(Op_MX[12]), .QN(n1869) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n376), .CK(n1952), .RN(n1926), .Q(
FS_Module_state_reg[2]), .QN(n1868) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(n1955), .RN(
n1936), .Q(Op_MY[26]), .QN(n1861) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_0_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N0), .CK(n1950), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_2_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N2), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_3_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N3), .CK(n1964), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_4_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N4), .CK(n1965), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_5_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N5), .CK(n1963), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_6_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N6), .CK(n1946), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_7_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N7), .CK(n1946), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_8_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N8), .CK(n1946), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_9_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N9), .CK(n1946), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_10_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N10), .CK(n1946), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_11_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N11), .CK(n1946), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_12_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N12), .CK(n1946), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_13_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N13), .CK(n1946), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_14_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N14), .CK(n1946), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_15_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N15), .CK(n1946), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_16_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N16), .CK(n1947), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_17_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N17), .CK(n1947), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_18_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N18), .CK(n1947), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_19_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N19), .CK(n1947), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_20_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N20), .CK(n1947), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_21_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N21), .CK(n1947), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_22_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N22), .CK(n1947), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_23_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N23), .CK(n1947), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_24_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N24), .CK(n1947), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_25_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N25), .CK(n1947), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_1_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N1), .CK(n1962), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_0_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N0), .CK(n1950), .Q(
Sgf_operation_Result[0]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_1_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N1), .CK(n1953), .Q(
Sgf_operation_Result[1]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_2_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N2), .CK(n1948), .Q(
Sgf_operation_Result[2]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_3_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N3), .CK(n1950), .Q(
Sgf_operation_Result[3]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_4_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N4), .CK(n620), .Q(
Sgf_operation_Result[4]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_5_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N5), .CK(n1950), .Q(
Sgf_operation_Result[5]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_6_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N6), .CK(n1951), .Q(
Sgf_operation_Result[6]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_7_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N7), .CK(n620), .Q(
Sgf_operation_Result[7]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_8_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N8), .CK(n1953), .Q(
Sgf_operation_Result[8]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_9_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N9), .CK(n620), .Q(
Sgf_operation_Result[9]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_10_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N10), .CK(n1951), .Q(
Sgf_operation_Result[10]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_11_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N11), .CK(n1948), .Q(
Sgf_operation_Result[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n174),
.CK(n1967), .RN(n1927), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n173),
.CK(n1971), .RN(n1927), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n172),
.CK(n1966), .RN(n1927), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n171),
.CK(n1968), .RN(n1927), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n170),
.CK(n1969), .RN(n1927), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n169),
.CK(n1967), .RN(n1927), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n167),
.CK(n1971), .RN(n1927), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n190),
.CK(n1971), .RN(n1929), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n189),
.CK(n1966), .RN(n1929), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n188),
.CK(n1969), .RN(n1929), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n187),
.CK(n1968), .RN(n1929), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n186),
.CK(n1967), .RN(n1928), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n185),
.CK(n1966), .RN(n1928), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n184),
.CK(n1969), .RN(n1928), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n183),
.CK(n1970), .RN(n1928), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n182),
.CK(n1970), .RN(n1928), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n181),
.CK(n1970), .RN(n1928), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n180),
.CK(n1970), .RN(n1928), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n179),
.CK(n1970), .RN(n1928), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n178),
.CK(n1970), .RN(n1928), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n177),
.CK(n1970), .RN(n1928), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n176),
.CK(n1970), .RN(n1927), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n175),
.CK(n1970), .RN(n1927), .Q(final_result_ieee[15]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_17_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N17), .CK(n1945), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[17]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_19_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N19), .CK(n1945), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[19]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_21_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N21), .CK(n1951), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[21]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_1_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N1), .CK(n1944), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n270),
.CK(n1968), .RN(n1930), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n269),
.CK(n1967), .RN(n1930), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n268),
.CK(n1971), .RN(n1929), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n267),
.CK(n1966), .RN(n1929), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n266),
.CK(n1969), .RN(n1929), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n265),
.CK(n1968), .RN(n1929), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n264),
.CK(n1967), .RN(n1929), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n263),
.CK(n1966), .RN(n1929), .Q(final_result_ieee[30]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_12_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N12), .CK(n1952), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[12]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_23_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N23), .CK(n1948), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[23]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n271), .CK(n1960), .RN(n1932),
.Q(Exp_module_Overflow_flag_A) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_2_ ( .D(n217), .CK(
n1962), .RN(n1925), .Q(P_Sgf[2]) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(n1956), .RN(
n1939), .Q(Op_MX[31]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_0_ ( .D(n215), .CK(
n1960), .RN(n1926), .Q(P_Sgf[0]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_15_ ( .D(n230), .CK(
n623), .RN(n1924), .Q(P_Sgf[15]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_14_ ( .D(n229), .CK(
n1962), .RN(n1924), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_3_ ( .D(n218), .CK(
n1962), .RN(n1925), .Q(P_Sgf[3]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_22_ ( .D(n237), .CK(
n1964), .RN(n1923), .Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_18_ ( .D(n233), .CK(
n1963), .RN(n1924), .Q(P_Sgf[18]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_17_ ( .D(n232), .CK(
n1965), .RN(n1924), .Q(P_Sgf[17]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_10_ ( .D(n225), .CK(
n1964), .RN(n1925), .Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_6_ ( .D(n221), .CK(
n623), .RN(n1925), .Q(P_Sgf[6]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_5_ ( .D(n220), .CK(
n623), .RN(n1925), .Q(P_Sgf[5]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_21_ ( .D(n236), .CK(
n1965), .RN(n1923), .Q(P_Sgf[21]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_16_ ( .D(n231), .CK(
n623), .RN(n1924), .Q(P_Sgf[16]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_12_ ( .D(n227), .CK(
n1960), .RN(n1924), .Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_11_ ( .D(n226), .CK(
n1960), .RN(n1924), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_4_ ( .D(n219), .CK(
n1960), .RN(n1925), .Q(P_Sgf[4]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n310), .CK(n1949), .RN(
n1935), .Q(Op_MY[31]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_20_ ( .D(n235), .CK(
n1964), .RN(n1924), .Q(P_Sgf[20]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_13_ ( .D(n228), .CK(
n1960), .RN(n1924), .Q(P_Sgf[13]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_9_ ( .D(n224), .CK(
n1960), .RN(n1925), .Q(P_Sgf[9]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_1_ ( .D(n216), .CK(
n1963), .RN(n1925), .Q(P_Sgf[1]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n283), .CK(n1957), .RN(n1937), .Q(Add_result[23]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_0_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N0), .CK(n1944), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[0]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_2_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N2), .CK(n1944), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[2]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_3_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N3), .CK(n1944), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[3]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_4_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N4), .CK(n1944), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[4]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_5_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N5), .CK(n1944), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[5]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_6_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N6), .CK(n1944), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[6]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_7_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N7), .CK(n1944), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[7]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_8_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N8), .CK(n1944), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[8]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_9_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N9), .CK(n1944), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_10_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N10), .CK(n1945), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_11_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N11), .CK(n1945), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_12_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N12), .CK(n1945), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[12]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_23_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N23), .CK(n1952), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[23]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n306), .CK(n1959), .RN(n1937),
.Q(Add_result[0]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_13_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N13), .CK(n1950), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[13]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_14_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N14), .CK(n1953), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[14]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_15_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N15), .CK(n1951), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[15]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_16_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N16), .CK(n620), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[16]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_17_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N17), .CK(n1948), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[17]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_18_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N18), .CK(n1952), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[18]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_19_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N19), .CK(n1952), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[19]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_20_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N20), .CK(n1951), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[20]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_21_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N21), .CK(n1948), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[21]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_22_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N22), .CK(n1953), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[22]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_23_ ( .D(n238), .CK(
n1960), .RN(n1923), .Q(P_Sgf[23]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_15_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N15), .CK(n1945), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[15]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_14_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N14), .CK(n1945), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[14]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_22_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N22), .CK(n1953), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[22]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_16_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N16), .CK(n1945), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[16]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_18_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N18), .CK(n1945), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[18]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_20_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N20), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[20]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(n1959), .RN(
n1937), .Q(Op_MY[28]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(n1955), .RN(
n1937), .Q(Op_MY[29]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_47_ ( .D(n380), .CK(
n1948), .RN(n1972), .Q(P_Sgf[47]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(n1957), .RN(
n1937), .Q(Op_MY[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(n620), .RN(
n1942), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(n1952), .RN(
n1942), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(n1948), .RN(
n1942), .Q(Op_MX[29]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(n1952), .RN(
n1942), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(n1951), .RN(
n1942), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(n1950), .RN(
n1942), .Q(Op_MX[23]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n281), .CK(n1963), .RN(n1933),
.Q(exp_oper_result[8]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n282), .CK(n1959), .RN(
n1937), .Q(FSM_add_overflow_flag) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(n1953), .RN(
n1943), .Q(Op_MX[30]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(n1956), .RN(
n1936), .Q(Op_MY[23]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n280), .CK(n1964), .RN(n1933),
.Q(exp_oper_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n279), .CK(n1962), .RN(n1933),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n278), .CK(n1963), .RN(n1933),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n277), .CK(n1965), .RN(n1933),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n276), .CK(n623), .RN(n1933),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n275), .CK(n1961), .RN(n1933),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n274), .CK(n1961), .RN(n1933),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n273), .CK(n623), .RN(n1933),
.Q(exp_oper_result[7]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(n1951), .RN(
n1942), .Q(Op_MX[24]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_45_ ( .D(n260), .CK(
n1961), .RN(n1972), .Q(P_Sgf[45]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n302), .CK(n1956), .RN(n1938),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n301), .CK(n1954), .RN(n1938),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n303), .CK(n1955), .RN(n1937),
.Q(Add_result[3]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_37_ ( .D(n252), .CK(
n1965), .RN(n1922), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_35_ ( .D(n250), .CK(
n1964), .RN(n1922), .Q(P_Sgf[35]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_33_ ( .D(n248), .CK(
n623), .RN(n1922), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_31_ ( .D(n246), .CK(
n1963), .RN(n1922), .Q(P_Sgf[31]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_29_ ( .D(n244), .CK(
n1965), .RN(n1923), .Q(P_Sgf[29]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n285), .CK(n1959), .RN(n1939), .Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n287), .CK(n1956), .RN(n1939), .Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n289), .CK(n1954), .RN(n1939), .Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n291), .CK(n1957), .RN(n1939), .Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n293), .CK(n1959), .RN(n1938), .Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n295), .CK(n1956), .RN(n1938), .Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n297), .CK(n1954), .RN(n1938),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n299), .CK(n1955), .RN(n1938),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n284), .CK(n1955), .RN(n1939), .Q(Add_result[22]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_43_ ( .D(n258), .CK(
n1962), .RN(n1926), .Q(P_Sgf[43]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_41_ ( .D(n256), .CK(
n1963), .RN(n1926), .Q(P_Sgf[41]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_39_ ( .D(n254), .CK(
n1965), .RN(n1922), .Q(P_Sgf[39]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_27_ ( .D(n242), .CK(
n1961), .RN(n1923), .Q(P_Sgf[27]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_25_ ( .D(n240), .CK(
n1962), .RN(n1923), .Q(P_Sgf[25]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n286), .CK(n1957), .RN(n1939), .Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n288), .CK(n1959), .RN(n1939), .Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n290), .CK(n1956), .RN(n1939), .Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n292), .CK(n1957), .RN(n1939), .Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n294), .CK(n1956), .RN(n1938), .Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n296), .CK(n1954), .RN(n1938), .Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n298), .CK(n1959), .RN(n1938),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n300), .CK(n1955), .RN(n1938),
.Q(Add_result[6]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n305), .CK(n1957), .RN(n1937),
.Q(Add_result[1]) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n272), .CK(n1967), .RN(n1930),
.Q(underflow_flag) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_13_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N13), .CK(n1945), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n193), .CK(n1971),
.RN(n1930), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n212), .CK(n1971),
.RN(n1932), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n210), .CK(n1969),
.RN(n1932), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n208), .CK(n1968),
.RN(n1932), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n206), .CK(n1966),
.RN(n1931), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n204), .CK(n1967),
.RN(n1931), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n202), .CK(n1971),
.RN(n1931), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n200), .CK(n1966),
.RN(n1931), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n198), .CK(n1969),
.RN(n1931), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n196), .CK(n1968),
.RN(n1930), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n194), .CK(n1966),
.RN(n1930), .Q(Sgf_normalized_result[3]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(n1953), .RN(
n1942), .Q(Op_MX[22]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n192), .CK(n1969),
.RN(n1930), .Q(Sgf_normalized_result[1]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(n1953), .RN(
n1941), .Q(Op_MX[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(n1950), .RN(
n1940), .Q(Op_MX[4]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(n1952), .RN(
n1942), .Q(Op_MX[20]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(n1953), .RN(
n1941), .Q(Op_MX[16]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(n1952), .RN(
n1940), .Q(Op_MX[6]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(n620), .RN(
n1940), .Q(Op_MX[8]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(n1948), .RN(
n1940), .Q(Op_MX[2]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(n620), .RN(
n1941), .Q(Op_MX[14]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n191), .CK(n1968),
.RN(n1930), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(n1959), .RN(
n1936), .Q(Op_MY[18]), .QN(n1879) );
CMPR32X2TS DP_OP_36J144_124_9196_U10 ( .A(S_Oper_A_exp[0]), .B(
DP_OP_36J144_124_9196_n33), .C(DP_OP_36J144_124_9196_n22), .CO(
DP_OP_36J144_124_9196_n9), .S(Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_36J144_124_9196_U9 ( .A(DP_OP_36J144_124_9196_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J144_124_9196_n9), .CO(
DP_OP_36J144_124_9196_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J144_124_9196_U8 ( .A(DP_OP_36J144_124_9196_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J144_124_9196_n8), .CO(
DP_OP_36J144_124_9196_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J144_124_9196_U7 ( .A(DP_OP_36J144_124_9196_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J144_124_9196_n7), .CO(
DP_OP_36J144_124_9196_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J144_124_9196_U6 ( .A(DP_OP_36J144_124_9196_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J144_124_9196_n6), .CO(
DP_OP_36J144_124_9196_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J144_124_9196_U5 ( .A(DP_OP_36J144_124_9196_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J144_124_9196_n5), .CO(
DP_OP_36J144_124_9196_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J144_124_9196_U4 ( .A(DP_OP_36J144_124_9196_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J144_124_9196_n4), .CO(
DP_OP_36J144_124_9196_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J144_124_9196_U3 ( .A(DP_OP_36J144_124_9196_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J144_124_9196_n3), .CO(
DP_OP_36J144_124_9196_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J144_124_9196_U2 ( .A(DP_OP_36J144_124_9196_n33), .B(
S_Oper_A_exp[8]), .C(DP_OP_36J144_124_9196_n2), .CO(
DP_OP_36J144_124_9196_n1), .S(Exp_module_Data_S[8]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(n1958), .RN(
n1935), .Q(Op_MY[11]), .QN(n1872) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(n1958), .RN(
n1935), .Q(Op_MY[13]), .QN(n1859) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(n1954), .RN(
n1935), .Q(Op_MY[8]), .QN(n1875) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(n1955), .RN(
n1934), .Q(Op_MY[4]), .QN(n1874) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(n1958), .RN(
n1935), .Q(Op_MY[16]), .QN(n1864) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(n1954), .RN(
n1936), .Q(Op_MY[22]), .QN(n1877) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(n1949), .RN(
n1941), .Q(Op_MX[17]), .QN(n1903) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(n1956), .RN(
n1940), .Q(Op_MX[1]), .QN(n650) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(n1955), .RN(
n1934), .Q(Op_MY[0]), .QN(n629) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(n1949), .RN(
n1941), .Q(Op_MX[13]), .QN(n1884) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(n1959), .RN(
n1934), .Q(Op_MY[6]), .QN(n1876) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(n1957), .RN(
n1936), .Q(Op_MY[20]), .QN(n1860) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(n1959), .RN(
n1936), .Q(Op_MY[21]), .QN(n1866) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(n1958), .RN(
n1936), .Q(Op_MY[17]), .QN(n1878) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(n1958), .RN(
n1935), .Q(Op_MY[15]), .QN(n1865) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(n1949), .RN(
n1941), .Q(Op_MX[11]), .QN(n1867) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_7_ ( .D(n222), .CK(
n623), .RN(n1925), .Q(P_Sgf[7]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_19_ ( .D(n234), .CK(
n623), .RN(n1924), .Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_8_ ( .D(n223), .CK(
n1962), .RN(n1925), .Q(P_Sgf[8]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(n1958), .RN(
n1935), .Q(Op_MY[10]), .QN(n1858) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(n1955), .RN(
n1934), .Q(Op_MY[1]), .QN(n1862) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(n1956), .RN(
n1934), .Q(Op_MY[7]), .QN(n1863) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(n1958), .RN(
n1935), .Q(Op_MY[14]), .QN(n1854) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(n1958), .RN(
n1935), .Q(Op_MY[12]), .QN(n1852) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(n1954), .RN(
n1934), .Q(Op_MY[3]), .QN(n1873) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(n1958), .RN(
n1934), .Q(Op_MY[5]), .QN(n1853) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(n1958), .RN(
n1935), .Q(Op_MY[9]), .QN(n1856) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(n1957), .RN(
n1934), .Q(Op_MY[2]), .QN(n1857) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n214), .CK(n1962), .RN(n1932), .Q(
FSM_selector_C), .QN(n401) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(n1955), .RN(
n1936), .Q(n393), .QN(n1880) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(n1957), .RN(
n1937), .Q(Op_MY[27]), .QN(n1855) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(n1949), .RN(
n1940), .Q(Op_MX[3]), .QN(n1901) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(n1949), .RN(
n1941), .Q(Op_MX[19]), .QN(n1904) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(n1949), .RN(
n1941), .Q(Op_MX[15]), .QN(n1900) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_46_ ( .D(n261), .CK(
n1964), .RN(n1926), .Q(P_Sgf[46]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_30_ ( .D(n245), .CK(
n1961), .RN(n1923), .Q(P_Sgf[30]), .QN(n1911) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(n1949), .RN(
n1940), .Q(Op_MX[7]), .QN(n1907) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(n1948), .RN(
n1940), .Q(Op_MX[9]), .QN(n1881) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(n1951), .RN(
n1941), .Q(Op_MX[10]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(n1951), .RN(
n1940), .Q(Op_MX[5]), .QN(n1902) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n195), .CK(n1967),
.RN(n1930), .Q(Sgf_normalized_result[4]), .QN(n1905) );
CMPR32X2TS U405 ( .A(Op_MY[22]), .B(n1732), .C(n1731), .CO(n1737), .S(n1734)
);
CMPR32X2TS U406 ( .A(n649), .B(n1356), .C(n1355), .CO(n1192), .S(n1357) );
CMPR32X2TS U407 ( .A(Op_MY[13]), .B(n581), .C(n1701), .CO(mult_x_23_n71),
.S(mult_x_23_n72) );
CMPR32X2TS U408 ( .A(n440), .B(Op_MY[13]), .C(n1401), .CO(n1402), .S(n1379)
);
CMPR32X2TS U409 ( .A(Op_MY[13]), .B(n821), .C(n820), .CO(n822), .S(n819) );
CMPR32X2TS U410 ( .A(n595), .B(Op_MY[22]), .C(n661), .CO(n662), .S(n1773) );
CMPR32X2TS U411 ( .A(Op_MX[10]), .B(Op_MX[22]), .C(n654), .CO(n652), .S(n656) );
CMPR32X2TS U412 ( .A(n562), .B(n583), .C(n680), .CO(n661), .S(n1492) );
CMPR32X2TS U413 ( .A(Op_MY[8]), .B(Op_MY[20]), .C(n691), .CO(n680), .S(n1453) );
CMPR32X2TS U414 ( .A(n588), .B(n598), .C(n690), .CO(n691), .S(n1416) );
CMPR32X2TS U415 ( .A(n597), .B(n649), .C(n792), .CO(n690), .S(n1483) );
CMPR32X2TS U416 ( .A(n558), .B(n582), .C(n780), .CO(n792), .S(n1481) );
CMPR32X2TS U417 ( .A(Op_MY[4]), .B(Op_MY[16]), .C(n781), .CO(n780), .S(n1496) );
CMPR32X2TS U418 ( .A(Op_MX[5]), .B(Op_MX[17]), .C(n695), .CO(n694), .S(n805)
);
CMPR32X2TS U419 ( .A(n586), .B(n581), .C(n682), .CO(n781), .S(n1498) );
CMPR32X2TS U420 ( .A(Op_MX[3]), .B(Op_MX[15]), .C(n660), .CO(n783), .S(n1321) );
CMPR32X2TS U421 ( .A(Op_MY[2]), .B(n560), .C(n686), .CO(n682), .S(n1490) );
CMPR32X2TS U422 ( .A(n584), .B(Op_MY[13]), .C(n658), .CO(n686), .S(n1488) );
AOI221X2TS U423 ( .A0(n578), .A1(n542), .B0(n573), .B1(n569), .C0(n1510),
.Y(DP_OP_111J144_123_4462_n42) );
OR3X2TS U424 ( .A(underflow_flag), .B(overflow_flag), .C(n1595), .Y(n1828)
);
ADDFX1TS U425 ( .A(n649), .B(n598), .CI(n1697), .CO(mult_x_23_n42), .S(
mult_x_23_n43) );
CLKBUFX2TS U426 ( .A(n1501), .Y(n617) );
CLKBUFX2TS U427 ( .A(n1731), .Y(n625) );
CLKBUFX2TS U428 ( .A(n1748), .Y(n451) );
CLKBUFX2TS U429 ( .A(n1502), .Y(n466) );
CLKINVX3TS U430 ( .A(n400), .Y(n390) );
CLKINVX3TS U431 ( .A(n399), .Y(n391) );
CLKINVX3TS U432 ( .A(n398), .Y(n392) );
NOR2X1TS U433 ( .A(n580), .B(n845), .Y(mult_x_23_n190) );
CLKBUFX3TS U434 ( .A(n1751), .Y(n626) );
OA21X2TS U435 ( .A0(n910), .A1(n1849), .B0(FS_Module_state_reg[1]), .Y(n701)
);
NAND3X2TS U436 ( .A(FS_Module_state_reg[3]), .B(n1721), .C(n1868), .Y(n1160)
);
NAND2X2TS U437 ( .A(n1721), .B(n1514), .Y(n1566) );
CLKBUFX2TS U438 ( .A(n802), .Y(n1752) );
CLKBUFX3TS U439 ( .A(Op_MY[20]), .Y(n590) );
CLKBUFX3TS U440 ( .A(Op_MY[21]), .Y(n583) );
CLKBUFX2TS U441 ( .A(Op_MX[11]), .Y(n471) );
CLKBUFX3TS U442 ( .A(Op_MY[6]), .Y(n597) );
CLKBUFX3TS U443 ( .A(Op_MY[17]), .Y(n582) );
CLKBUFX3TS U444 ( .A(Op_MY[15]), .Y(n581) );
CLKAND2X2TS U445 ( .A(n1537), .B(Op_MX[21]), .Y(n397) );
INVX2TS U446 ( .A(n807), .Y(n687) );
AOI221X1TS U447 ( .A0(n391), .A1(Op_MY[17]), .B0(n493), .B1(n1878), .C0(n818), .Y(n820) );
AOI221X1TS U448 ( .A0(n392), .A1(Op_MY[21]), .B0(n491), .B1(n1866), .C0(n817), .Y(n821) );
AOI221X1TS U449 ( .A0(n457), .A1(n559), .B0(n1749), .B1(n520), .C0(n810),
.Y(n838) );
CLKAND2X2TS U450 ( .A(Op_MX[19]), .B(n1540), .Y(n396) );
CLKAND2X2TS U451 ( .A(n812), .B(n1900), .Y(n408) );
CLKAND2X2TS U452 ( .A(n1539), .B(Op_MX[5]), .Y(n432) );
CLKAND2X2TS U453 ( .A(n831), .B(n1901), .Y(n409) );
AOI221X2TS U454 ( .A0(n578), .A1(n634), .B0(n573), .B1(n571), .C0(n1507),
.Y(n1304) );
AOI221X1TS U455 ( .A0(n578), .A1(n540), .B0(n573), .B1(n1772), .C0(n1775),
.Y(n1405) );
AOI221X1TS U456 ( .A0(n542), .A1(n1416), .B0(n569), .B1(n554), .C0(n1323),
.Y(n1326) );
AOI221X1TS U457 ( .A0(n542), .A1(n536), .B0(n569), .B1(n555), .C0(n1311),
.Y(n1398) );
AOI221X1TS U458 ( .A0(n634), .A1(n534), .B0(n571), .B1(n551), .C0(n1310),
.Y(n1399) );
AOI221X1TS U459 ( .A0(n542), .A1(n1481), .B0(n569), .B1(n553), .C0(n1307),
.Y(n1407) );
AOI221X1TS U460 ( .A0(n1768), .A1(n1416), .B0(n571), .B1(n554), .C0(n1306),
.Y(n1408) );
AOI221X1TS U461 ( .A0(n634), .A1(n536), .B0(n571), .B1(n535), .C0(n1349),
.Y(n1392) );
AOI221X1TS U462 ( .A0(n540), .A1(n534), .B0(n628), .B1(n533), .C0(n1348),
.Y(n1393) );
AOI221X1TS U463 ( .A0(n540), .A1(n526), .B0(n628), .B1(n554), .C0(n1347),
.Y(n1386) );
AOI221X1TS U464 ( .A0(n634), .A1(n518), .B0(n571), .B1(n553), .C0(n1346),
.Y(n1388) );
OAI221X1TS U465 ( .A0(n1416), .A1(n642), .B0(n554), .B1(n503), .C0(n793),
.Y(n794) );
OAI221X1TS U466 ( .A0(n1481), .A1(n1770), .B0(n553), .B1(n501), .C0(n791),
.Y(n795) );
AOI221X1TS U467 ( .A0(n540), .A1(n567), .B0(n628), .B1(n624), .C0(n797), .Y(
n823) );
AOI221X1TS U468 ( .A0(n610), .A1(n526), .B0(n1776), .B1(n554), .C0(n798),
.Y(n824) );
CLKAND2X2TS U469 ( .A(n1509), .B(n687), .Y(n413) );
CLKAND2X2TS U470 ( .A(n1506), .B(n697), .Y(n433) );
CLKAND2X2TS U471 ( .A(n1051), .B(n785), .Y(n435) );
INVX2TS U472 ( .A(n805), .Y(n785) );
OAI221X1TS U473 ( .A0(n645), .A1(n447), .B0(n1877), .B1(n1702), .C0(n450),
.Y(mult_x_23_n207) );
OAI221X1TS U474 ( .A0(Op_MY[18]), .A1(n497), .B0(n1879), .B1(n1700), .C0(
n1494), .Y(mult_x_23_n183) );
AOI221X1TS U475 ( .A0(n390), .A1(n590), .B0(n608), .B1(n1860), .C0(n1378),
.Y(n1401) );
OAI221X1TS U476 ( .A0(Op_MY[17]), .A1(n495), .B0(n1878), .B1(n487), .C0(
n1468), .Y(mult_x_23_n170) );
AOI221X1TS U477 ( .A0(n457), .A1(n596), .B0(n544), .B1(n477), .C0(n843), .Y(
n1358) );
OAI221X1TS U478 ( .A0(n563), .A1(n466), .B0(n524), .B1(n617), .C0(n1354),
.Y(mult_x_55_n186) );
OAI221X1TS U479 ( .A0(n589), .A1(n515), .B0(n442), .B1(n626), .C0(n1431),
.Y(mult_x_55_n174) );
OAI221X1TS U480 ( .A0(n596), .A1(n546), .B0(n477), .B1(n489), .C0(n1341),
.Y(mult_x_55_n199) );
OAI221X1TS U481 ( .A0(Op_MY[6]), .A1(n515), .B0(n1876), .B1(n626), .C0(n1495), .Y(mult_x_55_n175) );
AOI221X1TS U482 ( .A0(n465), .A1(n648), .B0(n548), .B1(n1875), .C0(n1417),
.Y(n1428) );
OAI221X1TS U483 ( .A0(n563), .A1(n545), .B0(n524), .B1(n488), .C0(n1339),
.Y(mult_x_55_n200) );
OAI221X1TS U484 ( .A0(n559), .A1(n515), .B0(n520), .B1(n1751), .C0(n1487),
.Y(mult_x_55_n176) );
OAI221X1TS U485 ( .A0(n480), .A1(n505), .B0(n481), .B1(n619), .C0(n1332),
.Y(mult_x_55_n213) );
OAI221X1TS U486 ( .A0(Op_MY[6]), .A1(n1502), .B0(n1876), .B1(n1501), .C0(
n1479), .Y(mult_x_55_n189) );
NAND3XLTS U487 ( .A(Op_MX[10]), .B(n1867), .C(Op_MX[9]), .Y(n404) );
OAI221X1TS U488 ( .A0(Op_MY[17]), .A1(n497), .B0(n1878), .B1(n644), .C0(
n1371), .Y(mult_x_23_n184) );
OAI221X1TS U489 ( .A0(n393), .A1(n509), .B0(n1880), .B1(n483), .C0(n1484),
.Y(mult_x_23_n196) );
OAI221X1TS U490 ( .A0(n561), .A1(n495), .B0(n440), .B1(n487), .C0(n666), .Y(
mult_x_23_n173) );
OAI221X1TS U491 ( .A0(Op_MY[18]), .A1(n509), .B0(n1879), .B1(n483), .C0(
n1376), .Y(mult_x_23_n197) );
OAI221X1TS U492 ( .A0(Op_MY[21]), .A1(n507), .B0(n1866), .B1(n450), .C0(
n1469), .Y(mult_x_23_n209) );
OAI221X1TS U493 ( .A0(n590), .A1(n507), .B0(n1860), .B1(n450), .C0(n1351),
.Y(mult_x_23_n210) );
AOI221X1TS U494 ( .A0(n390), .A1(Op_MY[15]), .B0(n608), .B1(n1865), .C0(n846), .Y(n1374) );
AOI221X1TS U495 ( .A0(n391), .A1(Op_MY[13]), .B0(n493), .B1(n1859), .C0(n847), .Y(n1373) );
AOI221X1TS U496 ( .A0(n463), .A1(Op_MY[17]), .B0(n1703), .B1(n1878), .C0(
n813), .Y(n1421) );
CLKAND2X2TS U497 ( .A(n1542), .B(Op_MX[17]), .Y(n395) );
CLKAND2X2TS U498 ( .A(Op_MX[15]), .B(n812), .Y(n426) );
OAI221X1TS U499 ( .A0(n559), .A1(n1502), .B0(n520), .B1(n1501), .C0(n1330),
.Y(mult_x_55_n190) );
OAI221X1TS U500 ( .A0(n589), .A1(n546), .B0(n442), .B1(n489), .C0(n1474),
.Y(mult_x_55_n202) );
OAI221X1TS U501 ( .A0(n478), .A1(n470), .B0(n479), .B1(n1748), .C0(n1442),
.Y(mult_x_55_n166) );
AOI221X1TS U502 ( .A0(n391), .A1(n645), .B0(n493), .B1(n1877), .C0(n1191),
.Y(n1355) );
OAI221X1TS U503 ( .A0(Op_MY[18]), .A1(n495), .B0(n1879), .B1(n487), .C0(
n1473), .Y(mult_x_23_n169) );
OAI221X1TS U504 ( .A0(Op_MY[21]), .A1(n497), .B0(n1866), .B1(n644), .C0(
n1352), .Y(mult_x_23_n180) );
OAI221X1TS U505 ( .A0(n393), .A1(n495), .B0(n1880), .B1(n487), .C0(n1385),
.Y(mult_x_23_n168) );
OAI221X1TS U506 ( .A0(n645), .A1(n497), .B0(n1877), .B1(n1700), .C0(n400),
.Y(mult_x_23_n179) );
OAI221X1TS U507 ( .A0(Op_MY[6]), .A1(n546), .B0(n1876), .B1(n489), .C0(n1325), .Y(mult_x_55_n203) );
OAI221X1TS U508 ( .A0(n563), .A1(n505), .B0(n524), .B1(n619), .C0(n1480),
.Y(mult_x_55_n215) );
OAI221X1TS U509 ( .A0(n648), .A1(n505), .B0(n1875), .B1(n619), .C0(n1314),
.Y(mult_x_55_n216) );
AOI221X1TS U510 ( .A0(n612), .A1(Op_MY[6]), .B0(n538), .B1(n1876), .C0(n900),
.Y(n1335) );
AOI221X1TS U511 ( .A0(n465), .A1(n587), .B0(n548), .B1(n441), .C0(n898), .Y(
n1337) );
AOI221X1TS U512 ( .A0(n569), .A1(n621), .B0(n542), .B1(n1778), .C0(n902),
.Y(n907) );
AOI221X1TS U513 ( .A0(n569), .A1(n527), .B0(n542), .B1(n528), .C0(n1303),
.Y(n1318) );
OAI221X1TS U514 ( .A0(n1773), .A1(n643), .B0(n527), .B1(n503), .C0(n1493),
.Y(DP_OP_111J144_123_4462_n219) );
OAI221X1TS U515 ( .A0(n534), .A1(n550), .B0(n533), .B1(n1779), .C0(n1403),
.Y(DP_OP_111J144_123_4462_n235) );
OAI221X1TS U516 ( .A0(n1483), .A1(n642), .B0(n535), .B1(n503), .C0(n1482),
.Y(DP_OP_111J144_123_4462_n223) );
OAI221X1TS U517 ( .A0(n567), .A1(n1770), .B0(n624), .B1(n501), .C0(n1396),
.Y(DP_OP_111J144_123_4462_n210) );
AOI221X1TS U518 ( .A0(n1768), .A1(n1490), .B0(n571), .B1(n557), .C0(n825),
.Y(n1343) );
AOI221X1TS U519 ( .A0(n610), .A1(n536), .B0(n1776), .B1(n555), .C0(n827),
.Y(n1381) );
AOI221X1TS U520 ( .A0(n540), .A1(n1498), .B0(n628), .B1(n516), .C0(n826),
.Y(n1383) );
OAI221X1TS U521 ( .A0(n596), .A1(n470), .B0(n477), .B1(n1748), .C0(n1362),
.Y(mult_x_55_n158) );
OAI221X1TS U522 ( .A0(n480), .A1(n515), .B0(n481), .B1(n626), .C0(n543), .Y(
mult_x_55_n170) );
OAI221X1TS U523 ( .A0(n648), .A1(n470), .B0(n1875), .B1(n1748), .C0(n1478),
.Y(mult_x_55_n160) );
OAI221X1TS U524 ( .A0(n480), .A1(n470), .B0(n481), .B1(n1748), .C0(n1363),
.Y(mult_x_55_n157) );
OAI221X1TS U525 ( .A0(n646), .A1(n497), .B0(n1864), .B1(n1700), .C0(n1461),
.Y(mult_x_23_n185) );
OAI221X1TS U526 ( .A0(Op_MY[15]), .A1(n496), .B0(n1865), .B1(n644), .C0(
n1463), .Y(mult_x_23_n186) );
OAI221X1TS U527 ( .A0(n646), .A1(n509), .B0(n1864), .B1(n483), .C0(n1452),
.Y(mult_x_23_n199) );
OAI221X1TS U528 ( .A0(Op_MY[15]), .A1(n509), .B0(n1865), .B1(n483), .C0(
n1455), .Y(mult_x_23_n200) );
OAI221X1TS U529 ( .A0(n443), .A1(n497), .B0(n444), .B1(n1700), .C0(n1438),
.Y(mult_x_23_n188) );
OAI221X1TS U530 ( .A0(n561), .A1(n509), .B0(n440), .B1(n483), .C0(n1370),
.Y(mult_x_23_n201) );
OAI221X1TS U531 ( .A0(n472), .A1(n496), .B0(n580), .B1(n644), .C0(n1444),
.Y(mult_x_23_n189) );
OAI221X1TS U532 ( .A0(n646), .A1(n507), .B0(n1864), .B1(n450), .C0(n1353),
.Y(mult_x_23_n214) );
AOI221X1TS U533 ( .A0(n392), .A1(Op_MY[13]), .B0(n491), .B1(n1859), .C0(n852), .Y(n859) );
AOI221X1TS U534 ( .A0(n463), .A1(n561), .B0(n448), .B1(n440), .C0(n853), .Y(
n858) );
OAI221X1TS U535 ( .A0(n443), .A1(n507), .B0(n1859), .B1(n450), .C0(n860),
.Y(n864) );
OAI221X1TS U536 ( .A0(n647), .A1(n1502), .B0(n1874), .B1(n1501), .C0(n1472),
.Y(mult_x_55_n191) );
OAI221X1TS U537 ( .A0(n587), .A1(n1502), .B0(n441), .B1(n617), .C0(n1491),
.Y(mult_x_55_n192) );
OAI221X1TS U538 ( .A0(n647), .A1(n546), .B0(n1874), .B1(n489), .C0(n1486),
.Y(mult_x_55_n205) );
OAI221X1TS U539 ( .A0(n585), .A1(n466), .B0(n475), .B1(n617), .C0(n1500),
.Y(mult_x_55_n194) );
OAI221X1TS U540 ( .A0(n478), .A1(n546), .B0(n479), .B1(n489), .C0(n1340),
.Y(mult_x_55_n207) );
OAI221X1TS U541 ( .A0(n559), .A1(n505), .B0(n520), .B1(n619), .C0(n1471),
.Y(mult_x_55_n219) );
OAI221X1TS U542 ( .A0(n630), .A1(n1502), .B0(n600), .B1(n1501), .C0(n1443),
.Y(mult_x_55_n195) );
OAI221X1TS U543 ( .A0(n647), .A1(n505), .B0(n1874), .B1(n619), .C0(n1334),
.Y(mult_x_55_n220) );
AOI221X1TS U544 ( .A0(n459), .A1(n585), .B0(n1485), .B1(n475), .C0(n879),
.Y(n887) );
AOI221X1TS U545 ( .A0(n612), .A1(n478), .B0(n538), .B1(n479), .C0(n880), .Y(
n886) );
OAI221X1TS U546 ( .A0(n585), .A1(n505), .B0(n475), .B1(n619), .C0(n888), .Y(
n891) );
CLKAND2X2TS U547 ( .A(Op_MX[3]), .B(n831), .Y(n394) );
CLKAND2X2TS U548 ( .A(Op_MX[0]), .B(Op_MX[1]), .Y(n411) );
OAI221X1TS U549 ( .A0(n528), .A1(n512), .B0(n552), .B1(n1415), .C0(n1412),
.Y(DP_OP_111J144_123_4462_n177) );
OAI221X1TS U550 ( .A0(n522), .A1(n512), .B0(n556), .B1(n1415), .C0(n1411),
.Y(DP_OP_111J144_123_4462_n178) );
OAI221X1TS U551 ( .A0(n1453), .A1(n512), .B0(n533), .B1(n638), .C0(n1410),
.Y(DP_OP_111J144_123_4462_n179) );
OAI221X1TS U552 ( .A0(n1416), .A1(n512), .B0(n554), .B1(n1415), .C0(n1414),
.Y(DP_OP_111J144_123_4462_n180) );
OAI221X1TS U553 ( .A0(n536), .A1(n513), .B0(n555), .B1(n638), .C0(n1404),
.Y(DP_OP_111J144_123_4462_n181) );
OAI221X1TS U554 ( .A0(n518), .A1(n513), .B0(n553), .B1(n638), .C0(n1397),
.Y(DP_OP_111J144_123_4462_n182) );
OAI221X1TS U555 ( .A0(n1496), .A1(n513), .B0(n624), .B1(n638), .C0(n1406),
.Y(DP_OP_111J144_123_4462_n183) );
OAI221X1TS U556 ( .A0(n565), .A1(n513), .B0(n516), .B1(n1415), .C0(n1315),
.Y(DP_OP_111J144_123_4462_n184) );
OAI221X1TS U557 ( .A0(n532), .A1(n513), .B0(n557), .B1(n1415), .C0(n1313),
.Y(DP_OP_111J144_123_4462_n185) );
OAI221X1TS U558 ( .A0(n1490), .A1(n1477), .B0(n557), .B1(n499), .C0(n1476),
.Y(DP_OP_111J144_123_4462_n198) );
OAI221X1TS U559 ( .A0(n1490), .A1(n1770), .B0(n557), .B1(n501), .C0(n1489),
.Y(DP_OP_111J144_123_4462_n212) );
OAI221X1TS U560 ( .A0(n1490), .A1(n643), .B0(n557), .B1(n503), .C0(n1380),
.Y(DP_OP_111J144_123_4462_n227) );
AOI221X1TS U561 ( .A0(n610), .A1(n565), .B0(n1776), .B1(n516), .C0(n779),
.Y(n1060) );
AOI221X1TS U562 ( .A0(n540), .A1(n1508), .B0(n628), .B1(n594), .C0(n1053),
.Y(n1065) );
AOI221X1TS U563 ( .A0(n610), .A1(n532), .B0(n1776), .B1(n557), .C0(n1050),
.Y(n1055) );
OAI211X1TS U564 ( .A0(n1869), .A1(n444), .B0(Op_MX[13]), .C0(n580), .Y(n770)
);
OAI211X1TS U565 ( .A0(n1882), .A1(n475), .B0(Op_MX[1]), .C0(n600), .Y(n734)
);
CLKBUFX3TS U566 ( .A(n1527), .Y(n1832) );
NAND2BX2TS U567 ( .AN(n1459), .B(n1867), .Y(n1748) );
NOR2X4TS U568 ( .A(n1881), .B(n833), .Y(n1749) );
INVX2TS U569 ( .A(n841), .Y(n1502) );
NOR3X4TS U570 ( .A(Op_MX[13]), .B(Op_MX[14]), .C(n1900), .Y(n1703) );
OR2X1TS U571 ( .A(Op_MX[17]), .B(n856), .Y(n398) );
OR2X1TS U572 ( .A(Op_MX[21]), .B(n814), .Y(n399) );
OR2X1TS U573 ( .A(Op_MX[19]), .B(n845), .Y(n400) );
INVX2TS U574 ( .A(n621), .Y(n627) );
INVX2TS U575 ( .A(n622), .Y(n1778) );
OR2X1TS U576 ( .A(n1590), .B(n401), .Y(n402) );
OR2X1TS U577 ( .A(n401), .B(n702), .Y(n403) );
CLKBUFX3TS U578 ( .A(clk), .Y(n777) );
OR3X1TS U579 ( .A(n807), .B(n656), .C(n655), .Y(n405) );
OR2X1TS U580 ( .A(FSM_selector_C), .B(n1590), .Y(n406) );
OR3X1TS U581 ( .A(Op_MX[10]), .B(Op_MX[9]), .C(n1867), .Y(n407) );
OR2X1TS U582 ( .A(Op_MX[1]), .B(n1882), .Y(n410) );
OR2X1TS U583 ( .A(n1328), .B(n1781), .Y(n412) );
OR2X1TS U584 ( .A(n807), .B(n806), .Y(n414) );
OR3X1TS U585 ( .A(Op_MX[1]), .B(Op_MX[2]), .C(n1901), .Y(n415) );
OR3X1TS U586 ( .A(n805), .B(n698), .C(n697), .Y(n416) );
OR2X1TS U587 ( .A(Op_MX[3]), .B(n1515), .Y(n417) );
OR2X1TS U588 ( .A(Op_MX[5]), .B(n884), .Y(n418) );
OR2X1TS U589 ( .A(n1907), .B(n1462), .Y(n419) );
OR2X1TS U590 ( .A(Op_MX[7]), .B(n1462), .Y(n420) );
OR2X1TS U591 ( .A(Op_MX[13]), .B(n1869), .Y(n421) );
OR3X1TS U592 ( .A(n903), .B(n688), .C(n687), .Y(n422) );
AND3X1TS U593 ( .A(Op_MX[16]), .B(Op_MX[15]), .C(n1903), .Y(n423) );
OR2X1TS U594 ( .A(n1903), .B(n856), .Y(n424) );
OR2X1TS U595 ( .A(n1904), .B(n845), .Y(n425) );
OR2X1TS U596 ( .A(Op_MX[15]), .B(n1594), .Y(n427) );
OR2X1TS U597 ( .A(n1906), .B(n814), .Y(n428) );
AND3X1TS U598 ( .A(Op_MX[20]), .B(Op_MX[19]), .C(n1906), .Y(n429) );
OR2X1TS U599 ( .A(Op_MX[9]), .B(n833), .Y(n430) );
AND3X1TS U600 ( .A(Op_MX[4]), .B(Op_MX[3]), .C(n1902), .Y(n431) );
OR2X1TS U601 ( .A(n805), .B(n804), .Y(n434) );
OR2X1TS U602 ( .A(n1321), .B(n722), .Y(n436) );
AO21X1TS U603 ( .A0(n662), .A1(Op_MY[11]), .B0(n572), .Y(n437) );
AND2X2TS U604 ( .A(n471), .B(n652), .Y(n438) );
OR2X1TS U605 ( .A(Op_MY[11]), .B(n662), .Y(n439) );
INVX2TS U606 ( .A(Op_MY[14]), .Y(n440) );
INVX2TS U607 ( .A(Op_MY[3]), .Y(n441) );
INVX2TS U608 ( .A(Op_MY[7]), .Y(n442) );
INVX2TS U609 ( .A(n1859), .Y(n443) );
INVX2TS U610 ( .A(n443), .Y(n444) );
INVX2TS U611 ( .A(n404), .Y(n445) );
INVX2TS U612 ( .A(n404), .Y(n446) );
INVX2TS U613 ( .A(n1703), .Y(n447) );
INVX2TS U614 ( .A(n447), .Y(n448) );
INVX2TS U615 ( .A(n408), .Y(n449) );
INVX2TS U616 ( .A(n408), .Y(n450) );
INVX2TS U617 ( .A(n421), .Y(n452) );
INVX2TS U618 ( .A(n421), .Y(n453) );
INVX2TS U619 ( .A(n411), .Y(n454) );
INVX2TS U620 ( .A(n411), .Y(n455) );
INVX2TS U621 ( .A(n430), .Y(n456) );
INVX2TS U622 ( .A(n430), .Y(n457) );
INVX2TS U623 ( .A(n418), .Y(n458) );
INVX2TS U624 ( .A(n418), .Y(n459) );
INVX2TS U625 ( .A(n410), .Y(n460) );
INVX2TS U626 ( .A(n410), .Y(n461) );
INVX2TS U627 ( .A(n427), .Y(n462) );
INVX2TS U628 ( .A(n427), .Y(n463) );
INVX2TS U629 ( .A(n420), .Y(n464) );
INVX2TS U630 ( .A(n420), .Y(n465) );
INVX2TS U631 ( .A(n1541), .Y(n467) );
INVX2TS U632 ( .A(n1541), .Y(n468) );
INVX2TS U633 ( .A(n1229), .Y(n469) );
INVX2TS U634 ( .A(n1229), .Y(n470) );
INVX2TS U635 ( .A(n1852), .Y(n472) );
INVX2TS U636 ( .A(n1852), .Y(n473) );
INVX2TS U637 ( .A(Op_MY[1]), .Y(n474) );
INVX2TS U638 ( .A(Op_MY[1]), .Y(n475) );
INVX2TS U639 ( .A(Op_MY[10]), .Y(n476) );
INVX2TS U640 ( .A(Op_MY[10]), .Y(n477) );
INVX2TS U641 ( .A(n1857), .Y(n478) );
INVX2TS U642 ( .A(n478), .Y(n479) );
INVX2TS U643 ( .A(n1872), .Y(n480) );
INVX2TS U644 ( .A(n480), .Y(n481) );
INVX2TS U645 ( .A(n423), .Y(n482) );
INVX2TS U646 ( .A(n423), .Y(n483) );
INVX2TS U647 ( .A(n407), .Y(n484) );
INVX2TS U648 ( .A(n407), .Y(n485) );
INVX2TS U649 ( .A(n429), .Y(n486) );
INVX2TS U650 ( .A(n429), .Y(n487) );
INVX2TS U651 ( .A(n431), .Y(n488) );
INVX2TS U652 ( .A(n431), .Y(n489) );
INVX2TS U653 ( .A(n424), .Y(n490) );
INVX2TS U654 ( .A(n424), .Y(n491) );
INVX2TS U655 ( .A(n428), .Y(n492) );
INVX2TS U656 ( .A(n428), .Y(n493) );
INVX2TS U657 ( .A(n397), .Y(n494) );
INVX2TS U658 ( .A(n397), .Y(n495) );
INVX2TS U659 ( .A(n396), .Y(n496) );
INVX2TS U660 ( .A(n396), .Y(n497) );
INVX2TS U661 ( .A(n413), .Y(n498) );
INVX2TS U662 ( .A(n413), .Y(n499) );
INVX2TS U663 ( .A(n433), .Y(n500) );
INVX2TS U664 ( .A(n433), .Y(n501) );
INVX2TS U665 ( .A(n435), .Y(n502) );
INVX2TS U666 ( .A(n435), .Y(n503) );
INVX2TS U667 ( .A(n394), .Y(n504) );
INVX2TS U668 ( .A(n394), .Y(n505) );
INVX2TS U669 ( .A(n426), .Y(n506) );
INVX2TS U670 ( .A(n426), .Y(n507) );
INVX2TS U671 ( .A(n395), .Y(n508) );
INVX2TS U672 ( .A(n395), .Y(n509) );
INVX2TS U673 ( .A(n406), .Y(n510) );
INVX2TS U674 ( .A(n406), .Y(n511) );
INVX2TS U675 ( .A(n1137), .Y(n512) );
INVX2TS U676 ( .A(n1137), .Y(n513) );
INVX2TS U677 ( .A(n1752), .Y(n514) );
INVX2TS U678 ( .A(n1752), .Y(n515) );
INVX2TS U679 ( .A(n1498), .Y(n516) );
INVX2TS U680 ( .A(n1481), .Y(n517) );
INVX2TS U681 ( .A(n517), .Y(n518) );
INVX2TS U682 ( .A(Op_MY[5]), .Y(n519) );
INVX2TS U683 ( .A(Op_MY[5]), .Y(n520) );
INVX2TS U684 ( .A(n1492), .Y(n521) );
INVX2TS U685 ( .A(n521), .Y(n522) );
INVX2TS U686 ( .A(Op_MY[9]), .Y(n523) );
INVX2TS U687 ( .A(Op_MY[9]), .Y(n524) );
INVX2TS U688 ( .A(n1416), .Y(n525) );
INVX2TS U689 ( .A(n525), .Y(n526) );
INVX2TS U690 ( .A(n1773), .Y(n527) );
INVX2TS U691 ( .A(n527), .Y(n528) );
INVX2TS U692 ( .A(n1488), .Y(n529) );
INVX2TS U693 ( .A(n529), .Y(n530) );
INVX2TS U694 ( .A(n1490), .Y(n531) );
INVX2TS U695 ( .A(n531), .Y(n532) );
INVX2TS U696 ( .A(n1453), .Y(n533) );
INVX2TS U697 ( .A(n533), .Y(n534) );
INVX2TS U698 ( .A(n1483), .Y(n535) );
INVX2TS U699 ( .A(n535), .Y(n536) );
INVX2TS U700 ( .A(n415), .Y(n537) );
INVX2TS U701 ( .A(n415), .Y(n538) );
INVX2TS U702 ( .A(n434), .Y(n539) );
INVX2TS U703 ( .A(n434), .Y(n540) );
INVX2TS U704 ( .A(n414), .Y(n541) );
INVX2TS U705 ( .A(n414), .Y(n542) );
INVX2TS U706 ( .A(n1749), .Y(n543) );
INVX2TS U707 ( .A(n543), .Y(n544) );
INVX2TS U708 ( .A(n432), .Y(n545) );
INVX2TS U709 ( .A(n432), .Y(n546) );
INVX2TS U710 ( .A(n419), .Y(n547) );
INVX2TS U711 ( .A(n419), .Y(n548) );
INVX2TS U712 ( .A(n1043), .Y(n549) );
INVX2TS U713 ( .A(n1043), .Y(n550) );
INVX2TS U714 ( .A(n1453), .Y(n551) );
INVX2TS U715 ( .A(n1773), .Y(n552) );
INVX2TS U716 ( .A(n1481), .Y(n553) );
INVX2TS U717 ( .A(n1416), .Y(n554) );
INVX2TS U718 ( .A(n1483), .Y(n555) );
INVX2TS U719 ( .A(n1492), .Y(n556) );
INVX2TS U720 ( .A(n1490), .Y(n557) );
INVX2TS U721 ( .A(n1853), .Y(n558) );
INVX2TS U722 ( .A(n1853), .Y(n559) );
INVX2TS U723 ( .A(n1854), .Y(n560) );
INVX2TS U724 ( .A(n1854), .Y(n561) );
INVX2TS U725 ( .A(n1856), .Y(n562) );
INVX2TS U726 ( .A(n1856), .Y(n563) );
INVX2TS U727 ( .A(n1498), .Y(n564) );
INVX2TS U728 ( .A(n564), .Y(n565) );
INVX2TS U729 ( .A(n1496), .Y(n566) );
INVX2TS U730 ( .A(n566), .Y(n567) );
INVX2TS U731 ( .A(n422), .Y(n568) );
INVX2TS U732 ( .A(n422), .Y(n569) );
INVX2TS U733 ( .A(n416), .Y(n570) );
INVX2TS U734 ( .A(n416), .Y(n571) );
INVX2TS U735 ( .A(n439), .Y(n572) );
INVX2TS U736 ( .A(n439), .Y(n573) );
INVX2TS U737 ( .A(n405), .Y(n574) );
INVX2TS U738 ( .A(n405), .Y(n575) );
INVX2TS U739 ( .A(n1488), .Y(n576) );
INVX2TS U740 ( .A(n572), .Y(n577) );
INVX2TS U741 ( .A(n572), .Y(n578) );
INVX2TS U742 ( .A(Op_MY[12]), .Y(n579) );
INVX2TS U743 ( .A(Op_MY[12]), .Y(n580) );
INVX2TS U744 ( .A(n1862), .Y(n584) );
INVX2TS U745 ( .A(n1862), .Y(n585) );
INVX2TS U746 ( .A(n1873), .Y(n586) );
INVX2TS U747 ( .A(n1873), .Y(n587) );
INVX2TS U748 ( .A(n1863), .Y(n588) );
INVX2TS U749 ( .A(n1863), .Y(n589) );
INVX2TS U750 ( .A(n438), .Y(n591) );
INVX2TS U751 ( .A(n438), .Y(n592) );
INVX2TS U752 ( .A(n1508), .Y(n593) );
INVX2TS U753 ( .A(n1508), .Y(n594) );
INVX2TS U754 ( .A(n1858), .Y(n595) );
INVX2TS U755 ( .A(n1858), .Y(n596) );
INVX2TS U756 ( .A(n1880), .Y(n598) );
INVX2TS U757 ( .A(n630), .Y(n599) );
INVX2TS U758 ( .A(Op_MY[0]), .Y(n600) );
INVX2TS U759 ( .A(n402), .Y(n601) );
INVX2TS U760 ( .A(n402), .Y(n602) );
INVX2TS U761 ( .A(n402), .Y(n603) );
INVX2TS U762 ( .A(n403), .Y(n604) );
INVX2TS U763 ( .A(n403), .Y(n605) );
INVX2TS U764 ( .A(n403), .Y(n606) );
NOR2X1TS U765 ( .A(n645), .B(n468), .Y(mult_x_23_n151) );
NOR2X1TS U766 ( .A(n579), .B(n625), .Y(mult_x_23_n162) );
OAI221X1TS U767 ( .A0(n645), .A1(n494), .B0(n1877), .B1(n486), .C0(n399),
.Y(n1697) );
OAI221X1TS U768 ( .A0(Op_MY[20]), .A1(n496), .B0(n1860), .B1(n644), .C0(
n1699), .Y(n1701) );
OAI221X1TS U769 ( .A0(n582), .A1(n508), .B0(n1878), .B1(n482), .C0(n668),
.Y(mult_x_23_n198) );
OAI221X1TS U770 ( .A0(n597), .A1(n469), .B0(n1876), .B1(n451), .C0(n670),
.Y(mult_x_55_n162) );
OAI221X1TS U771 ( .A0(n581), .A1(n494), .B0(n1865), .B1(n486), .C0(n700),
.Y(mult_x_23_n172) );
OAI221X1TS U772 ( .A0(n648), .A1(n514), .B0(n1875), .B1(n626), .C0(n669),
.Y(mult_x_55_n173) );
OAI221X1TS U773 ( .A0(n647), .A1(n469), .B0(n1874), .B1(n451), .C0(n674),
.Y(mult_x_55_n164) );
OAI221X1TS U774 ( .A0(Op_MY[20]), .A1(n494), .B0(n1860), .B1(n486), .C0(n739), .Y(mult_x_23_n167) );
OAI221X1TS U775 ( .A0(n443), .A1(n508), .B0(n444), .B1(n482), .C0(n667), .Y(
mult_x_23_n202) );
OAI221X1TS U776 ( .A0(n586), .A1(n514), .B0(n441), .B1(n626), .C0(n675), .Y(
mult_x_55_n178) );
OAI221X1TS U777 ( .A0(n478), .A1(n514), .B0(n1857), .B1(n626), .C0(n676),
.Y(mult_x_55_n179) );
OAI221X1TS U778 ( .A0(n584), .A1(n545), .B0(n474), .B1(n488), .C0(n678), .Y(
mult_x_55_n208) );
OAI221X1TS U779 ( .A0(n558), .A1(n545), .B0(n519), .B1(n488), .C0(n677), .Y(
mult_x_55_n204) );
OAI221X1TS U780 ( .A0(n530), .A1(n641), .B0(n529), .B1(n498), .C0(n693), .Y(
DP_OP_111J144_123_4462_n199) );
OAI221X1TS U781 ( .A0(n530), .A1(n640), .B0(n529), .B1(n500), .C0(n699), .Y(
DP_OP_111J144_123_4462_n213) );
OAI221X1TS U782 ( .A0(n572), .A1(n638), .B0(n577), .B1(n512), .C0(n679), .Y(
DP_OP_111J144_123_4462_n175) );
OAI221X1TS U783 ( .A0(n565), .A1(n641), .B0(n564), .B1(n498), .C0(n689), .Y(
DP_OP_111J144_123_4462_n197) );
OAI221X1TS U784 ( .A0(n526), .A1(n549), .B0(n525), .B1(n639), .C0(n692), .Y(
DP_OP_111J144_123_4462_n236) );
OAI221X1TS U785 ( .A0(n522), .A1(n549), .B0(n521), .B1(n639), .C0(n681), .Y(
DP_OP_111J144_123_4462_n234) );
OAI221X1TS U786 ( .A0(n645), .A1(n506), .B0(n1877), .B1(n449), .C0(n1704),
.Y(n1705) );
OAI32X1TS U787 ( .A0(n1843), .A1(n1845), .A2(n1035), .B0(n1888), .B1(n1832),
.Y(n253) );
OAI211XLTS U788 ( .A0(n1833), .A1(Sgf_operation_RECURSIVE_EVEN1_Q_left[22]),
.B0(n1832), .C0(n1831), .Y(n1834) );
OAI221X1TS U789 ( .A0(n645), .A1(n508), .B0(n1877), .B1(n482), .C0(n398),
.Y(mult_x_23_n193) );
OAI221X1TS U790 ( .A0(n583), .A1(n508), .B0(n1866), .B1(n482), .C0(n1364),
.Y(mult_x_23_n194) );
OAI221X1TS U791 ( .A0(n595), .A1(n466), .B0(n476), .B1(n1501), .C0(n1365),
.Y(mult_x_55_n185) );
OAI221X1TS U792 ( .A0(n528), .A1(n641), .B0(n552), .B1(n498), .C0(n1333),
.Y(DP_OP_111J144_123_4462_n191) );
OAI221X1TS U793 ( .A0(n582), .A1(n506), .B0(n1878), .B1(n449), .C0(n1460),
.Y(mult_x_23_n213) );
OAI221X1TS U794 ( .A0(n586), .A1(n545), .B0(n441), .B1(n488), .C0(n1456),
.Y(mult_x_55_n206) );
OAI221X1TS U795 ( .A0(n528), .A1(n640), .B0(n552), .B1(n500), .C0(n1458),
.Y(DP_OP_111J144_123_4462_n204) );
OAI221X1TS U796 ( .A0(n518), .A1(n641), .B0(n517), .B1(n498), .C0(n1464),
.Y(DP_OP_111J144_123_4462_n195) );
OAI211XLTS U797 ( .A0(Sgf_normalized_result[9]), .A1(n1802), .B0(n1820),
.C0(n1801), .Y(n1803) );
NOR2X2TS U798 ( .A(n1891), .B(n1798), .Y(n1802) );
OAI211XLTS U799 ( .A0(Sgf_normalized_result[13]), .A1(n1808), .B0(n1820),
.C0(n1807), .Y(n1809) );
NOR2X2TS U800 ( .A(n1893), .B(n1804), .Y(n1808) );
OAI211XLTS U801 ( .A0(Sgf_normalized_result[17]), .A1(n1814), .B0(n1820),
.C0(n1813), .Y(n1815) );
NOR2X2TS U802 ( .A(n1895), .B(n1810), .Y(n1814) );
OAI211XLTS U803 ( .A0(Sgf_normalized_result[21]), .A1(n1821), .B0(n1820),
.C0(n1819), .Y(n1822) );
NOR2X2TS U804 ( .A(n1897), .B(n1816), .Y(n1821) );
NOR2X2TS U805 ( .A(n1622), .B(n1838), .Y(n1836) );
NOR4X1TS U806 ( .A(n597), .B(n648), .C(n595), .D(n480), .Y(n1555) );
INVX2TS U807 ( .A(n425), .Y(n607) );
INVX2TS U808 ( .A(n425), .Y(n608) );
INVX2TS U809 ( .A(n436), .Y(n609) );
INVX2TS U810 ( .A(n436), .Y(n610) );
CLKINVX3TS U811 ( .A(n701), .Y(n1588) );
INVX2TS U812 ( .A(n417), .Y(n611) );
INVX2TS U813 ( .A(n417), .Y(n612) );
INVX2TS U814 ( .A(n1485), .Y(n613) );
INVX2TS U815 ( .A(n613), .Y(n614) );
INVX2TS U816 ( .A(n412), .Y(n615) );
INVX2TS U817 ( .A(n412), .Y(n616) );
NOR3X6TS U818 ( .A(n1150), .B(n1870), .C(n1921), .Y(n1830) );
NOR3X2TS U819 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]), .C(
n1868), .Y(n912) );
NOR3X2TS U820 ( .A(Op_MX[5]), .B(Op_MX[6]), .C(n1907), .Y(n841) );
BUFX4TS U821 ( .A(n777), .Y(n1968) );
BUFX4TS U822 ( .A(clk), .Y(n1967) );
CLKBUFX3TS U823 ( .A(n1566), .Y(n1598) );
OAI21X2TS U824 ( .A0(Op_MX[7]), .A1(Op_MX[8]), .B0(n1512), .Y(n833) );
AOI21X2TS U825 ( .A0(Op_MX[14]), .A1(Op_MX[13]), .B0(n1543), .Y(n812) );
INVX2TS U826 ( .A(n409), .Y(n618) );
INVX2TS U827 ( .A(n409), .Y(n619) );
BUFX4TS U828 ( .A(clk), .Y(n1947) );
BUFX4TS U829 ( .A(clk), .Y(n1945) );
BUFX4TS U830 ( .A(clk), .Y(n1944) );
BUFX4TS U831 ( .A(clk), .Y(n1946) );
BUFX4TS U832 ( .A(n776), .Y(n620) );
BUFX4TS U833 ( .A(n776), .Y(n1949) );
CLKBUFX3TS U834 ( .A(clk), .Y(n776) );
INVX2TS U835 ( .A(n437), .Y(n621) );
INVX2TS U836 ( .A(n437), .Y(n622) );
BUFX4TS U837 ( .A(n778), .Y(n623) );
BUFX4TS U838 ( .A(n778), .Y(n1960) );
CLKBUFX3TS U839 ( .A(clk), .Y(n778) );
BUFX6TS U840 ( .A(n778), .Y(n1964) );
BUFX6TS U841 ( .A(n778), .Y(n1965) );
BUFX6TS U842 ( .A(n778), .Y(n1963) );
BUFX6TS U843 ( .A(n778), .Y(n1962) );
BUFX4TS U844 ( .A(n1952), .Y(n1970) );
BUFX6TS U845 ( .A(n778), .Y(n1971) );
BUFX6TS U846 ( .A(n776), .Y(n1966) );
BUFX6TS U847 ( .A(n777), .Y(n1969) );
BUFX6TS U848 ( .A(n777), .Y(n1959) );
BUFX6TS U849 ( .A(n777), .Y(n1955) );
BUFX6TS U850 ( .A(n776), .Y(n1952) );
BUFX6TS U851 ( .A(n776), .Y(n1948) );
BUFX6TS U852 ( .A(n776), .Y(n1953) );
BUFX6TS U853 ( .A(n776), .Y(n1951) );
BUFX6TS U854 ( .A(n777), .Y(n1958) );
BUFX6TS U855 ( .A(n777), .Y(n1957) );
BUFX6TS U856 ( .A(n777), .Y(n1956) );
BUFX6TS U857 ( .A(n777), .Y(n1954) );
NOR2X2TS U858 ( .A(n655), .B(n1331), .Y(n1137) );
INVX2TS U859 ( .A(n1496), .Y(n624) );
NOR2X2TS U860 ( .A(Op_MX[19]), .B(Op_MX[20]), .Y(n1537) );
NOR2X2TS U861 ( .A(Op_MX[17]), .B(Op_MX[18]), .Y(n1540) );
AOI21X2TS U862 ( .A0(Op_MX[2]), .A1(Op_MX[1]), .B0(n1538), .Y(n831) );
NOR3X2TS U863 ( .A(n663), .B(n664), .C(n1328), .Y(n1043) );
OAI221X1TS U864 ( .A0(n1492), .A1(n1477), .B0(n556), .B1(n499), .C0(n1454),
.Y(DP_OP_111J144_123_4462_n67) );
NOR2X1TS U865 ( .A(n593), .B(n1331), .Y(DP_OP_111J144_123_4462_n187) );
NOR2X2TS U866 ( .A(n1898), .B(n1819), .Y(n1825) );
CLKBUFX2TS U867 ( .A(n1772), .Y(n628) );
OAI211XLTS U868 ( .A0(Sgf_normalized_result[19]), .A1(n1817), .B0(n1820),
.C0(n1816), .Y(n1818) );
NOR2X2TS U869 ( .A(n1896), .B(n1813), .Y(n1817) );
OAI211XLTS U870 ( .A0(Sgf_normalized_result[15]), .A1(n1811), .B0(n1820),
.C0(n1810), .Y(n1812) );
NOR2X2TS U871 ( .A(n1894), .B(n1807), .Y(n1811) );
OAI211XLTS U872 ( .A0(Sgf_normalized_result[11]), .A1(n1805), .B0(n1820),
.C0(n1804), .Y(n1806) );
NOR2X2TS U873 ( .A(n1892), .B(n1801), .Y(n1805) );
OAI211XLTS U874 ( .A0(Sgf_normalized_result[7]), .A1(n1799), .B0(n1820),
.C0(n1798), .Y(n1800) );
NOR2X2TS U875 ( .A(n1890), .B(n1795), .Y(n1799) );
NOR2X2TS U876 ( .A(n1624), .B(n1841), .Y(n1839) );
NOR2X2TS U877 ( .A(n1602), .B(n1835), .Y(n1833) );
NOR2BX2TS U878 ( .AN(Sgf_operation_RECURSIVE_EVEN1_Q_left[14]), .B(n1034),
.Y(n1845) );
AOI222X4TS U879 ( .A0(Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .A1(n1605),
.B0(Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .B1(n1607), .C0(n1605),
.C1(n1607), .Y(n1034) );
NOR2X2TS U880 ( .A(Op_MX[15]), .B(Op_MX[16]), .Y(n1542) );
NOR2X2TS U881 ( .A(n1867), .B(n1459), .Y(n1229) );
OAI21X2TS U882 ( .A0(Op_MX[10]), .A1(Op_MX[9]), .B0(n1761), .Y(n1459) );
NOR2X2TS U883 ( .A(Op_MX[3]), .B(Op_MX[4]), .Y(n1539) );
CLKINVX3TS U884 ( .A(n701), .Y(n766) );
OAI22X2TS U885 ( .A0(beg_FSM), .A1(n1943), .B0(ack_FSM), .B1(n1148), .Y(
n1562) );
NAND2X2TS U886 ( .A(Op_MX[13]), .B(n1869), .Y(n862) );
OAI21X2TS U887 ( .A0(Op_MX[5]), .A1(Op_MX[6]), .B0(n1707), .Y(n1462) );
INVX2TS U888 ( .A(n629), .Y(n630) );
NOR2X2TS U889 ( .A(FS_Module_state_reg[1]), .B(n1921), .Y(n1721) );
CMPR32X4TS U890 ( .A(Op_MX[1]), .B(Op_MX[13]), .C(n721), .CO(n659), .S(n1328) );
OR2X1TS U891 ( .A(FSM_selector_C), .B(n702), .Y(n1036) );
INVX2TS U892 ( .A(n1036), .Y(n631) );
INVX2TS U893 ( .A(n1036), .Y(n632) );
INVX2TS U894 ( .A(n631), .Y(n765) );
CLKBUFX2TS U895 ( .A(n1413), .Y(n633) );
OAI21X2TS U896 ( .A0(Op_MX[11]), .A1(n652), .B0(n591), .Y(n1145) );
CLKBUFX2TS U897 ( .A(n1768), .Y(n634) );
INVX2TS U898 ( .A(n1564), .Y(n635) );
NAND2X2TS U899 ( .A(n912), .B(n1870), .Y(n1564) );
INVX2TS U900 ( .A(n1457), .Y(n636) );
NOR2X2TS U901 ( .A(n722), .B(n664), .Y(n1776) );
OAI21X2TS U902 ( .A0(n1328), .A1(n663), .B0(n1322), .Y(n722) );
NAND2X2TS U903 ( .A(n723), .B(n1328), .Y(n637) );
AOI21X2TS U904 ( .A0(n1882), .A1(n1869), .B0(n721), .Y(n723) );
NAND2BX2TS U905 ( .AN(n1331), .B(n655), .Y(n638) );
OAI21X2TS U906 ( .A0(n807), .A1(n656), .B0(n1146), .Y(n1331) );
CLKBUFX2TS U907 ( .A(n1779), .Y(n639) );
NAND2X2TS U908 ( .A(n903), .B(n1506), .Y(n640) );
AOI21X2TS U909 ( .A0(n698), .A1(n805), .B0(n696), .Y(n1506) );
CMPR32X4TS U910 ( .A(Op_MX[7]), .B(Op_MX[19]), .C(n684), .CO(n683), .S(n903)
);
INVX2TS U911 ( .A(n1510), .Y(n641) );
AOI21X2TS U912 ( .A0(n688), .A1(n903), .B0(n685), .Y(n1509) );
CLKAND2X2TS U913 ( .A(n1051), .B(n805), .Y(n1775) );
INVX2TS U914 ( .A(n1775), .Y(n642) );
INVX2TS U915 ( .A(n1775), .Y(n643) );
AOI21X2TS U916 ( .A0(n786), .A1(n1321), .B0(n784), .Y(n1051) );
NAND3X2TS U917 ( .A(Op_MX[17]), .B(Op_MX[18]), .C(n1904), .Y(n644) );
CLKBUFX3TS U918 ( .A(Op_MY[22]), .Y(n645) );
CLKBUFX3TS U919 ( .A(Op_MY[16]), .Y(n646) );
CLKBUFX3TS U920 ( .A(Op_MY[4]), .Y(n647) );
CLKBUFX3TS U921 ( .A(Op_MY[8]), .Y(n648) );
CLKBUFX3TS U922 ( .A(Op_MY[18]), .Y(n649) );
NOR2XLTS U923 ( .A(n477), .B(n1867), .Y(n1756) );
INVX2TS U924 ( .A(mult_x_23_n66), .Y(n1208) );
INVX2TS U925 ( .A(mult_x_55_n52), .Y(n1289) );
INVX2TS U926 ( .A(mult_x_23_n101), .Y(n1233) );
OAI21XLTS U927 ( .A0(n864), .A1(n863), .B0(n1300), .Y(n1277) );
INVX2TS U928 ( .A(mult_x_55_n94), .Y(n1227) );
INVX2TS U929 ( .A(mult_x_23_n45), .Y(n876) );
OAI21XLTS U930 ( .A0(n573), .A1(n592), .B0(n1789), .Y(n1788) );
INVX2TS U931 ( .A(DP_OP_111J144_123_4462_n57), .Y(n1119) );
INVX2TS U932 ( .A(DP_OP_111J144_123_4462_n114), .Y(n1092) );
OAI21XLTS U933 ( .A0(n1042), .A1(n1041), .B0(n1058), .Y(n1047) );
AOI211XLTS U934 ( .A0(n1898), .A1(n1819), .B0(n1825), .C0(n1643), .Y(n1621)
);
OAI211XLTS U935 ( .A0(Sgf_normalized_result[5]), .A1(n1796), .B0(n1820),
.C0(n1795), .Y(n1797) );
OAI21XLTS U936 ( .A0(n1825), .A1(Sgf_normalized_result[23]), .B0(n1824), .Y(
n1826) );
OAI31X1TS U937 ( .A0(FS_Module_state_reg[1]), .A1(n1851), .A2(n1850), .B0(
n401), .Y(n214) );
NOR2X1TS U938 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n1514) );
NAND3X2TS U939 ( .A(n1921), .B(n1514), .C(n1870), .Y(n651) );
CLKBUFX2TS U940 ( .A(n651), .Y(n738) );
BUFX3TS U941 ( .A(n738), .Y(n1933) );
BUFX3TS U942 ( .A(n738), .Y(n1938) );
INVX2TS U943 ( .A(rst), .Y(n1972) );
BUFX3TS U944 ( .A(n1972), .Y(n1922) );
BUFX3TS U945 ( .A(n1972), .Y(n1924) );
BUFX3TS U946 ( .A(n1972), .Y(n1925) );
BUFX3TS U947 ( .A(n738), .Y(n1935) );
BUFX3TS U948 ( .A(n738), .Y(n1934) );
BUFX3TS U949 ( .A(n651), .Y(n1928) );
BUFX3TS U950 ( .A(n1972), .Y(n1923) );
BUFX3TS U951 ( .A(n738), .Y(n1937) );
BUFX3TS U952 ( .A(n651), .Y(n1927) );
BUFX3TS U953 ( .A(n651), .Y(n1940) );
BUFX3TS U954 ( .A(n651), .Y(n1941) );
BUFX3TS U955 ( .A(n651), .Y(n1942) );
BUFX3TS U956 ( .A(n651), .Y(n1930) );
BUFX3TS U957 ( .A(n738), .Y(n1939) );
NOR2X1TS U958 ( .A(n599), .B(n580), .Y(n658) );
NOR2X1TS U959 ( .A(n1882), .B(n1869), .Y(n721) );
INVX2TS U960 ( .A(n1145), .Y(n655) );
CMPR32X2TS U961 ( .A(Op_MX[9]), .B(Op_MX[21]), .C(n653), .CO(n654), .S(n807)
);
NAND2X1TS U962 ( .A(n807), .B(n656), .Y(n1146) );
NAND2BX2TS U963 ( .AN(n1331), .B(n655), .Y(n1415) );
AOI21X4TS U964 ( .A0(n599), .A1(n579), .B0(n658), .Y(n1508) );
NOR2X4TS U965 ( .A(n1146), .B(n1145), .Y(n1413) );
AOI22X1TS U966 ( .A0(n1508), .A1(n1413), .B0(n574), .B1(n593), .Y(n657) );
OAI221XLTS U967 ( .A0(n530), .A1(n513), .B0(n576), .B1(n638), .C0(n657), .Y(
DP_OP_111J144_123_4462_n186) );
CMPR32X2TS U968 ( .A(Op_MX[2]), .B(Op_MX[14]), .C(n659), .CO(n660), .S(n663)
);
INVX2TS U969 ( .A(n1321), .Y(n664) );
NAND2X1TS U970 ( .A(n1328), .B(n663), .Y(n1322) );
OR2X2TS U971 ( .A(n1322), .B(n1321), .Y(n1779) );
AOI22X1TS U972 ( .A0(n621), .A1(n636), .B0(n610), .B1(n627), .Y(n665) );
OAI221XLTS U973 ( .A0(n1773), .A1(n550), .B0(n552), .B1(n639), .C0(n665),
.Y(DP_OP_111J144_123_4462_n233) );
AO21X1TS U974 ( .A0(Op_MX[20]), .A1(Op_MX[19]), .B0(n1537), .Y(n814) );
AOI22X1TS U975 ( .A0(n581), .A1(n391), .B0(n492), .B1(n1865), .Y(n666) );
AO21X1TS U976 ( .A0(Op_MX[16]), .A1(Op_MX[15]), .B0(n1542), .Y(n856) );
AOI22X1TS U977 ( .A0(n560), .A1(n392), .B0(n490), .B1(n440), .Y(n667) );
AOI22X1TS U978 ( .A0(n649), .A1(n392), .B0(n490), .B1(n1879), .Y(n668) );
NOR3X1TS U979 ( .A(Op_MX[7]), .B(Op_MX[8]), .C(n1881), .Y(n802) );
NAND2X1TS U980 ( .A(Op_MX[7]), .B(Op_MX[8]), .Y(n1512) );
NAND2BX2TS U981 ( .AN(n1512), .B(n1881), .Y(n1751) );
AOI22X1TS U982 ( .A0(n562), .A1(n456), .B0(n544), .B1(n523), .Y(n669) );
NAND2X1TS U983 ( .A(Op_MX[10]), .B(Op_MX[9]), .Y(n1761) );
AOI22X1TS U984 ( .A0(n558), .A1(n445), .B0(n484), .B1(n519), .Y(n670) );
NOR2X1TS U985 ( .A(n1869), .B(n580), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N0) );
NOR2XLTS U986 ( .A(Sgf_operation_RECURSIVE_EVEN1_left_N0), .B(n1884), .Y(
n673) );
NOR2X2TS U987 ( .A(n1869), .B(n1884), .Y(n1706) );
AOI22X1TS U988 ( .A0(Op_MY[13]), .A1(n452), .B0(n1706), .B1(n444), .Y(n671)
);
OAI21XLTS U989 ( .A0(n473), .A1(n862), .B0(n671), .Y(n672) );
OA21XLTS U990 ( .A0(n673), .A1(n672), .B0(n770), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N1) );
AOI22X1TS U991 ( .A0(n586), .A1(n445), .B0(n484), .B1(n441), .Y(n674) );
AOI22X1TS U992 ( .A0(Op_MY[4]), .A1(n456), .B0(n544), .B1(n1874), .Y(n675)
);
AOI22X1TS U993 ( .A0(n586), .A1(n456), .B0(n544), .B1(n441), .Y(n676) );
AO21X1TS U994 ( .A0(Op_MX[4]), .A1(Op_MX[3]), .B0(n1539), .Y(n884) );
NOR2X4TS U995 ( .A(n1902), .B(n884), .Y(n1485) );
AOI22X1TS U996 ( .A0(n597), .A1(n458), .B0(n614), .B1(n1876), .Y(n677) );
AOI22X1TS U997 ( .A0(Op_MY[2]), .A1(n458), .B0(n614), .B1(n1857), .Y(n678)
);
AOI22X1TS U998 ( .A0(n621), .A1(n574), .B0(n633), .B1(n1778), .Y(n679) );
AOI22X1TS U999 ( .A0(n528), .A1(n609), .B0(n636), .B1(n552), .Y(n681) );
CMPR32X2TS U1000 ( .A(Op_MX[8]), .B(Op_MX[20]), .C(n683), .CO(n653), .S(n688) );
NOR2XLTS U1001 ( .A(n903), .B(n688), .Y(n685) );
NAND2X2TS U1002 ( .A(n1509), .B(n807), .Y(n1477) );
NAND2X1TS U1003 ( .A(n903), .B(n688), .Y(n806) );
AOI22X1TS U1004 ( .A0(n532), .A1(n541), .B0(n568), .B1(n531), .Y(n689) );
AOI22X1TS U1005 ( .A0(n1453), .A1(n609), .B0(n636), .B1(n551), .Y(n692) );
AOI22X1TS U1006 ( .A0(n1508), .A1(n541), .B0(n568), .B1(n593), .Y(n693) );
CMPR32X2TS U1007 ( .A(Op_MX[6]), .B(Op_MX[18]), .C(n694), .CO(n684), .S(n698) );
NOR2XLTS U1008 ( .A(n805), .B(n698), .Y(n696) );
NAND2X2TS U1009 ( .A(n903), .B(n1506), .Y(n1770) );
INVX2TS U1010 ( .A(n903), .Y(n697) );
NAND2X1TS U1011 ( .A(n805), .B(n698), .Y(n904) );
NOR2X4TS U1012 ( .A(n903), .B(n904), .Y(n1768) );
AOI22X1TS U1013 ( .A0(n1508), .A1(n1768), .B0(n570), .B1(n593), .Y(n699) );
AOI22X1TS U1014 ( .A0(Op_MY[16]), .A1(n391), .B0(n492), .B1(n1864), .Y(n700)
);
NAND2X1TS U1015 ( .A(FS_Module_state_reg[3]), .B(n1868), .Y(n1150) );
NOR2X2TS U1016 ( .A(FS_Module_state_reg[0]), .B(n1150), .Y(n1849) );
AOI32X2TS U1017 ( .A0(FSM_add_overflow_flag), .A1(FS_Module_state_reg[1]),
.A2(n1849), .B0(n912), .B1(FS_Module_state_reg[1]), .Y(n1590) );
INVX2TS U1018 ( .A(n510), .Y(n769) );
NOR2X1TS U1019 ( .A(FS_Module_state_reg[3]), .B(n1868), .Y(n910) );
AOI22X1TS U1020 ( .A0(Sgf_normalized_result[6]), .A1(n1588), .B0(
Add_result[7]), .B1(n601), .Y(n704) );
NAND2X1TS U1021 ( .A(n701), .B(n1590), .Y(n702) );
AOI22X1TS U1022 ( .A0(Add_result[6]), .A1(n604), .B0(n631), .B1(P_Sgf[29]),
.Y(n703) );
OAI211XLTS U1023 ( .A0(n769), .A1(n1911), .B0(n704), .C0(n703), .Y(n197) );
AOI22X1TS U1024 ( .A0(Sgf_normalized_result[8]), .A1(n766), .B0(
Add_result[9]), .B1(n601), .Y(n706) );
AOI22X1TS U1025 ( .A0(Add_result[8]), .A1(n604), .B0(n632), .B1(P_Sgf[31]),
.Y(n705) );
OAI211XLTS U1026 ( .A0(n769), .A1(n1910), .B0(n706), .C0(n705), .Y(n199) );
AOI22X1TS U1027 ( .A0(Sgf_normalized_result[10]), .A1(n766), .B0(
Add_result[11]), .B1(n602), .Y(n708) );
AOI22X1TS U1028 ( .A0(Add_result[10]), .A1(n604), .B0(n631), .B1(P_Sgf[33]),
.Y(n707) );
OAI211XLTS U1029 ( .A0(n769), .A1(n1909), .B0(n708), .C0(n707), .Y(n201) );
AOI22X1TS U1030 ( .A0(Sgf_normalized_result[12]), .A1(n766), .B0(
Add_result[13]), .B1(n603), .Y(n710) );
AOI22X1TS U1031 ( .A0(Add_result[12]), .A1(n604), .B0(n632), .B1(P_Sgf[35]),
.Y(n709) );
OAI211XLTS U1032 ( .A0(n769), .A1(n1908), .B0(n710), .C0(n709), .Y(n203) );
AOI22X1TS U1033 ( .A0(Sgf_normalized_result[14]), .A1(n766), .B0(
Add_result[15]), .B1(n602), .Y(n712) );
AOI22X1TS U1034 ( .A0(Add_result[14]), .A1(n605), .B0(n631), .B1(P_Sgf[37]),
.Y(n711) );
OAI211XLTS U1035 ( .A0(n769), .A1(n1888), .B0(n712), .C0(n711), .Y(n205) );
AOI22X1TS U1036 ( .A0(Sgf_normalized_result[16]), .A1(n766), .B0(
Add_result[17]), .B1(n603), .Y(n714) );
AOI22X1TS U1037 ( .A0(Add_result[16]), .A1(n606), .B0(n632), .B1(P_Sgf[39]),
.Y(n713) );
OAI211XLTS U1038 ( .A0(n1887), .A1(n406), .B0(n714), .C0(n713), .Y(n207) );
INVX2TS U1039 ( .A(n701), .Y(n746) );
AOI22X1TS U1040 ( .A0(Sgf_normalized_result[18]), .A1(n746), .B0(
Add_result[19]), .B1(n602), .Y(n716) );
AOI22X1TS U1041 ( .A0(Add_result[18]), .A1(n605), .B0(P_Sgf[41]), .B1(n631),
.Y(n715) );
OAI211XLTS U1042 ( .A0(n1886), .A1(n406), .B0(n716), .C0(n715), .Y(n209) );
AOI22X1TS U1043 ( .A0(Sgf_normalized_result[20]), .A1(n746), .B0(
Add_result[21]), .B1(n602), .Y(n718) );
AOI22X1TS U1044 ( .A0(Add_result[20]), .A1(n606), .B0(P_Sgf[43]), .B1(n632),
.Y(n717) );
OAI211XLTS U1045 ( .A0(n1885), .A1(n769), .B0(n718), .C0(n717), .Y(n211) );
AOI22X1TS U1046 ( .A0(Sgf_normalized_result[4]), .A1(n1588), .B0(n601), .B1(
Add_result[5]), .Y(n720) );
AOI22X1TS U1047 ( .A0(n632), .A1(P_Sgf[27]), .B0(n605), .B1(Add_result[4]),
.Y(n719) );
OAI211XLTS U1048 ( .A0(n769), .A1(n1912), .B0(n720), .C0(n719), .Y(n195) );
INVX2TS U1049 ( .A(n723), .Y(n1781) );
OAI211X1TS U1050 ( .A0(n1781), .A1(n529), .B0(n1328), .C0(n593), .Y(n728) );
OAI21X1TS U1051 ( .A0(n593), .A1(n722), .B0(n728), .Y(n726) );
NAND2X2TS U1052 ( .A(n723), .B(n1328), .Y(n1467) );
INVX2TS U1053 ( .A(n1328), .Y(n1780) );
NOR2X4TS U1054 ( .A(n723), .B(n1780), .Y(n1465) );
AOI22X1TS U1055 ( .A0(n615), .A1(n532), .B0(n1465), .B1(n576), .Y(n724) );
OAI21X1TS U1056 ( .A0(n1490), .A1(n1467), .B0(n724), .Y(n725) );
NAND2X1TS U1057 ( .A(n725), .B(n726), .Y(n1045) );
OA21XLTS U1058 ( .A0(n726), .A1(n725), .B0(n1045), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N2) );
NOR2X1TS U1059 ( .A(n1781), .B(n594), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N0) );
NOR2XLTS U1060 ( .A(Sgf_operation_RECURSIVE_EVEN1_middle_N0), .B(n1780), .Y(
n730) );
NAND2X1TS U1061 ( .A(n1488), .B(n616), .Y(n727) );
OAI21XLTS U1062 ( .A0(n1488), .A1(n637), .B0(n727), .Y(n729) );
OA21XLTS U1063 ( .A0(n730), .A1(n729), .B0(n728), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N1) );
NOR2X1TS U1064 ( .A(n1882), .B(n600), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N0) );
NOR2XLTS U1065 ( .A(Sgf_operation_RECURSIVE_EVEN1_right_N0), .B(n650), .Y(
n733) );
NAND2X1TS U1066 ( .A(n461), .B(n585), .Y(n731) );
OAI21XLTS U1067 ( .A0(n585), .A1(n455), .B0(n731), .Y(n732) );
OA21XLTS U1068 ( .A0(n733), .A1(n732), .B0(n734), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N1) );
NOR2X1TS U1069 ( .A(Op_MX[1]), .B(Op_MX[2]), .Y(n1538) );
OAI2BB1X1TS U1070 ( .A0N(n831), .A1N(n630), .B0(n734), .Y(n737) );
NOR2X2TS U1071 ( .A(Op_MX[0]), .B(n650), .Y(n1439) );
AOI22X1TS U1072 ( .A0(n460), .A1(Op_MY[2]), .B0(n1439), .B1(n474), .Y(n735)
);
OAI21X1TS U1073 ( .A0(Op_MY[2]), .A1(n455), .B0(n735), .Y(n736) );
NAND2X1TS U1074 ( .A(n736), .B(n737), .Y(n1152) );
OA21XLTS U1075 ( .A0(n737), .A1(n736), .B0(n1152), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N2) );
CLKBUFX2TS U1076 ( .A(n738), .Y(n1943) );
AOI22X1TS U1077 ( .A0(n583), .A1(n391), .B0(n492), .B1(n1866), .Y(n739) );
OR2X1TS U1078 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
AOI22X1TS U1079 ( .A0(Sgf_normalized_result[2]), .A1(n1588), .B0(n601), .B1(
Add_result[3]), .Y(n741) );
AOI22X1TS U1080 ( .A0(n631), .A1(P_Sgf[25]), .B0(n606), .B1(Add_result[2]),
.Y(n740) );
OAI211XLTS U1081 ( .A0(n769), .A1(n1913), .B0(n741), .C0(n740), .Y(n193) );
AOI22X1TS U1082 ( .A0(Sgf_normalized_result[21]), .A1(n746), .B0(
Add_result[22]), .B1(n603), .Y(n743) );
AOI22X1TS U1083 ( .A0(Add_result[21]), .A1(n605), .B0(P_Sgf[45]), .B1(n511),
.Y(n742) );
OAI211XLTS U1084 ( .A0(n1885), .A1(n765), .B0(n743), .C0(n742), .Y(n212) );
AOI22X1TS U1085 ( .A0(Sgf_normalized_result[19]), .A1(n746), .B0(
Add_result[20]), .B1(n603), .Y(n745) );
AOI22X1TS U1086 ( .A0(Add_result[19]), .A1(n606), .B0(P_Sgf[43]), .B1(n511),
.Y(n744) );
OAI211XLTS U1087 ( .A0(n1886), .A1(n765), .B0(n745), .C0(n744), .Y(n210) );
AOI22X1TS U1088 ( .A0(Sgf_normalized_result[17]), .A1(n746), .B0(
Add_result[18]), .B1(n602), .Y(n748) );
AOI22X1TS U1089 ( .A0(Add_result[17]), .A1(n605), .B0(P_Sgf[41]), .B1(n511),
.Y(n747) );
OAI211XLTS U1090 ( .A0(n1887), .A1(n765), .B0(n748), .C0(n747), .Y(n208) );
AOI22X1TS U1091 ( .A0(Sgf_normalized_result[15]), .A1(n766), .B0(
Add_result[16]), .B1(n603), .Y(n750) );
AOI22X1TS U1092 ( .A0(Add_result[15]), .A1(n606), .B0(n510), .B1(P_Sgf[39]),
.Y(n749) );
OAI211XLTS U1093 ( .A0(n1036), .A1(n1888), .B0(n750), .C0(n749), .Y(n206) );
AOI22X1TS U1094 ( .A0(Sgf_normalized_result[13]), .A1(n766), .B0(
Add_result[14]), .B1(n602), .Y(n752) );
AOI22X1TS U1095 ( .A0(Add_result[13]), .A1(n605), .B0(n510), .B1(P_Sgf[37]),
.Y(n751) );
OAI211XLTS U1096 ( .A0(n765), .A1(n1908), .B0(n752), .C0(n751), .Y(n204) );
AOI22X1TS U1097 ( .A0(Sgf_normalized_result[11]), .A1(n766), .B0(
Add_result[12]), .B1(n603), .Y(n754) );
AOI22X1TS U1098 ( .A0(Add_result[11]), .A1(n606), .B0(n510), .B1(P_Sgf[35]),
.Y(n753) );
OAI211XLTS U1099 ( .A0(n765), .A1(n1909), .B0(n754), .C0(n753), .Y(n202) );
AOI22X1TS U1100 ( .A0(Sgf_normalized_result[9]), .A1(n766), .B0(
Add_result[10]), .B1(n602), .Y(n756) );
AOI22X1TS U1101 ( .A0(Add_result[9]), .A1(n605), .B0(n510), .B1(P_Sgf[33]),
.Y(n755) );
OAI211XLTS U1102 ( .A0(n765), .A1(n1910), .B0(n756), .C0(n755), .Y(n200) );
AOI22X1TS U1103 ( .A0(Sgf_normalized_result[7]), .A1(n1588), .B0(
Add_result[8]), .B1(n602), .Y(n758) );
AOI22X1TS U1104 ( .A0(Add_result[7]), .A1(n606), .B0(n510), .B1(P_Sgf[31]),
.Y(n757) );
OAI211XLTS U1105 ( .A0(n765), .A1(n1911), .B0(n758), .C0(n757), .Y(n198) );
AOI22X1TS U1106 ( .A0(Sgf_normalized_result[5]), .A1(n1588), .B0(
Add_result[6]), .B1(n603), .Y(n760) );
AOI22X1TS U1107 ( .A0(n604), .A1(Add_result[5]), .B0(n511), .B1(P_Sgf[29]),
.Y(n759) );
OAI211XLTS U1108 ( .A0(n765), .A1(n1912), .B0(n760), .C0(n759), .Y(n196) );
AOI22X1TS U1109 ( .A0(Sgf_normalized_result[3]), .A1(n1588), .B0(n601), .B1(
Add_result[4]), .Y(n762) );
AOI22X1TS U1110 ( .A0(n604), .A1(Add_result[3]), .B0(n511), .B1(P_Sgf[27]),
.Y(n761) );
OAI211XLTS U1111 ( .A0(n765), .A1(n1913), .B0(n762), .C0(n761), .Y(n194) );
AOI22X1TS U1112 ( .A0(Sgf_normalized_result[1]), .A1(n1588), .B0(n601), .B1(
Add_result[2]), .Y(n764) );
AOI22X1TS U1113 ( .A0(n604), .A1(Add_result[1]), .B0(n511), .B1(P_Sgf[25]),
.Y(n763) );
OAI211XLTS U1114 ( .A0(n765), .A1(n1914), .B0(n764), .C0(n763), .Y(n192) );
AOI22X1TS U1115 ( .A0(Sgf_normalized_result[0]), .A1(n766), .B0(n601), .B1(
Add_result[1]), .Y(n768) );
AOI22X1TS U1116 ( .A0(n632), .A1(P_Sgf[23]), .B0(n605), .B1(Add_result[0]),
.Y(n767) );
OAI211XLTS U1117 ( .A0(n769), .A1(n1914), .B0(n768), .C0(n767), .Y(n191) );
INVX2TS U1118 ( .A(n1564), .Y(DP_OP_36J144_124_9196_n33) );
NOR2X1TS U1119 ( .A(Op_MX[13]), .B(Op_MX[14]), .Y(n1543) );
OAI2BB1X1TS U1120 ( .A0N(n812), .A1N(n473), .B0(n770), .Y(n773) );
AOI22X1TS U1121 ( .A0(n560), .A1(n452), .B0(n1706), .B1(n440), .Y(n771) );
OAI21X1TS U1122 ( .A0(n443), .A1(n862), .B0(n771), .Y(n772) );
NAND2X1TS U1123 ( .A(n772), .B(n773), .Y(n1275) );
OA21XLTS U1124 ( .A0(n773), .A1(n772), .B0(n1275), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N2) );
INVX2TS U1125 ( .A(n1706), .Y(n1505) );
OAI22X1TS U1126 ( .A0(n646), .A1(n862), .B0(n582), .B1(n1505), .Y(n774) );
AOI21X1TS U1127 ( .A0(n453), .A1(Op_MY[17]), .B0(n774), .Y(n868) );
AOI21X1TS U1128 ( .A0(n491), .A1(n579), .B0(n395), .Y(n869) );
NOR2X1TS U1129 ( .A(n868), .B(n869), .Y(mult_x_23_n136) );
INVX2TS U1130 ( .A(n1439), .Y(n881) );
OAI22X1TS U1131 ( .A0(n647), .A1(n881), .B0(n558), .B1(n454), .Y(n775) );
AOI21X1TS U1132 ( .A0(n460), .A1(n559), .B0(n775), .Y(n895) );
OA21XLTS U1133 ( .A0(n613), .A1(n630), .B0(n546), .Y(n896) );
NOR2X1TS U1134 ( .A(n895), .B(n896), .Y(mult_x_55_n136) );
BUFX3TS U1135 ( .A(n776), .Y(n1950) );
BUFX3TS U1136 ( .A(n778), .Y(n1961) );
AOI22X1TS U1137 ( .A0(n532), .A1(n1779), .B0(n550), .B1(n531), .Y(n779) );
INVX2TS U1138 ( .A(n1465), .Y(n1048) );
OAI22X1TS U1139 ( .A0(n1481), .A1(n1467), .B0(n567), .B1(n1048), .Y(n782) );
AOI21X1TS U1140 ( .A0(n616), .A1(n1481), .B0(n782), .Y(n1061) );
NOR2X1TS U1141 ( .A(n1060), .B(n1061), .Y(DP_OP_111J144_123_4462_n148) );
NOR2X2TS U1142 ( .A(Op_MX[21]), .B(Op_MX[22]), .Y(n1541) );
CMPR32X2TS U1143 ( .A(Op_MX[4]), .B(Op_MX[16]), .C(n783), .CO(n695), .S(n786) );
NOR2XLTS U1144 ( .A(n1321), .B(n786), .Y(n784) );
NAND2X1TS U1145 ( .A(n1321), .B(n786), .Y(n804) );
NOR3X6TS U1146 ( .A(n1321), .B(n786), .C(n785), .Y(n1772) );
AOI22X1TS U1147 ( .A0(n532), .A1(n539), .B0(n1772), .B1(n531), .Y(n787) );
OAI221X1TS U1148 ( .A0(n565), .A1(n643), .B0(n564), .B1(n502), .C0(n787),
.Y(n790) );
AOI22X1TS U1149 ( .A0(n518), .A1(n609), .B0(n636), .B1(n553), .Y(n788) );
OAI221X1TS U1150 ( .A0(n567), .A1(n549), .B0(n566), .B1(n1779), .C0(n788),
.Y(n789) );
NAND2X1TS U1151 ( .A(n789), .B(n790), .Y(n1382) );
OA21XLTS U1152 ( .A0(n790), .A1(n789), .B0(n1382), .Y(
DP_OP_111J144_123_4462_n142) );
AOI22X1TS U1153 ( .A0(n567), .A1(n1768), .B0(n570), .B1(n624), .Y(n791) );
AOI22X1TS U1154 ( .A0(n1483), .A1(n539), .B0(n1772), .B1(n555), .Y(n793) );
NAND2X1TS U1155 ( .A(n794), .B(n795), .Y(n1387) );
OA21XLTS U1156 ( .A0(n795), .A1(n794), .B0(n1387), .Y(
DP_OP_111J144_123_4462_n119) );
OAI22X1TS U1157 ( .A0(Op_MY[6]), .A1(n881), .B0(n588), .B1(n454), .Y(n796)
);
AOI21X1TS U1158 ( .A0(n461), .A1(n589), .B0(n796), .Y(n1745) );
NAND2X1TS U1159 ( .A(Op_MX[5]), .B(Op_MX[6]), .Y(n1707) );
AOI21X1TS U1160 ( .A0(n548), .A1(n600), .B0(n841), .Y(n1746) );
NOR2X1TS U1161 ( .A(n1745), .B(n1746), .Y(mult_x_55_n129) );
AOI22X1TS U1162 ( .A0(n518), .A1(n502), .B0(n642), .B1(n517), .Y(n797) );
AOI22X1TS U1163 ( .A0(n536), .A1(n1779), .B0(n550), .B1(n555), .Y(n798) );
NOR2X1TS U1164 ( .A(n823), .B(n824), .Y(DP_OP_111J144_123_4462_n131) );
OAI22X1TS U1165 ( .A0(n393), .A1(n1505), .B0(n649), .B1(n862), .Y(n799) );
AOI21X1TS U1166 ( .A0(n453), .A1(n393), .B0(n799), .Y(n1728) );
AO21X1TS U1167 ( .A0(Op_MX[18]), .A1(Op_MX[17]), .B0(n1540), .Y(n845) );
AOI21X1TS U1168 ( .A0(n608), .A1(n579), .B0(n396), .Y(n1729) );
NOR2X1TS U1169 ( .A(n1728), .B(n1729), .Y(mult_x_23_n129) );
OAI22X1TS U1170 ( .A0(n590), .A1(n862), .B0(n583), .B1(n1505), .Y(n800) );
AOI21X1TS U1171 ( .A0(n453), .A1(Op_MY[21]), .B0(n800), .Y(n1726) );
AOI21X1TS U1172 ( .A0(n493), .A1(n580), .B0(n397), .Y(n1727) );
NOR2X1TS U1173 ( .A(n1726), .B(n1727), .Y(mult_x_23_n119) );
OAI22X1TS U1174 ( .A0(Op_MY[8]), .A1(n881), .B0(n562), .B1(n454), .Y(n801)
);
AOI21X1TS U1175 ( .A0(n461), .A1(n563), .B0(n801), .Y(n1743) );
AOI21X1TS U1176 ( .A0(n544), .A1(n600), .B0(n802), .Y(n1744) );
NOR2X1TS U1177 ( .A(n1743), .B(n1744), .Y(mult_x_55_n119) );
AOI21X1TS U1178 ( .A0(Op_MX[22]), .A1(Op_MX[21]), .B0(n1541), .Y(n803) );
AOI21X1TS U1179 ( .A0(n803), .A1(n580), .B0(n1541), .Y(n1724) );
INVX2TS U1180 ( .A(n862), .Y(n1503) );
AOI21X1TS U1181 ( .A0(n1503), .A1(n1877), .B0(n453), .Y(n1725) );
NOR2X1TS U1182 ( .A(n1724), .B(n1725), .Y(mult_x_23_n106) );
INVX2TS U1183 ( .A(n803), .Y(n1731) );
NAND2X1TS U1184 ( .A(n805), .B(n804), .Y(DP_OP_111J144_123_4462_n215) );
NAND2X1TS U1185 ( .A(n807), .B(n806), .Y(DP_OP_111J144_123_4462_n188) );
OAI22X1TS U1186 ( .A0(n596), .A1(n881), .B0(Op_MY[11]), .B1(n454), .Y(n808)
);
AOI21X1TS U1187 ( .A0(n461), .A1(n480), .B0(n808), .Y(n1741) );
AOI21X1TS U1188 ( .A0(n1229), .A1(n600), .B0(n485), .Y(n1742) );
NOR2X1TS U1189 ( .A(n1741), .B(n1742), .Y(mult_x_55_n106) );
NAND2X1TS U1190 ( .A(n648), .B(Op_MX[11]), .Y(mult_x_55_n38) );
NAND2X1TS U1191 ( .A(n647), .B(Op_MX[11]), .Y(mult_x_55_n64) );
BUFX3TS U1192 ( .A(n1943), .Y(n1931) );
CLKBUFX3TS U1193 ( .A(n1972), .Y(n1926) );
BUFX3TS U1194 ( .A(n1943), .Y(n1932) );
BUFX3TS U1195 ( .A(n1943), .Y(n1936) );
BUFX3TS U1196 ( .A(n1943), .Y(n1929) );
AOI22X1TS U1197 ( .A0(Op_MY[8]), .A1(n488), .B0(n545), .B1(n1875), .Y(n809)
);
AOI221X1TS U1198 ( .A0(n458), .A1(n562), .B0(n614), .B1(n523), .C0(n809),
.Y(n839) );
NAND2X1TS U1199 ( .A(n585), .B(Op_MX[11]), .Y(n1425) );
INVX2TS U1200 ( .A(n1425), .Y(n1429) );
AOI22X1TS U1201 ( .A0(Op_MY[4]), .A1(n1751), .B0(n514), .B1(n1874), .Y(n810)
);
INVX2TS U1202 ( .A(n811), .Y(mult_x_55_n90) );
NAND2X1TS U1203 ( .A(Op_MX[13]), .B(Op_MX[14]), .Y(n1594) );
AOI22X1TS U1204 ( .A0(n649), .A1(n449), .B0(n506), .B1(n1879), .Y(n813) );
NAND2BXLTS U1205 ( .AN(n814), .B(n473), .Y(n1420) );
OAI22X1TS U1206 ( .A0(n393), .A1(n862), .B0(Op_MY[20]), .B1(n1505), .Y(n815)
);
AOI21X1TS U1207 ( .A0(n453), .A1(n590), .B0(n815), .Y(n1419) );
INVX2TS U1208 ( .A(n816), .Y(mult_x_23_n125) );
AOI22X1TS U1209 ( .A0(Op_MY[20]), .A1(n482), .B0(n508), .B1(n1860), .Y(n817)
);
AOI22X1TS U1210 ( .A0(Op_MY[16]), .A1(n486), .B0(n494), .B1(n1864), .Y(n818)
);
INVX2TS U1211 ( .A(n819), .Y(mult_x_23_n90) );
INVX2TS U1212 ( .A(n822), .Y(mult_x_23_n89) );
AO21XLTS U1213 ( .A0(n824), .A1(n823), .B0(DP_OP_111J144_123_4462_n131), .Y(
n1344) );
AOI22X1TS U1214 ( .A0(n565), .A1(n500), .B0(n1770), .B1(n564), .Y(n825) );
AOI22X1TS U1215 ( .A0(n567), .A1(n502), .B0(n643), .B1(n566), .Y(n826) );
AOI22X1TS U1216 ( .A0(n518), .A1(n1779), .B0(n550), .B1(n517), .Y(n827) );
INVX2TS U1217 ( .A(n828), .Y(DP_OP_111J144_123_4462_n129) );
NOR2X1TS U1218 ( .A(n1707), .B(Op_MX[7]), .Y(n842) );
INVX2TS U1219 ( .A(n842), .Y(n1501) );
AOI22X1TS U1220 ( .A0(Op_MY[8]), .A1(n617), .B0(n466), .B1(n1875), .Y(n829)
);
AOI221X1TS U1221 ( .A0(n464), .A1(n562), .B0(n547), .B1(n523), .C0(n829),
.Y(n1424) );
NAND2X1TS U1222 ( .A(n587), .B(Op_MX[11]), .Y(n1423) );
INVX2TS U1223 ( .A(n830), .Y(mult_x_55_n72) );
NAND2X1TS U1224 ( .A(Op_MX[1]), .B(Op_MX[2]), .Y(n1515) );
AOI22X1TS U1225 ( .A0(n597), .A1(n618), .B0(n504), .B1(n1876), .Y(n832) );
AOI221X1TS U1226 ( .A0(n611), .A1(n558), .B0(n537), .B1(n519), .C0(n832),
.Y(n1447) );
NAND2BXLTS U1227 ( .AN(n833), .B(n630), .Y(n1446) );
OAI22X1TS U1228 ( .A0(Op_MY[8]), .A1(n454), .B0(n588), .B1(n881), .Y(n834)
);
AOI21X1TS U1229 ( .A0(n461), .A1(n648), .B0(n834), .Y(n1445) );
INVX2TS U1230 ( .A(n835), .Y(mult_x_55_n125) );
NAND2X1TS U1231 ( .A(n630), .B(n471), .Y(n1434) );
AOI22X1TS U1232 ( .A0(n595), .A1(n618), .B0(n504), .B1(n476), .Y(n836) );
AOI221X1TS U1233 ( .A0(n611), .A1(n562), .B0(n537), .B1(n523), .C0(n836),
.Y(n1433) );
OAI21XLTS U1234 ( .A0(Op_MX[0]), .A1(n481), .B0(Op_MX[1]), .Y(n1432) );
INVX2TS U1235 ( .A(n837), .Y(mult_x_55_n99) );
CMPR32X2TS U1236 ( .A(n839), .B(n1429), .C(n838), .CO(n840), .S(n811) );
INVX2TS U1237 ( .A(n840), .Y(mult_x_55_n89) );
AOI221X1TS U1238 ( .A0(n842), .A1(Op_MY[11]), .B0(n841), .B1(n1872), .C0(
n547), .Y(n1360) );
NAND2X1TS U1239 ( .A(Op_MY[6]), .B(n471), .Y(n1368) );
INVX2TS U1240 ( .A(n1368), .Y(n1359) );
AOI22X1TS U1241 ( .A0(n563), .A1(n1751), .B0(n514), .B1(n524), .Y(n843) );
INVX2TS U1242 ( .A(n844), .Y(mult_x_55_n47) );
NAND3X2TS U1243 ( .A(Op_MX[17]), .B(Op_MX[18]), .C(n1904), .Y(n1700) );
AOI22X1TS U1244 ( .A0(n560), .A1(n1700), .B0(n496), .B1(n440), .Y(n846) );
AOI22X1TS U1245 ( .A0(n472), .A1(n486), .B0(n494), .B1(n579), .Y(n847) );
AOI22X1TS U1246 ( .A0(n598), .A1(n449), .B0(n506), .B1(n1880), .Y(n848) );
AOI221X1TS U1247 ( .A0(n462), .A1(n649), .B0(n448), .B1(n1879), .C0(n848),
.Y(n1372) );
INVX2TS U1248 ( .A(n849), .Y(mult_x_23_n118) );
AOI22X1TS U1249 ( .A0(n595), .A1(n1751), .B0(n515), .B1(n476), .Y(n850) );
AOI221X1TS U1250 ( .A0(n456), .A1(Op_MY[11]), .B0(n544), .B1(n1872), .C0(
n850), .Y(n1367) );
NAND2X1TS U1251 ( .A(n589), .B(n471), .Y(n1366) );
INVX2TS U1252 ( .A(n851), .Y(mult_x_55_n42) );
INVX2TS U1253 ( .A(mult_x_23_n58), .Y(n873) );
INVX2TS U1254 ( .A(mult_x_23_n53), .Y(n872) );
INVX2TS U1255 ( .A(mult_x_23_n59), .Y(n1207) );
INVX2TS U1256 ( .A(mult_x_23_n74), .Y(n1196) );
INVX2TS U1257 ( .A(mult_x_23_n67), .Y(n1195) );
INVX2TS U1258 ( .A(mult_x_23_n84), .Y(n1200) );
INVX2TS U1259 ( .A(mult_x_23_n75), .Y(n1199) );
INVX2TS U1260 ( .A(mult_x_23_n93), .Y(n1220) );
INVX2TS U1261 ( .A(mult_x_23_n85), .Y(n1219) );
INVX2TS U1262 ( .A(mult_x_23_n94), .Y(n1232) );
INVX2TS U1263 ( .A(mult_x_23_n109), .Y(n1281) );
INVX2TS U1264 ( .A(mult_x_23_n102), .Y(n1280) );
INVX2TS U1265 ( .A(mult_x_23_n115), .Y(n1261) );
INVX2TS U1266 ( .A(mult_x_23_n110), .Y(n1260) );
INVX2TS U1267 ( .A(mult_x_23_n122), .Y(n1241) );
INVX2TS U1268 ( .A(mult_x_23_n116), .Y(n1240) );
INVX2TS U1269 ( .A(mult_x_23_n127), .Y(n1237) );
INVX2TS U1270 ( .A(mult_x_23_n123), .Y(n1236) );
INVX2TS U1271 ( .A(mult_x_23_n132), .Y(n1224) );
INVX2TS U1272 ( .A(mult_x_23_n128), .Y(n1223) );
INVX2TS U1273 ( .A(mult_x_23_n133), .Y(n1257) );
AOI22X1TS U1274 ( .A0(n472), .A1(n482), .B0(n509), .B1(n579), .Y(n852) );
AOI22X1TS U1275 ( .A0(n581), .A1(n449), .B0(n506), .B1(n1865), .Y(n853) );
OAI22X1TS U1276 ( .A0(Op_MY[15]), .A1(n862), .B0(Op_MY[16]), .B1(n1505), .Y(
n854) );
AOI21X1TS U1277 ( .A0(n453), .A1(n646), .B0(n854), .Y(n867) );
AOI22X1TS U1278 ( .A0(n560), .A1(n450), .B0(n506), .B1(n440), .Y(n855) );
AOI221X1TS U1279 ( .A0(n462), .A1(Op_MY[13]), .B0(n448), .B1(n444), .C0(n855), .Y(n866) );
NAND2BXLTS U1280 ( .AN(n856), .B(n473), .Y(n865) );
CMPR32X2TS U1281 ( .A(n859), .B(n858), .C(n857), .CO(n1256), .S(n1269) );
AOI22X1TS U1282 ( .A0(n472), .A1(n462), .B0(n448), .B1(n579), .Y(n860) );
AOI22X1TS U1283 ( .A0(Op_MY[15]), .A1(n452), .B0(n1706), .B1(n1865), .Y(n861) );
OAI21X1TS U1284 ( .A0(n561), .A1(n862), .B0(n861), .Y(n863) );
NAND2X1TS U1285 ( .A(n863), .B(n864), .Y(n1300) );
OA21XLTS U1286 ( .A0(n507), .A1(n473), .B0(n447), .Y(n1276) );
CMPR32X2TS U1287 ( .A(n867), .B(n866), .C(n865), .CO(n857), .S(n1299) );
AO21XLTS U1288 ( .A0(n869), .A1(n868), .B0(mult_x_23_n136), .Y(n1267) );
INVX2TS U1289 ( .A(n870), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N17) );
INVX2TS U1290 ( .A(mult_x_23_n41), .Y(n877) );
INVX2TS U1291 ( .A(mult_x_23_n52), .Y(n1212) );
INVX2TS U1292 ( .A(mult_x_23_n46), .Y(n1211) );
CMPR32X2TS U1293 ( .A(n873), .B(n872), .C(n871), .CO(n1210), .S(n870) );
INVX2TS U1294 ( .A(n874), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N19) );
INVX2TS U1295 ( .A(mult_x_23_n33), .Y(n1204) );
INVX2TS U1296 ( .A(mult_x_23_n35), .Y(n1203) );
INVX2TS U1297 ( .A(mult_x_23_n36), .Y(n1216) );
INVX2TS U1298 ( .A(mult_x_23_n40), .Y(n1215) );
CMPR32X2TS U1299 ( .A(n877), .B(n876), .C(n875), .CO(n1214), .S(n874) );
INVX2TS U1300 ( .A(n878), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N21) );
INVX2TS U1301 ( .A(mult_x_55_n101), .Y(n1228) );
INVX2TS U1302 ( .A(mult_x_55_n109), .Y(n1189) );
INVX2TS U1303 ( .A(mult_x_55_n102), .Y(n1188) );
INVX2TS U1304 ( .A(mult_x_55_n115), .Y(n1185) );
INVX2TS U1305 ( .A(mult_x_55_n110), .Y(n1184) );
INVX2TS U1306 ( .A(mult_x_55_n122), .Y(n1181) );
INVX2TS U1307 ( .A(mult_x_55_n116), .Y(n1180) );
INVX2TS U1308 ( .A(mult_x_55_n127), .Y(n1177) );
INVX2TS U1309 ( .A(mult_x_55_n123), .Y(n1176) );
INVX2TS U1310 ( .A(mult_x_55_n132), .Y(n1173) );
INVX2TS U1311 ( .A(mult_x_55_n128), .Y(n1172) );
INVX2TS U1312 ( .A(mult_x_55_n133), .Y(n1168) );
AOI22X1TS U1313 ( .A0(Op_MY[0]), .A1(n488), .B0(n545), .B1(n599), .Y(n879)
);
AOI22X1TS U1314 ( .A0(n586), .A1(n618), .B0(n504), .B1(n1873), .Y(n880) );
OAI22X1TS U1315 ( .A0(n587), .A1(n881), .B0(Op_MY[4]), .B1(n455), .Y(n882)
);
AOI21X1TS U1316 ( .A0(n461), .A1(n647), .B0(n882), .Y(n894) );
AOI22X1TS U1317 ( .A0(Op_MY[2]), .A1(n618), .B0(n504), .B1(n1857), .Y(n883)
);
AOI221X1TS U1318 ( .A0(n611), .A1(n584), .B0(n537), .B1(n474), .C0(n883),
.Y(n893) );
NAND2BXLTS U1319 ( .AN(n884), .B(n630), .Y(n892) );
CMPR32X2TS U1320 ( .A(n887), .B(n886), .C(n885), .CO(n1167), .S(n1164) );
AOI22X1TS U1321 ( .A0(Op_MY[0]), .A1(n611), .B0(n537), .B1(n599), .Y(n888)
);
AOI22X1TS U1322 ( .A0(n586), .A1(n460), .B0(n1439), .B1(n1857), .Y(n889) );
OAI21X1TS U1323 ( .A0(n587), .A1(n455), .B0(n889), .Y(n890) );
NAND2X1TS U1324 ( .A(n890), .B(n891), .Y(n1157) );
OAI21XLTS U1325 ( .A0(n891), .A1(n890), .B0(n1157), .Y(n1154) );
AOI21X1TS U1326 ( .A0(n394), .A1(n600), .B0(n538), .Y(n1153) );
CMPR32X2TS U1327 ( .A(n894), .B(n893), .C(n892), .CO(n885), .S(n1156) );
AO21XLTS U1328 ( .A0(n896), .A1(n895), .B0(mult_x_55_n136), .Y(n1162) );
INVX2TS U1329 ( .A(n897), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N12) );
AOI22X1TS U1330 ( .A0(Op_MY[2]), .A1(n617), .B0(n466), .B1(n1857), .Y(n898)
);
AOI22X1TS U1331 ( .A0(n630), .A1(n1751), .B0(n514), .B1(n599), .Y(n899) );
AOI221X1TS U1332 ( .A0(n456), .A1(n584), .B0(n544), .B1(n474), .C0(n899),
.Y(n1336) );
AOI22X1TS U1333 ( .A0(n588), .A1(n618), .B0(n504), .B1(n442), .Y(n900) );
INVX2TS U1334 ( .A(n901), .Y(mult_x_55_n118) );
INVX2TS U1335 ( .A(n1770), .Y(n1507) );
AOI22X1TS U1336 ( .A0(n573), .A1(n1477), .B0(n499), .B1(n577), .Y(n902) );
CLKAND2X2TS U1337 ( .A(n904), .B(n903), .Y(n906) );
INVX2TS U1338 ( .A(n905), .Y(DP_OP_111J144_123_4462_n46) );
CMPR32X2TS U1339 ( .A(n1304), .B(n907), .C(n906), .CO(n905), .S(n908) );
INVX2TS U1340 ( .A(n908), .Y(DP_OP_111J144_123_4462_n47) );
AOI22X1TS U1341 ( .A0(n615), .A1(n534), .B0(n1465), .B1(n554), .Y(n909) );
OAI21XLTS U1342 ( .A0(n1453), .A1(n637), .B0(n909), .Y(
DP_OP_111J144_123_4462_n250) );
NOR2X1TS U1343 ( .A(FS_Module_state_reg[2]), .B(n1870), .Y(n1723) );
NAND3X2TS U1344 ( .A(n1723), .B(n1918), .C(FS_Module_state_reg[0]), .Y(n1649) );
INVX2TS U1345 ( .A(n1649), .Y(n1599) );
INVX2TS U1346 ( .A(n1160), .Y(n1692) );
NAND2X1TS U1347 ( .A(n1721), .B(n910), .Y(n1563) );
NOR2BX1TS U1348 ( .AN(P_Sgf[47]), .B(n1563), .Y(n1161) );
INVX2TS U1349 ( .A(n1161), .Y(n911) );
OAI31X1TS U1350 ( .A0(n1599), .A1(n1692), .A2(n1883), .B0(n911), .Y(n308) );
AOI31XLTS U1351 ( .A0(n1849), .A1(FS_Module_state_reg[1]), .A2(
FSM_add_overflow_flag), .B0(n912), .Y(n913) );
INVX2TS U1352 ( .A(n913), .Y(n1527) );
INVX2TS U1353 ( .A(n1832), .Y(n1843) );
INVX2TS U1354 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]), .Y(n940) );
INVX2TS U1355 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]), .Y(n936) );
INVX2TS U1356 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]), .Y(n914) );
CMPR32X2TS U1357 ( .A(n914), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[22]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_left[22]), .CO(n943), .S(n948) );
INVX2TS U1358 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]), .Y(n915) );
CMPR32X2TS U1359 ( .A(n915), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[21]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_left[21]), .CO(n947), .S(n952) );
INVX2TS U1360 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]), .Y(n916) );
CMPR32X2TS U1361 ( .A(n916), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[20]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_left[20]), .CO(n951), .S(n956) );
INVX2TS U1362 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]), .Y(n917) );
CMPR32X2TS U1363 ( .A(n917), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[19]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_left[19]), .CO(n955), .S(n960) );
INVX2TS U1364 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]), .Y(n918) );
CMPR32X2TS U1365 ( .A(n918), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[18]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_left[18]), .CO(n959), .S(n964) );
INVX2TS U1366 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]), .Y(n919) );
CMPR32X2TS U1367 ( .A(n919), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[17]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_left[17]), .CO(n963), .S(n968) );
INVX2TS U1368 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]), .Y(n920) );
CMPR32X2TS U1369 ( .A(n920), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[16]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_left[16]), .CO(n967), .S(n972) );
INVX2TS U1370 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]), .Y(n921) );
CMPR32X2TS U1371 ( .A(n921), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[15]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .CO(n971), .S(n976) );
INVX2TS U1372 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]), .Y(n922) );
CMPR32X2TS U1373 ( .A(n922), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[14]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_left[14]), .CO(n975), .S(n980) );
INVX2TS U1374 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]), .Y(n923) );
CMPR32X2TS U1375 ( .A(n923), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[13]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .CO(n979), .S(n984) );
INVX2TS U1376 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]), .Y(n924) );
CMPR32X2TS U1377 ( .A(n924), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[12]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .CO(n983), .S(n988) );
INVX2TS U1378 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]), .Y(n925) );
CMPR32X2TS U1379 ( .A(Sgf_operation_Result[11]), .B(n925), .C(
Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .CO(n987), .S(n992) );
INVX2TS U1380 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]), .Y(n926) );
CMPR32X2TS U1381 ( .A(Sgf_operation_Result[10]), .B(n926), .C(
Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .CO(n991), .S(n996) );
INVX2TS U1382 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]), .Y(n927) );
CMPR32X2TS U1383 ( .A(Sgf_operation_Result[9]), .B(n927), .C(
Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .CO(n995), .S(n1000) );
INVX2TS U1384 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]), .Y(n928) );
CMPR32X2TS U1385 ( .A(Sgf_operation_Result[8]), .B(n928), .C(
Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .CO(n999), .S(n1004) );
INVX2TS U1386 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]), .Y(n929) );
CMPR32X2TS U1387 ( .A(Sgf_operation_Result[7]), .B(n929), .C(
Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .CO(n1003), .S(n1008) );
INVX2TS U1388 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]), .Y(n930) );
CMPR32X2TS U1389 ( .A(Sgf_operation_Result[6]), .B(n930), .C(
Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .CO(n1007), .S(n1012) );
INVX2TS U1390 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]), .Y(n931) );
CMPR32X2TS U1391 ( .A(Sgf_operation_Result[5]), .B(n931), .C(
Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .CO(n1011), .S(n1016) );
INVX2TS U1392 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]), .Y(n932) );
CMPR32X2TS U1393 ( .A(Sgf_operation_Result[4]), .B(n932), .C(
Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .CO(n1015), .S(n1020) );
INVX2TS U1394 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]), .Y(n933) );
CMPR32X2TS U1395 ( .A(Sgf_operation_Result[3]), .B(n933), .C(
Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .CO(n1019), .S(n1024) );
INVX2TS U1396 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]), .Y(n934) );
INVX2TS U1397 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(n935) );
NOR2X1TS U1398 ( .A(n935), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]),
.Y(n1028) );
CMPR32X2TS U1399 ( .A(Sgf_operation_Result[2]), .B(n934), .C(
Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .CO(n1023), .S(n1027) );
AOI21X1TS U1400 ( .A0(Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]), .A1(n935),
.B0(n1028), .Y(n1031) );
INVX2TS U1401 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]), .Y(n1033) );
CMPR32X2TS U1402 ( .A(n936), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[23]),
.C(Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .CO(n938), .S(n944) );
CLKXOR2X2TS U1403 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]), .B(n937),
.Y(n1605) );
CMPR32X2TS U1404 ( .A(n940), .B(n939), .C(n938), .CO(n937), .S(n941) );
INVX2TS U1405 ( .A(n941), .Y(n1568) );
CMPR32X2TS U1406 ( .A(n944), .B(n943), .C(n942), .CO(n939), .S(n945) );
INVX2TS U1407 ( .A(n945), .Y(n1610) );
CMPR32X2TS U1408 ( .A(n948), .B(n947), .C(n946), .CO(n942), .S(n949) );
INVX2TS U1409 ( .A(n949), .Y(n1571) );
CMPR32X2TS U1410 ( .A(n952), .B(n951), .C(n950), .CO(n946), .S(n953) );
INVX2TS U1411 ( .A(n953), .Y(n1613) );
CMPR32X2TS U1412 ( .A(n956), .B(n955), .C(n954), .CO(n950), .S(n957) );
INVX2TS U1413 ( .A(n957), .Y(n1574) );
CMPR32X2TS U1414 ( .A(n960), .B(n959), .C(n958), .CO(n954), .S(n961) );
INVX2TS U1415 ( .A(n961), .Y(n1616) );
CMPR32X2TS U1416 ( .A(n964), .B(n963), .C(n962), .CO(n958), .S(n965) );
INVX2TS U1417 ( .A(n965), .Y(n1577) );
CMPR32X2TS U1418 ( .A(n968), .B(n967), .C(n966), .CO(n962), .S(n969) );
INVX2TS U1419 ( .A(n969), .Y(n1619) );
CMPR32X2TS U1420 ( .A(n972), .B(n971), .C(n970), .CO(n966), .S(n973) );
INVX2TS U1421 ( .A(n973), .Y(n1580) );
CMPR32X2TS U1422 ( .A(n976), .B(n975), .C(n974), .CO(n970), .S(n977) );
INVX2TS U1423 ( .A(n977), .Y(n1627) );
CMPR32X2TS U1424 ( .A(n980), .B(n979), .C(n978), .CO(n974), .S(n981) );
INVX2TS U1425 ( .A(n981), .Y(n1583) );
CMPR32X2TS U1426 ( .A(n984), .B(n983), .C(n982), .CO(n978), .S(n985) );
INVX2TS U1427 ( .A(n985), .Y(n1631) );
CMPR32X2TS U1428 ( .A(n988), .B(n987), .C(n986), .CO(n982), .S(n989) );
INVX2TS U1429 ( .A(n989), .Y(n1586) );
CMPR32X2TS U1430 ( .A(n992), .B(n991), .C(n990), .CO(n986), .S(n993) );
INVX2TS U1431 ( .A(n993), .Y(n1639) );
CMPR32X2TS U1432 ( .A(n996), .B(n995), .C(n994), .CO(n990), .S(n997) );
INVX2TS U1433 ( .A(n997), .Y(n1529) );
CMPR32X2TS U1434 ( .A(n1000), .B(n999), .C(n998), .CO(n994), .S(n1001) );
INVX2TS U1435 ( .A(n1001), .Y(n1664) );
CMPR32X2TS U1436 ( .A(n1004), .B(n1003), .C(n1002), .CO(n998), .S(n1005) );
INVX2TS U1437 ( .A(n1005), .Y(n1678) );
CMPR32X2TS U1438 ( .A(n1008), .B(n1007), .C(n1006), .CO(n1002), .S(n1009) );
INVX2TS U1439 ( .A(n1009), .Y(n1519) );
CMPR32X2TS U1440 ( .A(n1012), .B(n1011), .C(n1010), .CO(n1006), .S(n1013) );
INVX2TS U1441 ( .A(n1013), .Y(n1532) );
CMPR32X2TS U1442 ( .A(n1016), .B(n1015), .C(n1014), .CO(n1010), .S(n1017) );
INVX2TS U1443 ( .A(n1017), .Y(n1535) );
CMPR32X2TS U1444 ( .A(n1020), .B(n1019), .C(n1018), .CO(n1014), .S(n1021) );
INVX2TS U1445 ( .A(n1021), .Y(n1682) );
CMPR32X2TS U1446 ( .A(n1024), .B(n1023), .C(n1022), .CO(n1018), .S(n1025) );
INVX2TS U1447 ( .A(n1025), .Y(n1522) );
CMPR32X2TS U1448 ( .A(n1028), .B(n1027), .C(n1026), .CO(n1022), .S(n1029) );
INVX2TS U1449 ( .A(n1029), .Y(n1525) );
CMPR32X2TS U1450 ( .A(Sgf_operation_Result[1]), .B(n1031), .C(n1030), .CO(
n1026), .S(n1032) );
INVX2TS U1451 ( .A(n1032), .Y(n1694) );
INVX2TS U1452 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(n1685) );
CMPR32X2TS U1453 ( .A(Sgf_operation_Result[0]), .B(n1033), .C(
Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .CO(n1030), .S(n1686) );
NOR2X1TS U1454 ( .A(n1685), .B(n1686), .Y(n1693) );
NOR2BX1TS U1455 ( .AN(n1034), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[14]),
.Y(n1035) );
AOI22X1TS U1456 ( .A0(FSM_selector_C), .A1(Add_result[23]), .B0(P_Sgf[46]),
.B1(n401), .Y(n1589) );
AOI22X1TS U1457 ( .A0(Sgf_normalized_result[22]), .A1(n1588), .B0(
Add_result[22]), .B1(n606), .Y(n1038) );
NAND2X1TS U1458 ( .A(P_Sgf[45]), .B(n631), .Y(n1037) );
OAI211XLTS U1459 ( .A0(n1590), .A1(n1589), .B0(n1038), .C0(n1037), .Y(n213)
);
AOI22X1TS U1460 ( .A0(n530), .A1(n609), .B0(n636), .B1(n529), .Y(n1039) );
OAI221X1TS U1461 ( .A0(n1508), .A1(n549), .B0(n593), .B1(n1779), .C0(n1039),
.Y(n1042) );
AOI22X1TS U1462 ( .A0(n615), .A1(n1498), .B0(n1465), .B1(n557), .Y(n1040) );
OAI21X1TS U1463 ( .A0(n1498), .A1(n1467), .B0(n1040), .Y(n1041) );
NAND2X1TS U1464 ( .A(n1041), .B(n1042), .Y(n1058) );
AOI21X1TS U1465 ( .A0(n636), .A1(n594), .B0(n1043), .Y(n1046) );
INVX2TS U1466 ( .A(n1044), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N3) );
CMPR32X2TS U1467 ( .A(n1047), .B(n1046), .C(n1045), .CO(n1059), .S(n1044) );
OAI22X1TS U1468 ( .A0(n1496), .A1(n1467), .B0(n565), .B1(n1048), .Y(n1049)
);
AOI21X1TS U1469 ( .A0(n616), .A1(n1496), .B0(n1049), .Y(n1056) );
AOI22X1TS U1470 ( .A0(n530), .A1(n639), .B0(n550), .B1(n576), .Y(n1050) );
NAND2X1TS U1471 ( .A(n1508), .B(n1051), .Y(n1054) );
INVX2TS U1472 ( .A(n1052), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N4) );
AOI22X1TS U1473 ( .A0(n530), .A1(n502), .B0(n642), .B1(n576), .Y(n1053) );
CMPR32X2TS U1474 ( .A(n1056), .B(n1055), .C(n1054), .CO(n1064), .S(n1057) );
AOI21X1TS U1475 ( .A0(n1775), .A1(n594), .B0(n1772), .Y(n1063) );
CMPR32X2TS U1476 ( .A(n1059), .B(n1058), .C(n1057), .CO(n1067), .S(n1052) );
AO21XLTS U1477 ( .A0(n1061), .A1(n1060), .B0(DP_OP_111J144_123_4462_n148),
.Y(n1066) );
INVX2TS U1478 ( .A(n1062), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N5) );
INVX2TS U1479 ( .A(DP_OP_111J144_123_4462_n145), .Y(n1072) );
CMPR32X2TS U1480 ( .A(n1065), .B(n1064), .C(n1063), .CO(n1071), .S(n1068) );
CMPR32X2TS U1481 ( .A(n1068), .B(n1067), .C(n1066), .CO(n1070), .S(n1062) );
INVX2TS U1482 ( .A(n1069), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N6) );
INVX2TS U1483 ( .A(DP_OP_111J144_123_4462_n140), .Y(n1076) );
INVX2TS U1484 ( .A(DP_OP_111J144_123_4462_n144), .Y(n1075) );
CMPR32X2TS U1485 ( .A(n1072), .B(n1071), .C(n1070), .CO(n1074), .S(n1069) );
INVX2TS U1486 ( .A(n1073), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N7) );
INVX2TS U1487 ( .A(DP_OP_111J144_123_4462_n139), .Y(n1080) );
INVX2TS U1488 ( .A(DP_OP_111J144_123_4462_n135), .Y(n1079) );
CMPR32X2TS U1489 ( .A(n1076), .B(n1075), .C(n1074), .CO(n1078), .S(n1073) );
INVX2TS U1490 ( .A(n1077), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N8) );
INVX2TS U1491 ( .A(DP_OP_111J144_123_4462_n134), .Y(n1084) );
INVX2TS U1492 ( .A(DP_OP_111J144_123_4462_n128), .Y(n1083) );
CMPR32X2TS U1493 ( .A(n1080), .B(n1079), .C(n1078), .CO(n1082), .S(n1077) );
INVX2TS U1494 ( .A(n1081), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N9) );
INVX2TS U1495 ( .A(DP_OP_111J144_123_4462_n127), .Y(n1088) );
INVX2TS U1496 ( .A(DP_OP_111J144_123_4462_n122), .Y(n1087) );
CMPR32X2TS U1497 ( .A(n1084), .B(n1083), .C(n1082), .CO(n1086), .S(n1081) );
INVX2TS U1498 ( .A(n1085), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N10) );
CMPR32X2TS U1499 ( .A(n1088), .B(n1087), .C(n1086), .CO(n1091), .S(n1085) );
AOI21X1TS U1500 ( .A0(n1137), .A1(n594), .B0(n575), .Y(n1090) );
INVX2TS U1501 ( .A(n1089), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N11) );
INVX2TS U1502 ( .A(DP_OP_111J144_123_4462_n113), .Y(n1096) );
INVX2TS U1503 ( .A(DP_OP_111J144_123_4462_n106), .Y(n1095) );
CMPR32X2TS U1504 ( .A(n1092), .B(n1091), .C(n1090), .CO(n1094), .S(n1089) );
INVX2TS U1505 ( .A(n1093), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N12) );
INVX2TS U1506 ( .A(DP_OP_111J144_123_4462_n105), .Y(n1100) );
INVX2TS U1507 ( .A(DP_OP_111J144_123_4462_n98), .Y(n1099) );
CMPR32X2TS U1508 ( .A(n1096), .B(n1095), .C(n1094), .CO(n1098), .S(n1093) );
INVX2TS U1509 ( .A(n1097), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N13) );
INVX2TS U1510 ( .A(DP_OP_111J144_123_4462_n97), .Y(n1104) );
INVX2TS U1511 ( .A(DP_OP_111J144_123_4462_n89), .Y(n1103) );
CMPR32X2TS U1512 ( .A(n1100), .B(n1099), .C(n1098), .CO(n1102), .S(n1097) );
INVX2TS U1513 ( .A(n1101), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N14) );
INVX2TS U1514 ( .A(DP_OP_111J144_123_4462_n88), .Y(n1108) );
INVX2TS U1515 ( .A(DP_OP_111J144_123_4462_n79), .Y(n1107) );
CMPR32X2TS U1516 ( .A(n1104), .B(n1103), .C(n1102), .CO(n1106), .S(n1101) );
INVX2TS U1517 ( .A(n1105), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N15) );
INVX2TS U1518 ( .A(DP_OP_111J144_123_4462_n78), .Y(n1112) );
INVX2TS U1519 ( .A(DP_OP_111J144_123_4462_n71), .Y(n1111) );
CMPR32X2TS U1520 ( .A(n1108), .B(n1107), .C(n1106), .CO(n1110), .S(n1105) );
INVX2TS U1521 ( .A(n1109), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N16) );
INVX2TS U1522 ( .A(DP_OP_111J144_123_4462_n70), .Y(n1116) );
INVX2TS U1523 ( .A(DP_OP_111J144_123_4462_n63), .Y(n1115) );
CMPR32X2TS U1524 ( .A(n1112), .B(n1111), .C(n1110), .CO(n1114), .S(n1109) );
INVX2TS U1525 ( .A(n1113), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N17) );
INVX2TS U1526 ( .A(DP_OP_111J144_123_4462_n62), .Y(n1120) );
CMPR32X2TS U1527 ( .A(n1116), .B(n1115), .C(n1114), .CO(n1118), .S(n1113) );
INVX2TS U1528 ( .A(n1117), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N18) );
INVX2TS U1529 ( .A(DP_OP_111J144_123_4462_n56), .Y(n1124) );
INVX2TS U1530 ( .A(DP_OP_111J144_123_4462_n50), .Y(n1123) );
CMPR32X2TS U1531 ( .A(n1120), .B(n1119), .C(n1118), .CO(n1122), .S(n1117) );
INVX2TS U1532 ( .A(n1121), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N19) );
INVX2TS U1533 ( .A(DP_OP_111J144_123_4462_n45), .Y(n1128) );
INVX2TS U1534 ( .A(DP_OP_111J144_123_4462_n49), .Y(n1127) );
CMPR32X2TS U1535 ( .A(n1124), .B(n1123), .C(n1122), .CO(n1126), .S(n1121) );
INVX2TS U1536 ( .A(n1125), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N20) );
INVX2TS U1537 ( .A(DP_OP_111J144_123_4462_n44), .Y(n1132) );
INVX2TS U1538 ( .A(DP_OP_111J144_123_4462_n40), .Y(n1131) );
CMPR32X2TS U1539 ( .A(n1128), .B(n1127), .C(n1126), .CO(n1130), .S(n1125) );
INVX2TS U1540 ( .A(n1129), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N21) );
INVX2TS U1541 ( .A(DP_OP_111J144_123_4462_n39), .Y(n1136) );
INVX2TS U1542 ( .A(DP_OP_111J144_123_4462_n37), .Y(n1135) );
CMPR32X2TS U1543 ( .A(n1132), .B(n1131), .C(n1130), .CO(n1134), .S(n1129) );
INVX2TS U1544 ( .A(n1133), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N22) );
INVX2TS U1545 ( .A(DP_OP_111J144_123_4462_n36), .Y(n1143) );
CMPR32X2TS U1546 ( .A(n1136), .B(n1135), .C(n1134), .CO(n1142), .S(n1133) );
INVX2TS U1547 ( .A(DP_OP_111J144_123_4462_n35), .Y(n1140) );
AOI221X1TS U1548 ( .A0(n574), .A1(n572), .B0(n1413), .B1(n577), .C0(n1137),
.Y(n1139) );
INVX2TS U1549 ( .A(n591), .Y(n1766) );
AOI22X1TS U1550 ( .A0(n1766), .A1(n552), .B0(n622), .B1(n591), .Y(n1144) );
INVX2TS U1551 ( .A(n1138), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N23) );
CMPR32X2TS U1552 ( .A(n1140), .B(n1139), .C(n1144), .CO(n1784), .S(n1141) );
CMPR32X2TS U1553 ( .A(n1143), .B(n1142), .C(n1141), .CO(n1783), .S(n1138) );
INVX2TS U1554 ( .A(n1144), .Y(n1787) );
AOI22X1TS U1555 ( .A0(n1766), .A1(n627), .B0(n577), .B1(n591), .Y(n1786) );
CLKAND2X2TS U1556 ( .A(n1146), .B(n1145), .Y(n1785) );
INVX2TS U1557 ( .A(n1147), .Y(Sgf_operation_RECURSIVE_EVEN1_middle_N24) );
NAND2X1TS U1558 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n1720) );
NOR3X1TS U1559 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1720), .Y(ready) );
INVX2TS U1560 ( .A(ready), .Y(n1148) );
OAI21XLTS U1561 ( .A0(n1868), .A1(n1562), .B0(FS_Module_state_reg[3]), .Y(
n1149) );
OAI211XLTS U1562 ( .A0(n1889), .A1(n1564), .B0(n1588), .C0(n1149), .Y(n379)
);
INVX2TS U1563 ( .A(n1830), .Y(n1511) );
CLKBUFX3TS U1564 ( .A(n1511), .Y(n1595) );
XOR2X1TS U1565 ( .A(Op_MY[31]), .B(Op_MX[31]), .Y(n1717) );
NOR2XLTS U1566 ( .A(n1717), .B(underflow_flag), .Y(n1151) );
OAI32X1TS U1567 ( .A0(n1595), .A1(n1151), .A2(overflow_flag), .B0(n1830),
.B1(n1919), .Y(n262) );
CMPR32X2TS U1568 ( .A(n1154), .B(n1153), .C(n1152), .CO(n1158), .S(n1155) );
INVX2TS U1569 ( .A(n1155), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N3) );
CMPR32X2TS U1570 ( .A(n1158), .B(n1157), .C(n1156), .CO(n1163), .S(n1159) );
INVX2TS U1571 ( .A(n1159), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N4) );
CLKBUFX3TS U1572 ( .A(n1160), .Y(n1643) );
OAI211XLTS U1573 ( .A0(n1161), .A1(n1920), .B0(n1643), .C0(n1649), .Y(n309)
);
CMPR32X2TS U1574 ( .A(n1164), .B(n1163), .C(n1162), .CO(n1166), .S(n1165) );
INVX2TS U1575 ( .A(n1165), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N5) );
CMPR32X2TS U1576 ( .A(n1168), .B(n1167), .C(n1166), .CO(n1171), .S(n1169) );
INVX2TS U1577 ( .A(n1169), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N6) );
AOI22X1TS U1578 ( .A0(DP_OP_36J144_124_9196_n33), .A1(n1889), .B0(n1868),
.B1(n1921), .Y(n1170) );
OAI22X1TS U1579 ( .A0(n1170), .A1(n1562), .B0(P_Sgf[47]), .B1(n1563), .Y(
n378) );
CMPR32X2TS U1580 ( .A(n1173), .B(n1172), .C(n1171), .CO(n1175), .S(n1174) );
INVX2TS U1581 ( .A(n1174), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N7) );
CMPR32X2TS U1582 ( .A(n1177), .B(n1176), .C(n1175), .CO(n1179), .S(n1178) );
INVX2TS U1583 ( .A(n1178), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N8) );
CMPR32X2TS U1584 ( .A(n1181), .B(n1180), .C(n1179), .CO(n1183), .S(n1182) );
INVX2TS U1585 ( .A(n1182), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N9) );
CMPR32X2TS U1586 ( .A(n1185), .B(n1184), .C(n1183), .CO(n1187), .S(n1186) );
INVX2TS U1587 ( .A(n1186), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N10) );
CMPR32X2TS U1588 ( .A(n1189), .B(n1188), .C(n1187), .CO(n1226), .S(n1190) );
INVX2TS U1589 ( .A(n1190), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N11) );
NOR2BX1TS U1590 ( .AN(n644), .B(n608), .Y(n1356) );
AOI22X1TS U1591 ( .A0(n583), .A1(n486), .B0(n495), .B1(n1866), .Y(n1191) );
INVX2TS U1592 ( .A(n1192), .Y(mult_x_23_n47) );
AOI22X1TS U1593 ( .A0(n615), .A1(n1483), .B0(n1465), .B1(n553), .Y(n1193) );
OAI21XLTS U1594 ( .A0(n1483), .A1(n637), .B0(n1193), .Y(
DP_OP_111J144_123_4462_n252) );
CMPR32X2TS U1595 ( .A(n1196), .B(n1195), .C(n1194), .CO(n1206), .S(n1197) );
INVX2TS U1596 ( .A(n1197), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N15) );
CMPR32X2TS U1597 ( .A(n1200), .B(n1199), .C(n1198), .CO(n1194), .S(n1201) );
INVX2TS U1598 ( .A(n1201), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N14) );
INVX2TS U1599 ( .A(mult_x_23_n32), .Y(n1735) );
INVX2TS U1600 ( .A(mult_x_23_n31), .Y(n1732) );
CMPR32X2TS U1601 ( .A(n1204), .B(n1203), .C(n1202), .CO(n1733), .S(n878) );
INVX2TS U1602 ( .A(n1205), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N22) );
CMPR32X2TS U1603 ( .A(n1208), .B(n1207), .C(n1206), .CO(n871), .S(n1209) );
INVX2TS U1604 ( .A(n1209), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N16) );
CMPR32X2TS U1605 ( .A(n1212), .B(n1211), .C(n1210), .CO(n875), .S(n1213) );
INVX2TS U1606 ( .A(n1213), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N18) );
CMPR32X2TS U1607 ( .A(n1216), .B(n1215), .C(n1214), .CO(n1202), .S(n1217) );
INVX2TS U1608 ( .A(n1217), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N20) );
CMPR32X2TS U1609 ( .A(n1220), .B(n1219), .C(n1218), .CO(n1198), .S(n1221) );
INVX2TS U1610 ( .A(n1221), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N13) );
CMPR32X2TS U1611 ( .A(n1224), .B(n1223), .C(n1222), .CO(n1235), .S(n1225) );
INVX2TS U1612 ( .A(n1225), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N7) );
INVX2TS U1613 ( .A(mult_x_55_n32), .Y(n1755) );
INVX2TS U1614 ( .A(mult_x_55_n33), .Y(n1249) );
INVX2TS U1615 ( .A(mult_x_55_n35), .Y(n1248) );
INVX2TS U1616 ( .A(mult_x_55_n36), .Y(n1265) );
INVX2TS U1617 ( .A(mult_x_55_n40), .Y(n1264) );
INVX2TS U1618 ( .A(mult_x_55_n41), .Y(n1245) );
INVX2TS U1619 ( .A(mult_x_55_n45), .Y(n1244) );
INVX2TS U1620 ( .A(mult_x_55_n46), .Y(n1288) );
INVX2TS U1621 ( .A(mult_x_55_n58), .Y(n1285) );
INVX2TS U1622 ( .A(mult_x_55_n53), .Y(n1284) );
INVX2TS U1623 ( .A(mult_x_55_n66), .Y(n1297) );
INVX2TS U1624 ( .A(mult_x_55_n59), .Y(n1296) );
INVX2TS U1625 ( .A(mult_x_55_n74), .Y(n1253) );
INVX2TS U1626 ( .A(mult_x_55_n67), .Y(n1252) );
INVX2TS U1627 ( .A(mult_x_55_n84), .Y(n1273) );
INVX2TS U1628 ( .A(mult_x_55_n75), .Y(n1272) );
INVX2TS U1629 ( .A(mult_x_55_n93), .Y(n1293) );
INVX2TS U1630 ( .A(mult_x_55_n85), .Y(n1292) );
CMPR32X2TS U1631 ( .A(n1228), .B(n1227), .C(n1226), .CO(n1291), .S(n897) );
INVX2TS U1632 ( .A(mult_x_55_n31), .Y(n1758) );
AOI221X1TS U1633 ( .A0(n445), .A1(Op_MY[11]), .B0(n484), .B1(n1872), .C0(
n1229), .Y(n1757) );
INVX2TS U1634 ( .A(n1230), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N22) );
CMPR32X2TS U1635 ( .A(n1233), .B(n1232), .C(n1231), .CO(n1218), .S(n1234) );
INVX2TS U1636 ( .A(n1234), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N12) );
CMPR32X2TS U1637 ( .A(n1237), .B(n1236), .C(n1235), .CO(n1239), .S(n1238) );
INVX2TS U1638 ( .A(n1238), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N8) );
CMPR32X2TS U1639 ( .A(n1241), .B(n1240), .C(n1239), .CO(n1259), .S(n1242) );
INVX2TS U1640 ( .A(n1242), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N9) );
CMPR32X2TS U1641 ( .A(n1245), .B(n1244), .C(n1243), .CO(n1263), .S(n1246) );
INVX2TS U1642 ( .A(n1246), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N19) );
CMPR32X2TS U1643 ( .A(n1249), .B(n1248), .C(n1247), .CO(n1754), .S(n1250) );
INVX2TS U1644 ( .A(n1250), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N21) );
CMPR32X2TS U1645 ( .A(n1253), .B(n1252), .C(n1251), .CO(n1295), .S(n1254) );
INVX2TS U1646 ( .A(n1254), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N15) );
CMPR32X2TS U1647 ( .A(n1257), .B(n1256), .C(n1255), .CO(n1222), .S(n1258) );
INVX2TS U1648 ( .A(n1258), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N6) );
CMPR32X2TS U1649 ( .A(n1261), .B(n1260), .C(n1259), .CO(n1279), .S(n1262) );
INVX2TS U1650 ( .A(n1262), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N10) );
CMPR32X2TS U1651 ( .A(n1265), .B(n1264), .C(n1263), .CO(n1247), .S(n1266) );
INVX2TS U1652 ( .A(n1266), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N20) );
CMPR32X2TS U1653 ( .A(n1269), .B(n1268), .C(n1267), .CO(n1255), .S(n1270) );
INVX2TS U1654 ( .A(n1270), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N5) );
CMPR32X2TS U1655 ( .A(n1273), .B(n1272), .C(n1271), .CO(n1251), .S(n1274) );
INVX2TS U1656 ( .A(n1274), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N14) );
CMPR32X2TS U1657 ( .A(n1277), .B(n1276), .C(n1275), .CO(n1301), .S(n1278) );
INVX2TS U1658 ( .A(n1278), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N3) );
CMPR32X2TS U1659 ( .A(n1281), .B(n1280), .C(n1279), .CO(n1231), .S(n1282) );
INVX2TS U1660 ( .A(n1282), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N11) );
CMPR32X2TS U1661 ( .A(n1285), .B(n1284), .C(n1283), .CO(n1287), .S(n1286) );
INVX2TS U1662 ( .A(n1286), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N17) );
CMPR32X2TS U1663 ( .A(n1289), .B(n1288), .C(n1287), .CO(n1243), .S(n1290) );
INVX2TS U1664 ( .A(n1290), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N18) );
CMPR32X2TS U1665 ( .A(n1293), .B(n1292), .C(n1291), .CO(n1271), .S(n1294) );
INVX2TS U1666 ( .A(n1294), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N13) );
CMPR32X2TS U1667 ( .A(n1297), .B(n1296), .C(n1295), .CO(n1283), .S(n1298) );
INVX2TS U1668 ( .A(n1298), .Y(Sgf_operation_RECURSIVE_EVEN1_right_N16) );
CMPR32X2TS U1669 ( .A(n1301), .B(n1300), .C(n1299), .CO(n1268), .S(n1302) );
INVX2TS U1670 ( .A(n1302), .Y(Sgf_operation_RECURSIVE_EVEN1_left_N4) );
INVX2TS U1671 ( .A(DP_OP_111J144_123_4462_n58), .Y(n1319) );
AOI22X1TS U1672 ( .A0(n621), .A1(n1477), .B0(n499), .B1(n1778), .Y(n1303) );
INVX2TS U1673 ( .A(n1304), .Y(n1317) );
INVX2TS U1674 ( .A(n1305), .Y(DP_OP_111J144_123_4462_n51) );
AOI22X1TS U1675 ( .A0(n534), .A1(n500), .B0(n1770), .B1(n551), .Y(n1306) );
AOI22X1TS U1676 ( .A0(n536), .A1(n498), .B0(n1477), .B1(n555), .Y(n1307) );
INVX2TS U1677 ( .A(n1308), .Y(DP_OP_111J144_123_4462_n94) );
AOI22X1TS U1678 ( .A0(n528), .A1(n1413), .B0(n574), .B1(n552), .Y(n1309) );
OAI221X1TS U1679 ( .A0(n621), .A1(n1415), .B0(n627), .B1(n512), .C0(n1309),
.Y(DP_OP_111J144_123_4462_n176) );
AOI22X1TS U1680 ( .A0(n522), .A1(n500), .B0(n640), .B1(n556), .Y(n1310) );
AOI22X1TS U1681 ( .A0(n526), .A1(n499), .B0(n1477), .B1(n525), .Y(n1311) );
INVX2TS U1682 ( .A(n1312), .Y(DP_OP_111J144_123_4462_n84) );
AOI22X1TS U1683 ( .A0(n530), .A1(n1413), .B0(n574), .B1(n576), .Y(n1313) );
AOI22X1TS U1684 ( .A0(n588), .A1(n611), .B0(n537), .B1(n442), .Y(n1314) );
AOI22X1TS U1685 ( .A0(n532), .A1(n1413), .B0(n574), .B1(n557), .Y(n1315) );
AOI22X1TS U1686 ( .A0(n615), .A1(n1778), .B0(n1465), .B1(n527), .Y(n1316) );
OAI21X1TS U1687 ( .A0(n1467), .A1(n627), .B0(n1316), .Y(
DP_OP_111J144_123_4462_n247) );
CMPR32X2TS U1688 ( .A(n1319), .B(n1318), .C(n1317), .CO(n1305), .S(n1320) );
INVX2TS U1689 ( .A(n1320), .Y(DP_OP_111J144_123_4462_n52) );
CLKAND2X2TS U1690 ( .A(n1322), .B(n1321), .Y(n1327) );
AOI22X1TS U1691 ( .A0(n1453), .A1(n499), .B0(n641), .B1(n551), .Y(n1323) );
INVX2TS U1692 ( .A(n1324), .Y(DP_OP_111J144_123_4462_n75) );
AOI22X1TS U1693 ( .A0(n588), .A1(n458), .B0(n614), .B1(n442), .Y(n1325) );
CMPR32X2TS U1694 ( .A(n1328), .B(n1327), .C(n1326), .CO(n1324), .S(n1329) );
INVX2TS U1695 ( .A(n1329), .Y(DP_OP_111J144_123_4462_n76) );
AOI22X1TS U1696 ( .A0(n597), .A1(n464), .B0(n547), .B1(n1876), .Y(n1330) );
AOI22X1TS U1697 ( .A0(n595), .A1(n611), .B0(n538), .B1(n476), .Y(n1332) );
AOI22X1TS U1698 ( .A0(n522), .A1(n541), .B0(n568), .B1(n521), .Y(n1333) );
AOI22X1TS U1699 ( .A0(n587), .A1(n612), .B0(n538), .B1(n1873), .Y(n1334) );
CMPR32X2TS U1700 ( .A(n1337), .B(n1336), .C(n1335), .CO(n1338), .S(n901) );
INVX2TS U1701 ( .A(n1338), .Y(mult_x_55_n117) );
AOI22X1TS U1702 ( .A0(n595), .A1(n458), .B0(n614), .B1(n476), .Y(n1339) );
AOI22X1TS U1703 ( .A0(n587), .A1(n459), .B0(n614), .B1(n441), .Y(n1340) );
AOI22X1TS U1704 ( .A0(Op_MY[11]), .A1(n459), .B0(n1485), .B1(n481), .Y(n1341) );
CMPR32X2TS U1705 ( .A(n1344), .B(n1343), .C(n1342), .CO(n828), .S(n1345) );
INVX2TS U1706 ( .A(n1345), .Y(DP_OP_111J144_123_4462_n130) );
AOI22X1TS U1707 ( .A0(n1483), .A1(n500), .B0(n640), .B1(n555), .Y(n1346) );
AOI22X1TS U1708 ( .A0(n534), .A1(n502), .B0(n643), .B1(n551), .Y(n1347) );
AOI22X1TS U1709 ( .A0(n522), .A1(n502), .B0(n642), .B1(n521), .Y(n1348) );
AOI22X1TS U1710 ( .A0(n526), .A1(n501), .B0(n640), .B1(n525), .Y(n1349) );
INVX2TS U1711 ( .A(n1350), .Y(DP_OP_111J144_123_4462_n103) );
AOI22X1TS U1712 ( .A0(n598), .A1(n462), .B0(n448), .B1(n1880), .Y(n1351) );
AOI22X1TS U1713 ( .A0(Op_MY[22]), .A1(n390), .B0(n607), .B1(n1877), .Y(n1352) );
INVX2TS U1714 ( .A(n462), .Y(n1702) );
AOI22X1TS U1715 ( .A0(Op_MY[15]), .A1(n463), .B0(n448), .B1(n1865), .Y(n1353) );
AOI22X1TS U1716 ( .A0(n595), .A1(n464), .B0(n547), .B1(n476), .Y(n1354) );
INVX2TS U1717 ( .A(n1357), .Y(mult_x_23_n48) );
CMPR32X2TS U1718 ( .A(n1360), .B(n1359), .C(n1358), .CO(n844), .S(n1361) );
INVX2TS U1719 ( .A(n1361), .Y(mult_x_55_n48) );
AOI22X1TS U1720 ( .A0(n563), .A1(n445), .B0(n484), .B1(n524), .Y(n1362) );
AOI22X1TS U1721 ( .A0(n596), .A1(n445), .B0(n484), .B1(n477), .Y(n1363) );
AOI22X1TS U1722 ( .A0(Op_MY[22]), .A1(n392), .B0(n490), .B1(n1877), .Y(n1364) );
AOI22X1TS U1723 ( .A0(Op_MY[11]), .A1(n464), .B0(n547), .B1(n481), .Y(n1365)
);
CMPR32X2TS U1724 ( .A(n1368), .B(n1367), .C(n1366), .CO(n851), .S(n1369) );
INVX2TS U1725 ( .A(n1369), .Y(mult_x_55_n43) );
AOI22X1TS U1726 ( .A0(Op_MY[15]), .A1(n392), .B0(n490), .B1(n1865), .Y(n1370) );
AOI22X1TS U1727 ( .A0(n649), .A1(n390), .B0(n607), .B1(n1879), .Y(n1371) );
CMPR32X2TS U1728 ( .A(n1374), .B(n1373), .C(n1372), .CO(n1375), .S(n849) );
INVX2TS U1729 ( .A(n1375), .Y(mult_x_23_n117) );
AOI22X1TS U1730 ( .A0(n598), .A1(n392), .B0(n490), .B1(n1880), .Y(n1376) );
AOI22X1TS U1731 ( .A0(n615), .A1(n1773), .B0(n1465), .B1(n556), .Y(n1377) );
OAI21X1TS U1732 ( .A0(n1773), .A1(n637), .B0(n1377), .Y(
DP_OP_111J144_123_4462_n248) );
AOI22X1TS U1733 ( .A0(n393), .A1(n1700), .B0(n496), .B1(n1880), .Y(n1378) );
INVX2TS U1734 ( .A(n1379), .Y(mult_x_23_n80) );
AOI22X1TS U1735 ( .A0(n1488), .A1(n539), .B0(n1772), .B1(n576), .Y(n1380) );
CMPR32X2TS U1736 ( .A(n1383), .B(n1382), .C(n1381), .CO(n1342), .S(n1384) );
INVX2TS U1737 ( .A(n1384), .Y(DP_OP_111J144_123_4462_n137) );
AOI22X1TS U1738 ( .A0(n590), .A1(n391), .B0(n492), .B1(n1860), .Y(n1385) );
CMPR32X2TS U1739 ( .A(n1388), .B(n1387), .C(n1386), .CO(n1394), .S(n1389) );
INVX2TS U1740 ( .A(n1389), .Y(DP_OP_111J144_123_4462_n111) );
AOI22X1TS U1741 ( .A0(n616), .A1(n526), .B0(n1465), .B1(n535), .Y(n1390) );
OAI21X1TS U1742 ( .A0(n1416), .A1(n637), .B0(n1390), .Y(
DP_OP_111J144_123_4462_n251) );
AOI22X1TS U1743 ( .A0(n616), .A1(n522), .B0(n1465), .B1(n533), .Y(n1391) );
OAI21X1TS U1744 ( .A0(n1492), .A1(n637), .B0(n1391), .Y(
DP_OP_111J144_123_4462_n249) );
CMPR32X2TS U1745 ( .A(n1394), .B(n1393), .C(n1392), .CO(n1395), .S(n1350) );
INVX2TS U1746 ( .A(n1395), .Y(DP_OP_111J144_123_4462_n102) );
AOI22X1TS U1747 ( .A0(n565), .A1(n1768), .B0(n570), .B1(n516), .Y(n1396) );
NOR2X1TS U1748 ( .A(n1766), .B(n594), .Y(DP_OP_111J144_123_4462_n172) );
AOI22X1TS U1749 ( .A0(n567), .A1(n1413), .B0(n575), .B1(n624), .Y(n1397) );
CMPR32X2TS U1750 ( .A(n1780), .B(n1399), .C(n1398), .CO(n1400), .S(n1312) );
INVX2TS U1751 ( .A(n1400), .Y(DP_OP_111J144_123_4462_n83) );
INVX2TS U1752 ( .A(n1402), .Y(mult_x_23_n79) );
AOI22X1TS U1753 ( .A0(n522), .A1(n609), .B0(n636), .B1(n556), .Y(n1403) );
AOI22X1TS U1754 ( .A0(n518), .A1(n1413), .B0(n575), .B1(n553), .Y(n1404) );
INVX2TS U1755 ( .A(n1405), .Y(DP_OP_111J144_123_4462_n216) );
AOI22X1TS U1756 ( .A0(n1498), .A1(n1413), .B0(n575), .B1(n516), .Y(n1406) );
CMPR32X2TS U1757 ( .A(n1780), .B(n1408), .C(n1407), .CO(n1409), .S(n1308) );
INVX2TS U1758 ( .A(n1409), .Y(DP_OP_111J144_123_4462_n93) );
AOI22X1TS U1759 ( .A0(n526), .A1(n1413), .B0(n575), .B1(n554), .Y(n1410) );
AOI22X1TS U1760 ( .A0(n534), .A1(n633), .B0(n575), .B1(n533), .Y(n1411) );
AOI22X1TS U1761 ( .A0(n1492), .A1(n633), .B0(n575), .B1(n556), .Y(n1412) );
AOI22X1TS U1762 ( .A0(n536), .A1(n633), .B0(n574), .B1(n535), .Y(n1414) );
AOI22X1TS U1763 ( .A0(n588), .A1(n617), .B0(n466), .B1(n442), .Y(n1417) );
NAND2X1TS U1764 ( .A(n478), .B(n471), .Y(n1427) );
INVX2TS U1765 ( .A(n1418), .Y(mult_x_55_n79) );
CMPR32X2TS U1766 ( .A(n1421), .B(n1420), .C(n1419), .CO(n1422), .S(n816) );
INVX2TS U1767 ( .A(n1422), .Y(mult_x_23_n124) );
CMPR32X2TS U1768 ( .A(n1425), .B(n1424), .C(n1423), .CO(n1426), .S(n830) );
INVX2TS U1769 ( .A(n1426), .Y(mult_x_55_n71) );
CMPR32X2TS U1770 ( .A(n1429), .B(n1428), .C(n1427), .CO(n1418), .S(n1430) );
INVX2TS U1771 ( .A(n1430), .Y(mult_x_55_n80) );
NOR2X1TS U1772 ( .A(n523), .B(n1867), .Y(mult_x_55_n149) );
INVX2TS U1773 ( .A(n1477), .Y(n1510) );
INVX2TS U1774 ( .A(DP_OP_111J144_123_4462_n42), .Y(
DP_OP_111J144_123_4462_n41) );
AOI22X1TS U1775 ( .A0(Op_MY[8]), .A1(n457), .B0(n1749), .B1(n1875), .Y(n1431) );
CMPR32X2TS U1776 ( .A(n1434), .B(n1433), .C(n1432), .CO(n1435), .S(n837) );
INVX2TS U1777 ( .A(n1435), .Y(mult_x_55_n98) );
AOI221X1TS U1778 ( .A0(n1872), .A1(n537), .B0(Op_MY[11]), .B1(n612), .C0(
n394), .Y(n1436) );
INVX2TS U1779 ( .A(n1436), .Y(mult_x_55_n212) );
AOI22X1TS U1780 ( .A0(n460), .A1(Op_MY[6]), .B0(n1439), .B1(n519), .Y(n1437)
);
OAI21X1TS U1781 ( .A0(Op_MY[6]), .A1(n455), .B0(n1437), .Y(mult_x_55_n232)
);
AOI22X1TS U1782 ( .A0(n560), .A1(n390), .B0(n607), .B1(n1854), .Y(n1438) );
NOR2X1TS U1783 ( .A(n519), .B(n1867), .Y(mult_x_55_n151) );
AOI22X1TS U1784 ( .A0(n460), .A1(n596), .B0(n1439), .B1(n524), .Y(n1440) );
OAI21X1TS U1785 ( .A0(n596), .A1(n455), .B0(n1440), .Y(mult_x_55_n228) );
AOI22X1TS U1786 ( .A0(Op_MY[2]), .A1(n446), .B0(n484), .B1(n479), .Y(n1441)
);
OAI221X1TS U1787 ( .A0(n586), .A1(n469), .B0(n441), .B1(n451), .C0(n1441),
.Y(mult_x_55_n165) );
AOI22X1TS U1788 ( .A0(n584), .A1(n446), .B0(n485), .B1(n474), .Y(n1442) );
AOI22X1TS U1789 ( .A0(n584), .A1(n464), .B0(n547), .B1(n475), .Y(n1443) );
AOI22X1TS U1790 ( .A0(Op_MY[13]), .A1(n390), .B0(n607), .B1(n444), .Y(n1444)
);
CMPR32X2TS U1791 ( .A(n1447), .B(n1446), .C(n1445), .CO(n1448), .S(n835) );
INVX2TS U1792 ( .A(n1448), .Y(mult_x_55_n124) );
AOI22X1TS U1793 ( .A0(Op_MY[4]), .A1(n446), .B0(n485), .B1(n1874), .Y(n1449)
);
OAI221X1TS U1794 ( .A0(n558), .A1(n469), .B0(n519), .B1(n451), .C0(n1449),
.Y(mult_x_55_n163) );
AOI22X1TS U1795 ( .A0(Op_MX[10]), .A1(n599), .B0(n1867), .B1(n1881), .Y(
n1450) );
OAI221XLTS U1796 ( .A0(n1881), .A1(Op_MX[10]), .B0(n1867), .B1(n600), .C0(
n1450), .Y(n1451) );
OAI221X1TS U1797 ( .A0(n584), .A1(n469), .B0(n474), .B1(n451), .C0(n1451),
.Y(mult_x_55_n167) );
AOI22X1TS U1798 ( .A0(n582), .A1(n392), .B0(n490), .B1(n1878), .Y(n1452) );
AOI22X1TS U1799 ( .A0(n534), .A1(n541), .B0(n568), .B1(n533), .Y(n1454) );
INVX2TS U1800 ( .A(DP_OP_111J144_123_4462_n67), .Y(
DP_OP_111J144_123_4462_n68) );
AOI22X1TS U1801 ( .A0(Op_MY[16]), .A1(n392), .B0(n491), .B1(n1864), .Y(n1455) );
AOI22X1TS U1802 ( .A0(Op_MY[4]), .A1(n459), .B0(n1485), .B1(n1874), .Y(n1456) );
INVX2TS U1803 ( .A(n1776), .Y(n1457) );
OAI221X1TS U1804 ( .A0(n572), .A1(n639), .B0(n577), .B1(n549), .C0(n1457),
.Y(DP_OP_111J144_123_4462_n231) );
AOI22X1TS U1805 ( .A0(n1492), .A1(n1768), .B0(n570), .B1(n556), .Y(n1458) );
NOR2X1TS U1806 ( .A(n599), .B(n1459), .Y(mult_x_55_n168) );
AOI22X1TS U1807 ( .A0(Op_MY[16]), .A1(n463), .B0(n1703), .B1(n1864), .Y(
n1460) );
AOI22X1TS U1808 ( .A0(Op_MY[17]), .A1(n390), .B0(n607), .B1(n1878), .Y(n1461) );
NOR2X1TS U1809 ( .A(n599), .B(n1462), .Y(mult_x_55_n196) );
AOI22X1TS U1810 ( .A0(Op_MY[16]), .A1(n390), .B0(n607), .B1(n1864), .Y(n1463) );
AOI22X1TS U1811 ( .A0(n1496), .A1(n541), .B0(n568), .B1(n624), .Y(n1464) );
AOI22X1TS U1812 ( .A0(n616), .A1(n577), .B0(n1465), .B1(n622), .Y(n1466) );
OAI21X1TS U1813 ( .A0(n1467), .A1(n578), .B0(n1466), .Y(
DP_OP_111J144_123_4462_n246) );
AOI22X1TS U1814 ( .A0(Op_MY[18]), .A1(n391), .B0(n492), .B1(n1879), .Y(n1468) );
AOI22X1TS U1815 ( .A0(n590), .A1(n463), .B0(n1703), .B1(n1860), .Y(n1469) );
AOI22X1TS U1816 ( .A0(n1498), .A1(n541), .B0(n568), .B1(n516), .Y(n1470) );
OAI221X1TS U1817 ( .A0(n567), .A1(n1477), .B0(n566), .B1(n498), .C0(n1470),
.Y(DP_OP_111J144_123_4462_n196) );
AOI22X1TS U1818 ( .A0(Op_MY[4]), .A1(n612), .B0(n538), .B1(n1874), .Y(n1471)
);
AOI22X1TS U1819 ( .A0(n558), .A1(n465), .B0(n548), .B1(n520), .Y(n1472) );
AOI22X1TS U1820 ( .A0(n393), .A1(n391), .B0(n492), .B1(n1880), .Y(n1473) );
AOI22X1TS U1821 ( .A0(Op_MY[8]), .A1(n459), .B0(n1485), .B1(n1875), .Y(n1474) );
AOI22X1TS U1822 ( .A0(Op_MY[8]), .A1(n446), .B0(n485), .B1(n1875), .Y(n1475)
);
OAI221X1TS U1823 ( .A0(n562), .A1(n470), .B0(n523), .B1(n1748), .C0(n1475),
.Y(mult_x_55_n159) );
AOI22X1TS U1824 ( .A0(n1488), .A1(n542), .B0(n568), .B1(n576), .Y(n1476) );
AOI22X1TS U1825 ( .A0(n588), .A1(n446), .B0(n485), .B1(n442), .Y(n1478) );
AOI22X1TS U1826 ( .A0(n589), .A1(n465), .B0(n548), .B1(n1863), .Y(n1479) );
AOI22X1TS U1827 ( .A0(Op_MY[8]), .A1(n612), .B0(n538), .B1(n1875), .Y(n1480)
);
AOI22X1TS U1828 ( .A0(n1481), .A1(n539), .B0(n1772), .B1(n553), .Y(n1482) );
AOI22X1TS U1829 ( .A0(n590), .A1(n392), .B0(n491), .B1(n1860), .Y(n1484) );
AOI22X1TS U1830 ( .A0(n559), .A1(n459), .B0(n1485), .B1(n520), .Y(n1486) );
AOI22X1TS U1831 ( .A0(n597), .A1(n457), .B0(n1749), .B1(n1876), .Y(n1487) );
AOI22X1TS U1832 ( .A0(n1488), .A1(n1768), .B0(n570), .B1(n576), .Y(n1489) );
AOI22X1TS U1833 ( .A0(Op_MY[4]), .A1(n465), .B0(n548), .B1(n1874), .Y(n1491)
);
INVX2TS U1834 ( .A(mult_x_55_n64), .Y(mult_x_55_n63) );
AOI22X1TS U1835 ( .A0(n1492), .A1(n539), .B0(n1772), .B1(n556), .Y(n1493) );
AOI22X1TS U1836 ( .A0(n393), .A1(n390), .B0(n608), .B1(n1880), .Y(n1494) );
AOI22X1TS U1837 ( .A0(n589), .A1(n457), .B0(n1749), .B1(n1863), .Y(n1495) );
INVX2TS U1838 ( .A(mult_x_55_n38), .Y(mult_x_55_n37) );
AOI22X1TS U1839 ( .A0(n1496), .A1(n609), .B0(n636), .B1(n624), .Y(n1497) );
OAI221X1TS U1840 ( .A0(n565), .A1(n549), .B0(n564), .B1(n1779), .C0(n1497),
.Y(DP_OP_111J144_123_4462_n240) );
AOI22X1TS U1841 ( .A0(n452), .A1(Op_MY[22]), .B0(n1503), .B1(n1866), .Y(
n1499) );
OAI21X1TS U1842 ( .A0(Op_MY[22]), .A1(n1505), .B0(n1499), .Y(mult_x_23_n222)
);
AOI22X1TS U1843 ( .A0(Op_MY[2]), .A1(n465), .B0(n548), .B1(n479), .Y(n1500)
);
AOI22X1TS U1844 ( .A0(n452), .A1(Op_MY[18]), .B0(n1503), .B1(n1878), .Y(
n1504) );
OAI21X1TS U1845 ( .A0(Op_MY[18]), .A1(n1505), .B0(n1504), .Y(mult_x_23_n226)
);
CLKAND2X2TS U1846 ( .A(n1506), .B(n1508), .Y(DP_OP_111J144_123_4462_n214) );
AO21XLTS U1847 ( .A0(n594), .A1(n1507), .B0(n571), .Y(
DP_OP_111J144_123_4462_n156) );
CLKAND2X2TS U1848 ( .A(n1509), .B(n1508), .Y(DP_OP_111J144_123_4462_n200) );
AO21XLTS U1849 ( .A0(n594), .A1(n1510), .B0(n569), .Y(
DP_OP_111J144_123_4462_n155) );
NAND2BXLTS U1850 ( .AN(n491), .B(n483), .Y(mult_x_23_n192) );
INVX2TS U1851 ( .A(n1828), .Y(n1516) );
CLKBUFX2TS U1852 ( .A(n1511), .Y(n1513) );
AO22XLTS U1853 ( .A0(Sgf_normalized_result[2]), .A1(n1516), .B0(
final_result_ieee[2]), .B1(n1513), .Y(n188) );
AO22XLTS U1854 ( .A0(Sgf_normalized_result[3]), .A1(n1516), .B0(
final_result_ieee[3]), .B1(n1513), .Y(n187) );
AO22XLTS U1855 ( .A0(Sgf_normalized_result[7]), .A1(n1516), .B0(
final_result_ieee[7]), .B1(n1511), .Y(n183) );
AO22XLTS U1856 ( .A0(Sgf_normalized_result[8]), .A1(n1516), .B0(
final_result_ieee[8]), .B1(n1511), .Y(n182) );
AO22XLTS U1857 ( .A0(Sgf_normalized_result[4]), .A1(n1516), .B0(
final_result_ieee[4]), .B1(n1513), .Y(n186) );
AO22XLTS U1858 ( .A0(Sgf_normalized_result[9]), .A1(n1516), .B0(
final_result_ieee[9]), .B1(n1511), .Y(n181) );
AO22XLTS U1859 ( .A0(Sgf_normalized_result[5]), .A1(n1516), .B0(
final_result_ieee[5]), .B1(n1513), .Y(n185) );
INVX2TS U1860 ( .A(n1828), .Y(n1593) );
AO22XLTS U1861 ( .A0(Sgf_normalized_result[10]), .A1(n1593), .B0(
final_result_ieee[10]), .B1(n1513), .Y(n180) );
NAND2X1TS U1862 ( .A(Op_MX[9]), .B(n1512), .Y(mult_x_55_n169) );
AO22XLTS U1863 ( .A0(Sgf_normalized_result[1]), .A1(n1516), .B0(
final_result_ieee[1]), .B1(n1513), .Y(n189) );
AO22XLTS U1864 ( .A0(Sgf_normalized_result[12]), .A1(n1593), .B0(
final_result_ieee[12]), .B1(n1511), .Y(n178) );
AO22XLTS U1865 ( .A0(Sgf_normalized_result[11]), .A1(n1593), .B0(
final_result_ieee[11]), .B1(n1513), .Y(n179) );
AO22XLTS U1866 ( .A0(Sgf_normalized_result[13]), .A1(n1593), .B0(
final_result_ieee[13]), .B1(n1511), .Y(n177) );
AO22XLTS U1867 ( .A0(Sgf_normalized_result[14]), .A1(n1593), .B0(
final_result_ieee[14]), .B1(n1511), .Y(n176) );
AO22XLTS U1868 ( .A0(Sgf_normalized_result[15]), .A1(n1593), .B0(
final_result_ieee[15]), .B1(n1595), .Y(n175) );
CLKBUFX3TS U1869 ( .A(n1566), .Y(n1657) );
CLKBUFX2TS U1870 ( .A(n1566), .Y(n1656) );
INVX2TS U1871 ( .A(n1656), .Y(n1655) );
AO22XLTS U1872 ( .A0(n1654), .A1(Op_MX[13]), .B0(n1655), .B1(Data_MX[13]),
.Y(n357) );
NAND2X1TS U1873 ( .A(Op_MX[3]), .B(n1515), .Y(mult_x_55_n211) );
AO22XLTS U1874 ( .A0(Sgf_normalized_result[6]), .A1(n1516), .B0(
final_result_ieee[6]), .B1(n1511), .Y(n184) );
AO22XLTS U1875 ( .A0(Sgf_normalized_result[0]), .A1(n1516), .B0(
final_result_ieee[0]), .B1(n1595), .Y(n190) );
XNOR2X1TS U1876 ( .A(DP_OP_36J144_124_9196_n1), .B(n1564), .Y(n1517) );
AO22XLTS U1877 ( .A0(n1517), .A1(n1832), .B0(n1843), .B1(
Exp_module_Overflow_flag_A), .Y(n271) );
CLKBUFX2TS U1878 ( .A(n1527), .Y(n1633) );
INVX2TS U1879 ( .A(n1633), .Y(n1846) );
CLKBUFX3TS U1880 ( .A(n1527), .Y(n1684) );
AO22XLTS U1881 ( .A0(n1846), .A1(P_Sgf[2]), .B0(n1684), .B1(
Sgf_operation_Result[2]), .Y(n217) );
INVX2TS U1882 ( .A(n1656), .Y(n1689) );
CLKBUFX3TS U1883 ( .A(n1566), .Y(n1654) );
AO22XLTS U1884 ( .A0(n1689), .A1(Data_MX[31]), .B0(n1654), .B1(Op_MX[31]),
.Y(n343) );
AO22XLTS U1885 ( .A0(n1843), .A1(P_Sgf[0]), .B0(n1684), .B1(
Sgf_operation_Result[0]), .Y(n215) );
INVX2TS U1886 ( .A(n1527), .Y(n1680) );
CMPR32X2TS U1887 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[19]), .B(n1519),
.C(n1518), .CO(n1677), .S(n1520) );
AO22XLTS U1888 ( .A0(n1680), .A1(P_Sgf[19]), .B0(n1684), .B1(n1520), .Y(n234) );
INVX2TS U1889 ( .A(n1832), .Y(n1696) );
CMPR32X2TS U1890 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .B(n1522),
.C(n1521), .CO(n1681), .S(n1523) );
AO22XLTS U1891 ( .A0(n1696), .A1(P_Sgf[15]), .B0(n1684), .B1(n1523), .Y(n230) );
CLKBUFX3TS U1892 ( .A(n1527), .Y(n1844) );
CMPR32X2TS U1893 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[14]), .B(n1525),
.C(n1524), .CO(n1521), .S(n1526) );
AO22XLTS U1894 ( .A0(n1696), .A1(P_Sgf[14]), .B0(n1844), .B1(n1526), .Y(n229) );
CLKBUFX3TS U1895 ( .A(n1527), .Y(n1690) );
AO22XLTS U1896 ( .A0(n1846), .A1(P_Sgf[7]), .B0(n1690), .B1(
Sgf_operation_Result[7]), .Y(n222) );
AO22XLTS U1897 ( .A0(n1846), .A1(P_Sgf[3]), .B0(n1684), .B1(
Sgf_operation_Result[3]), .Y(n218) );
CLKBUFX3TS U1898 ( .A(n1527), .Y(n1666) );
CMPR32X2TS U1899 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[22]), .B(n1529),
.C(n1528), .CO(n1638), .S(n1530) );
AO22XLTS U1900 ( .A0(n1680), .A1(P_Sgf[22]), .B0(n1666), .B1(n1530), .Y(n237) );
CMPR32X2TS U1901 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[18]), .B(n1532),
.C(n1531), .CO(n1518), .S(n1533) );
AO22XLTS U1902 ( .A0(n1680), .A1(P_Sgf[18]), .B0(n1684), .B1(n1533), .Y(n233) );
CMPR32X2TS U1903 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[17]), .B(n1535),
.C(n1534), .CO(n1531), .S(n1536) );
AO22XLTS U1904 ( .A0(n1696), .A1(P_Sgf[17]), .B0(n1684), .B1(n1536), .Y(n232) );
AO22XLTS U1905 ( .A0(n1696), .A1(P_Sgf[10]), .B0(n1690), .B1(
Sgf_operation_Result[10]), .Y(n225) );
AO22XLTS U1906 ( .A0(n1846), .A1(P_Sgf[6]), .B0(n1690), .B1(
Sgf_operation_Result[6]), .Y(n221) );
AO22XLTS U1907 ( .A0(n1846), .A1(P_Sgf[5]), .B0(n1690), .B1(
Sgf_operation_Result[5]), .Y(n220) );
AO22XLTS U1908 ( .A0(n1657), .A1(Op_MX[0]), .B0(n1655), .B1(Data_MX[0]), .Y(
n344) );
NAND4XLTS U1909 ( .A(n1539), .B(n1538), .C(n1537), .D(n1867), .Y(n1560) );
NAND4XLTS U1910 ( .A(n1543), .B(n1542), .C(n1541), .D(n1540), .Y(n1559) );
NOR4X1TS U1911 ( .A(Op_MX[24]), .B(Op_MX[26]), .C(Op_MX[25]), .D(Op_MX[23]),
.Y(n1547) );
NOR4X1TS U1912 ( .A(Op_MX[30]), .B(Op_MX[29]), .C(Op_MX[28]), .D(Op_MX[27]),
.Y(n1546) );
NOR4X1TS U1913 ( .A(Op_MX[12]), .B(Op_MX[8]), .C(Op_MX[10]), .D(Op_MX[9]),
.Y(n1545) );
NOR4X1TS U1914 ( .A(Op_MX[0]), .B(Op_MX[5]), .C(Op_MX[6]), .D(Op_MX[7]), .Y(
n1544) );
NAND4XLTS U1915 ( .A(n1547), .B(n1546), .C(n1545), .D(n1544), .Y(n1558) );
NAND4XLTS U1916 ( .A(n1855), .B(n1861), .C(n1871), .D(n1899), .Y(n1548) );
NOR4X1TS U1917 ( .A(n598), .B(Op_MY[29]), .C(Op_MY[28]), .D(n1548), .Y(n1556) );
NOR4X1TS U1918 ( .A(n584), .B(Op_MY[23]), .C(Op_MY[30]), .D(Op_MY[4]), .Y(
n1554) );
NAND4XLTS U1919 ( .A(n600), .B(n524), .C(n1864), .D(n1878), .Y(n1552) );
NAND4XLTS U1920 ( .A(n441), .B(n479), .C(n520), .D(n442), .Y(n1551) );
NAND4XLTS U1921 ( .A(n1865), .B(n440), .C(n1859), .D(n1879), .Y(n1550) );
NAND4XLTS U1922 ( .A(n580), .B(n1860), .C(n1866), .D(n1877), .Y(n1549) );
NOR4X1TS U1923 ( .A(n1552), .B(n1551), .C(n1550), .D(n1549), .Y(n1553) );
NAND4XLTS U1924 ( .A(n1556), .B(n1555), .C(n1554), .D(n1553), .Y(n1557) );
OAI31X1TS U1925 ( .A0(n1560), .A1(n1559), .A2(n1558), .B0(n1557), .Y(n1561)
);
AO22XLTS U1926 ( .A0(n1649), .A1(zero_flag), .B0(n1599), .B1(n1561), .Y(n311) );
AO22XLTS U1927 ( .A0(n1598), .A1(Op_MX[9]), .B0(n1655), .B1(Data_MX[9]), .Y(
n353) );
INVX2TS U1928 ( .A(n1656), .Y(n1653) );
AO22XLTS U1929 ( .A0(n1653), .A1(Data_MY[25]), .B0(n1688), .B1(Op_MY[25]),
.Y(n337) );
AO22XLTS U1930 ( .A0(n1688), .A1(Op_MX[12]), .B0(n1655), .B1(Data_MX[12]),
.Y(n356) );
AOI32X1TS U1931 ( .A0(FS_Module_state_reg[1]), .A1(n1868), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n1562), .Y(
n1565) );
NAND3XLTS U1932 ( .A(n1565), .B(n1564), .C(n1563), .Y(n376) );
CLKBUFX2TS U1933 ( .A(n1566), .Y(n1600) );
INVX2TS U1934 ( .A(n1600), .Y(n1601) );
AO22XLTS U1935 ( .A0(n1601), .A1(Data_MY[24]), .B0(n1654), .B1(Op_MY[24]),
.Y(n336) );
CLKBUFX2TS U1936 ( .A(n1566), .Y(n1688) );
INVX2TS U1937 ( .A(n1656), .Y(n1660) );
AO22XLTS U1938 ( .A0(n1654), .A1(Op_MX[15]), .B0(n1660), .B1(Data_MX[15]),
.Y(n359) );
AO22XLTS U1939 ( .A0(n1653), .A1(Data_MY[26]), .B0(n1657), .B1(Op_MY[26]),
.Y(n338) );
AO22XLTS U1940 ( .A0(n1662), .A1(Op_MX[3]), .B0(n1655), .B1(Data_MX[3]), .Y(
n347) );
AO22XLTS U1941 ( .A0(n1688), .A1(Op_MX[5]), .B0(n1689), .B1(Data_MX[5]), .Y(
n349) );
AO22XLTS U1942 ( .A0(n1601), .A1(Data_MY[27]), .B0(n1598), .B1(Op_MY[27]),
.Y(n339) );
AO22XLTS U1943 ( .A0(n1657), .A1(Op_MX[17]), .B0(n1689), .B1(Data_MX[17]),
.Y(n361) );
AO22XLTS U1944 ( .A0(n1598), .A1(Op_MX[19]), .B0(n1689), .B1(Data_MX[19]),
.Y(n363) );
AO22XLTS U1945 ( .A0(n1662), .A1(Op_MX[21]), .B0(n1655), .B1(Data_MX[21]),
.Y(n365) );
AO22XLTS U1946 ( .A0(n1654), .A1(Op_MX[7]), .B0(n1689), .B1(Data_MX[7]), .Y(
n351) );
INVX2TS U1947 ( .A(n1832), .Y(n1629) );
CMPR32X2TS U1948 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .B(n1568),
.C(n1567), .CO(n1607), .S(n1569) );
AO22XLTS U1949 ( .A0(n1629), .A1(P_Sgf[36]), .B0(n1666), .B1(n1569), .Y(n251) );
CMPR32X2TS U1950 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .B(n1571),
.C(n1570), .CO(n1609), .S(n1572) );
AO22XLTS U1951 ( .A0(n1629), .A1(P_Sgf[34]), .B0(n1666), .B1(n1572), .Y(n249) );
CMPR32X2TS U1952 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .B(n1574),
.C(n1573), .CO(n1612), .S(n1575) );
AO22XLTS U1953 ( .A0(n1629), .A1(P_Sgf[32]), .B0(n1690), .B1(n1575), .Y(n247) );
CMPR32X2TS U1954 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .B(n1577),
.C(n1576), .CO(n1615), .S(n1578) );
AO22XLTS U1955 ( .A0(n1629), .A1(P_Sgf[30]), .B0(n1832), .B1(n1578), .Y(n245) );
CMPR32X2TS U1956 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .B(n1580),
.C(n1579), .CO(n1618), .S(n1581) );
AO22XLTS U1957 ( .A0(n1629), .A1(P_Sgf[28]), .B0(n1633), .B1(n1581), .Y(n243) );
CMPR32X2TS U1958 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .B(n1583),
.C(n1582), .CO(n1626), .S(n1584) );
AO22XLTS U1959 ( .A0(n1680), .A1(P_Sgf[26]), .B0(n1633), .B1(n1584), .Y(n241) );
CMPR32X2TS U1960 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .B(n1586),
.C(n1585), .CO(n1630), .S(n1587) );
AO22XLTS U1961 ( .A0(n1680), .A1(P_Sgf[24]), .B0(n1633), .B1(n1587), .Y(n239) );
NAND2X1TS U1962 ( .A(n1649), .B(n1915), .Y(n375) );
AOI32X1TS U1963 ( .A0(n1590), .A1(n701), .A2(n1589), .B0(n1916), .B1(n1588),
.Y(n307) );
OR3X1TS U1964 ( .A(Sgf_normalized_result[2]), .B(Sgf_normalized_result[1]),
.C(Sgf_normalized_result[0]), .Y(n1793) );
OAI21XLTS U1965 ( .A0(Sgf_normalized_result[1]), .A1(
Sgf_normalized_result[0]), .B0(Sgf_normalized_result[2]), .Y(n1591) );
AOI32X1TS U1966 ( .A0(n1793), .A1(n1692), .A2(n1591), .B0(n1917), .B1(n1643),
.Y(n304) );
NAND2X1TS U1967 ( .A(Op_MX[19]), .B(Op_MX[20]), .Y(n1592) );
NAND2X1TS U1968 ( .A(Op_MX[21]), .B(n1592), .Y(mult_x_23_n163) );
AO22XLTS U1969 ( .A0(Sgf_normalized_result[16]), .A1(n1593), .B0(
final_result_ieee[16]), .B1(n1595), .Y(n174) );
AO22XLTS U1970 ( .A0(Sgf_normalized_result[17]), .A1(n1593), .B0(
final_result_ieee[17]), .B1(n1595), .Y(n173) );
AO22XLTS U1971 ( .A0(Sgf_normalized_result[18]), .A1(n1593), .B0(
final_result_ieee[18]), .B1(n1595), .Y(n172) );
AO22XLTS U1972 ( .A0(Sgf_normalized_result[19]), .A1(n1593), .B0(
final_result_ieee[19]), .B1(n1595), .Y(n171) );
NAND2X1TS U1973 ( .A(Op_MX[15]), .B(n1594), .Y(mult_x_23_n205) );
INVX2TS U1974 ( .A(n1828), .Y(n1596) );
AO22XLTS U1975 ( .A0(Sgf_normalized_result[20]), .A1(n1596), .B0(
final_result_ieee[20]), .B1(n1595), .Y(n170) );
AO22XLTS U1976 ( .A0(Sgf_normalized_result[21]), .A1(n1596), .B0(
final_result_ieee[21]), .B1(n1595), .Y(n169) );
AO22XLTS U1977 ( .A0(Sgf_normalized_result[22]), .A1(n1596), .B0(
final_result_ieee[22]), .B1(n1511), .Y(n167) );
CLKBUFX3TS U1978 ( .A(n1566), .Y(n1662) );
INVX2TS U1979 ( .A(n1656), .Y(n1661) );
AO22XLTS U1980 ( .A0(n1657), .A1(n393), .B0(n1661), .B1(Data_MY[19]), .Y(
n331) );
AO22XLTS U1981 ( .A0(n1601), .A1(Data_MY[28]), .B0(n1662), .B1(Op_MY[28]),
.Y(n340) );
AO22XLTS U1982 ( .A0(n1653), .A1(Data_MY[29]), .B0(n1688), .B1(Op_MY[29]),
.Y(n341) );
INVX2TS U1983 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[21]), .Y(n1602) );
INVX2TS U1984 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[19]), .Y(n1622) );
INVX2TS U1985 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[17]), .Y(n1624) );
CLKAND2X2TS U1986 ( .A(n1845), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[15]),
.Y(n1848) );
NAND2X1TS U1987 ( .A(n1848), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[16]),
.Y(n1841) );
NAND2X1TS U1988 ( .A(n1839), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[18]),
.Y(n1838) );
NAND2X1TS U1989 ( .A(n1836), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[20]),
.Y(n1835) );
NAND2X1TS U1990 ( .A(n1833), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[22]),
.Y(n1831) );
XNOR2X1TS U1991 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[23]), .B(n1831),
.Y(n1597) );
AO22XLTS U1992 ( .A0(n1680), .A1(P_Sgf[47]), .B0(n1844), .B1(n1597), .Y(n380) );
AO22XLTS U1993 ( .A0(n1601), .A1(Data_MY[30]), .B0(n1654), .B1(Op_MY[30]),
.Y(n342) );
AO22XLTS U1994 ( .A0(n1653), .A1(Data_MX[28]), .B0(n1657), .B1(Op_MX[28]),
.Y(n372) );
AO22XLTS U1995 ( .A0(n1653), .A1(Data_MX[25]), .B0(n1600), .B1(Op_MX[25]),
.Y(n369) );
AO22XLTS U1996 ( .A0(n1601), .A1(Data_MX[29]), .B0(n1600), .B1(Op_MX[29]),
.Y(n373) );
AO22XLTS U1997 ( .A0(n1601), .A1(Data_MX[26]), .B0(n1600), .B1(Op_MX[26]),
.Y(n370) );
AO22XLTS U1998 ( .A0(n1601), .A1(Data_MX[27]), .B0(n1598), .B1(Op_MX[27]),
.Y(n371) );
AO22XLTS U1999 ( .A0(n1601), .A1(Data_MX[23]), .B0(n1600), .B1(Op_MX[23]),
.Y(n367) );
NOR2X4TS U2000 ( .A(n1599), .B(n1844), .Y(n1667) );
MX2X1TS U2001 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n1667),
.Y(n281) );
NAND2X1TS U2002 ( .A(Sgf_normalized_result[3]), .B(n1793), .Y(n1792) );
NAND2X1TS U2003 ( .A(n1905), .B(n1792), .Y(n1796) );
NAND2X1TS U2004 ( .A(Sgf_normalized_result[5]), .B(n1796), .Y(n1795) );
NAND2X1TS U2005 ( .A(Sgf_normalized_result[7]), .B(n1799), .Y(n1798) );
NAND2X1TS U2006 ( .A(Sgf_normalized_result[9]), .B(n1802), .Y(n1801) );
NAND2X1TS U2007 ( .A(Sgf_normalized_result[11]), .B(n1805), .Y(n1804) );
NAND2X1TS U2008 ( .A(Sgf_normalized_result[13]), .B(n1808), .Y(n1807) );
NAND2X1TS U2009 ( .A(Sgf_normalized_result[15]), .B(n1811), .Y(n1810) );
NAND2X1TS U2010 ( .A(Sgf_normalized_result[17]), .B(n1814), .Y(n1813) );
NAND2X1TS U2011 ( .A(Sgf_normalized_result[19]), .B(n1817), .Y(n1816) );
NAND2X1TS U2012 ( .A(Sgf_normalized_result[21]), .B(n1821), .Y(n1819) );
AOI21X1TS U2013 ( .A0(n1825), .A1(Sgf_normalized_result[23]), .B0(n1643),
.Y(n1824) );
AOI2BB1XLTS U2014 ( .A0N(n1692), .A1N(FSM_add_overflow_flag), .B0(n1824),
.Y(n282) );
AO22XLTS U2015 ( .A0(n1653), .A1(Data_MX[30]), .B0(n1600), .B1(Op_MX[30]),
.Y(n374) );
MX2X1TS U2016 ( .A(Op_MY[23]), .B(Data_MY[23]), .S0(n1601), .Y(n335) );
MX2X1TS U2017 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n1667),
.Y(n280) );
MX2X1TS U2018 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n1667),
.Y(n279) );
MX2X1TS U2019 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n1667),
.Y(n278) );
MX2X1TS U2020 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n1667),
.Y(n277) );
MX2X1TS U2021 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n1667),
.Y(n276) );
MX2X1TS U2022 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n1667),
.Y(n275) );
MX2X1TS U2023 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n1667),
.Y(n273) );
AO22XLTS U2024 ( .A0(n1601), .A1(Data_MX[24]), .B0(Op_MX[24]), .B1(n1600),
.Y(n368) );
AOI21X1TS U2025 ( .A0(n1835), .A1(n1602), .B0(n1833), .Y(n1603) );
AO22XLTS U2026 ( .A0(n1843), .A1(P_Sgf[45]), .B0(n1666), .B1(n1603), .Y(n260) );
INVX2TS U2027 ( .A(n1160), .Y(n1691) );
OAI21XLTS U2028 ( .A0(n1792), .A1(n1905), .B0(n1796), .Y(n1604) );
CLKBUFX3TS U2029 ( .A(n1160), .Y(n1827) );
AO22XLTS U2030 ( .A0(n1691), .A1(n1604), .B0(n1827), .B1(Add_result[4]), .Y(
n302) );
XOR2XLTS U2031 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .B(n1605),
.Y(n1606) );
XOR2XLTS U2032 ( .A(n1607), .B(n1606), .Y(n1608) );
AO22XLTS U2033 ( .A0(n1843), .A1(P_Sgf[37]), .B0(n1666), .B1(n1608), .Y(n252) );
CMPR32X2TS U2034 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .B(n1610),
.C(n1609), .CO(n1567), .S(n1611) );
AO22XLTS U2035 ( .A0(n1629), .A1(P_Sgf[35]), .B0(n1666), .B1(n1611), .Y(n250) );
CMPR32X2TS U2036 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .B(n1613),
.C(n1612), .CO(n1570), .S(n1614) );
AO22XLTS U2037 ( .A0(n1629), .A1(P_Sgf[33]), .B0(n1666), .B1(n1614), .Y(n248) );
CMPR32X2TS U2038 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .B(n1616),
.C(n1615), .CO(n1573), .S(n1617) );
AO22XLTS U2039 ( .A0(n1629), .A1(P_Sgf[31]), .B0(n1690), .B1(n1617), .Y(n246) );
CMPR32X2TS U2040 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .B(n1619),
.C(n1618), .CO(n1576), .S(n1620) );
AO22XLTS U2041 ( .A0(n1629), .A1(P_Sgf[29]), .B0(n1633), .B1(n1620), .Y(n244) );
AO21XLTS U2042 ( .A0(Add_result[22]), .A1(n1827), .B0(n1621), .Y(n284) );
AOI21X1TS U2043 ( .A0(n1838), .A1(n1622), .B0(n1836), .Y(n1623) );
AO22XLTS U2044 ( .A0(n1843), .A1(P_Sgf[43]), .B0(n1666), .B1(n1623), .Y(n258) );
AOI21X1TS U2045 ( .A0(n1841), .A1(n1624), .B0(n1839), .Y(n1625) );
AO22XLTS U2046 ( .A0(n1843), .A1(P_Sgf[41]), .B0(n1666), .B1(n1625), .Y(n256) );
CMPR32X2TS U2047 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .B(n1627),
.C(n1626), .CO(n1579), .S(n1628) );
AO22XLTS U2048 ( .A0(n1629), .A1(P_Sgf[27]), .B0(n1633), .B1(n1628), .Y(n242) );
CMPR32X2TS U2049 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .B(n1631),
.C(n1630), .CO(n1582), .S(n1632) );
AO22XLTS U2050 ( .A0(n1680), .A1(P_Sgf[25]), .B0(n1633), .B1(n1632), .Y(n240) );
AOI21X1TS U2051 ( .A0(n1897), .A1(n1816), .B0(n1821), .Y(n1634) );
AO22XLTS U2052 ( .A0(n1691), .A1(n1634), .B0(n1160), .B1(Add_result[20]),
.Y(n286) );
AOI21X1TS U2053 ( .A0(n1896), .A1(n1813), .B0(n1817), .Y(n1635) );
AO22XLTS U2054 ( .A0(n1691), .A1(n1635), .B0(n1643), .B1(Add_result[18]),
.Y(n288) );
AOI21X1TS U2055 ( .A0(n1895), .A1(n1810), .B0(n1814), .Y(n1636) );
AO22XLTS U2056 ( .A0(n1691), .A1(n1636), .B0(n1643), .B1(Add_result[16]),
.Y(n290) );
AOI21X1TS U2057 ( .A0(n1894), .A1(n1807), .B0(n1811), .Y(n1637) );
AO22XLTS U2058 ( .A0(n1692), .A1(n1637), .B0(n1643), .B1(Add_result[14]),
.Y(n292) );
CMPR32X2TS U2059 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .B(n1639),
.C(n1638), .CO(n1585), .S(n1640) );
AO22XLTS U2060 ( .A0(n1680), .A1(P_Sgf[23]), .B0(n1690), .B1(n1640), .Y(n238) );
AOI21X1TS U2061 ( .A0(n1893), .A1(n1804), .B0(n1808), .Y(n1641) );
AO22XLTS U2062 ( .A0(n1692), .A1(n1641), .B0(n1643), .B1(Add_result[12]),
.Y(n294) );
AOI21X1TS U2063 ( .A0(n1892), .A1(n1801), .B0(n1805), .Y(n1642) );
AO22XLTS U2064 ( .A0(n1692), .A1(n1642), .B0(n1643), .B1(Add_result[10]),
.Y(n296) );
AOI21X1TS U2065 ( .A0(n1891), .A1(n1798), .B0(n1802), .Y(n1644) );
AO22XLTS U2066 ( .A0(n1692), .A1(n1644), .B0(n1643), .B1(Add_result[8]), .Y(
n298) );
AOI21X1TS U2067 ( .A0(n1890), .A1(n1795), .B0(n1799), .Y(n1645) );
AO22XLTS U2068 ( .A0(n1692), .A1(n1645), .B0(n1827), .B1(Add_result[6]), .Y(
n300) );
NOR2XLTS U2069 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n1646) );
AOI21X1TS U2070 ( .A0(Sgf_normalized_result[0]), .A1(
Sgf_normalized_result[1]), .B0(n1646), .Y(n1647) );
AOI2BB2XLTS U2071 ( .B0(n1692), .B1(n1647), .A0N(Add_result[1]), .A1N(n1691),
.Y(n305) );
NOR3XLTS U2072 ( .A(Exp_module_Data_S[7]), .B(Exp_module_Data_S[8]), .C(
n1649), .Y(n1651) );
AND4X1TS U2073 ( .A(Exp_module_Data_S[6]), .B(Exp_module_Data_S[3]), .C(
Exp_module_Data_S[2]), .D(Exp_module_Data_S[1]), .Y(n1648) );
NAND4XLTS U2074 ( .A(Exp_module_Data_S[0]), .B(Exp_module_Data_S[5]), .C(
Exp_module_Data_S[4]), .D(n1648), .Y(n1650) );
AO22XLTS U2075 ( .A0(n1651), .A1(n1650), .B0(underflow_flag), .B1(n1649),
.Y(n272) );
CLKAND2X2TS U2076 ( .A(FSM_selector_A), .B(exp_oper_result[8]), .Y(
S_Oper_A_exp[8]) );
MX2X1TS U2077 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
NOR3BX1TS U2078 ( .AN(Op_MY[30]), .B(FSM_selector_B[0]), .C(
FSM_selector_B[1]), .Y(n1652) );
XOR2X1TS U2079 ( .A(DP_OP_36J144_124_9196_n33), .B(n1652), .Y(
DP_OP_36J144_124_9196_n15) );
AO22XLTS U2080 ( .A0(n1662), .A1(Op_MX[22]), .B0(n1660), .B1(Data_MX[22]),
.Y(n366) );
AO22XLTS U2081 ( .A0(n1653), .A1(Data_MX[18]), .B0(n1654), .B1(Op_MX[18]),
.Y(n362) );
AO22XLTS U2082 ( .A0(n1653), .A1(Data_MX[4]), .B0(n1657), .B1(Op_MX[4]), .Y(
n348) );
AO22XLTS U2083 ( .A0(n1653), .A1(Data_MX[20]), .B0(n1598), .B1(Op_MX[20]),
.Y(n364) );
AO22XLTS U2084 ( .A0(n1689), .A1(Data_MX[16]), .B0(n1657), .B1(Op_MX[16]),
.Y(n360) );
AO22XLTS U2085 ( .A0(n1689), .A1(Data_MX[6]), .B0(n1598), .B1(Op_MX[6]), .Y(
n350) );
AO22XLTS U2086 ( .A0(n1689), .A1(Data_MX[8]), .B0(n1662), .B1(Op_MX[8]), .Y(
n352) );
AO22XLTS U2087 ( .A0(n1653), .A1(Data_MX[2]), .B0(n1662), .B1(Op_MX[2]), .Y(
n346) );
AO22XLTS U2088 ( .A0(n1689), .A1(Data_MX[14]), .B0(n1566), .B1(Op_MX[14]),
.Y(n358) );
AO22XLTS U2089 ( .A0(n1688), .A1(Op_MX[10]), .B0(n1655), .B1(Data_MX[10]),
.Y(n354) );
AO22XLTS U2090 ( .A0(n1654), .A1(n630), .B0(n1660), .B1(Data_MY[0]), .Y(n312) );
AO22XLTS U2091 ( .A0(n1657), .A1(Op_MX[1]), .B0(n1655), .B1(Data_MX[1]), .Y(
n345) );
AO22XLTS U2092 ( .A0(n1598), .A1(n471), .B0(n1655), .B1(Data_MX[11]), .Y(
n355) );
AO22XLTS U2093 ( .A0(n1598), .A1(n473), .B0(n1655), .B1(Data_MY[12]), .Y(
n324) );
CLKBUFX3TS U2094 ( .A(n1662), .Y(n1659) );
INVX2TS U2095 ( .A(n1656), .Y(n1658) );
AO22XLTS U2096 ( .A0(n1659), .A1(n563), .B0(n1658), .B1(Data_MY[9]), .Y(n321) );
AO22XLTS U2097 ( .A0(n1659), .A1(n559), .B0(n1661), .B1(Data_MY[5]), .Y(n317) );
AO22XLTS U2098 ( .A0(n1662), .A1(n561), .B0(n1660), .B1(Data_MY[14]), .Y(
n326) );
AO22XLTS U2099 ( .A0(n1659), .A1(n478), .B0(n1660), .B1(Data_MY[2]), .Y(n314) );
AO22XLTS U2100 ( .A0(n1662), .A1(n581), .B0(n1660), .B1(Data_MY[15]), .Y(
n327) );
AO22XLTS U2101 ( .A0(n1654), .A1(n582), .B0(n1660), .B1(Data_MY[17]), .Y(
n329) );
AO22XLTS U2102 ( .A0(n1657), .A1(n583), .B0(n1661), .B1(Data_MY[21]), .Y(
n333) );
AO22XLTS U2103 ( .A0(n1659), .A1(n585), .B0(n1661), .B1(Data_MY[1]), .Y(n313) );
AO22XLTS U2104 ( .A0(n1659), .A1(n587), .B0(n1660), .B1(Data_MY[3]), .Y(n315) );
AO22XLTS U2105 ( .A0(n1688), .A1(n645), .B0(n1661), .B1(Data_MY[22]), .Y(
n334) );
AO22XLTS U2106 ( .A0(n1659), .A1(n589), .B0(n1658), .B1(Data_MY[7]), .Y(n319) );
AO22XLTS U2107 ( .A0(n1598), .A1(n590), .B0(n1661), .B1(Data_MY[20]), .Y(
n332) );
AO22XLTS U2108 ( .A0(n1662), .A1(n646), .B0(n1660), .B1(Data_MY[16]), .Y(
n328) );
AO22XLTS U2109 ( .A0(n1654), .A1(Op_MY[11]), .B0(n1658), .B1(Data_MY[11]),
.Y(n323) );
AO22XLTS U2110 ( .A0(n1659), .A1(n597), .B0(n1661), .B1(Data_MY[6]), .Y(n318) );
AO22XLTS U2111 ( .A0(n1659), .A1(n648), .B0(n1661), .B1(Data_MY[8]), .Y(n320) );
AO22XLTS U2112 ( .A0(n1659), .A1(n596), .B0(n1658), .B1(Data_MY[10]), .Y(
n322) );
AO22XLTS U2113 ( .A0(n1659), .A1(n647), .B0(n1661), .B1(Data_MY[4]), .Y(n316) );
AO22XLTS U2114 ( .A0(n1657), .A1(Op_MY[13]), .B0(n1660), .B1(Data_MY[13]),
.Y(n325) );
AO22XLTS U2115 ( .A0(n1598), .A1(n649), .B0(n1661), .B1(Data_MY[18]), .Y(
n330) );
CMPR32X2TS U2116 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[21]), .B(n1664),
.C(n1663), .CO(n1528), .S(n1665) );
AO22XLTS U2117 ( .A0(n1680), .A1(P_Sgf[21]), .B0(n1666), .B1(n1665), .Y(n236) );
MX2X1TS U2118 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n1667),
.Y(n274) );
NOR2XLTS U2119 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1668) );
NAND2X2TS U2120 ( .A(FSM_selector_B[0]), .B(n1883), .Y(n1675) );
OAI21XLTS U2121 ( .A0(FSM_selector_B[0]), .A1(n1668), .B0(n1675), .Y(n1669)
);
XOR2X1TS U2122 ( .A(DP_OP_36J144_124_9196_n33), .B(n1669), .Y(
DP_OP_36J144_124_9196_n22) );
MX2X1TS U2123 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
MX2X1TS U2124 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
OAI21XLTS U2125 ( .A0(FSM_selector_B[1]), .A1(n1899), .B0(n1675), .Y(n1670)
);
XOR2X1TS U2126 ( .A(DP_OP_36J144_124_9196_n33), .B(n1670), .Y(
DP_OP_36J144_124_9196_n21) );
MX2X1TS U2127 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
OAI21XLTS U2128 ( .A0(FSM_selector_B[1]), .A1(n1871), .B0(n1675), .Y(n1671)
);
XOR2X1TS U2129 ( .A(DP_OP_36J144_124_9196_n33), .B(n1671), .Y(
DP_OP_36J144_124_9196_n20) );
MX2X1TS U2130 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
OAI21XLTS U2131 ( .A0(FSM_selector_B[1]), .A1(n1861), .B0(n1675), .Y(n1672)
);
XOR2X1TS U2132 ( .A(DP_OP_36J144_124_9196_n33), .B(n1672), .Y(
DP_OP_36J144_124_9196_n19) );
MX2X1TS U2133 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
OAI21XLTS U2134 ( .A0(FSM_selector_B[1]), .A1(n1855), .B0(n1675), .Y(n1673)
);
XOR2X1TS U2135 ( .A(n635), .B(n1673), .Y(DP_OP_36J144_124_9196_n18) );
MX2X1TS U2136 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
OAI2BB1X1TS U2137 ( .A0N(Op_MY[28]), .A1N(n1883), .B0(n1675), .Y(n1674) );
XOR2X1TS U2138 ( .A(n635), .B(n1674), .Y(DP_OP_36J144_124_9196_n17) );
MX2X1TS U2139 ( .A(Op_MX[29]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
OAI2BB1X1TS U2140 ( .A0N(Op_MY[29]), .A1N(n1883), .B0(n1675), .Y(n1676) );
XOR2X1TS U2141 ( .A(n635), .B(n1676), .Y(DP_OP_36J144_124_9196_n16) );
CMPR32X2TS U2142 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[20]), .B(n1678),
.C(n1677), .CO(n1663), .S(n1679) );
AO22XLTS U2143 ( .A0(n1680), .A1(P_Sgf[20]), .B0(n1684), .B1(n1679), .Y(n235) );
CMPR32X2TS U2144 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .B(n1682),
.C(n1681), .CO(n1534), .S(n1683) );
AO22XLTS U2145 ( .A0(n1696), .A1(P_Sgf[16]), .B0(n1684), .B1(n1683), .Y(n231) );
AO22XLTS U2146 ( .A0(n1846), .A1(P_Sgf[4]), .B0(n1684), .B1(
Sgf_operation_Result[4]), .Y(n219) );
AO22XLTS U2147 ( .A0(n1696), .A1(P_Sgf[9]), .B0(n1690), .B1(
Sgf_operation_Result[9]), .Y(n224) );
AOI21X1TS U2148 ( .A0(n1686), .A1(n1685), .B0(n1693), .Y(n1687) );
AO22XLTS U2149 ( .A0(n1696), .A1(P_Sgf[12]), .B0(n1844), .B1(n1687), .Y(n227) );
AO22XLTS U2150 ( .A0(n1689), .A1(Data_MY[31]), .B0(n1688), .B1(Op_MY[31]),
.Y(n310) );
AO22XLTS U2151 ( .A0(n1696), .A1(P_Sgf[11]), .B0(n1690), .B1(
Sgf_operation_Result[11]), .Y(n226) );
AO22XLTS U2152 ( .A0(n1696), .A1(P_Sgf[8]), .B0(n1690), .B1(
Sgf_operation_Result[8]), .Y(n223) );
AO22XLTS U2153 ( .A0(n1846), .A1(P_Sgf[1]), .B0(n1844), .B1(
Sgf_operation_Result[1]), .Y(n216) );
AOI2BB2XLTS U2154 ( .B0(n1692), .B1(Sgf_normalized_result[0]), .A0N(
Add_result[0]), .A1N(n1691), .Y(n306) );
CMPR32X2TS U2155 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[13]), .B(n1694),
.C(n1693), .CO(n1524), .S(n1695) );
AO22XLTS U2156 ( .A0(n1696), .A1(P_Sgf[13]), .B0(n1844), .B1(n1695), .Y(n228) );
NAND2BXLTS U2157 ( .AN(n493), .B(n487), .Y(mult_x_23_n164) );
NAND2X1TS U2158 ( .A(Op_MX[17]), .B(Op_MX[18]), .Y(n1698) );
NAND2X1TS U2159 ( .A(Op_MX[19]), .B(n1698), .Y(mult_x_23_n177) );
AOI22X1TS U2160 ( .A0(Op_MY[21]), .A1(n390), .B0(n608), .B1(n1866), .Y(n1699) );
NAND2X1TS U2161 ( .A(n507), .B(n1702), .Y(mult_x_23_n206) );
AOI22X1TS U2162 ( .A0(Op_MY[21]), .A1(n463), .B0(n1703), .B1(n1866), .Y(
n1704) );
CMPR32X2TS U2163 ( .A(n472), .B(n1706), .C(n1705), .CO(mult_x_23_n98), .S(
mult_x_23_n99) );
NAND2X1TS U2164 ( .A(Op_MX[7]), .B(n1707), .Y(mult_x_55_n183) );
NAND2X1TS U2165 ( .A(Op_MX[3]), .B(Op_MX[4]), .Y(n1708) );
NAND2X1TS U2166 ( .A(Op_MX[5]), .B(n1708), .Y(mult_x_55_n197) );
NAND2X1TS U2167 ( .A(Op_MX[15]), .B(Op_MX[16]), .Y(n1709) );
NAND2X1TS U2168 ( .A(Op_MX[17]), .B(n1709), .Y(mult_x_23_n191) );
NOR4X1TS U2169 ( .A(P_Sgf[13]), .B(P_Sgf[17]), .C(P_Sgf[15]), .D(P_Sgf[16]),
.Y(n1716) );
NOR4X1TS U2170 ( .A(P_Sgf[20]), .B(P_Sgf[18]), .C(P_Sgf[19]), .D(P_Sgf[21]),
.Y(n1715) );
NOR4X1TS U2171 ( .A(P_Sgf[1]), .B(P_Sgf[5]), .C(P_Sgf[3]), .D(P_Sgf[4]), .Y(
n1713) );
NOR3XLTS U2172 ( .A(P_Sgf[22]), .B(P_Sgf[2]), .C(P_Sgf[0]), .Y(n1712) );
NOR4X1TS U2173 ( .A(P_Sgf[9]), .B(P_Sgf[10]), .C(P_Sgf[14]), .D(P_Sgf[12]),
.Y(n1711) );
NOR4X1TS U2174 ( .A(P_Sgf[8]), .B(P_Sgf[6]), .C(P_Sgf[7]), .D(P_Sgf[11]),
.Y(n1710) );
AND4X1TS U2175 ( .A(n1713), .B(n1712), .C(n1711), .D(n1710), .Y(n1714) );
NAND3XLTS U2176 ( .A(n1716), .B(n1715), .C(n1714), .Y(n1719) );
MXI2X1TS U2177 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n1717), .Y(n1718)
);
OAI211X1TS U2178 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n1719), .C0(
n1718), .Y(n1850) );
AOI22X1TS U2179 ( .A0(n1721), .A1(n1720), .B0(n1849), .B1(n1850), .Y(n1722)
);
OAI2BB1X1TS U2180 ( .A0N(n1723), .A1N(n1921), .B0(n1722), .Y(n377) );
AOI21X1TS U2181 ( .A0(n1725), .A1(n1724), .B0(mult_x_23_n106), .Y(
mult_x_23_n107) );
AOI21X1TS U2182 ( .A0(n1727), .A1(n1726), .B0(mult_x_23_n119), .Y(
mult_x_23_n120) );
AOI21X1TS U2183 ( .A0(n1729), .A1(n1728), .B0(mult_x_23_n129), .Y(
mult_x_23_n130) );
OAI22X1TS U2184 ( .A0(Op_MY[22]), .A1(n1731), .B0(n583), .B1(n468), .Y(
mult_x_23_n152) );
OAI22X1TS U2185 ( .A0(Op_MY[21]), .A1(n1731), .B0(Op_MY[20]), .B1(n468), .Y(
mult_x_23_n153) );
OAI22X1TS U2186 ( .A0(n590), .A1(n625), .B0(n598), .B1(n468), .Y(
mult_x_23_n154) );
OAI22X1TS U2187 ( .A0(Op_MY[18]), .A1(n467), .B0(n598), .B1(n1731), .Y(
mult_x_23_n155) );
OAI22X1TS U2188 ( .A0(Op_MY[18]), .A1(n1731), .B0(n582), .B1(n467), .Y(
mult_x_23_n156) );
OAI22X1TS U2189 ( .A0(Op_MY[17]), .A1(n1731), .B0(Op_MY[16]), .B1(n467), .Y(
mult_x_23_n157) );
OAI22X1TS U2190 ( .A0(n646), .A1(n1731), .B0(n581), .B1(n468), .Y(
mult_x_23_n158) );
OAI22X1TS U2191 ( .A0(n561), .A1(n467), .B0(n581), .B1(n1731), .Y(
mult_x_23_n159) );
OAI22X1TS U2192 ( .A0(n443), .A1(n467), .B0(n560), .B1(n625), .Y(
mult_x_23_n160) );
OAI22X1TS U2193 ( .A0(n443), .A1(n625), .B0(n472), .B1(n468), .Y(
mult_x_23_n161) );
AOI22X1TS U2194 ( .A0(n561), .A1(n391), .B0(n493), .B1(n1854), .Y(n1730) );
OAI221XLTS U2195 ( .A0(n443), .A1(n495), .B0(n1859), .B1(n487), .C0(n1730),
.Y(mult_x_23_n174) );
NAND2X1TS U2196 ( .A(Op_MX[21]), .B(Op_MX[22]), .Y(n1739) );
CMPR32X2TS U2197 ( .A(n1735), .B(n1734), .C(n1733), .CO(n1736), .S(n1205) );
XNOR2X1TS U2198 ( .A(n1737), .B(n1736), .Y(n1738) );
XOR2XLTS U2199 ( .A(n1739), .B(n1738), .Y(n1740) );
XNOR2X1TS U2200 ( .A(Op_MY[22]), .B(n1740), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N23) );
AOI21X1TS U2201 ( .A0(n1742), .A1(n1741), .B0(mult_x_55_n106), .Y(
mult_x_55_n107) );
AOI21X1TS U2202 ( .A0(n1744), .A1(n1743), .B0(mult_x_55_n119), .Y(
mult_x_55_n120) );
AOI21X1TS U2203 ( .A0(n1746), .A1(n1745), .B0(mult_x_55_n129), .Y(
mult_x_55_n130) );
AOI22X1TS U2204 ( .A0(n597), .A1(n446), .B0(n485), .B1(n1876), .Y(n1747) );
OAI221XLTS U2205 ( .A0(n589), .A1(n470), .B0(n442), .B1(n451), .C0(n1747),
.Y(mult_x_55_n161) );
AOI22X1TS U2206 ( .A0(Op_MY[2]), .A1(n457), .B0(n1749), .B1(n479), .Y(n1750)
);
OAI221XLTS U2207 ( .A0(n585), .A1(n515), .B0(n475), .B1(n626), .C0(n1750),
.Y(mult_x_55_n180) );
OAI221XLTS U2208 ( .A0(n480), .A1(n546), .B0(n481), .B1(n489), .C0(n613),
.Y(mult_x_55_n198) );
CMPR32X2TS U2209 ( .A(n1755), .B(n1754), .C(n1753), .CO(n1765), .S(n1230) );
CMPR32X2TS U2210 ( .A(n1758), .B(n1757), .C(n1756), .CO(n1763), .S(n1753) );
AOI22X1TS U2211 ( .A0(n596), .A1(n480), .B0(n1872), .B1(n477), .Y(n1760) );
OAI21XLTS U2212 ( .A0(n1761), .A1(n1760), .B0(n471), .Y(n1759) );
AOI21X1TS U2213 ( .A0(n1761), .A1(n1760), .B0(n1759), .Y(n1762) );
XOR2XLTS U2214 ( .A(n1763), .B(n1762), .Y(n1764) );
XNOR2X1TS U2215 ( .A(n1765), .B(n1764), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N23) );
AOI22X1TS U2216 ( .A0(n1766), .A1(n521), .B0(n552), .B1(n591), .Y(
DP_OP_111J144_123_4462_n162) );
AOI22X1TS U2217 ( .A0(n1766), .A1(n551), .B0(n521), .B1(n591), .Y(
DP_OP_111J144_123_4462_n163) );
AOI22X1TS U2218 ( .A0(n1766), .A1(n525), .B0(n551), .B1(n591), .Y(
DP_OP_111J144_123_4462_n164) );
AOI22X1TS U2219 ( .A0(n1766), .A1(n555), .B0(n525), .B1(n592), .Y(
DP_OP_111J144_123_4462_n165) );
AOI22X1TS U2220 ( .A0(n1766), .A1(n517), .B0(n555), .B1(n592), .Y(
DP_OP_111J144_123_4462_n166) );
AOI22X1TS U2221 ( .A0(n438), .A1(n566), .B0(n517), .B1(n592), .Y(
DP_OP_111J144_123_4462_n167) );
AOI22X1TS U2222 ( .A0(n438), .A1(n564), .B0(n566), .B1(n592), .Y(
DP_OP_111J144_123_4462_n168) );
AOI22X1TS U2223 ( .A0(n438), .A1(n531), .B0(n516), .B1(n592), .Y(
DP_OP_111J144_123_4462_n169) );
AOI22X1TS U2224 ( .A0(n438), .A1(n529), .B0(n531), .B1(n592), .Y(
DP_OP_111J144_123_4462_n170) );
AOI22X1TS U2225 ( .A0(n438), .A1(n593), .B0(n529), .B1(n592), .Y(
DP_OP_111J144_123_4462_n171) );
AOI22X1TS U2226 ( .A0(n621), .A1(n570), .B0(n1768), .B1(n1778), .Y(n1767) );
OAI221XLTS U2227 ( .A0(n573), .A1(n501), .B0(n578), .B1(n640), .C0(n1767),
.Y(DP_OP_111J144_123_4462_n202) );
AOI22X1TS U2228 ( .A0(n528), .A1(n1768), .B0(n570), .B1(n527), .Y(n1769) );
OAI221XLTS U2229 ( .A0(n622), .A1(n501), .B0(n437), .B1(n640), .C0(n1769),
.Y(DP_OP_111J144_123_4462_n203) );
AOI22X1TS U2230 ( .A0(n622), .A1(n1772), .B0(n540), .B1(n627), .Y(n1771) );
OAI221XLTS U2231 ( .A0(n573), .A1(n503), .B0(n578), .B1(n643), .C0(n1771),
.Y(DP_OP_111J144_123_4462_n217) );
AOI22X1TS U2232 ( .A0(n1773), .A1(n539), .B0(n1772), .B1(n527), .Y(n1774) );
OAI221XLTS U2233 ( .A0(n622), .A1(n503), .B0(n627), .B1(n642), .C0(n1774),
.Y(DP_OP_111J144_123_4462_n218) );
AOI22X1TS U2234 ( .A0(n573), .A1(n636), .B0(n610), .B1(n577), .Y(n1777) );
OAI221XLTS U2235 ( .A0(n622), .A1(n639), .B0(n437), .B1(n550), .C0(n1777),
.Y(DP_OP_111J144_123_4462_n232) );
AOI21X1TS U2236 ( .A0(n1781), .A1(n578), .B0(n1780), .Y(
DP_OP_111J144_123_4462_n245) );
CMPR32X2TS U2237 ( .A(n1784), .B(n1783), .C(n1782), .CO(n1791), .S(n1147) );
CMPR32X2TS U2238 ( .A(n1787), .B(n1786), .C(n1785), .CO(n1789), .S(n1782) );
OAI31X1TS U2239 ( .A0(n572), .A1(n1789), .A2(n591), .B0(n1788), .Y(n1790) );
XNOR2X1TS U2240 ( .A(n1791), .B(n1790), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N25) );
CLKBUFX2TS U2241 ( .A(n1160), .Y(n1823) );
INVX2TS U2242 ( .A(n1160), .Y(n1820) );
OAI211XLTS U2243 ( .A0(Sgf_normalized_result[3]), .A1(n1793), .B0(n1820),
.C0(n1792), .Y(n1794) );
OAI2BB1X1TS U2244 ( .A0N(Add_result[3]), .A1N(n1823), .B0(n1794), .Y(n303)
);
OAI2BB1X1TS U2245 ( .A0N(Add_result[5]), .A1N(n1823), .B0(n1797), .Y(n301)
);
OAI2BB1X1TS U2246 ( .A0N(Add_result[7]), .A1N(n1827), .B0(n1800), .Y(n299)
);
OAI2BB1X1TS U2247 ( .A0N(Add_result[9]), .A1N(n1827), .B0(n1803), .Y(n297)
);
OAI2BB1X1TS U2248 ( .A0N(Add_result[11]), .A1N(n1827), .B0(n1806), .Y(n295)
);
OAI2BB1X1TS U2249 ( .A0N(Add_result[13]), .A1N(n1827), .B0(n1809), .Y(n293)
);
OAI2BB1X1TS U2250 ( .A0N(Add_result[15]), .A1N(n1827), .B0(n1812), .Y(n291)
);
OAI2BB1X1TS U2251 ( .A0N(Add_result[17]), .A1N(n1827), .B0(n1815), .Y(n289)
);
OAI2BB1X1TS U2252 ( .A0N(Add_result[19]), .A1N(n1823), .B0(n1818), .Y(n287)
);
OAI2BB1X1TS U2253 ( .A0N(Add_result[21]), .A1N(n1823), .B0(n1822), .Y(n285)
);
OAI2BB1X1TS U2254 ( .A0N(Add_result[23]), .A1N(n1827), .B0(n1826), .Y(n283)
);
OA22X1TS U2255 ( .A0(n1830), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n1828), .Y(n270) );
CLKBUFX2TS U2256 ( .A(n1828), .Y(n1829) );
OA22X1TS U2257 ( .A0(n1830), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n1829), .Y(n269) );
OA22X1TS U2258 ( .A0(n1830), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n1829), .Y(n268) );
OA22X1TS U2259 ( .A0(n1830), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n1829), .Y(n267) );
OA22X1TS U2260 ( .A0(n1830), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n1829), .Y(n266) );
OA22X1TS U2261 ( .A0(n1830), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n1829), .Y(n265) );
OA22X1TS U2262 ( .A0(n1830), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n1829), .Y(n264) );
OA22X1TS U2263 ( .A0(n1830), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n1829), .Y(n263) );
OAI2BB1X1TS U2264 ( .A0N(n1846), .A1N(P_Sgf[46]), .B0(n1834), .Y(n261) );
OAI21XLTS U2265 ( .A0(n1836), .A1(Sgf_operation_RECURSIVE_EVEN1_Q_left[20]),
.B0(n1835), .Y(n1837) );
AOI22X1TS U2266 ( .A0(n1843), .A1(n1885), .B0(n1837), .B1(n1844), .Y(n259)
);
OAI21XLTS U2267 ( .A0(n1839), .A1(Sgf_operation_RECURSIVE_EVEN1_Q_left[18]),
.B0(n1838), .Y(n1840) );
AOI22X1TS U2268 ( .A0(n1843), .A1(n1886), .B0(n1840), .B1(n1844), .Y(n257)
);
OAI21XLTS U2269 ( .A0(n1848), .A1(Sgf_operation_RECURSIVE_EVEN1_Q_left[16]),
.B0(n1841), .Y(n1842) );
AOI22X1TS U2270 ( .A0(n1843), .A1(n1887), .B0(n1842), .B1(n1844), .Y(n255)
);
OAI21XLTS U2271 ( .A0(n1845), .A1(Sgf_operation_RECURSIVE_EVEN1_Q_left[15]),
.B0(n1844), .Y(n1847) );
OAI2BB2XLTS U2272 ( .B0(n1848), .B1(n1847), .A0N(n1846), .A1N(P_Sgf[39]),
.Y(n254) );
INVX2TS U2273 ( .A(n1849), .Y(n1851) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_noclk.tcl_KOA_2STAGE_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_4_V
`define SKY130_FD_SC_LP__NOR2_4_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_BLACKBOX_V
`define SKY130_FD_SC_LP__DFRTN_BLACKBOX_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_BLACKBOX_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Thu May 15 18:05:39 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/mono_radio/ip/dds/dds_stub.v
// Design : dds
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0,Vivado 2014.1" *)
module dds(aclk, s_axis_phase_tvalid, s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata, m_axis_phase_tvalid, m_axis_phase_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[39:0],m_axis_data_tvalid,m_axis_data_tdata[31:0],m_axis_phase_tvalid,m_axis_phase_tdata[39:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [39:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [31:0]m_axis_data_tdata;
output m_axis_phase_tvalid;
output [39:0]m_axis_phase_tdata;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_2TO1_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_MUX_2TO1_N_BLACKBOX_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_mux_2to1_N (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_2TO1_N_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_2_V
`define SKY130_FD_SC_LS__AND2B_2_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and2b_2 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and2b_2 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:35:06 04/15/2014
// Design Name:
// Module Name: diff_d2e
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module diff_d2e(
clk,clrn,
wreg,m2reg,shift,aluimm,wmem,wzero,aluc,rd,qa,qb,eximme,sa,adepend,bdepend,sdepend,
ewreg,em2reg,eshift,ealuimm,ewmem,ewzero,ealuc,erd,eqa,eqb,eeximme,esa,eadepend,ebdepend,esdepend
);
input clk,clrn;
input wreg,m2reg,shift,aluimm,wmem,wzero;
input [3:0] aluc;
input [4:0] rd,sa;
input[31:0] qa,qb,eximme;
input [1:0] adepend,bdepend,sdepend;
output ewreg,em2reg,eshift,ealuimm,ewmem,ewzero;
output[3:0] ealuc;
output[4:0] erd,esa;
output[31:0] eqa,eqb,eeximme;
output [1:0] eadepend,ebdepend,esdepend;
dff1 push_wreg (wreg,clk,clrn,ewreg);
dff1 push_m2reg (m2reg,clk,clrn,em2reg);
dff1 push_shift (shift,clk,clrn,eshift);
dff1 push_aluimm (aluimm,clk,clrn,ealuimm);
dff1 push_wmem (wmem,clk,clrn,ewmem);
dff1 push_wzero (wzero,clk,clrn,ewzero);
dff4 push_aluc (aluc,clk,clrn,ealuc);
dff5 push_rd (rd,clk,clrn,erd);
dff5 push_sa (sa,clk,clrn,esa);
dff32 push_qa (qa,clk,clrn,eqa);
dff32 push_qb (qb,clk,clrn,eqb);
dff32 push_eximme (eximme,clk,clrn,eeximme);
dff2 push_adepend (adepend,clk,clrn,eadepend);
dff2 push_bdepend (bdepend,clk,clrn,ebdepend);
dff2 push_sdepend (sdepend,clk,clrn,esdepend);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file raycaster_cache_mem.v when simulating
// the core, raycaster_cache_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module raycaster_cache_mem(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [31 : 0] dina;
output reg [31 : 0] douta;
input clkb;
input [0 : 0] web;
input [8 : 0] addrb;
input [31 : 0] dinb;
output reg [31 : 0] doutb;
// synthesis translate_off
reg [31:0] mem[0:511];
// assign douta = mem[addra];
// assign doutb = mem[addrb];
always @(posedge clka)
begin
if (wea)
mem[addra] <= dina;
douta <= mem[addra];
end
always @(posedge clkb)
begin
if (web)
mem[addra] <= dinb;
doutb <= mem[addrb];
end
// BLK_MEM_GEN_V6_2 #(
// .C_ADDRA_WIDTH(9),
// .C_ADDRB_WIDTH(9),
// .C_ALGORITHM(1),
// .C_AXI_ID_WIDTH(4),
// .C_AXI_SLAVE_TYPE(0),
// .C_AXI_TYPE(1),
// .C_BYTE_SIZE(9),
// .C_COMMON_CLK(1),
// .C_DEFAULT_DATA("0"),
// .C_DISABLE_WARN_BHV_COLL(0),
// .C_DISABLE_WARN_BHV_RANGE(0),
// .C_FAMILY("spartan6"),
// .C_HAS_AXI_ID(0),
// .C_HAS_ENA(0),
// .C_HAS_ENB(0),
// .C_HAS_INJECTERR(0),
// .C_HAS_MEM_OUTPUT_REGS_A(1),
// .C_HAS_MEM_OUTPUT_REGS_B(1),
// .C_HAS_MUX_OUTPUT_REGS_A(0),
// .C_HAS_MUX_OUTPUT_REGS_B(0),
// .C_HAS_REGCEA(0),
// .C_HAS_REGCEB(0),
// .C_HAS_RSTA(0),
// .C_HAS_RSTB(0),
// .C_HAS_SOFTECC_INPUT_REGS_A(0),
// .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
// .C_INIT_FILE_NAME("no_coe_file_loaded"),
// .C_INITA_VAL("0"),
// .C_INITB_VAL("0"),
// .C_INTERFACE_TYPE(0),
// .C_LOAD_INIT_FILE(0),
// .C_MEM_TYPE(2),
// .C_MUX_PIPELINE_STAGES(0),
// .C_PRIM_TYPE(1),
// .C_READ_DEPTH_A(512),
// .C_READ_DEPTH_B(512),
// .C_READ_WIDTH_A(32),
// .C_READ_WIDTH_B(32),
// .C_RST_PRIORITY_A("CE"),
// .C_RST_PRIORITY_B("CE"),
// .C_RST_TYPE("SYNC"),
// .C_RSTRAM_A(0),
// .C_RSTRAM_B(0),
// .C_SIM_COLLISION_CHECK("ALL"),
// .C_USE_BYTE_WEA(0),
// .C_USE_BYTE_WEB(0),
// .C_USE_DEFAULT_DATA(0),
// .C_USE_ECC(0),
// .C_USE_SOFTECC(0),
// .C_WEA_WIDTH(1),
// .C_WEB_WIDTH(1),
// .C_WRITE_DEPTH_A(512),
// .C_WRITE_DEPTH_B(512),
// .C_WRITE_MODE_A("WRITE_FIRST"),
// .C_WRITE_MODE_B("WRITE_FIRST"),
// .C_WRITE_WIDTH_A(32),
// .C_WRITE_WIDTH_B(32),
// .C_XDEVICEFAMILY("spartan6")
// )
// inst (
// .CLKA(clka),
// .WEA(wea),
// .ADDRA(addra),
// .DINA(dina),
// .DOUTA(douta),
// .CLKB(clkb),
// .WEB(web),
// .ADDRB(addrb),
// .DINB(dinb),
// .DOUTB(doutb),
// .RSTA(),
// .ENA(),
// .REGCEA(),
// .RSTB(),
// .ENB(),
// .REGCEB(),
// .INJECTSBITERR(),
// .INJECTDBITERR(),
// .SBITERR(),
// .DBITERR(),
// .RDADDRECC(),
// .S_ACLK(),
// .S_ARESETN(),
// .S_AXI_AWID(),
// .S_AXI_AWADDR(),
// .S_AXI_AWLEN(),
// .S_AXI_AWSIZE(),
// .S_AXI_AWBURST(),
// .S_AXI_AWVALID(),
// .S_AXI_AWREADY(),
// .S_AXI_WDATA(),
// .S_AXI_WSTRB(),
// .S_AXI_WLAST(),
// .S_AXI_WVALID(),
// .S_AXI_WREADY(),
// .S_AXI_BID(),
// .S_AXI_BRESP(),
// .S_AXI_BVALID(),
// .S_AXI_BREADY(),
// .S_AXI_ARID(),
// .S_AXI_ARADDR(),
// .S_AXI_ARLEN(),
// .S_AXI_ARSIZE(),
// .S_AXI_ARBURST(),
// .S_AXI_ARVALID(),
// .S_AXI_ARREADY(),
// .S_AXI_RID(),
// .S_AXI_RDATA(),
// .S_AXI_RRESP(),
// .S_AXI_RLAST(),
// .S_AXI_RVALID(),
// .S_AXI_RREADY(),
// .S_AXI_INJECTSBITERR(),
// .S_AXI_INJECTDBITERR(),
// .S_AXI_SBITERR(),
// .S_AXI_DBITERR(),
// .S_AXI_RDADDRECC()
// );
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_SYMBOL_V
`define SKY130_FD_SC_LS__NOR4BB_SYMBOL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_SYMBOL_V
|
`timescale 1ps/1ps
module srio_gen2_0_srio_clk
(// Clock in ports
input sys_clkp,
input sys_clkn,
// Status and control signals
input sys_rst,
input mode_1x,
// Clock out ports
output log_clk,
output phy_clk,
output gt_pcs_clk,
output gt_clk,
output refclk,
output drpclk,
// Status and control signals
output clk_lock
);
//------------------------------------
// wire declarations
//------------------------------------
wire refclk_bufg;
wire clkout0;
wire clkout1;
wire clkout2;
wire clkout3;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire to_feedback_in;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
// End wire declarations
//------------------------------------
// // input buffering
//------------------------------------
IBUFDS_GTE2 u_refclk_ibufds(
.O (refclk),
.I (sys_clkp),
.IB (sys_clkn),
.CEB (1'b0),
.ODIV2 ()
);
BUFG refclk_bufg_inst
(.O (refclk_bufg),
.I (refclk));
// End input buffering
// MMCME2_ADV instantiation
//------------------------------------
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (6.500),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (6.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (26),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (13),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (6.400),
.REF_JITTER1 (0.010))
srio_mmcm_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (refclk_bufg),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (clk_lock),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0)
);
// End 7 series MMCM instantiation
//______________________________________________________________________________
// output buffering
//-----------------------------------
BUFG drpclk_bufr_inst
(.O (drpclk),
.I (clkout1));
BUFG gt_clk_bufg_inst
(.O (gt_clk),
.I (clkout0));
BUFG gt_pcs_clk_bufg_inst
(.O (gt_pcs_clk),
.I (clkout2));
BUFGMUX phy_clk_bufg_inst
(.O (phy_clk),
.I0(clkout2),
.I1(clkout1),
.S (mode_1x));
// Note that this bufg is a duplicate of the gt_pcs_clk bufg, and is not necessary if BUFG resources are limited.
BUFG log_clk_bufg_inst
(.O (log_clk),
.I (clkout2));
// End output buffering
//______________________________________________________________________________
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLXBP_BEHAVIORAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBP_BEHAVIORAL_PP_V |
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