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// fpgaTop_biotite.v - ssiegel 2009-03-17
module fpgaTop(
input wire sys0_clkp, // sys0 Clock +
input wire sys0_clkn, // sys0 Clock -
input wire pci0_clkp, // PCIe Clock +
input wire pci0_clkn, // PCIe Clock -
input wire pci0_rstn, // PCIe Reset
output wire [7:0] pci_exp_txp, // PCIe lanes...
output wire [7:0] pci_exp_txn,
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [2:0] led, // LEDs ml555
input wire ppsExtIn, // PPS in
output wire ppsOut // PPS out
);
// Instance and connect mkFTop...
mkFTop_biotite ftop(
.sys0_clkp (sys0_clkp),
.sys0_clkn (sys0_clkn),
.pci0_clkp (pci0_clkp),
.pci0_clkn (pci0_clkn),
.pci0_rstn (pci0_rstn),
.pcie_rxp_i (pci_exp_rxp),
.pcie_rxn_i (pci_exp_rxn),
.pcie_txp (pci_exp_txp),
.pcie_txn (pci_exp_txn),
.led (led),
.gps_ppsSyncIn_x (ppsExtIn),
.gps_ppsSyncOut (ppsOut)
);
endmodule
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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* UDP ethernet frame receiver (IP frame in, UDP frame out, 64 bit datapath)
*/
module udp_ip_rx_64
(
input wire clk,
input wire rst,
/*
* IP frame input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [63:0] s_ip_payload_axis_tdata,
input wire [7:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* UDP frame output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [63:0] m_udp_payload_axis_tdata,
output wire [7:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire m_udp_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_header_early_termination,
output wire error_payload_early_termination
);
/*
UDP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
source port 2 octets
desination port 2 octets
length 2 octets
checksum 2 octets
payload length octets
This module receives an IP frame with header fields in parallel and payload on
an AXI stream interface, decodes and strips the UDP header fields, then
produces the header fields in parallel along with the UDP payload in a
separate AXI stream.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD = 3'd2,
STATE_READ_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_ip_hdr;
reg store_hdr_word_0;
reg store_last_word;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [63:0] last_word_data_reg = 64'd0;
reg [7:0] last_word_keep_reg = 8'd0;
reg m_udp_hdr_valid_reg = 1'b0, m_udp_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_length_reg = 16'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [7:0] m_ip_protocol_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg [15:0] m_udp_source_port_reg = 16'd0;
reg [15:0] m_udp_dest_port_reg = 16'd0;
reg [15:0] m_udp_length_reg = 16'd0;
reg [15:0] m_udp_checksum_reg = 16'd0;
reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
reg s_ip_payload_axis_tready_reg = 1'b0, s_ip_payload_axis_tready_next;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
// internal datapath
reg [63:0] m_udp_payload_axis_tdata_int;
reg [7:0] m_udp_payload_axis_tkeep_int;
reg m_udp_payload_axis_tvalid_int;
reg m_udp_payload_axis_tready_int_reg = 1'b0;
reg m_udp_payload_axis_tlast_int;
reg m_udp_payload_axis_tuser_int;
wire m_udp_payload_axis_tready_int_early;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
assign s_ip_payload_axis_tready = s_ip_payload_axis_tready_reg;
assign m_udp_hdr_valid = m_udp_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign m_udp_source_port = m_udp_source_port_reg;
assign m_udp_dest_port = m_udp_dest_port_reg;
assign m_udp_length = m_udp_length_reg;
assign m_udp_checksum = m_udp_checksum_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
function [7:0] count2keep;
input [3:0] k;
case (k)
4'd0: count2keep = 8'b00000000;
4'd1: count2keep = 8'b00000001;
4'd2: count2keep = 8'b00000011;
4'd3: count2keep = 8'b00000111;
4'd4: count2keep = 8'b00001111;
4'd5: count2keep = 8'b00011111;
4'd6: count2keep = 8'b00111111;
4'd7: count2keep = 8'b01111111;
4'd8: count2keep = 8'b11111111;
endcase
endfunction
always @* begin
state_next = STATE_IDLE;
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b0;
store_ip_hdr = 1'b0;
store_hdr_word_0 = 1'b0;
store_last_word = 1'b0;
word_count_next = word_count_reg;
m_udp_hdr_valid_next = m_udp_hdr_valid_reg && !m_udp_hdr_ready;
error_header_early_termination_next = 1'b0;
error_payload_early_termination_next = 1'b0;
m_udp_payload_axis_tdata_int = 64'd0;
m_udp_payload_axis_tkeep_int = 8'd0;
m_udp_payload_axis_tvalid_int = 1'b0;
m_udp_payload_axis_tlast_int = 1'b0;
m_udp_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for header
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
if (s_ip_hdr_ready && s_ip_hdr_valid) begin
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b1;
store_ip_hdr = 1'b1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header state
s_ip_payload_axis_tready_next = 1'b1;
word_count_next = {s_ip_payload_axis_tdata[39:32], s_ip_payload_axis_tdata[47:40]} - 16'd8;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
// word transfer in - store it
state_next = STATE_READ_HEADER;
store_hdr_word_0 = 1'b1;
m_udp_hdr_valid_next = 1'b1;
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
state_next = STATE_READ_PAYLOAD;
if (s_ip_payload_axis_tlast) begin
error_header_early_termination_next = 1'b1;
m_udp_hdr_valid_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD: begin
// read payload
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
m_udp_payload_axis_tdata_int = s_ip_payload_axis_tdata;
m_udp_payload_axis_tkeep_int = s_ip_payload_axis_tkeep;
m_udp_payload_axis_tvalid_int = s_ip_payload_axis_tvalid;
m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser;
store_last_word = 1'b1;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd8;
if (word_count_reg <= 8) begin
// have entire payload
m_udp_payload_axis_tkeep_int = s_ip_payload_axis_tkeep & count2keep(word_count_reg);
if (s_ip_payload_axis_tlast) begin
if (keep2count(s_ip_payload_axis_tkeep) < word_count_reg[4:0]) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_udp_payload_axis_tuser_int = 1'b1;
end
s_ip_payload_axis_tready_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
m_udp_payload_axis_tvalid_int = 1'b0;
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
if (s_ip_payload_axis_tlast) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_udp_payload_axis_tuser_int = 1'b1;
s_ip_payload_axis_tready_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
STATE_READ_PAYLOAD_LAST: begin
// read and discard until end of frame
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
m_udp_payload_axis_tdata_int = last_word_data_reg;
m_udp_payload_axis_tkeep_int = last_word_keep_reg;
m_udp_payload_axis_tvalid_int = s_ip_payload_axis_tvalid && s_ip_payload_axis_tlast;
m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
s_ip_payload_axis_tready_next = 1'b1;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_ip_hdr_ready_reg <= 1'b0;
s_ip_payload_axis_tready_reg <= 1'b0;
m_udp_hdr_valid_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
s_ip_payload_axis_tready_reg <= s_ip_payload_axis_tready_next;
m_udp_hdr_valid_reg <= m_udp_hdr_valid_next;
error_header_early_termination_reg <= error_header_early_termination_next;
error_payload_early_termination_reg <= error_payload_early_termination_next;
busy_reg <= state_next != STATE_IDLE;
end
word_count_reg <= word_count_next;
// datapath
if (store_ip_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
m_ip_version_reg <= s_ip_version;
m_ip_ihl_reg <= s_ip_ihl;
m_ip_dscp_reg <= s_ip_dscp;
m_ip_ecn_reg <= s_ip_ecn;
m_ip_length_reg <= s_ip_length;
m_ip_identification_reg <= s_ip_identification;
m_ip_flags_reg <= s_ip_flags;
m_ip_fragment_offset_reg <= s_ip_fragment_offset;
m_ip_ttl_reg <= s_ip_ttl;
m_ip_protocol_reg <= s_ip_protocol;
m_ip_header_checksum_reg <= s_ip_header_checksum;
m_ip_source_ip_reg <= s_ip_source_ip;
m_ip_dest_ip_reg <= s_ip_dest_ip;
end
if (store_last_word) begin
last_word_data_reg <= m_udp_payload_axis_tdata_int;
last_word_keep_reg <= m_udp_payload_axis_tkeep_int;
end
if (store_hdr_word_0) begin
m_udp_source_port_reg[15: 8] <= s_ip_payload_axis_tdata[ 7: 0];
m_udp_source_port_reg[ 7: 0] <= s_ip_payload_axis_tdata[15: 8];
m_udp_dest_port_reg[15: 8] <= s_ip_payload_axis_tdata[23:16];
m_udp_dest_port_reg[ 7: 0] <= s_ip_payload_axis_tdata[31:24];
m_udp_length_reg[15: 8] <= s_ip_payload_axis_tdata[39:32];
m_udp_length_reg[ 7: 0] <= s_ip_payload_axis_tdata[47:40];
m_udp_checksum_reg[15: 8] <= s_ip_payload_axis_tdata[55:48];
m_udp_checksum_reg[ 7: 0] <= s_ip_payload_axis_tdata[63:56];
end
end
// output datapath logic
reg [63:0] m_udp_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_udp_payload_axis_tkeep_reg = 8'd0;
reg m_udp_payload_axis_tvalid_reg = 1'b0, m_udp_payload_axis_tvalid_next;
reg m_udp_payload_axis_tlast_reg = 1'b0;
reg m_udp_payload_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_udp_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_udp_payload_axis_tkeep_reg = 8'd0;
reg temp_m_udp_payload_axis_tvalid_reg = 1'b0, temp_m_udp_payload_axis_tvalid_next;
reg temp_m_udp_payload_axis_tlast_reg = 1'b0;
reg temp_m_udp_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_udp_payload_int_to_output;
reg store_udp_payload_int_to_temp;
reg store_udp_payload_axis_temp_to_output;
assign m_udp_payload_axis_tdata = m_udp_payload_axis_tdata_reg;
assign m_udp_payload_axis_tkeep = m_udp_payload_axis_tkeep_reg;
assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
assign m_udp_payload_axis_tuser = m_udp_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
store_udp_payload_int_to_output = 1'b0;
store_udp_payload_int_to_temp = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b0;
if (m_udp_payload_axis_tready_int_reg) begin
// input is ready
if (m_udp_payload_axis_tready || !m_udp_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_udp_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_udp_payload_int_to_temp = 1'b1;
end
end else if (m_udp_payload_axis_tready) begin
// input is not ready, but output is ready
m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_udp_payload_axis_tvalid_reg <= 1'b0;
m_udp_payload_axis_tready_int_reg <= 1'b0;
temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
end
// datapath
if (store_udp_payload_int_to_output) begin
m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end else if (store_udp_payload_axis_temp_to_output) begin
m_udp_payload_axis_tdata_reg <= temp_m_udp_payload_axis_tdata_reg;
m_udp_payload_axis_tkeep_reg <= temp_m_udp_payload_axis_tkeep_reg;
m_udp_payload_axis_tlast_reg <= temp_m_udp_payload_axis_tlast_reg;
m_udp_payload_axis_tuser_reg <= temp_m_udp_payload_axis_tuser_reg;
end
if (store_udp_payload_int_to_temp) begin
temp_m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
temp_m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
temp_m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:39:12 09/13/2014
// Design Name: timer32
// Module Name: C:/ece4743/projects/lab6_solution/tb_timer32.v
// Project Name: lab6_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: timer32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_timer32;
// Inputs
reg clk;
reg reset;
reg [31:0] din;
reg wren;
reg rden;
reg [1:0] addr;
// Outputs
wire [31:0] dout;
`define PERIOD_INITIAL 32'h0000000F
`define TMR_REG 2'b00
`define PER_REG 2'b01
`define CON_REG 2'b10
// Instantiate the Unit Under Test (UUT)
timer32 #(.PERIOD(`PERIOD_INITIAL),.ENBIT(0)) uut (
.clk(clk),
.reset(reset),
.din(din),
.dout(dout),
.wren(wren),
.rden(rden),
.addr(addr)
);
initial begin
clk = 0;
#100 //reset delay
forever #20 clk = ~clk;
end
integer errors;
initial begin
// Initialize Inputs
#1
clk = 0;
reset = 1;
din = 0;
wren = 0;
rden = 0;
addr = 0;
errors = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
@(negedge clk);
rden = 1;
addr = `TMR_REG;
@(negedge clk);
//read Timer register
if (dout != 0) begin
$display("(%t)FAIL: Timer not reset to zero\n",$time());
errors = errors + 1;
end
addr = `PER_REG;
@(negedge clk);
//read Period register
if (dout != `PERIOD_INITIAL) begin
$display("(%t)FAIL: Period register not reset to initial parameter value\n",$time());
errors = errors + 1;
end
addr = `CON_REG;
@(negedge clk);
//read Control register
if (dout != 0) begin
$display("(%t)FAIL: Control register not reset to zero\n",$time());
errors = errors + 1;
end
addr = `PER_REG;
din = 32'h00000007;
wren = 1;
@(negedge clk); //write
//write Period register, read result
if (dout != 32'h00000007) begin
$display("(%t)FAIL: Period register write failed\n",$time());
errors = errors + 1;
end
//enable the timer, write a '1' to the EN bit
wren = 1;
addr = `CON_REG;
din = 1;
@(negedge clk);
wren = 0;
addr = `TMR_REG;
@(negedge clk);
//timer should have incremented
if (dout != 1) begin
$display("(%t)FAIL: Timer failed to increment\n",$time());
errors = errors + 1;
end
@(negedge clk);
//timer should have incremented
if (dout != 2) begin
$display("(%t)FAIL: Timer failed to increment\n",$time());
errors = errors + 1;
end
@(negedge clk); //timer=3
@(negedge clk); //timer=4
@(negedge clk); //timer=5
@(negedge clk); //timer=6
@(negedge clk); //timer=7
//period register should cause the timer to reset
@(negedge clk); //timer=0
if (dout != 0) begin
$display("(%t)FAIL: Timer (%d) failed to be reset by period register\n",$time(),din);
errors = errors + 1;
end
@(posedge clk); //timer =1
//read the control register, all three bits should be set!
//change addres after posedge so can read register output on negedge
addr = `CON_REG;
@(negedge clk); //timer=1
if (dout != 7) begin
$display("(%t)FAIL: Expected Control register value of 7, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=2
//read again, the timer flag bit should be cleared because of previous reead
if (dout != 5) begin
$display("(%t)FAIL: Expected Control register value of 5, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=3
addr = `CON_REG;
wren = 1;
din = 4; //disable the timer, keep the toggle bit as '1' ('b100)
//We are clearing the TMR enable bit to freeze the timer value
@(negedge clk); //timer=4, but should no longer increment
addr = `TMR_REG;
wren = 0;
//cannot check DOUT here as we have just changed the address bus
@(negedge clk); //timer=4
//Timer should be frozen at 4
if (dout != 4) begin
$display("(%t)FAIL: Expected Timer register value of 4, got (%d)\n",$time(),din);
errors = errors + 1;
end
//lets renable the timer
@(negedge clk); //timer=4
//Timer should be frozen at 4
addr = `CON_REG;
wren = 1;
din = 5; //enable the timer, keep the toggle bit as '1' ('b100)
@(negedge clk); //timer=4
addr = `TMR_REG;
wren = 0;
//Timer is 4, but should start counting again
@(negedge clk); //timer=5
if (dout != 5) begin
$display("(%t)FAIL: Expected Timer register value of 5, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=6
if (dout != 6) begin
$display("(%t)FAIL: Expected Timer register value of 6, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=7
if (dout != 7) begin
$display("(%t)FAIL: Expected Timer register value of 7, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=0
if (dout != 0) begin
$display("(%t)FAIL: Expected Timer register value of 0, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=1
@(posedge clk); //timer = 2
//change address right after pos edge so have time read at neg edge
addr = `CON_REG; //read the control register
@(negedge clk); //timer=2
//the toggle bit should cleared, the TMR Flag, enable bits should be set
if (dout != 3) begin
$display("(%t)FAIL: Expected Control register value of 3, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=3
//the toggle bit, TMR flag bits should cleared,the enable bits should be set
if (dout != 1) begin
$display("(%t)FAIL: Expected Control register value of 1, got (%d)\n",$time(),din);
errors = errors + 1;
end
if (errors == 0) begin
$display("(%t)PASSED: All vectors passed\n",$time());
end else begin
$display("(%t)FAILED: %d vectors failed\n",$time(),errors);
end
end
endmodule
|
// ctorng 2-23-17
//
// Synchronous 1-port ram with bit masking
// Only one read or one write may be done per cycle.
//
// Ports for tsmc16_1rw and tsmc16_1rf
//
// CLK // in
// Q // out
// CEN // lo true
// WEN // lo true
// GWEN // lo true
// A // in
// D // in
// STOV // Self-timing Override - disabled
// EMA // Extra Margin Adjustment - default value
// EMAW // Extra Margin Adjustment Write - default value
// EMAS // Extra Margin Adjustment Sense Amp. - default value
// RET1N // Retention Mode (active low) - disabled
`define bsg_mem_1rw_sync_mask_write_bit_macro(words,bits,lgEls) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc16_1rw_lg``lgEls``_w``bits``_bit mem \
(.CLK (clk_i ) \
,.Q (data_o) \
,.CEN (~v_i ) \
,.WEN (~w_mask_i) \
,.GWEN (~w_i ) \
,.A (addr_i) \
,.D (data_i) \
,.STOV (1'd0 ) \
,.EMA (3'd3 ) \
,.EMAW (2'd1 ) \
,.EMAS (1'd0 ) \
,.RET1N (1'b1 ) \
); \
end // block: macro
`define bsg_mem_1rw_sync_mask_write_bit_macro_rf(words,bits,lgEls) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc16_1rf_lg``lgEls``_w``bits``_bit mem \
(.Q (data_o) \
,.CLK (clk_i ) \
,.CEN (~v_i ) \
,.WEN (~w_mask_i) \
,.GWEN (~w_i ) \
,.A (addr_i) \
,.D (data_i) \
,.STOV (1'd0 ) \
,.EMA (3'd3 ) \
,.EMAW (2'd1 ) \
,.EMAS (1'd0 ) \
,.RET1N (1'b1 ) \
); \
end // block: macro
module bsg_mem_1rw_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p))
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input [width_p-1:0] w_mask_i
, input w_i
, output [width_p-1:0] data_o
);
`bsg_mem_1rw_sync_mask_write_bit_macro_rf(64,80,6) else
bsg_mem_1rw_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p(els_p)
) synth
(.*);
// synopsys translate_off
always_ff @(posedge clk_i)
if (v_i)
assert (addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", addr_i, els_p);
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit)
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:18:26 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_debounce_0_0/system_debounce_0_0_sim_netlist.v
// Design : system_debounce_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_debounce_0_0,debounce,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "debounce,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_debounce_0_0
(clk,
signal_in,
signal_out);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input signal_in;
output signal_out;
wire clk;
wire signal_in;
wire signal_out;
system_debounce_0_0_debounce U0
(.clk(clk),
.signal_in(signal_in),
.signal_out(signal_out));
endmodule
(* ORIG_REF_NAME = "debounce" *)
module system_debounce_0_0_debounce
(signal_out,
clk,
signal_in);
output signal_out;
input clk;
input signal_in;
wire \c[0]_i_3_n_0 ;
wire \c[0]_i_4_n_0 ;
wire \c[0]_i_5_n_0 ;
wire \c[0]_i_6_n_0 ;
wire \c[12]_i_2_n_0 ;
wire \c[12]_i_3_n_0 ;
wire \c[12]_i_4_n_0 ;
wire \c[12]_i_5_n_0 ;
wire \c[16]_i_2_n_0 ;
wire \c[16]_i_3_n_0 ;
wire \c[16]_i_4_n_0 ;
wire \c[16]_i_5_n_0 ;
wire \c[20]_i_2_n_0 ;
wire \c[20]_i_3_n_0 ;
wire \c[20]_i_4_n_0 ;
wire \c[20]_i_5_n_0 ;
wire \c[4]_i_2_n_0 ;
wire \c[4]_i_3_n_0 ;
wire \c[4]_i_4_n_0 ;
wire \c[4]_i_5_n_0 ;
wire \c[8]_i_2_n_0 ;
wire \c[8]_i_3_n_0 ;
wire \c[8]_i_4_n_0 ;
wire \c[8]_i_5_n_0 ;
wire [23:0]c_reg;
wire \c_reg[0]_i_2_n_0 ;
wire \c_reg[0]_i_2_n_1 ;
wire \c_reg[0]_i_2_n_2 ;
wire \c_reg[0]_i_2_n_3 ;
wire \c_reg[0]_i_2_n_4 ;
wire \c_reg[0]_i_2_n_5 ;
wire \c_reg[0]_i_2_n_6 ;
wire \c_reg[0]_i_2_n_7 ;
wire \c_reg[12]_i_1_n_0 ;
wire \c_reg[12]_i_1_n_1 ;
wire \c_reg[12]_i_1_n_2 ;
wire \c_reg[12]_i_1_n_3 ;
wire \c_reg[12]_i_1_n_4 ;
wire \c_reg[12]_i_1_n_5 ;
wire \c_reg[12]_i_1_n_6 ;
wire \c_reg[12]_i_1_n_7 ;
wire \c_reg[16]_i_1_n_0 ;
wire \c_reg[16]_i_1_n_1 ;
wire \c_reg[16]_i_1_n_2 ;
wire \c_reg[16]_i_1_n_3 ;
wire \c_reg[16]_i_1_n_4 ;
wire \c_reg[16]_i_1_n_5 ;
wire \c_reg[16]_i_1_n_6 ;
wire \c_reg[16]_i_1_n_7 ;
wire \c_reg[20]_i_1_n_1 ;
wire \c_reg[20]_i_1_n_2 ;
wire \c_reg[20]_i_1_n_3 ;
wire \c_reg[20]_i_1_n_4 ;
wire \c_reg[20]_i_1_n_5 ;
wire \c_reg[20]_i_1_n_6 ;
wire \c_reg[20]_i_1_n_7 ;
wire \c_reg[4]_i_1_n_0 ;
wire \c_reg[4]_i_1_n_1 ;
wire \c_reg[4]_i_1_n_2 ;
wire \c_reg[4]_i_1_n_3 ;
wire \c_reg[4]_i_1_n_4 ;
wire \c_reg[4]_i_1_n_5 ;
wire \c_reg[4]_i_1_n_6 ;
wire \c_reg[4]_i_1_n_7 ;
wire \c_reg[8]_i_1_n_0 ;
wire \c_reg[8]_i_1_n_1 ;
wire \c_reg[8]_i_1_n_2 ;
wire \c_reg[8]_i_1_n_3 ;
wire \c_reg[8]_i_1_n_4 ;
wire \c_reg[8]_i_1_n_5 ;
wire \c_reg[8]_i_1_n_6 ;
wire \c_reg[8]_i_1_n_7 ;
wire clear;
wire clk;
wire signal_in;
wire signal_out;
wire signal_out_i_1_n_0;
wire signal_out_i_2_n_0;
wire signal_out_i_3_n_0;
wire signal_out_i_4_n_0;
wire signal_out_i_5_n_0;
wire [3:3]\NLW_c_reg[20]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\c[0]_i_1
(.I0(signal_in),
.O(clear));
LUT1 #(
.INIT(2'h2))
\c[0]_i_3
(.I0(c_reg[3]),
.O(\c[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[0]_i_4
(.I0(c_reg[2]),
.O(\c[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[0]_i_5
(.I0(c_reg[1]),
.O(\c[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\c[0]_i_6
(.I0(c_reg[0]),
.O(\c[0]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_2
(.I0(c_reg[15]),
.O(\c[12]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_3
(.I0(c_reg[14]),
.O(\c[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_4
(.I0(c_reg[13]),
.O(\c[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_5
(.I0(c_reg[12]),
.O(\c[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_2
(.I0(c_reg[19]),
.O(\c[16]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_3
(.I0(c_reg[18]),
.O(\c[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_4
(.I0(c_reg[17]),
.O(\c[16]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_5
(.I0(c_reg[16]),
.O(\c[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_2
(.I0(c_reg[23]),
.O(\c[20]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_3
(.I0(c_reg[22]),
.O(\c[20]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_4
(.I0(c_reg[21]),
.O(\c[20]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_5
(.I0(c_reg[20]),
.O(\c[20]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_2
(.I0(c_reg[7]),
.O(\c[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_3
(.I0(c_reg[6]),
.O(\c[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_4
(.I0(c_reg[5]),
.O(\c[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_5
(.I0(c_reg[4]),
.O(\c[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_2
(.I0(c_reg[11]),
.O(\c[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_3
(.I0(c_reg[10]),
.O(\c[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_4
(.I0(c_reg[9]),
.O(\c[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_5
(.I0(c_reg[8]),
.O(\c[8]_i_5_n_0 ));
FDRE \c_reg[0]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_7 ),
.Q(c_reg[0]),
.R(clear));
CARRY4 \c_reg[0]_i_2
(.CI(1'b0),
.CO({\c_reg[0]_i_2_n_0 ,\c_reg[0]_i_2_n_1 ,\c_reg[0]_i_2_n_2 ,\c_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\c_reg[0]_i_2_n_4 ,\c_reg[0]_i_2_n_5 ,\c_reg[0]_i_2_n_6 ,\c_reg[0]_i_2_n_7 }),
.S({\c[0]_i_3_n_0 ,\c[0]_i_4_n_0 ,\c[0]_i_5_n_0 ,\c[0]_i_6_n_0 }));
FDRE \c_reg[10]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_5 ),
.Q(c_reg[10]),
.R(clear));
FDRE \c_reg[11]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_4 ),
.Q(c_reg[11]),
.R(clear));
FDRE \c_reg[12]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_7 ),
.Q(c_reg[12]),
.R(clear));
CARRY4 \c_reg[12]_i_1
(.CI(\c_reg[8]_i_1_n_0 ),
.CO({\c_reg[12]_i_1_n_0 ,\c_reg[12]_i_1_n_1 ,\c_reg[12]_i_1_n_2 ,\c_reg[12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[12]_i_1_n_4 ,\c_reg[12]_i_1_n_5 ,\c_reg[12]_i_1_n_6 ,\c_reg[12]_i_1_n_7 }),
.S({\c[12]_i_2_n_0 ,\c[12]_i_3_n_0 ,\c[12]_i_4_n_0 ,\c[12]_i_5_n_0 }));
FDRE \c_reg[13]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_6 ),
.Q(c_reg[13]),
.R(clear));
FDRE \c_reg[14]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_5 ),
.Q(c_reg[14]),
.R(clear));
FDRE \c_reg[15]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_4 ),
.Q(c_reg[15]),
.R(clear));
FDRE \c_reg[16]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_7 ),
.Q(c_reg[16]),
.R(clear));
CARRY4 \c_reg[16]_i_1
(.CI(\c_reg[12]_i_1_n_0 ),
.CO({\c_reg[16]_i_1_n_0 ,\c_reg[16]_i_1_n_1 ,\c_reg[16]_i_1_n_2 ,\c_reg[16]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[16]_i_1_n_4 ,\c_reg[16]_i_1_n_5 ,\c_reg[16]_i_1_n_6 ,\c_reg[16]_i_1_n_7 }),
.S({\c[16]_i_2_n_0 ,\c[16]_i_3_n_0 ,\c[16]_i_4_n_0 ,\c[16]_i_5_n_0 }));
FDRE \c_reg[17]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_6 ),
.Q(c_reg[17]),
.R(clear));
FDRE \c_reg[18]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_5 ),
.Q(c_reg[18]),
.R(clear));
FDRE \c_reg[19]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_4 ),
.Q(c_reg[19]),
.R(clear));
FDRE \c_reg[1]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_6 ),
.Q(c_reg[1]),
.R(clear));
FDRE \c_reg[20]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_7 ),
.Q(c_reg[20]),
.R(clear));
CARRY4 \c_reg[20]_i_1
(.CI(\c_reg[16]_i_1_n_0 ),
.CO({\NLW_c_reg[20]_i_1_CO_UNCONNECTED [3],\c_reg[20]_i_1_n_1 ,\c_reg[20]_i_1_n_2 ,\c_reg[20]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[20]_i_1_n_4 ,\c_reg[20]_i_1_n_5 ,\c_reg[20]_i_1_n_6 ,\c_reg[20]_i_1_n_7 }),
.S({\c[20]_i_2_n_0 ,\c[20]_i_3_n_0 ,\c[20]_i_4_n_0 ,\c[20]_i_5_n_0 }));
FDRE \c_reg[21]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_6 ),
.Q(c_reg[21]),
.R(clear));
FDRE \c_reg[22]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_5 ),
.Q(c_reg[22]),
.R(clear));
FDRE \c_reg[23]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_4 ),
.Q(c_reg[23]),
.R(clear));
FDRE \c_reg[2]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_5 ),
.Q(c_reg[2]),
.R(clear));
FDRE \c_reg[3]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_4 ),
.Q(c_reg[3]),
.R(clear));
FDRE \c_reg[4]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_7 ),
.Q(c_reg[4]),
.R(clear));
CARRY4 \c_reg[4]_i_1
(.CI(\c_reg[0]_i_2_n_0 ),
.CO({\c_reg[4]_i_1_n_0 ,\c_reg[4]_i_1_n_1 ,\c_reg[4]_i_1_n_2 ,\c_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[4]_i_1_n_4 ,\c_reg[4]_i_1_n_5 ,\c_reg[4]_i_1_n_6 ,\c_reg[4]_i_1_n_7 }),
.S({\c[4]_i_2_n_0 ,\c[4]_i_3_n_0 ,\c[4]_i_4_n_0 ,\c[4]_i_5_n_0 }));
FDRE \c_reg[5]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_6 ),
.Q(c_reg[5]),
.R(clear));
FDRE \c_reg[6]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_5 ),
.Q(c_reg[6]),
.R(clear));
FDRE \c_reg[7]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_4 ),
.Q(c_reg[7]),
.R(clear));
FDRE \c_reg[8]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_7 ),
.Q(c_reg[8]),
.R(clear));
CARRY4 \c_reg[8]_i_1
(.CI(\c_reg[4]_i_1_n_0 ),
.CO({\c_reg[8]_i_1_n_0 ,\c_reg[8]_i_1_n_1 ,\c_reg[8]_i_1_n_2 ,\c_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[8]_i_1_n_4 ,\c_reg[8]_i_1_n_5 ,\c_reg[8]_i_1_n_6 ,\c_reg[8]_i_1_n_7 }),
.S({\c[8]_i_2_n_0 ,\c[8]_i_3_n_0 ,\c[8]_i_4_n_0 ,\c[8]_i_5_n_0 }));
FDRE \c_reg[9]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_6 ),
.Q(c_reg[9]),
.R(clear));
LUT5 #(
.INIT(32'h80000000))
signal_out_i_1
(.I0(signal_out_i_2_n_0),
.I1(signal_out_i_3_n_0),
.I2(signal_out_i_4_n_0),
.I3(c_reg[0]),
.I4(signal_out_i_5_n_0),
.O(signal_out_i_1_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_2
(.I0(c_reg[3]),
.I1(c_reg[4]),
.I2(c_reg[1]),
.I3(c_reg[2]),
.I4(c_reg[6]),
.I5(c_reg[5]),
.O(signal_out_i_2_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_3
(.I0(c_reg[21]),
.I1(c_reg[22]),
.I2(c_reg[19]),
.I3(c_reg[20]),
.I4(signal_in),
.I5(c_reg[23]),
.O(signal_out_i_3_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_4
(.I0(c_reg[15]),
.I1(c_reg[16]),
.I2(c_reg[13]),
.I3(c_reg[14]),
.I4(c_reg[18]),
.I5(c_reg[17]),
.O(signal_out_i_4_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_5
(.I0(c_reg[9]),
.I1(c_reg[10]),
.I2(c_reg[7]),
.I3(c_reg[8]),
.I4(c_reg[12]),
.I5(c_reg[11]),
.O(signal_out_i_5_n_0));
FDRE signal_out_reg
(.C(clk),
.CE(1'b1),
.D(signal_out_i_1_n_0),
.Q(signal_out),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*****************************************************************************/
//
// Module : bbox_box_top.vpp
// Revision : $Revision: 1.8 $
// Last Modified On: $Date: 2012/01/12 21:08:40 $
// Last Modified By: $Author: dwalker $
//
//-----------------------------------------------------------------------------
//
// Original Author :
// Created On : Mon Feb 13 13:06:02 2012
//
//-----------------------------------------------------------------------------
//
// Description : top level interface of black box
//
//-----------------------------------------------------------------------------
//
// Copyright (c) 2012 : created by Convey Computer Corp. This model is the
// confidential and proprietary property of Convey Computer Corp.
//
/*****************************************************************************/
/* $Id: verilog-mode.el,v 1.8 2012/01/12 21:08:40 dwalker Exp $ */
`timescale 1 ns / 1 ps
// leda B_3413 off Task call in a combinational block
// leda VER_2_1_2_4 off Task should not be used
// leda W484 off Possible loss of carry/borrow in addition/subtraction
module bbox_box_top (/*AUTOARG*/
// Outputs
o_result, o_vm, o_done, o_hit, o_error,
// Inputs
clk2x, clk1x, clkhx, bb_clk1x, bb_clk2x, i_reset, i_start,
i_scalar, i_elemCnt, i_arc0, i_arc1, i_arc2, i_arc3, i_vrA, i_vrB
) ;
`include "bbox_user.vh"
/* ---------- port declarations ---------- */
// clk2x is used for all other inputs and outputs
input clk2x; // 300Mhz input clock,
input clk1x; // 150Mhz input clock synchronous with clk2x
input clkhx; // 75Mhz input clock, synchronous with clk2x
input bb_clk1x; // dedicated BB clock that is asynchronous with clk1x
// bb_clk1x is 1/2 the frequency of bb_clk2x
input bb_clk2x; // dedicated BB clock that is asynchronous with clk1x
// bb_clk2x is 2x the frequency of bb_clk1x
/*********** all following inputs/outputs are clocked by clk2x *******/
input i_reset; // input reset signal, asserted immediatly
// after the personality is loaded into the FPGA
/*********** input control signals (valid when start is asserted) *******/
input i_start; // a black box instruction is starting this cycle
input [63:0] i_scalar; // 64 bit value from the instruction
input [8:0] i_elemCnt;// number of elements to be processed for the
// coincident start signal
input [BBUSER_ARC0MSB:0] i_arc0; // control of BBox
// i_arc0[0] - single instruction op
// i_arc0[1] - start a LD op to Unit#0 AMS
// i_arc0[2] - start a BB op from Unit#0 AMS
// i_arc0[3] - start a ST op from Unit#0 AMS
// i_arc0[4] - start a LD op to Unit#1 AMS
// i_arc0[5] - start a BB op from Unit#1 AMS
// i_arc0[6] - start a ST op from Unit#1 AMS
// i_arc0[7+] - user defined
input [BBUSER_ARC1MSB:0] i_arc1; // 1 to 64 bits of user control for BBox
input [BBUSER_ARC2MSB:0] i_arc2; // 1 to 64 bits of user control for BBox
input [BBUSER_ARC3MSB:0] i_arc3; // 1 to 64 bits of user control for BBox
/******** input data elements (valid for elemCnt cycles starting coincident with i_start ****/
input [63:0] i_vrA;
input [63:0] i_vrB;
/******** output data elements (valid for elemCnt cycles ****/
output [63:0] o_result; // data results (valid for elemCnt cycles,
// starting BBUSER_PIPE_LEN cycles after start
output o_vm; // current element was a match,
// this signal gets written to VMt if specified by the instruction
// coincident with o_Result
/******** current multi-stage operation is done ****/
output o_done; // done with current operation in x? cycles,
// used in multi-stage mode
/******** these 2 signals are sent back to the controller to cause an exception *******/
output o_hit; // black box found something it was looking for, pull an exception
output o_error; // the BB has detected some sort of internal error, pull an exception
/* ---------- include files ---------- */
/* ---------- wires & regs ---------- */
reg r_reset;
reg r_t1_start;
reg [63:0] r_t1_scalar, r_t2_scalar;
reg [8:0] r_t1_elemCnt;
reg [BBUSER_ARC0MSB:0] r_t1_arc0;
reg [BBUSER_ARC0MSB:0] r_t2_arc0;
reg [BBUSER_ARC1MSB:0] r_t1_arc1;// not needed if no bits in arc1 are defined
reg [BBUSER_ARC2MSB:0] r_t1_arc2;// not needed if no bits in arc2 are defined
reg [BBUSER_ARC3MSB:0] r_t1_arc3;// not needed if no bits in arc3 are defined
reg [63:0] r_t1_vrA, r_t1_vrB;
reg [63:0] r_t2_vrA, r_t2_vrB;
wire [8:0] c_t1_cnt;
reg [8:0] r_t2_cnt;
wire c_t1_active;
reg r_t2_active;
reg r_t3_active;
reg r_t4_active;
wire c_t1_done;
reg r_t2_done;
wire [63:0] c_t2_inA;
reg [63:0] c_t2_inB, r_t3_inA, r_t3_inB;
reg [5:0] r_t4_posr, r_t4_posl;
reg [11:0] r_t5_wordr, r_t5_wordl;
reg [63:0] r_t6_datas;
reg r_t3_BBop;
reg r_t4_BBop;
reg r_t5_BBop;
/* ---------- centrifuge wires and regs ---------- */
reg [63:0] r_t4_inA, r_t4_inB;
reg [63:0] r_t7_datas, c_t6_datasr, c_t6_datasl;
// spin right
reg [3:0] r_t4_balr, c_t3_balr;
reg [3:0] r_t4_mixedr, c_t3_mixedr;
reg [11:0] r_t5_datar, c_t4_datar;
reg [11:0] r_t6_wordr;
reg [7:0] r_t6_byter;
reg r_t6_BBop;
reg [5:0] r_t5_posr, c_t4_posr, r_t6_posr_d;
reg c_t4_pos_ovr;
reg r_t5_bwer, r_t6_bwer_d;
// spin left
reg [3:0] r_t4_ball, c_t3_ball;
reg [3:0] r_t4_mixedl, c_t3_mixedl;
reg [11:0] r_t5_datal, c_t4_datal;
reg [11:0] r_t6_wordl;
reg [7:0] r_t6_bytel;
reg [5:0] r_t5_posl, c_t4_posl, r_t6_posl_d;
reg c_t4_pos_ovl;
reg r_t5_bwel, r_t6_bwel_d;
reg [63:0] r_t5_inA, r_t5_inB;
reg [63:0] r_t8_datas, c_t7_datasr, c_t7_datasl;
// spin right
reg [3:0] r_t5_balr, c_t4_balr;
reg [3:0] r_t5_mixedr, c_t4_mixedr;
reg [11:0] r_t6_datar, c_t5_datar;
reg [11:0] r_t7_wordr;
reg [7:0] r_t7_byter;
reg r_t7_BBop;
reg [5:0] r_t6_posr, c_t5_posr, r_t7_posr_d;
reg c_t5_pos_ovr;
reg r_t6_bwer, r_t7_bwer_d;
// spin left
reg [3:0] r_t5_ball, c_t4_ball;
reg [3:0] r_t5_mixedl, c_t4_mixedl;
reg [11:0] r_t6_datal, c_t5_datal;
reg [11:0] r_t7_wordl;
reg [7:0] r_t7_bytel;
reg [5:0] r_t6_posl, c_t5_posl, r_t7_posl_d;
reg c_t5_pos_ovl;
reg r_t6_bwel, r_t7_bwel_d;
reg [63:0] r_t6_inA, r_t6_inB;
reg [63:0] r_t9_datas, c_t8_datasr, c_t8_datasl;
// spin right
reg [3:0] r_t6_balr, c_t5_balr;
reg [3:0] r_t6_mixedr, c_t5_mixedr;
reg [11:0] r_t7_datar, c_t6_datar;
reg [11:0] r_t8_wordr;
reg [7:0] r_t8_byter;
reg r_t8_BBop;
reg [5:0] r_t7_posr, c_t6_posr, r_t8_posr_d;
reg c_t6_pos_ovr;
reg r_t7_bwer, r_t8_bwer_d;
// spin left
reg [3:0] r_t6_ball, c_t5_ball;
reg [3:0] r_t6_mixedl, c_t5_mixedl;
reg [11:0] r_t7_datal, c_t6_datal;
reg [11:0] r_t8_wordl;
reg [7:0] r_t8_bytel;
reg [5:0] r_t7_posl, c_t6_posl, r_t8_posl_d;
reg c_t6_pos_ovl;
reg r_t7_bwel, r_t8_bwel_d;
reg [63:0] r_t7_inA, r_t7_inB;
reg [63:0] r_t10_datas, c_t9_datasr, c_t9_datasl;
// spin right
reg [3:0] r_t7_balr, c_t6_balr;
reg [3:0] r_t7_mixedr, c_t6_mixedr;
reg [11:0] r_t8_datar, c_t7_datar;
reg [11:0] r_t9_wordr;
reg [7:0] r_t9_byter;
reg r_t9_BBop;
reg [5:0] r_t8_posr, c_t7_posr, r_t9_posr_d;
reg c_t7_pos_ovr;
reg r_t8_bwer, r_t9_bwer_d;
// spin left
reg [3:0] r_t7_ball, c_t6_ball;
reg [3:0] r_t7_mixedl, c_t6_mixedl;
reg [11:0] r_t8_datal, c_t7_datal;
reg [11:0] r_t9_wordl;
reg [7:0] r_t9_bytel;
reg [5:0] r_t8_posl, c_t7_posl, r_t9_posl_d;
reg c_t7_pos_ovl;
reg r_t8_bwel, r_t9_bwel_d;
reg [63:0] r_t8_inA, r_t8_inB;
reg [63:0] r_t11_datas, c_t10_datasr, c_t10_datasl;
// spin right
reg [3:0] r_t8_balr, c_t7_balr;
reg [3:0] r_t8_mixedr, c_t7_mixedr;
reg [11:0] r_t9_datar, c_t8_datar;
reg [11:0] r_t10_wordr;
reg [7:0] r_t10_byter;
reg r_t10_BBop;
reg [5:0] r_t9_posr, c_t8_posr, r_t10_posr_d;
reg c_t8_pos_ovr;
reg r_t9_bwer, r_t10_bwer_d;
// spin left
reg [3:0] r_t8_ball, c_t7_ball;
reg [3:0] r_t8_mixedl, c_t7_mixedl;
reg [11:0] r_t9_datal, c_t8_datal;
reg [11:0] r_t10_wordl;
reg [7:0] r_t10_bytel;
reg [5:0] r_t9_posl, c_t8_posl, r_t10_posl_d;
reg c_t8_pos_ovl;
reg r_t9_bwel, r_t10_bwel_d;
reg [63:0] r_t9_inA, r_t9_inB;
reg [63:0] r_t12_datas, c_t11_datasr, c_t11_datasl;
// spin right
reg [3:0] r_t9_balr, c_t8_balr;
reg [3:0] r_t9_mixedr, c_t8_mixedr;
reg [11:0] r_t10_datar, c_t9_datar;
reg [11:0] r_t11_wordr;
reg [7:0] r_t11_byter;
reg r_t11_BBop;
reg [5:0] r_t10_posr, c_t9_posr, r_t11_posr_d;
reg c_t9_pos_ovr;
reg r_t10_bwer, r_t11_bwer_d;
// spin left
reg [3:0] r_t9_ball, c_t8_ball;
reg [3:0] r_t9_mixedl, c_t8_mixedl;
reg [11:0] r_t10_datal, c_t9_datal;
reg [11:0] r_t11_wordl;
reg [7:0] r_t11_bytel;
reg [5:0] r_t10_posl, c_t9_posl, r_t11_posl_d;
reg c_t9_pos_ovl;
reg r_t10_bwel, r_t11_bwel_d;
reg [63:0] r_t10_inA, r_t10_inB;
reg [63:0] r_t13_datas, c_t12_datasr, c_t12_datasl;
// spin right
reg [3:0] r_t10_balr, c_t9_balr;
reg [3:0] r_t10_mixedr, c_t9_mixedr;
reg [11:0] r_t11_datar, c_t10_datar;
reg [11:0] r_t12_wordr;
reg [7:0] r_t12_byter;
reg r_t12_BBop;
reg [5:0] r_t11_posr, c_t10_posr, r_t12_posr_d;
reg c_t10_pos_ovr;
reg r_t11_bwer, r_t12_bwer_d;
// spin left
reg [3:0] r_t10_ball, c_t9_ball;
reg [3:0] r_t10_mixedl, c_t9_mixedl;
reg [11:0] r_t11_datal, c_t10_datal;
reg [11:0] r_t12_wordl;
reg [7:0] r_t12_bytel;
reg [5:0] r_t11_posl, c_t10_posl, r_t12_posl_d;
reg c_t10_pos_ovl;
reg r_t11_bwel, r_t12_bwel_d;
reg [63:0] r_t11_inA, r_t11_inB;
reg [63:0] r_t14_datas, c_t13_datasr, c_t13_datasl;
// spin right
reg [3:0] r_t11_balr, c_t10_balr;
reg [3:0] r_t11_mixedr, c_t10_mixedr;
reg [11:0] r_t12_datar, c_t11_datar;
reg [11:0] r_t13_wordr;
reg [7:0] r_t13_byter;
reg r_t13_BBop;
reg [5:0] r_t12_posr, c_t11_posr, r_t13_posr_d;
reg c_t11_pos_ovr;
reg r_t12_bwer, r_t13_bwer_d;
// spin left
reg [3:0] r_t11_ball, c_t10_ball;
reg [3:0] r_t11_mixedl, c_t10_mixedl;
reg [11:0] r_t12_datal, c_t11_datal;
reg [11:0] r_t13_wordl;
reg [7:0] r_t13_bytel;
reg [5:0] r_t12_posl, c_t11_posl, r_t13_posl_d;
reg c_t11_pos_ovl;
reg r_t12_bwel, r_t13_bwel_d;
reg [63:0] r_t12_inA, r_t12_inB;
reg [63:0] r_t15_datas, c_t14_datasr, c_t14_datasl;
// spin right
reg [3:0] r_t12_balr, c_t11_balr;
reg [3:0] r_t12_mixedr, c_t11_mixedr;
reg [11:0] r_t13_datar, c_t12_datar;
reg [11:0] r_t14_wordr;
reg [7:0] r_t14_byter;
reg r_t14_BBop;
reg [5:0] r_t13_posr, c_t12_posr, r_t14_posr_d;
reg c_t12_pos_ovr;
reg r_t13_bwer, r_t14_bwer_d;
// spin left
reg [3:0] r_t12_ball, c_t11_ball;
reg [3:0] r_t12_mixedl, c_t11_mixedl;
reg [11:0] r_t13_datal, c_t12_datal;
reg [11:0] r_t14_wordl;
reg [7:0] r_t14_bytel;
reg [5:0] r_t13_posl, c_t12_posl, r_t14_posl_d;
reg c_t12_pos_ovl;
reg r_t13_bwel, r_t14_bwel_d;
reg [63:0] r_t13_inA, r_t13_inB;
reg [63:0] r_t16_datas, c_t15_datasr, c_t15_datasl;
// spin right
reg [3:0] r_t13_balr, c_t12_balr;
reg [3:0] r_t13_mixedr, c_t12_mixedr;
reg [11:0] r_t14_datar, c_t13_datar;
reg [11:0] r_t15_wordr;
reg [7:0] r_t15_byter;
reg r_t15_BBop;
reg [5:0] r_t14_posr, c_t13_posr, r_t15_posr_d;
reg c_t13_pos_ovr;
reg r_t14_bwer, r_t15_bwer_d;
// spin left
reg [3:0] r_t13_ball, c_t12_ball;
reg [3:0] r_t13_mixedl, c_t12_mixedl;
reg [11:0] r_t14_datal, c_t13_datal;
reg [11:0] r_t15_wordl;
reg [7:0] r_t15_bytel;
reg [5:0] r_t14_posl, c_t13_posl, r_t15_posl_d;
reg c_t13_pos_ovl;
reg r_t14_bwel, r_t15_bwel_d;
reg [63:0] r_t14_inA, r_t14_inB;
reg [63:0] r_t17_datas, c_t16_datasr, c_t16_datasl;
// spin right
reg [3:0] r_t14_balr, c_t13_balr;
reg [3:0] r_t14_mixedr, c_t13_mixedr;
reg [11:0] r_t15_datar, c_t14_datar;
reg [11:0] r_t16_wordr;
reg [7:0] r_t16_byter;
reg r_t16_BBop;
reg [5:0] r_t15_posr, c_t14_posr, r_t16_posr_d;
reg c_t14_pos_ovr;
reg r_t15_bwer, r_t16_bwer_d;
// spin left
reg [3:0] r_t14_ball, c_t13_ball;
reg [3:0] r_t14_mixedl, c_t13_mixedl;
reg [11:0] r_t15_datal, c_t14_datal;
reg [11:0] r_t16_wordl;
reg [7:0] r_t16_bytel;
reg [5:0] r_t15_posl, c_t14_posl, r_t16_posl_d;
reg c_t14_pos_ovl;
reg r_t15_bwel, r_t16_bwel_d;
reg [63:0] r_t15_inA, r_t15_inB;
reg [63:0] r_t18_datas, c_t17_datasr, c_t17_datasl;
// spin right
reg [3:0] r_t15_balr, c_t14_balr;
reg [3:0] r_t15_mixedr, c_t14_mixedr;
reg [11:0] r_t16_datar, c_t15_datar;
reg [11:0] r_t17_wordr;
reg [7:0] r_t17_byter;
reg r_t17_BBop;
reg [5:0] r_t16_posr, c_t15_posr, r_t17_posr_d;
reg c_t15_pos_ovr;
reg r_t16_bwer, r_t17_bwer_d;
// spin left
reg [3:0] r_t15_ball, c_t14_ball;
reg [3:0] r_t15_mixedl, c_t14_mixedl;
reg [11:0] r_t16_datal, c_t15_datal;
reg [11:0] r_t17_wordl;
reg [7:0] r_t17_bytel;
reg [5:0] r_t16_posl, c_t15_posl, r_t17_posl_d;
reg c_t15_pos_ovl;
reg r_t16_bwel, r_t17_bwel_d;
reg [63:0] r_t16_inA, r_t16_inB;
reg [63:0] r_t19_datas, c_t18_datasr, c_t18_datasl;
// spin right
reg [3:0] r_t16_balr, c_t15_balr;
reg [3:0] r_t16_mixedr, c_t15_mixedr;
reg [11:0] r_t17_datar, c_t16_datar;
reg [11:0] r_t18_wordr;
reg [7:0] r_t18_byter;
reg r_t18_BBop;
reg [5:0] r_t17_posr, c_t16_posr, r_t18_posr_d;
reg c_t16_pos_ovr;
reg r_t17_bwer, r_t18_bwer_d;
// spin left
reg [3:0] r_t16_ball, c_t15_ball;
reg [3:0] r_t16_mixedl, c_t15_mixedl;
reg [11:0] r_t17_datal, c_t16_datal;
reg [11:0] r_t18_wordl;
reg [7:0] r_t18_bytel;
reg [5:0] r_t17_posl, c_t16_posl, r_t18_posl_d;
reg c_t16_pos_ovl;
reg r_t17_bwel, r_t18_bwel_d;
reg [63:0] r_t17_inA, r_t17_inB;
reg [63:0] r_t20_datas, c_t19_datasr, c_t19_datasl;
// spin right
reg [3:0] r_t17_balr, c_t16_balr;
reg [3:0] r_t17_mixedr, c_t16_mixedr;
reg [11:0] r_t18_datar, c_t17_datar;
reg [11:0] r_t19_wordr;
reg [7:0] r_t19_byter;
reg r_t19_BBop;
reg [5:0] r_t18_posr, c_t17_posr, r_t19_posr_d;
reg c_t17_pos_ovr;
reg r_t18_bwer, r_t19_bwer_d;
// spin left
reg [3:0] r_t17_ball, c_t16_ball;
reg [3:0] r_t17_mixedl, c_t16_mixedl;
reg [11:0] r_t18_datal, c_t17_datal;
reg [11:0] r_t19_wordl;
reg [7:0] r_t19_bytel;
reg [5:0] r_t18_posl, c_t17_posl, r_t19_posl_d;
reg c_t17_pos_ovl;
reg r_t18_bwel, r_t19_bwel_d;
reg [63:0] r_t18_inA, r_t18_inB;
reg [63:0] r_t21_datas, c_t20_datasr, c_t20_datasl;
// spin right
reg [3:0] r_t18_balr, c_t17_balr;
reg [3:0] r_t18_mixedr, c_t17_mixedr;
reg [11:0] r_t19_datar, c_t18_datar;
reg [11:0] r_t20_wordr;
reg [7:0] r_t20_byter;
reg r_t20_BBop;
reg [5:0] r_t19_posr, c_t18_posr, r_t20_posr_d;
reg c_t18_pos_ovr;
reg r_t19_bwer, r_t20_bwer_d;
// spin left
reg [3:0] r_t18_ball, c_t17_ball;
reg [3:0] r_t18_mixedl, c_t17_mixedl;
reg [11:0] r_t19_datal, c_t18_datal;
reg [11:0] r_t20_wordl;
reg [7:0] r_t20_bytel;
reg [5:0] r_t19_posl, c_t18_posl, r_t20_posl_d;
reg c_t18_pos_ovl;
reg r_t19_bwel, r_t20_bwel_d;
reg [63:0] r_t19_inA, r_t19_inB;
reg [63:0] r_t22_datas, c_t21_datasr, c_t21_datasl;
// spin right
reg [3:0] r_t19_balr, c_t18_balr;
reg [3:0] r_t19_mixedr, c_t18_mixedr;
reg [11:0] r_t20_datar, c_t19_datar;
reg [11:0] r_t21_wordr;
reg [7:0] r_t21_byter;
reg r_t21_BBop;
reg [5:0] r_t20_posr, c_t19_posr, r_t21_posr_d;
reg c_t19_pos_ovr;
reg r_t20_bwer, r_t21_bwer_d;
// spin left
reg [3:0] r_t19_ball, c_t18_ball;
reg [3:0] r_t19_mixedl, c_t18_mixedl;
reg [11:0] r_t20_datal, c_t19_datal;
reg [11:0] r_t21_wordl;
reg [7:0] r_t21_bytel;
reg [5:0] r_t20_posl, c_t19_posl, r_t21_posl_d;
reg c_t19_pos_ovl;
reg r_t20_bwel, r_t21_bwel_d;
reg r_t20_pos_ovr;
reg [5:0] r_t22_posl_d, r_t22_posr_d;
reg [6:0] r_t21_popc;
reg [63:0] r_t20_inA, r_t21_inA;
reg [32:0] r_t22_popc_l;
reg [31:0] r_t22_popc_u0, r_t22_popc_u1;
reg r_t22_BBop;
reg [7:0] r_t22_byter;
reg [7:0] r_t22_bytel;
reg [63:0] r_t23_datas, c_t22_datasr, c_t22_datasl;
reg [63:0] r_t24_cfuge_out;
// area reduction to improve synthesis area efficiency
wire [63:0] r_t6_MASK = 64'b0;
wire [63:0] r_t7_MASK = 64'hff000000000000ff;
wire [63:0] r_t8_MASK = 64'hff000000000000ff;
wire [63:0] r_t9_MASK = 64'hffff00000000ffff;
wire [63:0] r_t10_MASK = 64'hffff00000000ffff;
wire [63:0] r_t11_MASK = 64'hffffff0000ffffff;
wire [63:0] r_t12_MASK = 64'hffffff0000ffffff;
wire [63:0] r_t13_MASK = 64'hffffffffffffffff;
wire [63:0] r_t14_MASK = 64'hffffffffffffffff;
wire [63:0] r_t15_MASK = 64'hffffffffffffffff;
wire [63:0] r_t16_MASK = 64'hffffffffffffffff;
wire [63:0] r_t17_MASK = 64'hffffffffffffffff;
wire [63:0] r_t18_MASK = 64'hffffffffffffffff;
wire [63:0] r_t19_MASK = 64'hffffffffffffffff;
wire [63:0] r_t20_MASK = 64'hffffffffffffffff;
wire [63:0] r_t21_MASK = 64'hffffffffffffffff;
wire [63:0] r_t22_MASK = 64'hffffffffffffffff;
/* ---------- define tasks ---------- */
// identifies and compresses input bits to preserve
task mix;
// example:
// data_in = 4'b0010
// mask_in = 4'b1011
// dir = 1'b0
// data_out = 4'b0100
// balance = 4'b1110
input [3:0] data_in;
input [3:0] mask_in;
input dir; // 1/0 = left / right
output [3:0] data_out;
output [3:0] balance;
reg [2:0] c_cnt;
integer i;
begin
c_cnt = 3'b0;
data_out = 4'b0;
balance = 4'h0;
if (dir) begin
for (i=3; i>-1; i=i-1) begin
if (mask_in[i]) begin
data_out[3'h3 - c_cnt] = data_in[i];
balance[3'h3 - c_cnt] = 1'b1;
c_cnt = c_cnt + 3'h1;
end
end
end else begin
for (i=0; i<4; i=i+1) begin
if (~mask_in[i]) begin
data_out[c_cnt] = data_in[i];
balance[c_cnt] = 1'b1;
c_cnt = c_cnt + 3'h1;
end
end
end // else: !if(dir)
end
endtask // mix
// incorporates slice into 64-bit word accumulator
// this task cannot achieve 300MHz
// need to divide output into 8-bit addressable slices, to reduce fanin
// also, should not
task spin;
// example:
// slice_in = 4'h5
// balance_in = 4'he
// pos_in = 6'h07
// dir = 1'b0
// data_out = 64'h00000000000000ef
// pos_out = 6'h08
input [3:0] slice_in;
input [3:0] balance_in;
input [5:0] pos_in;
input dir; // 1/0 = left / right
output [11:0] data_out;
output [5:0] pos_out;
output pos_ov;
reg [3:0] pos_int;
reg [2:0] pop_cnt_bal;
integer i;
begin
// pos_out = pos_in;
pos_int = {1'b0,pos_in[2:0]};
data_out = 12'b0;
pop_cnt_bal = balance_in[3] + balance_in[2] + balance_in[1] + balance_in[0];
if (dir) begin
for (i=3; i>-1; i=i-1) begin
if (balance_in[i]) begin
data_out[pos_int] = slice_in[i];
// pos_out = pos_out - 6'h1;
pos_int = |pos_int ? pos_int - 4'h1 : 4'd11;
end
end
pos_out = pos_in - pop_cnt_bal;
pos_ov = ~pos_in[5] & pos_out[5];
end else begin
for (i=0; i<4; i=i+1) begin
if (balance_in[i]) begin
data_out[pos_int] = slice_in[i];
// pos_out = pos_out + 6'h1;
pos_int = pos_int + 4'h1;
end
end
pos_out = pos_in + pop_cnt_bal;
pos_ov = pos_in[5] & ~pos_out[5];
end // else: !if(dir)
end
endtask // spin
/* ---------- drive outputs ---------- */
wire o_done = r_t2_done; // default for non-multistage use
wire [63:0] o_result = r_t24_cfuge_out;
wire o_vm = 1'b0;
wire o_hit = 1'b0;
wire o_error = 1'b0;
/* ---------- combinatorial blocks ---------- */
// track the number of elements, starting at start
assign c_t1_cnt = r_reset ? 9'h0 :
r_t1_start ? r_t1_elemCnt :
|r_t2_cnt ? {r_t2_cnt - 9'h1} : r_t2_cnt;
// is the pipe active this cycle?
// following is equivalent to: assign c_t1_active = |c_t1_cnt;
assign c_t1_active = r_t1_start ? |r_t1_elemCnt :
|r_t2_cnt[8:1];
// if not using multi-stage mode, make sure a multi-stage start doesn't hang the machine
assign c_t1_done = r_t1_start && (r_t1_arc0[ARC0_START0] || r_t1_arc0[ARC0_START1]);
// select first part of mux here, mux in AMS data next cycle
always @(*)
begin
case (r_t2_arc0[ARC0_BMux+:2])
Arc0_BMux_B: c_t2_inB = r_t2_vrB;
Arc0_BMux_S: c_t2_inB = r_t2_scalar;
Arc0_BMux_Zero: c_t2_inB = 64'b0;
default: c_t2_inB = 64'b0;
endcase // case (r_t1_arc0[ARC0_BMux+:2])
end
assign c_t2_inA = r_t2_arc0[ARC0_AMux] == Arc0_AMux_Zero ? 64'b0 : r_t2_vrA;
// centrifuge specific functionality is here
// pipe 3
always @(*)
begin
mix(r_t3_inA[0+:4], r_t3_inB[0+:4], 1'b0, c_t3_mixedr[3:0], c_t3_balr[3:0]);
mix(r_t3_inA[63-:4], r_t3_inB[63-:4], 1'b1, c_t3_mixedl[3:0], c_t3_ball[3:0]);
end
// pipe 4
always @(*)
begin
mix(r_t4_inA[4+:4], r_t4_inB[4+:4], 1'b0, c_t4_mixedr[3:0], c_t4_balr[3:0]);
mix(r_t4_inA[59-:4], r_t4_inB[59-:4], 1'b1, c_t4_mixedl[3:0], c_t4_ball[3:0]);
end
// pipe 5
always @(*)
begin
mix(r_t5_inA[8+:4], r_t5_inB[8+:4], 1'b0, c_t5_mixedr[3:0], c_t5_balr[3:0]);
mix(r_t5_inA[55-:4], r_t5_inB[55-:4], 1'b1, c_t5_mixedl[3:0], c_t5_ball[3:0]);
end
// pipe 6
always @(*)
begin
mix(r_t6_inA[12+:4], r_t6_inB[12+:4], 1'b0, c_t6_mixedr[3:0], c_t6_balr[3:0]);
mix(r_t6_inA[51-:4], r_t6_inB[51-:4], 1'b1, c_t6_mixedl[3:0], c_t6_ball[3:0]);
end
// pipe 7
always @(*)
begin
mix(r_t7_inA[16+:4], r_t7_inB[16+:4], 1'b0, c_t7_mixedr[3:0], c_t7_balr[3:0]);
mix(r_t7_inA[47-:4], r_t7_inB[47-:4], 1'b1, c_t7_mixedl[3:0], c_t7_ball[3:0]);
end
// pipe 8
always @(*)
begin
mix(r_t8_inA[20+:4], r_t8_inB[20+:4], 1'b0, c_t8_mixedr[3:0], c_t8_balr[3:0]);
mix(r_t8_inA[43-:4], r_t8_inB[43-:4], 1'b1, c_t8_mixedl[3:0], c_t8_ball[3:0]);
end
// pipe 9
always @(*)
begin
mix(r_t9_inA[24+:4], r_t9_inB[24+:4], 1'b0, c_t9_mixedr[3:0], c_t9_balr[3:0]);
mix(r_t9_inA[39-:4], r_t9_inB[39-:4], 1'b1, c_t9_mixedl[3:0], c_t9_ball[3:0]);
end
// pipe 10
always @(*)
begin
mix(r_t10_inA[28+:4], r_t10_inB[28+:4], 1'b0, c_t10_mixedr[3:0], c_t10_balr[3:0]);
mix(r_t10_inA[35-:4], r_t10_inB[35-:4], 1'b1, c_t10_mixedl[3:0], c_t10_ball[3:0]);
end
// pipe 11
always @(*)
begin
mix(r_t11_inA[32+:4], r_t11_inB[32+:4], 1'b0, c_t11_mixedr[3:0], c_t11_balr[3:0]);
mix(r_t11_inA[31-:4], r_t11_inB[31-:4], 1'b1, c_t11_mixedl[3:0], c_t11_ball[3:0]);
end
// pipe 12
always @(*)
begin
mix(r_t12_inA[36+:4], r_t12_inB[36+:4], 1'b0, c_t12_mixedr[3:0], c_t12_balr[3:0]);
mix(r_t12_inA[27-:4], r_t12_inB[27-:4], 1'b1, c_t12_mixedl[3:0], c_t12_ball[3:0]);
end
// pipe 13
always @(*)
begin
mix(r_t13_inA[40+:4], r_t13_inB[40+:4], 1'b0, c_t13_mixedr[3:0], c_t13_balr[3:0]);
mix(r_t13_inA[23-:4], r_t13_inB[23-:4], 1'b1, c_t13_mixedl[3:0], c_t13_ball[3:0]);
end
// pipe 14
always @(*)
begin
mix(r_t14_inA[44+:4], r_t14_inB[44+:4], 1'b0, c_t14_mixedr[3:0], c_t14_balr[3:0]);
mix(r_t14_inA[19-:4], r_t14_inB[19-:4], 1'b1, c_t14_mixedl[3:0], c_t14_ball[3:0]);
end
// pipe 15
always @(*)
begin
mix(r_t15_inA[48+:4], r_t15_inB[48+:4], 1'b0, c_t15_mixedr[3:0], c_t15_balr[3:0]);
mix(r_t15_inA[15-:4], r_t15_inB[15-:4], 1'b1, c_t15_mixedl[3:0], c_t15_ball[3:0]);
end
// pipe 16
always @(*)
begin
mix(r_t16_inA[52+:4], r_t16_inB[52+:4], 1'b0, c_t16_mixedr[3:0], c_t16_balr[3:0]);
mix(r_t16_inA[11-:4], r_t16_inB[11-:4], 1'b1, c_t16_mixedl[3:0], c_t16_ball[3:0]);
end
// pipe 17
always @(*)
begin
mix(r_t17_inA[56+:4], r_t17_inB[56+:4], 1'b0, c_t17_mixedr[3:0], c_t17_balr[3:0]);
mix(r_t17_inA[7-:4], r_t17_inB[7-:4], 1'b1, c_t17_mixedl[3:0], c_t17_ball[3:0]);
end
// pipe 18
always @(*)
begin
mix(r_t18_inA[60+:4], r_t18_inB[60+:4], 1'b0, c_t18_mixedr[3:0], c_t18_balr[3:0]);
mix(r_t18_inA[3-:4], r_t18_inB[3-:4], 1'b1, c_t18_mixedl[3:0], c_t18_ball[3:0]);
end
// pipe 4
always @(*)
begin
spin(r_t4_mixedr, r_t4_balr, r_t4_posr, 1'b0,
c_t4_datar, c_t4_posr, c_t4_pos_ovr);
spin(r_t4_mixedl, r_t4_ball, r_t4_posl, 1'b1,
c_t4_datal, c_t4_posl, c_t4_pos_ovl);
end
// pipe 5
always @(*)
begin
spin(r_t5_mixedr, r_t5_balr, r_t5_posr, 1'b0,
c_t5_datar, c_t5_posr, c_t5_pos_ovr);
spin(r_t5_mixedl, r_t5_ball, r_t5_posl, 1'b1,
c_t5_datal, c_t5_posl, c_t5_pos_ovl);
end
// pipe 6
always @(*)
begin
spin(r_t6_mixedr, r_t6_balr, r_t6_posr, 1'b0,
c_t6_datar, c_t6_posr, c_t6_pos_ovr);
spin(r_t6_mixedl, r_t6_ball, r_t6_posl, 1'b1,
c_t6_datal, c_t6_posl, c_t6_pos_ovl);
end
// pipe 7
always @(*)
begin
spin(r_t7_mixedr, r_t7_balr, r_t7_posr, 1'b0,
c_t7_datar, c_t7_posr, c_t7_pos_ovr);
spin(r_t7_mixedl, r_t7_ball, r_t7_posl, 1'b1,
c_t7_datal, c_t7_posl, c_t7_pos_ovl);
end
// pipe 8
always @(*)
begin
spin(r_t8_mixedr, r_t8_balr, r_t8_posr, 1'b0,
c_t8_datar, c_t8_posr, c_t8_pos_ovr);
spin(r_t8_mixedl, r_t8_ball, r_t8_posl, 1'b1,
c_t8_datal, c_t8_posl, c_t8_pos_ovl);
end
// pipe 9
always @(*)
begin
spin(r_t9_mixedr, r_t9_balr, r_t9_posr, 1'b0,
c_t9_datar, c_t9_posr, c_t9_pos_ovr);
spin(r_t9_mixedl, r_t9_ball, r_t9_posl, 1'b1,
c_t9_datal, c_t9_posl, c_t9_pos_ovl);
end
// pipe 10
always @(*)
begin
spin(r_t10_mixedr, r_t10_balr, r_t10_posr, 1'b0,
c_t10_datar, c_t10_posr, c_t10_pos_ovr);
spin(r_t10_mixedl, r_t10_ball, r_t10_posl, 1'b1,
c_t10_datal, c_t10_posl, c_t10_pos_ovl);
end
// pipe 11
always @(*)
begin
spin(r_t11_mixedr, r_t11_balr, r_t11_posr, 1'b0,
c_t11_datar, c_t11_posr, c_t11_pos_ovr);
spin(r_t11_mixedl, r_t11_ball, r_t11_posl, 1'b1,
c_t11_datal, c_t11_posl, c_t11_pos_ovl);
end
// pipe 12
always @(*)
begin
spin(r_t12_mixedr, r_t12_balr, r_t12_posr, 1'b0,
c_t12_datar, c_t12_posr, c_t12_pos_ovr);
spin(r_t12_mixedl, r_t12_ball, r_t12_posl, 1'b1,
c_t12_datal, c_t12_posl, c_t12_pos_ovl);
end
// pipe 13
always @(*)
begin
spin(r_t13_mixedr, r_t13_balr, r_t13_posr, 1'b0,
c_t13_datar, c_t13_posr, c_t13_pos_ovr);
spin(r_t13_mixedl, r_t13_ball, r_t13_posl, 1'b1,
c_t13_datal, c_t13_posl, c_t13_pos_ovl);
end
// pipe 14
always @(*)
begin
spin(r_t14_mixedr, r_t14_balr, r_t14_posr, 1'b0,
c_t14_datar, c_t14_posr, c_t14_pos_ovr);
spin(r_t14_mixedl, r_t14_ball, r_t14_posl, 1'b1,
c_t14_datal, c_t14_posl, c_t14_pos_ovl);
end
// pipe 15
always @(*)
begin
spin(r_t15_mixedr, r_t15_balr, r_t15_posr, 1'b0,
c_t15_datar, c_t15_posr, c_t15_pos_ovr);
spin(r_t15_mixedl, r_t15_ball, r_t15_posl, 1'b1,
c_t15_datal, c_t15_posl, c_t15_pos_ovl);
end
// pipe 16
always @(*)
begin
spin(r_t16_mixedr, r_t16_balr, r_t16_posr, 1'b0,
c_t16_datar, c_t16_posr, c_t16_pos_ovr);
spin(r_t16_mixedl, r_t16_ball, r_t16_posl, 1'b1,
c_t16_datal, c_t16_posl, c_t16_pos_ovl);
end
// pipe 17
always @(*)
begin
spin(r_t17_mixedr, r_t17_balr, r_t17_posr, 1'b0,
c_t17_datar, c_t17_posr, c_t17_pos_ovr);
spin(r_t17_mixedl, r_t17_ball, r_t17_posl, 1'b1,
c_t17_datal, c_t17_posl, c_t17_pos_ovl);
end
// pipe 18
always @(*)
begin
spin(r_t18_mixedr, r_t18_balr, r_t18_posr, 1'b0,
c_t18_datar, c_t18_posr, c_t18_pos_ovr);
spin(r_t18_mixedl, r_t18_ball, r_t18_posl, 1'b1,
c_t18_datal, c_t18_posl, c_t18_pos_ovl);
end
// pipe 19
always @(*)
begin
spin(r_t19_mixedr, r_t19_balr, r_t19_posr, 1'b0,
c_t19_datar, c_t19_posr, c_t19_pos_ovr);
spin(r_t19_mixedl, r_t19_ball, r_t19_posl, 1'b1,
c_t19_datal, c_t19_posl, c_t19_pos_ovl);
end
// leda E267 off Range index out of bound
// pipe 6
always @(*)
begin
c_t6_datasr = 64'b0;
if (r_t6_bwer_d)
c_t6_datasr[{r_t6_posr_d[5:3],3'b0} +: 6'h8] = r_t6_byter[7:0];
c_t6_datasl = 64'b0;
if (r_t6_bwel_d)
c_t6_datasl[{r_t6_posl_d[5:3],3'b0} +: 6'h8] = r_t6_bytel[7:0];
end
// pipe 7
always @(*)
begin
c_t7_datasr = 64'b0;
if (r_t7_bwer_d)
c_t7_datasr[{r_t7_posr_d[5:3],3'b0} +: 6'h8] = r_t7_byter[7:0];
c_t7_datasl = 64'b0;
if (r_t7_bwel_d)
c_t7_datasl[{r_t7_posl_d[5:3],3'b0} +: 6'h8] = r_t7_bytel[7:0];
end
// pipe 8
always @(*)
begin
c_t8_datasr = 64'b0;
if (r_t8_bwer_d)
c_t8_datasr[{r_t8_posr_d[5:3],3'b0} +: 6'h8] = r_t8_byter[7:0];
c_t8_datasl = 64'b0;
if (r_t8_bwel_d)
c_t8_datasl[{r_t8_posl_d[5:3],3'b0} +: 6'h8] = r_t8_bytel[7:0];
end
// pipe 9
always @(*)
begin
c_t9_datasr = 64'b0;
if (r_t9_bwer_d)
c_t9_datasr[{r_t9_posr_d[5:3],3'b0} +: 6'h8] = r_t9_byter[7:0];
c_t9_datasl = 64'b0;
if (r_t9_bwel_d)
c_t9_datasl[{r_t9_posl_d[5:3],3'b0} +: 6'h8] = r_t9_bytel[7:0];
end
// pipe 10
always @(*)
begin
c_t10_datasr = 64'b0;
if (r_t10_bwer_d)
c_t10_datasr[{r_t10_posr_d[5:3],3'b0} +: 6'h8] = r_t10_byter[7:0];
c_t10_datasl = 64'b0;
if (r_t10_bwel_d)
c_t10_datasl[{r_t10_posl_d[5:3],3'b0} +: 6'h8] = r_t10_bytel[7:0];
end
// pipe 11
always @(*)
begin
c_t11_datasr = 64'b0;
if (r_t11_bwer_d)
c_t11_datasr[{r_t11_posr_d[5:3],3'b0} +: 6'h8] = r_t11_byter[7:0];
c_t11_datasl = 64'b0;
if (r_t11_bwel_d)
c_t11_datasl[{r_t11_posl_d[5:3],3'b0} +: 6'h8] = r_t11_bytel[7:0];
end
// pipe 12
always @(*)
begin
c_t12_datasr = 64'b0;
if (r_t12_bwer_d)
c_t12_datasr[{r_t12_posr_d[5:3],3'b0} +: 6'h8] = r_t12_byter[7:0];
c_t12_datasl = 64'b0;
if (r_t12_bwel_d)
c_t12_datasl[{r_t12_posl_d[5:3],3'b0} +: 6'h8] = r_t12_bytel[7:0];
end
// pipe 13
always @(*)
begin
c_t13_datasr = 64'b0;
if (r_t13_bwer_d)
c_t13_datasr[{r_t13_posr_d[5:3],3'b0} +: 6'h8] = r_t13_byter[7:0];
c_t13_datasl = 64'b0;
if (r_t13_bwel_d)
c_t13_datasl[{r_t13_posl_d[5:3],3'b0} +: 6'h8] = r_t13_bytel[7:0];
end
// pipe 14
always @(*)
begin
c_t14_datasr = 64'b0;
if (r_t14_bwer_d)
c_t14_datasr[{r_t14_posr_d[5:3],3'b0} +: 6'h8] = r_t14_byter[7:0];
c_t14_datasl = 64'b0;
if (r_t14_bwel_d)
c_t14_datasl[{r_t14_posl_d[5:3],3'b0} +: 6'h8] = r_t14_bytel[7:0];
end
// pipe 15
always @(*)
begin
c_t15_datasr = 64'b0;
if (r_t15_bwer_d)
c_t15_datasr[{r_t15_posr_d[5:3],3'b0} +: 6'h8] = r_t15_byter[7:0];
c_t15_datasl = 64'b0;
if (r_t15_bwel_d)
c_t15_datasl[{r_t15_posl_d[5:3],3'b0} +: 6'h8] = r_t15_bytel[7:0];
end
// pipe 16
always @(*)
begin
c_t16_datasr = 64'b0;
if (r_t16_bwer_d)
c_t16_datasr[{r_t16_posr_d[5:3],3'b0} +: 6'h8] = r_t16_byter[7:0];
c_t16_datasl = 64'b0;
if (r_t16_bwel_d)
c_t16_datasl[{r_t16_posl_d[5:3],3'b0} +: 6'h8] = r_t16_bytel[7:0];
end
// pipe 17
always @(*)
begin
c_t17_datasr = 64'b0;
if (r_t17_bwer_d)
c_t17_datasr[{r_t17_posr_d[5:3],3'b0} +: 6'h8] = r_t17_byter[7:0];
c_t17_datasl = 64'b0;
if (r_t17_bwel_d)
c_t17_datasl[{r_t17_posl_d[5:3],3'b0} +: 6'h8] = r_t17_bytel[7:0];
end
// pipe 18
always @(*)
begin
c_t18_datasr = 64'b0;
if (r_t18_bwer_d)
c_t18_datasr[{r_t18_posr_d[5:3],3'b0} +: 6'h8] = r_t18_byter[7:0];
c_t18_datasl = 64'b0;
if (r_t18_bwel_d)
c_t18_datasl[{r_t18_posl_d[5:3],3'b0} +: 6'h8] = r_t18_bytel[7:0];
end
// pipe 19
always @(*)
begin
c_t19_datasr = 64'b0;
if (r_t19_bwer_d)
c_t19_datasr[{r_t19_posr_d[5:3],3'b0} +: 6'h8] = r_t19_byter[7:0];
c_t19_datasl = 64'b0;
if (r_t19_bwel_d)
c_t19_datasl[{r_t19_posl_d[5:3],3'b0} +: 6'h8] = r_t19_bytel[7:0];
end
// pipe 20
always @(*)
begin
c_t20_datasr = 64'b0;
if (r_t20_bwer_d)
c_t20_datasr[{r_t20_posr_d[5:3],3'b0} +: 6'h8] = r_t20_byter[7:0];
c_t20_datasl = 64'b0;
if (r_t20_bwel_d)
c_t20_datasl[{r_t20_posl_d[5:3],3'b0} +: 6'h8] = r_t20_bytel[7:0];
end
// pipe 21
always @(*)
begin
c_t21_datasr = 64'b0;
c_t21_datasr[{r_t21_posr_d[5:3],3'b0} +: 6'h8] = r_t21_byter[7:0];
c_t21_datasl = 64'b0;
c_t21_datasl[{r_t21_posl_d[5:3],3'b0} +: 6'h8] = r_t21_bytel[7:0];
end
always @(*)
begin
c_t22_datasr = 64'b0;
c_t22_datasr[8 * r_t22_posr_d[5:3] +: 8] = r_t22_byter[7:0];
c_t22_datasl = 64'b0;
c_t22_datasl[8 * r_t22_posl_d[5:3] +: 8] = r_t22_bytel[7:0];
end
// leda E267 on Range index out of bound
/* ---------- registers ---------- */
always @(posedge clk2x) begin // 300Mhz
// register inputs
r_reset <= i_reset;
r_t1_start <= i_start;
r_t1_vrA <= i_vrA;
r_t1_vrB <= i_vrB;
r_t2_vrA <= r_t1_vrA;
r_t2_vrB <= r_t1_vrB;
r_t1_scalar <= i_start ? i_scalar : r_t1_scalar;
r_t1_elemCnt <= i_start ? i_elemCnt : r_t1_elemCnt;
r_t1_arc0 <= i_start ? i_arc0 : r_t1_arc0;
r_t1_arc1 <= i_start ? i_arc1 : r_t1_arc1;
r_t1_arc2 <= i_start ? i_arc2 : r_t1_arc2;
r_t1_arc3 <= i_start ? i_arc3 : r_t1_arc3;
r_t2_scalar <= r_t1_scalar;
// internal registers
r_t2_cnt <= c_t1_cnt;
r_t2_active <= r_reset ? 1'b0 : c_t1_active;
r_t2_arc0 <= r_reset ? BBARC0_idle : c_t1_active ? r_t1_arc0 : BBARC0_idle;
r_t2_done <= c_t1_done;
r_t3_inA <= r_t2_arc0[ARC0_BBop] ? c_t2_inB : c_t2_inA; // swap inputs if pop cnt
r_t3_active <= r_t2_active;
r_t3_inB <= r_t2_arc0[ARC0_BBop] ? c_t2_inA : c_t2_inB; // swap inputs if pop cnt
r_t3_BBop <= r_t2_arc0[ARC0_BBop];
r_t4_active <= r_t3_active;
r_t4_BBop <= r_t3_BBop;
r_t5_BBop <= r_t4_BBop;
//centrifuge constants
r_t4_posr <= 6'h0;
r_t4_posl <= 6'h3f;
r_t5_wordr <= 12'h0;
r_t5_wordl <= 12'h0;
r_t6_datas <= 64'b0;
// centrifuge pipeline registers
r_t4_inA <= r_t3_inA;
r_t4_inB <= r_t3_inB;
r_t4_mixedr <= c_t3_mixedr;
r_t4_mixedl <= c_t3_mixedl;
r_t4_balr <= c_t3_balr;
r_t4_ball <= c_t3_ball;
r_t5_posr <= c_t4_posr;
r_t5_posl <= c_t4_posl;
r_t5_bwer <= c_t4_posr[3] ^ r_t4_posr[3];
r_t5_bwel <= c_t4_posl[3] ^ r_t4_posl[3];
r_t5_datar <= c_t4_datar;
r_t5_datal <= c_t4_datal;
r_t6_BBop <= r_t5_BBop;
r_t6_wordr <= r_t5_bwer ? {8'b0, r_t5_wordr[11:8] | r_t5_datar[11:8]} : r_t5_wordr[11:0] | r_t5_datar[11:0];
r_t6_wordl <= r_t5_bwel ? {4'b0, r_t5_wordl[11:8] | r_t5_datal[11:8], 4'b0} : r_t5_wordl[11:0] | r_t5_datal[11:0];
r_t6_byter <= r_t5_wordr[7:0] | r_t5_datar[7:0];
r_t6_bytel <= r_t5_wordl[7:0] | r_t5_datal[7:0];
r_t6_bwer_d <= r_t5_bwer;
r_t6_bwel_d <= r_t5_bwel;
r_t6_posr_d <= r_t5_bwer ? (|r_t5_posr ? r_t5_posr - 6'h8 : 6'h38) : r_t5_posr;
r_t6_posl_d <= r_t5_bwel ? (&r_t5_posl ? 6'h00 : r_t5_posl + 6'h8) : r_t5_posl;
r_t7_datas <= r_t6_MASK & (c_t6_datasr | c_t6_datasl | r_t6_datas);
// centrifuge pipeline registers
r_t5_inA <= r_t4_inA;
r_t5_inB <= r_t4_inB;
r_t5_mixedr <= c_t4_mixedr;
r_t5_mixedl <= c_t4_mixedl;
r_t5_balr <= c_t4_balr;
r_t5_ball <= c_t4_ball;
r_t6_posr <= c_t5_posr;
r_t6_posl <= c_t5_posl;
r_t6_bwer <= c_t5_posr[3] ^ r_t5_posr[3];
r_t6_bwel <= c_t5_posl[3] ^ r_t5_posl[3];
r_t6_datar <= c_t5_datar;
r_t6_datal <= c_t5_datal;
r_t7_BBop <= r_t6_BBop;
r_t7_wordr <= r_t6_bwer ? {8'b0, r_t6_wordr[11:8] | r_t6_datar[11:8]} : r_t6_wordr[11:0] | r_t6_datar[11:0];
r_t7_wordl <= r_t6_bwel ? {4'b0, r_t6_wordl[11:8] | r_t6_datal[11:8], 4'b0} : r_t6_wordl[11:0] | r_t6_datal[11:0];
r_t7_byter <= r_t6_wordr[7:0] | r_t6_datar[7:0];
r_t7_bytel <= r_t6_wordl[7:0] | r_t6_datal[7:0];
r_t7_bwer_d <= r_t6_bwer;
r_t7_bwel_d <= r_t6_bwel;
r_t7_posr_d <= r_t6_bwer ? (|r_t6_posr ? r_t6_posr - 6'h8 : 6'h38) : r_t6_posr;
r_t7_posl_d <= r_t6_bwel ? (&r_t6_posl ? 6'h00 : r_t6_posl + 6'h8) : r_t6_posl;
r_t8_datas <= r_t7_MASK & (c_t7_datasr | c_t7_datasl | r_t7_datas);
// centrifuge pipeline registers
r_t6_inA <= r_t5_inA;
r_t6_inB <= r_t5_inB;
r_t6_mixedr <= c_t5_mixedr;
r_t6_mixedl <= c_t5_mixedl;
r_t6_balr <= c_t5_balr;
r_t6_ball <= c_t5_ball;
r_t7_posr <= c_t6_posr;
r_t7_posl <= c_t6_posl;
r_t7_bwer <= c_t6_posr[3] ^ r_t6_posr[3];
r_t7_bwel <= c_t6_posl[3] ^ r_t6_posl[3];
r_t7_datar <= c_t6_datar;
r_t7_datal <= c_t6_datal;
r_t8_BBop <= r_t7_BBop;
r_t8_wordr <= r_t7_bwer ? {8'b0, r_t7_wordr[11:8] | r_t7_datar[11:8]} : r_t7_wordr[11:0] | r_t7_datar[11:0];
r_t8_wordl <= r_t7_bwel ? {4'b0, r_t7_wordl[11:8] | r_t7_datal[11:8], 4'b0} : r_t7_wordl[11:0] | r_t7_datal[11:0];
r_t8_byter <= r_t7_wordr[7:0] | r_t7_datar[7:0];
r_t8_bytel <= r_t7_wordl[7:0] | r_t7_datal[7:0];
r_t8_bwer_d <= r_t7_bwer;
r_t8_bwel_d <= r_t7_bwel;
r_t8_posr_d <= r_t7_bwer ? (|r_t7_posr ? r_t7_posr - 6'h8 : 6'h38) : r_t7_posr;
r_t8_posl_d <= r_t7_bwel ? (&r_t7_posl ? 6'h00 : r_t7_posl + 6'h8) : r_t7_posl;
r_t9_datas <= r_t8_MASK & (c_t8_datasr | c_t8_datasl | r_t8_datas);
// centrifuge pipeline registers
r_t7_inA <= r_t6_inA;
r_t7_inB <= r_t6_inB;
r_t7_mixedr <= c_t6_mixedr;
r_t7_mixedl <= c_t6_mixedl;
r_t7_balr <= c_t6_balr;
r_t7_ball <= c_t6_ball;
r_t8_posr <= c_t7_posr;
r_t8_posl <= c_t7_posl;
r_t8_bwer <= c_t7_posr[3] ^ r_t7_posr[3];
r_t8_bwel <= c_t7_posl[3] ^ r_t7_posl[3];
r_t8_datar <= c_t7_datar;
r_t8_datal <= c_t7_datal;
r_t9_BBop <= r_t8_BBop;
r_t9_wordr <= r_t8_bwer ? {8'b0, r_t8_wordr[11:8] | r_t8_datar[11:8]} : r_t8_wordr[11:0] | r_t8_datar[11:0];
r_t9_wordl <= r_t8_bwel ? {4'b0, r_t8_wordl[11:8] | r_t8_datal[11:8], 4'b0} : r_t8_wordl[11:0] | r_t8_datal[11:0];
r_t9_byter <= r_t8_wordr[7:0] | r_t8_datar[7:0];
r_t9_bytel <= r_t8_wordl[7:0] | r_t8_datal[7:0];
r_t9_bwer_d <= r_t8_bwer;
r_t9_bwel_d <= r_t8_bwel;
r_t9_posr_d <= r_t8_bwer ? (|r_t8_posr ? r_t8_posr - 6'h8 : 6'h38) : r_t8_posr;
r_t9_posl_d <= r_t8_bwel ? (&r_t8_posl ? 6'h00 : r_t8_posl + 6'h8) : r_t8_posl;
r_t10_datas <= r_t9_MASK & (c_t9_datasr | c_t9_datasl | r_t9_datas);
// centrifuge pipeline registers
r_t8_inA <= r_t7_inA;
r_t8_inB <= r_t7_inB;
r_t8_mixedr <= c_t7_mixedr;
r_t8_mixedl <= c_t7_mixedl;
r_t8_balr <= c_t7_balr;
r_t8_ball <= c_t7_ball;
r_t9_posr <= c_t8_posr;
r_t9_posl <= c_t8_posl;
r_t9_bwer <= c_t8_posr[3] ^ r_t8_posr[3];
r_t9_bwel <= c_t8_posl[3] ^ r_t8_posl[3];
r_t9_datar <= c_t8_datar;
r_t9_datal <= c_t8_datal;
r_t10_BBop <= r_t9_BBop;
r_t10_wordr <= r_t9_bwer ? {8'b0, r_t9_wordr[11:8] | r_t9_datar[11:8]} : r_t9_wordr[11:0] | r_t9_datar[11:0];
r_t10_wordl <= r_t9_bwel ? {4'b0, r_t9_wordl[11:8] | r_t9_datal[11:8], 4'b0} : r_t9_wordl[11:0] | r_t9_datal[11:0];
r_t10_byter <= r_t9_wordr[7:0] | r_t9_datar[7:0];
r_t10_bytel <= r_t9_wordl[7:0] | r_t9_datal[7:0];
r_t10_bwer_d <= r_t9_bwer;
r_t10_bwel_d <= r_t9_bwel;
r_t10_posr_d <= r_t9_bwer ? (|r_t9_posr ? r_t9_posr - 6'h8 : 6'h38) : r_t9_posr;
r_t10_posl_d <= r_t9_bwel ? (&r_t9_posl ? 6'h00 : r_t9_posl + 6'h8) : r_t9_posl;
r_t11_datas <= r_t10_MASK & (c_t10_datasr | c_t10_datasl | r_t10_datas);
// centrifuge pipeline registers
r_t9_inA <= r_t8_inA;
r_t9_inB <= r_t8_inB;
r_t9_mixedr <= c_t8_mixedr;
r_t9_mixedl <= c_t8_mixedl;
r_t9_balr <= c_t8_balr;
r_t9_ball <= c_t8_ball;
r_t10_posr <= c_t9_posr;
r_t10_posl <= c_t9_posl;
r_t10_bwer <= c_t9_posr[3] ^ r_t9_posr[3];
r_t10_bwel <= c_t9_posl[3] ^ r_t9_posl[3];
r_t10_datar <= c_t9_datar;
r_t10_datal <= c_t9_datal;
r_t11_BBop <= r_t10_BBop;
r_t11_wordr <= r_t10_bwer ? {8'b0, r_t10_wordr[11:8] | r_t10_datar[11:8]} : r_t10_wordr[11:0] | r_t10_datar[11:0];
r_t11_wordl <= r_t10_bwel ? {4'b0, r_t10_wordl[11:8] | r_t10_datal[11:8], 4'b0} : r_t10_wordl[11:0] | r_t10_datal[11:0];
r_t11_byter <= r_t10_wordr[7:0] | r_t10_datar[7:0];
r_t11_bytel <= r_t10_wordl[7:0] | r_t10_datal[7:0];
r_t11_bwer_d <= r_t10_bwer;
r_t11_bwel_d <= r_t10_bwel;
r_t11_posr_d <= r_t10_bwer ? (|r_t10_posr ? r_t10_posr - 6'h8 : 6'h38) : r_t10_posr;
r_t11_posl_d <= r_t10_bwel ? (&r_t10_posl ? 6'h00 : r_t10_posl + 6'h8) : r_t10_posl;
r_t12_datas <= r_t11_MASK & (c_t11_datasr | c_t11_datasl | r_t11_datas);
// centrifuge pipeline registers
r_t10_inA <= r_t9_inA;
r_t10_inB <= r_t9_inB;
r_t10_mixedr <= c_t9_mixedr;
r_t10_mixedl <= c_t9_mixedl;
r_t10_balr <= c_t9_balr;
r_t10_ball <= c_t9_ball;
r_t11_posr <= c_t10_posr;
r_t11_posl <= c_t10_posl;
r_t11_bwer <= c_t10_posr[3] ^ r_t10_posr[3];
r_t11_bwel <= c_t10_posl[3] ^ r_t10_posl[3];
r_t11_datar <= c_t10_datar;
r_t11_datal <= c_t10_datal;
r_t12_BBop <= r_t11_BBop;
r_t12_wordr <= r_t11_bwer ? {8'b0, r_t11_wordr[11:8] | r_t11_datar[11:8]} : r_t11_wordr[11:0] | r_t11_datar[11:0];
r_t12_wordl <= r_t11_bwel ? {4'b0, r_t11_wordl[11:8] | r_t11_datal[11:8], 4'b0} : r_t11_wordl[11:0] | r_t11_datal[11:0];
r_t12_byter <= r_t11_wordr[7:0] | r_t11_datar[7:0];
r_t12_bytel <= r_t11_wordl[7:0] | r_t11_datal[7:0];
r_t12_bwer_d <= r_t11_bwer;
r_t12_bwel_d <= r_t11_bwel;
r_t12_posr_d <= r_t11_bwer ? (|r_t11_posr ? r_t11_posr - 6'h8 : 6'h38) : r_t11_posr;
r_t12_posl_d <= r_t11_bwel ? (&r_t11_posl ? 6'h00 : r_t11_posl + 6'h8) : r_t11_posl;
r_t13_datas <= r_t12_MASK & (c_t12_datasr | c_t12_datasl | r_t12_datas);
// centrifuge pipeline registers
r_t11_inA <= r_t10_inA;
r_t11_inB <= r_t10_inB;
r_t11_mixedr <= c_t10_mixedr;
r_t11_mixedl <= c_t10_mixedl;
r_t11_balr <= c_t10_balr;
r_t11_ball <= c_t10_ball;
r_t12_posr <= c_t11_posr;
r_t12_posl <= c_t11_posl;
r_t12_bwer <= c_t11_posr[3] ^ r_t11_posr[3];
r_t12_bwel <= c_t11_posl[3] ^ r_t11_posl[3];
r_t12_datar <= c_t11_datar;
r_t12_datal <= c_t11_datal;
r_t13_BBop <= r_t12_BBop;
r_t13_wordr <= r_t12_bwer ? {8'b0, r_t12_wordr[11:8] | r_t12_datar[11:8]} : r_t12_wordr[11:0] | r_t12_datar[11:0];
r_t13_wordl <= r_t12_bwel ? {4'b0, r_t12_wordl[11:8] | r_t12_datal[11:8], 4'b0} : r_t12_wordl[11:0] | r_t12_datal[11:0];
r_t13_byter <= r_t12_wordr[7:0] | r_t12_datar[7:0];
r_t13_bytel <= r_t12_wordl[7:0] | r_t12_datal[7:0];
r_t13_bwer_d <= r_t12_bwer;
r_t13_bwel_d <= r_t12_bwel;
r_t13_posr_d <= r_t12_bwer ? (|r_t12_posr ? r_t12_posr - 6'h8 : 6'h38) : r_t12_posr;
r_t13_posl_d <= r_t12_bwel ? (&r_t12_posl ? 6'h00 : r_t12_posl + 6'h8) : r_t12_posl;
r_t14_datas <= r_t13_MASK & (c_t13_datasr | c_t13_datasl | r_t13_datas);
// centrifuge pipeline registers
r_t12_inA <= r_t11_inA;
r_t12_inB <= r_t11_inB;
r_t12_mixedr <= c_t11_mixedr;
r_t12_mixedl <= c_t11_mixedl;
r_t12_balr <= c_t11_balr;
r_t12_ball <= c_t11_ball;
r_t13_posr <= c_t12_posr;
r_t13_posl <= c_t12_posl;
r_t13_bwer <= c_t12_posr[3] ^ r_t12_posr[3];
r_t13_bwel <= c_t12_posl[3] ^ r_t12_posl[3];
r_t13_datar <= c_t12_datar;
r_t13_datal <= c_t12_datal;
r_t14_BBop <= r_t13_BBop;
r_t14_wordr <= r_t13_bwer ? {8'b0, r_t13_wordr[11:8] | r_t13_datar[11:8]} : r_t13_wordr[11:0] | r_t13_datar[11:0];
r_t14_wordl <= r_t13_bwel ? {4'b0, r_t13_wordl[11:8] | r_t13_datal[11:8], 4'b0} : r_t13_wordl[11:0] | r_t13_datal[11:0];
r_t14_byter <= r_t13_wordr[7:0] | r_t13_datar[7:0];
r_t14_bytel <= r_t13_wordl[7:0] | r_t13_datal[7:0];
r_t14_bwer_d <= r_t13_bwer;
r_t14_bwel_d <= r_t13_bwel;
r_t14_posr_d <= r_t13_bwer ? (|r_t13_posr ? r_t13_posr - 6'h8 : 6'h38) : r_t13_posr;
r_t14_posl_d <= r_t13_bwel ? (&r_t13_posl ? 6'h00 : r_t13_posl + 6'h8) : r_t13_posl;
r_t15_datas <= r_t14_MASK & (c_t14_datasr | c_t14_datasl | r_t14_datas);
// centrifuge pipeline registers
r_t13_inA <= r_t12_inA;
r_t13_inB <= r_t12_inB;
r_t13_mixedr <= c_t12_mixedr;
r_t13_mixedl <= c_t12_mixedl;
r_t13_balr <= c_t12_balr;
r_t13_ball <= c_t12_ball;
r_t14_posr <= c_t13_posr;
r_t14_posl <= c_t13_posl;
r_t14_bwer <= c_t13_posr[3] ^ r_t13_posr[3];
r_t14_bwel <= c_t13_posl[3] ^ r_t13_posl[3];
r_t14_datar <= c_t13_datar;
r_t14_datal <= c_t13_datal;
r_t15_BBop <= r_t14_BBop;
r_t15_wordr <= r_t14_bwer ? {8'b0, r_t14_wordr[11:8] | r_t14_datar[11:8]} : r_t14_wordr[11:0] | r_t14_datar[11:0];
r_t15_wordl <= r_t14_bwel ? {4'b0, r_t14_wordl[11:8] | r_t14_datal[11:8], 4'b0} : r_t14_wordl[11:0] | r_t14_datal[11:0];
r_t15_byter <= r_t14_wordr[7:0] | r_t14_datar[7:0];
r_t15_bytel <= r_t14_wordl[7:0] | r_t14_datal[7:0];
r_t15_bwer_d <= r_t14_bwer;
r_t15_bwel_d <= r_t14_bwel;
r_t15_posr_d <= r_t14_bwer ? (|r_t14_posr ? r_t14_posr - 6'h8 : 6'h38) : r_t14_posr;
r_t15_posl_d <= r_t14_bwel ? (&r_t14_posl ? 6'h00 : r_t14_posl + 6'h8) : r_t14_posl;
r_t16_datas <= r_t15_MASK & (c_t15_datasr | c_t15_datasl | r_t15_datas);
// centrifuge pipeline registers
r_t14_inA <= r_t13_inA;
r_t14_inB <= r_t13_inB;
r_t14_mixedr <= c_t13_mixedr;
r_t14_mixedl <= c_t13_mixedl;
r_t14_balr <= c_t13_balr;
r_t14_ball <= c_t13_ball;
r_t15_posr <= c_t14_posr;
r_t15_posl <= c_t14_posl;
r_t15_bwer <= c_t14_posr[3] ^ r_t14_posr[3];
r_t15_bwel <= c_t14_posl[3] ^ r_t14_posl[3];
r_t15_datar <= c_t14_datar;
r_t15_datal <= c_t14_datal;
r_t16_BBop <= r_t15_BBop;
r_t16_wordr <= r_t15_bwer ? {8'b0, r_t15_wordr[11:8] | r_t15_datar[11:8]} : r_t15_wordr[11:0] | r_t15_datar[11:0];
r_t16_wordl <= r_t15_bwel ? {4'b0, r_t15_wordl[11:8] | r_t15_datal[11:8], 4'b0} : r_t15_wordl[11:0] | r_t15_datal[11:0];
r_t16_byter <= r_t15_wordr[7:0] | r_t15_datar[7:0];
r_t16_bytel <= r_t15_wordl[7:0] | r_t15_datal[7:0];
r_t16_bwer_d <= r_t15_bwer;
r_t16_bwel_d <= r_t15_bwel;
r_t16_posr_d <= r_t15_bwer ? (|r_t15_posr ? r_t15_posr - 6'h8 : 6'h38) : r_t15_posr;
r_t16_posl_d <= r_t15_bwel ? (&r_t15_posl ? 6'h00 : r_t15_posl + 6'h8) : r_t15_posl;
r_t17_datas <= r_t16_MASK & (c_t16_datasr | c_t16_datasl | r_t16_datas);
// centrifuge pipeline registers
r_t15_inA <= r_t14_inA;
r_t15_inB <= r_t14_inB;
r_t15_mixedr <= c_t14_mixedr;
r_t15_mixedl <= c_t14_mixedl;
r_t15_balr <= c_t14_balr;
r_t15_ball <= c_t14_ball;
r_t16_posr <= c_t15_posr;
r_t16_posl <= c_t15_posl;
r_t16_bwer <= c_t15_posr[3] ^ r_t15_posr[3];
r_t16_bwel <= c_t15_posl[3] ^ r_t15_posl[3];
r_t16_datar <= c_t15_datar;
r_t16_datal <= c_t15_datal;
r_t17_BBop <= r_t16_BBop;
r_t17_wordr <= r_t16_bwer ? {8'b0, r_t16_wordr[11:8] | r_t16_datar[11:8]} : r_t16_wordr[11:0] | r_t16_datar[11:0];
r_t17_wordl <= r_t16_bwel ? {4'b0, r_t16_wordl[11:8] | r_t16_datal[11:8], 4'b0} : r_t16_wordl[11:0] | r_t16_datal[11:0];
r_t17_byter <= r_t16_wordr[7:0] | r_t16_datar[7:0];
r_t17_bytel <= r_t16_wordl[7:0] | r_t16_datal[7:0];
r_t17_bwer_d <= r_t16_bwer;
r_t17_bwel_d <= r_t16_bwel;
r_t17_posr_d <= r_t16_bwer ? (|r_t16_posr ? r_t16_posr - 6'h8 : 6'h38) : r_t16_posr;
r_t17_posl_d <= r_t16_bwel ? (&r_t16_posl ? 6'h00 : r_t16_posl + 6'h8) : r_t16_posl;
r_t18_datas <= r_t17_MASK & (c_t17_datasr | c_t17_datasl | r_t17_datas);
// centrifuge pipeline registers
r_t16_inA <= r_t15_inA;
r_t16_inB <= r_t15_inB;
r_t16_mixedr <= c_t15_mixedr;
r_t16_mixedl <= c_t15_mixedl;
r_t16_balr <= c_t15_balr;
r_t16_ball <= c_t15_ball;
r_t17_posr <= c_t16_posr;
r_t17_posl <= c_t16_posl;
r_t17_bwer <= c_t16_posr[3] ^ r_t16_posr[3];
r_t17_bwel <= c_t16_posl[3] ^ r_t16_posl[3];
r_t17_datar <= c_t16_datar;
r_t17_datal <= c_t16_datal;
r_t18_BBop <= r_t17_BBop;
r_t18_wordr <= r_t17_bwer ? {8'b0, r_t17_wordr[11:8] | r_t17_datar[11:8]} : r_t17_wordr[11:0] | r_t17_datar[11:0];
r_t18_wordl <= r_t17_bwel ? {4'b0, r_t17_wordl[11:8] | r_t17_datal[11:8], 4'b0} : r_t17_wordl[11:0] | r_t17_datal[11:0];
r_t18_byter <= r_t17_wordr[7:0] | r_t17_datar[7:0];
r_t18_bytel <= r_t17_wordl[7:0] | r_t17_datal[7:0];
r_t18_bwer_d <= r_t17_bwer;
r_t18_bwel_d <= r_t17_bwel;
r_t18_posr_d <= r_t17_bwer ? (|r_t17_posr ? r_t17_posr - 6'h8 : 6'h38) : r_t17_posr;
r_t18_posl_d <= r_t17_bwel ? (&r_t17_posl ? 6'h00 : r_t17_posl + 6'h8) : r_t17_posl;
r_t19_datas <= r_t18_MASK & (c_t18_datasr | c_t18_datasl | r_t18_datas);
// centrifuge pipeline registers
r_t17_inA <= r_t16_inA;
r_t17_inB <= r_t16_inB;
r_t17_mixedr <= c_t16_mixedr;
r_t17_mixedl <= c_t16_mixedl;
r_t17_balr <= c_t16_balr;
r_t17_ball <= c_t16_ball;
r_t18_posr <= c_t17_posr;
r_t18_posl <= c_t17_posl;
r_t18_bwer <= c_t17_posr[3] ^ r_t17_posr[3];
r_t18_bwel <= c_t17_posl[3] ^ r_t17_posl[3];
r_t18_datar <= c_t17_datar;
r_t18_datal <= c_t17_datal;
r_t19_BBop <= r_t18_BBop;
r_t19_wordr <= r_t18_bwer ? {8'b0, r_t18_wordr[11:8] | r_t18_datar[11:8]} : r_t18_wordr[11:0] | r_t18_datar[11:0];
r_t19_wordl <= r_t18_bwel ? {4'b0, r_t18_wordl[11:8] | r_t18_datal[11:8], 4'b0} : r_t18_wordl[11:0] | r_t18_datal[11:0];
r_t19_byter <= r_t18_wordr[7:0] | r_t18_datar[7:0];
r_t19_bytel <= r_t18_wordl[7:0] | r_t18_datal[7:0];
r_t19_bwer_d <= r_t18_bwer;
r_t19_bwel_d <= r_t18_bwel;
r_t19_posr_d <= r_t18_bwer ? (|r_t18_posr ? r_t18_posr - 6'h8 : 6'h38) : r_t18_posr;
r_t19_posl_d <= r_t18_bwel ? (&r_t18_posl ? 6'h00 : r_t18_posl + 6'h8) : r_t18_posl;
r_t20_datas <= r_t19_MASK & (c_t19_datasr | c_t19_datasl | r_t19_datas);
// centrifuge pipeline registers
r_t18_inA <= r_t17_inA;
r_t18_inB <= r_t17_inB;
r_t18_mixedr <= c_t17_mixedr;
r_t18_mixedl <= c_t17_mixedl;
r_t18_balr <= c_t17_balr;
r_t18_ball <= c_t17_ball;
r_t19_posr <= c_t18_posr;
r_t19_posl <= c_t18_posl;
r_t19_bwer <= c_t18_posr[3] ^ r_t18_posr[3];
r_t19_bwel <= c_t18_posl[3] ^ r_t18_posl[3];
r_t19_datar <= c_t18_datar;
r_t19_datal <= c_t18_datal;
r_t20_BBop <= r_t19_BBop;
r_t20_wordr <= r_t19_bwer ? {8'b0, r_t19_wordr[11:8] | r_t19_datar[11:8]} : r_t19_wordr[11:0] | r_t19_datar[11:0];
r_t20_wordl <= r_t19_bwel ? {4'b0, r_t19_wordl[11:8] | r_t19_datal[11:8], 4'b0} : r_t19_wordl[11:0] | r_t19_datal[11:0];
r_t20_byter <= r_t19_wordr[7:0] | r_t19_datar[7:0];
r_t20_bytel <= r_t19_wordl[7:0] | r_t19_datal[7:0];
r_t20_bwer_d <= r_t19_bwer;
r_t20_bwel_d <= r_t19_bwel;
r_t20_posr_d <= r_t19_bwer ? (|r_t19_posr ? r_t19_posr - 6'h8 : 6'h38) : r_t19_posr;
r_t20_posl_d <= r_t19_bwel ? (&r_t19_posl ? 6'h00 : r_t19_posl + 6'h8) : r_t19_posl;
r_t21_datas <= r_t20_MASK & (c_t20_datasr | c_t20_datasl | r_t20_datas);
// centrifuge pipeline registers
r_t19_inA <= r_t18_inA;
r_t19_inB <= r_t18_inB;
r_t19_mixedr <= c_t18_mixedr;
r_t19_mixedl <= c_t18_mixedl;
r_t19_balr <= c_t18_balr;
r_t19_ball <= c_t18_ball;
r_t20_posr <= c_t19_posr;
r_t20_posl <= c_t19_posl;
r_t20_bwer <= c_t19_posr[3] ^ r_t19_posr[3];
r_t20_bwel <= c_t19_posl[3] ^ r_t19_posl[3];
r_t20_datar <= c_t19_datar;
r_t20_datal <= c_t19_datal;
r_t21_BBop <= r_t20_BBop;
r_t21_wordr <= {8'b0, r_t20_wordr[11:8] | r_t20_datar[11:8]};
r_t21_wordl <= {4'b0, r_t20_wordl[11:8] | r_t20_datal[11:8], 4'b0};
r_t21_byter <= r_t20_wordr[7:0] | r_t20_datar[7:0];
r_t21_bytel <= r_t20_wordl[7:0] | r_t20_datal[7:0];
r_t21_bwer_d <= r_t20_bwer;
r_t21_bwel_d <= r_t20_bwel;
r_t21_posr_d <= r_t20_bwer ? (|r_t20_posr ? r_t20_posr - 6'h8 : 6'h38) : r_t20_posr;
r_t21_posl_d <= r_t20_bwel ? (&r_t20_posl ? 6'h00 : r_t20_posl + 6'h8) : r_t20_posl;
r_t22_datas <= r_t21_MASK & (c_t21_datasr | c_t21_datasl | r_t21_datas);
r_t20_pos_ovr <= c_t19_pos_ovr;
r_t20_inA <= r_t19_inA;
r_t21_inA <= r_t20_inA;
r_t21_popc <= 7'h40 - {r_t20_pos_ovr,r_t20_posr};
// r_t22_popc <= {57'b0, r_t21_popc} + r_t21_inA;
r_t22_popc_l <= {26'b0, r_t21_popc} + {1'b0,r_t21_inA[31:0]};
r_t22_popc_u0 <= r_t21_inA[63:32];
r_t22_popc_u1 <= r_t21_inA[63:32] + 32'b1;
r_t22_posr_d <= |r_t21_posr_d ? r_t21_posr_d + 6'h8 : 6'h38;
r_t22_posl_d <= &r_t21_posl_d ? 6'h00 : r_t21_posl_d - 6'h8;
r_t22_byter <= r_t21_wordr[7:0];
r_t22_bytel <= r_t21_wordl[7:0];
r_t22_BBop <= r_t21_BBop;
r_t23_datas <= r_t22_BBop ? {r_t22_popc_l[32] ? r_t22_popc_u1 : r_t22_popc_u0, r_t22_popc_l[31:0]} : r_t22_MASK & (c_t22_datasr | c_t22_datasl | r_t22_datas);
r_t24_cfuge_out <= r_t23_datas;
end
/* ---------- debug & synopsys off blocks ---------- */
endmodule // bbox_box_top
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.58f
// \ \ Application: netgen
// / / Filename: gt_float_float_bool.v
// /___/ /\ Timestamp: Wed Jan 27 16:23:18 2016
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/jhegarty/lol/ipcore_dir/tmp/_cg/gt_float_float_bool.ngc /home/jhegarty/lol/ipcore_dir/tmp/_cg/gt_float_float_bool.v
// Device : 7z100ffg900-2
// Input file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/gt_float_float_bool.ngc
// Output file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/gt_float_float_bool.v
// # of Modules : 1
// Design Name : gt_float_float_bool
// Xilinx : /opt/Xilinx/14.5/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module gt_float32_float32_bool (
CLK, ce, inp, out
);
parameter INSTANCE_NAME="INST";
input wire CLK;
input wire ce;
input [63 : 0] inp;
output [0:0] out;
wire clk;
assign clk=CLK;
wire [31:0] a;
wire [31:0] b;
wire [0:0] result;
assign a = inp[31:0];
assign b = inp[63:32];
assign out = result;
wire \U0/op_inst/FLT_PT_OP/COMP_OP.SPD.OP/MET_REG/RTL.delay<0>_0 ;
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
assign
result[0] = \U0/op_inst/FLT_PT_OP/COMP_OP.SPD.OP/MET_REG/RTL.delay<0>_0 ;
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig00000002)
);
FDE #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.CE(ce),
.D(sig00000006),
.Q(sig00000019)
);
MUXCY blk00000004 (
.CI(sig00000007),
.DI(sig00000002),
.S(sig00000003),
.O(sig00000006)
);
MUXCY blk00000005 (
.CI(sig00000008),
.DI(sig00000002),
.S(sig00000005),
.O(sig00000007)
);
MUXCY blk00000006 (
.CI(sig00000001),
.DI(sig00000002),
.S(sig00000004),
.O(sig00000008)
);
MUXCY blk00000007 (
.CI(sig00000016),
.DI(sig00000002),
.S(sig00000010),
.O(sig00000009)
);
MUXCY blk00000008 (
.CI(sig00000009),
.DI(sig00000002),
.S(sig0000000f),
.O(sig0000000a)
);
MUXCY blk00000009 (
.CI(sig00000018),
.DI(sig00000002),
.S(sig0000000e),
.O(sig0000000b)
);
MUXCY blk0000000a (
.CI(sig0000000b),
.DI(sig00000002),
.S(sig0000000d),
.O(sig0000000c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000b (
.C(clk),
.CE(ce),
.D(sig00000012),
.Q(sig00000013)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000c (
.C(clk),
.CE(ce),
.D(sig00000011),
.Q(\U0/op_inst/FLT_PT_OP/COMP_OP.SPD.OP/MET_REG/RTL.delay<0>_0 )
);
FDE #(
.INIT ( 1'b0 ))
blk0000000d (
.C(clk),
.CE(ce),
.D(sig0000000a),
.Q(sig00000015)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000e (
.C(clk),
.CE(ce),
.D(sig0000000c),
.Q(sig00000017)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000f (
.C(clk),
.CE(ce),
.D(sig00000001),
.Q(sig0000001a)
);
MUXCY blk00000010 (
.CI(sig00000028),
.DI(sig00000002),
.S(sig0000001c),
.O(sig00000027)
);
MUXCY blk00000011 (
.CI(sig00000029),
.DI(sig00000002),
.S(sig0000001d),
.O(sig00000028)
);
MUXCY blk00000012 (
.CI(sig0000002a),
.DI(sig00000002),
.S(sig0000001e),
.O(sig00000029)
);
MUXCY blk00000013 (
.CI(sig0000002b),
.DI(sig00000002),
.S(sig0000001f),
.O(sig0000002a)
);
MUXCY blk00000014 (
.CI(sig0000002c),
.DI(sig00000002),
.S(sig00000020),
.O(sig0000002b)
);
MUXCY blk00000015 (
.CI(sig0000002d),
.DI(sig00000002),
.S(sig00000021),
.O(sig0000002c)
);
MUXCY blk00000016 (
.CI(sig0000002e),
.DI(sig00000002),
.S(sig00000022),
.O(sig0000002d)
);
MUXCY blk00000017 (
.CI(sig0000002f),
.DI(sig00000002),
.S(sig00000023),
.O(sig0000002e)
);
MUXCY blk00000018 (
.CI(sig00000030),
.DI(sig00000002),
.S(sig00000024),
.O(sig0000002f)
);
MUXCY blk00000019 (
.CI(sig00000031),
.DI(sig00000002),
.S(sig00000025),
.O(sig00000030)
);
MUXCY blk0000001a (
.CI(sig00000001),
.DI(sig00000002),
.S(sig00000026),
.O(sig00000031)
);
FDE #(
.INIT ( 1'b0 ))
blk0000001b (
.C(clk),
.CE(ce),
.D(sig00000027),
.Q(sig0000001b)
);
MUXCY blk0000001c (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000037),
.O(sig00000032)
);
MUXCY blk0000001d (
.CI(sig00000032),
.DI(sig00000001),
.S(sig00000036),
.O(sig00000033)
);
MUXCY blk0000001e (
.CI(sig00000033),
.DI(sig00000001),
.S(sig00000035),
.O(sig00000034)
);
MUXCY blk0000001f (
.CI(sig00000034),
.DI(sig00000001),
.S(sig00000038),
.O(sig00000016)
);
MUXCY blk00000020 (
.CI(sig00000002),
.DI(sig00000001),
.S(sig0000003e),
.O(sig00000039)
);
MUXCY blk00000021 (
.CI(sig00000039),
.DI(sig00000001),
.S(sig0000003d),
.O(sig0000003a)
);
MUXCY blk00000022 (
.CI(sig0000003a),
.DI(sig00000001),
.S(sig0000003c),
.O(sig0000003b)
);
MUXCY blk00000023 (
.CI(sig0000003b),
.DI(sig00000001),
.S(sig0000003f),
.O(sig00000018)
);
MUXCY blk00000024 (
.CI(sig00000061),
.DI(sig00000040),
.S(sig00000041),
.O(sig00000060)
);
MUXCY blk00000025 (
.CI(sig00000062),
.DI(sig00000042),
.S(sig00000043),
.O(sig00000061)
);
MUXCY blk00000026 (
.CI(sig00000063),
.DI(sig00000044),
.S(sig00000045),
.O(sig00000062)
);
MUXCY blk00000027 (
.CI(sig00000064),
.DI(sig00000046),
.S(sig00000047),
.O(sig00000063)
);
MUXCY blk00000028 (
.CI(sig00000065),
.DI(sig00000048),
.S(sig00000049),
.O(sig00000064)
);
MUXCY blk00000029 (
.CI(sig00000066),
.DI(sig0000004a),
.S(sig0000004b),
.O(sig00000065)
);
MUXCY blk0000002a (
.CI(sig00000067),
.DI(sig0000004c),
.S(sig0000004d),
.O(sig00000066)
);
MUXCY blk0000002b (
.CI(sig00000068),
.DI(sig0000004e),
.S(sig0000004f),
.O(sig00000067)
);
MUXCY blk0000002c (
.CI(sig00000069),
.DI(sig00000050),
.S(sig00000051),
.O(sig00000068)
);
MUXCY blk0000002d (
.CI(sig0000006a),
.DI(sig00000052),
.S(sig00000053),
.O(sig00000069)
);
MUXCY blk0000002e (
.CI(sig0000006b),
.DI(sig00000054),
.S(sig00000055),
.O(sig0000006a)
);
MUXCY blk0000002f (
.CI(sig0000006c),
.DI(sig00000056),
.S(sig00000057),
.O(sig0000006b)
);
MUXCY blk00000030 (
.CI(sig0000006d),
.DI(sig00000058),
.S(sig00000059),
.O(sig0000006c)
);
MUXCY blk00000031 (
.CI(sig0000006e),
.DI(sig0000005a),
.S(sig0000005b),
.O(sig0000006d)
);
MUXCY blk00000032 (
.CI(sig0000006f),
.DI(sig0000005c),
.S(sig0000005d),
.O(sig0000006e)
);
MUXCY blk00000033 (
.CI(sig00000002),
.DI(sig0000005e),
.S(sig0000005f),
.O(sig0000006f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000034 (
.C(clk),
.CE(ce),
.D(sig00000060),
.Q(sig00000014)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000035 (
.I0(a[27]),
.I1(a[28]),
.I2(a[29]),
.I3(a[30]),
.O(sig00000003)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000036 (
.I0(b[23]),
.I1(b[24]),
.I2(b[25]),
.I3(b[26]),
.I4(b[27]),
.I5(b[28]),
.O(sig00000004)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000037 (
.I0(b[29]),
.I1(b[30]),
.I2(a[23]),
.I3(a[24]),
.I4(a[25]),
.I5(a[26]),
.O(sig00000005)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000038 (
.I0(a[29]),
.I1(a[30]),
.O(sig0000000d)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000039 (
.I0(a[23]),
.I1(a[24]),
.I2(a[25]),
.I3(a[26]),
.I4(a[27]),
.I5(a[28]),
.O(sig0000000e)
);
LUT2 #(
.INIT ( 4'h8 ))
blk0000003a (
.I0(b[29]),
.I1(b[30]),
.O(sig0000000f)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk0000003b (
.I0(b[23]),
.I1(b[24]),
.I2(b[25]),
.I3(b[26]),
.I4(b[27]),
.I5(b[28]),
.O(sig00000010)
);
LUT2 #(
.INIT ( 4'h8 ))
blk0000003c (
.I0(a[31]),
.I1(b[31]),
.O(sig00000012)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000003d (
.I0(a[27]),
.I1(b[27]),
.I2(a[29]),
.I3(b[29]),
.I4(a[28]),
.I5(b[28]),
.O(sig0000001d)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000003e (
.I0(a[24]),
.I1(b[24]),
.I2(a[26]),
.I3(b[26]),
.I4(a[25]),
.I5(b[25]),
.O(sig0000001e)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000003f (
.I0(a[21]),
.I1(b[21]),
.I2(a[23]),
.I3(b[23]),
.I4(a[22]),
.I5(b[22]),
.O(sig0000001f)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000040 (
.I0(a[18]),
.I1(b[18]),
.I2(a[20]),
.I3(b[20]),
.I4(a[19]),
.I5(b[19]),
.O(sig00000020)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000041 (
.I0(a[15]),
.I1(b[15]),
.I2(a[17]),
.I3(b[17]),
.I4(a[16]),
.I5(b[16]),
.O(sig00000021)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000042 (
.I0(a[12]),
.I1(b[12]),
.I2(a[14]),
.I3(b[14]),
.I4(a[13]),
.I5(b[13]),
.O(sig00000022)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000043 (
.I0(a[10]),
.I1(b[10]),
.I2(a[9]),
.I3(b[9]),
.I4(a[11]),
.I5(b[11]),
.O(sig00000023)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000044 (
.I0(a[6]),
.I1(b[6]),
.I2(a[8]),
.I3(b[8]),
.I4(a[7]),
.I5(b[7]),
.O(sig00000024)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000045 (
.I0(a[3]),
.I1(b[3]),
.I2(a[5]),
.I3(b[5]),
.I4(a[4]),
.I5(b[4]),
.O(sig00000025)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000046 (
.I0(a[31]),
.I1(b[31]),
.I2(a[30]),
.I3(b[30]),
.O(sig0000001c)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000047 (
.I0(a[0]),
.I1(b[0]),
.I2(a[2]),
.I3(b[2]),
.I4(a[1]),
.I5(b[1]),
.O(sig00000026)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000048 (
.I0(b[12]),
.I1(b[13]),
.I2(b[14]),
.I3(b[15]),
.I4(b[16]),
.I5(b[17]),
.O(sig00000035)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000049 (
.I0(b[6]),
.I1(b[7]),
.I2(b[8]),
.I3(b[9]),
.I4(b[10]),
.I5(b[11]),
.O(sig00000036)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004a (
.I0(b[0]),
.I1(b[1]),
.I2(b[2]),
.I3(b[3]),
.I4(b[4]),
.I5(b[5]),
.O(sig00000037)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk0000004b (
.I0(b[18]),
.I1(b[19]),
.I2(b[20]),
.I3(b[21]),
.I4(b[22]),
.O(sig00000038)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004c (
.I0(a[12]),
.I1(a[13]),
.I2(a[14]),
.I3(a[15]),
.I4(a[16]),
.I5(a[17]),
.O(sig0000003c)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004d (
.I0(a[6]),
.I1(a[7]),
.I2(a[8]),
.I3(a[9]),
.I4(a[10]),
.I5(a[11]),
.O(sig0000003d)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004e (
.I0(a[0]),
.I1(a[1]),
.I2(a[2]),
.I3(a[3]),
.I4(a[4]),
.I5(a[5]),
.O(sig0000003e)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk0000004f (
.I0(a[18]),
.I1(a[19]),
.I2(a[20]),
.I3(a[21]),
.I4(a[22]),
.O(sig0000003f)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000050 (
.I0(a[19]),
.I1(b[19]),
.I2(a[18]),
.I3(b[18]),
.O(sig0000004d)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000051 (
.I0(a[17]),
.I1(b[17]),
.I2(a[16]),
.I3(b[16]),
.O(sig0000004f)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000052 (
.I0(a[15]),
.I1(b[15]),
.I2(a[14]),
.I3(b[14]),
.O(sig00000051)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000053 (
.I0(a[13]),
.I1(b[13]),
.I2(a[12]),
.I3(b[12]),
.O(sig00000053)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000054 (
.I0(a[11]),
.I1(b[11]),
.I2(a[10]),
.I3(b[10]),
.O(sig00000055)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000055 (
.I0(a[9]),
.I1(b[9]),
.I2(a[8]),
.I3(b[8]),
.O(sig00000057)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000056 (
.I0(a[7]),
.I1(b[7]),
.I2(a[6]),
.I3(b[6]),
.O(sig00000059)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000057 (
.I0(a[5]),
.I1(b[5]),
.I2(a[4]),
.I3(b[4]),
.O(sig0000005b)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000058 (
.I0(a[3]),
.I1(b[3]),
.I2(a[2]),
.I3(b[2]),
.O(sig0000005d)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000059 (
.I0(a[31]),
.I1(b[31]),
.I2(a[30]),
.I3(b[30]),
.O(sig00000041)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005a (
.I0(a[29]),
.I1(b[29]),
.I2(a[28]),
.I3(b[28]),
.O(sig00000043)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005b (
.I0(a[27]),
.I1(b[27]),
.I2(a[26]),
.I3(b[26]),
.O(sig00000045)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005c (
.I0(a[25]),
.I1(b[25]),
.I2(a[24]),
.I3(b[24]),
.O(sig00000047)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005d (
.I0(a[23]),
.I1(b[23]),
.I2(a[22]),
.I3(b[22]),
.O(sig00000049)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005e (
.I0(a[21]),
.I1(b[21]),
.I2(a[20]),
.I3(b[20]),
.O(sig0000004b)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005f (
.I0(a[1]),
.I1(b[1]),
.I2(a[0]),
.I3(b[0]),
.O(sig0000005f)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000060 (
.I0(a[31]),
.I1(b[31]),
.I2(a[30]),
.I3(b[30]),
.O(sig00000040)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000061 (
.I0(b[29]),
.I1(a[29]),
.I2(a[28]),
.I3(b[28]),
.O(sig00000042)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000062 (
.I0(b[27]),
.I1(a[27]),
.I2(a[26]),
.I3(b[26]),
.O(sig00000044)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000063 (
.I0(b[25]),
.I1(a[25]),
.I2(a[24]),
.I3(b[24]),
.O(sig00000046)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000064 (
.I0(b[23]),
.I1(a[23]),
.I2(a[22]),
.I3(b[22]),
.O(sig00000048)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000065 (
.I0(b[21]),
.I1(a[21]),
.I2(a[20]),
.I3(b[20]),
.O(sig0000004a)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000066 (
.I0(b[19]),
.I1(a[19]),
.I2(a[18]),
.I3(b[18]),
.O(sig0000004c)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000067 (
.I0(b[17]),
.I1(a[17]),
.I2(a[16]),
.I3(b[16]),
.O(sig0000004e)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000068 (
.I0(b[15]),
.I1(a[15]),
.I2(a[14]),
.I3(b[14]),
.O(sig00000050)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000069 (
.I0(b[13]),
.I1(a[13]),
.I2(a[12]),
.I3(b[12]),
.O(sig00000052)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006a (
.I0(b[11]),
.I1(a[11]),
.I2(a[10]),
.I3(b[10]),
.O(sig00000054)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006b (
.I0(b[9]),
.I1(a[9]),
.I2(a[8]),
.I3(b[8]),
.O(sig00000056)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006c (
.I0(b[7]),
.I1(a[7]),
.I2(a[6]),
.I3(b[6]),
.O(sig00000058)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006d (
.I0(b[5]),
.I1(a[5]),
.I2(a[4]),
.I3(b[4]),
.O(sig0000005a)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006e (
.I0(b[3]),
.I1(a[3]),
.I2(a[2]),
.I3(b[2]),
.O(sig0000005c)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006f (
.I0(b[1]),
.I1(a[1]),
.I2(a[0]),
.I3(b[0]),
.O(sig0000005e)
);
LUT2 #(
.INIT ( 4'h1 ))
blk00000070 (
.I0(sig00000015),
.I1(sig00000017),
.O(sig00000070)
);
LUT6 #(
.INIT ( 64'h001C00000000FFFF ))
blk00000071 (
.I0(sig0000001b),
.I1(sig00000014),
.I2(sig00000013),
.I3(sig00000019),
.I4(sig0000001a),
.I5(sig00000070),
.O(sig00000011)
);
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Gameover.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Gameover (
address,
clock,
q);
input [11:0] address;
input clock;
output [2:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "Gameover.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2400"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "3"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "Gameover.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2400"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 3 0 @q_a 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DFBBP_BEHAVIORAL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBP_BEHAVIORAL_V |
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
Debug Logic State Analyzer
Addr
0x000 : Control/Status
0x004 : Live Input Data
0x008 :
(...) : [Sample data, one per 'lsa_clk' with all 32-bits of input data]
0xFFF :
Control -
[0] Arm Trigger
[1] Force Trigger (Arm must also be set)
[2] Sample Done
[3] Sample Running
[7-4] RESERVED
[15-8] Mode (to debug target to select data/trigger settings)
[31-16] RESERVED
*/
module debug_lsa
(
input av_clk,
input av_rst,
input [9:0] av_address,
input av_write,
input av_read,
input [31:0] av_writedata,
output reg [31:0] av_readdata,
output reg av_readdatavalid,
output reg [7:0] lsa_mode,
input lsa_clk,
input lsa_trigger,
input [31:0] lsa_data
);
parameter INIT_ARMED = 1;
parameter INIT_FORCED = 0;
parameter INIT_MODE = 8'd0;
//
// Clock domain crossing
//
reg [1:0] sync_av;
reg [1:0] sync_lsa;
reg [1:0] sync_lsa_av;
reg ctrl_arm;
reg av_arm;
reg lsa_arm;
reg ctrl_force;
reg av_force;
reg lsa_force;
reg [7:0] ctrl_mode;
reg [7:0] av_mode;
// lsa_mode in port list
reg sample_done;
reg av_done;
reg lsa_done;
wire sample_running;
reg av_running;
reg lsa_running;
wire [31:0] sample_live = lsa_data;
reg [31:0] av_live;
reg [31:0] lsa_live;
always @ (posedge av_clk or posedge av_rst)
if (av_rst)
begin
sync_lsa_av <= 2'd0;
sync_av <= 2'd0;
end
else
begin
sync_lsa_av <= sync_lsa;
sync_av <= (sync_lsa_av == sync_av) ? sync_av + 2'd1 : sync_av;
end
always @ (posedge lsa_clk)
sync_lsa <= sync_av;
always @ (posedge av_clk)
if (sync_av == 2'b01)
{av_live, av_running, av_done, av_mode, av_force, av_arm} <=
{lsa_live, lsa_running, lsa_done, ctrl_mode, ctrl_force, ctrl_arm};
always @ (posedge lsa_clk)
if (sync_lsa == 2'b10)
{lsa_live, lsa_running, lsa_done, lsa_mode, lsa_force, lsa_arm} <=
{sample_live, sample_running, sample_done, av_mode, av_force, av_arm};
//
// Sample state machine
//
reg [10:0] sample_waddr;
assign sample_running = sample_waddr[10];
reg [31:0] sample_data[1023:0];
always @ (posedge lsa_clk)
sample_done <= lsa_arm && (sample_waddr == 11'h000);
always @ (posedge lsa_clk)
if (!lsa_arm)
sample_waddr <= 11'h001;
else if (!sample_waddr[10] && |sample_waddr[9:0])
sample_waddr <= sample_waddr + 11'd1;
else if (sample_waddr == 11'h400)
sample_waddr <= (lsa_force || lsa_trigger) ? 11'h401 : 11'h400;
else if (sample_waddr != 11'h000)
sample_waddr <= sample_waddr + 10'd1;
always @ (posedge lsa_clk)
if (lsa_arm)
sample_data[sample_waddr[9:0]] <= (sample_waddr[10]) ? lsa_data : 32'd0;
//
// Control register
//
reg init_cycle;
always @ (posedge av_clk or posedge av_rst)
if (av_rst)
begin
ctrl_arm <= 1'b0;
ctrl_force <= 1'b0;
ctrl_mode <= 8'd0;
init_cycle <= 1'b0;
end
else if (!init_cycle)
begin
ctrl_arm <= (INIT_ARMED != 0);
ctrl_force <= (INIT_FORCED != 0);
ctrl_mode <= INIT_MODE;
init_cycle <= 1'b1;
end
else if (av_write && (av_address == 10'd0))
begin
ctrl_arm <= av_writedata[0];
ctrl_force <= av_writedata[1];
ctrl_mode <= av_writedata[15:8];
end
always @ (posedge av_clk)
av_readdatavalid <= av_read;
always @ (posedge av_clk)
if (av_address == 10'd0)
av_readdata <= {16'd0, ctrl_mode, 4'd0, av_running, av_done, ctrl_force, ctrl_arm};
else if (av_address == 10'd1)
av_readdata <= av_live;
else
av_readdata <= sample_data[av_address];
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAM16_s36_s36_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RAM16_s36_s36_altera (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] q_a = sub_wire0[31:0];
wire [31:0] q_b = sub_wire1[31:0];
altsyncram altsyncram_component (
.clock0 (clock_a),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (clock_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Stratix II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_wave*.jpg TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:34:18 10/12/2013
// Design Name:
// Module Name: Logica_Bola
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Logica_Bola(
input clock,
input reset,
input actualizar_posicion,
input revisar_bordes,
input choque_barra,
output reg [9:0] ball_x,
output reg [8:0] ball_y );
reg dir_x_positiva;
reg dir_y_positiva;
initial
begin
dir_x_positiva <= 1'b1;
dir_y_positiva <= 1'b1;
ball_x <= `X_INICIAL_BOLA;
ball_y <= `Y_INICIAL_BOLA;
end
always @(posedge clock or posedge reset)
begin
if(reset)
begin
dir_x_positiva <= 1'b1;
dir_y_positiva <= 1'b1;
ball_x <= `X_INICIAL_BOLA;
ball_y <= `Y_INICIAL_BOLA;
end
else
begin
if(actualizar_posicion)
begin
if(dir_x_positiva)
ball_x <= ball_x + `VELOCIDAD_BOLA; //Hacia derecha
else
ball_x <= ball_x - `VELOCIDAD_BOLA; //Hacia izquierda
if(dir_y_positiva)
ball_y <= ball_y + `VELOCIDAD_BOLA; //Hacia abajo
else
ball_y <= ball_y - `VELOCIDAD_BOLA; //Hacia arriba
end
if(revisar_bordes)
begin
if ( ball_x > `LIMITE_DER_X_BOLA )
begin
ball_x <= `LIMITE_DER_X_BOLA;
dir_x_positiva <= 1'b0;
end
else if(choque_barra)
begin
ball_x <= `X_INICIAL_BARRA + `ANCHO_BARRA;
dir_x_positiva <= 1'b1;
end
else
begin
ball_x <= ball_x;
dir_x_positiva <= dir_x_positiva;
end
if( ball_y < `LIMITE_SUP_Y_BOLA )
begin
ball_y <= `LIMITE_SUP_Y_BOLA;
dir_y_positiva <= 1'b1;
end
else if( ball_y > `LIMITE_INF_Y_BOLA )
begin
ball_y <= `LIMITE_INF_Y_BOLA;
dir_y_positiva <= 1'b0;
end
else
begin
ball_y <= ball_y;
dir_y_positiva <= dir_y_positiva;
end
end
end /** Fin else NO reset */
end /** Fin always */
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module mi_nios_SW (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 3: 0] in_port;
input reset_n;
wire clk_en;
wire [ 3: 0] data_in;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
//--------------------------------------------------------------------------------
// controller.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Controls the capturing & readback operation.
//
// If no other operation has been activated, the controller samples data
// into the memory. When the run signal is received, it continues to do so
// for fwd * 4 samples and then sends bwd * 4 samples to the transmitter.
// This allows to capture data from before the trigger match which is a nice
// feature.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module controller (
input wire clock,
input wire reset,
input wire run,
input wire wrSize,
input wire [31:0] config_data,
input wire validIn,
input wire [31:0] dataIn,
input wire busy,
input wire arm,
// outputs...
output reg send,
output reg [31:0] memoryWrData,
output reg memoryRead,
output reg memoryWrite,
output reg memoryLastWrite
);
reg [15:0] fwd; // Config registers...
reg [15:0] bwd;
reg next_send;
reg next_memoryRead;
reg next_memoryWrite;
reg next_memoryLastWrite;
reg [17:0] counter, next_counter;
wire [17:0] counter_inc = counter+1'b1;
always @(posedge clock)
memoryWrData <= dataIn;
//
// Control FSM...
//
localparam [2:0]
IDLE = 3'h0,
SAMPLE = 3'h1,
DELAY = 3'h2,
READ = 3'h3,
READWAIT = 3'h4;
reg [2:0] state, next_state;
initial state = IDLE;
always @(posedge clock, posedge reset)
if (reset) begin
state <= IDLE;
memoryWrite <= 1'b0;
memoryLastWrite <= 1'b0;
memoryRead <= 1'b0;
end else begin
state <= next_state;
memoryWrite <= next_memoryWrite;
memoryLastWrite <= next_memoryLastWrite;
memoryRead <= next_memoryRead;
end
always @(posedge clock)
begin
counter <= next_counter;
send <= next_send;
end
// FSM to control the controller action
always @*
begin
next_state = state;
next_counter = counter;
next_memoryWrite = 1'b0;
next_memoryLastWrite = 1'b0;
next_memoryRead = 1'b0;
next_send = 1'b0;
case(state)
IDLE :
begin
next_counter = 0;
next_memoryWrite = 1;
if (run) next_state = DELAY;
else if (arm) next_state = SAMPLE;
end
// default mode: write data samples to memory
SAMPLE :
begin
next_counter = 0;
next_memoryWrite = validIn;
if (run) next_state = DELAY;
end
// keep sampling for 4 * fwd + 4 samples after run condition
DELAY :
begin
if (validIn)
begin
next_memoryWrite = 1'b1;
next_counter = counter_inc;
if (counter == {fwd,2'b11}) // IED - Evaluate only on validIn to make behavior
begin // match between sampling on all-clocks verses occasionally.
next_memoryLastWrite = 1'b1; // Added LastWrite flag to simplify write->read memory handling.
next_counter = 0;
next_state = READ;
end
end
end
// read back 4 * bwd + 4 samples after DELAY
// go into wait state after each sample to give transmitter time
READ :
begin
next_memoryRead = 1'b1;
next_send = 1'b1;
if (counter == {bwd,2'b11})
begin
next_counter = 0;
next_state = IDLE;
end
else
begin
next_counter = counter_inc;
next_state = READWAIT;
end
end
// wait for the transmitter to become ready again
READWAIT :
begin
if (!busy && !send) next_state = READ;
end
endcase
end
//
// Set speed and size registers if indicated...
//
always @(posedge clock)
if (wrSize) {fwd, bwd} <= config_data[31:0];
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: scdata_subbank.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module scdata_subbank(/*AUTOARG*/
// Outputs
scdata_scbuf_decc_c6_top_buf,
scdata_scbuf_decc_c6_bot_buf, scbuf_scdata_fbdecc_top_buf,
scbuf_scdata_fbdecc_bot_buf, l2d_fuse_data_out,
decc_out, se_buf, so,
// Inputs
wr_en, word_en, set, sehold, se, scdata_scbuf_decc_top,
scdata_scbuf_decc_bot, scbuf_scdata_fbdecc_top,
scbuf_scdata_fbdecc_bot, rclk, mem_write_disable,
fuse_read_data_in, fuse_l2d_wren, fuse_l2d_rid, fuse_l2d_rden,
fuse_l2d_data_in, efc_scdata_fuse_clk2, efc_scdata_fuse_clk1,
decc_in, col_offset, arst_l, way_sel, si
);
input [11:0] way_sel; // To block_1 of bw_r_l2d.v, ...
input si;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input arst_l; // To data_array_2 of bw_r_l2d.v
input col_offset; // To data_array_2 of bw_r_l2d.v
input [155:0] decc_in; // To data_array_2 of bw_r_l2d.v
input efc_scdata_fuse_clk1; // To data_array_2 of bw_r_l2d.v
input efc_scdata_fuse_clk2; // To data_array_2 of bw_r_l2d.v
input fuse_l2d_data_in; // To data_array_2 of bw_r_l2d.v
input fuse_l2d_rden; // To data_array_2 of bw_r_l2d.v
input [2:0] fuse_l2d_rid; // To data_array_2 of bw_r_l2d.v
input [5:0] fuse_l2d_wren; // To data_array_2 of bw_r_l2d.v
input fuse_read_data_in; // To data_array_2 of bw_r_l2d.v
input mem_write_disable; // To data_array_2 of bw_r_l2d.v
input rclk; // To data_array_0 of bw_r_l2d.v, ...
input [155:0] scbuf_scdata_fbdecc_bot;// To data_array_0 of bw_r_l2d.v
input [155:0] scbuf_scdata_fbdecc_top;// To data_array_0 of bw_r_l2d.v
input [155:0] scdata_scbuf_decc_bot; // To data_array_2 of bw_r_l2d.v
input [155:0] scdata_scbuf_decc_top; // To data_array_2 of bw_r_l2d.v
input se; // To data_array_2 of bw_r_l2d.v
input sehold; // To data_array_2 of bw_r_l2d.v
input [9:0] set; // To data_array_2 of bw_r_l2d.v
input [3:0] word_en; // To data_array_2 of bw_r_l2d.v
input wr_en; // To data_array_2 of bw_r_l2d.v
// End of automatics
output se_buf;
output so;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [155:0] decc_out; // From data_array_2 of bw_r_l2d.v
output l2d_fuse_data_out; // From data_array_0 of bw_r_l2d.v
output [155:0] scbuf_scdata_fbdecc_bot_buf;// From data_array_2 of bw_r_l2d.v
output [155:0] scbuf_scdata_fbdecc_top_buf;// From data_array_2 of bw_r_l2d.v
output [155:0] scdata_scbuf_decc_c6_bot_buf;// From data_array_0 of bw_r_l2d.v
output [155:0] scdata_scbuf_decc_c6_top_buf;// From data_array_0 of bw_r_l2d.v
// End of automatics
wire [11:0] way_sel_buf_1; // From data_array_1 of bw_r_l2d.v
wire [11:0] way_sel_buf_2; // From data_array_2 of bw_r_l2d.v
wire [5:0] fuse_l2d_wren_buf_1; // From data_array_1 of bw_r_l2d.v
wire [5:0] fuse_l2d_wren_buf_2; // From data_array_2 of bw_r_l2d.v
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire arst_l_buf_1; // From data_array_1 of bw_r_l2d.v
wire arst_l_buf_2; // From data_array_2 of bw_r_l2d.v
wire col_offset_buf_1; // From data_array_1 of bw_r_l2d.v
wire col_offset_buf_2; // From data_array_2 of bw_r_l2d.v
wire [155:0] decc_in_buf_1; // From data_array_1 of bw_r_l2d.v
wire [155:0] decc_in_buf_2; // From data_array_2 of bw_r_l2d.v
wire [155:0] decc_out_0; // From data_array_0 of bw_r_l2d.v
wire [155:0] decc_out_1; // From data_array_1 of bw_r_l2d.v
wire fuse_clk1_buf_1; // From data_array_1 of bw_r_l2d.v
wire fuse_clk1_buf_2; // From data_array_2 of bw_r_l2d.v
wire fuse_clk2_buf_1; // From data_array_1 of bw_r_l2d.v
wire fuse_clk2_buf_2; // From data_array_2 of bw_r_l2d.v
wire fuse_l2d_data_in_buf_1; // From data_array_1 of bw_r_l2d.v
wire fuse_l2d_data_in_buf_2; // From data_array_2 of bw_r_l2d.v
wire fuse_l2d_rden_buf_1; // From data_array_1 of bw_r_l2d.v
wire fuse_l2d_rden_buf_2; // From data_array_2 of bw_r_l2d.v
wire [2:0] fuse_l2d_rid_buf_1; // From data_array_1 of bw_r_l2d.v
wire [2:0] fuse_l2d_rid_buf_2; // From data_array_2 of bw_r_l2d.v
wire l2d_fuse_data_out_1; // From data_array_1 of bw_r_l2d.v
wire l2d_fuse_data_out_2; // From data_array_2 of bw_r_l2d.v
wire mem_write_disable_buf_1;// From data_array_1 of bw_r_l2d.v
wire mem_write_disable_buf_2;// From data_array_2 of bw_r_l2d.v
wire scan_out_1; // From data_array_1 of bw_r_l2d.v
wire scan_out_2; // From data_array_2 of bw_r_l2d.v
wire [155:0] scbuf_scdata_fbdecc_bot_buf_0;// From data_array_0 of bw_r_l2d.v
wire [155:0] scbuf_scdata_fbdecc_bot_buf_1;// From data_array_1 of bw_r_l2d.v
wire [155:0] scbuf_scdata_fbdecc_top_buf_0;// From data_array_0 of bw_r_l2d.v
wire [155:0] scbuf_scdata_fbdecc_top_buf_1;// From data_array_1 of bw_r_l2d.v
wire [155:0] scdata_scbuf_decc_bot_buf_1;// From data_array_1 of bw_r_l2d.v
wire [155:0] scdata_scbuf_decc_bot_buf_2;// From data_array_2 of bw_r_l2d.v
wire [155:0] scdata_scbuf_decc_top_buf_1;// From data_array_1 of bw_r_l2d.v
wire [155:0] scdata_scbuf_decc_top_buf_2;// From data_array_2 of bw_r_l2d.v
wire se_buf_1; // From data_array_1 of bw_r_l2d.v
wire se_buf_2; // From data_array_2 of bw_r_l2d.v
wire sehold_buf_1; // From data_array_1 of bw_r_l2d.v
wire sehold_buf_2; // From data_array_2 of bw_r_l2d.v
wire [9:0] set_buf_1; // From data_array_1 of bw_r_l2d.v
wire [9:0] set_buf_2; // From data_array_2 of bw_r_l2d.v
wire [3:0] word_en_buf_1; // From data_array_1 of bw_r_l2d.v
wire [3:0] word_en_buf_2; // From data_array_2 of bw_r_l2d.v
wire wr_en_buf_1; // From data_array_1 of bw_r_l2d.v
wire wr_en_buf_2; // From data_array_2 of bw_r_l2d.v
// End of automatics
/*
bw_r_l2d AUTO_TEMPLATE(
.decc_in(decc_in_buf_@"(+ @ 1)"[155:0]),
.decc_read_in(decc_out_@"(- @ 1)"[155:0]),
.word_en(word_en_buf_@"(+ @ 1)"[3:0]),
.set(set_buf_@"(+ @ 1)"[9:0]),
.col_offset(col_offset_buf_@"(+ @ 1)"),
.wr_en(wr_en_buf_@"(+ @ 1)"),
.decc_in_buf(decc_in_buf_@[155:0]),
.word_en_buf(word_en_buf_@[3:0]),
.set_buf(set_buf_@[9:0]),
.col_offset_buf(col_offset_buf_@),
.wr_en_buf(wr_en_buf_@),
.way_sel_buf(way_sel_buf_@[11:0]),
.decc_out(decc_out_@[155:0]),
.mem_write_disable(mem_write_disable_buf_@"(+ @ 1)"),
.l2d_fuse_data_out(l2d_fuse_data_out_@),
.fuse_read_data_in(l2d_fuse_data_out_@"(+ @ 1)"),
.fuse_l2d_rden(fuse_l2d_rden_buf_@"(+ @ 1)"),
.efc_scdata_fuse_clk1(fuse_clk1_buf_@"(+ @ 1)"),
.efc_scdata_fuse_clk2(fuse_clk2_buf_@"(+ @ 1)"),
.fuse_l2d_rid(fuse_l2d_rid_buf_@"(+ @ 1)"[2:0]),
.fuse_l2d_data_in(fuse_l2d_data_in_buf_@"(+ @ 1)"),
.arst_l(arst_l_buf_@"(+ @ 1)"),
.se(se_buf_@"(+ @ 1)"),
.sehold(sehold_buf_@"(+ @ 1)"),
.fuse_l2d_wren_buf(fuse_l2d_wren_buf_@[5:0]),
.fuse_l2d_rden_buf(fuse_l2d_rden_buf_@),
.fuse_clk1_buf(fuse_clk1_buf_@),
.fuse_clk2_buf(fuse_clk2_buf_@),
.fuse_l2d_rid_buf(fuse_l2d_rid_buf_@[2:0]),
.fuse_l2d_data_in_buf(fuse_l2d_data_in_buf_@),
.arst_l_buf(arst_l_buf_@),
.se_buf(se_buf_@),
.sehold_buf(sehold_buf_@),
.mem_write_disable_buf(mem_write_disable_buf_@),
.scbuf_scdata_fbdecc_top_buf(scbuf_scdata_fbdecc_top_buf_@[155:0]),
.scbuf_scdata_fbdecc_bot_buf(scbuf_scdata_fbdecc_bot_buf_@[155:0]),
.scdata_scbuf_decc_top_buf(scdata_scbuf_decc_top_buf_@[155:0]),
.scdata_scbuf_decc_bot_buf(scdata_scbuf_decc_bot_buf_@[155:0]),
.scbuf_scdata_fbdecc_top(scbuf_scdata_fbdecc_top_buf_@"(- @ 1)"[155:0]),
.scbuf_scdata_fbdecc_bot(scbuf_scdata_fbdecc_bot_buf_@"(- @ 1)"[155:0]),
.scdata_scbuf_decc_top(scdata_scbuf_decc_top_buf_@"(+ @ 1)"[155:0]),
.scdata_scbuf_decc_bot(scdata_scbuf_decc_bot_buf_@"(+ @ 1)"[155:0]),
.si(scan_out_@"(+ @ 1)"),
.so(scan_out_@));
*/
bw_r_l2d data_array_0(
// Inputs
.scbuf_scdata_fbdecc_top(scbuf_scdata_fbdecc_top[155:0]),
.scbuf_scdata_fbdecc_bot(scbuf_scdata_fbdecc_bot[155:0]),
.decc_read_in(156'b0),
.way_sel({way_sel_buf_1[7:0],4'b0}),
.fuse_l2d_wren({fuse_l2d_wren_buf_1[3:0],2'b0}),
// Outputs
.scdata_scbuf_decc_top_buf(scdata_scbuf_decc_c6_top_buf[155:0]),
.scdata_scbuf_decc_bot_buf(scdata_scbuf_decc_c6_bot_buf[155:0]),
.word_en_buf (),
.way_sel_buf (),
.set_buf (),
.col_offset_buf(),
.wr_en_buf (),
.decc_in_buf (),
.so(so),
.l2d_fuse_data_out(l2d_fuse_data_out),
.fuse_clk1_buf(),
.fuse_clk2_buf(),
.fuse_l2d_rid_buf(),
.fuse_l2d_rden_buf(),
.fuse_l2d_wren_buf(),
.fuse_l2d_data_in_buf(),
.arst_l_buf(),
.se_buf(se_buf),
.sehold_buf(),
.mem_write_disable_buf (),
/*AUTOINST*/
// Outputs
.decc_out (decc_out_0[155:0]), // Templated
.scbuf_scdata_fbdecc_bot_buf(scbuf_scdata_fbdecc_bot_buf_0[155:0]), // Templated
.scbuf_scdata_fbdecc_top_buf(scbuf_scdata_fbdecc_top_buf_0[155:0]), // Templated
// Inputs
.arst_l (arst_l_buf_1), // Templated
.col_offset (col_offset_buf_1), // Templated
.decc_in (decc_in_buf_1[155:0]), // Templated
.efc_scdata_fuse_clk1(fuse_clk1_buf_1), // Templated
.efc_scdata_fuse_clk2(fuse_clk2_buf_1), // Templated
.fuse_l2d_data_in(fuse_l2d_data_in_buf_1), // Templated
.fuse_l2d_rden(fuse_l2d_rden_buf_1), // Templated
.fuse_l2d_rid (fuse_l2d_rid_buf_1[2:0]), // Templated
.fuse_read_data_in(l2d_fuse_data_out_1), // Templated
.mem_write_disable(mem_write_disable_buf_1), // Templated
.rclk (rclk),
.scdata_scbuf_decc_bot(scdata_scbuf_decc_bot_buf_1[155:0]), // Templated
.scdata_scbuf_decc_top(scdata_scbuf_decc_top_buf_1[155:0]), // Templated
.se (se_buf_1), // Templated
.sehold (sehold_buf_1), // Templated
.set (set_buf_1[9:0]), // Templated
.si (scan_out_1), // Templated
.word_en (word_en_buf_1[3:0]), // Templated
.wr_en (wr_en_buf_1)); // Templated
bw_r_l2d data_array_1(
// Inputs
.way_sel({way_sel_buf_2[7:0],4'b0}),
.fuse_l2d_wren({fuse_l2d_wren_buf_2[3:0],2'b0}),
/*AUTOINST*/
// Outputs
.fuse_l2d_rid_buf(fuse_l2d_rid_buf_1[2:0]), // Templated
.fuse_l2d_data_in_buf(fuse_l2d_data_in_buf_1), // Templated
.arst_l_buf (arst_l_buf_1), // Templated
.se_buf (se_buf_1), // Templated
.sehold_buf (sehold_buf_1), // Templated
.fuse_l2d_rden_buf(fuse_l2d_rden_buf_1), // Templated
.fuse_l2d_wren_buf(fuse_l2d_wren_buf_1[5:0]), // Templated
.fuse_clk1_buf(fuse_clk1_buf_1), // Templated
.fuse_clk2_buf(fuse_clk2_buf_1), // Templated
.mem_write_disable_buf(mem_write_disable_buf_1), // Templated
.col_offset_buf(col_offset_buf_1), // Templated
.decc_in_buf (decc_in_buf_1[155:0]), // Templated
.decc_out (decc_out_1[155:0]), // Templated
.l2d_fuse_data_out(l2d_fuse_data_out_1), // Templated
.scbuf_scdata_fbdecc_bot_buf(scbuf_scdata_fbdecc_bot_buf_1[155:0]), // Templated
.scbuf_scdata_fbdecc_top_buf(scbuf_scdata_fbdecc_top_buf_1[155:0]), // Templated
.scdata_scbuf_decc_bot_buf(scdata_scbuf_decc_bot_buf_1[155:0]), // Templated
.scdata_scbuf_decc_top_buf(scdata_scbuf_decc_top_buf_1[155:0]), // Templated
.set_buf (set_buf_1[9:0]), // Templated
.so (scan_out_1), // Templated
.way_sel_buf (way_sel_buf_1[11:0]), // Templated
.word_en_buf (word_en_buf_1[3:0]), // Templated
.wr_en_buf (wr_en_buf_1), // Templated
// Inputs
.arst_l (arst_l_buf_2), // Templated
.col_offset (col_offset_buf_2), // Templated
.decc_in (decc_in_buf_2[155:0]), // Templated
.decc_read_in (decc_out_0[155:0]), // Templated
.efc_scdata_fuse_clk1(fuse_clk1_buf_2), // Templated
.efc_scdata_fuse_clk2(fuse_clk2_buf_2), // Templated
.fuse_l2d_data_in(fuse_l2d_data_in_buf_2), // Templated
.fuse_l2d_rden(fuse_l2d_rden_buf_2), // Templated
.fuse_l2d_rid (fuse_l2d_rid_buf_2[2:0]), // Templated
.fuse_read_data_in(l2d_fuse_data_out_2), // Templated
.mem_write_disable(mem_write_disable_buf_2), // Templated
.rclk (rclk),
.scbuf_scdata_fbdecc_bot(scbuf_scdata_fbdecc_bot_buf_0[155:0]), // Templated
.scbuf_scdata_fbdecc_top(scbuf_scdata_fbdecc_top_buf_0[155:0]), // Templated
.scdata_scbuf_decc_bot(scdata_scbuf_decc_bot_buf_2[155:0]), // Templated
.scdata_scbuf_decc_top(scdata_scbuf_decc_top_buf_2[155:0]), // Templated
.se (se_buf_2), // Templated
.sehold (sehold_buf_2), // Templated
.set (set_buf_2[9:0]), // Templated
.si (scan_out_2), // Templated
.word_en (word_en_buf_2[3:0]), // Templated
.wr_en (wr_en_buf_2)); // Templated
bw_r_l2d data_array_2(
// Inputs
.word_en(word_en[3:0]),
.way_sel(way_sel[11:0]),
.set(set[9:0]),
.col_offset(col_offset),
.wr_en(wr_en),
.decc_in(decc_in[155:0]),
.scdata_scbuf_decc_top(scdata_scbuf_decc_top[155:0]),
.scdata_scbuf_decc_bot(scdata_scbuf_decc_bot[155:0]),
.fuse_read_data_in(fuse_read_data_in),
.si(si),
.efc_scdata_fuse_clk1(efc_scdata_fuse_clk1),
.efc_scdata_fuse_clk2(efc_scdata_fuse_clk2),
.fuse_l2d_rid(fuse_l2d_rid[2:0]),
.fuse_l2d_rden(fuse_l2d_rden),
.fuse_l2d_wren(fuse_l2d_wren[5:0]),
.fuse_l2d_data_in(fuse_l2d_data_in),
.arst_l(arst_l),
.se(se),
.sehold(sehold),
.mem_write_disable(mem_write_disable),
// Outputs
.decc_out(decc_out[155:0]),
.scbuf_scdata_fbdecc_top_buf(scbuf_scdata_fbdecc_top_buf[155:0]),
.scbuf_scdata_fbdecc_bot_buf(scbuf_scdata_fbdecc_bot_buf[155:0]),
/*AUTOINST*/
// Outputs
.fuse_l2d_rid_buf(fuse_l2d_rid_buf_2[2:0]), // Templated
.fuse_l2d_data_in_buf(fuse_l2d_data_in_buf_2), // Templated
.arst_l_buf (arst_l_buf_2), // Templated
.se_buf (se_buf_2), // Templated
.sehold_buf (sehold_buf_2), // Templated
.fuse_l2d_rden_buf(fuse_l2d_rden_buf_2), // Templated
.fuse_l2d_wren_buf(fuse_l2d_wren_buf_2[5:0]), // Templated
.fuse_clk1_buf(fuse_clk1_buf_2), // Templated
.fuse_clk2_buf(fuse_clk2_buf_2), // Templated
.mem_write_disable_buf(mem_write_disable_buf_2), // Templated
.col_offset_buf(col_offset_buf_2), // Templated
.decc_in_buf (decc_in_buf_2[155:0]), // Templated
.l2d_fuse_data_out(l2d_fuse_data_out_2), // Templated
.scdata_scbuf_decc_bot_buf(scdata_scbuf_decc_bot_buf_2[155:0]), // Templated
.scdata_scbuf_decc_top_buf(scdata_scbuf_decc_top_buf_2[155:0]), // Templated
.set_buf (set_buf_2[9:0]), // Templated
.so (scan_out_2), // Templated
.way_sel_buf (way_sel_buf_2[11:0]), // Templated
.word_en_buf (word_en_buf_2[3:0]), // Templated
.wr_en_buf (wr_en_buf_2), // Templated
// Inputs
.decc_read_in (decc_out_1[155:0]), // Templated
.rclk (rclk),
.scbuf_scdata_fbdecc_bot(scbuf_scdata_fbdecc_bot_buf_1[155:0]), // Templated
.scbuf_scdata_fbdecc_top(scbuf_scdata_fbdecc_top_buf_1[155:0])); // Templated
endmodule // scdata_subbank
// Local Variables:
// verilog-library-directories:("." "../../srams/rtl")
// verilog-library-files: ("../../srams/rtl/bw_r_l2d.v")
// verilog-auto-sense-defines-constant:t
// End:
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
input wire phy_int_n,
inout wire phy_mdio,
output wire phy_mdc,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_125mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 8, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(8),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire [15:0] pcspma_status_vector;
wire pcspma_status_link_status = pcspma_status_vector[0];
wire pcspma_status_link_synchronization = pcspma_status_vector[1];
wire pcspma_status_rudi_c = pcspma_status_vector[2];
wire pcspma_status_rudi_i = pcspma_status_vector[3];
wire pcspma_status_rudi_invalid = pcspma_status_vector[4];
wire pcspma_status_rxdisperr = pcspma_status_vector[5];
wire pcspma_status_rxnotintable = pcspma_status_vector[6];
wire pcspma_status_phy_link_status = pcspma_status_vector[7];
wire [1:0] pcspma_status_remote_fault_encdg = pcspma_status_vector[9:8];
wire [1:0] pcspma_status_speed = pcspma_status_vector[11:10];
wire pcspma_status_duplex = pcspma_status_vector[12];
wire pcspma_status_remote_fault = pcspma_status_vector[13];
wire [1:0] pcspma_status_pause = pcspma_status_vector[15:14];
wire [4:0] pcspma_config_vector;
assign pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign pcspma_config_vector[3] = 1'b0; // isolate
assign pcspma_config_vector[2] = 1'b0; // power down
assign pcspma_config_vector[1] = 1'b0; // loopback enable
assign pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] pcspma_an_config_vector;
assign pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign pcspma_an_config_vector[9] = 1'b0; // reserved
assign pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign pcspma_an_config_vector[6] = 1'b0; // reserved
assign pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_ethernet_pcs_pma_0
eth_pcspma (
// SGMII
.txp_0 (phy_sgmii_tx_p),
.txn_0 (phy_sgmii_tx_n),
.rxp_0 (phy_sgmii_rx_p),
.rxn_0 (phy_sgmii_rx_n),
// Ref clock from PHY
.refclk625_p (phy_sgmii_clk_p),
.refclk625_n (phy_sgmii_clk_n),
// async reset
.reset (rst_125mhz_int),
// clock and reset outputs
.clk125_out (phy_gmii_clk_int),
.clk312_out (),
.rst_125_out (phy_gmii_rst_int),
.tx_logic_reset (),
.rx_logic_reset (),
.tx_locked (),
.rx_locked (),
.tx_pll_clk_out (),
.rx_pll_clk_out (),
// MAC clocking
.sgmii_clk_r_0 (),
.sgmii_clk_f_0 (),
.sgmii_clk_en_0 (phy_gmii_clk_en_int),
// Speed control
.speed_is_10_100_0 (pcspma_status_speed != 2'b10),
.speed_is_100_0 (pcspma_status_speed == 2'b01),
// Internal GMII
.gmii_txd_0 (phy_gmii_txd_int),
.gmii_tx_en_0 (phy_gmii_tx_en_int),
.gmii_tx_er_0 (phy_gmii_tx_er_int),
.gmii_rxd_0 (phy_gmii_rxd_int),
.gmii_rx_dv_0 (phy_gmii_rx_dv_int),
.gmii_rx_er_0 (phy_gmii_rx_er_int),
.gmii_isolate_0 (),
// Configuration
.configuration_vector_0 (pcspma_config_vector),
.an_interrupt_0 (),
.an_adv_config_vector_0 (pcspma_an_config_vector),
.an_restart_config_0 (1'b0),
// Status
.status_vector_0 (pcspma_status_vector),
.signal_detect_0 (1'b1),
// Cascade
.tx_bsc_rst_out (),
.rx_bsc_rst_out (),
.tx_bs_rst_out (),
.rx_bs_rst_out (),
.tx_rst_dly_out (),
.rx_rst_dly_out (),
.tx_bsc_en_vtc_out (),
.rx_bsc_en_vtc_out (),
.tx_bs_en_vtc_out (),
.rx_bs_en_vtc_out (),
.riu_clk_out (),
.riu_addr_out (),
.riu_wr_data_out (),
.riu_wr_en_out (),
.riu_nibble_sel_out (),
.riu_rddata_1 (16'b0),
.riu_valid_1 (1'b0),
.riu_prsnt_1 (1'b0),
.riu_rddata_2 (16'b0),
.riu_valid_2 (1'b0),
.riu_prsnt_2 (1'b0),
.riu_rddata_3 (16'b0),
.riu_valid_3 (1'b0),
.riu_prsnt_3 (1'b0),
.rx_btval_1 (),
.rx_btval_2 (),
.rx_btval_3 (),
.tx_dly_rdy_1 (1'b1),
.rx_dly_rdy_1 (1'b1),
.rx_vtc_rdy_1 (1'b1),
.tx_vtc_rdy_1 (1'b1),
.tx_dly_rdy_2 (1'b1),
.rx_dly_rdy_2 (1'b1),
.rx_vtc_rdy_2 (1'b1),
.tx_vtc_rdy_2 (1'b1),
.tx_dly_rdy_3 (1'b1),
.rx_dly_rdy_3 (1'b1),
.rx_vtc_rdy_3 (1'b1),
.tx_vtc_rdy_3 (1'b1),
.tx_rdclk_out ()
);
reg [19:0] delay_reg = 20'hfffff;
reg [4:0] mdio_cmd_phy_addr = 5'h03;
reg [4:0] mdio_cmd_reg_addr = 5'h00;
reg [15:0] mdio_cmd_data = 16'd0;
reg [1:0] mdio_cmd_opcode = 2'b01;
reg mdio_cmd_valid = 1'b0;
wire mdio_cmd_ready;
reg [3:0] state_reg = 0;
always @(posedge clk_125mhz_int) begin
if (rst_125mhz_int) begin
state_reg <= 0;
delay_reg <= 20'hfffff;
mdio_cmd_reg_addr <= 5'h00;
mdio_cmd_data <= 16'd0;
mdio_cmd_valid <= 1'b0;
end else begin
mdio_cmd_valid <= mdio_cmd_valid & !mdio_cmd_ready;
if (delay_reg > 0) begin
delay_reg <= delay_reg - 1;
end else if (!mdio_cmd_ready) begin
// wait for ready
state_reg <= state_reg;
end else begin
mdio_cmd_valid <= 1'b0;
case (state_reg)
// set SGMII autonegotiation timer to 11 ms
// write 0x0070 to CFG4 (0x0031)
4'd0: begin
// write to REGCR to load address
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h001F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd1;
end
4'd1: begin
// write address of CFG4 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h0031;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd2;
end
4'd2: begin
// write to REGCR to load data
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h401F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd3;
end
4'd3: begin
// write data for CFG4 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h0070;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd4;
end
// enable SGMII clock output
// write 0x4000 to SGMIICTL1 (0x00D3)
4'd4: begin
// write to REGCR to load address
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h001F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd5;
end
4'd5: begin
// write address of SGMIICTL1 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h00D3;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd6;
end
4'd6: begin
// write to REGCR to load data
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h401F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd7;
end
4'd7: begin
// write data for SGMIICTL1 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h4000;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd8;
end
// enable 10Mbps operation
// write 0x0015 to 10M_SGMII_CFG (0x016F)
4'd8: begin
// write to REGCR to load address
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h001F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd9;
end
4'd9: begin
// write address of 10M_SGMII_CFG to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h016F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd10;
end
4'd10: begin
// write to REGCR to load data
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h401F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd11;
end
4'd11: begin
// write data for 10M_SGMII_CFG to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h0015;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd12;
end
4'd12: begin
// done
state_reg <= 4'd12;
end
endcase
end
end
end
wire mdc;
wire mdio_i;
wire mdio_o;
wire mdio_t;
mdio_master
mdio_master_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.cmd_phy_addr(mdio_cmd_phy_addr),
.cmd_reg_addr(mdio_cmd_reg_addr),
.cmd_data(mdio_cmd_data),
.cmd_opcode(mdio_cmd_opcode),
.cmd_valid(mdio_cmd_valid),
.cmd_ready(mdio_cmd_ready),
.data_out(),
.data_out_valid(),
.data_out_ready(1'b1),
.mdc_o(mdc),
.mdio_i(mdio_i),
.mdio_o(mdio_o),
.mdio_t(mdio_t),
.busy(),
.prescale(8'd3)
);
assign phy_mdc = mdc;
assign mdio_i = phy_mdio;
assign phy_mdio = mdio_t ? 1'bz : mdio_o;
wire [7:0] led_int;
// SGMII interface debug:
// SW12:4 (sw[0]) off for payload byte, on for status vector
// SW12:3 (sw[1]) off for LSB of status vector, on for MSB
assign led = sw[0] ? (sw[1] ? pcspma_status_vector[15:8] : pcspma_status_vector[7:0]) : led_int;
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led_int),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
|
//==================================
// dc_planar
// luyanheng
// creat:2014-9-16
// modify:2015-1-9
//==================================
module dc_planar(
rstn,
clk,
counterrun1,
counterrun2,
gx,
gy,
cnt,
blockcnt,
bestmode,
bestmode16,
bestmode32,
modebest,
modebest16,
modebest32,
bestmode_o,
bestmode16_o,
bestmode32_o
);
parameter MODE=21;
parameter DIGIT=0;
parameter DC8=288;
parameter DC16=1152;
parameter DC32=4608;
parameter Plan8=32;
parameter Plan16=32;
parameter Plan32=32;
input rstn;
input clk;
input counterrun1;
input counterrun2;
input signed [10:0] gx;
input signed [10:0] gy;
input [5:0] cnt;
input [6:0] blockcnt;
input [5:0] bestmode;
input [5:0] bestmode16;
input [5:0] bestmode32;
input [MODE-DIGIT:0] modebest;
input [MODE-DIGIT+2:0] modebest16;
input [MODE-DIGIT+4:0] modebest32;
output [5:0] bestmode_o;
output [5:0] bestmode16_o;
output [5:0] bestmode32_o;
reg [10:0] data_tmp;
reg [15:0] modedata;
reg [15:0] modedata8;
reg [17:0] modedata16;
reg [19:0] modedata32;
reg [5:0] bestmode_o;
reg [5:0] bestmode16_o;
reg [5:0] bestmode32_o;
//==================mode data calculation====================================
always@(posedge clk or negedge rstn)
if(!rstn)
data_tmp <= 'd0;
else if(counterrun1)
data_tmp <= (gx[10]?(-gx):gx) + (gy[10]?(-gy):gy);
always@(posedge clk or negedge rstn)
if(!rstn)
modedata <= 'd0;
else if(counterrun2)
modedata <= modedata+data_tmp;
else if(counterrun1)
modedata <= 'd0;
always@(posedge clk or negedge rstn)
if(!rstn)
modedata8 <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd7))
modedata8 <= modedata;
always@(posedge clk or negedge rstn)
if(!rstn)
modedata16 <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd8) && (blockcnt[1:0] == 2'b01))
modedata16 <= modedata8;
else if((blockcnt != 'd0) && (cnt == 'd8))
modedata16 <= modedata16+modedata8;
always@(posedge clk or negedge rstn)
if(!rstn)
modedata32 <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd9) && (blockcnt[3:0] == 4'b0100))
modedata32 <= modedata16;
else if((blockcnt != 'd0) && (cnt == 'd9) && (blockcnt[1:0] == 2'b00))
modedata32 <= modedata32+modedata16;
//================best mode decision============================
always@(posedge clk or negedge rstn)
if(!rstn)
bestmode_o <= 'd0;
else if((modedata8 < DC8) && (blockcnt != 'd0) && (cnt == 'd35))
bestmode_o <= 'd1;
else if((modebest > Plan8 * modedata8) && (blockcnt != 'd0) && (cnt == 'd35))
bestmode_o <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd35))
bestmode_o <= bestmode;
always@(posedge clk or negedge rstn)
if(!rstn)
bestmode16_o <= 'd0;
else if((modedata16 < DC16) && (blockcnt != 'd0) && (cnt == 'd38) && (blockcnt[1:0] == 2'b00))
bestmode16_o <= 'd1;
else if((modebest16 > Plan16 * modedata16) && (blockcnt != 'd0) && (cnt == 'd38) && (blockcnt[1:0] == 2'b00))
bestmode16_o <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd38) && (blockcnt[1:0] == 2'b00))
bestmode16_o <= bestmode16;
always@(posedge clk or negedge rstn)
if(!rstn)
bestmode32_o <= 'd0;
else if((modedata32 < DC32) && (blockcnt != 'd0) && (cnt == 'd39) && (blockcnt[3:0] == 4'b0000))
bestmode32_o <= 'd1;
else if((modebest32 > Plan32 * modedata32) && (blockcnt != 'd0) && (cnt == 'd39) && (blockcnt[3:0] == 4'b0000))
bestmode32_o <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd39) && (blockcnt[3:0] == 4'b0000))
bestmode32_o <= bestmode32;
endmodule
|
// file: testclk_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module testclk_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [4:1] CLK_OUT,
// High bits of counters driven by clocks
output [4:1] COUNT
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 4;
genvar count_gen;
// Create reset for the counters
wire reset_int = COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Connect the feedback on chip
wire CLKFB_OUT;
wire CLKFB_IN;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Connect the feedback on chip- duplicate the delay for CLK_OUT1
assign CLKFB_IN = CLKFB_OUT;
// Instantiation of the clocking network
//--------------------------------------
testclk clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
.CLKFB_IN (CLKFB_IN),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]),
.CLK_OUT3 (clk_int[3]),
.CLK_OUT4 (clk_int[4]),
.CLKFB_OUT (CLKFB_OUT));
genvar clk_out_pins;
generate
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
begin: gen_outclk_oddr
ODDR clkout_oddr
(.Q (CLK_OUT[clk_out_pins]),
.C (clk[clk_out_pins]),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
BUFG clkout1_buf
(.O (clk[1]),
.I (clk_int[1]));
BUFG clkout2_buf
(.O (clk[2]),
.I (clk_int[2]));
BUFG clkout3_buf
(.O (clk[3]),
.I (clk_int[3]));
BUFG clkout4_buf
(.O (clk[4]),
.I (clk_int[4]));
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
|
module ram_wb_b3(
wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o,
wb_clk_i, wb_rst_i);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input [1:0] wb_bte_i;
input [2:0] wb_cti_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
output [dw-1:0] wb_dat_o;
input wb_clk_i;
input wb_rst_i;
// Memory parameters
parameter mem_size_bytes = 32'h0002_0000; // 128KBytes
parameter mem_adr_width = 17; //(log2(mem_size_bytes));
parameter bytes_per_dw = (dw/8);
parameter adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
parameter mem_words = (mem_size_bytes/bytes_per_dw);
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [0:mem_words-1] /* synthesis ram_style = block */;
// Register to address internal memory array
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
wire [31:0] wr_data;
// Register to indicate if the cycle is a Wishbone B3-registered feedback
// type access
reg wb_b3_trans;
wire wb_b3_trans_start, wb_b3_trans_stop;
// Register to use for counting the addresses when doing burst accesses
reg [mem_adr_width-adr_width_for_num_word_bytes-1:0] burst_adr_counter;
reg [2:0] wb_cti_i_r;
reg [1:0] wb_bte_i_r;
wire using_burst_adr;
wire burst_access_wrong_wb_adr;
// Wire to indicate addressing error
wire addr_err;
// Logic to detect if there's a burst access going on
assign wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
wb_stb_i & !wb_b3_trans;
assign wb_b3_trans_stop = ((wb_cti_i == 3'b111) &
wb_stb_i & wb_b3_trans & wb_ack_o) | wb_err_o;
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_b3_trans <= 0;
else if (wb_b3_trans_start)
wb_b3_trans <= 1;
else if (wb_b3_trans_stop)
wb_b3_trans <= 0;
// Burst address generation logic
always @(/*AUTOSENSE*/wb_ack_o or wb_b3_trans or wb_b3_trans_start
or wb_bte_i_r or wb_cti_i_r or wb_adr_i or adr)
if (wb_b3_trans_start)
// Kick off burst_adr_counter, this assumes 4-byte words when getting
// address off incoming Wishbone bus address!
// So if dw is no longer 4 bytes, change this!
burst_adr_counter = wb_adr_i[mem_adr_width-1:2];
else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
// Incrementing burst
begin
if (wb_bte_i_r == 2'b00) // Linear burst
burst_adr_counter = adr + 1;
if (wb_bte_i_r == 2'b01) // 4-beat wrap burst
burst_adr_counter[1:0] = adr[1:0] + 1;
if (wb_bte_i_r == 2'b10) // 8-beat wrap burst
burst_adr_counter[2:0] = adr[2:0] + 1;
if (wb_bte_i_r == 2'b11) // 16-beat wrap burst
burst_adr_counter[3:0] = adr[3:0] + 1;
end // if ((wb_cti_i_r == 3'b010) & wb_ack_o_r)
always @(posedge wb_clk_i)
wb_bte_i_r <= wb_bte_i;
// Register it locally
always @(posedge wb_clk_i)
wb_cti_i_r <= wb_cti_i;
assign using_burst_adr = wb_b3_trans;
assign burst_access_wrong_wb_adr = (using_burst_adr &
(adr != wb_adr_i[mem_adr_width-1:2]));
// Address registering logic
always@(posedge wb_clk_i)
if(wb_rst_i)
adr <= 0;
else if (using_burst_adr)
adr <= burst_adr_counter;
else if (wb_cyc_i & wb_stb_i)
adr <= wb_adr_i[mem_adr_width-1:2];
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr_comb;
// Address registering logic, combinational version, to enable block ram infer
always@(*)
if(wb_rst_i)
adr_comb = 0;
else if (using_burst_adr)
adr_comb = burst_adr_counter;
else if (wb_cyc_i & wb_stb_i)
adr_comb = wb_adr_i[mem_adr_width-1:2];
// Memory initialisation.
parameter memory_file = "sram.vmem";
// Must add -use_new_parser yes to XST command line for this to work
//otherwise XST requires an odd format
integer k;
initial begin
// synthesis translate_off
for(k = 0; k < (1 << mem_words); k = k + 1)
begin
mem[k] = 0;
end
// synthesis translate_on
$readmemh(memory_file, mem);
end
assign wb_rty_o = 0;
// mux for data to ram, RMW on part sel != 4'hf
assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
wire ram_we;
assign ram_we = wb_we_i & wb_ack_o;
reg [dw-1:0] data_from_mem;
always @(posedge wb_clk_i)begin
if(wb_cyc_i)
data_from_mem <= mem[adr_comb];
end
assign wb_dat_o = data_from_mem;
// Write logic
always @ (posedge wb_clk_i)
begin
if (ram_we)
mem[adr] <= wr_data;
end
// Ack Logic
reg wb_ack_o_r;
assign wb_ack_o = wb_ack_o_r & wb_stb_i &
!(burst_access_wrong_wb_adr | addr_err);
always @ (posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o_r <= 1'b0;
else if (wb_cyc_i) // We have bus
begin
if (addr_err & wb_stb_i)
begin
wb_ack_o_r <= 1;
end
else if (wb_cti_i == 3'b000)
begin
// Classic cycle acks
if (wb_stb_i)
begin
if (!wb_ack_o_r)
wb_ack_o_r <= 1;
else
wb_ack_o_r <= 0;
end
end // if (wb_cti_i == 3'b000)
else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010))
begin
// Increment/constant address bursts
if (wb_stb_i)
wb_ack_o_r <= 1;
else
wb_ack_o_r <= 0;
end
else if (wb_cti_i == 3'b111)
begin
// End of cycle
if (!wb_ack_o_r)
wb_ack_o_r <= wb_stb_i;
else
wb_ack_o_r <= 0;
end
end // if (wb_cyc_i)
else
wb_ack_o_r <= 0;
//
// Error signal generation
//
// Error when out of bounds of memory - skip top byte of address in case
// this is mapped somewhere other than 0x00.
assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1:mem_adr_width]);
// OR in other errors here...
assign wb_err_o = wb_ack_o_r & wb_stb_i &
(burst_access_wrong_wb_adr | addr_err);
`ifdef verilator
//
// Access functions
//
// Function to access RAM (for use by Verilator).
function [31:0] get_mem32;
// verilator public
input [aw-1:0] addr;
get_mem32 = mem[addr];
endfunction // get_mem32
// Function to access RAM (for use by Verilator).
function [7:0] get_mem8;
// verilator public
input [aw-1:0] addr;
reg [31:0] temp_word;
begin
temp_word = mem[{addr[aw-1:2],2'd0}];
// Big endian mapping.
get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
(addr[1:0]==2'b01) ? temp_word[23:16] :
(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
end
endfunction // get_mem8
// Function to write RAM (for use by Verilator).
function set_mem32;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
mem[addr] = data;
endfunction // set_mem32
`endif
endmodule // ram_wb_b3
|
`timescale 1ns / 100ps
/* This test module works by tickling various inputs over a sequence of time.
* If the output waveforms graphically, each test scenario is uniquely
* identified by a number on the `scenario_o` bus.
*/
module test();
reg clk_o;
reg rst_o;
reg [7:0] scenario_o;
reg [1:0] mode_o;
reg d_o;
reg stb_o;
wire q_i;
/* Device Under Test */
GPIA_BIT dut (
.clk_i(clk_o),
.res_i(rst_o),
.mode_i(mode_o),
.d_i(d_o),
.stb_i(stb_o),
.q_o(q_i)
);
/* Initial models will correspond to a 12.5MHz system clock, to make it as
* close to the Kestrel-3's initial hardware configuration as possible.
* Alternative synthesis targets may want to adjust this setting if it affects
* how the circuit is synthesized. I have no experience with ASICs or large,
* mega-FPGAs, so I'm ignorant of its effects in those contexts.
*/
always begin
#20 clk_o <= ~clk_o;
end
/* Everything on the Wishbone bus happens on the rising edge of the clock.
* I'm not personally a fan of this approach, but it works well in an FPGA
* context. This task is responsible for synchronizing these unit tests
* against Wishbone's expectations of when a new cycle starts.
*/
task waitclk;
begin @(negedge clk_o); @(posedge clk_o);
end
endtask
/* About half of the test cases cover a reset bit, and the other half when
* the bit is set. This task fakes a Wishbone bus transaction which sets
* the bit.
*/
task setq;
begin
rst_o <= 0;
mode_o <= 0;
d_o <= 1;
stb_o <= 1;
waitclk;
end
endtask
/* The scenario tests commence here. */
initial begin
clk_o <= 0;
rst_o <= 0;
scenario_o <= 8'h00;
mode_o <= 0;
d_o <= 0;
stb_o <= 0;
$dumpfile("test.vcd");
$dumpvars;
/* Given a reset GPIA, all outputs MUST be low. */
@(posedge clk_o);
scenario_o <= 8'h01;
rst_o <= 1;
waitclk;
rst_o <= 0;
waitclk;
if(q_i == 1) begin
$display("FAIL 01: Q not 0"); $finish;
end
/* Given a reset GPIA, followed by a write of '0', q_i MUST
* become '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h10;
waitclk;
rst_o <= 0;
mode_o <= 0;
d_o <= 0;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 10: Q must remain 0"); $finish;
end
/* Given a reset GPIA, followed by a set-bit of '0', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h14;
waitclk;
rst_o <= 0;
mode_o <= 1;
d_o <= 0;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 14: Q must remain 0"); $finish;
end
/* Given a reset GPIA, followed by a clr-bit of '0', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h18;
waitclk;
rst_o <= 0;
mode_o <= 2;
d_o <= 0;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 18: Q must remain 0"); $finish;
end
/* Given a reset GPIA, followed by a tgl-bit of '0', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h1C;
waitclk;
rst_o <= 0;
mode_o <= 3;
d_o <= 0;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 1C: Q must remain 0"); $finish;
end
/* Given a reset GPIA, followed by a write of '1', q_i MUST
* become '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h20;
waitclk;
rst_o <= 0;
mode_o <= 0;
d_o <= 1;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i == 0) begin
$display("FAIL 20: Q not 1 on write"); $finish;
end
/* Given a reset GPIA, followed by a set-bit of '1', q_i MUST
* become '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h24;
waitclk;
rst_o <= 0;
mode_o <= 1;
d_o <= 1;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i == 0) begin
$display("FAIL 24: Q not 1 on set-bit"); $finish;
end
/* Given a reset GPIA, followed by a clr-bit of '1', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h28;
waitclk;
rst_o <= 0;
mode_o <= 2;
d_o <= 1;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i == 1) begin
$display("FAIL 28: a cleared Q must remain 0"); $finish;
end
/* Given a reset GPIA, followed by a tgl-bit of '1', q_i MUST
* become '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h2C;
waitclk;
rst_o <= 0;
mode_o <= 3;
d_o <= 1;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 1) begin
$display("FAIL 2C: a cleared Q must toggle to 1"); $finish;
end
/* Given a reset GPIA with a set output bit,
* and followed by a write of '0', q_i MUST
* reset to '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h30;
waitclk;
setq;
d_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 30: Q must reset to 0"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a set-bit of '0', q_i MUST
* remain '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h34;
waitclk;
setq;
d_o <= 0;
mode_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 1) begin
$display("FAIL 34: Q must remain 0"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a clr-bit of '0', q_i MUST
* remain '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h38;
waitclk;
setq;
mode_o <= 2;
d_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 1) begin
$display("FAIL 38: Q must remain 1"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a tgl-bit of '0', q_i MUST
* remain '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h3C;
waitclk;
setq;
mode_o <= 3;
d_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 1) begin
$display("FAIL 3C: Q must remain 1"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a write of '1', q_i MUST
* remain '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h40;
waitclk;
setq;
mode_o <= 0;
d_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i == 0) begin
$display("FAIL 40: Q not 1 on write"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a set-bit of '1', q_i MUST
* remain '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h44;
waitclk;
setq;
mode_o <= 1;
d_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 1) begin
$display("FAIL 44: Q not 1 on set-bit"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a clr-bit of '1', q_i MUST
* become '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h48;
waitclk;
setq;
mode_o <= 2;
d_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 48: a set Q must become 0"); $finish;
end
/* Given a reset GPIA with a set output bit,
* followed by a tgl-bit of '1', q_i MUST
* become '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h4C;
waitclk;
setq;
mode_o <= 3;
d_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 4C: a set Q must toggle to 0"); $finish;
end
/* Given a reset GPIA with clear output bit,
* a reset STB input,
* followed by a write of '1', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h50;
waitclk;
mode_o <= 0;
d_o <= 1;
stb_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 50: Q shouldn't be affected on masked write"); $finish;
end
/* Given a reset GPIA with clear output bit,
* a reset STB input,
* followed by a set-bit of '1', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h54;
waitclk;
mode_o <= 1;
d_o <= 1;
stb_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 54: Q shouldn't be affected on masked write"); $finish;
end
/* Given a reset GPIA with clear output bit,
* a reset STB input,
* followed by a clear-bit of '1', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h58;
waitclk;
mode_o <= 2;
d_o <= 1;
stb_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 58: Q shouldn't be affected on masked write"); $finish;
end
/* Given a reset GPIA with clear output bit,
* a reset STB input,
* followed by a toggle of '1', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h5C;
waitclk;
mode_o <= 0;
d_o <= 1;
stb_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 5C: Q shouldn't be affected on masked write"); $finish;
end
$display("PASS"); $finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O2BB2AI_FUNCTIONAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2AI_FUNCTIONAL_PP_V |
`timescale 1ns / 100ps
module uartlib(
input UART_CLK, output reg UART_TX
);
integer counter;
initial
UART_TX = 1;
task write_byte;
input [7:0] data;
begin
//start bit
$display("write_byte: 0x%x (0b%b) [%c]", data, data, data);
repeat(2) @(posedge UART_CLK) UART_TX <= 1;
@(posedge UART_CLK) UART_TX <= 0;
//data
@(posedge UART_CLK) UART_TX <= data[0];
@(posedge UART_CLK) UART_TX <= data[1];
@(posedge UART_CLK) UART_TX <= data[2];
@(posedge UART_CLK) UART_TX <= data[3];
@(posedge UART_CLK) UART_TX <= data[4];
@(posedge UART_CLK) UART_TX <= data[5];
@(posedge UART_CLK) UART_TX <= data[6];
@(posedge UART_CLK) UART_TX <= data[7];
//stop bit
@(posedge UART_CLK) UART_TX <= 1;
repeat(2) @(posedge UART_CLK);
end
endtask
task write;
input [31:0] addr;
input [31:0] size;
begin
repeat (40) @(posedge UART_CLK);
write_byte(8'h61); // 0x61 = a
write_byte(addr[7:0]);
write_byte(addr[15:8]);
write_byte(addr[23:16]);
write_byte(addr[31:24]);
repeat(40) @(posedge UART_CLK) ;
write_byte(8'h6c); // 0x6c = l
write_byte(size[7:0]);
write_byte(size[15:8]);
write_byte(size[23:16]);
write_byte(size[31:24]);
repeat(40) @(posedge UART_CLK) ;
write_byte(8'h77); //0x77 = w
repeat(40) @(posedge UART_CLK) ;
end
endtask
task read;
input [31:0] addr;
input [31:0] size;
begin
repeat (40) @(posedge UART_CLK);
write_byte(8'h61); // 0x61 = a
write_byte(addr[7:0]);
write_byte(addr[15:8]);
write_byte(addr[23:16]);
write_byte(addr[31:24]);
repeat(40) @(posedge UART_CLK) ;
write_byte(8'h6c); // 0x6c = l
write_byte(size[7:0]);
write_byte(size[15:8]);
write_byte(size[23:16]);
write_byte(size[31:24]);
repeat(40) @(posedge UART_CLK) ;//wait for receiving OK
write_byte(8'h72); // 0x72 = r
repeat(40) @(posedge UART_CLK) ;
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_SYMBOL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_SYMBOL_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s25 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_1_V
`define SKY130_FD_SC_HS__CLKINV_1_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkinv_1 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkinv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_BLACKBOX_V
`define SKY130_FD_SC_LS__DLYMETAL6S2S_BLACKBOX_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlymetal6s2s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S2S_BLACKBOX_V
|
`include "mmcme2_test.v"
`default_nettype none
// ============================================================================
module top
(
input wire clk,
input wire [7:0] sw,
output wire [7:0] led,
input wire jc1, // unused
output wire jc2,
input wire jc3, // unused
input wire jc4
);
// ============================================================================
// Reset generator
wire CLK;
BUFG bufgctrl(.I(clk), .O(CLK));
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge CLK)
if (sw[0])
rst_sr <= 4'hF;
else
rst_sr <= rst_sr >> 1;
wire RST = rst_sr[0];
// ============================================================================
// The tester
mmcme2_test #
(
.FEEDBACK ("INTERNAL"),
.CLKFBOUT_MULT_F (10.750),
.CLKOUT0_DIVIDE_F (10.250)
)
mmcme2_test
(
.CLK (clk),
.RST (RST),
.CLKFBOUT (),
.CLKFBIN (),
.I_PWRDWN (sw[1]),
.I_CLKINSEL (sw[2]),
.O_LOCKED (led[6]),
.O_CNT (led[5:0])
);
assign led [7] = |sw[7:3];
assign jc2 = jc4;
endmodule
|
`include "../include/tune.v"
// Pentevo project (c) NedoPC 2008-2012
//
// top-level
module top(
// clocks
input fclk,
output clkz_out,
input clkz_in,
// z80
input iorq_n,
input mreq_n,
input rd_n,
input wr_n,
input m1_n,
input rfsh_n,
output int_n,
output nmi_n,
output wait_n,
output res,
inout [7:0] d,
input [15:0] a,
// zxbus and related
output csrom,
output romoe_n,
output romwe_n,
output rompg0_n,
output dos_n, // aka rompg1
output rompg2,
output rompg3,
output rompg4,
input iorqge1,
input iorqge2,
output iorq1_n,
output iorq2_n,
// DRAM
inout [15:0] rd,
output [9:0] ra,
output rwe_n,
output rucas_n,
output rlcas_n,
output rras0_n,
output rras1_n,
// video
output [1:0] vred,
output [1:0] vgrn,
output [1:0] vblu,
output vhsync,
output vvsync,
output vcsync,
// AY control and audio/tape
output ay_clk,
output ay_bdir,
output ay_bc1,
output beep,
// IDE
output [2:0] ide_a,
inout [15:0] ide_d,
output ide_dir,
input ide_rdy,
output ide_cs0_n,
output ide_cs1_n,
output ide_rs_n,
output ide_rd_n,
output ide_wr_n,
// VG93 and diskdrive
output vg_clk,
output vg_cs_n,
output vg_res_n,
output vg_hrdy,
output vg_rclk,
output vg_rawr,
output [1:0] vg_a, // disk drive selection
output vg_wrd,
output vg_side,
input step,
input vg_sl,
input vg_sr,
input vg_tr43,
input rdat_b_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd,
// serial links (atmega-fpga, sdcard)
output sdcs_n,
output sddo,
output sdclk,
input sddi,
input spics_n,
input spick,
input spido,
output spidi,
output spiint_n
);
wire dos;
wire zclk; // z80 clock for short
wire zpos,zneg;
wire rst_n; // global reset
wire rrdy;
wire [15:0] rddata;
wire [4:0] rompg;
wire [7:0] zports_dout;
wire zports_dataout;
wire porthit;
wire [39:0] kbd_data;
wire [ 7:0] mus_data;
wire kbd_stb,mus_xstb,mus_ystb,mus_btnstb,kj_stb;
wire [ 4:0] kbd_port_data;
wire [ 4:0] kj_port_data;
wire [ 7:0] mus_port_data;
wire [7:0] wait_read,wait_write;
wire wait_rnw;
wire wait_start_gluclock;
wire wait_start_comport;
wire wait_end;
wire [7:0] gluclock_addr;
wire [2:0] comport_addr;
wire [6:0] waits;
// config signals
wire [7:0] not_used;
wire cfg_vga_on;
// nmi signals
wire gen_nmi;
wire clr_nmi;
wire in_nmi;
wire [1:0] set_nmi;
wire imm_nmi;
// breakpoint signals
wire brk_ena;
wire [15:0] brk_addr;
wire tape_in;
wire [15:0] ideout;
wire [15:0] idein;
wire idedataout;
wire [7:0] zmem_dout;
wire zmem_dataout;
reg [3:0] ayclk_gen;
wire [7:0] received;
wire [7:0] tobesent;
wire intrq,drq;
wire vg_wrFF;
assign zclk = clkz_in;
// RESETTER
wire genrst;
resetter myrst( .clk(fclk),
.rst_in_n(~genrst),
.rst_out_n(rst_n) );
defparam myrst.RST_CNT_SIZE = 6;
assign nmi_n=gen_nmi ? 1'b0 : 1'bZ;
assign res= ~rst_n;
assign ide_rs_n = rst_n;
assign ide_d = idedataout ? ideout : 16'hZZZZ;
assign idein = ide_d;
assign ide_dir = ~idedataout;
wire [7:0] peff7;
wire [7:0] p7ffd;
wire romrw_en;
wire cpm_n;
wire fnt_wr;
wire cpu_req,cpu_rnw,cpu_wrbsel,cpu_strobe;
wire [20:0] cpu_addr;
wire [15:0] cpu_rddata;
wire [7:0] cpu_wrdata;
wire cbeg,post_cbeg,pre_cend,cend;
wire go;
// AVR SDcard control
wire avr_lock_claim,
avr_lock_grant,
avr_sdcs_n,
avr_sd_start;
wire [7:0] avr_sd_datain;
wire [7:0] avr_sd_dataout;
// ZX SDcard control
wire zx_sdcs_n_val,
zx_sdcs_n_stb,
zx_sd_start;
wire [7:0] zx_sd_datain;
wire [7:0] zx_sd_dataout;
wire tape_read; // data for tapein
wire beeper_mux; // what is mixed to FPGA beeper output - beeper (0) or tapeout (1)
wire [2:0] atm_scr_mode;
wire atm_turbo;
wire beeper_wr, covox_wr;
wire [5:0] palcolor; // palette readback
wire [1:0] int_turbo;
wire cpu_next;
wire cpu_stall;
wire external_port;
//AY control
always @(posedge fclk)
begin
ayclk_gen <= ayclk_gen + 4'd1;
end
assign ay_clk = ayclk_gen[3];
// fix ATM2-style ROM addressing for PENT-like ROM layout.
// this causes compications when writing to the flashROM from Z80
// and need to split and re-build old ATM romfiles before burning in
// flash
// wire [1:0] adr_fix;
// assign adr_fix = ~{ rompg[0], rompg[1] };
// assign rompg0_n = ~adr_fix[0];
// assign dos_n = adr_fix[1];
// assign rompg2 = 1'b0;//rompg[2];
// assign rompg3 = 1'b0;//rompg[3];
// assign rompg4 = 1'b0;//rompg[4];
assign rompg0_n = ~rompg[0];
assign dos_n = rompg[1];
assign rompg2 = rompg[2];
assign rompg3 = rompg[3];
assign rompg4 = rompg[4];
wire [3:0] zclk_stall;
zclock zclock
(
.fclk(fclk), .rst_n(rst_n), .zclk(zclk), .rfsh_n(rfsh_n), .zclk_out(clkz_out),
.zpos(zpos), .zneg(zneg),
.turbo( {atm_turbo,~(peff7[4])} ), .pre_cend(pre_cend), .cbeg(cbeg),
.zclk_stall( cpu_stall | (|zclk_stall) ), .int_turbo(int_turbo),
.external_port(external_port), .iorq_n(iorq_n), .m1_n(m1_n)
);
wire [7:0] dout_ram;
wire ena_ram;
wire [7:0] dout_ports;
wire ena_ports;
wire [3:0] border;
wire drive_ff;
wire atm_palwr;
wire [5:0] atm_paldata;
wire [7:0] fontrom_readback;
wire int_start;
// data bus out: either RAM data or internal ports data or 0xFF with unused ports
assign d = ena_ram ? dout_ram : ( ena_ports ? dout_ports : ( drive_ff ? 8'hFF : 8'bZZZZZZZZ ) );
zbus zxbus( .iorq_n(iorq_n), .rd_n(rd_n), .wr_n(wr_n), .m1_n(m1_n),
.iorq1_n(iorq1_n), .iorq2_n(iorq2_n), .iorqge1(iorqge1), .iorqge2(iorqge2),
.porthit(porthit), .drive_ff(drive_ff) );
/////////////////////////////////////
// ATM memory pagers instantiation //
/////////////////////////////////////
wire pager_off;
wire pent1m_ROM;
wire [ 5:0] pent1m_page;
wire pent1m_ram0_0;
wire pent1m_1m_on;
wire atmF7_wr_fclk;
wire [3:0] dos_turn_off,
dos_turn_on;
wire [ 7:0] page [0:3];
wire [ 3:0] romnram;
// for reading back data via xxBE port
wire [ 7:0] rd_pages [0:7];
wire [ 7:0] rd_ramnrom;
wire [ 7:0] rd_dos7ffd;
generate
genvar i;
for(i=0;i<4;i=i+1)
begin : instantiate_atm_pagers
atm_pager #( .ADDR(i) )
atm_pager( .rst_n(rst_n),
.fclk (fclk),
.zpos (zpos),
.zneg (zneg),
.za(a),
.zd(d),
.mreq_n(mreq_n),
.rd_n (rd_n),
.m1_n (m1_n),
.pager_off(pager_off),
.pent1m_ROM (pent1m_ROM),
.pent1m_page (pent1m_page),
.pent1m_ram0_0(pent1m_ram0_0),
.pent1m_1m_on (pent1m_1m_on),
.in_nmi(in_nmi),
.atmF7_wr(atmF7_wr_fclk),
.dos(dos),
.dos_turn_on (dos_turn_on[i]),
.dos_turn_off(dos_turn_off[i]),
.zclk_stall(zclk_stall[i]),
.page (page[i]),
.romnram(romnram[i]),
.rd_page0 (rd_pages[i ]),
.rd_page1 (rd_pages[i+4]),
.rd_ramnrom( {rd_ramnrom[i+4], rd_ramnrom[i]} ),
.rd_dos7ffd( {rd_dos7ffd[i+4], rd_dos7ffd[i]} )
);
end
endgenerate
///////////////////////////
// DOS signal controller //
///////////////////////////
zdos zdos( .rst_n(rst_n),
.fclk(fclk),
.dos_turn_on ( |dos_turn_on ),
.dos_turn_off( |dos_turn_off ),
.cpm_n(cpm_n),
.dos(dos)
);
///////////////////////////
// Z80 memory controller //
///////////////////////////
zmem z80mem
(
.fclk (fclk ),
.rst_n(rst_n),
.zpos(zpos),
.zneg(zneg),
.cbeg (cbeg ),
.post_cbeg(post_cbeg),
.pre_cend (pre_cend ),
.cend (cend ),
.za (a ),
.zd_in (d ),
.zd_out(dout_ram),
.zd_ena(ena_ram ),
.m1_n (m1_n ),
.rfsh_n(rfsh_n ),
.iorq_n(iorq_n ),
.mreq_n(mreq_n ),
.rd_n (rd_n ),
.wr_n (wr_n ),
.win0_romnram(romnram[0]),
.win1_romnram(romnram[1]),
.win2_romnram(romnram[2]),
.win3_romnram(romnram[3]),
.win0_page(page[0]),
.win1_page(page[1]),
.win2_page(page[2]),
.win3_page(page[3]),
.romrw_en(romrw_en),
.rompg (rompg ),
.romoe_n(romoe_n),
.romwe_n(romwe_n),
.csrom (csrom ),
.cpu_req (cpu_req ),
.cpu_rnw (cpu_rnw ),
.cpu_wrbsel(cpu_wrbsel),
.cpu_strobe(cpu_strobe),
.cpu_addr (cpu_addr ),
.cpu_wrdata(cpu_wrdata),
.cpu_rddata(cpu_rddata),
.cpu_stall (cpu_stall ),
.cpu_next (cpu_next ),
.int_turbo(int_turbo)
);
wire [20:0] daddr;
wire dreq;
wire drnw;
wire [15:0] drddata;
wire [15:0] dwrdata;
wire [1:0] dbsel;
dram dram( .clk(fclk),
.rst_n(rst_n),
.addr(daddr),
.req(dreq),
.rnw(drnw),
.cbeg(cbeg),
.rrdy(drrdy),
.rddata(drddata),
.wrdata(dwrdata),
.bsel(dbsel),
.ra(ra),
.rd(rd),
.rwe_n(rwe_n),
.rucas_n(rucas_n),
.rlcas_n(rlcas_n),
.rras0_n(rras0_n),
.rras1_n(rras1_n)
);
wire [1:0] bw;
wire [20:0] video_addr;
wire [15:0] video_data;
wire video_strobe;
wire video_next;
arbiter dramarb( .clk(fclk),
.rst_n(rst_n),
.dram_addr(daddr),
.dram_req(dreq),
.dram_rnw(drnw),
.dram_cbeg(cbeg),
.dram_rrdy(drrdy),
.dram_bsel(dbsel),
.dram_rddata(drddata),
.dram_wrdata(dwrdata),
.post_cbeg(post_cbeg),
.pre_cend (pre_cend ),
.cend (cend ),
.go(go),
.bw(bw),
.video_addr(video_addr),
.video_data(video_data),
.video_strobe(video_strobe),
.video_next(video_next),
//.cpu_waitcyc(cpu_waitcyc),
.cpu_next (cpu_next),
.cpu_req(cpu_req),
.cpu_rnw(cpu_rnw),
.cpu_addr(cpu_addr),
.cpu_wrbsel(cpu_wrbsel),
.cpu_wrdata(cpu_wrdata),
.cpu_rddata(cpu_rddata),
.cpu_strobe(cpu_strobe) );
video_top video_top(
.clk(fclk),
.vred(vred),
.vgrn(vgrn),
.vblu(vblu),
.vhsync(vhsync),
.vvsync(vvsync),
.vcsync(vcsync),
.zxborder(border),
.pent_vmode( {peff7[0],peff7[5]} ),
.atm_vmode (atm_scr_mode),
.scr_page(p7ffd[3]),
.vga_on(cfg_vga_on),
.cbeg (cbeg ),
.post_cbeg(post_cbeg),
.pre_cend (pre_cend ),
.cend (cend ),
.video_go (go ),
.video_bw (bw ),
.video_addr (video_addr ),
.video_data (video_data ),
.video_strobe(video_strobe),
.video_next (video_next ),
.atm_palwr (atm_palwr ),
.atm_paldata(atm_paldata),
.int_start(int_start),
.fnt_a (a[10:0]),
.fnt_d (d ),
.fnt_wr(fnt_wr ),
.palcolor(palcolor),
.fontrom_readback(fontrom_readback)
);
slavespi slavespi(
.fclk(fclk), .rst_n(rst_n),
.spics_n(spics_n), .spidi(spidi),
.spido(spido), .spick(spick),
.status_in({/* wait_rnw */ wr_n, waits[6:0]}), .genrst(genrst),
.kbd_out(kbd_data),
.kbd_stb(kbd_stb), .mus_out(mus_data),
.mus_xstb(mus_xstb), .mus_ystb(mus_ystb),
.mus_btnstb(mus_btnstb), .kj_stb(kj_stb),
.gluclock_addr(gluclock_addr),
.comport_addr (comport_addr),
.wait_write(wait_write),
.wait_read(wait_read),
.wait_rnw(wait_rnw),
.wait_end(wait_end),
.config0( { not_used[7:4], beeper_mux, tape_read, set_nmi[0], cfg_vga_on} ),
.sd_lock_out(avr_lock_claim),
.sd_lock_in (avr_lock_grant),
.sd_cs_n (avr_sdcs_n ),
.sd_start (avr_sd_start ),
.sd_datain (avr_sd_datain ),
.sd_dataout (avr_sd_dataout)
);
zkbdmus zkbdmus( .fclk(fclk), .rst_n(rst_n),
.kbd_in(kbd_data), .kbd_stb(kbd_stb),
.mus_in(mus_data), .mus_xstb(mus_xstb),
.mus_ystb(mus_ystb), .mus_btnstb(mus_btnstb),
.kj_stb(kj_stb), .kj_data(kj_port_data),
.zah(a[15:8]), .kbd_data(kbd_port_data),
.mus_data(mus_port_data)
);
zports zports( .zclk(zclk), .fclk(fclk), .rst_n(rst_n), .zpos(zpos), .zneg(zneg),
.din(d), .dout(dout_ports), .dataout(ena_ports),
.a(a), .iorq_n(iorq_n), .rd_n(rd_n), .wr_n(wr_n), .porthit(porthit),
.ay_bdir(ay_bdir), .ay_bc1(ay_bc1), .border(border),
.p7ffd(p7ffd), .peff7(peff7), .mreq_n(mreq_n), .m1_n(m1_n), .dos(dos),
.vg_intrq(intrq), .vg_drq(drq), .vg_wrFF(vg_wrFF), .vg_cs_n(vg_cs_n),
.idein(idein), .ideout(ideout), .idedataout(idedataout),
.ide_a(ide_a), .ide_cs0_n(ide_cs0_n), .ide_cs1_n(ide_cs1_n),
.ide_wr_n(ide_wr_n), .ide_rd_n(ide_rd_n),
.sd_cs_n_val(zx_sdcs_n_val),
.sd_cs_n_stb(zx_sdcs_n_stb),
.sd_start (zx_sd_start ),
.sd_datain (zx_sd_datain ),
.sd_dataout (zx_sd_dataout),
.keys_in(kbd_port_data),
.mus_in (mus_port_data),
.kj_in (kj_port_data ),
.tape_read(tape_read),
.gluclock_addr(gluclock_addr),
.comport_addr (comport_addr ),
.wait_start_gluclock(wait_start_gluclock),
.wait_start_comport (wait_start_comport ),
.wait_rnw (wait_rnw ),
.wait_write(wait_write),
`ifndef SIMULATE
.wait_read (wait_read ),
`else
.wait_read(8'hFF),
`endif
.atmF7_wr_fclk(atmF7_wr_fclk),
.atm_scr_mode(atm_scr_mode),
.atm_turbo (atm_turbo),
.atm_pen (pager_off),
.atm_cpm_n (cpm_n),
.atm_pen2 (atm_pen2),
.romrw_en(romrw_en),
.pent1m_ram0_0(pent1m_ram0_0),
.pent1m_1m_on (pent1m_1m_on),
.pent1m_page (pent1m_page),
.pent1m_ROM (pent1m_ROM),
.atm_palwr (atm_palwr ),
.atm_paldata(atm_paldata),
.beeper_wr(beeper_wr),
.covox_wr (covox_wr ),
.fnt_wr(fnt_wr),
.clr_nmi(clr_nmi),
.pages(~{ rd_pages[7], rd_pages[6],
rd_pages[5], rd_pages[4],
rd_pages[3], rd_pages[2],
rd_pages[1], rd_pages[0] }),
.ramnroms( rd_ramnrom ),
.dos7ffds( rd_dos7ffd ),
.palcolor(palcolor),
.fontrom_readback(fontrom_readback),
.external_port(external_port),
.set_nmi(set_nmi[1]),
.brk_ena (brk_ena ),
.brk_addr(brk_addr)
);
zint zint(
.fclk(fclk),
.zpos(zpos),
.zneg(zneg),
.int_start(int_start),
.iorq_n(iorq_n),
.m1_n (m1_n ),
.int_n(int_n)
);
znmi znmi
(
.rst_n(rst_n),
.fclk(fclk),
.zpos(zpos),
.zneg(zneg),
.rfsh_n(rfsh_n),
.m1_n (m1_n ),
.mreq_n(mreq_n),
.csrom (csrom ),
.a (a ),
.int_start(int_start),
.set_nmi(set_nmi),
.imm_nmi(imm_nmi),
.clr_nmi(clr_nmi),
.in_nmi (in_nmi ),
.gen_nmi(gen_nmi)
);
zbreak zbreak
(
.rst_n(rst_n),
.fclk(fclk),
.zpos(zpos),
.zneg(zneg),
.m1_n (m1_n ),
.mreq_n(mreq_n),
.a (a ),
.imm_nmi(imm_nmi),
.brk_ena (brk_ena ),
.brk_addr(brk_addr)
);
zwait zwait( .wait_start_gluclock(wait_start_gluclock),
.wait_start_comport (wait_start_comport),
.wait_end(wait_end),
.rst_n(rst_n),
.wait_n(wait_n),
.waits(waits),
.spiint_n(spiint_n) );
wire [1:0] vg_ddrv;
assign vg_a[0] = vg_ddrv[0] ? 1'b1 : 1'b0; // possibly open drain?
assign vg_a[1] = vg_ddrv[1] ? 1'b1 : 1'b0;
vg93 vgshka( .zclk(zclk), .rst_n(rst_n), .fclk(fclk), .vg_clk(vg_clk),
.vg_res_n(vg_res_n), .din(d), .intrq(intrq), .drq(drq), .vg_wrFF(vg_wrFF),
.vg_hrdy(vg_hrdy), .vg_rclk(vg_rclk), .vg_rawr(vg_rawr), .vg_a(vg_ddrv),
.vg_wrd(vg_wrd), .vg_side(vg_side), .step(step), .vg_sl(vg_sl), .vg_sr(vg_sr),
.vg_tr43(vg_tr43), .rdat_n(rdat_b_n), .vg_wf_de(vg_wf_de), .vg_drq(vg_drq),
.vg_irq(vg_irq), .vg_wd(vg_wd) );
// spi2 zspi( .clock(fclk), .sck(sdclk), .sdo(sddo), .sdi(sddi), .start(sd_start),
// .speed(2'b00), .din(sd_datain), .dout(sd_dataout) );
spihub spihub(
.fclk (fclk ),
.rst_n(rst_n),
.sdcs_n(sdcs_n),
.sdclk (sdclk ),
.sddo (sddo ),
.sddi (sddi ),
.zx_sdcs_n_val(zx_sdcs_n_val),
.zx_sdcs_n_stb(zx_sdcs_n_stb),
.zx_sd_start (zx_sd_start ),
.zx_sd_datain (zx_sd_datain ),
.zx_sd_dataout(zx_sd_dataout),
.avr_lock_in (avr_lock_claim),
.avr_lock_out (avr_lock_grant),
.avr_sdcs_n (avr_sdcs_n ),
.avr_sd_start (avr_sd_start ),
.avr_sd_datain (avr_sd_datain ),
.avr_sd_dataout(avr_sd_dataout)
);
//////////////////////////////////////
// sound: beeper, tapeout and covox //
//////////////////////////////////////
sound sound(
.clk(fclk),
.din(d),
.beeper_wr(beeper_wr),
.covox_wr (covox_wr ),
.beeper_mux(beeper_mux),
.sound_bit(beep)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SEDFXBP_FUNCTIONAL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_pg/sky130_fd_sc_hs__u_df_p_pg.v"
`celldefine
module sky130_fd_sc_hs__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hs__u_mux_2_1 u_mux_21 (de_d , buf_Q, D, DE );
sky130_fd_sc_hs__u_df_p_pg `UNIT_DELAY u_df_p_pg0 (buf_Q , mux_out, CLK, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXBP_FUNCTIONAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// Each core or library found in this collection may have its own licensing terms.
// The user should keep this in in mind while exploring these cores.
//
// Redistribution and use in source and binary forms,
// with or without modification of this file, are permitted under the terms of either
// (at the option of the user):
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory, or at:
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
//
// OR
//
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_perfect_shuffle #(
parameter NUM_GROUPS = 2,
parameter WORDS_PER_GROUP = 2,
parameter WORD_WIDTH = 8
) (
input [NUM_GROUPS*WORDS_PER_GROUP*WORD_WIDTH-1:0] data_in,
output [NUM_GROUPS*WORDS_PER_GROUP*WORD_WIDTH-1:0] data_out
);
/*
* Performs the perfect shuffle operation.
*
* The perfect shuffle splits the input vector into NUM_GROUPS groups and then
* each group in WORDS_PER_GROUP. The output vector consists of WORDS_PER_GROUP
* groups and each group has NUM_GROUPS words. The data is remapped, so that
* the i-th word of the j-th word in the output vector is the j-th word of the
* i-th group of the input vector.
* The inverse operation of the perfect shuffle is the perfect shuffle with
* both parameters swapped.
* I.e. [perfect_suffle B A [perfect_shuffle A B data]] == data
*
* Examples:
* NUM_GROUPS = 2, WORDS_PER_GROUP = 4
* [A B C D a b c d] => [A a B b C c D d]
* NUM_GROUPS = 4, WORDS_PER_GROUP = 2
* [A a B b C c D d] => [A B C D a b c d]
* NUM_GROUPS = 3, WORDS_PER_GROUP = 2
* [A B a b 1 2] => [A a 1 B b 2]
*/
generate
genvar i;
genvar j;
for (i = 0; i < NUM_GROUPS; i = i + 1) begin: shuffle_outer
for (j = 0; j < WORDS_PER_GROUP; j = j + 1) begin: shuffle_inner
localparam src_lsb = (j + i * WORDS_PER_GROUP) * WORD_WIDTH;
localparam dst_lsb = (i + j * NUM_GROUPS) * WORD_WIDTH;
assign data_out[dst_lsb+:WORD_WIDTH] = data_in[src_lsb+:WORD_WIDTH];
end
end
endgenerate
endmodule
|
// system_acl_iface.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_acl_iface (
input wire config_clk_clk, // config_clk.clk
input wire reset_n, // global_reset.reset_n
input wire kernel_pll_refclk_clk, // kernel_pll_refclk.clk
output wire kernel_clk_clk, // kernel_clk.clk
output wire kernel_reset_reset_n, // kernel_reset.reset_n
output wire kernel_clk2x_clk, // kernel_clk2x.clk
output wire kernel_mem0_waitrequest, // kernel_mem0.waitrequest
output wire [255:0] kernel_mem0_readdata, // .readdata
output wire kernel_mem0_readdatavalid, // .readdatavalid
input wire [4:0] kernel_mem0_burstcount, // .burstcount
input wire [255:0] kernel_mem0_writedata, // .writedata
input wire [29:0] kernel_mem0_address, // .address
input wire kernel_mem0_write, // .write
input wire kernel_mem0_read, // .read
input wire [31:0] kernel_mem0_byteenable, // .byteenable
input wire kernel_mem0_debugaccess, // .debugaccess
output wire acl_kernel_clk_kernel_pll_locked_export, // acl_kernel_clk_kernel_pll_locked.export
output wire kernel_clk_snoop_clk, // kernel_clk_snoop.clk
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
output wire peripheral_hps_io_emac1_inst_TX_CLK, // peripheral.hps_io_emac1_inst_TX_CLK
output wire peripheral_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire peripheral_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire peripheral_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire peripheral_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire peripheral_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire peripheral_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire peripheral_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire peripheral_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire peripheral_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire peripheral_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire peripheral_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire peripheral_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire peripheral_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire peripheral_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire peripheral_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire peripheral_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire peripheral_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire peripheral_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire peripheral_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
input wire peripheral_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire peripheral_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire peripheral_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire peripheral_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire peripheral_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
output wire [1:0] acl_internal_memorg_kernel_mode, // acl_internal_memorg_kernel.mode
input wire [0:0] kernel_irq_irq, // kernel_irq.irq
input wire kernel_cra_waitrequest, // kernel_cra.waitrequest
input wire [63:0] kernel_cra_readdata, // .readdata
input wire kernel_cra_readdatavalid, // .readdatavalid
output wire [0:0] kernel_cra_burstcount, // .burstcount
output wire [63:0] kernel_cra_writedata, // .writedata
output wire [29:0] kernel_cra_address, // .address
output wire kernel_cra_write, // .write
output wire kernel_cra_read, // .read
output wire [7:0] kernel_cra_byteenable, // .byteenable
output wire kernel_cra_debugaccess, // .debugaccess
output wire [1:0] kernel_interface_acl_bsp_memorg_host_mode // kernel_interface_acl_bsp_memorg_host.mode
);
wire pll_outclk0_clk; // pll:outclk_0 -> [address_span_extender_kernel:clk, clock_cross_kernel_mem1:m0_clk, hps:f2h_sdram0_clk, mm_interconnect_1:pll_outclk0_clk, mm_interconnect_2:pll_outclk0_clk, rst_controller_001:clk, rst_controller_003:clk]
wire [1:0] hps_h2f_lw_axi_master_awburst; // hps:h2f_lw_AWBURST -> mm_interconnect_0:hps_h2f_lw_axi_master_awburst
wire [3:0] hps_h2f_lw_axi_master_arlen; // hps:h2f_lw_ARLEN -> mm_interconnect_0:hps_h2f_lw_axi_master_arlen
wire [3:0] hps_h2f_lw_axi_master_wstrb; // hps:h2f_lw_WSTRB -> mm_interconnect_0:hps_h2f_lw_axi_master_wstrb
wire hps_h2f_lw_axi_master_wready; // mm_interconnect_0:hps_h2f_lw_axi_master_wready -> hps:h2f_lw_WREADY
wire [11:0] hps_h2f_lw_axi_master_rid; // mm_interconnect_0:hps_h2f_lw_axi_master_rid -> hps:h2f_lw_RID
wire hps_h2f_lw_axi_master_rready; // hps:h2f_lw_RREADY -> mm_interconnect_0:hps_h2f_lw_axi_master_rready
wire [3:0] hps_h2f_lw_axi_master_awlen; // hps:h2f_lw_AWLEN -> mm_interconnect_0:hps_h2f_lw_axi_master_awlen
wire [11:0] hps_h2f_lw_axi_master_wid; // hps:h2f_lw_WID -> mm_interconnect_0:hps_h2f_lw_axi_master_wid
wire [3:0] hps_h2f_lw_axi_master_arcache; // hps:h2f_lw_ARCACHE -> mm_interconnect_0:hps_h2f_lw_axi_master_arcache
wire hps_h2f_lw_axi_master_wvalid; // hps:h2f_lw_WVALID -> mm_interconnect_0:hps_h2f_lw_axi_master_wvalid
wire [20:0] hps_h2f_lw_axi_master_araddr; // hps:h2f_lw_ARADDR -> mm_interconnect_0:hps_h2f_lw_axi_master_araddr
wire [2:0] hps_h2f_lw_axi_master_arprot; // hps:h2f_lw_ARPROT -> mm_interconnect_0:hps_h2f_lw_axi_master_arprot
wire [2:0] hps_h2f_lw_axi_master_awprot; // hps:h2f_lw_AWPROT -> mm_interconnect_0:hps_h2f_lw_axi_master_awprot
wire [31:0] hps_h2f_lw_axi_master_wdata; // hps:h2f_lw_WDATA -> mm_interconnect_0:hps_h2f_lw_axi_master_wdata
wire hps_h2f_lw_axi_master_arvalid; // hps:h2f_lw_ARVALID -> mm_interconnect_0:hps_h2f_lw_axi_master_arvalid
wire [3:0] hps_h2f_lw_axi_master_awcache; // hps:h2f_lw_AWCACHE -> mm_interconnect_0:hps_h2f_lw_axi_master_awcache
wire [11:0] hps_h2f_lw_axi_master_arid; // hps:h2f_lw_ARID -> mm_interconnect_0:hps_h2f_lw_axi_master_arid
wire [1:0] hps_h2f_lw_axi_master_arlock; // hps:h2f_lw_ARLOCK -> mm_interconnect_0:hps_h2f_lw_axi_master_arlock
wire [1:0] hps_h2f_lw_axi_master_awlock; // hps:h2f_lw_AWLOCK -> mm_interconnect_0:hps_h2f_lw_axi_master_awlock
wire [20:0] hps_h2f_lw_axi_master_awaddr; // hps:h2f_lw_AWADDR -> mm_interconnect_0:hps_h2f_lw_axi_master_awaddr
wire [1:0] hps_h2f_lw_axi_master_bresp; // mm_interconnect_0:hps_h2f_lw_axi_master_bresp -> hps:h2f_lw_BRESP
wire hps_h2f_lw_axi_master_arready; // mm_interconnect_0:hps_h2f_lw_axi_master_arready -> hps:h2f_lw_ARREADY
wire [31:0] hps_h2f_lw_axi_master_rdata; // mm_interconnect_0:hps_h2f_lw_axi_master_rdata -> hps:h2f_lw_RDATA
wire hps_h2f_lw_axi_master_awready; // mm_interconnect_0:hps_h2f_lw_axi_master_awready -> hps:h2f_lw_AWREADY
wire [1:0] hps_h2f_lw_axi_master_arburst; // hps:h2f_lw_ARBURST -> mm_interconnect_0:hps_h2f_lw_axi_master_arburst
wire [2:0] hps_h2f_lw_axi_master_arsize; // hps:h2f_lw_ARSIZE -> mm_interconnect_0:hps_h2f_lw_axi_master_arsize
wire hps_h2f_lw_axi_master_bready; // hps:h2f_lw_BREADY -> mm_interconnect_0:hps_h2f_lw_axi_master_bready
wire hps_h2f_lw_axi_master_rlast; // mm_interconnect_0:hps_h2f_lw_axi_master_rlast -> hps:h2f_lw_RLAST
wire hps_h2f_lw_axi_master_wlast; // hps:h2f_lw_WLAST -> mm_interconnect_0:hps_h2f_lw_axi_master_wlast
wire [1:0] hps_h2f_lw_axi_master_rresp; // mm_interconnect_0:hps_h2f_lw_axi_master_rresp -> hps:h2f_lw_RRESP
wire [11:0] hps_h2f_lw_axi_master_awid; // hps:h2f_lw_AWID -> mm_interconnect_0:hps_h2f_lw_axi_master_awid
wire [11:0] hps_h2f_lw_axi_master_bid; // mm_interconnect_0:hps_h2f_lw_axi_master_bid -> hps:h2f_lw_BID
wire hps_h2f_lw_axi_master_bvalid; // mm_interconnect_0:hps_h2f_lw_axi_master_bvalid -> hps:h2f_lw_BVALID
wire [2:0] hps_h2f_lw_axi_master_awsize; // hps:h2f_lw_AWSIZE -> mm_interconnect_0:hps_h2f_lw_axi_master_awsize
wire hps_h2f_lw_axi_master_awvalid; // hps:h2f_lw_AWVALID -> mm_interconnect_0:hps_h2f_lw_axi_master_awvalid
wire hps_h2f_lw_axi_master_rvalid; // mm_interconnect_0:hps_h2f_lw_axi_master_rvalid -> hps:h2f_lw_RVALID
wire [31:0] mm_interconnect_0_version_id_s_readdata; // version_id:slave_readdata -> mm_interconnect_0:version_id_s_readdata
wire mm_interconnect_0_version_id_s_read; // mm_interconnect_0:version_id_s_read -> version_id:slave_read
wire [31:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdata; // acl_kernel_interface:kernel_cntrl_readdata -> mm_interconnect_0:acl_kernel_interface_kernel_cntrl_readdata
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_waitrequest; // acl_kernel_interface:kernel_cntrl_waitrequest -> mm_interconnect_0:acl_kernel_interface_kernel_cntrl_waitrequest
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_debugaccess; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_debugaccess -> acl_kernel_interface:kernel_cntrl_debugaccess
wire [13:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_address; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_address -> acl_kernel_interface:kernel_cntrl_address
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_read; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_read -> acl_kernel_interface:kernel_cntrl_read
wire [3:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_byteenable; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_byteenable -> acl_kernel_interface:kernel_cntrl_byteenable
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdatavalid; // acl_kernel_interface:kernel_cntrl_readdatavalid -> mm_interconnect_0:acl_kernel_interface_kernel_cntrl_readdatavalid
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_write; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_write -> acl_kernel_interface:kernel_cntrl_write
wire [31:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_writedata; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_writedata -> acl_kernel_interface:kernel_cntrl_writedata
wire [0:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_burstcount; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_burstcount -> acl_kernel_interface:kernel_cntrl_burstcount
wire [31:0] mm_interconnect_0_acl_kernel_clk_ctrl_readdata; // acl_kernel_clk:ctrl_readdata -> mm_interconnect_0:acl_kernel_clk_ctrl_readdata
wire mm_interconnect_0_acl_kernel_clk_ctrl_waitrequest; // acl_kernel_clk:ctrl_waitrequest -> mm_interconnect_0:acl_kernel_clk_ctrl_waitrequest
wire mm_interconnect_0_acl_kernel_clk_ctrl_debugaccess; // mm_interconnect_0:acl_kernel_clk_ctrl_debugaccess -> acl_kernel_clk:ctrl_debugaccess
wire [10:0] mm_interconnect_0_acl_kernel_clk_ctrl_address; // mm_interconnect_0:acl_kernel_clk_ctrl_address -> acl_kernel_clk:ctrl_address
wire mm_interconnect_0_acl_kernel_clk_ctrl_read; // mm_interconnect_0:acl_kernel_clk_ctrl_read -> acl_kernel_clk:ctrl_read
wire [3:0] mm_interconnect_0_acl_kernel_clk_ctrl_byteenable; // mm_interconnect_0:acl_kernel_clk_ctrl_byteenable -> acl_kernel_clk:ctrl_byteenable
wire mm_interconnect_0_acl_kernel_clk_ctrl_readdatavalid; // acl_kernel_clk:ctrl_readdatavalid -> mm_interconnect_0:acl_kernel_clk_ctrl_readdatavalid
wire mm_interconnect_0_acl_kernel_clk_ctrl_write; // mm_interconnect_0:acl_kernel_clk_ctrl_write -> acl_kernel_clk:ctrl_write
wire [31:0] mm_interconnect_0_acl_kernel_clk_ctrl_writedata; // mm_interconnect_0:acl_kernel_clk_ctrl_writedata -> acl_kernel_clk:ctrl_writedata
wire [0:0] mm_interconnect_0_acl_kernel_clk_ctrl_burstcount; // mm_interconnect_0:acl_kernel_clk_ctrl_burstcount -> acl_kernel_clk:ctrl_burstcount
wire clock_cross_kernel_mem1_m0_waitrequest; // mm_interconnect_1:clock_cross_kernel_mem1_m0_waitrequest -> clock_cross_kernel_mem1:m0_waitrequest
wire [255:0] clock_cross_kernel_mem1_m0_readdata; // mm_interconnect_1:clock_cross_kernel_mem1_m0_readdata -> clock_cross_kernel_mem1:m0_readdata
wire clock_cross_kernel_mem1_m0_debugaccess; // clock_cross_kernel_mem1:m0_debugaccess -> mm_interconnect_1:clock_cross_kernel_mem1_m0_debugaccess
wire [29:0] clock_cross_kernel_mem1_m0_address; // clock_cross_kernel_mem1:m0_address -> mm_interconnect_1:clock_cross_kernel_mem1_m0_address
wire clock_cross_kernel_mem1_m0_read; // clock_cross_kernel_mem1:m0_read -> mm_interconnect_1:clock_cross_kernel_mem1_m0_read
wire [31:0] clock_cross_kernel_mem1_m0_byteenable; // clock_cross_kernel_mem1:m0_byteenable -> mm_interconnect_1:clock_cross_kernel_mem1_m0_byteenable
wire clock_cross_kernel_mem1_m0_readdatavalid; // mm_interconnect_1:clock_cross_kernel_mem1_m0_readdatavalid -> clock_cross_kernel_mem1:m0_readdatavalid
wire [255:0] clock_cross_kernel_mem1_m0_writedata; // clock_cross_kernel_mem1:m0_writedata -> mm_interconnect_1:clock_cross_kernel_mem1_m0_writedata
wire clock_cross_kernel_mem1_m0_write; // clock_cross_kernel_mem1:m0_write -> mm_interconnect_1:clock_cross_kernel_mem1_m0_write
wire [4:0] clock_cross_kernel_mem1_m0_burstcount; // clock_cross_kernel_mem1:m0_burstcount -> mm_interconnect_1:clock_cross_kernel_mem1_m0_burstcount
wire [255:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdata; // address_span_extender_kernel:avs_s0_readdata -> mm_interconnect_1:address_span_extender_kernel_windowed_slave_readdata
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_waitrequest; // address_span_extender_kernel:avs_s0_waitrequest -> mm_interconnect_1:address_span_extender_kernel_windowed_slave_waitrequest
wire [24:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_address; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_address -> address_span_extender_kernel:avs_s0_address
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_read; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_read -> address_span_extender_kernel:avs_s0_read
wire [31:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_byteenable; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_byteenable -> address_span_extender_kernel:avs_s0_byteenable
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdatavalid; // address_span_extender_kernel:avs_s0_readdatavalid -> mm_interconnect_1:address_span_extender_kernel_windowed_slave_readdatavalid
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_write; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_write -> address_span_extender_kernel:avs_s0_write
wire [255:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_writedata; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_writedata -> address_span_extender_kernel:avs_s0_writedata
wire [4:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_burstcount; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_burstcount -> address_span_extender_kernel:avs_s0_burstcount
wire address_span_extender_kernel_expanded_master_waitrequest; // mm_interconnect_2:address_span_extender_kernel_expanded_master_waitrequest -> address_span_extender_kernel:avm_m0_waitrequest
wire [255:0] address_span_extender_kernel_expanded_master_readdata; // mm_interconnect_2:address_span_extender_kernel_expanded_master_readdata -> address_span_extender_kernel:avm_m0_readdata
wire [31:0] address_span_extender_kernel_expanded_master_address; // address_span_extender_kernel:avm_m0_address -> mm_interconnect_2:address_span_extender_kernel_expanded_master_address
wire address_span_extender_kernel_expanded_master_read; // address_span_extender_kernel:avm_m0_read -> mm_interconnect_2:address_span_extender_kernel_expanded_master_read
wire [31:0] address_span_extender_kernel_expanded_master_byteenable; // address_span_extender_kernel:avm_m0_byteenable -> mm_interconnect_2:address_span_extender_kernel_expanded_master_byteenable
wire address_span_extender_kernel_expanded_master_readdatavalid; // mm_interconnect_2:address_span_extender_kernel_expanded_master_readdatavalid -> address_span_extender_kernel:avm_m0_readdatavalid
wire address_span_extender_kernel_expanded_master_write; // address_span_extender_kernel:avm_m0_write -> mm_interconnect_2:address_span_extender_kernel_expanded_master_write
wire [255:0] address_span_extender_kernel_expanded_master_writedata; // address_span_extender_kernel:avm_m0_writedata -> mm_interconnect_2:address_span_extender_kernel_expanded_master_writedata
wire [4:0] address_span_extender_kernel_expanded_master_burstcount; // address_span_extender_kernel:avm_m0_burstcount -> mm_interconnect_2:address_span_extender_kernel_expanded_master_burstcount
wire [255:0] mm_interconnect_2_hps_f2h_sdram0_data_readdata; // hps:f2h_sdram0_READDATA -> mm_interconnect_2:hps_f2h_sdram0_data_readdata
wire mm_interconnect_2_hps_f2h_sdram0_data_waitrequest; // hps:f2h_sdram0_WAITREQUEST -> mm_interconnect_2:hps_f2h_sdram0_data_waitrequest
wire [26:0] mm_interconnect_2_hps_f2h_sdram0_data_address; // mm_interconnect_2:hps_f2h_sdram0_data_address -> hps:f2h_sdram0_ADDRESS
wire mm_interconnect_2_hps_f2h_sdram0_data_read; // mm_interconnect_2:hps_f2h_sdram0_data_read -> hps:f2h_sdram0_READ
wire [31:0] mm_interconnect_2_hps_f2h_sdram0_data_byteenable; // mm_interconnect_2:hps_f2h_sdram0_data_byteenable -> hps:f2h_sdram0_BYTEENABLE
wire mm_interconnect_2_hps_f2h_sdram0_data_readdatavalid; // hps:f2h_sdram0_READDATAVALID -> mm_interconnect_2:hps_f2h_sdram0_data_readdatavalid
wire mm_interconnect_2_hps_f2h_sdram0_data_write; // mm_interconnect_2:hps_f2h_sdram0_data_write -> hps:f2h_sdram0_WRITE
wire [255:0] mm_interconnect_2_hps_f2h_sdram0_data_writedata; // mm_interconnect_2:hps_f2h_sdram0_data_writedata -> hps:f2h_sdram0_WRITEDATA
wire [7:0] mm_interconnect_2_hps_f2h_sdram0_data_burstcount; // mm_interconnect_2:hps_f2h_sdram0_data_burstcount -> hps:f2h_sdram0_BURSTCOUNT
wire irq_mapper_receiver0_irq; // acl_kernel_interface:kernel_irq_to_host_irq -> irq_mapper:receiver0_irq
wire [31:0] hps_f2h_irq0_irq; // irq_mapper:sender_irq -> hps:f2h_irq_p0
wire [31:0] hps_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps:f2h_irq_p1
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [acl_kernel_clk:reset_reset_n, acl_kernel_interface:reset_reset_n, acl_kernel_interface:sw_reset_in_reset, mm_interconnect_0:version_id_clk_reset_reset_bridge_in_reset_reset, version_id:resetn]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [address_span_extender_kernel:reset, clock_cross_kernel_mem1:m0_reset, mm_interconnect_1:clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset, mm_interconnect_2:address_span_extender_kernel_reset_reset_bridge_in_reset_reset]
wire acl_kernel_interface_sw_reset_export_reset; // acl_kernel_interface:sw_reset_export_reset_n -> rst_controller_001:reset_in0
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> mm_interconnect_0:hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
wire hps_h2f_reset_reset; // hps:h2f_rst_n -> [rst_controller_002:reset_in0, rst_controller_003:reset_in0]
wire rst_controller_003_reset_out_reset; // rst_controller_003:reset_out -> mm_interconnect_2:hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset
system_acl_iface_acl_kernel_clk acl_kernel_clk (
.kernel_clk2x_clk (kernel_clk2x_clk), // kernel_clk2x.clk
.pll_refclk_clk (kernel_pll_refclk_clk), // pll_refclk.clk
.ctrl_waitrequest (mm_interconnect_0_acl_kernel_clk_ctrl_waitrequest), // ctrl.waitrequest
.ctrl_readdata (mm_interconnect_0_acl_kernel_clk_ctrl_readdata), // .readdata
.ctrl_readdatavalid (mm_interconnect_0_acl_kernel_clk_ctrl_readdatavalid), // .readdatavalid
.ctrl_burstcount (mm_interconnect_0_acl_kernel_clk_ctrl_burstcount), // .burstcount
.ctrl_writedata (mm_interconnect_0_acl_kernel_clk_ctrl_writedata), // .writedata
.ctrl_address (mm_interconnect_0_acl_kernel_clk_ctrl_address), // .address
.ctrl_write (mm_interconnect_0_acl_kernel_clk_ctrl_write), // .write
.ctrl_read (mm_interconnect_0_acl_kernel_clk_ctrl_read), // .read
.ctrl_byteenable (mm_interconnect_0_acl_kernel_clk_ctrl_byteenable), // .byteenable
.ctrl_debugaccess (mm_interconnect_0_acl_kernel_clk_ctrl_debugaccess), // .debugaccess
.kernel_clk_clk (kernel_clk_clk), // kernel_clk.clk
.kernel_pll_locked_export (acl_kernel_clk_kernel_pll_locked_export), // kernel_pll_locked.export
.clk_clk (config_clk_clk), // clk.clk
.reset_reset_n (~rst_controller_reset_out_reset) // reset.reset_n
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (256),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (30),
.BURSTCOUNT_WIDTH (5),
.COMMAND_FIFO_DEPTH (64),
.RESPONSE_FIFO_DEPTH (64),
.MASTER_SYNC_DEPTH (2),
.SLAVE_SYNC_DEPTH (2)
) clock_cross_kernel_mem1 (
.m0_clk (pll_outclk0_clk), // m0_clk.clk
.m0_reset (rst_controller_001_reset_out_reset), // m0_reset.reset
.s0_clk (kernel_clk_clk), // s0_clk.clk
.s0_reset (~kernel_reset_reset_n), // s0_reset.reset
.s0_waitrequest (kernel_mem0_waitrequest), // s0.waitrequest
.s0_readdata (kernel_mem0_readdata), // .readdata
.s0_readdatavalid (kernel_mem0_readdatavalid), // .readdatavalid
.s0_burstcount (kernel_mem0_burstcount), // .burstcount
.s0_writedata (kernel_mem0_writedata), // .writedata
.s0_address (kernel_mem0_address), // .address
.s0_write (kernel_mem0_write), // .write
.s0_read (kernel_mem0_read), // .read
.s0_byteenable (kernel_mem0_byteenable), // .byteenable
.s0_debugaccess (kernel_mem0_debugaccess), // .debugaccess
.m0_waitrequest (clock_cross_kernel_mem1_m0_waitrequest), // m0.waitrequest
.m0_readdata (clock_cross_kernel_mem1_m0_readdata), // .readdata
.m0_readdatavalid (clock_cross_kernel_mem1_m0_readdatavalid), // .readdatavalid
.m0_burstcount (clock_cross_kernel_mem1_m0_burstcount), // .burstcount
.m0_writedata (clock_cross_kernel_mem1_m0_writedata), // .writedata
.m0_address (clock_cross_kernel_mem1_m0_address), // .address
.m0_write (clock_cross_kernel_mem1_m0_write), // .write
.m0_read (clock_cross_kernel_mem1_m0_read), // .read
.m0_byteenable (clock_cross_kernel_mem1_m0_byteenable), // .byteenable
.m0_debugaccess (clock_cross_kernel_mem1_m0_debugaccess) // .debugaccess
);
version_id #(
.WIDTH (32),
.VERSION_ID (-1597521440)
) version_id (
.clk (config_clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_read (mm_interconnect_0_version_id_s_read), // s.read
.slave_readdata (mm_interconnect_0_version_id_s_readdata) // .readdata
);
system_acl_iface_hps #(
.F2S_Width (0),
.S2F_Width (0)
) hps (
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (peripheral_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (peripheral_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (peripheral_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (peripheral_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (peripheral_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (peripheral_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (peripheral_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (peripheral_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (peripheral_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (peripheral_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (peripheral_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (peripheral_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (peripheral_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (peripheral_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (peripheral_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (peripheral_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (peripheral_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (peripheral_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (peripheral_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (peripheral_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_uart0_inst_RX (peripheral_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (peripheral_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (peripheral_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (peripheral_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO53 (peripheral_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (pll_outclk0_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (mm_interconnect_2_hps_f2h_sdram0_data_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (mm_interconnect_2_hps_f2h_sdram0_data_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (mm_interconnect_2_hps_f2h_sdram0_data_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (mm_interconnect_2_hps_f2h_sdram0_data_readdata), // .readdata
.f2h_sdram0_READDATAVALID (mm_interconnect_2_hps_f2h_sdram0_data_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (mm_interconnect_2_hps_f2h_sdram0_data_read), // .read
.f2h_sdram0_WRITEDATA (mm_interconnect_2_hps_f2h_sdram0_data_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (mm_interconnect_2_hps_f2h_sdram0_data_byteenable), // .byteenable
.f2h_sdram0_WRITE (mm_interconnect_2_hps_f2h_sdram0_data_write), // .write
.h2f_lw_axi_clk (config_clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_h2f_lw_axi_master_rready), // .rready
.f2h_irq_p0 (hps_f2h_irq0_irq), // f2h_irq0.irq
.f2h_irq_p1 (hps_f2h_irq1_irq) // f2h_irq1.irq
);
system_acl_iface_acl_kernel_interface acl_kernel_interface (
.clk_clk (config_clk_clk), // clk.clk
.reset_reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.kernel_cntrl_waitrequest (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_waitrequest), // kernel_cntrl.waitrequest
.kernel_cntrl_readdata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdata), // .readdata
.kernel_cntrl_readdatavalid (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdatavalid), // .readdatavalid
.kernel_cntrl_burstcount (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_burstcount), // .burstcount
.kernel_cntrl_writedata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_writedata), // .writedata
.kernel_cntrl_address (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_address), // .address
.kernel_cntrl_write (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_write), // .write
.kernel_cntrl_read (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_read), // .read
.kernel_cntrl_byteenable (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_byteenable), // .byteenable
.kernel_cntrl_debugaccess (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_debugaccess), // .debugaccess
.kernel_cra_waitrequest (kernel_cra_waitrequest), // kernel_cra.waitrequest
.kernel_cra_readdata (kernel_cra_readdata), // .readdata
.kernel_cra_readdatavalid (kernel_cra_readdatavalid), // .readdatavalid
.kernel_cra_burstcount (kernel_cra_burstcount), // .burstcount
.kernel_cra_writedata (kernel_cra_writedata), // .writedata
.kernel_cra_address (kernel_cra_address), // .address
.kernel_cra_write (kernel_cra_write), // .write
.kernel_cra_read (kernel_cra_read), // .read
.kernel_cra_byteenable (kernel_cra_byteenable), // .byteenable
.kernel_cra_debugaccess (kernel_cra_debugaccess), // .debugaccess
.kernel_irq_from_kernel_irq (kernel_irq_irq), // kernel_irq_from_kernel.irq
.acl_bsp_memorg_kernel_mode (acl_internal_memorg_kernel_mode), // acl_bsp_memorg_kernel.mode
.acl_bsp_memorg_host_mode (kernel_interface_acl_bsp_memorg_host_mode), // acl_bsp_memorg_host.mode
.sw_reset_in_reset (rst_controller_reset_out_reset), // sw_reset_in.reset
.kernel_clk_clk (kernel_clk_clk), // kernel_clk.clk
.sw_reset_export_reset_n (acl_kernel_interface_sw_reset_export_reset), // sw_reset_export.reset_n
.kernel_reset_reset_n (kernel_reset_reset_n), // kernel_reset.reset_n
.kernel_irq_to_host_irq (irq_mapper_receiver0_irq) // kernel_irq_to_host.irq
);
system_acl_iface_pll pll (
.refclk (config_clk_clk), // refclk.clk
.rst (~reset_n), // reset.reset
.outclk_0 (pll_outclk0_clk), // outclk0.clk
.locked () // (terminated)
);
altera_address_span_extender #(
.DATA_WIDTH (256),
.BYTEENABLE_WIDTH (32),
.MASTER_ADDRESS_WIDTH (32),
.SLAVE_ADDRESS_WIDTH (25),
.SLAVE_ADDRESS_SHIFT (5),
.BURSTCOUNT_WIDTH (5),
.CNTL_ADDRESS_WIDTH (1),
.SUB_WINDOW_COUNT (1),
.MASTER_ADDRESS_DEF (64'b0000000000000000000000000000000000000000000000000000000000000000)
) address_span_extender_kernel (
.clk (pll_outclk0_clk), // clock.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.avs_s0_address (mm_interconnect_1_address_span_extender_kernel_windowed_slave_address), // windowed_slave.address
.avs_s0_read (mm_interconnect_1_address_span_extender_kernel_windowed_slave_read), // .read
.avs_s0_readdata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdata), // .readdata
.avs_s0_write (mm_interconnect_1_address_span_extender_kernel_windowed_slave_write), // .write
.avs_s0_writedata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_writedata), // .writedata
.avs_s0_readdatavalid (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdatavalid), // .readdatavalid
.avs_s0_waitrequest (mm_interconnect_1_address_span_extender_kernel_windowed_slave_waitrequest), // .waitrequest
.avs_s0_byteenable (mm_interconnect_1_address_span_extender_kernel_windowed_slave_byteenable), // .byteenable
.avs_s0_burstcount (mm_interconnect_1_address_span_extender_kernel_windowed_slave_burstcount), // .burstcount
.avm_m0_address (address_span_extender_kernel_expanded_master_address), // expanded_master.address
.avm_m0_read (address_span_extender_kernel_expanded_master_read), // .read
.avm_m0_waitrequest (address_span_extender_kernel_expanded_master_waitrequest), // .waitrequest
.avm_m0_readdata (address_span_extender_kernel_expanded_master_readdata), // .readdata
.avm_m0_write (address_span_extender_kernel_expanded_master_write), // .write
.avm_m0_writedata (address_span_extender_kernel_expanded_master_writedata), // .writedata
.avm_m0_readdatavalid (address_span_extender_kernel_expanded_master_readdatavalid), // .readdatavalid
.avm_m0_byteenable (address_span_extender_kernel_expanded_master_byteenable), // .byteenable
.avm_m0_burstcount (address_span_extender_kernel_expanded_master_burstcount), // .burstcount
.avs_cntl_address (1'b0), // (terminated)
.avs_cntl_read (1'b0), // (terminated)
.avs_cntl_readdata (), // (terminated)
.avs_cntl_write (1'b0), // (terminated)
.avs_cntl_writedata (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.avs_cntl_byteenable (8'b00000000) // (terminated)
);
system_acl_iface_mm_interconnect_0 mm_interconnect_0 (
.hps_h2f_lw_axi_master_awid (hps_h2f_lw_axi_master_awid), // hps_h2f_lw_axi_master.awid
.hps_h2f_lw_axi_master_awaddr (hps_h2f_lw_axi_master_awaddr), // .awaddr
.hps_h2f_lw_axi_master_awlen (hps_h2f_lw_axi_master_awlen), // .awlen
.hps_h2f_lw_axi_master_awsize (hps_h2f_lw_axi_master_awsize), // .awsize
.hps_h2f_lw_axi_master_awburst (hps_h2f_lw_axi_master_awburst), // .awburst
.hps_h2f_lw_axi_master_awlock (hps_h2f_lw_axi_master_awlock), // .awlock
.hps_h2f_lw_axi_master_awcache (hps_h2f_lw_axi_master_awcache), // .awcache
.hps_h2f_lw_axi_master_awprot (hps_h2f_lw_axi_master_awprot), // .awprot
.hps_h2f_lw_axi_master_awvalid (hps_h2f_lw_axi_master_awvalid), // .awvalid
.hps_h2f_lw_axi_master_awready (hps_h2f_lw_axi_master_awready), // .awready
.hps_h2f_lw_axi_master_wid (hps_h2f_lw_axi_master_wid), // .wid
.hps_h2f_lw_axi_master_wdata (hps_h2f_lw_axi_master_wdata), // .wdata
.hps_h2f_lw_axi_master_wstrb (hps_h2f_lw_axi_master_wstrb), // .wstrb
.hps_h2f_lw_axi_master_wlast (hps_h2f_lw_axi_master_wlast), // .wlast
.hps_h2f_lw_axi_master_wvalid (hps_h2f_lw_axi_master_wvalid), // .wvalid
.hps_h2f_lw_axi_master_wready (hps_h2f_lw_axi_master_wready), // .wready
.hps_h2f_lw_axi_master_bid (hps_h2f_lw_axi_master_bid), // .bid
.hps_h2f_lw_axi_master_bresp (hps_h2f_lw_axi_master_bresp), // .bresp
.hps_h2f_lw_axi_master_bvalid (hps_h2f_lw_axi_master_bvalid), // .bvalid
.hps_h2f_lw_axi_master_bready (hps_h2f_lw_axi_master_bready), // .bready
.hps_h2f_lw_axi_master_arid (hps_h2f_lw_axi_master_arid), // .arid
.hps_h2f_lw_axi_master_araddr (hps_h2f_lw_axi_master_araddr), // .araddr
.hps_h2f_lw_axi_master_arlen (hps_h2f_lw_axi_master_arlen), // .arlen
.hps_h2f_lw_axi_master_arsize (hps_h2f_lw_axi_master_arsize), // .arsize
.hps_h2f_lw_axi_master_arburst (hps_h2f_lw_axi_master_arburst), // .arburst
.hps_h2f_lw_axi_master_arlock (hps_h2f_lw_axi_master_arlock), // .arlock
.hps_h2f_lw_axi_master_arcache (hps_h2f_lw_axi_master_arcache), // .arcache
.hps_h2f_lw_axi_master_arprot (hps_h2f_lw_axi_master_arprot), // .arprot
.hps_h2f_lw_axi_master_arvalid (hps_h2f_lw_axi_master_arvalid), // .arvalid
.hps_h2f_lw_axi_master_arready (hps_h2f_lw_axi_master_arready), // .arready
.hps_h2f_lw_axi_master_rid (hps_h2f_lw_axi_master_rid), // .rid
.hps_h2f_lw_axi_master_rdata (hps_h2f_lw_axi_master_rdata), // .rdata
.hps_h2f_lw_axi_master_rresp (hps_h2f_lw_axi_master_rresp), // .rresp
.hps_h2f_lw_axi_master_rlast (hps_h2f_lw_axi_master_rlast), // .rlast
.hps_h2f_lw_axi_master_rvalid (hps_h2f_lw_axi_master_rvalid), // .rvalid
.hps_h2f_lw_axi_master_rready (hps_h2f_lw_axi_master_rready), // .rready
.config_clk_out_clk_clk (config_clk_clk), // config_clk_out_clk.clk
.hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.version_id_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // version_id_clk_reset_reset_bridge_in_reset.reset
.acl_kernel_clk_ctrl_address (mm_interconnect_0_acl_kernel_clk_ctrl_address), // acl_kernel_clk_ctrl.address
.acl_kernel_clk_ctrl_write (mm_interconnect_0_acl_kernel_clk_ctrl_write), // .write
.acl_kernel_clk_ctrl_read (mm_interconnect_0_acl_kernel_clk_ctrl_read), // .read
.acl_kernel_clk_ctrl_readdata (mm_interconnect_0_acl_kernel_clk_ctrl_readdata), // .readdata
.acl_kernel_clk_ctrl_writedata (mm_interconnect_0_acl_kernel_clk_ctrl_writedata), // .writedata
.acl_kernel_clk_ctrl_burstcount (mm_interconnect_0_acl_kernel_clk_ctrl_burstcount), // .burstcount
.acl_kernel_clk_ctrl_byteenable (mm_interconnect_0_acl_kernel_clk_ctrl_byteenable), // .byteenable
.acl_kernel_clk_ctrl_readdatavalid (mm_interconnect_0_acl_kernel_clk_ctrl_readdatavalid), // .readdatavalid
.acl_kernel_clk_ctrl_waitrequest (mm_interconnect_0_acl_kernel_clk_ctrl_waitrequest), // .waitrequest
.acl_kernel_clk_ctrl_debugaccess (mm_interconnect_0_acl_kernel_clk_ctrl_debugaccess), // .debugaccess
.acl_kernel_interface_kernel_cntrl_address (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_address), // acl_kernel_interface_kernel_cntrl.address
.acl_kernel_interface_kernel_cntrl_write (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_write), // .write
.acl_kernel_interface_kernel_cntrl_read (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_read), // .read
.acl_kernel_interface_kernel_cntrl_readdata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdata), // .readdata
.acl_kernel_interface_kernel_cntrl_writedata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_writedata), // .writedata
.acl_kernel_interface_kernel_cntrl_burstcount (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_burstcount), // .burstcount
.acl_kernel_interface_kernel_cntrl_byteenable (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_byteenable), // .byteenable
.acl_kernel_interface_kernel_cntrl_readdatavalid (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdatavalid), // .readdatavalid
.acl_kernel_interface_kernel_cntrl_waitrequest (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_waitrequest), // .waitrequest
.acl_kernel_interface_kernel_cntrl_debugaccess (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_debugaccess), // .debugaccess
.version_id_s_read (mm_interconnect_0_version_id_s_read), // version_id_s.read
.version_id_s_readdata (mm_interconnect_0_version_id_s_readdata) // .readdata
);
system_acl_iface_mm_interconnect_1 mm_interconnect_1 (
.pll_outclk0_clk (pll_outclk0_clk), // pll_outclk0.clk
.clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset.reset
.clock_cross_kernel_mem1_m0_address (clock_cross_kernel_mem1_m0_address), // clock_cross_kernel_mem1_m0.address
.clock_cross_kernel_mem1_m0_waitrequest (clock_cross_kernel_mem1_m0_waitrequest), // .waitrequest
.clock_cross_kernel_mem1_m0_burstcount (clock_cross_kernel_mem1_m0_burstcount), // .burstcount
.clock_cross_kernel_mem1_m0_byteenable (clock_cross_kernel_mem1_m0_byteenable), // .byteenable
.clock_cross_kernel_mem1_m0_read (clock_cross_kernel_mem1_m0_read), // .read
.clock_cross_kernel_mem1_m0_readdata (clock_cross_kernel_mem1_m0_readdata), // .readdata
.clock_cross_kernel_mem1_m0_readdatavalid (clock_cross_kernel_mem1_m0_readdatavalid), // .readdatavalid
.clock_cross_kernel_mem1_m0_write (clock_cross_kernel_mem1_m0_write), // .write
.clock_cross_kernel_mem1_m0_writedata (clock_cross_kernel_mem1_m0_writedata), // .writedata
.clock_cross_kernel_mem1_m0_debugaccess (clock_cross_kernel_mem1_m0_debugaccess), // .debugaccess
.address_span_extender_kernel_windowed_slave_address (mm_interconnect_1_address_span_extender_kernel_windowed_slave_address), // address_span_extender_kernel_windowed_slave.address
.address_span_extender_kernel_windowed_slave_write (mm_interconnect_1_address_span_extender_kernel_windowed_slave_write), // .write
.address_span_extender_kernel_windowed_slave_read (mm_interconnect_1_address_span_extender_kernel_windowed_slave_read), // .read
.address_span_extender_kernel_windowed_slave_readdata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdata), // .readdata
.address_span_extender_kernel_windowed_slave_writedata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_writedata), // .writedata
.address_span_extender_kernel_windowed_slave_burstcount (mm_interconnect_1_address_span_extender_kernel_windowed_slave_burstcount), // .burstcount
.address_span_extender_kernel_windowed_slave_byteenable (mm_interconnect_1_address_span_extender_kernel_windowed_slave_byteenable), // .byteenable
.address_span_extender_kernel_windowed_slave_readdatavalid (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdatavalid), // .readdatavalid
.address_span_extender_kernel_windowed_slave_waitrequest (mm_interconnect_1_address_span_extender_kernel_windowed_slave_waitrequest) // .waitrequest
);
system_acl_iface_mm_interconnect_2 mm_interconnect_2 (
.pll_outclk0_clk (pll_outclk0_clk), // pll_outclk0.clk
.address_span_extender_kernel_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // address_span_extender_kernel_reset_reset_bridge_in_reset.reset
.hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset), // hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset.reset
.address_span_extender_kernel_expanded_master_address (address_span_extender_kernel_expanded_master_address), // address_span_extender_kernel_expanded_master.address
.address_span_extender_kernel_expanded_master_waitrequest (address_span_extender_kernel_expanded_master_waitrequest), // .waitrequest
.address_span_extender_kernel_expanded_master_burstcount (address_span_extender_kernel_expanded_master_burstcount), // .burstcount
.address_span_extender_kernel_expanded_master_byteenable (address_span_extender_kernel_expanded_master_byteenable), // .byteenable
.address_span_extender_kernel_expanded_master_read (address_span_extender_kernel_expanded_master_read), // .read
.address_span_extender_kernel_expanded_master_readdata (address_span_extender_kernel_expanded_master_readdata), // .readdata
.address_span_extender_kernel_expanded_master_readdatavalid (address_span_extender_kernel_expanded_master_readdatavalid), // .readdatavalid
.address_span_extender_kernel_expanded_master_write (address_span_extender_kernel_expanded_master_write), // .write
.address_span_extender_kernel_expanded_master_writedata (address_span_extender_kernel_expanded_master_writedata), // .writedata
.hps_f2h_sdram0_data_address (mm_interconnect_2_hps_f2h_sdram0_data_address), // hps_f2h_sdram0_data.address
.hps_f2h_sdram0_data_write (mm_interconnect_2_hps_f2h_sdram0_data_write), // .write
.hps_f2h_sdram0_data_read (mm_interconnect_2_hps_f2h_sdram0_data_read), // .read
.hps_f2h_sdram0_data_readdata (mm_interconnect_2_hps_f2h_sdram0_data_readdata), // .readdata
.hps_f2h_sdram0_data_writedata (mm_interconnect_2_hps_f2h_sdram0_data_writedata), // .writedata
.hps_f2h_sdram0_data_burstcount (mm_interconnect_2_hps_f2h_sdram0_data_burstcount), // .burstcount
.hps_f2h_sdram0_data_byteenable (mm_interconnect_2_hps_f2h_sdram0_data_byteenable), // .byteenable
.hps_f2h_sdram0_data_readdatavalid (mm_interconnect_2_hps_f2h_sdram0_data_readdatavalid), // .readdatavalid
.hps_f2h_sdram0_data_waitrequest (mm_interconnect_2_hps_f2h_sdram0_data_waitrequest) // .waitrequest
);
system_acl_iface_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (hps_f2h_irq0_irq) // sender.irq
);
system_acl_iface_irq_mapper_001 irq_mapper_001 (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (hps_f2h_irq1_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_n), // reset_in0.reset
.clk (config_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~acl_kernel_interface_sw_reset_export_reset), // reset_in0.reset
.clk (pll_outclk0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~hps_h2f_reset_reset), // reset_in0.reset
.clk (config_clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_003 (
.reset_in0 (~hps_h2f_reset_reset), // reset_in0.reset
.clk (pll_outclk0_clk), // clk.clk
.reset_out (rst_controller_003_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
assign kernel_clk_snoop_clk = kernel_clk_clk;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: counter.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple up-counter. The maximum value is the largest expected
// value. The counter will not pass the SAT_VALUE. If the SAT_VALUE > MAX_VALUE,
// the counter will roll over and never stop. On RST_IN, the counter
// synchronously resets to the RST_VALUE
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module counter
#(parameter C_MAX_VALUE = 10,
parameter C_SAT_VALUE = 10,
parameter C_RST_VALUE = 0)
(
input CLK,
input RST_IN,
input ENABLE,
output [clog2s(C_MAX_VALUE+1)-1:0] VALUE
);
`include "functions.vh"
wire wEnable;
reg [clog2s(C_MAX_VALUE+1)-1:0] wCtrValue;
reg [clog2s(C_MAX_VALUE+1)-1:0] rCtrValue;
/* verilator lint_off WIDTH */
assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue);
/* verilator lint_on WIDTH */
assign VALUE = rCtrValue;
always @(posedge CLK) begin
if(RST_IN) begin
rCtrValue <= C_RST_VALUE;
end else if(wEnable) begin
rCtrValue <= rCtrValue + 1;
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_mc_phy_wrapper.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Oct 10 2010
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Wrapper file that encompasses the MC_PHY module
// instantiation and handles the vector remapping between
// the MC_PHY ports and the user's DDR3 ports. Vector
// remapping affects DDR3 control, address, and DQ/DQS/DM.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_0_ddr_mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter CK_WIDTH = 1, // # of CK
parameter CWL = 5, // CAS Write latency
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter ODT_WIDTH = 1, // # of ODT outputs
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// Simulation options
parameter SIM_CAL_OPTION = "NONE",
// The PHY_CONTROL primitive in the bank where PLL exists is declared
// as the Master PHY_CONTROL.
parameter MASTER_PHY_CTL = 1
)
(
input rst,
input clk,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input phy_if_empty_def,
input phy_if_reset,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output [4:0] idelaye2_init_val,
output [5:0] oclkdelay_init_val,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output phy_pre_data_a_full,
output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input [HIGHEST_BANK-1:0] calib_zero_ctrl,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
output [8:0] po_counter_read_val,
output [5:0] pi_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
input idelay_ce,
input idelay_inc,
input idelay_ld,
input idle,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [1:0] mux_odt,
input [nCK_PER_CLK-1:0] mux_cke,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
input mux_reset_n,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
output ddr_reset_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n
,input dbg_pi_counter_read_en
,output ref_dll_lock
,input rst_phaser_ref
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
);
function [71:0] generate_bytelanes_ddr_ck;
input [143:0] ck_byte_map;
integer v ;
begin
generate_bytelanes_ddr_ck = 'b0 ;
for (v = 0; v < CK_WIDTH; v = v + 1) begin
if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)
generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)
generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else
generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
end
end
endfunction
function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;
input [143:0] ck_byte_map;
integer g;
begin
generate_ddr_ck_map = 'b0 ;
for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin
generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" :
(ck_byte_map[(g*8)+:4] == 4'd1) ? "B" :
(ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ;
generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" :
(ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location
end
end
endfunction
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;
localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
//localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
//// Temporary method to force MC_PHY to generate ODDR associated with
//// CK/CK# output only for a single byte lane in the design. All banks
//// that won't be generating the CK/CK# will have "UNUSED" as their
//// PHY_GENERATE_DDR_CK parameter
//localparam TMP_PHY_0_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_1_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_2_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx
// which indicates which bit lanes in data byte lanes are
// output-only bitlanes (e.g. used specifically for data mask outputs)
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
// Only enable BITLANES parameters for data masks if, well, if
// the data masks are actually enabled
if (USE_DM_PORT == 1)
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF
= (CKE_MAP[11:8] == 4'h0) ? 0 :
((CKE_MAP[11:8] == 4'h1) ? 1 :
((CKE_MAP[11:8] == 4'h2) ? 2 :
((CKE_MAP[11:8] == 4'h3) ? 3 :
((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF
= (CKE_MAP[7:4] == 4'h0) ? "A" :
((CKE_MAP[7:4] == 4'h1) ? "B" :
((CKE_MAP[7:4] == 4'h2) ? "C" :
((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;
localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;
//***************************************************************************
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
//***************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz
// and 1.25 for Mem_RefClk > 300 MHz
localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";
//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,
//DIV4: MemRefClk < 200 MHz
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" :
tCK > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 :
PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;
// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0);
// Phaser-Out Stage3 Tap delay for 90 deg shift.
// Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) -
(INT_DELAY + HALF_CYCLE_DELAY))
* 63 * FREQ_REF_DIV;
//localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
localparam integer PHY_0_A_PO_OCLK_DELAY_HW
= (tCK > 2273) ? 34 :
(tCK > 2000) ? 33 :
(tCK > 1724) ? 32 :
(tCK > 1515) ? 31 :
(tCK > 1315) ? 30 :
(tCK > 1136) ? 29 :
(tCK > 1021) ? 28 : 27;
// Note that simulation requires a different value than in H/W because of the
// difference in the way delays are modeled
localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ?
((tCK > 2500) ? 8 :
(DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :
MC_OCLK_DELAY;
// Initial DQ IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 :
(tCK < 1000) ? 0 :
(tCK < 1330) ? 0 :
(tCK < 2300) ? 0 :
(tCK < 2500) ? 2 : 0;
//localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10;
localparam PHY_0_RD_CMD_OFFSET_1 = 10;
localparam PHY_0_RD_CMD_OFFSET_2 = 10;
localparam PHY_0_RD_CMD_OFFSET_3 = 10;
// 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing
localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;
// 4:1 and 2:1 have different values
localparam PHY_0_WR_DURATION_0 = 7;
localparam PHY_0_WR_DURATION_1 = 7;
localparam PHY_0_WR_DURATION_2 = 7;
localparam PHY_0_WR_DURATION_3 = 7;
// Aux_out parameters for toggle mode (CKE)
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :
(CWL < 7) ?
4 + ((CWL_M % 2) ? 0 : 1) :
5 + ((CWL_M % 2) ? 0 : 1);
// temporary parameter to enable/disable PHY PC counters. In both 4:1 and
// 2:1 cases, this should be disabled. For now, enable for 4:1 mode to
// avoid making too many changes at once.
localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE";
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [ODT_WIDTH -1:0] out_odt;
wire [CKE_WIDTH -1 :0] out_cke ;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire phy_rd_en;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
reg [31:0] phy_ctl_wd_i1;
reg [31:0] phy_ctl_wd_i2;
reg phy_ctl_wr_i1;
reg phy_ctl_wr_i2;
reg [5:0] data_offset_1_i1;
reg [5:0] data_offset_1_i2;
reg [5:0] data_offset_2_i1;
reg [5:0] data_offset_2_i2;
wire [31:0] phy_ctl_wd_temp;
wire phy_ctl_wr_temp;
wire [5:0] data_offset_1_temp;
wire [5:0] data_offset_2_temp;
wire [5:0] data_offset_1_of;
wire [5:0] data_offset_2_of;
wire [31:0] phy_ctl_wd_of;
wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */;
wire [3:0] phy_ctl_full_temp;
wire data_io_idle_pwrdwn;
// Always read from input data FIFOs when not empty
assign phy_rd_en = !if_empty;
// IDELAYE2 initial value
assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;
assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;
// Idle powerdown when there are no pending reads in the MC
assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins
if (CKE_WIDTH == 1) begin : gen_cke
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_cke_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke)
);
end else begin: gen_2rank_cke
OBUF u_cke0_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke[0])
);
OBUF u_cke1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_cke[1])
);
end
end
endgenerate
generate
if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins
if (USE_ODT_PORT == 1) begin : gen_use_odt
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_odt_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),
.O (ddr_odt[0])
);
if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
OBUF u_odt2_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[2])
);
end
end else begin
assign ddr_odt = 'b0;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if (REG_CTRL == "ON") begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n,x;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
if (USE_CS_PORT == 1) begin: gen_cs_n_out
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
end
if(CKE_ODT_AUX == "FALSE") begin
// ODT_ports
wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;
if(RANKS == 1) begin
for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin
assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;
end
end else begin
for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin
assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;
assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;
end
end
if (USE_ODT_PORT == 1) begin: gen_odt_out
for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1
assign out_odt[m]
= mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +
12*ODT_MAP[(12*m+4)+:2] +
ODT_MAP[12*m+:4]];
if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*ODT_MAP[12*m+:4] + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*(ODT_MAP[12*m+:4]-5) + 4 + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;
for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin
assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;
end
for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out
assign out_cke[m]
= mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +
12*CKE_MAP[(12*m+4)+:2] +
CKE_MAP[12*m+:4]];
if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*CKE_MAP[12*m+:4] + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*(CKE_MAP[12*m+:4]-5) + 4 + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
if (USE_CS_PORT == 1) begin: gen_cs_n_obuf
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
end
if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo
if (USE_ODT_PORT== 1) begin: gen_odt_obuf
for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf
OBUF u_cs_n_obuf
(
.I (out_odt[p]),
.O (ddr_odt[p])
);
end
end
for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf
OBUF u_cs_n_obuf
(
.I (out_cke[p]),
.O (ddr_cke[p])
);
end
end
if (REG_CTRL == "ON") begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf
// Generate reset output only for DDR3 and DDR2 RDIMMs
OBUF u_reset_obuf
(
.I (mux_reset_n),
.O (ddr_reset_n)
);
end else begin: gen_reset_tieoff
assign ddr_reset_n = 1'b1;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else begin: gen_dq_iobuf_default
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
end
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
end
end
end else begin: gen_dqs_iobuf_default
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
end
end
end
endgenerate
always @(posedge clk) begin
phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;
phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;
phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;
phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;
data_offset_1_i1 <= #TCQ data_offset_1;
data_offset_1_i2 <= #TCQ data_offset_1_i1;
data_offset_2_i1 <= #TCQ data_offset_2;
data_offset_2_i2 <= #TCQ data_offset_2_i1;
end
// 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.
// 2:1 mode the command goes through pre fifo
assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;
assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;
assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;
assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;
generate
begin
mig_7series_v2_0_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (32)
)
phy_ctl_pre_fifo_0
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[1]),
.wr_en_in (phy_ctl_wr),
.d_in (phy_ctl_wd),
.wr_en_out (phy_ctl_wr_of),
.d_out (phy_ctl_wd_of)
);
mig_7series_v2_0_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_1
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[2]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_1),
.wr_en_out (),
.d_out (data_offset_1_of)
);
mig_7series_v2_0_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_2
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[3]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_2),
.wr_en_out (),
.d_out (data_offset_2_of)
);
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
assign phy_ctl_full = phy_ctl_full_temp[0];
mig_7series_v2_0_ddr_mc_phy #
(
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
//.CKE_ODT_AUX (CKE_ODT_AUX),
.GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),
.BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),
.NUM_DDR_CK (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.PO_CTL_COARSE_BYPASS ("FALSE"),
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_CLK_RATIO (nCK_PER_CLK),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.PHY_FOUR_WINDOW_CLOCKS (63),
.PHY_EVENTS_DELAY (18),
.PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN
.PHY_SYNC_MODE ("FALSE"),
.SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"),
.PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE"
.PHY_0_GENERATE_IDELAYCTRL ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
//.PHY_1_NUM_DDR_CK (1),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
//.PHY_2_NUM_DDR_CK (1),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.TCK (tCK),
.PHY_0_IODELAY_GRP (IODELAY_GRP)
,.PHY_1_IODELAY_GRP (IODELAY_GRP)
,.PHY_2_IODELAY_GRP (IODELAY_GRP)
,.BANK_TYPE (BANK_TYPE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.auxout_clk (),
.sync_pulse (sync_pulse),
// IDELAYCTRL instantiated outside of mc_phy module
.idelayctrl_refclk (),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phy_ctl_wd (phy_ctl_wd_temp),
.phy_ctl_wr (phy_ctl_wr_temp),
.if_empty_def (phy_if_empty_def),
.if_rst (phy_if_reset),
.phyGo ('b1),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
// No support yet for different data offsets for different I/O banks
// (possible use in supporting wider range of skew among bytes)
.data_offset_1 (data_offset_1_temp),
.data_offset_2 (data_offset_2_temp),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.if_empty_or (),
.if_empty_and (),
.of_ctl_a_full (),
// .of_data_a_full (phy_data_full),
.of_ctl_full (phy_cmd_full),
.of_data_full (),
.pre_data_a_full (phy_pre_data_a_full),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (),
.phy_ctl_full (phy_ctl_full_temp),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
//.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.calib_zero_lanes ('b0),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (dbg_pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (pi_counter_read_val),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
,.ref_dll_lock (ref_dll_lock)
,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)
// ,.rst_phaser_ref (rst_phaser_ref)
);
endmodule
|
`include "../../primitives/slice/CCU2C/CCU2C.sim.v"
`include "../../primitives/slice/L6MUX21/L6MUX21.sim.v"
`include "../../primitives/slice/LUT4/LUT4.sim.v"
`include "../../primitives/slice/PFUMX/PFUMX.sim.v"
`include "../../primitives/slice/TRELLIS_FF/TRELLIS_FF.sim.v"
`include "../../primitives/slice/TRELLIS_RAM16X2/TRELLIS_RAM16X2.sim.v"
`default_nettype none
module TRELLIS_SLICE(
input A0, B0, C0, D0,
input A1, B1, C1, D1,
input M0, M1,
input FCI, FXA, FXB,
input CLK, LSR, CE,
input DI0, DI1,
input WD0, WD1,
input WAD0, WAD1, WAD2, WAD3,
input WRE, WCK,
output F0, Q0,
output F1, Q1,
output FCO, OFX0, OFX1,
output WDO0, WDO1, WDO2, WDO3,
output WADO0, WADO1, WADO2, WADO3
);
parameter MODE = "LOGIC";
parameter GSR = "ENABLED";
parameter SRMODE = "LSR_OVER_CE";
parameter [127:0] CEMUX = "1";
parameter CLKMUX = "CLK";
parameter LSRMUX = "LSR";
parameter LUT0_INITVAL = 16'h0000;
parameter LUT1_INITVAL = 16'h0000;
parameter REG0_SD = "0";
parameter REG1_SD = "0";
parameter REG0_REGSET = "RESET";
parameter REG1_REGSET = "RESET";
parameter [127:0] CCU2_INJECT1_0 = "NO";
parameter [127:0] CCU2_INJECT1_1 = "NO";
parameter WREMUX = "WRE";
function [15:0] permute_initval;
input [15:0] initval;
integer i;
begin
for (i = 0; i < 16; i = i + 1) begin
permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
end
end
endfunction
generate
if (MODE == "LOGIC") begin
// LUTs
LUT4 #(
.INIT(LUT0_INITVAL)
) lut4_0 (
.A(A0), .B(B0), .C(C0), .D(D0),
.Z(F0)
);
LUT4 #(
.INIT(LUT1_INITVAL)
) lut4_1 (
.A(A1), .B(B1), .C(C1), .D(D1),
.Z(F1)
);
// LUT expansion muxes
PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
end else if (MODE == "CCU2") begin
CCU2C #(
.INIT0(LUT0_INITVAL),
.INIT1(LUT1_INITVAL),
.INJECT1_0(CCU2_INJECT1_0),
.INJECT1_1(CCU2_INJECT1_1)
) ccu2c_i (
.CIN(FCI),
.A0(A0), .B0(B0), .C0(C0), .D0(D0),
.A1(A1), .B1(B1), .C1(C1), .D1(D1),
.S0(F0), .S1(F1),
.COUT(FCO)
);
end else if (MODE == "RAMW") begin
assign WDO0 = C1;
assign WDO1 = A1;
assign WDO2 = D1;
assign WDO3 = B1;
assign WADO0 = D0;
assign WADO1 = B0;
assign WADO2 = C0;
assign WADO3 = A0;
end else if (MODE == "DPRAM") begin
TRELLIS_RAM16X2 #(
.INITVAL_0(permute_initval(LUT0_INITVAL)),
.INITVAL_1(permute_initval(LUT1_INITVAL)),
.WREMUX(WREMUX)
) ram_i (
.DI0(WD0), .DI1(WD1),
.WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
.WRE(WRE), .WCK(WCK),
.RAD0(D0), .RAD1(B0), .RAD2(C0), .RAD3(A0),
.DO0(F0), .DO1(F1)
);
// TODO: confirm RAD and INITVAL ordering
// DPRAM mode contract?
always @(*) begin
assert(A0==A1);
assert(B0==B1);
assert(C0==C1);
assert(D0==D1);
end
end else begin
ERROR_UNKNOWN_SLICE_MODE error();
end
endgenerate
// FF input selection muxes
wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
// Flipflops
TRELLIS_FF #(
.GSR(GSR),
.CEMUX(CEMUX),
.CLKMUX(CLKMUX),
.LSRMUX(LSRMUX),
.SRMODE(SRMODE),
.REGSET(REG0_REGSET)
) ff_0 (
.CLK(CLK), .LSR(LSR), .CE(CE),
.DI(muxdi0),
.Q(Q0)
);
TRELLIS_FF #(
.GSR(GSR),
.CEMUX(CEMUX),
.CLKMUX(CLKMUX),
.LSRMUX(LSRMUX),
.SRMODE(SRMODE),
.REGSET(REG1_REGSET)
) ff_1 (
.CLK(CLK), .LSR(LSR), .CE(CE),
.DI(muxdi1),
.Q(Q1)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s50 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module receiver_logic #(
parameter DSIZE = 10
) (
input wire RESET,
input wire WCLK,
input wire FCLK,
input wire FCLK2X,
input wire BUS_CLK,
input wire RX_DATA,
input wire read,
output wire [23:0] data,
output wire empty,
output reg rx_fifo_full,
output wire rec_sync_ready,
output reg [7:0] lost_data_cnt,
output reg [7:0] decoder_err_cnt,
output reg [15:0] fifo_size,
input wire invert_rx_data,
input wire enable_rx,
input wire FIFO_CLK
);
wire RESET_WCLK;
flag_domain_crossing reset_domain_crossing_wclk_inst (
.CLK_A(BUS_CLK),
.CLK_B(WCLK),
.FLAG_IN_CLK_A(RESET),
.FLAG_OUT_CLK_B(RESET_WCLK)
);
wire RESET_FCLK;
flag_domain_crossing reset_domain_crossing_fclk_inst (
.CLK_A(BUS_CLK),
.CLK_B(FCLK),
.FLAG_IN_CLK_A(RESET),
.FLAG_OUT_CLK_B(RESET_FCLK)
);
wire RESET_FIFO_CLK;
flag_domain_crossing reset_domain_crossing_fifo_clk_inst (
.CLK_A(BUS_CLK),
.CLK_B(FIFO_CLK),
.FLAG_IN_CLK_A(RESET),
.FLAG_OUT_CLK_B(RESET_FIFO_CLK)
);
// data to clock phase alignment
wire RX_DATA_SYNC; //, USEAOUT, USEBOUT, USECOUT, USEDOUT;
sync_master sync_master_inst(
.clk(FCLK), // clock input
.clk_2x(FCLK2X), // clock 90 input
.datain(RX_DATA), // data inputs
.rst(RESET_FCLK), // reset input
.useaout(), // useA output for cascade
.usebout(), // useB output for cascade
.usecout(), // useC output for cascade
.usedout(), // useD output for cascade
.ctrlout(), // ctrl outputs for cascade
.sdataout(RX_DATA_SYNC)
);
reg RX_DATA_SYNC_BUF, RX_DATA_SYNC_BUF2;
always @(posedge FCLK) begin
RX_DATA_SYNC_BUF <= RX_DATA_SYNC;
RX_DATA_SYNC_BUF2 <= RX_DATA_SYNC_BUF;
end
// 8b/10b record sync
wire [9:0] data_8b10b;
reg decoder_err;
rec_sync #(
.DSIZE(DSIZE)
) rec_sync_inst (
.reset(RESET_WCLK),
.datain(invert_rx_data ? ~RX_DATA_SYNC_BUF2 : RX_DATA_SYNC_BUF2),
.data(data_8b10b),
.WCLK(WCLK),
.FCLK(FCLK),
.rec_sync_ready(rec_sync_ready),
.decoder_err(decoder_err)
);
wire write_8b10b;
assign write_8b10b = rec_sync_ready & enable_rx;
reg [9:0] data_to_dec;
integer i;
always @(*) begin
for (i=0; i<10; i=i+1)
data_to_dec[(10-1)-i] = data_8b10b[i];
end
reg dispin;
wire dispout;
always @(posedge WCLK) begin
if(RESET_WCLK)
dispin <= 1'b0;
else// if(write_8b10b)
dispin <= dispout;
// if(RESET_WCLK)
// dispin <= 1'b0;
// else
// if(write_8b10b)
// dispin <= ~dispout;
// else
// dispin <= dispin;
end
wire dec_k;
wire [7:0] dec_data;
wire code_err, disp_err;
decode_8b10b decode_8b10b_inst (
.datain(data_to_dec),
.dispin(dispin),
.dataout({dec_k,dec_data}), // control character, data out
.dispout(dispout),
.code_err(code_err),
.disp_err(disp_err)
);
always @(posedge WCLK) begin
if(RESET_WCLK)
decoder_err <= 1'b0;
else
decoder_err <= code_err | disp_err;
end
// Invalid symbols may or may not cause
// disparity errors depending on the symbol
// itself and the disparities of the previous and
// subsequent symbols. For this reason,
// DISP_ERR should always be combined
// with CODE_ERR to detect all errors.
always @(posedge WCLK) begin
if(RESET_WCLK)
decoder_err_cnt <= 0;
else
if(decoder_err && write_8b10b && decoder_err_cnt != 8'hff)
decoder_err_cnt <= decoder_err_cnt + 1;
end
reg [2:0] byte_sel;
always @(posedge WCLK) begin
if(RESET_WCLK || (write_8b10b && dec_k) || (write_8b10b && dec_k==0 && byte_sel==2))
byte_sel <= 0;
else if(write_8b10b)
byte_sel <= byte_sel + 1;
// if(RESET_WCLK || (write_8b10b && dec_k) || (write_8b10b && dec_k==0 && byte_sel==2))
// byte_sel <= 0;
// else
// if(write_8b10b)
// byte_sel <= byte_sel + 1;
// else
// byte_sel <= byte_sel;
end
reg [7:0] data_dec_in [2:0];
always @(posedge WCLK) begin
for (i=0; i<3; i=i+1)
data_dec_in[i] <= data_dec_in[i];
if(RESET_WCLK)
for (i=0; i<3; i=i+1)
data_dec_in[i] <= 8'b0;
else
if(write_8b10b && dec_k==0)
data_dec_in[byte_sel] <= dec_data;
end
reg cdc_fifo_write;
always @(posedge WCLK) begin
if(RESET_WCLK)
cdc_fifo_write <= 0;
else
if(write_8b10b && dec_k==0 && byte_sel==2)
cdc_fifo_write <= 1;
else
cdc_fifo_write <= 0;
end
wire [23:0] cdc_data_out;
wire [23:0] wdata;
assign wdata = {data_dec_in[0], data_dec_in[1], data_dec_in[2]};
// generate long reset
reg [3:0] rst_cnt_wclk;
reg RST_LONG_WCLK;
always @(posedge WCLK) begin
if (RESET_WCLK)
rst_cnt_wclk <= 4'b1111; // start value
else if (rst_cnt_wclk != 0)
rst_cnt_wclk <= rst_cnt_wclk - 1;
RST_LONG_WCLK <= |rst_cnt_wclk;
end
reg [3:0] rst_cnt_fifo_clk;
reg RST_LONG_FIFO_CLK;
always @(posedge FIFO_CLK) begin
if (RESET_FIFO_CLK)
rst_cnt_fifo_clk <= 4'b1111; // start value
else if (rst_cnt_fifo_clk != 0)
rst_cnt_fifo_clk <= rst_cnt_fifo_clk - 1;
RST_LONG_FIFO_CLK <= |rst_cnt_fifo_clk;
end
wire wfull;
wire fifo_full, cdc_fifo_empty;
cdc_syncfifo #(
.DSIZE(24),
.ASIZE(2)
) cdc_syncfifo_i (
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(wdata),
.winc(cdc_fifo_write),
.wclk(WCLK),
.wrst(RST_LONG_WCLK),
.rinc(!fifo_full),
.rclk(FIFO_CLK),
.rrst(RST_LONG_FIFO_CLK)
);
wire [10:0] fifo_size_int;
gerneric_fifo #(
.DATA_SIZE(24),
.DEPTH(2048)
) fifo_i (
.clk(FIFO_CLK),
.reset(RST_LONG_FIFO_CLK),
.write(!cdc_fifo_empty),
.read(read),
.data_in(cdc_data_out),
.full(fifo_full),
.empty(empty),
.data_out(data),
.size(fifo_size_int)
);
always @(posedge WCLK) begin
if (wfull && cdc_fifo_write) begin // write when FIFO full
rx_fifo_full <= 1'b1;
end else if (!wfull && cdc_fifo_write) begin // write when FIFO not full
rx_fifo_full <= 1'b0;
end
end
always @(posedge WCLK) begin
if (RESET_WCLK)
lost_data_cnt <= 0;
else
if (wfull && cdc_fifo_write && lost_data_cnt != 8'b1111_1111)
lost_data_cnt <= lost_data_cnt + 1;
end
always @(posedge FIFO_CLK) begin
fifo_size <= {5'b0, fifo_size_int};
end
`ifdef SYNTHESIS_NOT
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.CLK(FCLK),
.TRIG0({dec_k, dec_data, data_to_dec, rec_sync_ready, 1'b0, USEAOUT, USEBOUT, USECOUT, USEDOUT, RX_DATA_SYNC, RX_DATA})
);
`endif
endmodule
|
// file: clk_200_400_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module clk_200_400_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk;
reg [C_W-1:0] counter;
// Insert BUFGs on all input clocks that don't already have them
//--------------------------------------------------------------
BUFG clkin1_buf
(.O (clk_in1_buf),
.I (CLK_IN1));
// Instantiation of the clocking network
//--------------------------------------
clk_200_400 clknetwork
(// Clock in ports
.CLK_IN1 (clk_in1_buf),
// Clock out ports
.CLK_OUT1 (clk_int),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
// Library - static, Cell - th33, View - schematic
// LAST TIME SAVED: May 23 16:52:47 2014
// NETLIST TIME: May 23 16:53:06 2014
`timescale 1ns / 1ns
module th33 ( y, a, b, c );
output y;
input a, b, c;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th33";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N6 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(b), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net035), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N15 ( .d(net32), .g(c), .s(net44), .b(cds_globals.gnd_));
nfet_b N10 ( .d(net32), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N2 ( .d(net038), .g(b), .s(net035), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net32), .g(a), .s(net038), .b(cds_globals.gnd_));
pfet_b P12 ( .b(cds_globals.vdd_), .g(c), .s(cds_globals.vdd_),
.d(net036));
pfet_b P5 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net036));
pfet_b P4 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net036));
pfet_b P3 ( .b(cds_globals.vdd_), .g(y), .s(net036), .d(net32));
pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net32));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net32);
endmodule
|
module avlst_n_to_1 #(
parameter N = 8,
parameter DATA_W = 16,
)(
input csi_clk,
input rsi_reset,
output asi_ready,
input asi_valid,
input [N*DATA_W-1:0] asi_data,
input aso_ready,
output aso_valid,
output [DATA_W-1:0] aso_data
);
reg ready;
reg valid;
reg [DATA_W-1:0] data;
reg [DATA_W-1:0] buffer [0:N-1];
assign asi_ready = read;
assign aso_valid = valid;
assign aso_data = data;
reg fval;
always@(posedge csi_clk, posedge rsi_reset) begin
if(rsi_reset == 1'b1)
fval <= 1'b0;
else
if(asi_valid == 1'b1)
fval <= 1'b1;
if(cnt == 3'h7)
end
genvar i;
generate
for(i=0; i<N; i++) begin : main
always@(posedge csi_clk, posedge rsi_reset) begin
if(rsi_reset == 1'b1)
buffer[i] <= {DATA_W{1'b0}};
else begin
if(asi_valid == 1'b1)
buffer[i] <= asi_data[(i+1)*DATA_W-1:i*DATA_W];
end
end
end
endgenerate
always@(posedge csi_clk, posedge rsi_reset) begin
if(rsi_reset == 1'b1) begin
valid <= 1'b0;
end
valid <= fval &
end
always@(posedge csi_clk, posedge rsi_reset) begin
if(rsi_reset == 1'b1) begin
data <= {DATA_W{1'b0}};
end
data <= buffer[cnt];
end
reg [2:0] cnt;
always@(posedge csi_clk, posedge rsi_reset) begin
if(rsi_reset == 1'b1)
cnt <= 3'h0;
else begin
if(aso_ready == 1'b1 && src_valid == 1'b1)
cnt <= cnt+3'h1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_SYMBOL_V
`define SKY130_FD_SC_MS__EBUFN_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVN_8_V
`define SKY130_FD_SC_LS__EINVN_8_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVN_8_V
|
//Alan Achtenberg
//Lab 7
//Part 2
module Dlatch (q,qbar,clock,data);
output q, qbar;
input clock, data;
wire nand1, nand2;
wire databar;
not #1 (databar,data);
nand #1 (nand1,clock, data);
nand #1 (nand2,clock, databar);
nand #1 (qbar,nand2,q);
nand #1 (q,nand1,qbar);
endmodule
module m555(clock);
parameter InitDelay = 10, Ton = 50, Toff = 50;
output clock;
reg clock;
initial begin
#InitDelay clock = 1;
end
always begin
#Ton clock = ~clock;
#Toff clock = ~clock;
end
endmodule
module testD(q, qbar, clock, data);
input q, qbar, clock;
output data;
reg data;
initial begin
$monitor ($time, " q = %d, qbar = %d, clock = %d, data = %d", q, qbar, clock, data);
data = 0;
#25
data = 1;
#100
data = 0;
#50
data = 1;
#50
data = 0;
#100
data = 1;
#50
data = 0;
#50
data = 1;
#100
$finish; /* $finish simulation after 100 time simulation units */
end
endmodule
module testBenchD;
wire clock, q, qbar, data;
m555 clk(clock);
Dlatch dl(q, qbar, clock, data);
testD td(q, qbar, clock, data);
endmodule |
// hps_design.v
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design (
input wire clk_clk, // clk.clk
output wire [14:0] hps_ddr_mem_a, // hps_ddr.mem_a
output wire [2:0] hps_ddr_mem_ba, // .mem_ba
output wire hps_ddr_mem_ck, // .mem_ck
output wire hps_ddr_mem_ck_n, // .mem_ck_n
output wire hps_ddr_mem_cke, // .mem_cke
output wire hps_ddr_mem_cs_n, // .mem_cs_n
output wire hps_ddr_mem_ras_n, // .mem_ras_n
output wire hps_ddr_mem_cas_n, // .mem_cas_n
output wire hps_ddr_mem_we_n, // .mem_we_n
output wire hps_ddr_mem_reset_n, // .mem_reset_n
inout wire [31:0] hps_ddr_mem_dq, // .mem_dq
inout wire [3:0] hps_ddr_mem_dqs, // .mem_dqs
inout wire [3:0] hps_ddr_mem_dqs_n, // .mem_dqs_n
output wire hps_ddr_mem_odt, // .mem_odt
output wire [3:0] hps_ddr_mem_dm, // .mem_dm
input wire hps_ddr_oct_rzqin, // .oct_rzqin
output wire ledr_export, // ledr.export
output wire pll_0_sdram_clk // pll_0_sdram.clk
);
wire pll_0_outclk0_clk; // pll_0:outclk_0 -> [SMP_HPS:h2f_lw_axi_clk, mm_interconnect_0:pll_0_outclk0_clk, pio_0:clk, rst_controller:clk, rst_controller_001:clk]
wire smp_hps_h2f_reset_reset; // SMP_HPS:h2f_rst_n -> [pll_0:rst, rst_controller:reset_in0, rst_controller_001:reset_in0]
wire [1:0] smp_hps_h2f_lw_axi_master_awburst; // SMP_HPS:h2f_lw_AWBURST -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awburst
wire [3:0] smp_hps_h2f_lw_axi_master_arlen; // SMP_HPS:h2f_lw_ARLEN -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arlen
wire [3:0] smp_hps_h2f_lw_axi_master_wstrb; // SMP_HPS:h2f_lw_WSTRB -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wstrb
wire smp_hps_h2f_lw_axi_master_wready; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wready -> SMP_HPS:h2f_lw_WREADY
wire [11:0] smp_hps_h2f_lw_axi_master_rid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rid -> SMP_HPS:h2f_lw_RID
wire smp_hps_h2f_lw_axi_master_rready; // SMP_HPS:h2f_lw_RREADY -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rready
wire [3:0] smp_hps_h2f_lw_axi_master_awlen; // SMP_HPS:h2f_lw_AWLEN -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awlen
wire [11:0] smp_hps_h2f_lw_axi_master_wid; // SMP_HPS:h2f_lw_WID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wid
wire [3:0] smp_hps_h2f_lw_axi_master_arcache; // SMP_HPS:h2f_lw_ARCACHE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arcache
wire smp_hps_h2f_lw_axi_master_wvalid; // SMP_HPS:h2f_lw_WVALID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wvalid
wire [20:0] smp_hps_h2f_lw_axi_master_araddr; // SMP_HPS:h2f_lw_ARADDR -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_araddr
wire [2:0] smp_hps_h2f_lw_axi_master_arprot; // SMP_HPS:h2f_lw_ARPROT -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arprot
wire [2:0] smp_hps_h2f_lw_axi_master_awprot; // SMP_HPS:h2f_lw_AWPROT -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awprot
wire [31:0] smp_hps_h2f_lw_axi_master_wdata; // SMP_HPS:h2f_lw_WDATA -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wdata
wire smp_hps_h2f_lw_axi_master_arvalid; // SMP_HPS:h2f_lw_ARVALID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arvalid
wire [3:0] smp_hps_h2f_lw_axi_master_awcache; // SMP_HPS:h2f_lw_AWCACHE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awcache
wire [11:0] smp_hps_h2f_lw_axi_master_arid; // SMP_HPS:h2f_lw_ARID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arid
wire [1:0] smp_hps_h2f_lw_axi_master_arlock; // SMP_HPS:h2f_lw_ARLOCK -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arlock
wire [1:0] smp_hps_h2f_lw_axi_master_awlock; // SMP_HPS:h2f_lw_AWLOCK -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awlock
wire [20:0] smp_hps_h2f_lw_axi_master_awaddr; // SMP_HPS:h2f_lw_AWADDR -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awaddr
wire [1:0] smp_hps_h2f_lw_axi_master_bresp; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bresp -> SMP_HPS:h2f_lw_BRESP
wire smp_hps_h2f_lw_axi_master_arready; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arready -> SMP_HPS:h2f_lw_ARREADY
wire [31:0] smp_hps_h2f_lw_axi_master_rdata; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rdata -> SMP_HPS:h2f_lw_RDATA
wire smp_hps_h2f_lw_axi_master_awready; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awready -> SMP_HPS:h2f_lw_AWREADY
wire [1:0] smp_hps_h2f_lw_axi_master_arburst; // SMP_HPS:h2f_lw_ARBURST -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arburst
wire [2:0] smp_hps_h2f_lw_axi_master_arsize; // SMP_HPS:h2f_lw_ARSIZE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arsize
wire smp_hps_h2f_lw_axi_master_bready; // SMP_HPS:h2f_lw_BREADY -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bready
wire smp_hps_h2f_lw_axi_master_rlast; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rlast -> SMP_HPS:h2f_lw_RLAST
wire smp_hps_h2f_lw_axi_master_wlast; // SMP_HPS:h2f_lw_WLAST -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wlast
wire [1:0] smp_hps_h2f_lw_axi_master_rresp; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rresp -> SMP_HPS:h2f_lw_RRESP
wire [11:0] smp_hps_h2f_lw_axi_master_awid; // SMP_HPS:h2f_lw_AWID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awid
wire [11:0] smp_hps_h2f_lw_axi_master_bid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bid -> SMP_HPS:h2f_lw_BID
wire smp_hps_h2f_lw_axi_master_bvalid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bvalid -> SMP_HPS:h2f_lw_BVALID
wire [2:0] smp_hps_h2f_lw_axi_master_awsize; // SMP_HPS:h2f_lw_AWSIZE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awsize
wire smp_hps_h2f_lw_axi_master_awvalid; // SMP_HPS:h2f_lw_AWVALID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awvalid
wire smp_hps_h2f_lw_axi_master_rvalid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rvalid -> SMP_HPS:h2f_lw_RVALID
wire mm_interconnect_0_pio_0_s1_chipselect; // mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
wire [31:0] mm_interconnect_0_pio_0_s1_readdata; // pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
wire [1:0] mm_interconnect_0_pio_0_s1_address; // mm_interconnect_0:pio_0_s1_address -> pio_0:address
wire mm_interconnect_0_pio_0_s1_write; // mm_interconnect_0:pio_0_s1_write -> pio_0:write_n
wire [31:0] mm_interconnect_0_pio_0_s1_writedata; // mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:pio_0_reset_reset_bridge_in_reset_reset, pio_0:reset_n]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
hps_design_SMP_HPS #(
.F2S_Width (0),
.S2F_Width (0)
) smp_hps (
.mem_a (hps_ddr_mem_a), // memory.mem_a
.mem_ba (hps_ddr_mem_ba), // .mem_ba
.mem_ck (hps_ddr_mem_ck), // .mem_ck
.mem_ck_n (hps_ddr_mem_ck_n), // .mem_ck_n
.mem_cke (hps_ddr_mem_cke), // .mem_cke
.mem_cs_n (hps_ddr_mem_cs_n), // .mem_cs_n
.mem_ras_n (hps_ddr_mem_ras_n), // .mem_ras_n
.mem_cas_n (hps_ddr_mem_cas_n), // .mem_cas_n
.mem_we_n (hps_ddr_mem_we_n), // .mem_we_n
.mem_reset_n (hps_ddr_mem_reset_n), // .mem_reset_n
.mem_dq (hps_ddr_mem_dq), // .mem_dq
.mem_dqs (hps_ddr_mem_dqs), // .mem_dqs
.mem_dqs_n (hps_ddr_mem_dqs_n), // .mem_dqs_n
.mem_odt (hps_ddr_mem_odt), // .mem_odt
.mem_dm (hps_ddr_mem_dm), // .mem_dm
.oct_rzqin (hps_ddr_oct_rzqin), // .oct_rzqin
.h2f_rst_n (smp_hps_h2f_reset_reset), // h2f_reset.reset_n
.h2f_lw_axi_clk (pll_0_outclk0_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (smp_hps_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (smp_hps_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (smp_hps_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (smp_hps_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (smp_hps_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (smp_hps_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (smp_hps_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (smp_hps_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (smp_hps_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (smp_hps_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (smp_hps_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (smp_hps_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (smp_hps_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (smp_hps_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (smp_hps_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (smp_hps_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (smp_hps_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (smp_hps_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (smp_hps_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (smp_hps_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (smp_hps_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (smp_hps_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (smp_hps_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (smp_hps_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (smp_hps_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (smp_hps_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (smp_hps_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (smp_hps_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (smp_hps_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (smp_hps_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (smp_hps_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (smp_hps_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (smp_hps_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (smp_hps_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (smp_hps_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (smp_hps_h2f_lw_axi_master_rready) // .rready
);
hps_design_pio_0 pio_0 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_0_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.out_port (ledr_export) // external_connection.export
);
hps_design_pll_0 pll_0 (
.refclk (clk_clk), // refclk.clk
.rst (~smp_hps_h2f_reset_reset), // reset.reset
.outclk_0 (pll_0_outclk0_clk), // outclk0.clk
.outclk_1 (), // outclk1.clk
.outclk_2 (pll_0_sdram_clk), // outclk2.clk
.locked () // (terminated)
);
hps_design_mm_interconnect_0 mm_interconnect_0 (
.SMP_HPS_h2f_lw_axi_master_awid (smp_hps_h2f_lw_axi_master_awid), // SMP_HPS_h2f_lw_axi_master.awid
.SMP_HPS_h2f_lw_axi_master_awaddr (smp_hps_h2f_lw_axi_master_awaddr), // .awaddr
.SMP_HPS_h2f_lw_axi_master_awlen (smp_hps_h2f_lw_axi_master_awlen), // .awlen
.SMP_HPS_h2f_lw_axi_master_awsize (smp_hps_h2f_lw_axi_master_awsize), // .awsize
.SMP_HPS_h2f_lw_axi_master_awburst (smp_hps_h2f_lw_axi_master_awburst), // .awburst
.SMP_HPS_h2f_lw_axi_master_awlock (smp_hps_h2f_lw_axi_master_awlock), // .awlock
.SMP_HPS_h2f_lw_axi_master_awcache (smp_hps_h2f_lw_axi_master_awcache), // .awcache
.SMP_HPS_h2f_lw_axi_master_awprot (smp_hps_h2f_lw_axi_master_awprot), // .awprot
.SMP_HPS_h2f_lw_axi_master_awvalid (smp_hps_h2f_lw_axi_master_awvalid), // .awvalid
.SMP_HPS_h2f_lw_axi_master_awready (smp_hps_h2f_lw_axi_master_awready), // .awready
.SMP_HPS_h2f_lw_axi_master_wid (smp_hps_h2f_lw_axi_master_wid), // .wid
.SMP_HPS_h2f_lw_axi_master_wdata (smp_hps_h2f_lw_axi_master_wdata), // .wdata
.SMP_HPS_h2f_lw_axi_master_wstrb (smp_hps_h2f_lw_axi_master_wstrb), // .wstrb
.SMP_HPS_h2f_lw_axi_master_wlast (smp_hps_h2f_lw_axi_master_wlast), // .wlast
.SMP_HPS_h2f_lw_axi_master_wvalid (smp_hps_h2f_lw_axi_master_wvalid), // .wvalid
.SMP_HPS_h2f_lw_axi_master_wready (smp_hps_h2f_lw_axi_master_wready), // .wready
.SMP_HPS_h2f_lw_axi_master_bid (smp_hps_h2f_lw_axi_master_bid), // .bid
.SMP_HPS_h2f_lw_axi_master_bresp (smp_hps_h2f_lw_axi_master_bresp), // .bresp
.SMP_HPS_h2f_lw_axi_master_bvalid (smp_hps_h2f_lw_axi_master_bvalid), // .bvalid
.SMP_HPS_h2f_lw_axi_master_bready (smp_hps_h2f_lw_axi_master_bready), // .bready
.SMP_HPS_h2f_lw_axi_master_arid (smp_hps_h2f_lw_axi_master_arid), // .arid
.SMP_HPS_h2f_lw_axi_master_araddr (smp_hps_h2f_lw_axi_master_araddr), // .araddr
.SMP_HPS_h2f_lw_axi_master_arlen (smp_hps_h2f_lw_axi_master_arlen), // .arlen
.SMP_HPS_h2f_lw_axi_master_arsize (smp_hps_h2f_lw_axi_master_arsize), // .arsize
.SMP_HPS_h2f_lw_axi_master_arburst (smp_hps_h2f_lw_axi_master_arburst), // .arburst
.SMP_HPS_h2f_lw_axi_master_arlock (smp_hps_h2f_lw_axi_master_arlock), // .arlock
.SMP_HPS_h2f_lw_axi_master_arcache (smp_hps_h2f_lw_axi_master_arcache), // .arcache
.SMP_HPS_h2f_lw_axi_master_arprot (smp_hps_h2f_lw_axi_master_arprot), // .arprot
.SMP_HPS_h2f_lw_axi_master_arvalid (smp_hps_h2f_lw_axi_master_arvalid), // .arvalid
.SMP_HPS_h2f_lw_axi_master_arready (smp_hps_h2f_lw_axi_master_arready), // .arready
.SMP_HPS_h2f_lw_axi_master_rid (smp_hps_h2f_lw_axi_master_rid), // .rid
.SMP_HPS_h2f_lw_axi_master_rdata (smp_hps_h2f_lw_axi_master_rdata), // .rdata
.SMP_HPS_h2f_lw_axi_master_rresp (smp_hps_h2f_lw_axi_master_rresp), // .rresp
.SMP_HPS_h2f_lw_axi_master_rlast (smp_hps_h2f_lw_axi_master_rlast), // .rlast
.SMP_HPS_h2f_lw_axi_master_rvalid (smp_hps_h2f_lw_axi_master_rvalid), // .rvalid
.SMP_HPS_h2f_lw_axi_master_rready (smp_hps_h2f_lw_axi_master_rready), // .rready
.pll_0_outclk0_clk (pll_0_outclk0_clk), // pll_0_outclk0.clk
.pio_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // pio_0_reset_reset_bridge_in_reset.reset
.SMP_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // SMP_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.pio_0_s1_address (mm_interconnect_0_pio_0_s1_address), // pio_0_s1.address
.pio_0_s1_write (mm_interconnect_0_pio_0_s1_write), // .write
.pio_0_s1_readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.pio_0_s1_writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.pio_0_s1_chipselect (mm_interconnect_0_pio_0_s1_chipselect) // .chipselect
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~smp_hps_h2f_reset_reset), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~smp_hps_h2f_reset_reset), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_2port.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// --------------------------------------------------------
// Quartus Prime Verilog Template
// True Dual Port RAM with single clock
module true_dual_port_ram_single_clock
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)
(
input [(DATA_WIDTH-1):0] data_a, data_b,
input [(ADDR_WIDTH-1):0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [(DATA_WIDTH-1):0] q_a, q_b
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule
// --------------------------------------------------------
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_2port (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [4:0] address_a;
input [4:0] address_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] q_a = sub_wire0[31:0];
wire [31:0] q_b = sub_wire1[31:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
`ifdef NO_PLI
altsyncram_component.init_file = "../../program/program.rif"
`else
altsyncram_component.init_file = "../../program/program.hex"
`endif
,
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.numwords_b = 32,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../program/program.hex"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../program/program.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL "address_a[4..0]"
// Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL "address_b[4..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_2port.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_2port.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_2port.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_2port.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_2port_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_2port_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: ITCR
// Engineer: Yermy Benavides
//
// Create Date: 21:40:24 02/29/2016
// Design Name: MDF
// Module Name: D:/ISE/Proyecto1/TB_MDF.v
// Project Name: Proyecto1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MDF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_MDF;
// Inputs
reg clk;
reg rst;
reg [3:0] entrada;
// Outputs
wire salida;
wire [15:0]q;
// Instantiate the Unit Under Test (UUT)
MDF uut (
.clk(clk),
.rst(rst),
.entrada(entrada),
.salida(salida),
.q(q)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
entrada = 0;
// Wait 100 ns for global reset to finish
#10;
entrada = 4'b1111;
#10000;
entrada = 4'b1010;
end
always #1000 clk = ~clk;
/* initial
begin
$monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,rst,div,clkd);
end
initial
#500 $finish;
*/
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "include/mbus_def.v"
module layer_wrapper(
// layer controller
CLK,
RESETn,
INT_VECTOR,
CLR_INT_EXTERNAL,
// mbus
CLKIN,
CLKOUT,
DIN,
DOUT
);
parameter RF_DEPTH = 64; // this number is intend to be less than LC_RF_DEPTH
parameter ROM_DEPTH = 64;
parameter ADDRESS = 20'hccccc;
parameter LC_RF_DATA_WIDTH =24;
parameter LC_RF_DEPTH = 128; // 1 ~ 2^8
parameter LC_MEM_DATA_WIDTH = 32; // should ALWAYS less than DATA_WIDTH
parameter LC_MEM_ADDR_WIDTH = 32; // should ALWAYS less than DATA_WIDTH
parameter LC_MEM_DEPTH = 65536; // 1 ~ 2^30
parameter LC_INT_DEPTH = 8;
input CLK;
input RESETn;
input [LC_INT_DEPTH-1:0] INT_VECTOR;
output [LC_INT_DEPTH-1:0] CLR_INT_EXTERNAL;
input CLKIN;
output CLKOUT;
input DIN;
output DOUT;
// from layer controller, need isolation
// Mem
wire mem_req_out, mem_write;
wire [LC_MEM_DATA_WIDTH-1:0] mem_dout;
wire [LC_MEM_ADDR_WIDTH-3:0] mem_aout;
// RF
wire [LC_RF_DATA_WIDTH-1:0] rf_dout;
wire [LC_RF_DEPTH-1:0] rf_load;
// Mbus
wire [`ADDR_WIDTH-1:0] tx_addr;
wire [`DATA_WIDTH-1:0] tx_data;
wire tx_req, tx_priority, tx_pend, tx_resp_ack;
wire tx_ack, tx_succ, tx_fail;
// Interrupt
wire [LC_INT_DEPTH-1:0] clr_int;
// unknown state when power if off
// Mem
reg mem_req_out_f_lc, mem_write_f_lc;
reg [LC_MEM_DATA_WIDTH-1:0] mem_dout_f_lc;
reg [LC_MEM_ADDR_WIDTH-3:0] mem_aout_f_lc;
// RF
reg [LC_RF_DATA_WIDTH-1:0] rf_dout_f_lc;
reg [LC_RF_DEPTH-1:0] rf_load_f_lc;
// Mbus
reg [`ADDR_WIDTH-1:0] tx_addr_f_lc;
reg [`DATA_WIDTH-1:0] tx_data_f_lc;
reg tx_req_f_lc, priority_f_lc, tx_pend_f_lc, tx_resp_ack_f_lc;
reg rx_ack_f_lc;
// Interrupt
reg [LC_INT_DEPTH-1:0] clr_int_f_lc;
// output from isolation
// Mem
wire mem_req_out_t_mem, mem_write_t_mem;
wire [LC_MEM_DATA_WIDTH-1:0] mem_dout_t_mem;
wire [LC_MEM_ADDR_WIDTH-3:0] mem_aout_t_mem;
// RF
wire [LC_RF_DATA_WIDTH-1:0] rf_dout_t_rf;
wire [LC_RF_DEPTH-1:0] rf_load_t_rf;
// Mbus
wire [`ADDR_WIDTH-1:0] tx_addr_t_mbus;
wire [`DATA_WIDTH-1:0] tx_data_t_mbus;
wire tx_req_t_mbus, priority_t_mbus, tx_pend_t_mbus, tx_resp_ack_t_mbus;
wire rx_ack_t_mbus;
// To layer controller, doesn't need isolation
// MEM
wire mem_ack_f_mem;
wire [LC_MEM_DATA_WIDTH-1:0] mem_data_f_mem;
// RF
wire [LC_RF_DATA_WIDTH*RF_DEPTH-1:0] rf_dout_f_rf;
// ROM
wire [LC_RF_DATA_WIDTH*ROM_DEPTH-1:0] sensor_dat_f_rom;
wire [`FUNC_WIDTH*LC_INT_DEPTH-1:0] int_func_id_f_rom;
wire [(`DATA_WIDTH<<1)*LC_INT_DEPTH-1:0] int_payload_f_rom;
// Mbus
wire [`ADDR_WIDTH-1:0] rx_addr;
wire [`DATA_WIDTH-1:0] rx_data;
wire rx_req, rx_fail, rx_pend, rx_broadcast;
wire rx_ack;
// Power signals
wire lc_pwr_on, lc_release_clk, lc_release_rst, lc_release_iso;
// interrupt, clock
wire req_int = (INT_VECTOR>0)? 1'b1 : 1'b0;
wire CLK_LC = (CLK&(~lc_release_clk));
// always on isolation
layer_ctrl_isolation #(
.LC_RF_DATA_WIDTH(LC_RF_DATA_WIDTH), .LC_RF_DEPTH(LC_RF_DEPTH),
.LC_MEM_DATA_WIDTH(LC_MEM_DATA_WIDTH), .LC_MEM_ADDR_WIDTH(LC_MEM_ADDR_WIDTH),
.LC_INT_DEPTH(LC_INT_DEPTH)) lc_iso0(
.LC_ISOLATION(lc_release_iso),
// Interface with MBus
.TX_ADDR_FROM_LC(tx_addr_f_lc), .TX_DATA_FROM_LC(tx_data_f_lc), .TX_PEND_FROM_LC(tx_pend_f_lc), .TX_REQ_FROM_LC(tx_req_f_lc),
.PRIORITY_FROM_LC(priority_f_lc), .RX_ACK_FROM_LC(rx_ack_f_lc), .TX_RESP_ACK_FROM_LC(tx_resp_ack_f_lc),
// Interface with Registers
.RF_DATA_FROM_LC(rf_dout_f_lc), .RF_LOAD_FROM_LC(rf_load_f_lc),
// Interface with MEM
.MEM_REQ_OUT_FROM_LC(mem_req_out_f_lc), .MEM_WRITE_FROM_LC(mem_write_f_lc), .MEM_DOUT_FROM_LC(mem_dout_f_lc), .MEM_AOUT_FROM_LC(mem_aout_f_lc),
// Interrupt
.CLR_INT_FROM_LC(clr_int_f_lc),
// Interface with MBus
.TX_ADDR_TO_MBUS(tx_addr_t_mbus), .TX_DATA_TO_MBUS(tx_data_t_mbus), .TX_PEND_TO_MBUS(tx_pend_t_mbus), .TX_REQ_TO_MBUS(tx_req_t_mbus),
.PRIORITY_TO_MBUS(priority_t_mbus), .RX_ACK_TO_MBUS(rx_ack_t_mbus), .TX_RESP_ACK_TO_MBUS(tx_resp_ack_t_mbus),
// Interface with Registers
.RF_DATA_TO_RF(rf_dout_t_rf), .RF_LOAD_TO_RF(rf_load_t_rf),
// Interface with MEM
.MEM_REQ_OUT_TO_MEM(mem_req_out_t_mem), .MEM_WRITE_TO_MEM(mem_write_t_mem), .MEM_DOUT_TO_MEM(mem_dout_t_mem), .MEM_AOUT_TO_MEM(mem_aout_t_mem),
// Interrupt
.CLR_INT_EXTERNAL(CLR_INT_EXTERNAL)
);
layer_ctrl
#(.LC_RF_DATA_WIDTH(LC_RF_DATA_WIDTH), .LC_RF_DEPTH(LC_RF_DEPTH),
.LC_MEM_DATA_WIDTH(LC_MEM_DATA_WIDTH), .LC_MEM_ADDR_WIDTH(LC_MEM_ADDR_WIDTH), .LC_MEM_DEPTH(LC_MEM_DEPTH),
.LC_INT_DEPTH(LC_INT_DEPTH)) lc0(
.CLK(CLK_LC),
.RESETn(RESETn),
// Interface with MBus
.TX_ADDR(tx_addr),
.TX_DATA(tx_data),
.TX_PEND(tx_pend),
.TX_REQ(tx_req),
.TX_ACK(tx_ack),
.TX_PRIORITY(tx_priority),
.RX_ADDR(rx_addr),
.RX_DATA(rx_data),
.RX_PEND(rx_pend),
.RX_REQ(rx_req),
.RX_ACK(rx_ack),
.RX_BROADCAST(rx_broadcast),
.RX_FAIL(rx_fail),
.TX_FAIL(tx_fail),
.TX_SUCC(tx_succ),
.TX_RESP_ACK(tx_resp_ack),
.RELEASE_RST_FROM_MBUS(lc_release_rst),
// Interface with Registers
.REG_RD_DATA({sensor_dat_f_rom, rf_dout_f_rf}),
.REG_WR_DATA(rf_dout),
.REG_WR_EN(rf_load),
// Interface with MEM
.MEM_REQ_OUT(mem_req_out),
.MEM_WRITE(mem_write),
.MEM_ACK_IN(mem_ack_f_mem),
.MEM_WR_DATA(mem_dout),
.MEM_RD_DATA(mem_data_f_mem),
.MEM_ADDR(mem_aout),
// Interrupt
.INT_VECTOR(INT_VECTOR),
.CLR_INT(clr_int),
.INT_FU_ID(int_func_id_f_rom),
.INT_CMD(int_payload_f_rom)
);
mbus_layer_wrapper #(.ADDRESS(ADDRESS)) mbus_node0
(.CLKIN(CLKIN), .CLKOUT(CLKOUT), .RESETn(RESETn), .DIN(DIN), .DOUT(DOUT),
.TX_ADDR(tx_addr_t_mbus), .TX_DATA(tx_data_t_mbus), .TX_REQ(tx_req_t_mbus), .TX_ACK(tx_ack), .TX_PEND(tx_pend_t_mbus), .TX_PRIORITY(priority_t_mbus),
.RX_ADDR(rx_addr), .RX_DATA(rx_data), .RX_REQ(rx_req), .RX_ACK(rx_ack_t_mbus), .RX_FAIL(rx_fail), .RX_PEND(rx_pend),
.TX_SUCC(tx_succ), .TX_FAIL(tx_fail), .TX_RESP_ACK(tx_resp_ack_t_mbus), .RX_BROADCAST(rx_broadcast),
.LC_POWER_ON(lc_pwr_on), .LC_RELEASE_CLK(lc_release_clk), .LC_RELEASE_RST(lc_release_rst), .LC_RELEASE_ISO(lc_release_iso),
.REQ_INT(req_int));
always @ *
begin
// LC is power off, output from LC should be XXXX
if (lc_pwr_on)
begin
tx_addr_f_lc = {(`ADDR_WIDTH){1'bx}};
tx_data_f_lc = {(`DATA_WIDTH){1'bx}};
tx_pend_f_lc = 1'bx;
tx_req_f_lc = 1'bx;
priority_f_lc = 1'bx;
rx_ack_f_lc = 1'bx;
tx_resp_ack_f_lc = 1'bx;
end
else
begin
tx_addr_f_lc = tx_addr;
tx_data_f_lc = tx_data;
tx_pend_f_lc = tx_pend;
tx_req_f_lc = tx_req;
priority_f_lc = tx_priority;
rx_ack_f_lc = rx_ack;
tx_resp_ack_f_lc = tx_resp_ack;
end
end
always @ *
begin
if (lc_pwr_on)
begin
rf_dout_f_lc= {(LC_RF_DATA_WIDTH){1'bx}};
rf_load_f_lc = {(LC_RF_DEPTH){1'bx}};
end
else
begin
rf_dout_f_lc = rf_dout;
rf_load_f_lc = rf_load;
end
end
always @ *
begin
if (lc_pwr_on)
begin
mem_req_out_f_lc = 1'bx;
mem_write_f_lc = 1'bx;
mem_dout_f_lc = {(LC_MEM_DATA_WIDTH){1'bx}};
mem_aout_f_lc = {(LC_MEM_ADDR_WIDTH-2){1'bx}};
end
else
begin
mem_req_out_f_lc = mem_req_out;
mem_write_f_lc = mem_write;
mem_dout_f_lc = mem_dout;
mem_aout_f_lc = mem_aout;
end
end
always @ *
begin
if (lc_pwr_on)
begin
clr_int_f_lc = 1'bx;
end
else
begin
clr_int_f_lc = clr_int;
end
end
// always on MEM
mem_ctrl #(.MEM_DEPTH(LC_MEM_DEPTH), .LC_MEM_DATA_WIDTH(LC_MEM_DATA_WIDTH), .LC_MEM_ADDR_WIDTH(LC_MEM_ADDR_WIDTH)) mem0(
.CLK(CLK),
.RESETn(RESETn),
.ADDR(mem_aout_t_mem),
.DATA_IN(mem_dout_t_mem),
.MEM_REQ(mem_req_out_t_mem),
.MEM_WRITE(mem_write_t_mem),
.DATA_OUT(mem_data_f_mem),
.MEM_ACK_OUT(mem_ack_f_mem)
);
// always on RF
rf_ctrl #(.RF_DEPTH(RF_DEPTH)) rf0(
.RESETn(RESETn),
.DIN(rf_dout_t_rf),
.LOAD(rf_load_t_rf[RF_DEPTH-1:0]),
.DOUT(rf_dout_f_rf)
);
// always on sensor roms
sensor_rom #(.ROM_DEPTH(ROM_DEPTH)) r0(
.DOUT(sensor_dat_f_rom)
);
// always on interrupt command roms
int_action_rom #(.LC_INT_DEPTH(LC_INT_DEPTH), .LC_RF_DEPTH(LC_RF_DEPTH), .LC_MEM_DEPTH(LC_MEM_DEPTH)) ir0(
.int_func_id(int_func_id_f_rom),
.int_payload(int_payload_f_rom)
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file obc_lower.v when simulating
// the core, obc_lower. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module obc_lower(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_MUX_2TO1_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_MUX_2TO1_SYMBOL_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_mux_2to1 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_MUX_2TO1_SYMBOL_V
|
module wb_intercon
(input wb_clk_i,
input wb_rst_i,
input [31:0] wb_dbg_adr_i,
input [31:0] wb_dbg_dat_i,
input [3:0] wb_dbg_sel_i,
input wb_dbg_we_i,
input wb_dbg_cyc_i,
input wb_dbg_stb_i,
input [2:0] wb_dbg_cti_i,
input [1:0] wb_dbg_bte_i,
output [31:0] wb_dbg_dat_o,
output wb_dbg_ack_o,
output wb_dbg_err_o,
output wb_dbg_rty_o,
input [31:0] wb_or1k_i_adr_i,
input [31:0] wb_or1k_i_dat_i,
input [3:0] wb_or1k_i_sel_i,
input wb_or1k_i_we_i,
input wb_or1k_i_cyc_i,
input wb_or1k_i_stb_i,
input [2:0] wb_or1k_i_cti_i,
input [1:0] wb_or1k_i_bte_i,
output [31:0] wb_or1k_i_dat_o,
output wb_or1k_i_ack_o,
output wb_or1k_i_err_o,
output wb_or1k_i_rty_o,
input [31:0] wb_or1k_d_adr_i,
input [31:0] wb_or1k_d_dat_i,
input [3:0] wb_or1k_d_sel_i,
input wb_or1k_d_we_i,
input wb_or1k_d_cyc_i,
input wb_or1k_d_stb_i,
input [2:0] wb_or1k_d_cti_i,
input [1:0] wb_or1k_d_bte_i,
output [31:0] wb_or1k_d_dat_o,
output wb_or1k_d_ack_o,
output wb_or1k_d_err_o,
output wb_or1k_d_rty_o,
output [31:0] wb_uart0_adr_o,
output [7:0] wb_uart0_dat_o,
output [3:0] wb_uart0_sel_o,
output wb_uart0_we_o,
output wb_uart0_cyc_o,
output wb_uart0_stb_o,
output [2:0] wb_uart0_cti_o,
output [1:0] wb_uart0_bte_o,
input [7:0] wb_uart0_dat_i,
input wb_uart0_ack_i,
input wb_uart0_err_i,
input wb_uart0_rty_i,
output [31:0] wb_sdram_dbus_adr_o,
output [31:0] wb_sdram_dbus_dat_o,
output [3:0] wb_sdram_dbus_sel_o,
output wb_sdram_dbus_we_o,
output wb_sdram_dbus_cyc_o,
output wb_sdram_dbus_stb_o,
output [2:0] wb_sdram_dbus_cti_o,
output [1:0] wb_sdram_dbus_bte_o,
input [31:0] wb_sdram_dbus_dat_i,
input wb_sdram_dbus_ack_i,
input wb_sdram_dbus_err_i,
input wb_sdram_dbus_rty_i,
output [31:0] wb_gpio0_adr_o,
output [7:0] wb_gpio0_dat_o,
output [3:0] wb_gpio0_sel_o,
output wb_gpio0_we_o,
output wb_gpio0_cyc_o,
output wb_gpio0_stb_o,
output [2:0] wb_gpio0_cti_o,
output [1:0] wb_gpio0_bte_o,
input [7:0] wb_gpio0_dat_i,
input wb_gpio0_ack_i,
input wb_gpio0_err_i,
input wb_gpio0_rty_i,
output [31:0] wb_rom0_adr_o,
output [31:0] wb_rom0_dat_o,
output [3:0] wb_rom0_sel_o,
output wb_rom0_we_o,
output wb_rom0_cyc_o,
output wb_rom0_stb_o,
output [2:0] wb_rom0_cti_o,
output [1:0] wb_rom0_bte_o,
input [31:0] wb_rom0_dat_i,
input wb_rom0_ack_i,
input wb_rom0_err_i,
input wb_rom0_rty_i,
output [31:0] wb_sdram_ibus_adr_o,
output [31:0] wb_sdram_ibus_dat_o,
output [3:0] wb_sdram_ibus_sel_o,
output wb_sdram_ibus_we_o,
output wb_sdram_ibus_cyc_o,
output wb_sdram_ibus_stb_o,
output [2:0] wb_sdram_ibus_cti_o,
output [1:0] wb_sdram_ibus_bte_o,
input [31:0] wb_sdram_ibus_dat_i,
input wb_sdram_ibus_ack_i,
input wb_sdram_ibus_err_i,
input wb_sdram_ibus_rty_i);
wire [31:0] wb_m2s_dbg_sdram_dbus_adr;
wire [31:0] wb_m2s_dbg_sdram_dbus_dat;
wire [3:0] wb_m2s_dbg_sdram_dbus_sel;
wire wb_m2s_dbg_sdram_dbus_we;
wire wb_m2s_dbg_sdram_dbus_cyc;
wire wb_m2s_dbg_sdram_dbus_stb;
wire [2:0] wb_m2s_dbg_sdram_dbus_cti;
wire [1:0] wb_m2s_dbg_sdram_dbus_bte;
wire [31:0] wb_s2m_dbg_sdram_dbus_dat;
wire wb_s2m_dbg_sdram_dbus_ack;
wire wb_s2m_dbg_sdram_dbus_err;
wire wb_s2m_dbg_sdram_dbus_rty;
wire [31:0] wb_m2s_dbg_uart0_adr;
wire [31:0] wb_m2s_dbg_uart0_dat;
wire [3:0] wb_m2s_dbg_uart0_sel;
wire wb_m2s_dbg_uart0_we;
wire wb_m2s_dbg_uart0_cyc;
wire wb_m2s_dbg_uart0_stb;
wire [2:0] wb_m2s_dbg_uart0_cti;
wire [1:0] wb_m2s_dbg_uart0_bte;
wire [31:0] wb_s2m_dbg_uart0_dat;
wire wb_s2m_dbg_uart0_ack;
wire wb_s2m_dbg_uart0_err;
wire wb_s2m_dbg_uart0_rty;
wire [31:0] wb_m2s_dbg_gpio0_adr;
wire [31:0] wb_m2s_dbg_gpio0_dat;
wire [3:0] wb_m2s_dbg_gpio0_sel;
wire wb_m2s_dbg_gpio0_we;
wire wb_m2s_dbg_gpio0_cyc;
wire wb_m2s_dbg_gpio0_stb;
wire [2:0] wb_m2s_dbg_gpio0_cti;
wire [1:0] wb_m2s_dbg_gpio0_bte;
wire [31:0] wb_s2m_dbg_gpio0_dat;
wire wb_s2m_dbg_gpio0_ack;
wire wb_s2m_dbg_gpio0_err;
wire wb_s2m_dbg_gpio0_rty;
wire [31:0] wb_m2s_or1k_d_sdram_dbus_adr;
wire [31:0] wb_m2s_or1k_d_sdram_dbus_dat;
wire [3:0] wb_m2s_or1k_d_sdram_dbus_sel;
wire wb_m2s_or1k_d_sdram_dbus_we;
wire wb_m2s_or1k_d_sdram_dbus_cyc;
wire wb_m2s_or1k_d_sdram_dbus_stb;
wire [2:0] wb_m2s_or1k_d_sdram_dbus_cti;
wire [1:0] wb_m2s_or1k_d_sdram_dbus_bte;
wire [31:0] wb_s2m_or1k_d_sdram_dbus_dat;
wire wb_s2m_or1k_d_sdram_dbus_ack;
wire wb_s2m_or1k_d_sdram_dbus_err;
wire wb_s2m_or1k_d_sdram_dbus_rty;
wire [31:0] wb_m2s_or1k_d_uart0_adr;
wire [31:0] wb_m2s_or1k_d_uart0_dat;
wire [3:0] wb_m2s_or1k_d_uart0_sel;
wire wb_m2s_or1k_d_uart0_we;
wire wb_m2s_or1k_d_uart0_cyc;
wire wb_m2s_or1k_d_uart0_stb;
wire [2:0] wb_m2s_or1k_d_uart0_cti;
wire [1:0] wb_m2s_or1k_d_uart0_bte;
wire [31:0] wb_s2m_or1k_d_uart0_dat;
wire wb_s2m_or1k_d_uart0_ack;
wire wb_s2m_or1k_d_uart0_err;
wire wb_s2m_or1k_d_uart0_rty;
wire [31:0] wb_m2s_or1k_d_gpio0_adr;
wire [31:0] wb_m2s_or1k_d_gpio0_dat;
wire [3:0] wb_m2s_or1k_d_gpio0_sel;
wire wb_m2s_or1k_d_gpio0_we;
wire wb_m2s_or1k_d_gpio0_cyc;
wire wb_m2s_or1k_d_gpio0_stb;
wire [2:0] wb_m2s_or1k_d_gpio0_cti;
wire [1:0] wb_m2s_or1k_d_gpio0_bte;
wire [31:0] wb_s2m_or1k_d_gpio0_dat;
wire wb_s2m_or1k_d_gpio0_ack;
wire wb_s2m_or1k_d_gpio0_err;
wire wb_s2m_or1k_d_gpio0_rty;
wire [31:0] wb_m2s_resize_uart0_adr;
wire [31:0] wb_m2s_resize_uart0_dat;
wire [3:0] wb_m2s_resize_uart0_sel;
wire wb_m2s_resize_uart0_we;
wire wb_m2s_resize_uart0_cyc;
wire wb_m2s_resize_uart0_stb;
wire [2:0] wb_m2s_resize_uart0_cti;
wire [1:0] wb_m2s_resize_uart0_bte;
wire [31:0] wb_s2m_resize_uart0_dat;
wire wb_s2m_resize_uart0_ack;
wire wb_s2m_resize_uart0_err;
wire wb_s2m_resize_uart0_rty;
wire [31:0] wb_m2s_resize_gpio0_adr;
wire [31:0] wb_m2s_resize_gpio0_dat;
wire [3:0] wb_m2s_resize_gpio0_sel;
wire wb_m2s_resize_gpio0_we;
wire wb_m2s_resize_gpio0_cyc;
wire wb_m2s_resize_gpio0_stb;
wire [2:0] wb_m2s_resize_gpio0_cti;
wire [1:0] wb_m2s_resize_gpio0_bte;
wire [31:0] wb_s2m_resize_gpio0_dat;
wire wb_s2m_resize_gpio0_ack;
wire wb_s2m_resize_gpio0_err;
wire wb_s2m_resize_gpio0_rty;
wb_mux
#(.num_slaves (3),
.MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
.MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
wb_mux_dbg
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_dbg_adr_i),
.wbm_dat_i (wb_dbg_dat_i),
.wbm_sel_i (wb_dbg_sel_i),
.wbm_we_i (wb_dbg_we_i),
.wbm_cyc_i (wb_dbg_cyc_i),
.wbm_stb_i (wb_dbg_stb_i),
.wbm_cti_i (wb_dbg_cti_i),
.wbm_bte_i (wb_dbg_bte_i),
.wbm_dat_o (wb_dbg_dat_o),
.wbm_ack_o (wb_dbg_ack_o),
.wbm_err_o (wb_dbg_err_o),
.wbm_rty_o (wb_dbg_rty_o),
.wbs_adr_o ({wb_m2s_dbg_sdram_dbus_adr, wb_m2s_dbg_uart0_adr, wb_m2s_dbg_gpio0_adr}),
.wbs_dat_o ({wb_m2s_dbg_sdram_dbus_dat, wb_m2s_dbg_uart0_dat, wb_m2s_dbg_gpio0_dat}),
.wbs_sel_o ({wb_m2s_dbg_sdram_dbus_sel, wb_m2s_dbg_uart0_sel, wb_m2s_dbg_gpio0_sel}),
.wbs_we_o ({wb_m2s_dbg_sdram_dbus_we, wb_m2s_dbg_uart0_we, wb_m2s_dbg_gpio0_we}),
.wbs_cyc_o ({wb_m2s_dbg_sdram_dbus_cyc, wb_m2s_dbg_uart0_cyc, wb_m2s_dbg_gpio0_cyc}),
.wbs_stb_o ({wb_m2s_dbg_sdram_dbus_stb, wb_m2s_dbg_uart0_stb, wb_m2s_dbg_gpio0_stb}),
.wbs_cti_o ({wb_m2s_dbg_sdram_dbus_cti, wb_m2s_dbg_uart0_cti, wb_m2s_dbg_gpio0_cti}),
.wbs_bte_o ({wb_m2s_dbg_sdram_dbus_bte, wb_m2s_dbg_uart0_bte, wb_m2s_dbg_gpio0_bte}),
.wbs_dat_i ({wb_s2m_dbg_sdram_dbus_dat, wb_s2m_dbg_uart0_dat, wb_s2m_dbg_gpio0_dat}),
.wbs_ack_i ({wb_s2m_dbg_sdram_dbus_ack, wb_s2m_dbg_uart0_ack, wb_s2m_dbg_gpio0_ack}),
.wbs_err_i ({wb_s2m_dbg_sdram_dbus_err, wb_s2m_dbg_uart0_err, wb_s2m_dbg_gpio0_err}),
.wbs_rty_i ({wb_s2m_dbg_sdram_dbus_rty, wb_s2m_dbg_uart0_rty, wb_s2m_dbg_gpio0_rty}));
wb_mux
#(.num_slaves (2),
.MATCH_ADDR ({32'h00000000, 32'hf0000100}),
.MATCH_MASK ({32'hfe000000, 32'hffffffc0}))
wb_mux_or1k_i
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_or1k_i_adr_i),
.wbm_dat_i (wb_or1k_i_dat_i),
.wbm_sel_i (wb_or1k_i_sel_i),
.wbm_we_i (wb_or1k_i_we_i),
.wbm_cyc_i (wb_or1k_i_cyc_i),
.wbm_stb_i (wb_or1k_i_stb_i),
.wbm_cti_i (wb_or1k_i_cti_i),
.wbm_bte_i (wb_or1k_i_bte_i),
.wbm_dat_o (wb_or1k_i_dat_o),
.wbm_ack_o (wb_or1k_i_ack_o),
.wbm_err_o (wb_or1k_i_err_o),
.wbm_rty_o (wb_or1k_i_rty_o),
.wbs_adr_o ({wb_sdram_ibus_adr_o, wb_rom0_adr_o}),
.wbs_dat_o ({wb_sdram_ibus_dat_o, wb_rom0_dat_o}),
.wbs_sel_o ({wb_sdram_ibus_sel_o, wb_rom0_sel_o}),
.wbs_we_o ({wb_sdram_ibus_we_o, wb_rom0_we_o}),
.wbs_cyc_o ({wb_sdram_ibus_cyc_o, wb_rom0_cyc_o}),
.wbs_stb_o ({wb_sdram_ibus_stb_o, wb_rom0_stb_o}),
.wbs_cti_o ({wb_sdram_ibus_cti_o, wb_rom0_cti_o}),
.wbs_bte_o ({wb_sdram_ibus_bte_o, wb_rom0_bte_o}),
.wbs_dat_i ({wb_sdram_ibus_dat_i, wb_rom0_dat_i}),
.wbs_ack_i ({wb_sdram_ibus_ack_i, wb_rom0_ack_i}),
.wbs_err_i ({wb_sdram_ibus_err_i, wb_rom0_err_i}),
.wbs_rty_i ({wb_sdram_ibus_rty_i, wb_rom0_rty_i}));
wb_mux
#(.num_slaves (3),
.MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
.MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
wb_mux_or1k_d
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_or1k_d_adr_i),
.wbm_dat_i (wb_or1k_d_dat_i),
.wbm_sel_i (wb_or1k_d_sel_i),
.wbm_we_i (wb_or1k_d_we_i),
.wbm_cyc_i (wb_or1k_d_cyc_i),
.wbm_stb_i (wb_or1k_d_stb_i),
.wbm_cti_i (wb_or1k_d_cti_i),
.wbm_bte_i (wb_or1k_d_bte_i),
.wbm_dat_o (wb_or1k_d_dat_o),
.wbm_ack_o (wb_or1k_d_ack_o),
.wbm_err_o (wb_or1k_d_err_o),
.wbm_rty_o (wb_or1k_d_rty_o),
.wbs_adr_o ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_or1k_d_uart0_adr, wb_m2s_or1k_d_gpio0_adr}),
.wbs_dat_o ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_or1k_d_uart0_dat, wb_m2s_or1k_d_gpio0_dat}),
.wbs_sel_o ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_or1k_d_uart0_sel, wb_m2s_or1k_d_gpio0_sel}),
.wbs_we_o ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_or1k_d_uart0_we, wb_m2s_or1k_d_gpio0_we}),
.wbs_cyc_o ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_or1k_d_uart0_cyc, wb_m2s_or1k_d_gpio0_cyc}),
.wbs_stb_o ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_or1k_d_uart0_stb, wb_m2s_or1k_d_gpio0_stb}),
.wbs_cti_o ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_or1k_d_uart0_cti, wb_m2s_or1k_d_gpio0_cti}),
.wbs_bte_o ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_or1k_d_uart0_bte, wb_m2s_or1k_d_gpio0_bte}),
.wbs_dat_i ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_or1k_d_uart0_dat, wb_s2m_or1k_d_gpio0_dat}),
.wbs_ack_i ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_or1k_d_uart0_ack, wb_s2m_or1k_d_gpio0_ack}),
.wbs_err_i ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_or1k_d_uart0_err, wb_s2m_or1k_d_gpio0_err}),
.wbs_rty_i ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_or1k_d_uart0_rty, wb_s2m_or1k_d_gpio0_rty}));
wb_arbiter
#(.num_masters (2))
wb_arbiter_uart0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_or1k_d_uart0_adr, wb_m2s_dbg_uart0_adr}),
.wbm_dat_i ({wb_m2s_or1k_d_uart0_dat, wb_m2s_dbg_uart0_dat}),
.wbm_sel_i ({wb_m2s_or1k_d_uart0_sel, wb_m2s_dbg_uart0_sel}),
.wbm_we_i ({wb_m2s_or1k_d_uart0_we, wb_m2s_dbg_uart0_we}),
.wbm_cyc_i ({wb_m2s_or1k_d_uart0_cyc, wb_m2s_dbg_uart0_cyc}),
.wbm_stb_i ({wb_m2s_or1k_d_uart0_stb, wb_m2s_dbg_uart0_stb}),
.wbm_cti_i ({wb_m2s_or1k_d_uart0_cti, wb_m2s_dbg_uart0_cti}),
.wbm_bte_i ({wb_m2s_or1k_d_uart0_bte, wb_m2s_dbg_uart0_bte}),
.wbm_dat_o ({wb_s2m_or1k_d_uart0_dat, wb_s2m_dbg_uart0_dat}),
.wbm_ack_o ({wb_s2m_or1k_d_uart0_ack, wb_s2m_dbg_uart0_ack}),
.wbm_err_o ({wb_s2m_or1k_d_uart0_err, wb_s2m_dbg_uart0_err}),
.wbm_rty_o ({wb_s2m_or1k_d_uart0_rty, wb_s2m_dbg_uart0_rty}),
.wbs_adr_o (wb_m2s_resize_uart0_adr),
.wbs_dat_o (wb_m2s_resize_uart0_dat),
.wbs_sel_o (wb_m2s_resize_uart0_sel),
.wbs_we_o (wb_m2s_resize_uart0_we),
.wbs_cyc_o (wb_m2s_resize_uart0_cyc),
.wbs_stb_o (wb_m2s_resize_uart0_stb),
.wbs_cti_o (wb_m2s_resize_uart0_cti),
.wbs_bte_o (wb_m2s_resize_uart0_bte),
.wbs_dat_i (wb_s2m_resize_uart0_dat),
.wbs_ack_i (wb_s2m_resize_uart0_ack),
.wbs_err_i (wb_s2m_resize_uart0_err),
.wbs_rty_i (wb_s2m_resize_uart0_rty));
wb_data_resize
#(.aw (32),
.mdw (32),
.sdw (8))
wb_data_resize_uart0
(.wbm_adr_i (wb_m2s_resize_uart0_adr),
.wbm_dat_i (wb_m2s_resize_uart0_dat),
.wbm_sel_i (wb_m2s_resize_uart0_sel),
.wbm_we_i (wb_m2s_resize_uart0_we),
.wbm_cyc_i (wb_m2s_resize_uart0_cyc),
.wbm_stb_i (wb_m2s_resize_uart0_stb),
.wbm_cti_i (wb_m2s_resize_uart0_cti),
.wbm_bte_i (wb_m2s_resize_uart0_bte),
.wbm_dat_o (wb_s2m_resize_uart0_dat),
.wbm_ack_o (wb_s2m_resize_uart0_ack),
.wbm_err_o (wb_s2m_resize_uart0_err),
.wbm_rty_o (wb_s2m_resize_uart0_rty),
.wbs_adr_o (wb_uart0_adr_o),
.wbs_dat_o (wb_uart0_dat_o),
.wbs_we_o (wb_uart0_we_o),
.wbs_cyc_o (wb_uart0_cyc_o),
.wbs_stb_o (wb_uart0_stb_o),
.wbs_cti_o (wb_uart0_cti_o),
.wbs_bte_o (wb_uart0_bte_o),
.wbs_dat_i (wb_uart0_dat_i),
.wbs_ack_i (wb_uart0_ack_i),
.wbs_err_i (wb_uart0_err_i),
.wbs_rty_i (wb_uart0_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_sdram_dbus
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_dbg_sdram_dbus_adr}),
.wbm_dat_i ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_dbg_sdram_dbus_dat}),
.wbm_sel_i ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_dbg_sdram_dbus_sel}),
.wbm_we_i ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_dbg_sdram_dbus_we}),
.wbm_cyc_i ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_dbg_sdram_dbus_cyc}),
.wbm_stb_i ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_dbg_sdram_dbus_stb}),
.wbm_cti_i ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_dbg_sdram_dbus_cti}),
.wbm_bte_i ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_dbg_sdram_dbus_bte}),
.wbm_dat_o ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_dbg_sdram_dbus_dat}),
.wbm_ack_o ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_dbg_sdram_dbus_ack}),
.wbm_err_o ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_dbg_sdram_dbus_err}),
.wbm_rty_o ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_dbg_sdram_dbus_rty}),
.wbs_adr_o (wb_sdram_dbus_adr_o),
.wbs_dat_o (wb_sdram_dbus_dat_o),
.wbs_sel_o (wb_sdram_dbus_sel_o),
.wbs_we_o (wb_sdram_dbus_we_o),
.wbs_cyc_o (wb_sdram_dbus_cyc_o),
.wbs_stb_o (wb_sdram_dbus_stb_o),
.wbs_cti_o (wb_sdram_dbus_cti_o),
.wbs_bte_o (wb_sdram_dbus_bte_o),
.wbs_dat_i (wb_sdram_dbus_dat_i),
.wbs_ack_i (wb_sdram_dbus_ack_i),
.wbs_err_i (wb_sdram_dbus_err_i),
.wbs_rty_i (wb_sdram_dbus_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_gpio0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_or1k_d_gpio0_adr, wb_m2s_dbg_gpio0_adr}),
.wbm_dat_i ({wb_m2s_or1k_d_gpio0_dat, wb_m2s_dbg_gpio0_dat}),
.wbm_sel_i ({wb_m2s_or1k_d_gpio0_sel, wb_m2s_dbg_gpio0_sel}),
.wbm_we_i ({wb_m2s_or1k_d_gpio0_we, wb_m2s_dbg_gpio0_we}),
.wbm_cyc_i ({wb_m2s_or1k_d_gpio0_cyc, wb_m2s_dbg_gpio0_cyc}),
.wbm_stb_i ({wb_m2s_or1k_d_gpio0_stb, wb_m2s_dbg_gpio0_stb}),
.wbm_cti_i ({wb_m2s_or1k_d_gpio0_cti, wb_m2s_dbg_gpio0_cti}),
.wbm_bte_i ({wb_m2s_or1k_d_gpio0_bte, wb_m2s_dbg_gpio0_bte}),
.wbm_dat_o ({wb_s2m_or1k_d_gpio0_dat, wb_s2m_dbg_gpio0_dat}),
.wbm_ack_o ({wb_s2m_or1k_d_gpio0_ack, wb_s2m_dbg_gpio0_ack}),
.wbm_err_o ({wb_s2m_or1k_d_gpio0_err, wb_s2m_dbg_gpio0_err}),
.wbm_rty_o ({wb_s2m_or1k_d_gpio0_rty, wb_s2m_dbg_gpio0_rty}),
.wbs_adr_o (wb_m2s_resize_gpio0_adr),
.wbs_dat_o (wb_m2s_resize_gpio0_dat),
.wbs_sel_o (wb_m2s_resize_gpio0_sel),
.wbs_we_o (wb_m2s_resize_gpio0_we),
.wbs_cyc_o (wb_m2s_resize_gpio0_cyc),
.wbs_stb_o (wb_m2s_resize_gpio0_stb),
.wbs_cti_o (wb_m2s_resize_gpio0_cti),
.wbs_bte_o (wb_m2s_resize_gpio0_bte),
.wbs_dat_i (wb_s2m_resize_gpio0_dat),
.wbs_ack_i (wb_s2m_resize_gpio0_ack),
.wbs_err_i (wb_s2m_resize_gpio0_err),
.wbs_rty_i (wb_s2m_resize_gpio0_rty));
wb_data_resize
#(.aw (32),
.mdw (32),
.sdw (8))
wb_data_resize_gpio0
(.wbm_adr_i (wb_m2s_resize_gpio0_adr),
.wbm_dat_i (wb_m2s_resize_gpio0_dat),
.wbm_sel_i (wb_m2s_resize_gpio0_sel),
.wbm_we_i (wb_m2s_resize_gpio0_we),
.wbm_cyc_i (wb_m2s_resize_gpio0_cyc),
.wbm_stb_i (wb_m2s_resize_gpio0_stb),
.wbm_cti_i (wb_m2s_resize_gpio0_cti),
.wbm_bte_i (wb_m2s_resize_gpio0_bte),
.wbm_dat_o (wb_s2m_resize_gpio0_dat),
.wbm_ack_o (wb_s2m_resize_gpio0_ack),
.wbm_err_o (wb_s2m_resize_gpio0_err),
.wbm_rty_o (wb_s2m_resize_gpio0_rty),
.wbs_adr_o (wb_gpio0_adr_o),
.wbs_dat_o (wb_gpio0_dat_o),
.wbs_we_o (wb_gpio0_we_o),
.wbs_cyc_o (wb_gpio0_cyc_o),
.wbs_stb_o (wb_gpio0_stb_o),
.wbs_cti_o (wb_gpio0_cti_o),
.wbs_bte_o (wb_gpio0_bte_o),
.wbs_dat_i (wb_gpio0_dat_i),
.wbs_ack_i (wb_gpio0_ack_i),
.wbs_err_i (wb_gpio0_err_i),
.wbs_rty_i (wb_gpio0_rty_i));
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_pm(
input [6:0] kc_I,
input [5:0] kf_I,
input [8:0] mod_I,
input add,
output reg [12:0] kcex
);
reg [9:0] lim;
reg [13:0] kcex0, kcex1;
reg [1:0] extra;
reg [6:0] kcin;
reg carry;
always @(*) begin: kc_input_cleaner
{ carry, kcin } = kc_I[1:0]==2'd3 ? { 1'b0, kc_I } + 8'd1 : {1'b0,kc_I};
end
always @(*) begin : addition
lim = { 1'd0, mod_I } + { 4'd0, kf_I };
case( kcin[3:0] )
default:
if( lim>=10'd448 ) extra = 2'd2;
else if( lim>=10'd256 ) extra = 2'd1;
else extra = 2'd0;
4'd1,4'd5,4'd9,4'd13:
if( lim>=10'd384 ) extra = 2'd2;
else if( lim>=10'd192 ) extra = 2'd1;
else extra = 2'd0;
4'd2,4'd6,4'd10,4'd14:
if( lim>=10'd512 ) extra = 2'd3;
else if( lim>=10'd320 ) extra = 2'd2;
else if( lim>=10'd128 ) extra = 2'd1;
else extra = 2'd0;
endcase
kcex0 = {1'b0,kcin,kf_I} + { 4'd0, extra, 6'd0 } + { 1'd0, mod_I };
kcex1 = kcex0[7:6]==2'd3 ? kcex0 + 14'd64 : kcex0;
end
reg signed [9:0] slim;
reg [1:0] sextra;
reg [13:0] skcex0, skcex1;
always @(*) begin : subtraction
slim = { 1'd0, mod_I } - { 4'd0, kf_I };
case( kcin[3:0] )
default:
if( slim>=10'sd449 ) sextra = 2'd3;
else if( slim>=10'sd257 ) sextra = 2'd2;
else if( slim>=10'sd65 ) sextra = 2'd1;
else sextra = 2'd0;
4'd1,4'd5,4'd9,4'd13:
if( slim>=10'sd321 ) sextra = 2'd2;
else if( slim>=10'sd129 ) sextra = 2'd1;
else sextra = 2'd0;
4'd2,4'd6,4'd10,4'd14:
if( slim>=10'sd385 ) sextra = 2'd2;
else if( slim>=10'sd193 ) sextra = 2'd1;
else sextra = 2'd0;
endcase
skcex0 = {1'b0,kcin,kf_I} - { 4'd0, sextra, 6'd0 } - { 1'd0, mod_I };
skcex1 = skcex0[7:6]==2'd3 ? skcex0 - 14'd64 : skcex0;
end
always @(*) begin : mux
if ( add )
kcex = kcex1[13] | carry ? {3'd7, 4'd14, 6'd63} : kcex1[12:0];
else
kcex = carry ? {3'd7, 4'd14, 6'd63} : (skcex1[13] ? 13'd0 : skcex1[12:0]);
end
endmodule
|
`define bsg_nor3_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_40_NR3D1BWP_b``bits nor3_gate (.i0(a_i),.i1(b_i),.i2(c_i),.o); \
end
module bsg_nor3 #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, input [width_p-1:0] c_i
, output [width_p-1:0] o
);
`bsg_nor3_macro(34) else
`bsg_nor3_macro(33) else
`bsg_nor3_macro(32) else
`bsg_nor3_macro(31) else
`bsg_nor3_macro(30) else
`bsg_nor3_macro(29) else
`bsg_nor3_macro(28) else
`bsg_nor3_macro(27) else
`bsg_nor3_macro(26) else
`bsg_nor3_macro(25) else
`bsg_nor3_macro(24) else
`bsg_nor3_macro(23) else
`bsg_nor3_macro(22) else
`bsg_nor3_macro(21) else
`bsg_nor3_macro(20) else
`bsg_nor3_macro(19) else
`bsg_nor3_macro(18) else
`bsg_nor3_macro(17) else
`bsg_nor3_macro(16) else
`bsg_nor3_macro(15) else
`bsg_nor3_macro(14) else
`bsg_nor3_macro(13) else
`bsg_nor3_macro(12) else
`bsg_nor3_macro(11) else
`bsg_nor3_macro(10) else
`bsg_nor3_macro(9) else
`bsg_nor3_macro(8) else
`bsg_nor3_macro(7) else
`bsg_nor3_macro(6) else
`bsg_nor3_macro(5) else
`bsg_nor3_macro(4) else
`bsg_nor3_macro(3) else
`bsg_nor3_macro(2) else
`bsg_nor3_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = ~(a_i | b_i | c_i);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nor3)
|
//******************************************************************************
// *
// Copyright (C) 2010 Regents of the University of California. *
// *
// The information contained herein is the exclusive property of the VCL *
// group but may be used and/or modified for non-comercial purposes if the *
// author is acknowledged. For all other uses, permission must be attained *
// by the VLSI Computation Lab. *
// *
// This work has been developed by members of the VLSI Computation Lab *
// (VCL) in the Department of Electrical and Computer Engineering at *
// the University of California at Davis. Contact: [email protected] *
//******************************************************************************
// FIFO.v
//
// 16-bit by 32, dual-clock circular FIFO for interfacing at clock boundaries
//
// $Id: FIFO.v,v 1.0 7/19/2010 02:15:36 astill Exp $
// Written by: Aaron Stillmaker
//
// Origional AsAP FIFO Written by: Ryan Apperson
// First In First Out circuitry:
// Main goal in rewriting was to have the whole FIFO in one file and not be
// AsAP specific. I started fresh writing most code from scratch using
// Ryan's thesis as a guide, some of code was used from his origional
// code, and some of the new code was modeled after the origional code.
//
// Define FIFO Address width minus 1 and Data word width minus 1
`define ADDR_WIDTH_M1 6
`define DATA_WIDTH_M1 15
`timescale 10ps/1ps
`celldefine
module FIFO (
reserve, // reserve space constant
wr_sync_cntrl, // Config input for wr side synchronizer
clk_wr, // clock coming from write side of FIFO -- write signals
data_in, // data to be written
wr_valid, // write side data is valid for writing to FIFO
delay_sel, // choose one/two delay cell for input data
wr_request, // low= Full or utilizing reserve space, else NOT FULL
async_empty, // true if empty, but referenced to write side
reset, // synchronous to read clock --------------------------
clk_rd, // clock coming from read side of FIFO -- read signals
data_out, // data to be read
empty, // FIFO is EMPTY (combinational in from 1st stage of FIFO)
rd_request, // asks the FIFO for data
async_full, // true if FIFO is in reserve, but referenced to read side
rd_sync_cntrl, // Config input for rd side synchronizer
nap, // no increment read pointer signal
fifo_util // FIFO utilization, used for DVFS
);
// I/O %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
input [1:0] delay_sel;
input [`DATA_WIDTH_M1:0] data_in;
input [`ADDR_WIDTH_M1:0] reserve;
input [2:0] wr_sync_cntrl;
input [2:0] rd_sync_cntrl;
input clk_wr,
clk_rd,
reset,
wr_valid,
rd_request,
nap;
output [`DATA_WIDTH_M1:0] data_out;
output [1:0] fifo_util;
output empty,
wr_request,
async_full,
async_empty;
// Internal Wires %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
wire [`ADDR_WIDTH_M1:0] temp_adder_out, // temporary address out
rd_ptr_on_wr,
wr_ptr_gray; // write pointer in gray code
wire [`DATA_WIDTH_M1:0] data_out_c; // data out from memory
wire wr_conv_temp1, // temporary wires used in gray
wr_conv_temp2, //to binary conversions
rd_conv_temp1,
rd_conv_temp2,
rd_en, // read inable flag
rd_inc; // read increment flag
// Internal Registers %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
reg [`ADDR_WIDTH_M1:0] wr_ptr, // write pointer
rd_ptr, // read pointer
rd_ptr_gray, // read pointer in gray code
wr_ptr_gray_d1, // delayed write ptr in gray code
wr_ptr_gray_d2,
rd_ptr_gray_d1, // delayed read ptr in gray code
rd_ptr_gray_d2,
rd_ptr_gray_on_wr,
wr_ptr_gray_on_rd,
wr_ptr_on_rd,
wr_Reg1, // registered pointers
wr_Reg2,
wr_Reg3,
wr_Reg4,
wr_RegS,
rd_Reg1,
rd_Reg2,
rd_Reg3,
rd_Reg4,
rd_RegS;
reg [`DATA_WIDTH_M1:0] data_out, // data output
data_in_d,
data_inREG1, // registered data in values
data_inREG2,
data_inREG3;
reg wr_hold_r, // delayed write hold value
wr_valid_d,
validREG1, // registered valid values
validREG2,
validREG3;
// Main %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Write Logic %%%
// Temporary wires used in the Gray Code to Binary Converter
assign wr_conv_temp1 = (rd_ptr_gray_on_wr[1]^rd_ptr_gray_on_wr[2]);
assign wr_conv_temp2 = (rd_ptr_gray_on_wr[1]^(~rd_ptr_gray_on_wr[2]));
// Reserve Logic Calculation, if the MSB is 1, hold.
//Accordingly assign the wr request output and async full
assign temp_adder_out = wr_ptr_on_rd - rd_ptr + {1'b0, reserve};
assign async_full = temp_adder_out[`ADDR_WIDTH_M1];
assign wr_request = ~wr_hold_r;
// Asynchronous Communication of RD address pointer from RD side to WR side
always @(wr_sync_cntrl or rd_ptr_gray_d2 or wr_Reg1 or wr_Reg2 or wr_Reg3 or
wr_Reg4) begin
case(wr_sync_cntrl)
3'b000: wr_RegS = rd_ptr_gray_d2;
3'b100: wr_RegS = wr_Reg1;
3'b101: wr_RegS = wr_Reg2;
3'b110: wr_RegS = wr_Reg3;
3'b111: wr_RegS = wr_Reg4;
default: wr_RegS = 7'bxxxxxxx;
endcase
end
always @(posedge clk_wr or posedge reset) begin
// Binary Incrementer %%
// Asynchronous Communication of RD address pointer from RD side to
//WR side %%
if (reset) begin //reset address FFs
wr_ptr <= 7'b0000000;
wr_ptr_gray_d1 <= #1 7'b0000000;
wr_ptr_gray_d2 <= #1 7'b0000000;
wr_hold_r <= #1 1'b0;
wr_Reg1 <= 7'b0000000;
wr_Reg2 <= 7'b0000000;
wr_Reg3 <= 7'b0000000;
wr_Reg4 <= 7'b0000000;
rd_ptr_gray_on_wr <= 7'b0000000;
// Insert delay to avoid the holdtime violation
case (delay_sel)
0: begin
wr_valid_d <= wr_valid;
data_in_d <= data_in;
end
1: begin
wr_valid_d <= validREG1;
data_in_d <= data_inREG1;
end
2: begin
wr_valid_d <= validREG2;
data_in_d <= data_inREG2;
end
3: begin
wr_valid_d <= validREG3;
data_in_d <= data_inREG3;
end
default: begin
wr_valid_d <= wr_valid;
data_in_d <= data_in;
end
endcase
end
else begin
wr_ptr <= #1 wr_ptr + wr_valid_d;
wr_ptr_gray_d1 <= #1 wr_ptr_gray;
wr_ptr_gray_d2 <= #1 wr_ptr_gray_d1;
wr_hold_r <= #1 async_full;
wr_Reg1 <= #1 rd_ptr_gray_d2;
wr_Reg2 <= #1 wr_Reg1;
wr_Reg3 <= #1 wr_Reg2;
wr_Reg4 <= #1 wr_Reg3;
validREG1 <= #1 wr_valid;
validREG2 <= #1 validREG1;
validREG3 <= #1 validREG2;
data_inREG1 <= #1 data_in;
data_inREG2 <= #1 data_inREG1;
data_inREG3 <= #1 data_inREG2;
rd_ptr_gray_on_wr <= wr_RegS;
// Insert delay to avoid the holdtime violation
case (delay_sel)
0: begin
wr_valid_d <= wr_valid;
data_in_d <= data_in;
end
1: begin
wr_valid_d <= validREG1;
data_in_d <= data_inREG1;
end
2: begin
wr_valid_d <= validREG2;
data_in_d <= data_inREG2;
end
3: begin
wr_valid_d <= validREG3;
data_in_d <= data_inREG3;
end
default: begin
wr_valid_d <= wr_valid;
data_in_d <= data_in;
end
endcase
end
end
// Binary to Gray Code Converter %%
assign wr_ptr_gray[0] = wr_ptr[0]^wr_ptr[1];
assign wr_ptr_gray[1] = wr_ptr[1]^wr_ptr[2];
assign wr_ptr_gray[2] = wr_ptr[2]^wr_ptr[3];
assign wr_ptr_gray[3] = wr_ptr[3]^wr_ptr[4];
assign wr_ptr_gray[4] = wr_ptr[4]^wr_ptr[5];
assign wr_ptr_gray[5] = wr_ptr[5]^wr_ptr[6];
assign wr_ptr_gray[6] = wr_ptr[6];
// Gray Code to Binary Converter %%
assign rd_ptr_on_wr[6] = rd_ptr_gray_on_wr[6];
assign rd_ptr_on_wr[5] = rd_ptr_gray_on_wr[5]^rd_ptr_gray_on_wr[6];
assign rd_ptr_on_wr[4] = rd_ptr_gray_on_wr[4]^rd_ptr_on_wr[5];
assign rd_ptr_on_wr[3] = rd_ptr_gray_on_wr[3]^rd_ptr_on_wr[4];
assign rd_ptr_on_wr[2] = rd_ptr_on_wr[3] ? ~rd_ptr_gray_on_wr[2] :
rd_ptr_gray_on_wr[2];
assign rd_ptr_on_wr[1] = rd_ptr_on_wr[3] ? wr_conv_temp2 : wr_conv_temp1;
assign rd_ptr_on_wr[0] = rd_ptr_on_wr[3] ? wr_conv_temp2^rd_ptr_gray_on_wr[0]
: wr_conv_temp1^rd_ptr_gray_on_wr[0];
// Read Logic %%%
// Temporary wires used in the Gray Code to Binary Converter
assign rd_conv_temp1 = (wr_ptr_gray_on_rd[1]^wr_ptr_gray_on_rd[2]);
assign rd_conv_temp2 = (wr_ptr_gray_on_rd[1]^(~wr_ptr_gray_on_rd[2]));
// Read Enable Logic
assign rd_en = ~empty & rd_request;
// Increment Enable Logic
assign rd_inc = rd_en & ~nap;
// Empty Logic, see if the next value for the read pointer would be empty
assign empty = (rd_ptr + 1 == wr_ptr_on_rd) & ~nap;
// Asynchronous Communication of WR address pointer from WR side to RD side
always @(rd_sync_cntrl or wr_ptr_gray_d2 or rd_Reg1 or rd_Reg2 or rd_Reg3 or
rd_Reg4) begin
case(rd_sync_cntrl)
3'b000: rd_RegS = wr_ptr_gray_d2;
3'b100: rd_RegS = rd_Reg1;
3'b101: rd_RegS = rd_Reg2;
3'b110: rd_RegS = rd_Reg3;
3'b111: rd_RegS = rd_Reg4;
default: rd_RegS = 7'bxxxxxxx;
endcase
end
always @(posedge clk_rd) begin
// Binary Incrementers %%
if (reset) begin
rd_ptr <= #1 7'b1111111;
wr_ptr_on_rd = 7'b0000000;
rd_ptr_gray <= #1 7'b0000000;
rd_ptr_gray_d1 <= #1 7'b0000000;
rd_ptr_gray_d2 <= #1 7'b0000000;
end else begin
rd_ptr <= #1 rd_ptr + rd_inc;
rd_ptr_gray_d1 <= #1 rd_ptr_gray;
rd_ptr_gray_d2 <= #1 rd_ptr_gray_d1;
end
// Binary to Gray Code Converter %%
rd_ptr_gray[0] <= rd_ptr[0]^rd_ptr[1];
rd_ptr_gray[1] <= rd_ptr[1]^rd_ptr[2];
rd_ptr_gray[2] <= rd_ptr[2]^rd_ptr[3];
rd_ptr_gray[3] <= rd_ptr[3]^rd_ptr[4];
rd_ptr_gray[4] <= rd_ptr[4]^rd_ptr[5];
rd_ptr_gray[5] <= rd_ptr[5]^rd_ptr[6];
rd_ptr_gray[6] <= rd_ptr[6];
// Asynchronous Communication of WR address ptr from WR side to RD side %%
if (reset) begin
rd_Reg1 <= 7'b0000000;
rd_Reg2 <= 7'b0000000;
rd_Reg3 <= 7'b0000000;
rd_Reg4 <= 7'b0000000;
wr_ptr_gray_on_rd <= 7'b0000000;
end else begin
rd_Reg1 <= #1 wr_ptr_gray_d2;
rd_Reg2 <= #1 rd_Reg1;
rd_Reg3 <= #1 rd_Reg2;
rd_Reg4 <= #1 rd_Reg3;
wr_ptr_gray_on_rd <= rd_RegS;
end
// Gray Code to Binary Converter %%
wr_ptr_on_rd[6] = wr_ptr_gray_on_rd[6];
wr_ptr_on_rd[5] = wr_ptr_gray_on_rd[5]^wr_ptr_gray_on_rd[6];
wr_ptr_on_rd[4] = wr_ptr_gray_on_rd[4]^wr_ptr_on_rd[5];
wr_ptr_on_rd[3] = wr_ptr_gray_on_rd[3]^wr_ptr_on_rd[4];
wr_ptr_on_rd[2] = wr_ptr_on_rd[3] ? ~wr_ptr_gray_on_rd[2] :
wr_ptr_gray_on_rd[2];
wr_ptr_on_rd[1] = wr_ptr_on_rd[3] ? rd_conv_temp2 : rd_conv_temp1;
wr_ptr_on_rd[0] = wr_ptr_on_rd[3] ? rd_conv_temp2^wr_ptr_gray_on_rd[0] :
rd_conv_temp1^wr_ptr_gray_on_rd[0];
// Register the SRAM output
data_out <= #1 data_out_c;
end
// Asychronous Empty Logic, used for asynchrnous wake
assign async_empty = (wr_ptr == rd_ptr_on_wr);
// FIFO utilization used by Dynamic Voltage and Frequency Scaling logic %%%
wire [6:0] fifo_util_temp;
assign fifo_util_temp = wr_ptr - rd_ptr - 1;
reg [1:0] fifo_util;
always @ ( fifo_util_temp )
begin
if( fifo_util_temp[6] == 1'b1 ) begin // util = 64
fifo_util = 2'b11;
end
else begin
fifo_util = fifo_util_temp[5:4]; // util = 0 to 63
end
end
//SRAM Memory Definition
SRAM SRAM (
.wr_en(wr_valid_d), // write enable
.clk_wr(clk_wr), // clock coming from write side of FIFO
.wr_ptr(wr_ptr), // write pointer
.data_in(data_in_d), // data to be written into the SRAM
.rd_en(rd_en), // read enable
.clk_rd(clk_rd), // clock coming from read side of FIFO
.rd_ptr(rd_ptr), // read pointer
.data_out(data_out_c) // data to be read from the SRAM
);
endmodule
`endcelldefine
`celldefine
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lights_switches (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
// megafunction wizard: %ALTMULT_ADD%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: sv_mult27.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_lnsim
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altmult_add ACCUM_SLOAD_REGISTER="UNREGISTERED" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="UNREGISTERED" ADDNSUB_MULTIPLIER_REGISTER1="CLOCK0" CBX_AUTO_BLACKBOX="ALL" COEF0_0=0 COEF0_1=0 COEF0_2=0 COEF0_3=0 COEF0_4=0 COEF0_5=0 COEF0_6=0 COEF0_7=0 COEF1_0=0 COEF1_1=0 COEF1_2=0 COEF1_3=0 COEF1_4=0 COEF1_5=0 COEF1_6=0 COEF1_7=0 COEF2_0=0 COEF2_1=0 COEF2_2=0 COEF2_3=0 COEF2_4=0 COEF2_5=0 COEF2_6=0 COEF2_7=0 COEF3_0=0 COEF3_1=0 COEF3_2=0 COEF3_3=0 COEF3_4=0 COEF3_5=0 COEF3_6=0 COEF3_7=0 COEFSEL0_REGISTER="UNREGISTERED" DEDICATED_MULTIPLIER_CIRCUITRY="AUTO" DEVICE_FAMILY="Stratix V" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_REGISTER_C0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" LOADCONST_VALUE=64 MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_REGISTER0="UNREGISTERED" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="CLOCK0" port_addnsub1="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" PREADDER_DIRECTION_0="ADD" PREADDER_DIRECTION_1="ADD" PREADDER_DIRECTION_2="ADD" PREADDER_DIRECTION_3="ADD" PREADDER_MODE="SIMPLE" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SIGNED_PIPELINE_REGISTER_A="UNREGISTERED" SIGNED_PIPELINE_REGISTER_B="UNREGISTERED" SIGNED_REGISTER_A="CLOCK0" SIGNED_REGISTER_B="CLOCK0" SYSTOLIC_DELAY1="UNREGISTERED" SYSTOLIC_DELAY3="UNREGISTERED" WIDTH_A=27 WIDTH_B=27 WIDTH_RESULT=54 clock0 dataa datab result
//VERSION_BEGIN 12.1 cbx_alt_ded_mult_y 2012:11:07:18:03:20:SJ cbx_altera_mult_add 2012:11:07:18:03:20:SJ cbx_altmult_add 2012:11:07:18:03:20:SJ cbx_cycloneii 2012:11:07:18:03:20:SJ cbx_lpm_add_sub 2012:11:07:18:03:20:SJ cbx_lpm_mult 2012:11:07:18:03:20:SJ cbx_mgl 2012:11:07:18:50:05:SJ cbx_padd 2012:11:07:18:03:20:SJ cbx_parallel_add 2012:11:07:18:03:20:SJ cbx_stratix 2012:11:07:18:03:20:SJ cbx_stratixii 2012:11:07:18:03:20:SJ cbx_util_mgl 2012:11:07:18:03:20:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = altera_mult_add 1 dsp_mac 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sv_mult27_mult_add_cfq3
(
clock0,
ena0,
dataa,
datab,
result) ;
parameter REPRESENTATION = "UNSIGNED";
input clock0;
input ena0;
input [26:0] dataa;
input [26:0] datab;
output [53:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [26:0] dataa;
tri0 [26:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [53:0] wire_altera_mult_add1_result;
wire ena1;
wire ena2;
wire ena3;
altera_mult_add altera_mult_add1
(
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.ena0(ena0),
.ena1(ena1),
.ena2(ena2),
.ena3(ena3),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add1_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr0(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({22{1'b0}}),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({27{1'b0}}),
.scaninb({27{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sourcea({1{1'b0}}),
.sourceb({1{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add1.accum_direction = "ADD",
altera_mult_add1.accum_sload_aclr = "ACLR0",
altera_mult_add1.accum_sload_pipeline_aclr = "ACLR0",
altera_mult_add1.accum_sload_pipeline_register = "CLOCK0",
altera_mult_add1.accum_sload_register = "UNREGISTERED",
altera_mult_add1.accumulator = "NO",
altera_mult_add1.adder1_rounding = "NO",
altera_mult_add1.adder3_rounding = "NO",
altera_mult_add1.addnsub1_round_aclr = "ACLR0",
altera_mult_add1.addnsub1_round_pipeline_aclr = "ACLR0",
altera_mult_add1.addnsub1_round_pipeline_register = "CLOCK0",
altera_mult_add1.addnsub1_round_register = "CLOCK0",
altera_mult_add1.addnsub3_round_aclr = "ACLR0",
altera_mult_add1.addnsub3_round_pipeline_aclr = "ACLR0",
altera_mult_add1.addnsub3_round_pipeline_register = "CLOCK0",
altera_mult_add1.addnsub3_round_register = "CLOCK0",
altera_mult_add1.addnsub_multiplier_aclr1 = "ACLR0",
altera_mult_add1.addnsub_multiplier_aclr3 = "ACLR0",
altera_mult_add1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
altera_mult_add1.addnsub_multiplier_pipeline_aclr3 = "ACLR0",
altera_mult_add1.addnsub_multiplier_pipeline_register1 = "UNREGISTERED",
altera_mult_add1.addnsub_multiplier_pipeline_register3 = "CLOCK0",
altera_mult_add1.addnsub_multiplier_register1 = "CLOCK0",
altera_mult_add1.addnsub_multiplier_register3 = "CLOCK0",
altera_mult_add1.chainout_aclr = "ACLR0",
altera_mult_add1.chainout_adder = "NO",
altera_mult_add1.chainout_register = "CLOCK0",
altera_mult_add1.chainout_round_aclr = "ACLR0",
altera_mult_add1.chainout_round_output_aclr = "ACLR0",
altera_mult_add1.chainout_round_output_register = "CLOCK0",
altera_mult_add1.chainout_round_pipeline_aclr = "ACLR0",
altera_mult_add1.chainout_round_pipeline_register = "CLOCK0",
altera_mult_add1.chainout_round_register = "CLOCK0",
altera_mult_add1.chainout_rounding = "NO",
altera_mult_add1.chainout_saturate_aclr = "ACLR0",
altera_mult_add1.chainout_saturate_output_aclr = "ACLR0",
altera_mult_add1.chainout_saturate_output_register = "CLOCK0",
altera_mult_add1.chainout_saturate_pipeline_aclr = "ACLR0",
altera_mult_add1.chainout_saturate_pipeline_register = "CLOCK0",
altera_mult_add1.chainout_saturate_register = "CLOCK0",
altera_mult_add1.chainout_saturation = "NO",
altera_mult_add1.coef0_0 = 0,
altera_mult_add1.coef0_1 = 0,
altera_mult_add1.coef0_2 = 0,
altera_mult_add1.coef0_3 = 0,
altera_mult_add1.coef0_4 = 0,
altera_mult_add1.coef0_5 = 0,
altera_mult_add1.coef0_6 = 0,
altera_mult_add1.coef0_7 = 0,
altera_mult_add1.coef1_0 = 0,
altera_mult_add1.coef1_1 = 0,
altera_mult_add1.coef1_2 = 0,
altera_mult_add1.coef1_3 = 0,
altera_mult_add1.coef1_4 = 0,
altera_mult_add1.coef1_5 = 0,
altera_mult_add1.coef1_6 = 0,
altera_mult_add1.coef1_7 = 0,
altera_mult_add1.coef2_0 = 0,
altera_mult_add1.coef2_1 = 0,
altera_mult_add1.coef2_2 = 0,
altera_mult_add1.coef2_3 = 0,
altera_mult_add1.coef2_4 = 0,
altera_mult_add1.coef2_5 = 0,
altera_mult_add1.coef2_6 = 0,
altera_mult_add1.coef2_7 = 0,
altera_mult_add1.coef3_0 = 0,
altera_mult_add1.coef3_1 = 0,
altera_mult_add1.coef3_2 = 0,
altera_mult_add1.coef3_3 = 0,
altera_mult_add1.coef3_4 = 0,
altera_mult_add1.coef3_5 = 0,
altera_mult_add1.coef3_6 = 0,
altera_mult_add1.coef3_7 = 0,
altera_mult_add1.coefsel0_aclr = "ACLR0",
altera_mult_add1.coefsel0_register = "UNREGISTERED",
altera_mult_add1.coefsel1_aclr = "ACLR0",
altera_mult_add1.coefsel1_register = "CLOCK0",
altera_mult_add1.coefsel2_aclr = "ACLR0",
altera_mult_add1.coefsel2_register = "CLOCK0",
altera_mult_add1.coefsel3_aclr = "ACLR0",
altera_mult_add1.coefsel3_register = "CLOCK0",
altera_mult_add1.dedicated_multiplier_circuitry = "AUTO",
altera_mult_add1.double_accum = "NO",
altera_mult_add1.dsp_block_balancing = "Auto",
altera_mult_add1.extra_latency = 0,
altera_mult_add1.input_aclr_a0 = "ACLR0",
altera_mult_add1.input_aclr_a1 = "ACLR0",
altera_mult_add1.input_aclr_a2 = "ACLR0",
altera_mult_add1.input_aclr_a3 = "ACLR0",
altera_mult_add1.input_aclr_b0 = "ACLR0",
altera_mult_add1.input_aclr_b1 = "ACLR0",
altera_mult_add1.input_aclr_b2 = "ACLR0",
altera_mult_add1.input_aclr_b3 = "ACLR0",
altera_mult_add1.input_aclr_c0 = "ACLR0",
altera_mult_add1.input_aclr_c1 = "ACLR0",
altera_mult_add1.input_aclr_c2 = "ACLR0",
altera_mult_add1.input_aclr_c3 = "ACLR0",
altera_mult_add1.input_register_a0 = "CLOCK0",
altera_mult_add1.input_register_a1 = "CLOCK0",
altera_mult_add1.input_register_a2 = "CLOCK0",
altera_mult_add1.input_register_a3 = "CLOCK0",
altera_mult_add1.input_register_b0 = "CLOCK0",
altera_mult_add1.input_register_b1 = "CLOCK0",
altera_mult_add1.input_register_b2 = "CLOCK0",
altera_mult_add1.input_register_b3 = "CLOCK0",
altera_mult_add1.input_register_c0 = "UNREGISTERED",
altera_mult_add1.input_register_c1 = "CLOCK0",
altera_mult_add1.input_register_c2 = "CLOCK0",
altera_mult_add1.input_register_c3 = "CLOCK0",
altera_mult_add1.input_source_a0 = "DATAA",
altera_mult_add1.input_source_a1 = "DATAA",
altera_mult_add1.input_source_a2 = "DATAA",
altera_mult_add1.input_source_a3 = "DATAA",
altera_mult_add1.input_source_b0 = "DATAB",
altera_mult_add1.input_source_b1 = "DATAB",
altera_mult_add1.input_source_b2 = "DATAB",
altera_mult_add1.input_source_b3 = "DATAB",
altera_mult_add1.loadconst_control_aclr = "ACLR0",
altera_mult_add1.loadconst_control_register = "CLOCK0",
altera_mult_add1.loadconst_value = 64,
altera_mult_add1.mult01_round_aclr = "ACLR0",
altera_mult_add1.mult01_round_register = "CLOCK0",
altera_mult_add1.mult01_saturation_aclr = "ACLR1",
altera_mult_add1.mult01_saturation_register = "CLOCK0",
altera_mult_add1.mult23_round_aclr = "ACLR0",
altera_mult_add1.mult23_round_register = "CLOCK0",
altera_mult_add1.mult23_saturation_aclr = "ACLR0",
altera_mult_add1.mult23_saturation_register = "CLOCK0",
altera_mult_add1.multiplier01_rounding = "NO",
altera_mult_add1.multiplier01_saturation = "NO",
altera_mult_add1.multiplier1_direction = "ADD",
altera_mult_add1.multiplier23_rounding = "NO",
altera_mult_add1.multiplier23_saturation = "NO",
altera_mult_add1.multiplier3_direction = "ADD",
altera_mult_add1.multiplier_aclr0 = "ACLR0",
altera_mult_add1.multiplier_aclr1 = "ACLR0",
altera_mult_add1.multiplier_aclr2 = "ACLR0",
altera_mult_add1.multiplier_aclr3 = "ACLR0",
altera_mult_add1.multiplier_register0 = "UNREGISTERED",
altera_mult_add1.multiplier_register1 = "CLOCK0",
altera_mult_add1.multiplier_register2 = "CLOCK0",
altera_mult_add1.multiplier_register3 = "CLOCK0",
altera_mult_add1.number_of_multipliers = 1,
altera_mult_add1.output_aclr = "ACLR0",
altera_mult_add1.output_register = "CLOCK0",
altera_mult_add1.output_round_aclr = "ACLR0",
altera_mult_add1.output_round_pipeline_aclr = "ACLR0",
altera_mult_add1.output_round_pipeline_register = "CLOCK0",
altera_mult_add1.output_round_register = "CLOCK0",
altera_mult_add1.output_round_type = "NEAREST_INTEGER",
altera_mult_add1.output_rounding = "NO",
altera_mult_add1.output_saturate_aclr = "ACLR0",
altera_mult_add1.output_saturate_pipeline_aclr = "ACLR0",
altera_mult_add1.output_saturate_pipeline_register = "CLOCK0",
altera_mult_add1.output_saturate_register = "CLOCK0",
altera_mult_add1.output_saturate_type = "ASYMMETRIC",
altera_mult_add1.output_saturation = "NO",
altera_mult_add1.port_addnsub1 = "PORT_UNUSED",
altera_mult_add1.port_addnsub3 = "PORT_UNUSED",
altera_mult_add1.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add1.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add1.port_signa = "PORT_UNUSED",
altera_mult_add1.port_signb = "PORT_UNUSED",
altera_mult_add1.preadder_direction_0 = "ADD",
altera_mult_add1.preadder_direction_1 = "ADD",
altera_mult_add1.preadder_direction_2 = "ADD",
altera_mult_add1.preadder_direction_3 = "ADD",
altera_mult_add1.preadder_mode = "SIMPLE",
altera_mult_add1.representation_a = REPRESENTATION,
altera_mult_add1.representation_b = REPRESENTATION,
altera_mult_add1.rotate_aclr = "ACLR0",
altera_mult_add1.rotate_output_aclr = "ACLR0",
altera_mult_add1.rotate_output_register = "CLOCK0",
altera_mult_add1.rotate_pipeline_aclr = "ACLR0",
altera_mult_add1.rotate_pipeline_register = "CLOCK0",
altera_mult_add1.rotate_register = "CLOCK0",
altera_mult_add1.scanouta_aclr = "ACLR0",
altera_mult_add1.scanouta_register = "UNREGISTERED",
altera_mult_add1.selected_device_family = "Stratix V",
altera_mult_add1.shift_mode = "NO",
altera_mult_add1.shift_right_aclr = "ACLR0",
altera_mult_add1.shift_right_output_aclr = "ACLR0",
altera_mult_add1.shift_right_output_register = "CLOCK0",
altera_mult_add1.shift_right_pipeline_aclr = "ACLR0",
altera_mult_add1.shift_right_pipeline_register = "CLOCK0",
altera_mult_add1.shift_right_register = "CLOCK0",
altera_mult_add1.signed_aclr_a = "ACLR0",
altera_mult_add1.signed_aclr_b = "ACLR0",
altera_mult_add1.signed_pipeline_aclr_a = "ACLR0",
altera_mult_add1.signed_pipeline_aclr_b = "ACLR0",
altera_mult_add1.signed_pipeline_register_a = "UNREGISTERED",
altera_mult_add1.signed_pipeline_register_b = "UNREGISTERED",
altera_mult_add1.signed_register_a = "CLOCK0",
altera_mult_add1.signed_register_b = "CLOCK0",
altera_mult_add1.systolic_aclr1 = "ACLR0",
altera_mult_add1.systolic_aclr3 = "ACLR0",
altera_mult_add1.systolic_delay1 = "UNREGISTERED",
altera_mult_add1.systolic_delay3 = "UNREGISTERED",
altera_mult_add1.width_a = 27,
altera_mult_add1.width_b = 27,
altera_mult_add1.width_c = 22,
altera_mult_add1.width_chainin = 1,
altera_mult_add1.width_coef = 18,
altera_mult_add1.width_msb = 17,
altera_mult_add1.width_result = 54,
altera_mult_add1.width_saturate_sign = 1,
altera_mult_add1.zero_chainout_output_aclr = "ACLR0",
altera_mult_add1.zero_chainout_output_register = "CLOCK0",
altera_mult_add1.zero_loopback_aclr = "ACLR0",
altera_mult_add1.zero_loopback_output_aclr = "ACLR0",
altera_mult_add1.zero_loopback_output_register = "CLOCK0",
altera_mult_add1.zero_loopback_pipeline_aclr = "ACLR0",
altera_mult_add1.zero_loopback_pipeline_register = "CLOCK0",
altera_mult_add1.zero_loopback_register = "CLOCK0",
altera_mult_add1.lpm_type = "altera_mult_add";
assign
ena1 = 1'b1,
ena2 = 1'b1,
ena3 = 1'b1,
result = wire_altera_mult_add1_result;
endmodule //sv_mult27_mult_add_cfq3
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sv_mult27 (
clock0,
ena0,
dataa_0,
datab_0,
result);
parameter REPRESENTATION = "UNSIGNED";
input clock0;
input ena0;
input [26:0] dataa_0;
input [26:0] datab_0;
output [53:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [26:0] dataa_0;
tri0 [26:0] datab_0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [53:0] sub_wire0;
wire [53:0] result = sub_wire0[53:0];
sv_mult27_mult_add_cfq3 sv_mult27_mult_add_cfq3_component (
.clock0 (clock0),
.ena0(ena0),
.dataa (dataa_0),
.datab (datab_0),
.result (sub_wire0));
defparam sv_mult27_mult_add_cfq3_component.REPRESENTATION = REPRESENTATION;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "2"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "0"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "0"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "2"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: C_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: C_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: ENABLE_PRELOAD_CONSTANT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: MULT_COEFSEL STRING "0"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGC NUMERIC "0"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "0"
// Retrieval info: PRIVATE: MULT_REG_ACCUM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: MULT_REG_SYSTOLIC_DELAY NUMERIC "0"
// Retrieval info: PRIVATE: NUM_MULT STRING "1"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "54"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "54"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SIGNA STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "0"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "0"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SYSTOLIC_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: SYSTOLIC_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: WIDTHA STRING "27"
// Retrieval info: PRIVATE: WIDTHB STRING "27"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUM_SLOAD_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: COEF0_0 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_1 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_2 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_3 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_4 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_5 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_6 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_7 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_0 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_1 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_2 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_3 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_4 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_5 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_6 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_7 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_0 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_1 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_2 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_3 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_4 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_5 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_6 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_7 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_0 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_1 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_2 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_3 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_4 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_5 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_6 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_7 NUMERIC "0"
// Retrieval info: CONSTANT: COEFSEL0_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_C0 STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LOADCONST_VALUE NUMERIC "64"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "UNREGISTERED"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "1"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PREADDER_DIRECTION_0 STRING "ADD"
// Retrieval info: CONSTANT: PREADDER_DIRECTION_1 STRING "ADD"
// Retrieval info: CONSTANT: PREADDER_DIRECTION_2 STRING "ADD"
// Retrieval info: CONSTANT: PREADDER_DIRECTION_3 STRING "ADD"
// Retrieval info: CONSTANT: PREADDER_MODE STRING "SIMPLE"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SYSTOLIC_DELAY1 STRING "UNREGISTERED"
// Retrieval info: CONSTANT: SYSTOLIC_DELAY3 STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "27"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "27"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "54"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 27 0 INPUT GND "dataa_0[26..0]"
// Retrieval info: USED_PORT: datab_0 0 0 27 0 INPUT GND "datab_0[26..0]"
// Retrieval info: USED_PORT: result 0 0 54 0 OUTPUT GND "result[53..0]"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 27 0 dataa_0 0 0 27 0
// Retrieval info: CONNECT: @datab 0 0 27 0 datab_0 0 0 27 0
// Retrieval info: CONNECT: result 0 0 54 0 @result 0 0 54 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27_bb.v TRUE
// Retrieval info: LIB_FILE: altera_lnsim
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main(
`ifdef MK2
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
output [22:0] ROM_ADDR,
output ROM_CE,
input MCU_OVR,
/* debug */
output p113_out,
`endif
`ifdef MK3
input SNES_CIC_CLK,
/* Bus 1: 2x PSRAM, 64Mbit, 16bit, 70ns */
output [21:0] ROM_ADDR,
output ROM_1CE,
output ROM_2CE,
output ROM_ZZ,
/* debug */
output PM6_out,
output PN6_out,
input PT5_in,
`endif
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA_IN,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
inout [15:0] ROM_DATA,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
input SPI_SCK,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK
);
wire CLK2;
wire [7:0] CX4_SNES_DATA_IN;
wire [7:0] CX4_SNES_DATA_OUT;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
wire [2:0] dac_vol_select_out;
wire [8:0] dac_ptr_addr;
wire [7:0] msu_volumerq_out;
wire [7:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [23:0] cx4_datrom_data;
wire [9:0] cx4_datrom_addr;
wire cx4_datrom_we;
wire [8:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
reg [7:0] SNES_PARDr = 8'b11111111;
reg [7:0] SNES_PAWRr = 8'b11111111;
reg [7:0] SNES_READr = 8'b11111111;
reg [7:0] SNES_WRITEr = 8'b11111111;
reg [7:0] SNES_CPU_CLKr = 8'b00000000;
reg [7:0] SNES_ROMSELr = 8'b11111111;
reg [23:0] SNES_ADDRr [6:0];
reg [7:0] SNES_PAr [6:0];
reg [7:0] SNES_DATAr [4:0];
reg[17:0] SNES_DEAD_CNTr = 18'h00000;
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
wire [23:0] SNES_ADDR = (SNES_ADDRr[5] & SNES_ADDRr[4]);
wire [7:0] SNES_PA = (SNES_PAr[5] & SNES_PAr[4]);
wire [7:0] SNES_DATA_IN = (SNES_DATAr[3] & SNES_DATAr[2]);
wire SNES_PARD_start = (SNES_PARDr[6:1] == 6'b111110);
// Sample PAWR data earlier on CPU accesses, later on DMA accesses...
wire SNES_PAWR_start = (SNES_PAWRr[7:1] == (({SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h02100) ? 7'b1110000 : 7'b1000000));
wire SNES_PAWR_end = (SNES_PAWRr[6:1] == 6'b000001);
wire SNES_RD_start = (SNES_READr[6:1] == 6'b111110);
wire SNES_RD_end = (SNES_READr[6:1] == 6'b000001);
wire SNES_WR_end = (SNES_WRITEr[6:1] == 6'b000001);
wire SNES_cycle_start = (SNES_CPU_CLKr[6:1] == 6'b000001);
wire SNES_cycle_end = (SNES_CPU_CLKr[6:1] == 6'b111110);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire SNES_PAWR = SNES_PAWRr[2] & SNES_PAWRr[1];
wire SNES_ROMSEL = (SNES_ROMSELr[5] & SNES_ROMSELr[4]);
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ) BUS_DATA <= SNES_DATA;
else if(~SNES_WRITE) BUS_DATA <= SNES_DATA_IN;
end
wire free_slot = SNES_cycle_end | free_strobe;
wire ROM_HIT;
assign DCM_RST=0;
always @(posedge CLK2) begin
free_strobe <= 1'b0;
if(SNES_cycle_start) free_strobe <= ~ROM_HIT;
end
always @(posedge CLK2) begin
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ROMSELr <= {SNES_ROMSELr[6:0], SNES_ROMSEL_IN};
SNES_ADDRr[6] <= SNES_ADDRr[5];
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
SNES_PAr[6] <= SNES_PAr[5];
SNES_PAr[5] <= SNES_PAr[4];
SNES_PAr[4] <= SNES_PAr[3];
SNES_PAr[3] <= SNES_PAr[2];
SNES_PAr[2] <= SNES_PAr[1];
SNES_PAr[1] <= SNES_PAr[0];
SNES_PAr[0] <= SNES_PA_IN;
SNES_DATAr[4] <= SNES_DATAr[3];
SNES_DATAr[3] <= SNES_DATAr[2];
SNES_DATAr[2] <= SNES_DATAr[1];
SNES_DATAr[1] <= SNES_DATAr[0];
SNES_DATAr[0] <= SNES_DATA;
end
parameter ST_IDLE = 7'b0000001;
parameter ST_MCU_RD_ADDR = 7'b0000010;
parameter ST_MCU_RD_END = 7'b0000100;
parameter ST_MCU_WR_ADDR = 7'b0001000;
parameter ST_MCU_WR_END = 7'b0010000;
parameter ST_CX4_RD_ADDR = 7'b0100000;
parameter ST_CX4_RD_END = 7'b1000000;
parameter ROM_CYCLE_LEN = 4'd6;
parameter SNES_DEAD_TIMEOUT = 17'd80000; // 1ms
reg [6:0] STATE;
initial STATE = ST_IDLE;
assign MSU_SNES_DATA_IN = BUS_DATA;
assign CX4_SNES_DATA_IN = BUS_DATA;
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK)
);
wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk_out(DAC_MCLK),
.lrck_out(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.vol_select(dac_vol_select_out),
.palmode(dac_palmode_out),
.play(dac_play),
.reset(dac_reset),
.dac_address_ext(dac_ptr_addr)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
reg [7:0] MCU_DINr;
wire [7:0] MCU_DOUT;
wire [15:0] featurebits;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
wire [15:0] dsp_feat;
wire [7:0] snescmd_data_in_mcu_dbg;
wire feat_cmd_unlock = featurebits[5];
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
// .dac_volume_out(dac_volume),
// .dac_volume_latch_out(dac_vol_latch),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.dac_vol_select_out(dac_vol_select_out),
.dac_palmode_out(dac_palmode_out),
.dac_ptr_out(dac_ptr_addr),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.featurebits_out(featurebits),
.cx4_reset_out(cx4_reset),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we),
.dsp_feat_out(dsp_feat)
);
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_PA(SNES_PA),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_HIT(ROM_HIT),
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
.featurebits(featurebits),
//MSU-1
.msu_enable(msu_enable),
//CX4
.cx4_enable(cx4_enable),
.cx4_vect_enable(cx4_vect_enable),
//region
.r213f_enable(r213f_enable),
//brightness fix
.r2100_hit(r2100_hit),
//CMD Interface
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable)
);
//always @(posedge CLK2) begin
// non_hit_cycle <= 1'b0;
// if(SNES_cycle_start) non_hit_cycle <= ~ROM_HIT;
//end
reg [7:0] CX4_DINr;
wire [23:0] CX4_ADDR;
wire [2:0] cx4_busy;
cx4 snes_cx4 (
.DI(CX4_SNES_DATA_IN),
.DO(CX4_SNES_DATA_OUT),
.ADDR(SNES_ADDR[12:0]),
.CS(cx4_enable),
.SNES_VECT_EN(cx4_vect_enable),
.reg_we_rising(SNES_WR_end),
.CLK(CLK2),
.BUS_DI(CX4_DINr),
.BUS_ADDR(CX4_ADDR),
.BUS_RRQ(CX4_RRQ),
.BUS_RDY(CX4_RDY),
.cx4_active(cx4_active),
.cx4_busy_out(cx4_busy),
.speed(dsp_feat[0])
);
reg pad_latch = 0;
reg [4:0] pad_cnt = 0;
reg snes_ajr = 0;
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.SNES_cycle_start(SNES_cycle_start),
.SNES_wr_strobe(SNES_WR_end),
.SNES_rd_strobe(SNES_RD_start),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.pad_latch(pad_latch),
.snes_ajr(snes_ajr),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock)
);
wire [7:0] snescmd_dout;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [1:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 0;
initial r213f_state = 2'b01;
initial r213f_delay = 3'b000;
reg [7:0] r2100r = 0;
reg r2100_forcewrite = 0;
reg r2100_forcewrite_pre = 0;
wire [3:0] r2100_limit = featurebits[10:7];
wire [3:0] r2100_limited = (SNES_DATA[3:0] > r2100_limit) ? r2100_limit : SNES_DATA[3:0];
wire r2100_patch = featurebits[6];
wire r2100_enable = r2100_hit & (r2100_patch | ~(&r2100_limit));
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
wire r4016_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04016;
always @(posedge CLK2) begin
r2100_forcewrite <= r2100_forcewrite_pre;
end
always @(posedge CLK2) begin
if(SNES_WR_end & snoop_4200_enable) begin
snes_ajr <= SNES_DATA[0];
end
end
always @(posedge CLK2) begin
if(SNES_WR_end & r4016_enable) begin
pad_latch <= 1'b1;
pad_cnt <= 5'h0;
end
if(SNES_RD_start & r4016_enable) begin
pad_cnt <= pad_cnt + 1;
if(&pad_cnt[3:0]) begin
pad_latch <= 1'b0;
end
end
end
assign SNES_DATA = (r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(r2100_enable & ~SNES_PAWR & r2100_forcewrite) ? r2100r
:((~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
& ~(r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE))
? (msu_enable ? MSU_SNES_DATA_OUT
:cx4_enable ? CX4_SNES_DATA_OUT
:(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
:(cheat_hit & ~feat_cmd_unlock) ? cheat_data_out
:(snescmd_unlock | feat_cmd_unlock) & snescmd_enable ? snescmd_dout
:(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])
): 8'bZ;
reg [4:0] ST_MEM_DELAYr;
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg CX4_RD_PENDr = 0;
reg [23:0] ROM_ADDRr;
reg [23:0] CX4_ADDRr;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
assign MCU_RDY = RQ_MCU_RDYr;
reg RQ_CX4_RDYr;
initial RQ_CX4_RDYr = 1'b1;
assign CX4_RDY = RQ_CX4_RDYr;
wire MCU_WE_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_WR_HIT = |(STATE & (ST_MCU_WR_ADDR | ST_MCU_WR_END));
wire MCU_RD_HIT = |(STATE & (ST_MCU_RD_ADDR | ST_MCU_RD_END));
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
wire CX4_HIT = |(STATE & ST_CX4_RD_ADDR);
`ifdef MK2
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST)
);
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : CX4_HIT ? CX4_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : MCU_HIT ? ROM_ADDRr[0] : CX4_HIT ? CX4_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_CE = 1'b0;
assign p113_out = 1'b0;
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable)), // input [0 : 0] wea
.addra(SNES_ADDR[8:0]), // input [8 : 0] addra
.dina(SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [8 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
`ifdef MK3
pll snes_pll(
.inclk0(CLKIN),
.c0(CLK2),
.locked(DCM_LOCKED),
.areset(DCM_RST)
);
wire ROM_ADDR22;
assign ROM_ADDR22 = (SD_DMA_TO_ROM) ? MCU_ADDR[1] : MCU_HIT ? ROM_ADDRr[1] : CX4_HIT ? CX4_ADDRr[1] : MAPPED_SNES_ADDR[1];
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:2] : MCU_HIT ? ROM_ADDRr[23:2] : CX4_HIT ? CX4_ADDRr[23:2] : MAPPED_SNES_ADDR[23:2];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : MCU_HIT ? ROM_ADDRr[0] : CX4_HIT ? CX4_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_ZZ = 1'b1;
assign ROM_1CE = ROM_ADDR22;
assign ROM_2CE = ~ROM_ADDR22;
snescmd_buf snescmd (
.clock(CLK2), // input clka
.wren_a(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable)), // input [0 : 0] wea
.address_a(SNES_ADDR[8:0]), // input [8 : 0] addra
.data_a(SNES_DATA), // input [7 : 0] dina
.q_a(snescmd_dout), // output [7 : 0] douta
.wren_b(snescmd_we_mcu), // input [0 : 0] web
.address_b(snescmd_addr_mcu), // input [8 : 0] addrb
.data_b(snescmd_data_out_mcu), // input [7 : 0] dinb
.q_b(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
always @(posedge CLK2) begin
if(cx4_active) begin
if(CX4_RRQ) begin
CX4_RD_PENDr <= 1'b1;
RQ_CX4_RDYr <= 1'b0;
CX4_ADDRr <= CX4_ADDR;
end else if(STATE == ST_CX4_RD_END) begin
CX4_RD_PENDr <= 1'b0;
RQ_CX4_RDYr <= 1'b1;
end
end
end
always @(posedge CLK2) begin
if(MCU_RRQ) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 17'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(cx4_active) begin
if (CX4_RD_PENDr) begin
STATE <= ST_CX4_RD_ADDR;
ST_MEM_DELAYr <= 16;
end
end else if(free_slot | SNES_DEADr) begin
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_MCU_RD_END, ST_MCU_WR_END: begin
STATE <= ST_IDLE;
end
ST_CX4_RD_ADDR: begin
STATE <= ST_CX4_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_CX4_RD_END;
CX4_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_CX4_RD_END: begin
STATE <= ST_IDLE;
end
endcase
end
always @(posedge CLK2) begin
if(SNES_cycle_end) r213f_forceread <= 1'b1;
else if(SNES_PARD_start & r213f_enable) begin
r213f_delay <= 3'b001;
r213f_state <= 2'b10;
end else if(r213f_state == 2'b10) begin
r213f_delay <= r213f_delay - 1;
if(r213f_delay == 3'b000) begin
r213f_forceread <= 1'b0;
r213f_state <= 2'b01;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
end
end
end
/*********************************
* R2100 patching (experimental) *
*********************************/
reg [3:0] r2100_bright = 0;
reg [3:0] r2100_bright_orig = 0;
always @(posedge CLK2) begin
if(SNES_cycle_end) r2100_forcewrite_pre <= 1'b0;
else if(SNES_PAWR_start & r2100_hit) begin
if(r2100_patch & SNES_DATA[7]) begin
// keep previous brightness during forced blanking so there is no DAC step
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b010, r2100_bright}; // 0xAx
end else if (r2100_patch && SNES_DATA == 8'h00 && r2100r[7]) begin
// extend forced blanking when game goes from blanking to brightness 0 (Star Fox top of screen)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {1'b1, 3'b111, r2100_bright}; // 0xFx
end else if (r2100_patch && SNES_DATA[3:0] < 4'h8 && r2100_bright_orig > 4'hd) begin
// substitute big brightness changes with brightness 0 (so it is visible on 1CHIP)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b011, 4'h0}; // 0x3x / 0xBx(!)
end else if (r2100_patch | ~(&r2100_limit)) begin
// save brightness, limit brightness
r2100_bright <= r2100_limited;
r2100_bright_orig <= SNES_DATA[3:0];
if (~(&r2100_limit) && SNES_DATA[3:0] > r2100_limit) begin
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b100, r2100_limited}; // 0x4x / 0xCx
end
end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) MCU_WRITE_1<= MCU_WRITE;
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
: (ROM_HIT & IS_WRITABLE & SNES_CPU_CLK) ? SNES_WRITE
: MCU_WE_HIT ? 1'b0
: 1'b1;
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
assign ROM_BHE = ROM_ADDR0;
assign ROM_BLE = ~ROM_ADDR0;
assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
cx4_enable ? 1'b0 :
(cx4_active & cx4_vect_enable) ? 1'b0 :
(r213f_enable & ~SNES_PARD) ? 1'b0 :
(r2100_enable & ~SNES_PAWR) ? 1'b0 :
snoop_4200_enable ? SNES_WRITE :
snescmd_enable ? (~(snescmd_unlock | feat_cmd_unlock) | (SNES_READ & SNES_WRITE)) :
((IS_ROM & SNES_ROMSEL)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
|(SNES_READ & SNES_WRITE)
);
/* data bus direction: 0 = SNES -> FPGA; 1 = FPGA -> SNES
* data bus is always SNES -> FPGA to avoid fighting except when:
* a) the SNES wants to read
* b) we want to force a value on the bus
*/
assign SNES_DATABUS_DIR = (~SNES_READ | (~SNES_PARD & (r213f_enable)))
? (1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
^ (r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE))
: ((~SNES_PAWR & r2100_enable) ? r2100_forcewrite
: 1'b0);
assign SNES_IRQ = 1'b0;
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: digilentinc.com:ip:pmod_bridge:1.0
// IP Revision: 6
(* X_CORE_INFO = "pmod_concat,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "PmodJSTK_pmod_bridge_0_0,pmod_concat,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PmodJSTK_pmod_bridge_0_0 (
in0_I,
in1_I,
in2_I,
in3_I,
in0_O,
in1_O,
in2_O,
in3_O,
in0_T,
in1_T,
in2_T,
in3_T,
out0_I,
out1_I,
out2_I,
out3_I,
out4_I,
out5_I,
out6_I,
out7_I,
out0_O,
out1_O,
out2_O,
out3_O,
out4_O,
out5_O,
out6_O,
out7_O,
out0_T,
out1_T,
out2_T,
out3_T,
out4_T,
out5_T,
out6_T,
out7_T
);
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_I" *)
output wire in0_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_I" *)
output wire in1_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_I" *)
output wire in2_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_I" *)
output wire in3_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_O" *)
input wire in0_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_O" *)
input wire in1_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_O" *)
input wire in2_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_O" *)
input wire in3_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_T" *)
input wire in0_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_T" *)
input wire in1_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_T" *)
input wire in2_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_T" *)
input wire in3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_I" *)
input wire out0_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_I" *)
input wire out1_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_I" *)
input wire out2_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_I" *)
input wire out3_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_I" *)
input wire out4_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_I" *)
input wire out5_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_I" *)
input wire out6_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_I" *)
input wire out7_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_O" *)
output wire out0_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_O" *)
output wire out1_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_O" *)
output wire out2_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_O" *)
output wire out3_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_O" *)
output wire out4_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_O" *)
output wire out5_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_O" *)
output wire out6_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_O" *)
output wire out7_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_T" *)
output wire out0_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_T" *)
output wire out1_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_T" *)
output wire out2_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_T" *)
output wire out3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_T" *)
output wire out4_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_T" *)
output wire out5_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_T" *)
output wire out6_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_T" *)
output wire out7_T;
pmod_concat #(
.Top_Row_Interface("SPI"),
.Bottom_Row_Interface("Disabled")
) inst (
.in_top_bus_I(),
.in_top_bus_O(4'B0),
.in_top_bus_T(4'B0),
.in_top_uart_gpio_bus_I(),
.in_top_uart_gpio_bus_O(2'B1),
.in_top_uart_gpio_bus_T(2'B1),
.in_top_i2c_gpio_bus_I(),
.in_top_i2c_gpio_bus_O(2'B1),
.in_top_i2c_gpio_bus_T(2'B1),
.in_bottom_bus_I(),
.in_bottom_bus_O(4'B1),
.in_bottom_bus_T(4'B1),
.in_bottom_uart_gpio_bus_I(),
.in_bottom_uart_gpio_bus_O(2'B1),
.in_bottom_uart_gpio_bus_T(2'B1),
.in_bottom_i2c_gpio_bus_I(),
.in_bottom_i2c_gpio_bus_O(2'B1),
.in_bottom_i2c_gpio_bus_T(2'B1),
.in0_I(in0_I),
.in1_I(in1_I),
.in2_I(in2_I),
.in3_I(in3_I),
.in4_I(),
.in5_I(),
.in6_I(),
.in7_I(),
.in0_O(in0_O),
.in1_O(in1_O),
.in2_O(in2_O),
.in3_O(in3_O),
.in4_O(1'B1),
.in5_O(1'B1),
.in6_O(1'B1),
.in7_O(1'B1),
.in0_T(in0_T),
.in1_T(in1_T),
.in2_T(in2_T),
.in3_T(in3_T),
.in4_T(1'B1),
.in5_T(1'B1),
.in6_T(1'B1),
.in7_T(1'B1),
.out0_I(out0_I),
.out1_I(out1_I),
.out2_I(out2_I),
.out3_I(out3_I),
.out4_I(out4_I),
.out5_I(out5_I),
.out6_I(out6_I),
.out7_I(out7_I),
.out0_O(out0_O),
.out1_O(out1_O),
.out2_O(out2_O),
.out3_O(out3_O),
.out4_O(out4_O),
.out5_O(out5_O),
.out6_O(out6_O),
.out7_O(out7_O),
.out0_T(out0_T),
.out1_T(out1_T),
.out2_T(out2_T),
.out3_T(out3_T),
.out4_T(out4_T),
.out5_T(out5_T),
.out6_T(out6_T),
.out7_T(out7_T)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PR_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DFF_PR_SYMBOL_V
/**
* udp_dff$PR: Positive edge triggered D flip-flop with active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$PR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PR_SYMBOL_V
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Set Implicit Arguments.
Require Export Notations.
Notation "A -> B" := (forall (_ : A), B) : type_scope.
(** * Propositional connectives *)
(** [True] is the always true proposition *)
Inductive True : Prop :=
I : True.
(** [False] is the always false proposition *)
Inductive False : Prop :=.
(** [not A], written [~A], is the negation of [A] *)
Definition not (A:Prop) := A -> False.
Notation "~ x" := (not x) : type_scope.
Hint Unfold not: core.
(** [and A B], written [A /\ B], is the conjunction of [A] and [B]
[conj p q] is a proof of [A /\ B] as soon as
[p] is a proof of [A] and [q] a proof of [B]
[proj1] and [proj2] are first and second projections of a conjunction *)
Inductive and (A B:Prop) : Prop :=
conj : A -> B -> A /\ B
where "A /\ B" := (and A B) : type_scope.
Section Conjunction.
Variables A B : Prop.
Theorem proj1 : A /\ B -> A.
Proof.
destruct 1; trivial.
Qed.
Theorem proj2 : A /\ B -> B.
Proof.
destruct 1; trivial.
Qed.
End Conjunction.
(** [or A B], written [A \/ B], is the disjunction of [A] and [B] *)
Inductive or (A B:Prop) : Prop :=
| or_introl : A -> A \/ B
| or_intror : B -> A \/ B
where "A \/ B" := (or A B) : type_scope.
Arguments or_introl [A B] _, [A] B _.
Arguments or_intror [A B] _, A [B] _.
(** [iff A B], written [A <-> B], expresses the equivalence of [A] and [B] *)
Definition iff (A B:Prop) := (A -> B) /\ (B -> A).
Notation "A <-> B" := (iff A B) : type_scope.
Section Equivalence.
Theorem iff_refl : forall A:Prop, A <-> A.
Proof.
split; auto.
Qed.
Theorem iff_trans : forall A B C:Prop, (A <-> B) -> (B <-> C) -> (A <-> C).
Proof.
intros A B C [H1 H2] [H3 H4]; split; auto.
Qed.
Theorem iff_sym : forall A B:Prop, (A <-> B) -> (B <-> A).
Proof.
intros A B [H1 H2]; split; auto.
Qed.
End Equivalence.
Hint Unfold iff: extcore.
(** Backward direction of the equivalences above does not need assumptions *)
Theorem and_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A /\ B <-> A /\ C).
Proof.
intros ? ? ? [Hl Hr]; split; intros [? ?]; (split; [ assumption | ]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem and_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B /\ A <-> C /\ A).
Proof.
intros ? ? ? [Hl Hr]; split; intros [? ?]; (split; [ | assumption ]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem or_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A \/ B <-> A \/ C).
Proof.
intros ? ? ? [Hl Hr]; split; (intros [?|?]; [left; assumption| right]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem or_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B \/ A <-> C \/ A).
Proof.
intros ? ? ? [Hl Hr]; split; (intros [?|?]; [left| right; assumption]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem imp_iff_compat_l : forall A B C : Prop,
(B <-> C) -> ((A -> B) <-> (A -> C)).
Proof.
intros ? ? ? [Hl Hr]; split; intros H ?; [apply Hl | apply Hr]; apply H; assumption.
Qed.
Theorem imp_iff_compat_r : forall A B C : Prop,
(B <-> C) -> ((B -> A) <-> (C -> A)).
Proof.
intros ? ? ? [Hl Hr]; split; intros H ?; [apply H, Hr | apply H, Hl]; assumption.
Qed.
Theorem not_iff_compat : forall A B : Prop,
(A <-> B) -> (~ A <-> ~B).
Proof.
intros; apply imp_iff_compat_r; assumption.
Qed.
(** Some equivalences *)
Theorem neg_false : forall A : Prop, ~ A <-> (A <-> False).
Proof.
intro A; unfold not; split.
- intro H; split; [exact H | intro H1; elim H1].
- intros [H _]; exact H.
Qed.
Theorem and_cancel_l : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((A /\ B <-> A /\ C) <-> (B <-> C)).
Proof.
intros A B C Hl Hr.
split; [ | apply and_iff_compat_l]; intros [HypL HypR]; split; intros.
+ apply HypL; split; [apply Hl | ]; assumption.
+ apply HypR; split; [apply Hr | ]; assumption.
Qed.
Theorem and_cancel_r : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((B /\ A <-> C /\ A) <-> (B <-> C)).
Proof.
intros A B C Hl Hr.
split; [ | apply and_iff_compat_r]; intros [HypL HypR]; split; intros.
+ apply HypL; split; [ | apply Hl ]; assumption.
+ apply HypR; split; [ | apply Hr ]; assumption.
Qed.
Theorem and_comm : forall A B : Prop, A /\ B <-> B /\ A.
Proof.
intros; split; intros [? ?]; split; assumption.
Qed.
Theorem and_assoc : forall A B C : Prop, (A /\ B) /\ C <-> A /\ B /\ C.
Proof.
intros; split; [ intros [[? ?] ?]| intros [? [? ?]]]; repeat split; assumption.
Qed.
Theorem or_cancel_l : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((A \/ B <-> A \/ C) <-> (B <-> C)).
Proof.
intros ? ? ? Fl Fr; split; [ | apply or_iff_compat_l]; intros [Hl Hr]; split; intros.
{ destruct Hl; [ right | destruct Fl | ]; assumption. }
{ destruct Hr; [ right | destruct Fr | ]; assumption. }
Qed.
Theorem or_cancel_r : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((B \/ A <-> C \/ A) <-> (B <-> C)).
Proof.
intros ? ? ? Fl Fr; split; [ | apply or_iff_compat_r]; intros [Hl Hr]; split; intros.
{ destruct Hl; [ left | | destruct Fl ]; assumption. }
{ destruct Hr; [ left | | destruct Fr ]; assumption. }
Qed.
Theorem or_comm : forall A B : Prop, (A \/ B) <-> (B \/ A).
Proof.
intros; split; (intros [? | ?]; [ right | left ]; assumption).
Qed.
Theorem or_assoc : forall A B C : Prop, (A \/ B) \/ C <-> A \/ B \/ C.
Proof.
intros; split; [ intros [[?|?]|?]| intros [?|[?|?]]].
+ left; assumption.
+ right; left; assumption.
+ right; right; assumption.
+ left; left; assumption.
+ left; right; assumption.
+ right; assumption.
Qed.
Lemma iff_and : forall A B : Prop, (A <-> B) -> (A -> B) /\ (B -> A).
Proof.
intros A B []; split; trivial.
Qed.
Lemma iff_to_and : forall A B : Prop, (A <-> B) <-> (A -> B) /\ (B -> A).
Proof.
intros; split; intros [Hl Hr]; (split; intros; [ apply Hl | apply Hr]); assumption.
Qed.
(** [(IF_then_else P Q R)], written [IF P then Q else R] denotes
either [P] and [Q], or [~P] and [R] *)
Definition IF_then_else (P Q R:Prop) := P /\ Q \/ ~ P /\ R.
Notation "'IF' c1 'then' c2 'else' c3" := (IF_then_else c1 c2 c3)
(at level 200, right associativity) : type_scope.
(** * First-order quantifiers *)
(** [ex P], or simply [exists x, P x], or also [exists x:A, P x],
expresses the existence of an [x] of some type [A] in [Set] which
satisfies the predicate [P]. This is existential quantification.
[ex2 P Q], or simply [exists2 x, P x & Q x], or also
[exists2 x:A, P x & Q x], expresses the existence of an [x] of
type [A] which satisfies both predicates [P] and [Q].
Universal quantification is primitively written [forall x:A, Q]. By
symmetry with existential quantification, the construction [all P]
is provided too.
*)
Inductive ex (A:Type) (P:A -> Prop) : Prop :=
ex_intro : forall x:A, P x -> ex (A:=A) P.
Inductive ex2 (A:Type) (P Q:A -> Prop) : Prop :=
ex_intro2 : forall x:A, P x -> Q x -> ex2 (A:=A) P Q.
Definition all (A:Type) (P:A -> Prop) := forall x:A, P x.
(* Rule order is important to give printing priority to fully typed exists *)
Notation "'exists' x .. y , p" := (ex (fun x => .. (ex (fun y => p)) ..))
(at level 200, x binder, right associativity,
format "'[' 'exists' '/ ' x .. y , '/ ' p ']'")
: type_scope.
Notation "'exists2' x , p & q" := (ex2 (fun x => p) (fun x => q))
(at level 200, x ident, p at level 200, right associativity) : type_scope.
Notation "'exists2' x : A , p & q" := (ex2 (A:=A) (fun x => p) (fun x => q))
(at level 200, x ident, A at level 200, p at level 200, right associativity,
format "'[' 'exists2' '/ ' x : A , '/ ' '[' p & '/' q ']' ']'")
: type_scope.
Notation "'exists2' ' x , p & q" := (ex2 (fun x => p) (fun x => q))
(at level 200, x strict pattern, p at level 200, right associativity) : type_scope.
Notation "'exists2' ' x : A , p & q" := (ex2 (A:=A) (fun x => p) (fun x => q))
(at level 200, x strict pattern, A at level 200, p at level 200, right associativity,
format "'[' 'exists2' '/ ' ' x : A , '/ ' '[' p & '/' q ']' ']'")
: type_scope.
(** Derived rules for universal quantification *)
Section universal_quantification.
Variable A : Type.
Variable P : A -> Prop.
Theorem inst : forall x:A, all (fun x => P x) -> P x.
Proof.
unfold all; auto.
Qed.
Theorem gen : forall (B:Prop) (f:forall y:A, B -> P y), B -> all P.
Proof.
red; auto.
Qed.
End universal_quantification.
(** * Equality *)
(** [eq x y], or simply [x=y] expresses the equality of [x] and
[y]. Both [x] and [y] must belong to the same type [A].
The definition is inductive and states the reflexivity of the equality.
The others properties (symmetry, transitivity, replacement of
equals by equals) are proved below. The type of [x] and [y] can be
made explicit using the notation [x = y :> A]. This is Leibniz equality
as it expresses that [x] and [y] are equal iff every property on
[A] which is true of [x] is also true of [y] *)
Inductive eq (A:Type) (x:A) : A -> Prop :=
eq_refl : x = x :>A
where "x = y :> A" := (@eq A x y) : type_scope.
Notation "x = y" := (x = y :>_) : type_scope.
Notation "x <> y :> T" := (~ x = y :>T) : type_scope.
Notation "x <> y" := (x <> y :>_) : type_scope.
Arguments eq {A} x _.
Arguments eq_refl {A x} , [A] x.
Arguments eq_ind [A] x P _ y _.
Arguments eq_rec [A] x P _ y _.
Arguments eq_rect [A] x P _ y _.
Hint Resolve I conj or_introl or_intror : core.
Hint Resolve eq_refl: core.
Hint Resolve ex_intro ex_intro2: core.
Section Logic_lemmas.
Theorem absurd : forall A C:Prop, A -> ~ A -> C.
Proof.
unfold not; intros A C h1 h2.
destruct (h2 h1).
Qed.
Section equality.
Variables A B : Type.
Variable f : A -> B.
Variables x y z : A.
Theorem eq_sym : x = y -> y = x.
Proof.
destruct 1; trivial.
Defined.
Theorem eq_trans : x = y -> y = z -> x = z.
Proof.
destruct 2; trivial.
Defined.
Theorem f_equal : x = y -> f x = f y.
Proof.
destruct 1; trivial.
Defined.
Theorem not_eq_sym : x <> y -> y <> x.
Proof.
red; intros h1 h2; apply h1; destruct h2; trivial.
Qed.
End equality.
Definition eq_ind_r :
forall (A:Type) (x:A) (P:A -> Prop), P x -> forall y:A, y = x -> P y.
intros A x P H y H0. elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rec_r :
forall (A:Type) (x:A) (P:A -> Set), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rect_r :
forall (A:Type) (x:A) (P:A -> Type), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
End Logic_lemmas.
Module EqNotations.
Notation "'rew' H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10,
format "'[' 'rew' H in '/' H' ']'").
Notation "'rew' [ P ] H 'in' H'" := (eq_rect _ P H' _ H)
(at level 10, H' at level 10,
format "'[' 'rew' [ P ] '/ ' H in '/' H' ']'").
Notation "'rew' <- H 'in' H'" := (eq_rect_r _ H' H)
(at level 10, H' at level 10,
format "'[' 'rew' <- H in '/' H' ']'").
Notation "'rew' <- [ P ] H 'in' H'" := (eq_rect_r P H' H)
(at level 10, H' at level 10,
format "'[' 'rew' <- [ P ] '/ ' H in '/' H' ']'").
Notation "'rew' -> H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10, only parsing).
Notation "'rew' -> [ P ] H 'in' H'" := (eq_rect _ P H' _ H)
(at level 10, H' at level 10, only parsing).
End EqNotations.
Import EqNotations.
Lemma rew_opp_r : forall A (P:A->Type) (x y:A) (H:x=y) (a:P y), rew H in rew <- H in a = a.
Proof.
intros.
destruct H.
reflexivity.
Defined.
Lemma rew_opp_l : forall A (P:A->Type) (x y:A) (H:x=y) (a:P x), rew <- H in rew H in a = a.
Proof.
intros.
destruct H.
reflexivity.
Defined.
Theorem f_equal2 :
forall (A1 A2 B:Type) (f:A1 -> A2 -> B) (x1 y1:A1)
(x2 y2:A2), x1 = y1 -> x2 = y2 -> f x1 x2 = f y1 y2.
Proof.
destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal3 :
forall (A1 A2 A3 B:Type) (f:A1 -> A2 -> A3 -> B) (x1 y1:A1)
(x2 y2:A2) (x3 y3:A3),
x1 = y1 -> x2 = y2 -> x3 = y3 -> f x1 x2 x3 = f y1 y2 y3.
Proof.
destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal4 :
forall (A1 A2 A3 A4 B:Type) (f:A1 -> A2 -> A3 -> A4 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4),
x1 = y1 -> x2 = y2 -> x3 = y3 -> x4 = y4 -> f x1 x2 x3 x4 = f y1 y2 y3 y4.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal5 :
forall (A1 A2 A3 A4 A5 B:Type) (f:A1 -> A2 -> A3 -> A4 -> A5 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4) (x5 y5:A5),
x1 = y1 ->
x2 = y2 ->
x3 = y3 -> x4 = y4 -> x5 = y5 -> f x1 x2 x3 x4 x5 = f y1 y2 y3 y4 y5.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal_compose : forall A B C (a b:A) (f:A->B) (g:B->C) (e:a=b),
f_equal g (f_equal f e) = f_equal (fun a => g (f a)) e.
Proof.
destruct e. reflexivity.
Defined.
(** The goupoid structure of equality *)
Theorem eq_trans_refl_l : forall A (x y:A) (e:x=y), eq_trans eq_refl e = e.
Proof.
destruct e. reflexivity.
Defined.
Theorem eq_trans_refl_r : forall A (x y:A) (e:x=y), eq_trans e eq_refl = e.
Proof.
destruct e. reflexivity.
Defined.
Theorem eq_sym_involutive : forall A (x y:A) (e:x=y), eq_sym (eq_sym e) = e.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_sym_inv_l : forall A (x y:A) (e:x=y), eq_trans (eq_sym e) e = eq_refl.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_sym_inv_r : forall A (x y:A) (e:x=y), eq_trans e (eq_sym e) = eq_refl.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_assoc : forall A (x y z t:A) (e:x=y) (e':y=z) (e'':z=t),
eq_trans e (eq_trans e' e'') = eq_trans (eq_trans e e') e''.
Proof.
destruct e''; reflexivity.
Defined.
(** Extra properties of equality *)
Theorem eq_id_comm_l : forall A (f:A->A) (Hf:forall a, a = f a), forall a, f_equal f (Hf a) = Hf (f a).
Proof.
intros.
unfold f_equal.
rewrite <- (eq_trans_sym_inv_l (Hf a)).
destruct (Hf a) at 1 2.
destruct (Hf a).
reflexivity.
Defined.
Theorem eq_id_comm_r : forall A (f:A->A) (Hf:forall a, f a = a), forall a, f_equal f (Hf a) = Hf (f a).
Proof.
intros.
unfold f_equal.
rewrite <- (eq_trans_sym_inv_l (Hf (f (f a)))).
set (Hfsymf := fun a => eq_sym (Hf a)).
change (eq_sym (Hf (f (f a)))) with (Hfsymf (f (f a))).
pattern (Hfsymf (f (f a))).
destruct (eq_id_comm_l f Hfsymf (f a)).
destruct (eq_id_comm_l f Hfsymf a).
unfold Hfsymf.
destruct (Hf a). simpl.
rewrite eq_trans_refl_l.
reflexivity.
Defined.
Lemma eq_refl_map_distr : forall A B x (f:A->B), f_equal f (eq_refl x) = eq_refl (f x).
Proof.
reflexivity.
Qed.
Lemma eq_trans_map_distr : forall A B x y z (f:A->B) (e:x=y) (e':y=z), f_equal f (eq_trans e e') = eq_trans (f_equal f e) (f_equal f e').
Proof.
destruct e'.
reflexivity.
Defined.
Lemma eq_sym_map_distr : forall A B (x y:A) (f:A->B) (e:x=y), eq_sym (f_equal f e) = f_equal f (eq_sym e).
Proof.
destruct e.
reflexivity.
Defined.
Lemma eq_trans_sym_distr : forall A (x y z:A) (e:x=y) (e':y=z), eq_sym (eq_trans e e') = eq_trans (eq_sym e') (eq_sym e).
Proof.
destruct e, e'.
reflexivity.
Defined.
Lemma eq_trans_rew_distr : forall A (P:A -> Type) (x y z:A) (e:x=y) (e':y=z) (k:P x),
rew (eq_trans e e') in k = rew e' in rew e in k.
Proof.
destruct e, e'; reflexivity.
Qed.
Lemma rew_const : forall A P (x y:A) (e:x=y) (k:P),
rew [fun _ => P] e in k = k.
Proof.
destruct e; reflexivity.
Qed.
(* Aliases *)
Notation sym_eq := eq_sym (only parsing).
Notation trans_eq := eq_trans (only parsing).
Notation sym_not_eq := not_eq_sym (only parsing).
Notation refl_equal := eq_refl (only parsing).
Notation sym_equal := eq_sym (only parsing).
Notation trans_equal := eq_trans (only parsing).
Notation sym_not_equal := not_eq_sym (only parsing).
Hint Immediate eq_sym not_eq_sym: core.
(** Basic definitions about relations and properties *)
Definition subrelation (A B : Type) (R R' : A->B->Prop) :=
forall x y, R x y -> R' x y.
Definition unique (A : Type) (P : A->Prop) (x:A) :=
P x /\ forall (x':A), P x' -> x=x'.
Definition uniqueness (A:Type) (P:A->Prop) := forall x y, P x -> P y -> x = y.
(** Unique existence *)
Notation "'exists' ! x .. y , p" :=
(ex (unique (fun x => .. (ex (unique (fun y => p))) ..)))
(at level 200, x binder, right associativity,
format "'[' 'exists' ! '/ ' x .. y , '/ ' p ']'")
: type_scope.
Lemma unique_existence : forall (A:Type) (P:A->Prop),
((exists x, P x) /\ uniqueness P) <-> (exists! x, P x).
Proof.
intros A P; split.
- intros ((x,Hx),Huni); exists x; red; auto.
- intros (x,(Hx,Huni)); split.
+ exists x; assumption.
+ intros x' x'' Hx' Hx''; transitivity x.
symmetry; auto.
auto.
Qed.
Lemma forall_exists_unique_domain_coincide :
forall A (P:A->Prop), (exists! x, P x) ->
forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x).
Proof.
intros A P (x & Hp & Huniq); split.
- intro; exists x; auto.
- intros (x0 & HPx0 & HQx0) x1 HPx1.
assert (H : x0 = x1) by (transitivity x; [symmetry|]; auto).
destruct H.
assumption.
Qed.
Lemma forall_exists_coincide_unique_domain :
forall A (P:A->Prop),
(forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x))
-> (exists! x, P x).
Proof.
intros A P H.
destruct H with (Q:=P) as ((x & Hx & _),_); [trivial|].
exists x. split; [trivial|].
destruct H with (Q:=fun x'=>x=x') as (_,Huniq).
apply Huniq. exists x; auto.
Qed.
(** * Being inhabited *)
(** The predicate [inhabited] can be used in different contexts. If [A] is
thought as a type, [inhabited A] states that [A] is inhabited. If [A] is
thought as a computationally relevant proposition, then
[inhabited A] weakens [A] so as to hide its computational meaning.
The so-weakened proof remains computationally relevant but only in
a propositional context.
*)
Inductive inhabited (A:Type) : Prop := inhabits : A -> inhabited A.
Hint Resolve inhabits: core.
Lemma exists_inhabited : forall (A:Type) (P:A->Prop),
(exists x, P x) -> inhabited A.
Proof.
destruct 1; auto.
Qed.
Lemma inhabited_covariant (A B : Type) : (A -> B) -> inhabited A -> inhabited B.
Proof.
intros f [x];exact (inhabits (f x)).
Qed.
(** Declaration of stepl and stepr for eq and iff *)
Lemma eq_stepl : forall (A : Type) (x y z : A), x = y -> x = z -> z = y.
Proof.
intros A x y z H1 H2. rewrite <- H2; exact H1.
Qed.
Declare Left Step eq_stepl.
Declare Right Step eq_trans.
Lemma iff_stepl : forall A B C : Prop, (A <-> B) -> (A <-> C) -> (C <-> B).
Proof.
intros ? ? ? [? ?] [? ?]; split; intros; auto.
Qed.
Declare Left Step iff_stepl.
Declare Right Step iff_trans.
Local Notation "'rew' 'dependent' H 'in' H'"
:= (match H with
| eq_refl => H'
end)
(at level 10, H' at level 10,
format "'[' 'rew' 'dependent' '/ ' H in '/' H' ']'").
(** Equality for [ex] *)
Section ex.
Local Unset Implicit Arguments.
Definition eq_ex_uncurried {A : Type} (P : A -> Prop) {u1 v1 : A} {u2 : P u1} {v2 : P v1}
(pq : exists p : u1 = v1, rew p in u2 = v2)
: ex_intro P u1 u2 = ex_intro P v1 v2.
Proof.
destruct pq as [p q].
destruct q; simpl in *.
destruct p; reflexivity.
Qed.
Definition eq_ex {A : Type} {P : A -> Prop} (u1 v1 : A) (u2 : P u1) (v2 : P v1)
(p : u1 = v1) (q : rew p in u2 = v2)
: ex_intro P u1 u2 = ex_intro P v1 v2
:= eq_ex_uncurried P (ex_intro _ p q).
Definition eq_ex_hprop {A} {P : A -> Prop} (P_hprop : forall (x : A) (p q : P x), p = q)
(u1 v1 : A) (u2 : P u1) (v2 : P v1)
(p : u1 = v1)
: ex_intro P u1 u2 = ex_intro P v1 v2
:= eq_ex u1 v1 u2 v2 p (P_hprop _ _ _).
Lemma rew_ex {A x} {P : A -> Type} (Q : forall a, P a -> Prop) (u : exists p, Q x p) {y} (H : x = y)
: rew [fun a => exists p, Q a p] H in u
= match u with
| ex_intro _ u1 u2
=> ex_intro
(Q y)
(rew H in u1)
(rew dependent H in u2)
end.
Proof.
destruct H, u; reflexivity.
Qed.
End ex.
(** Equality for [ex2] *)
Section ex2.
Local Unset Implicit Arguments.
Definition eq_ex2_uncurried {A : Type} (P Q : A -> Prop) {u1 v1 : A}
{u2 : P u1} {v2 : P v1}
{u3 : Q u1} {v3 : Q v1}
(pq : exists2 p : u1 = v1, rew p in u2 = v2 & rew p in u3 = v3)
: ex_intro2 P Q u1 u2 u3 = ex_intro2 P Q v1 v2 v3.
Proof.
destruct pq as [p q r].
destruct r, q, p; simpl in *.
reflexivity.
Qed.
Definition eq_ex2 {A : Type} {P Q : A -> Prop}
(u1 v1 : A)
(u2 : P u1) (v2 : P v1)
(u3 : Q u1) (v3 : Q v1)
(p : u1 = v1) (q : rew p in u2 = v2) (r : rew p in u3 = v3)
: ex_intro2 P Q u1 u2 u3 = ex_intro2 P Q v1 v2 v3
:= eq_ex2_uncurried P Q (ex_intro2 _ _ p q r).
Definition eq_ex2_hprop {A} {P Q : A -> Prop}
(P_hprop : forall (x : A) (p q : P x), p = q)
(Q_hprop : forall (x : A) (p q : Q x), p = q)
(u1 v1 : A) (u2 : P u1) (v2 : P v1) (u3 : Q u1) (v3 : Q v1)
(p : u1 = v1)
: ex_intro2 P Q u1 u2 u3 = ex_intro2 P Q v1 v2 v3
:= eq_ex2 u1 v1 u2 v2 u3 v3 p (P_hprop _ _ _) (Q_hprop _ _ _).
Lemma rew_ex2 {A x} {P : A -> Type}
(Q : forall a, P a -> Prop)
(R : forall a, P a -> Prop)
(u : exists2 p, Q x p & R x p) {y} (H : x = y)
: rew [fun a => exists2 p, Q a p & R a p] H in u
= match u with
| ex_intro2 _ _ u1 u2 u3
=> ex_intro2
(Q y)
(R y)
(rew H in u1)
(rew dependent H in u2)
(rew dependent H in u3)
end.
Proof.
destruct H, u; reflexivity.
Qed.
End ex2.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_M_V
`define SKY130_FD_SC_LP__OR4_M_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_m (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_m (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_M_V
|
// Copyright (c) 2013, Simon Que
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
`timescale 1ns/1ps
`define BYTE_WIDTH 8 // Number of bits per byte.
module SPIBusTest;
// Main SPI interface.
reg main_nss, main_sck, main_mosi;
wire main_miso;
// Secondary SPI interface.
reg alt_nss, alt_sck, alt_mosi;
wire alt_miso;
// SPI memory bus interface.
wire mem_nss, mem_sck, mem_mosi;
reg mem_miso;
// Instantiate the Unit Under Test (UUT).
SPIBus spi_bus(main_nss, main_sck, main_mosi, main_miso,
alt_nss, alt_sck, alt_mosi, alt_miso,
mem_nss, mem_sck, mem_mosi, mem_miso);
integer stage; // Keeps track of test progress.
// Generate contents of |mem_miso| as the inverse of |mem_mosi|.
always @ (*)
mem_miso <= ~mem_mosi;
initial begin
main_nss = 0;
main_sck = 0;
main_mosi = 0;
alt_nss = 1;
alt_sck = 0;
alt_mosi = 0;
stage = 0;
#1 main_nss = 1;
#10
stage = 1;
// Perform some memory bus accesses.
#10
main_nss = 0;
main_spi_transmit(8'h01);
main_spi_transmit(8'h02);
main_spi_transmit(8'h04);
main_spi_transmit(8'h08);
main_nss = 1;
// Attempt a secondary SPI access, should go through.
#10
alt_nss = 0;
alt_spi_transmit(8'h11);
alt_spi_transmit(8'h22);
alt_spi_transmit(8'h44);
alt_spi_transmit(8'h88);
alt_nss = 1;
#10
stage = 2;
// Assert the main bus and the secondary bus at the same time. Neither
// should have nSS access, but the main bus should have SCK and MISO access.
#10
main_nss = 0;
alt_nss = 0;
main_spi_transmit(8'h01);
main_spi_transmit(8'h02);
main_spi_transmit(8'h04);
main_spi_transmit(8'h08);
alt_spi_transmit(8'h11);
alt_spi_transmit(8'h22);
alt_spi_transmit(8'h44);
alt_spi_transmit(8'h88);
main_nss = 1;
alt_nss = 1;
#10
stage = 3;
end
// Task to send a byte over primary SPI bus.
task main_spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
main_sck = 0;
#2
main_sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
main_mosi = data[`BYTE_WIDTH - 1 - i];
#1
main_sck = 1;
#1
main_sck = 0;
end
#2
main_sck = 0;
main_mosi = 0;
end
endtask
// Task to send a byte over secondary SPI bus.
task alt_spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
alt_sck = 0;
#2
alt_sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
alt_mosi = data[`BYTE_WIDTH - 1 - i];
#1
alt_sck = 1;
#1
alt_sck = 0;
end
#2
alt_sck = 0;
alt_mosi = 0;
end
endtask
endmodule
|
`timescale 1ns / 1ps
module fifo_test();
parameter WIDTH = 8;
parameter DEPTH = 12;
`include "dut.v"
integer i;
reg [WIDTH-1:0] tempdata;
reg tempstart;
reg tempend;
initial
begin
#15 reset = 0;
fork
data_in.sync_write(8'hAA);
data_in_start.sync_write(1);
join
for ( i = 1; i < 100; i = i + 1)
begin
data_in.sync_write(i);
end
fork
data_in.sync_write(8'hAB);
data_in_end.sync_write(1);
join
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == 8'hAA, "Reading FIFO Data");
util.assert(tempstart == 1, "Reading FIFO Start");
util.assert(tempend == 0, "Reading FIFO End");
for ( i = 1; i < 100; i = i + 1)
begin
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == i, "Reading FIFO Data");
util.assert(tempstart == 0, "Reading FIFO Start");
util.assert(tempend == 0, "Reading FIFO End");
end
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == 8'hAB, "Reading FIFO Data");
util.assert(tempstart == 0, "Reading FIFO Start");
util.assert(tempend == 1, "Reading FIFO End");
$finish;
end
endmodule
|
// N64 controller read command parser/receiver
//
// Inputs: clk_4M 4 MHz clock
// din Input data line
// enable Only samples when this is active
// Outputs: ctrl_state 32-bit register with controller state
// ctrl_clk Output clock, sample at negative edge
module n64_readcmd_rx(input wire clk_4M,
input wire din,
input wire enable,
output reg [31:0] ctrl_state,
output wire ctrl_clk);
// In sample window, we can read the value of the
// last 8 samples of the input signal.
// Sampling frequency is 4 MHz
wire [6:0] sampling_window;
shiftM #(.M(7), .INI(7'b1111111))
shift_sampling_reg (
.clk(clk_4M),
.enable(enable),
.serin(din),
.data(sampling_window)
);
// When we detect a falling edge at the oldest bit of
// the sampling window, we already have our desired
// bit at the newest position
wire [32:0] ctrl_state_dirty;
shiftM #(.M(33), .INI(33'b0))
shift_controller_state_reg (
.clk(~sampling_window[6]),
.enable(enable),
.serin(sampling_window[0]),
.data(ctrl_state_dirty)
);
// We need to update our 'ctrl_state' from 'ctrl_state_dirty'
// at the right time, that is, when we finish reading
// all of the 32 bits.
wire output_en;
counterM #(.M(32))
counter_signal_complete (
.clk(~sampling_window[6]),
.reset(ctrl_clk),
.empty(ctrl_clk)
);
initial ctrl_state = 32'b0;
always @(posedge ctrl_clk)
ctrl_state <= ctrl_state_dirty[32:1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_4_V
`define SKY130_FD_SC_LP__NOR3_4_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3_4 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3_4 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFRTN_BLACKBOX_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_BLACKBOX_V
|
/* Title: seven_seg_decoder.v
* Author: Sergiy Kolodyazhnyy <[email protected]>
* Date: March 9, 2017
* Purpose: Data-flow code for simple binary to hex display driver
* Developed on: Ubuntu 16.04 LTS , Quartus Prime Lite 16.1
* Tested on: DE1-SoC , Cyclone V , 5CSEMA5F31
*/
module seven_seg_decoder(led_out,bin_in);
output [6:0] led_out;
input [3:0] bin_in;
wire [3:0] bin_in_inv;
assign bin_in_inv = ~bin_in;
/* A => bin_in[3]
* B => bin_in[2]
* C => bin_in[1]
* D => bin_in[0]
*/
// note: tmp variables use implicit nets
//led_out[6] = A’B’C’ + A’BCD + ABC’D’
assign led_out[6] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1]) |
(bin_in_inv[3] & bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]);
//led_out[5] = A’B’D + A’B’C + A’CD +ABC’D
assign led_out[5] = (bin_in_inv[3] & bin_in_inv[2] & bin_in[0]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
//led_out[4] = A’D + B’C’D + A’BC’
assign led_out[4] = (bin_in_inv[3] & bin_in[0]) |
(bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1]);
//led_out[3] = B’C’D + BCD + A’BC’D’ + AB’CD’
assign led_out[3] = (bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
//led_out[2] = ABD’ + ABC + A’B’CD’
assign led_out[2] = (bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in[3] & bin_in[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
//led_out[1] = BCD’ + ACD + ABD’ + A’BC’D
assign led_out[1] = (bin_in[2] & bin_in[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
//led_out[0] = A’B’C’D + A’BC’D’ + AB’CD + ABC’D
assign led_out[0] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
endmodule
module stimulus_seven_seg;
reg [3:0] bin_in = 0000;
wire [6:0] led_out;
reg clk;
// instantiate the seven segment decoder
seven_seg_decoder s1(led_out,bin_in);
// We'll make a counter that counts from 00 to 1111
// In order to do that, we'll need a clock
initial
clk = 1'b0;
always
#5 clk = ~clk; //toggle clock every 5 time units
always @(posedge clk)
bin_in = bin_in + 1;
initial
begin
$monitor("At time",$time,"binary input=%b and hex output=%h\n",bin_in,led_out);
#160 $stop;
end
endmodule
|
//altera_mult_add ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="UNREGISTERED" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone II" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_addnsub3="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SELECTED_DEVICE_FAMILY="CYCLONEII" SIGNED_PIPELINE_ACLR_A="ACLR0" SIGNED_PIPELINE_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="UNREGISTERED" SIGNED_REGISTER_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_RESULT=16 aclr0 clock0 dataa datab result
//VERSION_BEGIN 13.0 cbx_altera_mult_add 2013:06:12:18:03:43:SJ cbx_altera_mult_add_rtl 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = altera_mult_add_rtl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_mult_add_opt2
(
aclr0,
clock0,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr0;
input clock0;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [15:0] dataa;
tri0 [15:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] wire_altera_mult_add_rtl1_result;
altera_mult_add_rtl altera_mult_add_rtl1
(
.aclr0(aclr0),
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add_rtl1_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({22{1'b0}}),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({16{1'b0}}),
.scaninb({16{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sload_accum(1'b0),
.sourcea({1{1'b0}}),
.sourceb({1{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add_rtl1.accum_direction = "ADD",
altera_mult_add_rtl1.accum_sload_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_pipeline_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.accum_sload_register = "UNREGISTERED",
altera_mult_add_rtl1.accumulator = "NO",
altera_mult_add_rtl1.adder1_rounding = "NO",
altera_mult_add_rtl1.adder3_rounding = "NO",
altera_mult_add_rtl1.addnsub1_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub1_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_register3 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.chainout_aclr = "NONE",
altera_mult_add_rtl1.chainout_adder = "NO",
altera_mult_add_rtl1.chainout_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_rounding = "NO",
altera_mult_add_rtl1.chainout_saturate_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturation = "NO",
altera_mult_add_rtl1.coef0_0 = 0,
altera_mult_add_rtl1.coef0_1 = 0,
altera_mult_add_rtl1.coef0_2 = 0,
altera_mult_add_rtl1.coef0_3 = 0,
altera_mult_add_rtl1.coef0_4 = 0,
altera_mult_add_rtl1.coef0_5 = 0,
altera_mult_add_rtl1.coef0_6 = 0,
altera_mult_add_rtl1.coef0_7 = 0,
altera_mult_add_rtl1.coef1_0 = 0,
altera_mult_add_rtl1.coef1_1 = 0,
altera_mult_add_rtl1.coef1_2 = 0,
altera_mult_add_rtl1.coef1_3 = 0,
altera_mult_add_rtl1.coef1_4 = 0,
altera_mult_add_rtl1.coef1_5 = 0,
altera_mult_add_rtl1.coef1_6 = 0,
altera_mult_add_rtl1.coef1_7 = 0,
altera_mult_add_rtl1.coef2_0 = 0,
altera_mult_add_rtl1.coef2_1 = 0,
altera_mult_add_rtl1.coef2_2 = 0,
altera_mult_add_rtl1.coef2_3 = 0,
altera_mult_add_rtl1.coef2_4 = 0,
altera_mult_add_rtl1.coef2_5 = 0,
altera_mult_add_rtl1.coef2_6 = 0,
altera_mult_add_rtl1.coef2_7 = 0,
altera_mult_add_rtl1.coef3_0 = 0,
altera_mult_add_rtl1.coef3_1 = 0,
altera_mult_add_rtl1.coef3_2 = 0,
altera_mult_add_rtl1.coef3_3 = 0,
altera_mult_add_rtl1.coef3_4 = 0,
altera_mult_add_rtl1.coef3_5 = 0,
altera_mult_add_rtl1.coef3_6 = 0,
altera_mult_add_rtl1.coef3_7 = 0,
altera_mult_add_rtl1.coefsel0_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_register = "UNREGISTERED",
altera_mult_add_rtl1.dedicated_multiplier_circuitry = "YES",
altera_mult_add_rtl1.double_accum = "NO",
altera_mult_add_rtl1.dsp_block_balancing = "Auto",
altera_mult_add_rtl1.extra_latency = 0,
altera_mult_add_rtl1.input_aclr_a0 = "NONE",
altera_mult_add_rtl1.input_aclr_a1 = "NONE",
altera_mult_add_rtl1.input_aclr_a2 = "NONE",
altera_mult_add_rtl1.input_aclr_a3 = "NONE",
altera_mult_add_rtl1.input_aclr_b0 = "NONE",
altera_mult_add_rtl1.input_aclr_b1 = "NONE",
altera_mult_add_rtl1.input_aclr_b2 = "NONE",
altera_mult_add_rtl1.input_aclr_b3 = "NONE",
altera_mult_add_rtl1.input_aclr_c0 = "NONE",
altera_mult_add_rtl1.input_aclr_c1 = "NONE",
altera_mult_add_rtl1.input_aclr_c2 = "NONE",
altera_mult_add_rtl1.input_aclr_c3 = "NONE",
altera_mult_add_rtl1.input_register_a0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c3 = "UNREGISTERED",
altera_mult_add_rtl1.input_source_a0 = "DATAA",
altera_mult_add_rtl1.input_source_a1 = "DATAA",
altera_mult_add_rtl1.input_source_a2 = "DATAA",
altera_mult_add_rtl1.input_source_a3 = "DATAA",
altera_mult_add_rtl1.input_source_b0 = "DATAB",
altera_mult_add_rtl1.input_source_b1 = "DATAB",
altera_mult_add_rtl1.input_source_b2 = "DATAB",
altera_mult_add_rtl1.input_source_b3 = "DATAB",
altera_mult_add_rtl1.loadconst_control_aclr = "NONE",
altera_mult_add_rtl1.loadconst_control_register = "UNREGISTERED",
altera_mult_add_rtl1.loadconst_value = 64,
altera_mult_add_rtl1.mult01_round_aclr = "NONE",
altera_mult_add_rtl1.mult01_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult01_saturation_aclr = "ACLR0",
altera_mult_add_rtl1.mult01_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_round_aclr = "NONE",
altera_mult_add_rtl1.mult23_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_saturation_aclr = "NONE",
altera_mult_add_rtl1.mult23_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.multiplier01_rounding = "NO",
altera_mult_add_rtl1.multiplier01_saturation = "NO",
altera_mult_add_rtl1.multiplier1_direction = "ADD",
altera_mult_add_rtl1.multiplier23_rounding = "NO",
altera_mult_add_rtl1.multiplier23_saturation = "NO",
altera_mult_add_rtl1.multiplier3_direction = "ADD",
altera_mult_add_rtl1.multiplier_aclr0 = "ACLR0",
altera_mult_add_rtl1.multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.multiplier_aclr2 = "NONE",
altera_mult_add_rtl1.multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.multiplier_register0 = "CLOCK0",
altera_mult_add_rtl1.multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register2 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.number_of_multipliers = 1,
altera_mult_add_rtl1.output_aclr = "NONE",
altera_mult_add_rtl1.output_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_type = "NEAREST_INTEGER",
altera_mult_add_rtl1.output_rounding = "NO",
altera_mult_add_rtl1.output_saturate_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_type = "ASYMMETRIC",
altera_mult_add_rtl1.output_saturation = "NO",
altera_mult_add_rtl1.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_rtl1.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_rtl1.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_signa = "PORT_UNUSED",
altera_mult_add_rtl1.port_signb = "PORT_UNUSED",
altera_mult_add_rtl1.preadder_direction_0 = "ADD",
altera_mult_add_rtl1.preadder_direction_1 = "ADD",
altera_mult_add_rtl1.preadder_direction_2 = "ADD",
altera_mult_add_rtl1.preadder_direction_3 = "ADD",
altera_mult_add_rtl1.preadder_mode = "SIMPLE",
altera_mult_add_rtl1.representation_a = "UNSIGNED",
altera_mult_add_rtl1.representation_b = "UNSIGNED",
altera_mult_add_rtl1.rotate_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.rotate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_register = "UNREGISTERED",
altera_mult_add_rtl1.scanouta_aclr = "NONE",
altera_mult_add_rtl1.scanouta_register = "UNREGISTERED",
altera_mult_add_rtl1.selected_device_family = "Cyclone II",
altera_mult_add_rtl1.shift_mode = "NO",
altera_mult_add_rtl1.shift_right_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_pipeline_aclr = "NONE",
altera_mult_add_rtl1.shift_right_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_register = "UNREGISTERED",
altera_mult_add_rtl1.signed_aclr_a = "NONE",
altera_mult_add_rtl1.signed_aclr_b = "NONE",
altera_mult_add_rtl1.signed_pipeline_aclr_a = "ACLR0",
altera_mult_add_rtl1.signed_pipeline_aclr_b = "ACLR0",
altera_mult_add_rtl1.signed_pipeline_register_a = "CLOCK0",
altera_mult_add_rtl1.signed_pipeline_register_b = "CLOCK0",
altera_mult_add_rtl1.signed_register_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_b = "UNREGISTERED",
altera_mult_add_rtl1.systolic_aclr1 = "NONE",
altera_mult_add_rtl1.systolic_aclr3 = "NONE",
altera_mult_add_rtl1.systolic_delay1 = "UNREGISTERED",
altera_mult_add_rtl1.systolic_delay3 = "UNREGISTERED",
altera_mult_add_rtl1.use_sload_accum_port = "NO",
altera_mult_add_rtl1.width_a = 16,
altera_mult_add_rtl1.width_b = 16,
altera_mult_add_rtl1.width_c = 22,
altera_mult_add_rtl1.width_chainin = 1,
altera_mult_add_rtl1.width_coef = 18,
altera_mult_add_rtl1.width_msb = 17,
altera_mult_add_rtl1.width_result = 16,
altera_mult_add_rtl1.width_saturate_sign = 1,
altera_mult_add_rtl1.zero_chainout_output_aclr = "NONE",
altera_mult_add_rtl1.zero_chainout_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_pipeline_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_register = "UNREGISTERED",
altera_mult_add_rtl1.lpm_type = "altera_mult_add_rtl";
assign
result = wire_altera_mult_add_rtl1_result;
endmodule //altera_mult_add_opt2
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S4S_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DLYMETAL6S4S_PP_SYMBOL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlymetal6s4s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S4S_PP_SYMBOL_V
|
`default_nettype none
module mmu_table_load(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Load Req
input wire iLD_REQ,
input wire [31:0] iLD_ADDR,
output wire oLD_BUSY,
//Memory Pipe - REQ
output wire oMEM_REQ,
input wire iMEM_LOCK,
output wire [31:0] oMEM_ADDR,
//Memory Pipe - ACK
input wire iMEM_VALID,
input wire [63:0] iMEM_DATA,
//DONE
output wire oDONE_VALID,
output wire [31:0] oDONE_DATA,
output wire [11:0] oDONE_FLAG0,
output wire [11:0] oDONE_FLAG1
);
reg [1:0] b_main_state;
reg [31:0] b_req_addr;
localparam PL_MAIN_STT_IDLE = 2'h0;
localparam PL_MAIN_STT_REQ = 2'h1;
localparam PL_MAIN_STT_WAITING = 2'h2;
wire latch_condition = iLD_REQ && (b_main_state == PL_MAIN_STT_IDLE);
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_req_addr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_req_addr <= 32'h0;
end
else begin
if(latch_condition)begin
b_req_addr <= iLD_ADDR;
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_main_state <= PL_MAIN_STT_IDLE;
end
else if(iRESET_SYNC)begin
b_main_state <= PL_MAIN_STT_IDLE;
end
else begin
case(b_main_state)
PL_MAIN_STT_IDLE:
begin
if(latch_condition)begin
if(iMEM_LOCK)begin
b_main_state <= PL_MAIN_STT_REQ;
end
else begin
b_main_state <= PL_MAIN_STT_WAITING;
end
end
end
PL_MAIN_STT_REQ:
begin
if(!iMEM_LOCK)begin
b_main_state <= PL_MAIN_STT_WAITING;
end
end
PL_MAIN_STT_WAITING:
begin
if(iMEM_VALID)begin
b_main_state <= PL_MAIN_STT_IDLE;
end
end
default:
begin
b_main_state <= PL_MAIN_STT_IDLE;
end
endcase
end
end
/*
reg b_buff_valid;
reg [31:0] b_buff_data;
reg [11:0] b_buff_flag0;
reg [11:0] b_buff_flag1;
always@(posedge iCLOCK or negedge inRESET)begin
b_buff_valid <= (b_main_state == PL_MAIN_STT_WAITING) && iMEM_VALID;
end
always@(posedge iCLOCK or negedge inRESET)begin
b_buff_data <= (b_req_addr[2])? iMEM_DATA[63:32] : iMEM_DATA[31:0];
b_buff_flag0 <= iMEM_DATA[11:0];
b_buff_flag1 <= iMEM_DATA[43:32];
end
*/
assign oLD_BUSY = (b_main_state != PL_MAIN_STT_IDLE);
//Memory Pipe - REQ
assign oMEM_REQ = (b_main_state == PL_MAIN_STT_REQ) || latch_condition;
assign oMEM_ADDR = (b_main_state == PL_MAIN_STT_REQ)? b_req_addr : iLD_ADDR;
//DONE
assign oDONE_VALID = (b_main_state == PL_MAIN_STT_WAITING) && iMEM_VALID;
assign oDONE_DATA = (b_req_addr[2])? iMEM_DATA[63:32] : iMEM_DATA[31:0];
assign oDONE_FLAG0 = iMEM_DATA[11:0];
assign oDONE_FLAG1 = iMEM_DATA[43:32];
/*
assign oDONE_VALID = b_buff_valid;
assign oDONE_DATA = b_buff_data;
assign oDONE_FLAG0 = b_buff_flag0;
assign oDONE_FLAG1 = b_buff_flag1;
*/
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21A_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O21A_PP_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21A_PP_BLACKBOX_V
|
module register_ctrl_top(
input I_sys_clk ,
input I_sys_rst ,
//=====================System usb_uart_if===========================
output O_usb_uart_tx_req ,
output [7 : 0] O_usb_uart_tx_data ,
input I_usb_uart_tx_full ,
output O_usb_uart_rx_req ,
input [7 : 0] I_usb_uart_rx_data ,
input I_usb_uart_rx_empty ,
//==================================================================
output O_usb_dir ,
output O_motor_start ,
output tp ,
input I_key_start
);
//=======================================================================
reg R_usb_uart_rx_req ;
reg R_usb_uart_rx_req_d1 ;
reg R_tx_en ;
reg [7 : 0] R_tx_data ;
reg R_rx_en ;
reg [7 : 0] R_rx_data ;
reg R_usb_dir ;
reg R_motor_start ;
//=======================================================================
always@(posedge I_sys_clk)
begin
if(I_sys_rst)
begin
R_usb_uart_rx_req <= 1'd0 ;
end
else if(I_usb_uart_rx_empty == 1'b0) // if has data .then read
begin
R_usb_uart_rx_req <= 1'd1 ;
end
else
begin
R_usb_uart_rx_req <= 1'd0 ;
end
//
R_usb_uart_rx_req_d1 <= R_usb_uart_rx_req;
end
always@(posedge I_sys_clk)
begin
if(I_sys_rst)
begin
R_rx_en <= 1'd0 ;
R_rx_data <= 8'd0 ;
end
else if(R_usb_uart_rx_req_d1 == 1'b1)
begin
R_rx_en <= 1'd1 ;
R_rx_data <= I_usb_uart_rx_data ;
end
else
begin
R_rx_en <= 1'd0 ;
end
end
always@(posedge I_sys_clk)
begin
if(I_sys_rst)
begin
R_tx_en <= 1'd0 ;
R_tx_data <= 8'd0 ;
end
else if(I_usb_uart_tx_full==1'b0) // not full
begin
if(I_key_start==1'b1)
begin
R_tx_en <= 1'b1 ;//R_rx_en;
R_tx_data <= 8'h55 ;//R_rx_data;
end
else
begin
R_tx_en <= 1'b0 ;//R_rx_en;
end
end
else
begin
R_tx_en <= 1'b0 ;
end
end
always@(posedge I_sys_clk)
begin
if(I_sys_rst)
begin
R_usb_dir <= 1'd0; //目前采用了默认值
R_motor_start <= 1'b0;
end
else if(R_rx_en)
begin
case(R_rx_data)
8'h00:
begin
R_usb_dir <= 1'b0; //wr TO USB
end
8'hff:
begin
R_usb_dir <= 1'b1; // rd FROM USB
end
8'h02:
begin
R_motor_start <= 1'b1; // motor
end
endcase
end
else
begin
R_motor_start <= 1'b0;
end
end
assign O_usb_uart_rx_req = R_usb_uart_rx_req;
assign O_usb_uart_tx_req = R_tx_en ;
assign O_usb_uart_tx_data = R_tx_data;
assign O_usb_dir = R_usb_dir ;
assign O_motor_start = R_motor_start;
assign tp = R_rx_en & (&R_rx_data) & O_motor_start & O_usb_dir;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DECAP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DECAP_PP_SYMBOL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__decap (
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DECAP_PP_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PIO.v
// Version : 1.11
//
// Description: Programmed I/O module. Design implements 8 KBytes of programmable
//-- memory space. Host processor can access this memory space using
//-- Memory Read 32 and Memory Write 32 TLPs. Design accepts
//-- 1 Double Word (DW) payload length on Memory Write 32 TLP and
//-- responds to 1 DW length Memory Read 32 TLPs with a Completion
//-- with Data TLP (1DW payload).
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module PIO #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width
parameter TCQ = 1
)(
input user_clk,
input user_reset,
input user_lnk_up,
// AXIS
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
input cfg_to_turnoff,
output cfg_turnoff_ok,
input [15:0] cfg_completer_id
); // synthesis syn_hier = "hard"
// Local wires
wire req_compl;
wire compl_done;
reg pio_reset_n;
always @(posedge user_clk) begin
if (user_reset)
pio_reset_n <= #TCQ 1'b0;
else
pio_reset_n <= #TCQ user_lnk_up;
end
//
// PIO instance
//
PIO_EP #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH ),
.TCQ( TCQ )
) PIO_EP_inst (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tkeep( s_axis_tx_tkeep ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tkeep( m_axis_rx_tkeep ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
.req_compl(req_compl), // O
.compl_done(compl_done), // O
.cfg_completer_id ( cfg_completer_id ) // I [15:0]
);
//
// Turn-Off controller
//
PIO_TO_CTRL #(
.TCQ( TCQ )
) PIO_TO_inst (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.req_compl( req_compl ), // I
.compl_done( compl_done ), // I
.cfg_to_turnoff( cfg_to_turnoff ), // I
.cfg_turnoff_ok( cfg_turnoff_ok ) // O
);
endmodule // PIO
|
`default_nettype none
`include "processor.h"
module dispatch_general_register(
//System
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Write Port
input wire iWR_VALID,
input wire [4:0] iWR_ADDR,
input wire [31:0] iWR_DATA,
//Read Port0
input wire [4:0] iRD0_ADDR,
output wire [31:0] oRD0_DATA,
//Read Port1
input wire [4:0] iRD1_ADDR,
output wire [31:0] oRD1_DATA,
//Debug Module
output wire [31:0] oDEBUG_REG_OUT_GR0,
output wire [31:0] oDEBUG_REG_OUT_GR1,
output wire [31:0] oDEBUG_REG_OUT_GR2,
output wire [31:0] oDEBUG_REG_OUT_GR3,
output wire [31:0] oDEBUG_REG_OUT_GR4,
output wire [31:0] oDEBUG_REG_OUT_GR5,
output wire [31:0] oDEBUG_REG_OUT_GR6,
output wire [31:0] oDEBUG_REG_OUT_GR7,
output wire [31:0] oDEBUG_REG_OUT_GR8,
output wire [31:0] oDEBUG_REG_OUT_GR9,
output wire [31:0] oDEBUG_REG_OUT_GR10,
output wire [31:0] oDEBUG_REG_OUT_GR11,
output wire [31:0] oDEBUG_REG_OUT_GR12,
output wire [31:0] oDEBUG_REG_OUT_GR13,
output wire [31:0] oDEBUG_REG_OUT_GR14,
output wire [31:0] oDEBUG_REG_OUT_GR15,
output wire [31:0] oDEBUG_REG_OUT_GR16,
output wire [31:0] oDEBUG_REG_OUT_GR17,
output wire [31:0] oDEBUG_REG_OUT_GR18,
output wire [31:0] oDEBUG_REG_OUT_GR19,
output wire [31:0] oDEBUG_REG_OUT_GR20,
output wire [31:0] oDEBUG_REG_OUT_GR21,
output wire [31:0] oDEBUG_REG_OUT_GR22,
output wire [31:0] oDEBUG_REG_OUT_GR23,
output wire [31:0] oDEBUG_REG_OUT_GR24,
output wire [31:0] oDEBUG_REG_OUT_GR25,
output wire [31:0] oDEBUG_REG_OUT_GR26,
output wire [31:0] oDEBUG_REG_OUT_GR27,
output wire [31:0] oDEBUG_REG_OUT_GR28,
output wire [31:0] oDEBUG_REG_OUT_GR29,
output wire [31:0] oDEBUG_REG_OUT_GR30,
output wire [31:0] oDEBUG_REG_OUT_GR31
);
integer i;
reg [31:0] b_ram0[0:31];
reg [31:0] b_ram1[0:31];
//RAM0
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 32; i = i + 1)begin
b_ram0[i] <= 32'h0;
end
end
else if(iRESET_SYNC)begin
for(i = 0; i < 32; i = i + 1)begin
b_ram0[i] <= 32'h0;
end
end
else begin
if(iWR_VALID)begin
b_ram0[iWR_ADDR] <= iWR_DATA;
end
end
end//General Register Write Back
//RAM1
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 32; i = i + 1)begin
b_ram1[i] <= 32'h0;
end
end
else if(iRESET_SYNC)begin
for(i = 0; i < 32; i = i + 1)begin
b_ram1[i] <= 32'h0;
end
end
else begin
if(iWR_VALID)begin
b_ram1[iWR_ADDR] <= iWR_DATA;
end
end
end//General Register Write Back
assign oRD0_DATA = b_ram0[iRD0_ADDR];
assign oRD1_DATA = b_ram1[iRD1_ADDR];
//Debug Module Enable
`ifdef MIST1032ISA_STANDARD_DEBUGGER
assign oDEBUG_REG_OUT_GR0 = b_ram0[0];
assign oDEBUG_REG_OUT_GR1 = b_ram0[1];
assign oDEBUG_REG_OUT_GR2 = b_ram0[2];
assign oDEBUG_REG_OUT_GR3 = b_ram0[3];
assign oDEBUG_REG_OUT_GR4 = b_ram0[4];
assign oDEBUG_REG_OUT_GR5 = b_ram0[5];
assign oDEBUG_REG_OUT_GR6 = b_ram0[6];
assign oDEBUG_REG_OUT_GR7 = b_ram0[7];
assign oDEBUG_REG_OUT_GR8 = b_ram0[8];
assign oDEBUG_REG_OUT_GR9 = b_ram0[9];
assign oDEBUG_REG_OUT_GR10 = b_ram0[10];
assign oDEBUG_REG_OUT_GR11 = b_ram0[11];
assign oDEBUG_REG_OUT_GR12 = b_ram0[12];
assign oDEBUG_REG_OUT_GR13 = b_ram0[13];
assign oDEBUG_REG_OUT_GR14 = b_ram0[14];
assign oDEBUG_REG_OUT_GR15 = b_ram0[15];
assign oDEBUG_REG_OUT_GR16 = b_ram0[16];
assign oDEBUG_REG_OUT_GR17 = b_ram0[17];
assign oDEBUG_REG_OUT_GR18 = b_ram0[18];
assign oDEBUG_REG_OUT_GR19 = b_ram0[19];
assign oDEBUG_REG_OUT_GR20 = b_ram0[20];
assign oDEBUG_REG_OUT_GR21 = b_ram0[21];
assign oDEBUG_REG_OUT_GR22 = b_ram0[22];
assign oDEBUG_REG_OUT_GR23 = b_ram0[23];
assign oDEBUG_REG_OUT_GR24 = b_ram0[24];
assign oDEBUG_REG_OUT_GR25 = b_ram0[25];
assign oDEBUG_REG_OUT_GR26 = b_ram0[26];
assign oDEBUG_REG_OUT_GR27 = b_ram0[27];
assign oDEBUG_REG_OUT_GR28 = b_ram0[28];
assign oDEBUG_REG_OUT_GR29 = b_ram0[29];
assign oDEBUG_REG_OUT_GR30 = b_ram0[30];
assign oDEBUG_REG_OUT_GR31 = b_ram0[31];
`else
//Disable
assign oDEBUG_REG_OUT_GR0 = 32'h0;
assign oDEBUG_REG_OUT_GR1 = 32'h0;
assign oDEBUG_REG_OUT_GR2 = 32'h0;
assign oDEBUG_REG_OUT_GR3 = 32'h0;
assign oDEBUG_REG_OUT_GR4 = 32'h0;
assign oDEBUG_REG_OUT_GR5 = 32'h0;
assign oDEBUG_REG_OUT_GR6 = 32'h0;
assign oDEBUG_REG_OUT_GR7 = 32'h0;
assign oDEBUG_REG_OUT_GR8 = 32'h0;
assign oDEBUG_REG_OUT_GR9 = 32'h0;
assign oDEBUG_REG_OUT_GR10 = 32'h0;
assign oDEBUG_REG_OUT_GR11 = 32'h0;
assign oDEBUG_REG_OUT_GR12 = 32'h0;
assign oDEBUG_REG_OUT_GR13 = 32'h0;
assign oDEBUG_REG_OUT_GR14 = 32'h0;
assign oDEBUG_REG_OUT_GR15 = 32'h0;
assign oDEBUG_REG_OUT_GR16 = 32'h0;
assign oDEBUG_REG_OUT_GR17 = 32'h0;
assign oDEBUG_REG_OUT_GR18 = 32'h0;
assign oDEBUG_REG_OUT_GR19 = 32'h0;
assign oDEBUG_REG_OUT_GR20 = 32'h0;
assign oDEBUG_REG_OUT_GR21 = 32'h0;
assign oDEBUG_REG_OUT_GR22 = 32'h0;
assign oDEBUG_REG_OUT_GR23 = 32'h0;
assign oDEBUG_REG_OUT_GR24 = 32'h0;
assign oDEBUG_REG_OUT_GR25 = 32'h0;
assign oDEBUG_REG_OUT_GR26 = 32'h0;
assign oDEBUG_REG_OUT_GR27 = 32'h0;
assign oDEBUG_REG_OUT_GR28 = 32'h0;
assign oDEBUG_REG_OUT_GR29 = 32'h0;
assign oDEBUG_REG_OUT_GR30 = 32'h0;
assign oDEBUG_REG_OUT_GR31 = 32'h0;
`endif
endmodule // dispatch_general_register
`default_nettype wire
|
// wasca.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module wasca (
input wire [9:0] abus_avalon_sdram_bridge_0_abus_address, // abus_avalon_sdram_bridge_0_abus.address
input wire abus_avalon_sdram_bridge_0_abus_read, // .read
output wire abus_avalon_sdram_bridge_0_abus_waitrequest, // .waitrequest
inout wire [15:0] abus_avalon_sdram_bridge_0_abus_addressdata, // .addressdata
input wire [2:0] abus_avalon_sdram_bridge_0_abus_chipselect, // .chipselect
output wire abus_avalon_sdram_bridge_0_abus_direction, // .direction
output wire abus_avalon_sdram_bridge_0_abus_disable_out, // .disable_out
output wire abus_avalon_sdram_bridge_0_abus_interrupt, // .interrupt
output wire [1:0] abus_avalon_sdram_bridge_0_abus_muxing, // .muxing
input wire [1:0] abus_avalon_sdram_bridge_0_abus_writebyteenable_n, // .writebyteenable_n
input wire abus_avalon_sdram_bridge_0_abus_reset, // .reset
output wire [12:0] abus_avalon_sdram_bridge_0_sdram_addr, // abus_avalon_sdram_bridge_0_sdram.addr
output wire [1:0] abus_avalon_sdram_bridge_0_sdram_ba, // .ba
output wire abus_avalon_sdram_bridge_0_sdram_cas_n, // .cas_n
output wire abus_avalon_sdram_bridge_0_sdram_cke, // .cke
output wire abus_avalon_sdram_bridge_0_sdram_cs_n, // .cs_n
inout wire [15:0] abus_avalon_sdram_bridge_0_sdram_dq, // .dq
output wire [1:0] abus_avalon_sdram_bridge_0_sdram_dqm, // .dqm
output wire abus_avalon_sdram_bridge_0_sdram_ras_n, // .ras_n
output wire abus_avalon_sdram_bridge_0_sdram_we_n, // .we_n
output wire abus_avalon_sdram_bridge_0_sdram_clk, // .clk
inout wire altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd, // altera_up_sd_card_avalon_interface_0_conduit_end.b_SD_cmd
inout wire altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat, // .b_SD_dat
inout wire altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3, // .b_SD_dat3
output wire altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock, // .o_SD_clock
input wire altpll_1_areset_conduit_export, // altpll_1_areset_conduit.export
output wire altpll_1_locked_conduit_export, // altpll_1_locked_conduit.export
output wire altpll_1_phasedone_conduit_export, // altpll_1_phasedone_conduit.export
input wire audio_out_BCLK, // audio_out.BCLK
output wire audio_out_DACDAT, // .DACDAT
input wire audio_out_DACLRCK, // .DACLRCK
output wire buffered_spi_mosi, // buffered_spi.mosi
output wire buffered_spi_clk, // .clk
input wire buffered_spi_miso, // .miso
output wire buffered_spi_cs, // .cs
input wire clk_clk, // clk.clk
output wire clock_116_mhz_clk, // clock_116_mhz.clk
input wire reset_reset_n, // reset.reset_n
input wire reset_controller_0_reset_in1_reset, // reset_controller_0_reset_in1.reset
input wire uart_0_external_connection_rxd, // uart_0_external_connection.rxd
output wire uart_0_external_connection_txd // .txd
);
wire nios2_gen2_0_debug_reset_request_reset; // nios2_gen2_0:debug_reset_request -> [buffered_spi_0:reset, mm_interconnect_0:buffered_spi_0_reset_reset_bridge_in_reset_reset, reset_controller_0:reset_in0]
wire [31:0] nios2_gen2_0_data_master_readdata; // mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
wire nios2_gen2_0_data_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
wire nios2_gen2_0_data_master_debugaccess; // nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
wire [26:0] nios2_gen2_0_data_master_address; // nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
wire [3:0] nios2_gen2_0_data_master_byteenable; // nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
wire nios2_gen2_0_data_master_read; // nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
wire nios2_gen2_0_data_master_write; // nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
wire [31:0] nios2_gen2_0_data_master_writedata; // nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
wire [31:0] nios2_gen2_0_instruction_master_readdata; // mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
wire nios2_gen2_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
wire [19:0] nios2_gen2_0_instruction_master_address; // nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
wire nios2_gen2_0_instruction_master_read; // nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
wire [15:0] mm_interconnect_0_buffered_spi_0_avalon_readdata; // buffered_spi_0:avalon_readdata -> mm_interconnect_0:buffered_spi_0_avalon_readdata
wire mm_interconnect_0_buffered_spi_0_avalon_waitrequest; // buffered_spi_0:avalon_waitrequest -> mm_interconnect_0:buffered_spi_0_avalon_waitrequest
wire [13:0] mm_interconnect_0_buffered_spi_0_avalon_address; // mm_interconnect_0:buffered_spi_0_avalon_address -> buffered_spi_0:avalon_address
wire mm_interconnect_0_buffered_spi_0_avalon_read; // mm_interconnect_0:buffered_spi_0_avalon_read -> buffered_spi_0:avalon_read
wire mm_interconnect_0_buffered_spi_0_avalon_readdatavalid; // buffered_spi_0:avalon_readdatavalid -> mm_interconnect_0:buffered_spi_0_avalon_readdatavalid
wire mm_interconnect_0_buffered_spi_0_avalon_write; // mm_interconnect_0:buffered_spi_0_avalon_write -> buffered_spi_0:avalon_write
wire [15:0] mm_interconnect_0_buffered_spi_0_avalon_writedata; // mm_interconnect_0:buffered_spi_0_avalon_writedata -> buffered_spi_0:avalon_writedata
wire mm_interconnect_0_audio_0_avalon_audio_slave_chipselect; // mm_interconnect_0:audio_0_avalon_audio_slave_chipselect -> audio_0:chipselect
wire [31:0] mm_interconnect_0_audio_0_avalon_audio_slave_readdata; // audio_0:readdata -> mm_interconnect_0:audio_0_avalon_audio_slave_readdata
wire [1:0] mm_interconnect_0_audio_0_avalon_audio_slave_address; // mm_interconnect_0:audio_0_avalon_audio_slave_address -> audio_0:address
wire mm_interconnect_0_audio_0_avalon_audio_slave_read; // mm_interconnect_0:audio_0_avalon_audio_slave_read -> audio_0:read
wire mm_interconnect_0_audio_0_avalon_audio_slave_write; // mm_interconnect_0:audio_0_avalon_audio_slave_write -> audio_0:write
wire [31:0] mm_interconnect_0_audio_0_avalon_audio_slave_writedata; // mm_interconnect_0:audio_0_avalon_audio_slave_writedata -> audio_0:writedata
wire [15:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdata; // abus_avalon_sdram_bridge_0:avalon_regs_readdata -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_readdata
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_waitrequest; // abus_avalon_sdram_bridge_0:avalon_regs_waitrequest -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_waitrequest
wire [7:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_address; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_address -> abus_avalon_sdram_bridge_0:avalon_regs_address
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_read; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_read -> abus_avalon_sdram_bridge_0:avalon_regs_read
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid; // abus_avalon_sdram_bridge_0:avalon_regs_readdatavalid -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_write; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_write -> abus_avalon_sdram_bridge_0:avalon_regs_write
wire [15:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_writedata; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_writedata -> abus_avalon_sdram_bridge_0:avalon_regs_writedata
wire mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_chipselect; // mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_chip_select
wire [31:0] mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_readdata; // Altera_UP_SD_Card_Avalon_Interface_0:o_avalon_readdata -> mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata
wire mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_waitrequest; // Altera_UP_SD_Card_Avalon_Interface_0:o_avalon_waitrequest -> mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest
wire [7:0] mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_address; // mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_address
wire mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_read; // mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_read
wire [3:0] mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_byteenable; // mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_byteenable
wire mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_write; // mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_write
wire [31:0] mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_writedata; // mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_writedata
wire [15:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdata; // abus_avalon_sdram_bridge_0:avalon_sdram_readdata -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_readdata
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest; // abus_avalon_sdram_bridge_0:avalon_sdram_waitrequest -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest
wire [25:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_address; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_address -> abus_avalon_sdram_bridge_0:avalon_sdram_address
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_read; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_read -> abus_avalon_sdram_bridge_0:avalon_sdram_read
wire [1:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_byteenable; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_byteenable -> abus_avalon_sdram_bridge_0:avalon_sdram_byteenable
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid; // abus_avalon_sdram_bridge_0:avalon_sdram_readdatavalid -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_write; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_write -> abus_avalon_sdram_bridge_0:avalon_sdram_write
wire [15:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_writedata; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_writedata -> abus_avalon_sdram_bridge_0:avalon_sdram_writedata
wire [31:0] mm_interconnect_0_onchip_flash_0_data_readdata; // onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata
wire mm_interconnect_0_onchip_flash_0_data_waitrequest; // onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest
wire [15:0] mm_interconnect_0_onchip_flash_0_data_address; // mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr
wire mm_interconnect_0_onchip_flash_0_data_read; // mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read
wire mm_interconnect_0_onchip_flash_0_data_readdatavalid; // onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid
wire [3:0] mm_interconnect_0_onchip_flash_0_data_burstcount; // mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount
wire [31:0] mm_interconnect_0_altpll_1_pll_slave_readdata; // altpll_1:readdata -> mm_interconnect_0:altpll_1_pll_slave_readdata
wire [1:0] mm_interconnect_0_altpll_1_pll_slave_address; // mm_interconnect_0:altpll_1_pll_slave_address -> altpll_1:address
wire mm_interconnect_0_altpll_1_pll_slave_read; // mm_interconnect_0:altpll_1_pll_slave_read -> altpll_1:read
wire mm_interconnect_0_altpll_1_pll_slave_write; // mm_interconnect_0:altpll_1_pll_slave_write -> altpll_1:write
wire [31:0] mm_interconnect_0_altpll_1_pll_slave_writedata; // mm_interconnect_0:altpll_1_pll_slave_writedata -> altpll_1:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [11:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_uart_0_s1_chipselect; // mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
wire [15:0] mm_interconnect_0_uart_0_s1_readdata; // uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
wire [2:0] mm_interconnect_0_uart_0_s1_address; // mm_interconnect_0:uart_0_s1_address -> uart_0:address
wire mm_interconnect_0_uart_0_s1_read; // mm_interconnect_0:uart_0_s1_read -> uart_0:read_n
wire mm_interconnect_0_uart_0_s1_begintransfer; // mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
wire mm_interconnect_0_uart_0_s1_write; // mm_interconnect_0:uart_0_s1_write -> uart_0:write_n
wire [15:0] mm_interconnect_0_uart_0_s1_writedata; // mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata; // nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest; // nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
wire irq_mapper_receiver0_irq; // audio_0:irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // uart_0:irq -> irq_mapper:receiver1_irq
wire [31:0] nios2_gen2_0_irq_irq; // irq_mapper:sender_irq -> nios2_gen2_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [Altera_UP_SD_Card_Avalon_Interface_0:i_reset_n, abus_avalon_sdram_bridge_0:reset, audio_0:reset, irq_mapper:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, onchip_memory2_0:reset, rst_translator:in_reset, uart_0:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire reset_controller_0_reset_out_reset; // reset_controller_0:reset_out -> [rst_controller:reset_in0, rst_controller_002:reset_in0]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [altpll_1:reset, mm_interconnect_0:altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset]
Altera_UP_SD_Card_Avalon_Interface altera_up_sd_card_avalon_interface_0 (
.i_avalon_chip_select (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_chipselect), // avalon_sdcard_slave.chipselect
.i_avalon_address (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_address), // .address
.i_avalon_read (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_read), // .read
.i_avalon_write (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_write), // .write
.i_avalon_byteenable (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_byteenable), // .byteenable
.i_avalon_writedata (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_writedata), // .writedata
.o_avalon_readdata (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_readdata), // .readdata
.o_avalon_waitrequest (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_waitrequest), // .waitrequest
.i_clock (clock_116_mhz_clk), // clk.clk
.i_reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.b_SD_cmd (altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd), // conduit_end.export
.b_SD_dat (altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat), // .export
.b_SD_dat3 (altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3), // .export
.o_SD_clock (altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock) // .export
);
abus_avalon_sdram_bridge abus_avalon_sdram_bridge_0 (
.abus_address (abus_avalon_sdram_bridge_0_abus_address), // abus.address
.abus_read (abus_avalon_sdram_bridge_0_abus_read), // .read
.abus_waitrequest (abus_avalon_sdram_bridge_0_abus_waitrequest), // .waitrequest
.abus_addressdata (abus_avalon_sdram_bridge_0_abus_addressdata), // .addressdata
.abus_chipselect (abus_avalon_sdram_bridge_0_abus_chipselect), // .chipselect
.abus_direction (abus_avalon_sdram_bridge_0_abus_direction), // .direction
.abus_disable_out (abus_avalon_sdram_bridge_0_abus_disable_out), // .disable_out
.abus_interrupt (abus_avalon_sdram_bridge_0_abus_interrupt), // .interrupt
.abus_muxing (abus_avalon_sdram_bridge_0_abus_muxing), // .muxing
.abus_write (abus_avalon_sdram_bridge_0_abus_writebyteenable_n), // .writebyteenable_n
.saturn_reset (abus_avalon_sdram_bridge_0_abus_reset), // .reset
.avalon_sdram_read (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_read), // avalon_sdram.read
.avalon_sdram_write (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_write), // .write
.avalon_sdram_waitrequest (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest), // .waitrequest
.avalon_sdram_address (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_address), // .address
.avalon_sdram_writedata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_writedata), // .writedata
.avalon_sdram_readdata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdata), // .readdata
.avalon_sdram_readdatavalid (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid), // .readdatavalid
.avalon_sdram_byteenable (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_byteenable), // .byteenable
.avalon_regs_read (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_read), // avalon_regs.read
.avalon_regs_write (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_write), // .write
.avalon_regs_waitrequest (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_waitrequest), // .waitrequest
.avalon_regs_address (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_address), // .address
.avalon_regs_writedata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_writedata), // .writedata
.avalon_regs_readdata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdata), // .readdata
.avalon_regs_readdatavalid (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid), // .readdatavalid
.reset (rst_controller_reset_out_reset), // reset.reset
.clock (clock_116_mhz_clk), // clock.clk
.sdram_addr (abus_avalon_sdram_bridge_0_sdram_addr), // sdram.addr
.sdram_ba (abus_avalon_sdram_bridge_0_sdram_ba), // .ba
.sdram_cas_n (abus_avalon_sdram_bridge_0_sdram_cas_n), // .cas_n
.sdram_cke (abus_avalon_sdram_bridge_0_sdram_cke), // .cke
.sdram_cs_n (abus_avalon_sdram_bridge_0_sdram_cs_n), // .cs_n
.sdram_dq (abus_avalon_sdram_bridge_0_sdram_dq), // .dq
.sdram_dqm (abus_avalon_sdram_bridge_0_sdram_dqm), // .dqm
.sdram_ras_n (abus_avalon_sdram_bridge_0_sdram_ras_n), // .ras_n
.sdram_we_n (abus_avalon_sdram_bridge_0_sdram_we_n), // .we_n
.sdram_clk (abus_avalon_sdram_bridge_0_sdram_clk) // .clk
);
wasca_altpll_1 altpll_1 (
.clk (clk_clk), // inclk_interface.clk
.reset (rst_controller_001_reset_out_reset), // inclk_interface_reset.reset
.read (mm_interconnect_0_altpll_1_pll_slave_read), // pll_slave.read
.write (mm_interconnect_0_altpll_1_pll_slave_write), // .write
.address (mm_interconnect_0_altpll_1_pll_slave_address), // .address
.readdata (mm_interconnect_0_altpll_1_pll_slave_readdata), // .readdata
.writedata (mm_interconnect_0_altpll_1_pll_slave_writedata), // .writedata
.c0 (clock_116_mhz_clk), // c0.clk
.areset (altpll_1_areset_conduit_export), // areset_conduit.export
.locked (altpll_1_locked_conduit_export), // locked_conduit.export
.phasedone (altpll_1_phasedone_conduit_export) // phasedone_conduit.export
);
wasca_audio_0 audio_0 (
.clk (clock_116_mhz_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.address (mm_interconnect_0_audio_0_avalon_audio_slave_address), // avalon_audio_slave.address
.chipselect (mm_interconnect_0_audio_0_avalon_audio_slave_chipselect), // .chipselect
.read (mm_interconnect_0_audio_0_avalon_audio_slave_read), // .read
.write (mm_interconnect_0_audio_0_avalon_audio_slave_write), // .write
.writedata (mm_interconnect_0_audio_0_avalon_audio_slave_writedata), // .writedata
.readdata (mm_interconnect_0_audio_0_avalon_audio_slave_readdata), // .readdata
.irq (irq_mapper_receiver0_irq), // interrupt.irq
.AUD_BCLK (audio_out_BCLK), // external_interface.export
.AUD_DACDAT (audio_out_DACDAT), // .export
.AUD_DACLRCK (audio_out_DACLRCK) // .export
);
buffered_spi buffered_spi_0 (
.reset (nios2_gen2_0_debug_reset_request_reset), // reset.reset
.avalon_read (mm_interconnect_0_buffered_spi_0_avalon_read), // avalon.read
.avalon_write (mm_interconnect_0_buffered_spi_0_avalon_write), // .write
.avalon_address (mm_interconnect_0_buffered_spi_0_avalon_address), // .address
.avalon_waitrequest (mm_interconnect_0_buffered_spi_0_avalon_waitrequest), // .waitrequest
.avalon_writedata (mm_interconnect_0_buffered_spi_0_avalon_writedata), // .writedata
.avalon_readdata (mm_interconnect_0_buffered_spi_0_avalon_readdata), // .readdata
.avalon_readdatavalid (mm_interconnect_0_buffered_spi_0_avalon_readdatavalid), // .readdatavalid
.spi_mosi (buffered_spi_mosi), // conduit_end.mosi
.spi_clk (buffered_spi_clk), // .clk
.spi_miso (buffered_spi_miso), // .miso
.spi_cs (buffered_spi_cs), // .cs
.clock (clock_116_mhz_clk) // clock.clk
);
wasca_nios2_gen2_0 nios2_gen2_0 (
.clk (clock_116_mhz_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.d_address (nios2_gen2_0_data_master_address), // data_master.address
.d_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.d_read (nios2_gen2_0_data_master_read), // .read
.d_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_gen2_0_data_master_write), // .write
.d_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_gen2_0_instruction_master_address), // instruction_master.address
.i_read (nios2_gen2_0_instruction_master_read), // .read
.i_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.irq (nios2_gen2_0_irq_irq), // irq.irq
.debug_reset_request (nios2_gen2_0_debug_reset_request_reset), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
altera_onchip_flash #(
.INIT_FILENAME ("wasca_onchip_flash_0.hex"),
.INIT_FILENAME_SIM ("wasca_onchip_flash_0.dat"),
.DEVICE_FAMILY ("MAX 10"),
.PART_NAME ("10M08SAE144C8GES"),
.DEVICE_ID ("08"),
.SECTOR1_START_ADDR (0),
.SECTOR1_END_ADDR (4095),
.SECTOR2_START_ADDR (4096),
.SECTOR2_END_ADDR (8191),
.SECTOR3_START_ADDR (8192),
.SECTOR3_END_ADDR (29183),
.SECTOR4_START_ADDR (29184),
.SECTOR4_END_ADDR (44031),
.SECTOR5_START_ADDR (0),
.SECTOR5_END_ADDR (0),
.MIN_VALID_ADDR (0),
.MAX_VALID_ADDR (44031),
.MIN_UFM_VALID_ADDR (0),
.MAX_UFM_VALID_ADDR (44031),
.SECTOR1_MAP (1),
.SECTOR2_MAP (2),
.SECTOR3_MAP (3),
.SECTOR4_MAP (4),
.SECTOR5_MAP (0),
.ADDR_RANGE1_END_ADDR (44031),
.ADDR_RANGE1_OFFSET (512),
.ADDR_RANGE2_OFFSET (0),
.AVMM_DATA_ADDR_WIDTH (16),
.AVMM_DATA_DATA_WIDTH (32),
.AVMM_DATA_BURSTCOUNT_WIDTH (4),
.SECTOR_READ_PROTECTION_MODE (31),
.FLASH_SEQ_READ_DATA_COUNT (2),
.FLASH_ADDR_ALIGNMENT_BITS (1),
.FLASH_READ_CYCLE_MAX_INDEX (3),
.FLASH_RESET_CYCLE_MAX_INDEX (29),
.FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX (111),
.FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX (40603248),
.FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX (35382),
.PARALLEL_MODE (1),
.READ_AND_WRITE_MODE (0),
.WRAPPING_BURST_MODE (0),
.IS_DUAL_BOOT ("False"),
.IS_ERAM_SKIP ("True"),
.IS_COMPRESSED_IMAGE ("True")
) onchip_flash_0 (
.clock (clock_116_mhz_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // nreset.reset_n
.avmm_data_addr (mm_interconnect_0_onchip_flash_0_data_address), // data.address
.avmm_data_read (mm_interconnect_0_onchip_flash_0_data_read), // .read
.avmm_data_readdata (mm_interconnect_0_onchip_flash_0_data_readdata), // .readdata
.avmm_data_waitrequest (mm_interconnect_0_onchip_flash_0_data_waitrequest), // .waitrequest
.avmm_data_readdatavalid (mm_interconnect_0_onchip_flash_0_data_readdatavalid), // .readdatavalid
.avmm_data_burstcount (mm_interconnect_0_onchip_flash_0_data_burstcount), // .burstcount
.avmm_data_writedata (32'b00000000000000000000000000000000), // (terminated)
.avmm_data_write (1'b0), // (terminated)
.avmm_csr_addr (1'b0), // (terminated)
.avmm_csr_read (1'b0), // (terminated)
.avmm_csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.avmm_csr_write (1'b0), // (terminated)
.avmm_csr_readdata () // (terminated)
);
wasca_onchip_memory2_0 onchip_memory2_0 (
.clk (clock_116_mhz_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) reset_controller_0 (
.reset_in0 (nios2_gen2_0_debug_reset_request_reset), // reset_in0.reset
.reset_in1 (reset_controller_0_reset_in1_reset), // reset_in1.reset
.clk (clock_116_mhz_clk), // clk.clk
.reset_out (reset_controller_0_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
wasca_uart_0 uart_0 (
.clk (clock_116_mhz_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_0_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_0_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_0_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_0_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.dataavailable (), // .dataavailable
.readyfordata (), // .readyfordata
.rxd (uart_0_external_connection_rxd), // external_connection.export
.txd (uart_0_external_connection_txd), // .export
.irq (irq_mapper_receiver1_irq) // irq.irq
);
wasca_mm_interconnect_0 mm_interconnect_0 (
.altpll_1_c0_clk (clock_116_mhz_clk), // altpll_1_c0.clk
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // altpll_1_inclk_interface_reset_reset_bridge_in_reset.reset
.buffered_spi_0_reset_reset_bridge_in_reset_reset (nios2_gen2_0_debug_reset_request_reset), // buffered_spi_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_gen2_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_data_master_address (nios2_gen2_0_data_master_address), // nios2_gen2_0_data_master.address
.nios2_gen2_0_data_master_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.nios2_gen2_0_data_master_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.nios2_gen2_0_data_master_read (nios2_gen2_0_data_master_read), // .read
.nios2_gen2_0_data_master_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.nios2_gen2_0_data_master_write (nios2_gen2_0_data_master_write), // .write
.nios2_gen2_0_data_master_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.nios2_gen2_0_data_master_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.nios2_gen2_0_instruction_master_address (nios2_gen2_0_instruction_master_address), // nios2_gen2_0_instruction_master.address
.nios2_gen2_0_instruction_master_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.nios2_gen2_0_instruction_master_read (nios2_gen2_0_instruction_master_read), // .read
.nios2_gen2_0_instruction_master_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.abus_avalon_sdram_bridge_0_avalon_regs_address (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_address), // abus_avalon_sdram_bridge_0_avalon_regs.address
.abus_avalon_sdram_bridge_0_avalon_regs_write (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_write), // .write
.abus_avalon_sdram_bridge_0_avalon_regs_read (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_read), // .read
.abus_avalon_sdram_bridge_0_avalon_regs_readdata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdata), // .readdata
.abus_avalon_sdram_bridge_0_avalon_regs_writedata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_writedata), // .writedata
.abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid), // .readdatavalid
.abus_avalon_sdram_bridge_0_avalon_regs_waitrequest (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_waitrequest), // .waitrequest
.abus_avalon_sdram_bridge_0_avalon_sdram_address (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_address), // abus_avalon_sdram_bridge_0_avalon_sdram.address
.abus_avalon_sdram_bridge_0_avalon_sdram_write (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_write), // .write
.abus_avalon_sdram_bridge_0_avalon_sdram_read (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_read), // .read
.abus_avalon_sdram_bridge_0_avalon_sdram_readdata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdata), // .readdata
.abus_avalon_sdram_bridge_0_avalon_sdram_writedata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_writedata), // .writedata
.abus_avalon_sdram_bridge_0_avalon_sdram_byteenable (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_byteenable), // .byteenable
.abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid), // .readdatavalid
.abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest), // .waitrequest
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_address), // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave.address
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_write), // .write
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_read), // .read
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_readdata), // .readdata
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_writedata), // .writedata
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_byteenable), // .byteenable
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_waitrequest), // .waitrequest
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect (mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_chipselect), // .chipselect
.altpll_1_pll_slave_address (mm_interconnect_0_altpll_1_pll_slave_address), // altpll_1_pll_slave.address
.altpll_1_pll_slave_write (mm_interconnect_0_altpll_1_pll_slave_write), // .write
.altpll_1_pll_slave_read (mm_interconnect_0_altpll_1_pll_slave_read), // .read
.altpll_1_pll_slave_readdata (mm_interconnect_0_altpll_1_pll_slave_readdata), // .readdata
.altpll_1_pll_slave_writedata (mm_interconnect_0_altpll_1_pll_slave_writedata), // .writedata
.audio_0_avalon_audio_slave_address (mm_interconnect_0_audio_0_avalon_audio_slave_address), // audio_0_avalon_audio_slave.address
.audio_0_avalon_audio_slave_write (mm_interconnect_0_audio_0_avalon_audio_slave_write), // .write
.audio_0_avalon_audio_slave_read (mm_interconnect_0_audio_0_avalon_audio_slave_read), // .read
.audio_0_avalon_audio_slave_readdata (mm_interconnect_0_audio_0_avalon_audio_slave_readdata), // .readdata
.audio_0_avalon_audio_slave_writedata (mm_interconnect_0_audio_0_avalon_audio_slave_writedata), // .writedata
.audio_0_avalon_audio_slave_chipselect (mm_interconnect_0_audio_0_avalon_audio_slave_chipselect), // .chipselect
.buffered_spi_0_avalon_address (mm_interconnect_0_buffered_spi_0_avalon_address), // buffered_spi_0_avalon.address
.buffered_spi_0_avalon_write (mm_interconnect_0_buffered_spi_0_avalon_write), // .write
.buffered_spi_0_avalon_read (mm_interconnect_0_buffered_spi_0_avalon_read), // .read
.buffered_spi_0_avalon_readdata (mm_interconnect_0_buffered_spi_0_avalon_readdata), // .readdata
.buffered_spi_0_avalon_writedata (mm_interconnect_0_buffered_spi_0_avalon_writedata), // .writedata
.buffered_spi_0_avalon_readdatavalid (mm_interconnect_0_buffered_spi_0_avalon_readdatavalid), // .readdatavalid
.buffered_spi_0_avalon_waitrequest (mm_interconnect_0_buffered_spi_0_avalon_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // nios2_gen2_0_debug_mem_slave.address
.nios2_gen2_0_debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.nios2_gen2_0_debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.nios2_gen2_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.nios2_gen2_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.nios2_gen2_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.nios2_gen2_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.onchip_flash_0_data_address (mm_interconnect_0_onchip_flash_0_data_address), // onchip_flash_0_data.address
.onchip_flash_0_data_read (mm_interconnect_0_onchip_flash_0_data_read), // .read
.onchip_flash_0_data_readdata (mm_interconnect_0_onchip_flash_0_data_readdata), // .readdata
.onchip_flash_0_data_burstcount (mm_interconnect_0_onchip_flash_0_data_burstcount), // .burstcount
.onchip_flash_0_data_readdatavalid (mm_interconnect_0_onchip_flash_0_data_readdatavalid), // .readdatavalid
.onchip_flash_0_data_waitrequest (mm_interconnect_0_onchip_flash_0_data_waitrequest), // .waitrequest
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.uart_0_s1_address (mm_interconnect_0_uart_0_s1_address), // uart_0_s1.address
.uart_0_s1_write (mm_interconnect_0_uart_0_s1_write), // .write
.uart_0_s1_read (mm_interconnect_0_uart_0_s1_read), // .read
.uart_0_s1_readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.uart_0_s1_writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.uart_0_s1_begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.uart_0_s1_chipselect (mm_interconnect_0_uart_0_s1_chipselect) // .chipselect
);
wasca_irq_mapper irq_mapper (
.clk (clock_116_mhz_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.sender_irq (nios2_gen2_0_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (reset_controller_0_reset_out_reset), // reset_in0.reset
.clk (clock_116_mhz_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("both"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (reset_controller_0_reset_out_reset), // reset_in0.reset
.clk (clock_116_mhz_clk), // clk.clk
.reset_out (), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
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