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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_hd__udp_dff_p.v"
`celldefine
module sky130_fd_sc_hd__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file pezhman_mem.v when simulating
// the core, pezhman_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module pezhman_mem(
clka,
addra,
douta
);
input clka;
input [14 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(15),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(1),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("pezhman_mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32768),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(32768),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_pipe_reset.v
// Version : 1.3
//------------------------------------------------------------------------------
// Filename : pipe_reset.v
// Description : PIPE Reset Module for 7 Series Transceiver
// Version : 11.2
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Reset Module -------------------------------------------------
module pcie_7x_v1_3_pipe_reset #
(
//---------- Global ------------------------------------
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable
parameter PCIE_LANE = 1, // PCIe number of lanes
//---------- Local -------------------------------------
parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max
parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK
)
(
//---------- Input -------------------------------------
input RST_CLK,
input RST_RXUSRCLK,
input RST_DCLK,
input RST_RST_N,
input [PCIE_LANE-1:0] RST_CPLLLOCK,
input RST_QPLL_IDLE,
input [PCIE_LANE-1:0] RST_RATE_IDLE,
input [PCIE_LANE-1:0] RST_RXCDRLOCK,
input RST_MMCM_LOCK,
input [PCIE_LANE-1:0] RST_RESETDONE,
input [PCIE_LANE-1:0] RST_PHYSTATUS,
input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
//---------- Output ------------------------------------
output RST_CPLLRESET,
output RST_CPLLPD,
output RST_RXUSRCLK_RESET,
output RST_DCLK_RESET,
output RST_GTRESET,
output RST_USERRDY,
output RST_TXSYNC_START,
output RST_IDLE,
output [10:0] RST_FSM
);
//---------- Input Register ----------------------------
reg [PCIE_LANE-1:0] cplllock_reg1;
reg qpll_idle_reg1;
reg [PCIE_LANE-1:0] rate_idle_reg1;
reg [PCIE_LANE-1:0] rxcdrlock_reg1;
reg mmcm_lock_reg1;
reg [PCIE_LANE-1:0] resetdone_reg1;
reg [PCIE_LANE-1:0] phystatus_reg1;
reg [PCIE_LANE-1:0] txsync_done_reg1;
reg [PCIE_LANE-1:0] cplllock_reg2;
reg qpll_idle_reg2;
reg [PCIE_LANE-1:0] rate_idle_reg2;
reg [PCIE_LANE-1:0] rxcdrlock_reg2;
reg mmcm_lock_reg2;
reg [PCIE_LANE-1:0] resetdone_reg2;
reg [PCIE_LANE-1:0] phystatus_reg2;
reg [PCIE_LANE-1:0] txsync_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 5:0] cfg_wait_cnt = 6'd0;
//---------- Output Register ---------------------------
reg cpllreset = 1'd0;
reg cpllpd = 1'd0;
reg rxusrclk_rst_reg1 = 1'd0;
reg rxusrclk_rst_reg2 = 1'd0;
reg dclk_rst_reg1 = 1'd0;
reg dclk_rst_reg2 = 1'd0;
reg gtreset = 1'd0;
reg userrdy = 1'd0;
reg [10:0] fsm = 11'd2;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 11'b00000000001;
localparam FSM_CFG_WAIT = 11'b00000000010;
localparam FSM_CPLLRESET = 11'b00000000100;
localparam FSM_CPLLLOCK = 11'b00000001000;
localparam FSM_DRP = 11'b00000010000;
localparam FSM_GTRESET = 11'b00000100000;
localparam FSM_MMCM_LOCK = 11'b00001000000;
localparam FSM_RESETDONE = 11'b00010000000;
localparam FSM_CPLL_PD = 11'b00100000000;
localparam FSM_TXSYNC_START = 11'b01000000000;
localparam FSM_TXSYNC_DONE = 11'b10000000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
//---------- 1st Stage FF --------------------------
cplllock_reg1 <= {PCIE_LANE{1'd0}};
qpll_idle_reg1 <= 1'd0;
rate_idle_reg1 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg1 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg1 <= 1'd0;
resetdone_reg1 <= {PCIE_LANE{1'd0}};
phystatus_reg1 <= {PCIE_LANE{1'd0}};
txsync_done_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
cplllock_reg2 <= {PCIE_LANE{1'd0}};
qpll_idle_reg2 <= 1'd0;
rate_idle_reg2 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg2 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg2 <= 1'd0;
resetdone_reg2 <= {PCIE_LANE{1'd0}};
phystatus_reg2 <= {PCIE_LANE{1'd0}};
txsync_done_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
cplllock_reg1 <= RST_CPLLLOCK;
qpll_idle_reg1 <= RST_QPLL_IDLE;
rate_idle_reg1 <= RST_RATE_IDLE;
rxcdrlock_reg1 <= RST_RXCDRLOCK;
mmcm_lock_reg1 <= RST_MMCM_LOCK;
resetdone_reg1 <= RST_RESETDONE;
phystatus_reg1 <= RST_PHYSTATUS;
txsync_done_reg1 <= RST_TXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
cplllock_reg2 <= cplllock_reg1;
qpll_idle_reg2 <= qpll_idle_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
resetdone_reg2 <= resetdone_reg1;
phystatus_reg2 <= phystatus_reg1;
txsync_done_reg2 <= txsync_done_reg1;
end
end
//---------- Configuration Reset Wait Counter ----------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
cfg_wait_cnt <= 6'd0;
else
//---------- Increment Configuration Reset Wait Counter
if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
//---------- Hold Configuration Reset Wait Counter -
else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt;
//---------- Reset Configuration Reset Wait Counter
else
cfg_wait_cnt <= 6'd0;
end
//---------- PIPE Reset FSM ----------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
end
//---------- Wait for Configuration Reset Delay ---
FSM_CFG_WAIT :
begin
fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_CPLLRESET : FSM_CFG_WAIT);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Hold CPLL and GTX Channel in Reset ----
FSM_CPLLRESET :
begin
fsm <= ((&(~cplllock_reg2) && (&(~resetdone_reg2))) ? FSM_CPLLLOCK : FSM_CPLLRESET);
cpllreset <= 1'd1;
cpllpd <= cpllpd;
gtreset <= 1'd1;
userrdy <= userrdy;
end
//---------- Wait for CPLL Lock --------------------
FSM_CPLLLOCK :
begin
fsm <= (&cplllock_reg2 ? FSM_DRP : FSM_CPLLLOCK);
cpllreset <= 1'd0;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP Done to Setup Gen1 -------
FSM_DRP :
begin
fsm <= (&rate_idle_reg2 ? FSM_GTRESET : FSM_DRP);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Release GTX Channel Reset -------------
FSM_GTRESET :
begin
fsm <= FSM_MMCM_LOCK;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= 1'b0;
userrdy <= userrdy;
end
//---------- Wait for MMCM and RX CDR Lock ---------
FSM_MMCM_LOCK :
begin
if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)) && (qpll_idle_reg2 || (PCIE_PLL_SEL == "CPLL")))
begin
fsm <= FSM_RESETDONE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= 1'd1;
end
else
begin
fsm <= FSM_MMCM_LOCK;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= 1'd0;
end
end
//---------- Wait for [TX/RX]RESETDONE and PHYSTATUS
FSM_RESETDONE :
begin
fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_CPLL_PD : FSM_RESETDONE);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Power-Down CPLL if QPLL is Used for Gen1/Gen2
FSM_CPLL_PD :
begin
fsm <= ((PCIE_TXBUF_EN == "TRUE") ? FSM_IDLE : FSM_TXSYNC_START);
cpllreset <= cpllreset;
cpllpd <= (PCIE_PLL_SEL == "QPLL");
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START :
begin
fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE :
begin
fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
endcase
end
end
//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
always @ (posedge RST_RXUSRCLK)
begin
if (cpllreset)
begin
rxusrclk_rst_reg1 <= 1'd1;
rxusrclk_rst_reg2 <= 1'd1;
end
else
begin
rxusrclk_rst_reg1 <= 1'd0;
rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
end
end
//---------- DCLK Reset Synchronizer -------------------------------------------
always @ (posedge RST_DCLK)
begin
if (cpllreset)
begin
dclk_rst_reg1 <= 1'd1;
dclk_rst_reg2 <= 1'd1;
end
else
begin
dclk_rst_reg1 <= 1'd0;
dclk_rst_reg2 <= dclk_rst_reg1;
end
end
//---------- PIPE Reset Output -------------------------------------------------
assign RST_CPLLRESET = cpllreset;
assign RST_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
assign RST_DCLK_RESET = dclk_rst_reg2;
assign RST_GTRESET = gtreset;
assign RST_USERRDY = userrdy;
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RST_IDLE = (fsm == FSM_IDLE);
assign RST_FSM = fsm;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__TAPVGND2_FUNCTIONAL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvgnd2 (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND2_FUNCTIONAL_V |
// bsg_barrier
//
// Light-weight configurable wire/logic efficient barrier.
//
// This barrier works with any nearest-neighbor connected topology (e.g., chain, torus, mesh, ruche)
// with bidirectional links.
//
// This allows all of the node hardware to be identical, but configured according into a number
// of subgraphs each capable of doing an independent barrier.
//
// Each node will have a local node input (Pi) and output (Po), and then a bunch of
// connections to neighbor links. In the normal state, Pi and Po match. To enter the barrier,
// a node will flip the Pi bit (i.e. via XOR). Each node has a bitmask of incoming links that
// must all match the new barrier value before the output link outputs the barrier value.
// The barrier value propagates through the network until you get to the root node. The root node
// completes the barrier, usually pulling in links from every direction, going into a special flop
// which is the barrier root. Then the barrier root is broadcast across the reverse links specified
// by the incoming link list, eventually setting all of the Po links. As soon as a node receives the
// broadcast, it flips its "sense bit" which says whether a 1 or 0 is the new barrier target value.
//
// In a RISC-V based system, the approach would be
//
// <setup>:
//
// mtcsr BARCFG, 8'b <this node's output id selector> 24'b <this node's input bitmask>
//
// <execution>:
//
// memory fence # if needed, stall until all memory operations done
// barsend # flip Pi bit (bit 1) of BAR csr (note: Po bit is mapped to bit 2 of the register)
// barreceive # stall in decode until Pi==Po
//
// Here is an example barrier for a Ruche factor 3 topology (you would configure the letters on the left of
// the -> as the input mask and the letter on the right as the output direction). Note R is the "Root".
//
// 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.
// P->E P->E P->E PW->E PW->E PW->E PW->e PWwE->S PWEe->S PW->w PE->W PE->W PE->W P->W P->W P->W 0
// P->E P->E P->E PW->E PW->E PW->E PW->e NPWwE->S NPWEe->S PW->w PE->W PE->W PE->W P->W P->W P->W 1
// P->E P->E P->E PW->E PW->E PW->E PW->e NPWwE->S NPWEe->S PW->w PE->W PE->W PE->W P->W P->W P->W 2
// P->E P->E P->E PW->E PW->E PW->E PW->e NPWwE->e NPWEwe->S PW->w PE->W PE->W PE->W P->W P->W P->W 3
//
// P->E P->E P->E PW->E PW->E PW->E PW->e SPWeE->e NSPWEwe->R PW->w PE->W PE->W PE->W P->W P->W P->W 4
// P->E P->E P->E PW->E PW->E PW->E PW->e SPWwE->N SPWEe->N PW->w PE->W PE->W PE->W P->W P->W P->W 5
// P->E P->E P->E PW->E PW->E PW->E PW->e SPWwE->N SPWEe->N PW->w PE->W PE->W PE->W P->W P->W P->W 6
// P->E P->E P->E PW->E PW->E PW->E PW->e PWwE->N PWEe->N PW->w PE->W PE->W PE->W P->W P->W P->W 7
//
//
// Context switching. The barrier is context switchable. To context switch the barrier, you interrupt all of the relevant tiles
// and wait long enough for any successful barrier to fully propagate. At this point, using BAR CSR, you can determine if you are either barrier-completed
// (Pi = Po) for all tiles or barrier in progress (Pi != Po for some subset of nodes.) For barrier in progress, we can record all of the nodes
// that have barrier in progress, and then reset the corresponding Pi bit to clear the in progress barrier.
//
module bsg_barrier
#(`BSG_INV_PARAM(dirs_p),lg_dirs_lp=`BSG_SAFE_CLOG2(dirs_p+1))
(
input clk_i
,input reset_i
// to remote nodes
,input [dirs_p-1:0] data_i // late
,output [dirs_p-1:0] data_o // early-ish
//
// control of the barrier:
//
// which inputs we will gather from
// and which outputs we send the gather output to
// and for the broadcast phase, the opposite.
//
// usually comes from a CSR (or bsg_tag)
//
,input [dirs_p-1:0] src_r_i
,input [lg_dirs_lp-1:0] dest_r_i
);
wire [dirs_p:0] data_r;
wire activate_n;
wire data_broadcast_in = data_r[dest_r_i];
wire sense_n, sense_r;
wire gather_and = & (~src_r_i | data_r[dirs_p-1:0]); // true if all selected bits are set to 1
wire gather_or = | (src_r_i & data_r[dirs_p-1:0]); // false if all selected bits are set to 0
// the barrier should go forward, based on the sense bit, if we are either all 0 or all 1.
wire gather_out = sense_r ? gather_or : gather_and;
//
// flip sense bit if we are receiving the incoming broadcast
// we are relying on the P bit still being high at the leaves
// sense_r broadcast_in sense_n
// 0 0 0
// 0 1 1
// 1 1 1
// 1 0 0
// if we see a transition on data_broadcast_in, then we have completed the barrier
assign sense_n = data_broadcast_in;
bsg_dff_reset #(.width_p(dirs_p+2)) dff
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i({activate_n, data_i[dirs_p-1:0], sense_n})
,.data_o({data_r[dirs_p], data_r[dirs_p-1:0], sense_r})
);
// this is simply a matter of propagating the value in question
wire [dirs_p-1:0] data_broadcast_out = { dirs_p { data_broadcast_in } } & src_r_i;
// here we propagate the gather_out value, either to network outputs, or to the local activate reg (at the root of the broadcast)
wire [dirs_p:0] dest_decode = 1 << (dest_r_i);
wire [dirs_p:0] data_gather_out = dest_decode & { (dirs_p+1) { gather_out } };
assign data_o = data_broadcast_out | data_gather_out[dirs_p-1:0];
assign activate_n = data_gather_out[dirs_p];
localparam debug_p = 0;
if (debug_p)
always @(negedge clk_i)
$display("%d: %m %b %b %b %b %b %b", $time, gather_and, gather_or, gather_out, sense_n, data_i, data_o);
endmodule
`BSG_ABSTRACT_MODULE(bsg_barrier);
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_pktout_mux.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_pktout_mux -- Format J_ADTYPE and J_AD data from various sources.
// _____________________________________________________________________________
//
`include "sys.h"
`include "jbi.h"
module jbi_pktout_mux (/*AUTOARG*/
// Outputs
jbi_io_j_adtype, jbi_io_j_ad, jbi_io_j_adp,
// Inputs
sel_queue, sel_j_adbus, sct0rdq_install_state, sct0rdq_unmapped_error,
sct0rdq_jid, sct0rdq_data, sct0rdq_ue_err, sct1rdq_install_state,
sct1rdq_unmapped_error, sct1rdq_jid, sct1rdq_data, sct1rdq_ue_err,
sct2rdq_install_state, sct2rdq_unmapped_error, sct2rdq_jid, sct2rdq_data,
sct2rdq_ue_err, sct3rdq_install_state, sct3rdq_unmapped_error, sct3rdq_jid,
sct3rdq_data, sct3rdq_ue_err, ncio_pio_ue, ncio_pio_be, ncio_pio_ad,
ncio_mondo_agnt_id, ncio_mondo_cpu_id, dbg_data, unused_jid, inj_err_j_ad,
csr_jbi_debug_info_enb, thread_id, sct0rdq_trans_count, sct1rdq_trans_count,
sct2rdq_trans_count, sct3rdq_trans_count, ncio_prqq_level, ncio_makq_level,
clk
);
`include "jbi_mout.h"
// Select.
input [2:0] sel_queue;
input [3:0] sel_j_adbus;
// Input sources
// SCT0 RDQ.
input sct0rdq_install_state;
input sct0rdq_unmapped_error;
input [5:0] sct0rdq_jid;
input [127:0] sct0rdq_data;
input sct0rdq_ue_err;
// SCT1 RDQ.
input sct1rdq_install_state;
input sct1rdq_unmapped_error;
input [5:0] sct1rdq_jid;
input [127:0] sct1rdq_data;
input sct1rdq_ue_err;
// SCT2 RDQ.
input sct2rdq_install_state;
input sct2rdq_unmapped_error;
input [5:0] sct2rdq_jid;
input [127:0] sct2rdq_data;
input sct2rdq_ue_err;
// SCT3 RDQ.
input sct3rdq_install_state;
input sct3rdq_unmapped_error;
input [5:0] sct3rdq_jid;
input [127:0] sct3rdq_data;
input sct3rdq_ue_err;
// PIO RQQ.
input ncio_pio_ue;
input [15:0] ncio_pio_be;
input [63:0] ncio_pio_ad;
// PIO ACKQ.
input [4:0] ncio_mondo_agnt_id;
input [4:0] ncio_mondo_cpu_id;
// DBGQ.
input [127:0] dbg_data;
// YID-to-JID Translation.
input [5:0] unused_jid;
// J_ADTYPE, J_AD, J_ADP busses.
output [7:0] jbi_io_j_adtype;
output [127:0] jbi_io_j_ad;
output [3:0] jbi_io_j_adp;
// Error injection.
input [3:0] inj_err_j_ad; // Inject an error on the J_AD[] (bit3=J_AD[96], bit2=J_AD[64], bit1=J_AD[32], bit0=J_AD[0]).
// Debug Info.
input csr_jbi_debug_info_enb; // Put these data fields in high half of JBus Address Cycles.
input [4:0] thread_id;
input [3:0] sct0rdq_trans_count;
input [3:0] sct1rdq_trans_count;
input [3:0] sct2rdq_trans_count;
input [3:0] sct3rdq_trans_count;
input [4:0] ncio_prqq_level;
input [4:0] ncio_makq_level;
// Clock.
input clk;
// Wires and Regs.
wire sct0rdq_ue_err_p1;
wire sct1rdq_ue_err_p1;
wire sct2rdq_ue_err_p1;
wire sct3rdq_ue_err_p1;
reg [127:0] j_ad;
reg [7:0] jbi_io_j_adtype;
// Preformatting Debug Info field.
wire [111:64] debug_info = { 11'b000_0000_0000, thread_id[4:0], sct0rdq_trans_count[3:0], sct1rdq_trans_count[3:0], sct2rdq_trans_count[3:0], sct3rdq_trans_count[3:0],
3'b000, ncio_prqq_level[4:0], 3'b000, ncio_makq_level[4:0] };
// IDLE Output formatting.
//
wire [7:0] idle_adtype = { 8'hff };
wire [127:0] idle_ad = csr_jbi_debug_info_enb? { 16'hffff, debug_info[111:64], 64'hffff_ffff_ffff_ffff }:
{ 64'hffff_ffff_ffff_ffff, 64'hffff_ffff_ffff_ffff };
// SCT0 RDQ Output formatting.
//
// RD16
wire [3:0] sct0rdq_target_aid = sct0rdq_jid[5:2];
wire [1:0] sct0rdq_trans_id = sct0rdq_jid[1:0];
wire [7:0] sct0rdq_rd16_adtype = { 2'h2, sct0rdq_target_aid, sct0rdq_trans_id };
wire [127:0] sct0rdq_rd16_ad = { sct0rdq_data[127:0] };
// RD64
wire [2:0] sct0rdq_state = (sct0rdq_install_state == `JBI_SCTAG_TAG_INSTALL_INVALID)? INSTALL_INVALID:
INSTALL_SHARED;
wire [1:0] sct0rdq_uece_err = { sct0rdq_ue_err, 1'b0 };
wire [1:0] sct0rdq_uece_err_p1 = { sct0rdq_ue_err_p1, 1'b0 };
dff_ns sct0rdq_ue_err_p1_reg (.din(sct0rdq_ue_err), .q(sct0rdq_ue_err_p1), .clk(clk));
//
wire [7:0] sct0rdq_rd64_0_adtype = { 2'h1, sct0rdq_target_aid, sct0rdq_trans_id };
wire [127:0] sct0rdq_rd64_0_ad = { sct0rdq_data[127:0] };
//
wire [7:0] sct0rdq_rd64_1_adtype = { 1'h0, sct0rdq_uece_err_p1, sct0rdq_uece_err, sct0rdq_state };
wire [127:0] sct0rdq_rd64_1_ad = { sct0rdq_data[127:0] };
//
wire [7:0] sct0rdq_rd64_2_adtype = { 3'h0, sct0rdq_uece_err, 3'h0 };
wire [127:0] sct0rdq_rd64_2_ad = { sct0rdq_data[127:0] };
//
wire [7:0] sct0rdq_rd64_3_adtype = { 3'h0, sct0rdq_uece_err, 3'h0 };
wire [127:0] sct0rdq_rd64_3_ad = { sct0rdq_data[127:0] };
// RDER
wire [7:0] sct0rdq_rder_adtype = { 2'h0, sct0rdq_target_aid, sct0rdq_trans_id };
wire [2:0] sct0rdq_rder_error = (sct0rdq_unmapped_error)? RDER_UNMAPPED: RDER_BUS_ERROR;
wire [127:0] sct0rdq_rder_ad = { sct0rdq_data[127:3], sct0rdq_rder_error[2:0] };
// SCT1 RDQ Output formatting.
//
// RD16
wire [3:0] sct1rdq_target_aid = sct1rdq_jid[5:2];
wire [1:0] sct1rdq_trans_id = sct1rdq_jid[1:0];
wire [7:0] sct1rdq_rd16_adtype = { 2'h2, sct1rdq_target_aid, sct1rdq_trans_id };
wire [127:0] sct1rdq_rd16_ad = { sct1rdq_data[127:0] };
// RD64
wire [2:0] sct1rdq_state = (sct1rdq_install_state == `JBI_SCTAG_TAG_INSTALL_INVALID)? INSTALL_INVALID:
INSTALL_SHARED;
wire [1:0] sct1rdq_uece_err = { sct1rdq_ue_err, 1'b0 };
wire [1:0] sct1rdq_uece_err_p1 = { sct1rdq_ue_err_p1, 1'b0 };
dff_ns sct1rdq_ue_err_p1_reg (.din(sct1rdq_ue_err), .q(sct1rdq_ue_err_p1), .clk(clk));
//
wire [7:0] sct1rdq_rd64_0_adtype = { 2'h1, sct1rdq_target_aid, sct1rdq_trans_id };
wire [127:0] sct1rdq_rd64_0_ad = { sct1rdq_data[127:0] };
//
wire [7:0] sct1rdq_rd64_1_adtype = { 1'h0, sct1rdq_uece_err_p1, sct1rdq_uece_err, sct1rdq_state };
wire [127:0] sct1rdq_rd64_1_ad = { sct1rdq_data[127:0] };
//
wire [7:0] sct1rdq_rd64_2_adtype = { 3'h0, sct1rdq_uece_err, 3'h0 };
wire [127:0] sct1rdq_rd64_2_ad = { sct1rdq_data[127:0] };
//
wire [7:0] sct1rdq_rd64_3_adtype = { 3'h0, sct1rdq_uece_err, 3'h0 };
wire [127:0] sct1rdq_rd64_3_ad = { sct1rdq_data[127:0] };
// RDER
wire [7:0] sct1rdq_rder_adtype = { 2'h0, sct1rdq_target_aid, sct1rdq_trans_id };
wire [2:0] sct1rdq_rder_error = (sct1rdq_unmapped_error)? RDER_UNMAPPED: RDER_BUS_ERROR;
wire [127:0] sct1rdq_rder_ad = { sct1rdq_data[127:3], sct1rdq_rder_error[2:0] };
// SCT2 RDQ Output formatting.
//
// RD16
wire [3:0] sct2rdq_target_aid = sct2rdq_jid[5:2];
wire [1:0] sct2rdq_trans_id = sct2rdq_jid[1:0];
wire [7:0] sct2rdq_rd16_adtype = { 2'h2, sct2rdq_target_aid, sct2rdq_trans_id };
wire [127:0] sct2rdq_rd16_ad = { sct2rdq_data[127:0] };
// RD64
wire [2:0] sct2rdq_state = (sct2rdq_install_state == `JBI_SCTAG_TAG_INSTALL_INVALID)? INSTALL_INVALID:
INSTALL_SHARED;
wire [1:0] sct2rdq_uece_err = { sct2rdq_ue_err, 1'b0 };
wire [1:0] sct2rdq_uece_err_p1 = { sct2rdq_ue_err_p1, 1'b0 };
dff_ns sct2rdq_ue_err_p1_reg (.din(sct2rdq_ue_err), .q(sct2rdq_ue_err_p1), .clk(clk));
//
wire [7:0] sct2rdq_rd64_0_adtype = { 2'h1, sct2rdq_target_aid, sct2rdq_trans_id };
wire [127:0] sct2rdq_rd64_0_ad = { sct2rdq_data[127:0] };
//
wire [7:0] sct2rdq_rd64_1_adtype = { 1'h0, sct2rdq_uece_err_p1, sct2rdq_uece_err, sct2rdq_state };
wire [127:0] sct2rdq_rd64_1_ad = { sct2rdq_data[127:0] };
//
wire [7:0] sct2rdq_rd64_2_adtype = { 3'h0, sct2rdq_uece_err, 3'h0 };
wire [127:0] sct2rdq_rd64_2_ad = { sct2rdq_data[127:0] };
//
wire [7:0] sct2rdq_rd64_3_adtype = { 3'h0, sct2rdq_uece_err, 3'h0 };
wire [127:0] sct2rdq_rd64_3_ad = { sct2rdq_data[127:0] };
// RDER
wire [7:0] sct2rdq_rder_adtype = { 2'h0, sct2rdq_target_aid, sct2rdq_trans_id };
wire [2:0] sct2rdq_rder_error = (sct2rdq_unmapped_error)? RDER_UNMAPPED: RDER_BUS_ERROR;
wire [127:0] sct2rdq_rder_ad = { sct2rdq_data[127:3], sct2rdq_rder_error[2:0] };
// SCT3 RDQ Output formatting.
//
// RD16
wire [3:0] sct3rdq_target_aid = sct3rdq_jid[5:2];
wire [1:0] sct3rdq_trans_id = sct3rdq_jid[1:0];
wire [7:0] sct3rdq_rd16_adtype = { 2'h2, sct3rdq_target_aid[3:0], sct3rdq_trans_id[1:0] };
wire [127:0] sct3rdq_rd16_ad = { sct3rdq_data[127:0] };
// RD64
wire [2:0] sct3rdq_state = (sct3rdq_install_state == `JBI_SCTAG_TAG_INSTALL_INVALID)? INSTALL_INVALID:
INSTALL_SHARED;
wire [1:0] sct3rdq_uece_err = { sct3rdq_ue_err, 1'b0 };
wire [1:0] sct3rdq_uece_err_p1 = { sct3rdq_ue_err_p1, 1'b0 };
dff_ns sct3rdq_ue_err_p1_reg (.din(sct3rdq_ue_err), .q(sct3rdq_ue_err_p1), .clk(clk));
//
wire [7:0] sct3rdq_rd64_0_adtype = { 2'h1, sct3rdq_target_aid[3:0], sct3rdq_trans_id[1:0] };
wire [127:0] sct3rdq_rd64_0_ad = { sct3rdq_data[127:0] };
//
wire [7:0] sct3rdq_rd64_1_adtype = { 1'h0, sct3rdq_uece_err_p1, sct3rdq_uece_err, sct3rdq_state };
wire [127:0] sct3rdq_rd64_1_ad = { sct3rdq_data[127:0] };
//
wire [7:0] sct3rdq_rd64_2_adtype = { 3'h0, sct3rdq_uece_err, 3'h0 };
wire [127:0] sct3rdq_rd64_2_ad = { sct3rdq_data[127:0] };
//
wire [7:0] sct3rdq_rd64_3_adtype = { 3'h0, sct3rdq_uece_err, 3'h0 };
wire [127:0] sct3rdq_rd64_3_ad = { sct3rdq_data[127:0] };
// RDER
wire [7:0] sct3rdq_rder_adtype = { 2'h0, sct3rdq_target_aid, sct3rdq_trans_id };
wire [2:0] sct3rdq_rder_error = (sct3rdq_unmapped_error)? RDER_UNMAPPED: RDER_BUS_ERROR;
wire [127:0] sct3rdq_rder_ad = { sct3rdq_data[127:3], sct3rdq_rder_error[2:0] };
// PIO RQQ Output formatting.
//
// NCRD
wire [7:0] piorqq_ncrd_adtype = { 2'h3, unused_jid[5:2], unused_jid[1:0] };
wire [127:0] piorqq_ncrd_ad = csr_jbi_debug_info_enb? { ncio_pio_be[15:0], debug_info[111:64], ncio_pio_be[15:0], TRANS_NCRD, ncio_pio_ad[42:0] }:
{ ncio_pio_be[15:0], TRANS_NCRD, ncio_pio_ad[42:0], ncio_pio_be[15:0], TRANS_NCRD, ncio_pio_ad[42:0] };
// NCWR
wire [7:0] piorqq_ncwr_0_adtype = { 2'h3, 4'h0, 2'h0 };
wire [127:0] piorqq_ncwr_0_ad = csr_jbi_debug_info_enb? { ncio_pio_be[15:0], debug_info[111:64], ncio_pio_be[15:0], TRANS_NCWR, ncio_pio_ad[42:0] }:
{ ncio_pio_be[15:0], TRANS_NCWR, ncio_pio_ad[42:0], ncio_pio_be[15:0], TRANS_NCWR, ncio_pio_ad[42:0] };
//
wire [7:0] piorqq_ncwr_1_adtype = { 3'h0, ncio_pio_ue, 1'h0, 3'h0 };
wire [127:0] piorqq_ncwr_1_ad = { ncio_pio_ad[63:0], ncio_pio_ad[63:0] };
// PIO ACKQ Output formatting.
//
// INTACK
wire [4:0] pioackq_target_aid = ncio_mondo_agnt_id;
wire [4:0] pioackq_source_aid = ncio_mondo_cpu_id;
//
wire [7:0] pioackq_intack_adtype = { 2'h3, 4'h0, 2'h0 };
wire [127:0] pioackq_intack_ad = csr_jbi_debug_info_enb? { 16'h0000, debug_info[111:64],
16'h0000, TRANS_INTACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000 }:
{ 16'h0000, TRANS_INTACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000,
16'h0000, TRANS_INTACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000 };
// INTNACK
wire [7:0] pioackq_intnack_adtype = { 2'h3, 4'h0, 2'h0 };
wire [127:0] pioackq_intnack_ad = csr_jbi_debug_info_enb? { 16'h0000, debug_info[111:64],
16'h0000, TRANS_INTNACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000 }:
{ 16'h0000, TRANS_INTNACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000,
16'h0000, TRANS_INTNACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000 };
// DBGQ
wire [3:0] dbgq_target_aid = 4'h4;
wire [1:0] dbgq_trans_id = 2'h0;
wire [7:0] dbgq_rd16_adtype = { 2'h2, dbgq_target_aid[3:0], dbgq_trans_id[1:0] };
wire [127:0] dbgq_rd16_ad = { dbg_data[127:0] };
// Packet assembly multiplexer.
always @(/*AS*/dbgq_rd16_ad or dbgq_rd16_adtype or idle_ad or idle_adtype
or pioackq_intack_ad or pioackq_intack_adtype or pioackq_intnack_ad
or pioackq_intnack_adtype or piorqq_ncrd_ad or piorqq_ncrd_adtype
or piorqq_ncwr_0_ad or piorqq_ncwr_0_adtype or piorqq_ncwr_1_ad
or piorqq_ncwr_1_adtype or sct0rdq_rd16_ad or sct0rdq_rd16_adtype
or sct0rdq_rd64_0_ad or sct0rdq_rd64_0_adtype or sct0rdq_rd64_1_ad
or sct0rdq_rd64_1_adtype or sct0rdq_rd64_2_ad
or sct0rdq_rd64_2_adtype or sct0rdq_rd64_3_ad
or sct0rdq_rd64_3_adtype or sct0rdq_rder_ad or sct0rdq_rder_adtype
or sct1rdq_rd16_ad or sct1rdq_rd16_adtype or sct1rdq_rd64_0_ad
or sct1rdq_rd64_0_adtype or sct1rdq_rd64_1_ad
or sct1rdq_rd64_1_adtype or sct1rdq_rd64_2_ad
or sct1rdq_rd64_2_adtype or sct1rdq_rd64_3_ad
or sct1rdq_rd64_3_adtype or sct1rdq_rder_ad or sct1rdq_rder_adtype
or sct2rdq_rd16_ad or sct2rdq_rd16_adtype or sct2rdq_rd64_0_ad
or sct2rdq_rd64_0_adtype or sct2rdq_rd64_1_ad
or sct2rdq_rd64_1_adtype or sct2rdq_rd64_2_ad
or sct2rdq_rd64_2_adtype or sct2rdq_rd64_3_ad
or sct2rdq_rd64_3_adtype or sct2rdq_rder_ad or sct2rdq_rder_adtype
or sct3rdq_rd16_ad or sct3rdq_rd16_adtype or sct3rdq_rd64_0_ad
or sct3rdq_rd64_0_adtype or sct3rdq_rd64_1_ad
or sct3rdq_rd64_1_adtype or sct3rdq_rd64_2_ad
or sct3rdq_rd64_2_adtype or sct3rdq_rd64_3_ad
or sct3rdq_rd64_3_adtype or sct3rdq_rder_ad or sct3rdq_rder_adtype
or sel_j_adbus or sel_queue) begin
casex ({ sel_queue, sel_j_adbus })
{ LRQ_X, SEL_IDLE }: { jbi_io_j_adtype, j_ad } = { idle_adtype, idle_ad };
{ LRQ_SCT0RDQ, SEL_RD16 }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rd16_adtype, sct0rdq_rd16_ad };
{ LRQ_SCT0RDQ, SEL_RD64_0 }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rd64_0_adtype, sct0rdq_rd64_0_ad };
{ LRQ_SCT0RDQ, SEL_RD64_1 }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rd64_1_adtype, sct0rdq_rd64_1_ad };
{ LRQ_SCT0RDQ, SEL_RD64_2 }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rd64_2_adtype, sct0rdq_rd64_2_ad };
{ LRQ_SCT0RDQ, SEL_RD64_3 }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rd64_3_adtype, sct0rdq_rd64_3_ad };
{ LRQ_SCT0RDQ, SEL_RDER }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rder_adtype, sct0rdq_rder_ad };
{ LRQ_SCT1RDQ, SEL_RD16 }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rd16_adtype, sct1rdq_rd16_ad };
{ LRQ_SCT1RDQ, SEL_RD64_0 }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rd64_0_adtype, sct1rdq_rd64_0_ad };
{ LRQ_SCT1RDQ, SEL_RD64_1 }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rd64_1_adtype, sct1rdq_rd64_1_ad };
{ LRQ_SCT1RDQ, SEL_RD64_2 }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rd64_2_adtype, sct1rdq_rd64_2_ad };
{ LRQ_SCT1RDQ, SEL_RD64_3 }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rd64_3_adtype, sct1rdq_rd64_3_ad };
{ LRQ_SCT1RDQ, SEL_RDER }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rder_adtype, sct1rdq_rder_ad };
{ LRQ_SCT2RDQ, SEL_RD16 }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rd16_adtype, sct2rdq_rd16_ad };
{ LRQ_SCT2RDQ, SEL_RD64_0 }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rd64_0_adtype, sct2rdq_rd64_0_ad };
{ LRQ_SCT2RDQ, SEL_RD64_1 }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rd64_1_adtype, sct2rdq_rd64_1_ad };
{ LRQ_SCT2RDQ, SEL_RD64_2 }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rd64_2_adtype, sct2rdq_rd64_2_ad };
{ LRQ_SCT2RDQ, SEL_RD64_3 }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rd64_3_adtype, sct2rdq_rd64_3_ad };
{ LRQ_SCT2RDQ, SEL_RDER }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rder_adtype, sct2rdq_rder_ad };
{ LRQ_SCT3RDQ, SEL_RD16 }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rd16_adtype, sct3rdq_rd16_ad };
{ LRQ_SCT3RDQ, SEL_RD64_0 }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rd64_0_adtype, sct3rdq_rd64_0_ad };
{ LRQ_SCT3RDQ, SEL_RD64_1 }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rd64_1_adtype, sct3rdq_rd64_1_ad };
{ LRQ_SCT3RDQ, SEL_RD64_2 }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rd64_2_adtype, sct3rdq_rd64_2_ad };
{ LRQ_SCT3RDQ, SEL_RD64_3 }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rd64_3_adtype, sct3rdq_rd64_3_ad };
{ LRQ_SCT3RDQ, SEL_RDER }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rder_adtype, sct3rdq_rder_ad };
{ LRQ_PIORQQ, SEL_NCRD }: { jbi_io_j_adtype, j_ad } = { piorqq_ncrd_adtype, piorqq_ncrd_ad };
{ LRQ_PIORQQ, SEL_NCWR_0 }: { jbi_io_j_adtype, j_ad } = { piorqq_ncwr_0_adtype, piorqq_ncwr_0_ad };
{ LRQ_PIORQQ, SEL_NCWR_1 }: { jbi_io_j_adtype, j_ad } = { piorqq_ncwr_1_adtype, piorqq_ncwr_1_ad };
{ LRQ_PIOACKQ, SEL_INTACK }: { jbi_io_j_adtype, j_ad } = { pioackq_intack_adtype, pioackq_intack_ad };
{ LRQ_PIOACKQ, SEL_INTNACK }: { jbi_io_j_adtype, j_ad } = { pioackq_intnack_adtype, pioackq_intnack_ad };
{ LRQ_DBGQ, SEL_RD16 }: { jbi_io_j_adtype, j_ad } = { dbgq_rd16_adtype, dbgq_rd16_ad };
default: { jbi_io_j_adtype, j_ad } = { 8'bX, 128'bX };
endcase
end
// Error injection (inj_err_j_ad[3]=J_AD[96], [2]=J_AD[64], [1]=J_AD[32], [0]=J_AD[0]).
assign jbi_io_j_ad[127:0] = { j_ad[127:97], (j_ad[96]^inj_err_j_ad[3]),
j_ad[ 95:65], (j_ad[64]^inj_err_j_ad[2]),
j_ad[ 63:33], (j_ad[32]^inj_err_j_ad[1]),
j_ad[ 31: 1], (j_ad[ 0]^inj_err_j_ad[0]) };
// J_ADP odd parity bits generation (undriven, 1's, is correct parity [JBus Spec pg 20]).
assign jbi_io_j_adp[3] = ~((^ j_ad[127:96]) ^ (^ jbi_io_j_adtype[7:0]));
assign jbi_io_j_adp[2] = ~ (^ j_ad[ 95:64]);
assign jbi_io_j_adp[1] = ~ (^ j_ad[ 63:32]);
assign jbi_io_j_adp[0] = ~ (^ j_ad[ 31: 0]);
// Monitors.
// simtech modcovoff -bpen
// synopsys translate_off
// Check: Address halves are the same for address cycles.
always @(posedge clk) begin
if ((sel_j_adbus == SEL_IDLE || sel_j_adbus == SEL_INTACK || sel_j_adbus == SEL_INTNACK || sel_j_adbus == SEL_NCRD || sel_j_adbus == SEL_NCWR_0) &&
(j_ad[127:64] != j_ad[63:0]) && !csr_jbi_debug_info_enb) begin
$dispmon ("jbi_mout_jbi_pktout_mux", 49, "%d %m: ERROR - Upper and halves of J_AD[] must match on address cycles. (%h, %h)", $time, j_ad[127:64], j_ad[63:0]);
end
end
// Check: Select of case has a valid state.
always @(posedge clk) begin
if ({ jbi_io_j_adtype, j_ad } === { 8'bX, 128'bX }) begin
$dispmon ("jbi_mout_jbi_pktout_mux", 49, "%d %m: ERROR - Invalid multiplexer select value. (%b)", $time, sel_j_adbus);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../include")
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-auto-read-includes:t
// verilog-module-parents:("jbi_pktout_asm")
// End:
|
//---------------------------------------------------------------------//
// Name: addrgen.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Generates addresses.
//---------------------------------------------------------------------//
module addrgen(
clk,
nrst,
start,
n,
wraddr,
wren,
rdaddr,
vexaddr
);
input clk;
input nrst;
input start;
input [15:0]n;
output [10:0]wraddr;
output [10:0]rdaddr;
output [13:0]vexaddr;
output wren;
reg [15:0]counter1;
reg [15:0]counter2;
reg [15:0]counter3;
reg [15:0]counter4;
reg [15:0]timer1;
reg [15:0]timer2;
reg [15:0]timer3;
reg [29:0]t1_exp_dly;
reg [29:0]t2_exp_dly;
reg [29:0]start_dly;
wire t1_expire = timer1[15];
wire t2_expire = timer2[15];
wire t3_expire = timer3[15];
assign rdaddr = counter1[10:0];
assign vexaddr = counter3[13:0];
assign wraddr = counter4[10:0];
//---------------------------------------------------------------------//
// Timers
//---------------------------------------------------------------------//
// Timer T1
// - Loads 'n' on start.
// - Stops counting when it reaches -1.
// - Decrements on t2_expire;
always @(posedge clk)
if (~nrst) timer1 <= -1;
else if(start) timer1 <= {1'b0,n[14:0]};
else if(!t1_expire && t2_expire) timer1 <= timer1 - 1;
// Timer T2
// - Counts down from T1 divided by 4.
// - Resets when it hits -1.
// - Stops decrementing the initial input once t3 expires.
wire [15:0] t2_startval = {3'b0, n[15:2]} - 1;
wire [15:0] t1_minus = timer1 - 5;
always @(posedge clk)
if (~nrst) timer2 <= -1;
else if(start) timer2 <= t2_startval;
else if(!t1_expire && t2_expire && !t3_expire) timer2 <= {3'b0, t1_minus[15:2]};
else if(!t1_expire && t2_expire && t3_expire) timer2 <= 30;
else if(!t1_expire && !t2_expire) timer2 <= timer2 - 1;
// Timer T3
always @(posedge clk)
if(~nrst) timer3 <= -1;
else if(start) timer3 <= n-128; // For a 30 cycle pipeline.
else if(!t3_expire && t2_expire) timer3 <= timer3 - 1;
// Shift registers for delayed counting.
always@(posedge clk)
if (~nrst) t1_exp_dly <= 0;
else t1_exp_dly <= {t1_exp_dly[28:0], t1_expire};
always@(posedge clk)
if(~nrst) t2_exp_dly <= 0;
else t2_exp_dly <= {t2_exp_dly[28:0], t2_expire};
always@(posedge clk)
if(~nrst) start_dly <= 0;
else start_dly <= {start_dly[28:0], start};
wire sig_a = t1_exp_dly[24];
wire sig_b = t2_exp_dly[24];
wire sig_c = start_dly[24];
wire sig_d = t1_exp_dly[29];
wire sig_e = t2_exp_dly[29];
wire sig_f = start_dly[29];
assign wren = !sig_d;
//---------------------------------------------------------------------//
// Logic for generating rdaddr.
//---------------------------------------------------------------------//
// Counter C1
// - Counts up from 0.
// - Resets when t2 expires.
// - Stops when t1 expires.
always @(posedge clk)
if (~nrst) counter1 <= -1;
else if(start) counter1 <= 0;
else if(!t1_expire && t2_expire) counter1 <= 0;
else if(!t1_expire && !t2_expire) counter1 <= counter1 + 1;
//---------------------------------------------------------------------//
// Logic for generating vex_addr.
//---------------------------------------------------------------------//
// Counter C2
// - Counts up from 0.
// - Resets at start.
// - Stops counting when t4 expires.
always @(posedge clk)
if(~nrst) counter2 <= -1;
else if(sig_c) counter2 <= 0;
else if(!sig_a && sig_b) counter2 <= counter2 + 1;
// Counter C3
// - Counts up from 0.
// - Resets at start.
// - Stops counting when t1 expires.
always @(posedge clk)
if(~nrst) counter3 <= -1;
else if(sig_c) counter3 <= 0;
else if(!sig_a && sig_b) counter3 <= counter2 + 1;
else if(!sig_a && !sig_b) counter3 <= counter3 + 8;
//---------------------------------------------------------------------//
// Logic for generating wraddr.
//---------------------------------------------------------------------//
// Counter C4
// - Counts up from 0.
// - Resets when t2 expires.
// - Stops when t1 expires.
always @(posedge clk)
if (~nrst) counter4 <= -1;
else if(sig_f) counter4 <= 0;
else if(!sig_d && sig_e) counter4 <= 0;
else if(!sig_d && !sig_e) counter4 <= counter4 + 1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V |
module top(
input i_ce,
input i_clk,
input i_clkb,
input i_rst,
input [11:0] io,
output o_q1,
output o_q2
);
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_AO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_AO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_BO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_BO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_CO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_CO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_DO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_DO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_AMUX;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_AO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_BMUX;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_BO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_BO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_CMUX;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_CO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_CO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_DO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_DO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_AMUX;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_AO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_BMUX;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_BO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_BO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_CMUX;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_CO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_CO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_DO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_DO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_AO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_AO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_BO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_BO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_CO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_CO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_DO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_DO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D_XOR;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S1;
wire [0:0] LIOB33_X0Y33_IOB_X0Y34_I;
wire [0:0] LIOB33_X0Y35_IOB_X0Y35_I;
wire [0:0] LIOB33_X0Y35_IOB_X0Y36_I;
wire [0:0] LIOB33_X0Y37_IOB_X0Y37_I;
wire [0:0] LIOB33_X0Y37_IOB_X0Y38_I;
wire [0:0] LIOB33_X0Y39_IOB_X0Y39_I;
wire [0:0] LIOB33_X0Y39_IOB_X0Y40_I;
wire [0:0] LIOB33_X0Y41_IOB_X0Y41_I;
wire [0:0] LIOB33_X0Y41_IOB_X0Y42_I;
wire [0:0] LIOB33_X0Y43_IOB_X0Y43_I;
wire [0:0] LIOB33_X0Y45_IOB_X0Y45_I;
wire [0:0] LIOB33_X0Y45_IOB_X0Y46_I;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CE1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CLK;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CLKB;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_D;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q2;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_SR;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CE1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CLK;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CLKB;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_D;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q2;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_SR;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CE1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CLK;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CLKB;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_D;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q2;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_SR;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_CE1;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_CLK;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_CLKB;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_D;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_Q1;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_Q2;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_SR;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_CE1;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_CLK;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_CLKB;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_D;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_Q1;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_Q2;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_SR;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_CE1;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_CLK;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_CLKB;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_D;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_Q1;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_Q2;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_SR;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_CE1;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_CLK;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_CLKB;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_D;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_Q1;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_Q2;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_SR;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_CE1;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_CLK;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_CLKB;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_D;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_Q1;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_Q2;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_SR;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_CE1;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_CLK;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_CLKB;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_D;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_Q1;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_Q2;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_SR;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_CE1;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_CLK;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_CLKB;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_D;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_Q1;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_Q2;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_SR;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_CE1;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_CLK;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_CLKB;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_D;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_Q1;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_Q2;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_SR;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_CE1;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_CLK;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_CLKB;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_D;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_Q1;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_Q2;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_SR;
wire [0:0] RIOB33_X43Y23_IOB_X1Y24_I;
wire [0:0] RIOB33_X43Y25_IOB_X1Y26_I;
wire [0:0] RIOB33_X43Y43_IOB_X1Y43_O;
wire [0:0] RIOB33_X43Y43_IOB_X1Y44_O;
wire [0:0] RIOB33_X43Y45_IOB_X1Y45_I;
wire [0:0] RIOB33_X43Y45_IOB_X1Y46_I;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_D1;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_OQ;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_T1;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_TQ;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_D1;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_OQ;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_T1;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_TQ;
wire [0:0] RIOI3_X43Y23_ILOGIC_X1Y24_D;
wire [0:0] RIOI3_X43Y23_ILOGIC_X1Y24_O;
wire [0:0] RIOI3_X43Y25_ILOGIC_X1Y26_D;
wire [0:0] RIOI3_X43Y25_ILOGIC_X1Y26_O;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y45_D;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y45_O;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y46_D;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y46_O;
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y42_SLICE_X0Y42_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X0Y42_DO5),
.O6(CLBLL_L_X2Y42_SLICE_X0Y42_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y42_SLICE_X0Y42_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X0Y42_CO5),
.O6(CLBLL_L_X2Y42_SLICE_X0Y42_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y42_SLICE_X0Y42_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X0Y42_BO5),
.O6(CLBLL_L_X2Y42_SLICE_X0Y42_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y42_SLICE_X0Y42_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X0Y42_AO5),
.O6(CLBLL_L_X2Y42_SLICE_X0Y42_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y42_SLICE_X1Y42_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X1Y42_DO5),
.O6(CLBLL_L_X2Y42_SLICE_X1Y42_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000010100000000)
) CLBLL_L_X2Y42_SLICE_X1Y42_CLUT (
.I0(LIOI3_X0Y35_ILOGIC_X0Y36_Q1),
.I1(LIOI3_X0Y33_ILOGIC_X0Y34_Q1),
.I2(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q1),
.I3(1'b1),
.I4(LIOI3_X0Y35_ILOGIC_X0Y35_Q1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X1Y42_CO5),
.O6(CLBLL_L_X2Y42_SLICE_X1Y42_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000500000000)
) CLBLL_L_X2Y42_SLICE_X1Y42_BLUT (
.I0(LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q1),
.I1(1'b1),
.I2(LIOI3_X0Y45_ILOGIC_X0Y45_Q1),
.I3(LIOI3_X0Y41_ILOGIC_X0Y42_Q1),
.I4(LIOI3_X0Y45_ILOGIC_X0Y46_Q1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X1Y42_BO5),
.O6(CLBLL_L_X2Y42_SLICE_X1Y42_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'hfffffffdffffffff)
) CLBLL_L_X2Y42_SLICE_X1Y42_ALUT (
.I0(CLBLL_L_X2Y42_SLICE_X1Y42_BO6),
.I1(LIOI3_X0Y39_ILOGIC_X0Y39_Q1),
.I2(LIOI3_X0Y41_ILOGIC_X0Y41_Q1),
.I3(LIOI3_X0Y39_ILOGIC_X0Y40_Q1),
.I4(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q1),
.I5(CLBLL_L_X2Y42_SLICE_X1Y42_CO6),
.O5(CLBLL_L_X2Y42_SLICE_X1Y42_AO5),
.O6(CLBLL_L_X2Y42_SLICE_X1Y42_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y43_SLICE_X0Y43_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X0Y43_DO5),
.O6(CLBLL_L_X2Y43_SLICE_X0Y43_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000010100000000)
) CLBLL_L_X2Y43_SLICE_X0Y43_CLUT (
.I0(LIOI3_X0Y35_ILOGIC_X0Y36_Q2),
.I1(LIOI3_X0Y33_ILOGIC_X0Y34_Q2),
.I2(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q2),
.I3(1'b1),
.I4(LIOI3_X0Y35_ILOGIC_X0Y35_Q2),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X0Y43_CO5),
.O6(CLBLL_L_X2Y43_SLICE_X0Y43_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000500000000)
) CLBLL_L_X2Y43_SLICE_X0Y43_BLUT (
.I0(LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q2),
.I1(1'b1),
.I2(LIOI3_X0Y45_ILOGIC_X0Y45_Q2),
.I3(LIOI3_X0Y41_ILOGIC_X0Y42_Q2),
.I4(LIOI3_X0Y45_ILOGIC_X0Y46_Q2),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X0Y43_BO5),
.O6(CLBLL_L_X2Y43_SLICE_X0Y43_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'hfffffffdffffffff)
) CLBLL_L_X2Y43_SLICE_X0Y43_ALUT (
.I0(CLBLL_L_X2Y43_SLICE_X0Y43_BO6),
.I1(LIOI3_X0Y39_ILOGIC_X0Y39_Q2),
.I2(LIOI3_X0Y41_ILOGIC_X0Y41_Q2),
.I3(LIOI3_X0Y39_ILOGIC_X0Y40_Q2),
.I4(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q2),
.I5(CLBLL_L_X2Y43_SLICE_X0Y43_CO6),
.O5(CLBLL_L_X2Y43_SLICE_X0Y43_AO5),
.O6(CLBLL_L_X2Y43_SLICE_X0Y43_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y43_SLICE_X1Y43_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X1Y43_DO5),
.O6(CLBLL_L_X2Y43_SLICE_X1Y43_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y43_SLICE_X1Y43_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X1Y43_CO5),
.O6(CLBLL_L_X2Y43_SLICE_X1Y43_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y43_SLICE_X1Y43_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X1Y43_BO5),
.O6(CLBLL_L_X2Y43_SLICE_X1Y43_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y43_SLICE_X1Y43_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X1Y43_AO5),
.O6(CLBLL_L_X2Y43_SLICE_X1Y43_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "BUFGCTRL" *)
BUFGCTRL #(
.INIT_OUT(0),
.IS_CE0_INVERTED(0),
.IS_CE1_INVERTED(1),
.IS_IGNORE0_INVERTED(1),
.IS_IGNORE1_INVERTED(0),
.IS_S0_INVERTED(0),
.IS_S1_INVERTED(1),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE")
) CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_BUFGCTRL (
.CE0(1'b1),
.CE1(1'b1),
.I0(RIOB33_X43Y25_IOB_X1Y26_I),
.I1(1'b1),
.IGNORE0(1'b1),
.IGNORE1(1'b1),
.O(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.S0(1'b1),
.S1(1'b1)
);
(* KEEP, DONT_TOUCH, BEL = "BUFGCTRL" *)
BUFGCTRL #(
.INIT_OUT(0),
.IS_CE0_INVERTED(0),
.IS_CE1_INVERTED(1),
.IS_IGNORE0_INVERTED(1),
.IS_IGNORE1_INVERTED(0),
.IS_S0_INVERTED(0),
.IS_S1_INVERTED(1),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE")
) CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_BUFGCTRL (
.CE0(1'b1),
.CE1(1'b1),
.I0(RIOB33_X43Y23_IOB_X1Y24_I),
.I1(1'b1),
.IGNORE0(1'b1),
.IGNORE1(1'b1),
.O(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.S0(1'b1),
.S1(1'b1)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y33_IOB_X0Y34_IBUF (
.I(io[11]),
.O(LIOB33_X0Y33_IOB_X0Y34_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y35_IOB_X0Y35_IBUF (
.I(io[10]),
.O(LIOB33_X0Y35_IOB_X0Y35_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y35_IOB_X0Y36_IBUF (
.I(io[9]),
.O(LIOB33_X0Y35_IOB_X0Y36_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y37_IOB_X0Y37_IBUF (
.I(io[8]),
.O(LIOB33_X0Y37_IOB_X0Y37_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y37_IOB_X0Y38_IBUF (
.I(io[7]),
.O(LIOB33_X0Y37_IOB_X0Y38_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y39_IOB_X0Y39_IBUF (
.I(io[6]),
.O(LIOB33_X0Y39_IOB_X0Y39_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y39_IOB_X0Y40_IBUF (
.I(io[5]),
.O(LIOB33_X0Y39_IOB_X0Y40_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y41_IOB_X0Y41_IBUF (
.I(io[4]),
.O(LIOB33_X0Y41_IOB_X0Y41_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y41_IOB_X0Y42_IBUF (
.I(io[3]),
.O(LIOB33_X0Y41_IOB_X0Y42_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y43_IOB_X0Y43_IBUF (
.I(io[2]),
.O(LIOB33_X0Y43_IOB_X0Y43_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y45_IOB_X0Y45_IBUF (
.I(io[1]),
.O(LIOB33_X0Y45_IOB_X0Y45_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y45_IOB_X0Y46_IBUF (
.I(io[0]),
.O(LIOB33_X0Y45_IOB_X0Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b1),
.SRTYPE("SYNC")
) LIOI3_X0Y33_ILOGIC_X0Y34_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y33_IOB_X0Y34_I),
.Q1(LIOI3_X0Y33_ILOGIC_X0Y34_Q1),
.Q2(LIOI3_X0Y33_ILOGIC_X0Y34_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b1),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y35_ILOGIC_X0Y36_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y35_IOB_X0Y36_I),
.Q1(LIOI3_X0Y35_ILOGIC_X0Y36_Q1),
.Q2(LIOI3_X0Y35_ILOGIC_X0Y36_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y35_ILOGIC_X0Y35_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y35_IOB_X0Y35_I),
.Q1(LIOI3_X0Y35_ILOGIC_X0Y35_Q1),
.Q2(LIOI3_X0Y35_ILOGIC_X0Y35_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y39_ILOGIC_X0Y40_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y39_IOB_X0Y40_I),
.Q1(LIOI3_X0Y39_ILOGIC_X0Y40_Q1),
.Q2(LIOI3_X0Y39_ILOGIC_X0Y40_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y39_ILOGIC_X0Y39_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y39_IOB_X0Y39_I),
.Q1(LIOI3_X0Y39_ILOGIC_X0Y39_Q1),
.Q2(LIOI3_X0Y39_ILOGIC_X0Y39_Q2),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y41_ILOGIC_X0Y42_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y41_IOB_X0Y42_I),
.Q1(LIOI3_X0Y41_ILOGIC_X0Y42_Q1),
.Q2(LIOI3_X0Y41_ILOGIC_X0Y42_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y41_ILOGIC_X0Y41_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y41_IOB_X0Y41_I),
.Q1(LIOI3_X0Y41_ILOGIC_X0Y41_Q1),
.Q2(LIOI3_X0Y41_ILOGIC_X0Y41_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y45_ILOGIC_X0Y46_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y45_IOB_X0Y46_I),
.Q1(LIOI3_X0Y45_ILOGIC_X0Y46_Q1),
.Q2(LIOI3_X0Y45_ILOGIC_X0Y46_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y45_ILOGIC_X0Y45_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y45_IOB_X0Y45_I),
.Q1(LIOI3_X0Y45_ILOGIC_X0Y45_Q1),
.Q2(LIOI3_X0Y45_ILOGIC_X0Y45_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y43_IOB_X0Y43_I),
.Q1(LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q1),
.Q2(LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y37_IOB_X0Y38_I),
.Q1(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q1),
.Q2(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q2),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y37_IOB_X0Y37_I),
.Q1(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q1),
.Q2(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y23_IOB_X1Y24_IBUF (
.I(i_clkb),
.O(RIOB33_X43Y23_IOB_X1Y24_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y25_IOB_X1Y26_IBUF (
.I(i_clk),
.O(RIOB33_X43Y25_IOB_X1Y26_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) RIOB33_X43Y43_IOB_X1Y43_OBUF (
.I(CLBLL_L_X2Y43_SLICE_X0Y43_AO6),
.O(o_q2)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) RIOB33_X43Y43_IOB_X1Y44_OBUF (
.I(CLBLL_L_X2Y42_SLICE_X1Y42_AO6),
.O(o_q1)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y45_IOB_X1Y45_IBUF (
.I(i_ce),
.O(RIOB33_X43Y45_IOB_X1Y45_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y45_IOB_X1Y46_IBUF (
.I(i_rst),
.O(RIOB33_X43Y45_IOB_X1Y46_I)
);
assign CLBLL_L_X2Y42_SLICE_X0Y42_COUT = CLBLL_L_X2Y42_SLICE_X0Y42_D_CY;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A = CLBLL_L_X2Y42_SLICE_X0Y42_AO6;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B = CLBLL_L_X2Y42_SLICE_X0Y42_BO6;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C = CLBLL_L_X2Y42_SLICE_X0Y42_CO6;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D = CLBLL_L_X2Y42_SLICE_X0Y42_DO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_COUT = CLBLL_L_X2Y42_SLICE_X1Y42_D_CY;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A = CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B = CLBLL_L_X2Y42_SLICE_X1Y42_BO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C = CLBLL_L_X2Y42_SLICE_X1Y42_CO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D = CLBLL_L_X2Y42_SLICE_X1Y42_DO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_AMUX = CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_BMUX = CLBLL_L_X2Y42_SLICE_X1Y42_BO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_CMUX = CLBLL_L_X2Y42_SLICE_X1Y42_CO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_COUT = CLBLL_L_X2Y43_SLICE_X0Y43_D_CY;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A = CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B = CLBLL_L_X2Y43_SLICE_X0Y43_BO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C = CLBLL_L_X2Y43_SLICE_X0Y43_CO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D = CLBLL_L_X2Y43_SLICE_X0Y43_DO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_AMUX = CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_BMUX = CLBLL_L_X2Y43_SLICE_X0Y43_BO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_CMUX = CLBLL_L_X2Y43_SLICE_X0Y43_CO6;
assign CLBLL_L_X2Y43_SLICE_X1Y43_COUT = CLBLL_L_X2Y43_SLICE_X1Y43_D_CY;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A = CLBLL_L_X2Y43_SLICE_X1Y43_AO6;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B = CLBLL_L_X2Y43_SLICE_X1Y43_BO6;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C = CLBLL_L_X2Y43_SLICE_X1Y43_CO6;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D = CLBLL_L_X2Y43_SLICE_X1Y43_DO6;
assign RIOI3_X43Y23_ILOGIC_X1Y24_O = RIOB33_X43Y23_IOB_X1Y24_I;
assign RIOI3_X43Y25_ILOGIC_X1Y26_O = RIOB33_X43Y25_IOB_X1Y26_I;
assign RIOI3_X43Y45_ILOGIC_X1Y46_O = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_X43Y45_ILOGIC_X1Y45_O = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_OQ = CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_TQ = 1'b1;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_OQ = CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_TQ = 1'b1;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_D1 = CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
assign LIOI3_X0Y39_ILOGIC_X0Y40_D = LIOB33_X0Y39_IOB_X0Y40_I;
assign LIOI3_X0Y39_ILOGIC_X0Y39_D = LIOB33_X0Y39_IOB_X0Y39_I;
assign LIOI3_X0Y39_ILOGIC_X0Y40_SR = 1'b0;
assign LIOI3_X0Y39_ILOGIC_X0Y39_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_T1 = 1'b1;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_D1 = CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
assign LIOI3_X0Y39_ILOGIC_X0Y39_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y33_ILOGIC_X0Y34_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_T1 = 1'b1;
assign LIOI3_X0Y33_ILOGIC_X0Y34_D = LIOB33_X0Y33_IOB_X0Y34_I;
assign RIOI3_X43Y23_ILOGIC_X1Y24_D = RIOB33_X43Y23_IOB_X1Y24_I;
assign LIOI3_X0Y33_ILOGIC_X0Y34_SR = 1'b0;
assign LIOI3_X0Y41_ILOGIC_X0Y41_SR = 1'b0;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A1 = CLBLL_L_X2Y43_SLICE_X0Y43_BO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A2 = LIOI3_X0Y39_ILOGIC_X0Y39_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A3 = LIOI3_X0Y41_ILOGIC_X0Y41_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A4 = LIOI3_X0Y39_ILOGIC_X0Y40_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A5 = LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A6 = CLBLL_L_X2Y43_SLICE_X0Y43_CO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B1 = LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B3 = LIOI3_X0Y45_ILOGIC_X0Y45_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B4 = LIOI3_X0Y41_ILOGIC_X0Y42_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B5 = LIOI3_X0Y45_ILOGIC_X0Y46_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B6 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C1 = LIOI3_X0Y35_ILOGIC_X0Y36_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C2 = LIOI3_X0Y33_ILOGIC_X0Y34_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C3 = LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C5 = LIOI3_X0Y35_ILOGIC_X0Y35_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C6 = 1'b1;
assign LIOI3_X0Y35_ILOGIC_X0Y36_SR = 1'b0;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D1 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D3 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D5 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D6 = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_D = LIOB33_X0Y37_IOB_X0Y38_I;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_D = LIOB33_X0Y37_IOB_X0Y37_I;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y41_ILOGIC_X0Y42_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A1 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A3 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A5 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A6 = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_SR = 1'b0;
assign LIOI3_X0Y41_ILOGIC_X0Y42_D = LIOB33_X0Y41_IOB_X0Y42_I;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B1 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B3 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B5 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B6 = 1'b1;
assign LIOI3_X0Y41_ILOGIC_X0Y42_SR = 1'b0;
assign LIOI3_X0Y41_ILOGIC_X0Y41_D = LIOB33_X0Y41_IOB_X0Y41_I;
assign LIOI3_X0Y41_ILOGIC_X0Y41_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C1 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C3 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C5 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C6 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D1 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D3 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D5 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D6 = 1'b1;
assign LIOI3_X0Y35_ILOGIC_X0Y36_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y35_ILOGIC_X0Y36_D = LIOB33_X0Y35_IOB_X0Y36_I;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE1 = 1'b1;
assign LIOI3_X0Y35_ILOGIC_X0Y35_D = LIOB33_X0Y35_IOB_X0Y35_I;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S1 = 1'b1;
assign LIOI3_X0Y35_ILOGIC_X0Y35_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y35_ILOGIC_X0Y35_SR = 1'b0;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A3 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A5 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A6 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B3 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B5 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B6 = 1'b1;
assign RIOI3_X43Y45_ILOGIC_X1Y46_D = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_X43Y45_ILOGIC_X1Y45_D = RIOB33_X43Y45_IOB_X1Y45_I;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C3 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C5 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C6 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D3 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D5 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D6 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I0 = RIOB33_X43Y25_IOB_X1Y26_I;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A1 = CLBLL_L_X2Y42_SLICE_X1Y42_BO6;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I0 = RIOB33_X43Y23_IOB_X1Y24_I;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A2 = LIOI3_X0Y39_ILOGIC_X0Y39_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A3 = LIOI3_X0Y41_ILOGIC_X0Y41_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A4 = LIOI3_X0Y39_ILOGIC_X0Y40_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A5 = LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A6 = CLBLL_L_X2Y42_SLICE_X1Y42_CO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B1 = LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B3 = LIOI3_X0Y45_ILOGIC_X0Y45_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B4 = LIOI3_X0Y41_ILOGIC_X0Y42_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B5 = LIOI3_X0Y45_ILOGIC_X0Y46_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B6 = 1'b1;
assign RIOI3_X43Y25_ILOGIC_X1Y26_D = RIOB33_X43Y25_IOB_X1Y26_I;
assign LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_D = LIOB33_X0Y43_IOB_X0Y43_I;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C1 = LIOI3_X0Y35_ILOGIC_X0Y36_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C2 = LIOI3_X0Y33_ILOGIC_X0Y34_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C3 = LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C5 = LIOI3_X0Y35_ILOGIC_X0Y35_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C6 = 1'b1;
assign LIOI3_X0Y45_ILOGIC_X0Y46_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D3 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D5 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D6 = 1'b1;
assign LIOI3_X0Y45_ILOGIC_X0Y46_D = LIOB33_X0Y45_IOB_X0Y46_I;
assign LIOI3_X0Y45_ILOGIC_X0Y45_D = LIOB33_X0Y45_IOB_X0Y45_I;
assign LIOI3_X0Y45_ILOGIC_X0Y46_SR = 1'b0;
assign LIOI3_X0Y45_ILOGIC_X0Y45_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_SR = 1'b0;
assign RIOB33_X43Y43_IOB_X1Y43_O = CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
assign RIOB33_X43Y43_IOB_X1Y44_O = CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
assign LIOI3_X0Y45_ILOGIC_X0Y45_SR = 1'b0;
assign LIOI3_X0Y39_ILOGIC_X0Y40_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y39_ILOGIC_X0Y39_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y33_ILOGIC_X0Y34_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y41_ILOGIC_X0Y42_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y41_ILOGIC_X0Y41_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y35_ILOGIC_X0Y36_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y35_ILOGIC_X0Y35_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y45_ILOGIC_X0Y46_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y45_ILOGIC_X0Y45_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y39_ILOGIC_X0Y40_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y39_ILOGIC_X0Y39_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y33_ILOGIC_X0Y34_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y41_ILOGIC_X0Y42_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y41_ILOGIC_X0Y41_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y35_ILOGIC_X0Y36_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y35_ILOGIC_X0Y35_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y45_ILOGIC_X0Y46_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y45_ILOGIC_X0Y45_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y39_ILOGIC_X0Y40_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_PP_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_PP_V |
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import Arith Bool List Omega.
Require Import CpdtTactics MoreSpecif.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** %\chapter{More Dependent Types}% *)
(** Subset types and their relatives help us integrate verification with programming. Though they reorganize the certified programmer's workflow, they tend not to have deep effects on proofs. We write largely the same proofs as we would for classical verification, with some of the structure moved into the programs themselves. It turns out that, when we use dependent types to their full potential, we warp the development and proving process even more than that, picking up "free theorems" to the extent that often a certified program is hardly more complex than its uncertified counterpart in Haskell or ML.
In particular, we have only scratched the tip of the iceberg that is Coq's inductive definition mechanism. The inductive types we have seen so far have their counterparts in the other proof assistants that we surveyed in Chapter 1. This chapter explores the strange new world of dependent inductive datatypes outside [Prop], a possibility that sets Coq apart from all of the competition not based on type theory. *)
(** * Length-Indexed Lists *)
(** Many introductions to dependent types start out by showing how to use them to eliminate array bounds checks%\index{array bounds checks}%. When the type of an array tells you how many elements it has, your compiler can detect out-of-bounds dereferences statically. Since we are working in a pure functional language, the next best thing is length-indexed lists%\index{length-indexed lists}%, which the following code defines. *)
Section ilist.
Variable A : Set.
Inductive ilist : nat -> Set :=
| Nil : ilist O
| Cons : forall n, A -> ilist n -> ilist (S n).
(** We see that, within its section, [ilist] is given type [nat -> Set]. Previously, every inductive type we have seen has either had plain [Set] as its type or has been a predicate with some type ending in [Prop]. The full generality of inductive definitions lets us integrate the expressivity of predicates directly into our normal programming.
The [nat] argument to [ilist] tells us the length of the list. The types of [ilist]'s constructors tell us that a [Nil] list has length [O] and that a [Cons] list has length one greater than the length of its tail. We may apply [ilist] to any natural number, even natural numbers that are only known at runtime. It is this breaking of the%\index{phase distinction}% _phase distinction_ that characterizes [ilist] as _dependently typed_.
In expositions of list types, we usually see the length function defined first, but here that would not be a very productive function to code. Instead, let us implement list concatenation. *)
Fixpoint app n1 (ls1 : ilist n1) n2 (ls2 : ilist n2) : ilist (n1 + n2) :=
match ls1 with
| Nil => ls2
| Cons _ x ls1' => Cons x (app ls1' ls2)
end.
(** Past Coq versions signalled an error for this definition. The code is still invalid within Coq's core language, but current Coq versions automatically add annotations to the original program, producing a valid core program. These are the annotations on [match] discriminees that we began to study in the previous chapter. We can rewrite [app] to give the annotations explicitly. *)
(* begin thide *)
Fixpoint app' n1 (ls1 : ilist n1) n2 (ls2 : ilist n2) : ilist (n1 + n2) :=
match ls1 in (ilist n1) return (ilist (n1 + n2)) with
| Nil => ls2
| Cons _ x ls1' => Cons x (app' ls1' ls2)
end.
(* end thide *)
(** Using [return] alone allowed us to express a dependency of the [match] result type on the _value_ of the discriminee. What %\index{Gallina terms!in}%[in] adds to our arsenal is a way of expressing a dependency on the _type_ of the discriminee. Specifically, the [n1] in the [in] clause above is a _binding occurrence_ whose scope is the [return] clause.
We may use [in] clauses only to bind names for the arguments of an inductive type family. That is, each [in] clause must be an inductive type family name applied to a sequence of underscores and variable names of the proper length. The positions for _parameters_ to the type family must all be underscores. Parameters are those arguments declared with section variables or with entries to the left of the first colon in an inductive definition. They cannot vary depending on which constructor was used to build the discriminee, so Coq prohibits pointless matches on them. It is those arguments defined in the type to the right of the colon that we may name with [in] clauses.
Our [app] function could be typed in so-called%\index{stratified type systems}% _stratified_ type systems, which avoid true dependency. That is, we could consider the length indices to lists to live in a separate, compile-time-only universe from the lists themselves. Compile-time data may be _erased_ such that we can still execute a program. As an example where erasure would not work, consider an injection function from regular lists to length-indexed lists. Here the run-time computation actually depends on details of the compile-time argument, if we decide that the list to inject can be considered compile-time. More commonly, we think of lists as run-time data. Neither case will work with %\%naive%{}% erasure. (It is not too important to grasp the details of this run-time/compile-time distinction, since Coq's expressive power comes from avoiding such restrictions.) *)
(* EX: Implement injection from normal lists *)
(* begin thide *)
Fixpoint inject (ls : list A) : ilist (length ls) :=
match ls with
| nil => Nil
| h :: t => Cons h (inject t)
end.
(** We can define an inverse conversion and prove that it really is an inverse. *)
Fixpoint unject n (ls : ilist n) : list A :=
match ls with
| Nil => nil
| Cons _ h t => h :: unject t
end.
Theorem inject_inverse : forall ls, unject (inject ls) = ls.
induction ls; crush.
Qed.
(* end thide *)
(* EX: Implement statically checked "car"/"hd" *)
(** Now let us attempt a function that is surprisingly tricky to write. In ML, the list head function raises an exception when passed an empty list. With length-indexed lists, we can rule out such invalid calls statically, and here is a first attempt at doing so. We write [???] as a placeholder for a term that we do not know how to write, not for any real Coq notation like those introduced two chapters ago.
[[
Definition hd n (ls : ilist (S n)) : A :=
match ls with
| Nil => ???
| Cons _ h _ => h
end.
]]
It is not clear what to write for the [Nil] case, so we are stuck before we even turn our function over to the type checker. We could try omitting the [Nil] case:
[[
Definition hd n (ls : ilist (S n)) : A :=
match ls with
| Cons _ h _ => h
end.
]]
<<
Error: Non exhaustive pattern-matching: no clause found for pattern Nil
>>
Unlike in ML, we cannot use inexhaustive pattern matching, because there is no conception of a <<Match>> exception to be thrown. In fact, recent versions of Coq _do_ allow this, by implicit translation to a [match] that considers all constructors; the error message above was generated by an older Coq version. It is educational to discover for ourselves the encoding that the most recent Coq versions use. We might try using an [in] clause somehow.
[[
Definition hd n (ls : ilist (S n)) : A :=
match ls in (ilist (S n)) with
| Cons _ h _ => h
end.
]]
<<
Error: The reference n was not found in the current environment
>>
In this and other cases, we feel like we want [in] clauses with type family arguments that are not variables. Unfortunately, Coq only supports variables in those positions. A completely general mechanism could only be supported with a solution to the problem of higher-order unification%~\cite{HOU}%, which is undecidable. There _are_ useful heuristics for handling non-variable indices which are gradually making their way into Coq, but we will spend some time in this and the next few chapters on effective pattern matching on dependent types using only the primitive [match] annotations.
Our final, working attempt at [hd] uses an auxiliary function and a surprising [return] annotation. *)
(* begin thide *)
Definition hd' n (ls : ilist n) :=
match ls in (ilist n) return (match n with O => unit | S _ => A end) with
| Nil => tt
| Cons _ h _ => h
end.
Check hd'.
(** %\vspace{-.15in}% [[
hd'
: forall n : nat, ilist n -> match n with
| 0 => unit
| S _ => A
end
]]
*)
Definition hd n (ls : ilist (S n)) : A := hd' ls.
(* end thide *)
End ilist.
(** We annotate our main [match] with a type that is itself a [match]. We write that the function [hd'] returns [unit] when the list is empty and returns the carried type [A] in all other cases. In the definition of [hd], we just call [hd']. Because the index of [ls] is known to be nonzero, the type checker reduces the [match] in the type of [hd'] to [A]. *)
(** * The One Rule of Dependent Pattern Matching in Coq *)
(** The rest of this chapter will demonstrate a few other elegant applications of dependent types in Coq. Readers encountering such ideas for the first time often feel overwhelmed, concluding that there is some magic at work whereby Coq sometimes solves the halting problem for the programmer and sometimes does not, applying automated program understanding in a way far beyond what is found in conventional languages. The point of this section is to cut off that sort of thinking right now! Dependent type-checking in Coq follows just a few algorithmic rules. Chapters 10 and 12 introduce many of those rules more formally, and the main additional rule is centered on%\index{dependent pattern matching}% _dependent pattern matching_ of the kind we met in the previous section.
A dependent pattern match is a [match] expression where the type of the overall [match] is a function of the value and/or the type of the%\index{discriminee}% _discriminee_, the value being matched on. In other words, the [match] type _depends_ on the discriminee.
When exactly will Coq accept a dependent pattern match as well-typed? Some other dependently typed languages employ fancy decision procedures to determine when programs satisfy their very expressive types. The situation in Coq is just the opposite. Only very straightforward symbolic rules are applied. Such a design choice has its drawbacks, as it forces programmers to do more work to convince the type checker of program validity. However, the great advantage of a simple type checking algorithm is that its action on _invalid_ programs is easier to understand!
We come now to the one rule of dependent pattern matching in Coq. A general dependent pattern match assumes this form (with unnecessary parentheses included to make the syntax easier to parse):
[[
match E as y in (T x1 ... xn) return U with
| C z1 ... zm => B
| ...
end
]]
The discriminee is a term [E], a value in some inductive type family [T], which takes [n] arguments. An %\index{as clause}%[as] clause binds the name [y] to refer to the discriminee [E]. An %\index{in clause}%[in] clause binds an explicit name [xi] for the [i]th argument passed to [T] in the type of [E].
We bind these new variables [y] and [xi] so that they may be referred to in [U], a type given in the %\index{return clause}%[return] clause. The overall type of the [match] will be [U], with [E] substituted for [y], and with each [xi] substituted by the actual argument appearing in that position within [E]'s type.
In general, each case of a [match] may have a pattern built up in several layers from the constructors of various inductive type families. To keep this exposition simple, we will focus on patterns that are just single applications of inductive type constructors to lists of variables. Coq actually compiles the more general kind of pattern matching into this more restricted kind automatically, so understanding the typing of [match] requires understanding the typing of [match]es lowered to match one constructor at a time.
The last piece of the typing rule tells how to type-check a [match] case. A generic constructor application [C z1 ... zm] has some type [T x1' ... xn'], an application of the type family used in [E]'s type, probably with occurrences of the [zi] variables. From here, a simple recipe determines what type we will require for the case body [B]. The type of [B] should be [U] with the following two substitutions applied: we replace [y] (the [as] clause variable) with [C z1 ... zm], and we replace each [xi] (the [in] clause variables) with [xi']. In other words, we specialize the result type based on what we learn based on which pattern has matched the discriminee.
This is an exhaustive description of the ways to specify how to take advantage of which pattern has matched! No other mechanisms come into play. For instance, there is no way to specify that the types of certain free variables should be refined based on which pattern has matched. In the rest of the book, we will learn design patterns for achieving similar effects, where each technique leads to an encoding only in terms of [in], [as], and [return] clauses.
A few details have been omitted above. In Chapter 3, we learned that inductive type families may have both%\index{parameters}% _parameters_ and regular arguments. Within an [in] clause, a parameter position must have the wildcard [_] written, instead of a variable. (In general, Coq uses wildcard [_]'s either to indicate pattern variables that will not be mentioned again or to indicate positions where we would like type inference to infer the appropriate terms.) Furthermore, recent Coq versions are adding more and more heuristics to infer dependent [match] annotations in certain conditions. The general annotation inference problem is undecidable, so there will always be serious limitations on how much work these heuristics can do. When in doubt about why a particular dependent [match] is failing to type-check, add an explicit [return] annotation! At that point, the mechanical rule sketched in this section will provide a complete account of "what the type checker is thinking." Be sure to avoid the common pitfall of writing a [return] annotation that does not mention any variables bound by [in] or [as]; such a [match] will never refine typing requirements based on which pattern has matched. (One simple exception to this rule is that, when the discriminee is a variable, that same variable may be treated as if it were repeated as an [as] clause.) *)
(** * A Tagless Interpreter *)
(** A favorite example for motivating the power of functional programming is implementation of a simple expression language interpreter. In ML and Haskell, such interpreters are often implemented using an algebraic datatype of values, where at many points it is checked that a value was built with the right constructor of the value type. With dependent types, we can implement a%\index{tagless interpreters}% _tagless_ interpreter that both removes this source of runtime inefficiency and gives us more confidence that our implementation is correct. *)
Inductive type : Set :=
| Nat : type
| Bool : type
| Prod : type -> type -> type.
Inductive exp : type -> Set :=
| NConst : nat -> exp Nat
| Plus : exp Nat -> exp Nat -> exp Nat
| Eq : exp Nat -> exp Nat -> exp Bool
| BConst : bool -> exp Bool
| And : exp Bool -> exp Bool -> exp Bool
| If : forall t, exp Bool -> exp t -> exp t -> exp t
| Pair : forall t1 t2, exp t1 -> exp t2 -> exp (Prod t1 t2)
| Fst : forall t1 t2, exp (Prod t1 t2) -> exp t1
| Snd : forall t1 t2, exp (Prod t1 t2) -> exp t2.
(** We have a standard algebraic datatype [type], defining a type language of naturals, Booleans, and product (pair) types. Then we have the indexed inductive type [exp], where the argument to [exp] tells us the encoded type of an expression. In effect, we are defining the typing rules for expressions simultaneously with the syntax.
We can give types and expressions semantics in a new style, based critically on the chance for _type-level computation_. *)
Fixpoint typeDenote (t : type) : Set :=
match t with
| Nat => nat
| Bool => bool
| Prod t1 t2 => typeDenote t1 * typeDenote t2
end%type.
(** The [typeDenote] function compiles types of our object language into "native" Coq types. It is deceptively easy to implement. The only new thing we see is the [%]%\coqdocvar{%#<tt>#type#</tt>#%}% annotation, which tells Coq to parse the [match] expression using the notations associated with types. Without this annotation, the [*] would be interpreted as multiplication on naturals, rather than as the product type constructor. The token %\coqdocvar{%#<tt>#type#</tt>#%}% is one example of an identifier bound to a%\index{notation scope delimiter}% _notation scope delimiter_. In this book, we will not go into more detail on notation scopes, but the Coq manual can be consulted for more information.
We can define a function [expDenote] that is typed in terms of [typeDenote]. *)
Fixpoint expDenote t (e : exp t) : typeDenote t :=
match e with
| NConst n => n
| Plus e1 e2 => expDenote e1 + expDenote e2
| Eq e1 e2 => if eq_nat_dec (expDenote e1) (expDenote e2) then true else false
| BConst b => b
| And e1 e2 => expDenote e1 && expDenote e2
| If _ e' e1 e2 => if expDenote e' then expDenote e1 else expDenote e2
| Pair _ _ e1 e2 => (expDenote e1, expDenote e2)
| Fst _ _ e' => fst (expDenote e')
| Snd _ _ e' => snd (expDenote e')
end.
(* begin hide *)
(* begin thide *)
Definition sumboool := sumbool.
(* end thide *)
(* end hide *)
(** Despite the fancy type, the function definition is routine. In fact, it is less complicated than what we would write in ML or Haskell 98, since we do not need to worry about pushing final values in and out of an algebraic datatype. The only unusual thing is the use of an expression of the form [if E then true else false] in the [Eq] case. Remember that [eq_nat_dec] has a rich dependent type, rather than a simple Boolean type. Coq's native [if] is overloaded to work on a test of any two-constructor type, so we can use [if] to build a simple Boolean from the [sumbool] that [eq_nat_dec] returns.
We can implement our old favorite, a constant folding function, and prove it correct. It will be useful to write a function [pairOut] that checks if an [exp] of [Prod] type is a pair, returning its two components if so. Unsurprisingly, a first attempt leads to a type error.
[[
Definition pairOut t1 t2 (e : exp (Prod t1 t2)) : option (exp t1 * exp t2) :=
match e in (exp (Prod t1 t2)) return option (exp t1 * exp t2) with
| Pair _ _ e1 e2 => Some (e1, e2)
| _ => None
end.
]]
<<
Error: The reference t2 was not found in the current environment
>>
We run again into the problem of not being able to specify non-variable arguments in [in] clauses. The problem would just be hopeless without a use of an [in] clause, though, since the result type of the [match] depends on an argument to [exp]. Our solution will be to use a more general type, as we did for [hd]. First, we define a type-valued function to use in assigning a type to [pairOut]. *)
(* EX: Define a function [pairOut : forall t1 t2, exp (Prod t1 t2) -> option (exp t1 * exp t2)] *)
(* begin thide *)
Definition pairOutType (t : type) := option (match t with
| Prod t1 t2 => exp t1 * exp t2
| _ => unit
end).
(** When passed a type that is a product, [pairOutType] returns our final desired type. On any other input type, [pairOutType] returns the harmless [option unit], since we do not care about extracting components of non-pairs. Now [pairOut] is easy to write. *)
Definition pairOut t (e : exp t) :=
match e in (exp t) return (pairOutType t) with
| Pair _ _ e1 e2 => Some (e1, e2)
| _ => None
end.
(* end thide *)
(** With [pairOut] available, we can write [cfold] in a straightforward way. There are really no surprises beyond that Coq verifies that this code has such an expressive type, given the small annotation burden. In some places, we see that Coq's [match] annotation inference is too smart for its own good, and we have to turn that inference off with explicit [return] clauses. *)
Fixpoint cfold t (e : exp t) : exp t :=
match e with
| NConst n => NConst n
| Plus e1 e2 =>
let e1' := cfold e1 in
let e2' := cfold e2 in
match e1', e2' return exp Nat with
| NConst n1, NConst n2 => NConst (n1 + n2)
| _, _ => Plus e1' e2'
end
| Eq e1 e2 =>
let e1' := cfold e1 in
let e2' := cfold e2 in
match e1', e2' return exp Bool with
| NConst n1, NConst n2 => BConst (if eq_nat_dec n1 n2 then true else false)
| _, _ => Eq e1' e2'
end
| BConst b => BConst b
| And e1 e2 =>
let e1' := cfold e1 in
let e2' := cfold e2 in
match e1', e2' return exp Bool with
| BConst b1, BConst b2 => BConst (b1 && b2)
| _, _ => And e1' e2'
end
| If _ e e1 e2 =>
let e' := cfold e in
match e' with
| BConst true => cfold e1
| BConst false => cfold e2
| _ => If e' (cfold e1) (cfold e2)
end
| Pair _ _ e1 e2 => Pair (cfold e1) (cfold e2)
| Fst _ _ e =>
let e' := cfold e in
match pairOut e' with
| Some p => fst p
| None => Fst e'
end
| Snd _ _ e =>
let e' := cfold e in
match pairOut e' with
| Some p => snd p
| None => Snd e'
end
end.
(** The correctness theorem for [cfold] turns out to be easy to prove, once we get over one serious hurdle. *)
Theorem cfold_correct : forall t (e : exp t), expDenote e = expDenote (cfold e).
(* begin thide *)
induction e; crush.
(** The first remaining subgoal is:
[[
expDenote (cfold e1) + expDenote (cfold e2) =
expDenote
match cfold e1 with
| NConst n1 =>
match cfold e2 with
| NConst n2 => NConst (n1 + n2)
| Plus _ _ => Plus (cfold e1) (cfold e2)
| Eq _ _ => Plus (cfold e1) (cfold e2)
| BConst _ => Plus (cfold e1) (cfold e2)
| And _ _ => Plus (cfold e1) (cfold e2)
| If _ _ _ _ => Plus (cfold e1) (cfold e2)
| Pair _ _ _ _ => Plus (cfold e1) (cfold e2)
| Fst _ _ _ => Plus (cfold e1) (cfold e2)
| Snd _ _ _ => Plus (cfold e1) (cfold e2)
end
| Plus _ _ => Plus (cfold e1) (cfold e2)
| Eq _ _ => Plus (cfold e1) (cfold e2)
| BConst _ => Plus (cfold e1) (cfold e2)
| And _ _ => Plus (cfold e1) (cfold e2)
| If _ _ _ _ => Plus (cfold e1) (cfold e2)
| Pair _ _ _ _ => Plus (cfold e1) (cfold e2)
| Fst _ _ _ => Plus (cfold e1) (cfold e2)
| Snd _ _ _ => Plus (cfold e1) (cfold e2)
end
]]
We would like to do a case analysis on [cfold e1], and we attempt to do so in the way that has worked so far.
[[
destruct (cfold e1).
]]
<<
User error: e1 is used in hypothesis e
>>
Coq gives us another cryptic error message. Like so many others, this one basically means that Coq is not able to build some proof about dependent types. It is hard to generate helpful and specific error messages for problems like this, since that would require some kind of understanding of the dependency structure of a piece of code. We will encounter many examples of case-specific tricks for recovering from errors like this one.
For our current proof, we can use a tactic [dep_destruct]%\index{tactics!dep\_destruct}% defined in the book's [CpdtTactics] module. General elimination/inversion of dependently typed hypotheses is undecidable, as witnessed by a simple reduction from the known-undecidable problem of higher-order unification, which has come up a few times already. The tactic [dep_destruct] makes a best effort to handle some common cases, relying upon the more primitive %\index{tactics!dependent destruction}%[dependent destruction] tactic that comes with Coq. In a future chapter, we will learn about the explicit manipulation of equality proofs that is behind [dependent destruction]'s implementation, but for now, we treat it as a useful black box. (In Chapter 12, we will also see how [dependent destruction] forces us to make a larger philosophical commitment about our logic than we might like, and we will see some workarounds.) *)
dep_destruct (cfold e1).
(** This successfully breaks the subgoal into 5 new subgoals, one for each constructor of [exp] that could produce an [exp Nat]. Note that [dep_destruct] is successful in ruling out the other cases automatically, in effect automating some of the work that we have done manually in implementing functions like [hd] and [pairOut].
This is the only new trick we need to learn to complete the proof. We can back up and give a short, automated proof (which again is safe to skip and uses Ltac features not introduced yet). *)
Restart.
induction e; crush;
repeat (match goal with
| [ |- context[match cfold ?E with NConst _ => _ | _ => _ end] ] =>
dep_destruct (cfold E)
| [ |- context[match pairOut (cfold ?E) with Some _ => _
| None => _ end] ] =>
dep_destruct (cfold E)
| [ |- (if ?E then _ else _) = _ ] => destruct E
end; crush).
Qed.
(* end thide *)
(** With this example, we get a first taste of how to build automated proofs that adapt automatically to changes in function definitions. *)
(** * Dependently Typed Red-Black Trees *)
(** Red-black trees are a favorite purely functional data structure with an interesting invariant. We can use dependent types to guarantee that operations on red-black trees preserve the invariant. For simplicity, we specialize our red-black trees to represent sets of [nat]s. *)
Inductive color : Set := Red | Black.
Inductive rbtree : color -> nat -> Set :=
| Leaf : rbtree Black 0
| RedNode : forall n, rbtree Black n -> nat -> rbtree Black n -> rbtree Red n
| BlackNode : forall c1 c2 n, rbtree c1 n -> nat -> rbtree c2 n -> rbtree Black (S n).
(** A value of type [rbtree c d] is a red-black tree whose root has color [c] and that has black depth [d]. The latter property means that there are exactly [d] black-colored nodes on any path from the root to a leaf. *)
(** At first, it can be unclear that this choice of type indices tracks any useful property. To convince ourselves, we will prove that every red-black tree is balanced. We will phrase our theorem in terms of a depth calculating function that ignores the extra information in the types. It will be useful to parameterize this function over a combining operation, so that we can re-use the same code to calculate the minimum or maximum height among all paths from root to leaf. *)
(* EX: Prove that every [rbtree] is balanced. *)
(* begin thide *)
Require Import Max Min.
Section depth.
Variable f : nat -> nat -> nat.
Fixpoint depth c n (t : rbtree c n) : nat :=
match t with
| Leaf => 0
| RedNode _ t1 _ t2 => S (f (depth t1) (depth t2))
| BlackNode _ _ _ t1 _ t2 => S (f (depth t1) (depth t2))
end.
End depth.
(** Our proof of balanced-ness decomposes naturally into a lower bound and an upper bound. We prove the lower bound first. Unsurprisingly, a tree's black depth provides such a bound on the minimum path length. We use the richly typed procedure [min_dec] to do case analysis on whether [min X Y] equals [X] or [Y]. *)
Check min_dec.
(** %\vspace{-.15in}% [[
min_dec
: forall n m : nat, {min n m = n} + {min n m = m}
]]
*)
Theorem depth_min : forall c n (t : rbtree c n), depth min t >= n.
induction t; crush;
match goal with
| [ |- context[min ?X ?Y] ] => destruct (min_dec X Y)
end; crush.
Qed.
(** There is an analogous upper-bound theorem based on black depth. Unfortunately, a symmetric proof script does not suffice to establish it. *)
Theorem depth_max : forall c n (t : rbtree c n), depth max t <= 2 * n + 1.
induction t; crush;
match goal with
| [ |- context[max ?X ?Y] ] => destruct (max_dec X Y)
end; crush.
(** Two subgoals remain. One of them is: [[
n : nat
t1 : rbtree Black n
n0 : nat
t2 : rbtree Black n
IHt1 : depth max t1 <= n + (n + 0) + 1
IHt2 : depth max t2 <= n + (n + 0) + 1
e : max (depth max t1) (depth max t2) = depth max t1
============================
S (depth max t1) <= n + (n + 0) + 1
]]
We see that [IHt1] is _almost_ the fact we need, but it is not quite strong enough. We will need to strengthen our induction hypothesis to get the proof to go through. *)
Abort.
(** In particular, we prove a lemma that provides a stronger upper bound for trees with black root nodes. We got stuck above in a case about a red root node. Since red nodes have only black children, our IH strengthening will enable us to finish the proof. *)
Lemma depth_max' : forall c n (t : rbtree c n), match c with
| Red => depth max t <= 2 * n + 1
| Black => depth max t <= 2 * n
end.
induction t; crush;
match goal with
| [ |- context[max ?X ?Y] ] => destruct (max_dec X Y)
end; crush;
repeat (match goal with
| [ H : context[match ?C with Red => _ | Black => _ end] |- _ ] =>
destruct C
end; crush).
Qed.
(** The original theorem follows easily from the lemma. We use the tactic %\index{tactics!generalize}%[generalize pf], which, when [pf] proves the proposition [P], changes the goal from [Q] to [P -> Q]. This transformation is useful because it makes the truth of [P] manifest syntactically, so that automation machinery can rely on [P], even if that machinery is not smart enough to establish [P] on its own. *)
Theorem depth_max : forall c n (t : rbtree c n), depth max t <= 2 * n + 1.
intros; generalize (depth_max' t); destruct c; crush.
Qed.
(** The final balance theorem establishes that the minimum and maximum path lengths of any tree are within a factor of two of each other. *)
Theorem balanced : forall c n (t : rbtree c n), 2 * depth min t + 1 >= depth max t.
intros; generalize (depth_min t); generalize (depth_max t); crush.
Qed.
(* end thide *)
(** Now we are ready to implement an example operation on our trees, insertion. Insertion can be thought of as breaking the tree invariants locally but then rebalancing. In particular, in intermediate states we find red nodes that may have red children. The type [rtree] captures the idea of such a node, continuing to track black depth as a type index. *)
Inductive rtree : nat -> Set :=
| RedNode' : forall c1 c2 n, rbtree c1 n -> nat -> rbtree c2 n -> rtree n.
(** Before starting to define [insert], we define predicates capturing when a data value is in the set represented by a normal or possibly invalid tree. *)
Section present.
Variable x : nat.
Fixpoint present c n (t : rbtree c n) : Prop :=
match t with
| Leaf => False
| RedNode _ a y b => present a \/ x = y \/ present b
| BlackNode _ _ _ a y b => present a \/ x = y \/ present b
end.
Definition rpresent n (t : rtree n) : Prop :=
match t with
| RedNode' _ _ _ a y b => present a \/ x = y \/ present b
end.
End present.
(** Insertion relies on two balancing operations. It will be useful to give types to these operations using a relative of the subset types from last chapter. While subset types let us pair a value with a proof about that value, here we want to pair a value with another non-proof dependently typed value. The %\index{Gallina terms!sigT}%[sigT] type fills this role. *)
Locate "{ _ : _ & _ }".
(** %\vspace{-.15in}%[[
Notation Scope
"{ x : A & P }" := sigT (fun x : A => P)
]]
*)
Print sigT.
(** %\vspace{-.15in}%[[
Inductive sigT (A : Type) (P : A -> Type) : Type :=
existT : forall x : A, P x -> sigT P
]]
*)
(** It will be helpful to define a concise notation for the constructor of [sigT]. *)
Notation "{< x >}" := (existT _ _ x).
(** Each balance function is used to construct a new tree whose keys include the keys of two input trees, as well as a new key. One of the two input trees may violate the red-black alternation invariant (that is, it has an [rtree] type), while the other tree is known to be valid. Crucially, the two input trees have the same black depth.
A balance operation may return a tree whose root is of either color. Thus, we use a [sigT] type to package the result tree with the color of its root. Here is the definition of the first balance operation, which applies when the possibly invalid [rtree] belongs to the left of the valid [rbtree].
A quick word of encouragement: After writing this code, even I do not understand the precise details of how balancing works! I consulted Chris Okasaki's paper "Red-Black Trees in a Functional Setting" %\cite{Okasaki} %and transcribed the code to use dependent types. Luckily, the details are not so important here; types alone will tell us that insertion preserves balanced-ness, and we will prove that insertion produces trees containing the right keys.*)
Definition balance1 n (a : rtree n) (data : nat) c2 :=
match a in rtree n return rbtree c2 n
-> { c : color & rbtree c (S n) } with
| RedNode' _ c0 _ t1 y t2 =>
match t1 in rbtree c n return rbtree c0 n -> rbtree c2 n
-> { c : color & rbtree c (S n) } with
| RedNode _ a x b => fun c d =>
{<RedNode (BlackNode a x b) y (BlackNode c data d)>}
| t1' => fun t2 =>
match t2 in rbtree c n return rbtree Black n -> rbtree c2 n
-> { c : color & rbtree c (S n) } with
| RedNode _ b x c => fun a d =>
{<RedNode (BlackNode a y b) x (BlackNode c data d)>}
| b => fun a t => {<BlackNode (RedNode a y b) data t>}
end t1'
end t2
end.
(** We apply a trick that I call the%\index{convoy pattern}% _convoy pattern_. Recall that [match] annotations only make it possible to describe a dependence of a [match] _result type_ on the discriminee. There is no automatic refinement of the types of free variables. However, it is possible to effect such a refinement by finding a way to encode free variable type dependencies in the [match] result type, so that a [return] clause can express the connection.
In particular, we can extend the [match] to return _functions over the free variables whose types we want to refine_. In the case of [balance1], we only find ourselves wanting to refine the type of one tree variable at a time. We match on one subtree of a node, and we want the type of the other subtree to be refined based on what we learn. We indicate this with a [return] clause starting like [rbtree _ n -> ...], where [n] is bound in an [in] pattern. Such a [match] expression is applied immediately to the "old version" of the variable to be refined, and the type checker is happy.
Here is the symmetric function [balance2], for cases where the possibly invalid tree appears on the right rather than on the left. *)
Definition balance2 n (a : rtree n) (data : nat) c2 :=
match a in rtree n return rbtree c2 n -> { c : color & rbtree c (S n) } with
| RedNode' _ c0 _ t1 z t2 =>
match t1 in rbtree c n return rbtree c0 n -> rbtree c2 n
-> { c : color & rbtree c (S n) } with
| RedNode _ b y c => fun d a =>
{<RedNode (BlackNode a data b) y (BlackNode c z d)>}
| t1' => fun t2 =>
match t2 in rbtree c n return rbtree Black n -> rbtree c2 n
-> { c : color & rbtree c (S n) } with
| RedNode _ c z' d => fun b a =>
{<RedNode (BlackNode a data b) z (BlackNode c z' d)>}
| b => fun a t => {<BlackNode t data (RedNode a z b)>}
end t1'
end t2
end.
(** Now we are almost ready to get down to the business of writing an [insert] function. First, we enter a section that declares a variable [x], for the key we want to insert. *)
Section insert.
Variable x : nat.
(** Most of the work of insertion is done by a helper function [ins], whose return types are expressed using a type-level function [insResult]. *)
Definition insResult c n :=
match c with
| Red => rtree n
| Black => { c' : color & rbtree c' n }
end.
(** That is, inserting into a tree with root color [c] and black depth [n], the variety of tree we get out depends on [c]. If we started with a red root, then we get back a possibly invalid tree of depth [n]. If we started with a black root, we get back a valid tree of depth [n] with a root node of an arbitrary color.
Here is the definition of [ins]. Again, we do not want to dwell on the functional details. *)
Fixpoint ins c n (t : rbtree c n) : insResult c n :=
match t with
| Leaf => {< RedNode Leaf x Leaf >}
| RedNode _ a y b =>
if le_lt_dec x y
then RedNode' (projT2 (ins a)) y b
else RedNode' a y (projT2 (ins b))
| BlackNode c1 c2 _ a y b =>
if le_lt_dec x y
then
match c1 return insResult c1 _ -> _ with
| Red => fun ins_a => balance1 ins_a y b
| _ => fun ins_a => {< BlackNode (projT2 ins_a) y b >}
end (ins a)
else
match c2 return insResult c2 _ -> _ with
| Red => fun ins_b => balance2 ins_b y a
| _ => fun ins_b => {< BlackNode a y (projT2 ins_b) >}
end (ins b)
end.
(** The one new trick is a variation of the convoy pattern. In each of the last two pattern matches, we want to take advantage of the typing connection between the trees [a] and [b]. We might %\%naive%{}%ly apply the convoy pattern directly on [a] in the first [match] and on [b] in the second. This satisfies the type checker per se, but it does not satisfy the termination checker. Inside each [match], we would be calling [ins] recursively on a locally bound variable. The termination checker is not smart enough to trace the dataflow into that variable, so the checker does not know that this recursive argument is smaller than the original argument. We make this fact clearer by applying the convoy pattern on _the result of a recursive call_, rather than just on that call's argument.
Finally, we are in the home stretch of our effort to define [insert]. We just need a few more definitions of non-recursive functions. First, we need to give the final characterization of [insert]'s return type. Inserting into a red-rooted tree gives a black-rooted tree where black depth has increased, and inserting into a black-rooted tree gives a tree where black depth has stayed the same and where the root is an arbitrary color. *)
Definition insertResult c n :=
match c with
| Red => rbtree Black (S n)
| Black => { c' : color & rbtree c' n }
end.
(** A simple clean-up procedure translates [insResult]s into [insertResult]s. *)
Definition makeRbtree c n : insResult c n -> insertResult c n :=
match c with
| Red => fun r =>
match r with
| RedNode' _ _ _ a x b => BlackNode a x b
end
| Black => fun r => r
end.
(** We modify Coq's default choice of implicit arguments for [makeRbtree], so that we do not need to specify the [c] and [n] arguments explicitly in later calls. *)
Implicit Arguments makeRbtree [c n].
(** Finally, we define [insert] as a simple composition of [ins] and [makeRbtree]. *)
Definition insert c n (t : rbtree c n) : insertResult c n :=
makeRbtree (ins t).
(** As we noted earlier, the type of [insert] guarantees that it outputs balanced trees whose depths have not increased too much. We also want to know that [insert] operates correctly on trees interpreted as finite sets, so we finish this section with a proof of that fact. *)
Section present.
Variable z : nat.
(** The variable [z] stands for an arbitrary key. We will reason about [z]'s presence in particular trees. As usual, outside the section the theorems we prove will quantify over all possible keys, giving us the facts we wanted.
We start by proving the correctness of the balance operations. It is useful to define a custom tactic [present_balance] that encapsulates the reasoning common to the two proofs. We use the keyword %\index{Vernacular commands!Ltac}%[Ltac] to assign a name to a proof script. This particular script just iterates between [crush] and identification of a tree that is being pattern-matched on and should be destructed. *)
Ltac present_balance :=
crush;
repeat (match goal with
| [ _ : context[match ?T with Leaf => _ | _ => _ end] |- _ ] =>
dep_destruct T
| [ |- context[match ?T with Leaf => _ | _ => _ end] ] => dep_destruct T
end; crush).
(** The balance correctness theorems are simple first-order logic equivalences, where we use the function [projT2] to project the payload of a [sigT] value. *)
Lemma present_balance1 : forall n (a : rtree n) (y : nat) c2 (b : rbtree c2 n),
present z (projT2 (balance1 a y b))
<-> rpresent z a \/ z = y \/ present z b.
destruct a; present_balance.
Qed.
Lemma present_balance2 : forall n (a : rtree n) (y : nat) c2 (b : rbtree c2 n),
present z (projT2 (balance2 a y b))
<-> rpresent z a \/ z = y \/ present z b.
destruct a; present_balance.
Qed.
(** To state the theorem for [ins], it is useful to define a new type-level function, since [ins] returns different result types based on the type indices passed to it. Recall that [x] is the section variable standing for the key we are inserting. *)
Definition present_insResult c n :=
match c return (rbtree c n -> insResult c n -> Prop) with
| Red => fun t r => rpresent z r <-> z = x \/ present z t
| Black => fun t r => present z (projT2 r) <-> z = x \/ present z t
end.
(** Now the statement and proof of the [ins] correctness theorem are straightforward, if verbose. We proceed by induction on the structure of a tree, followed by finding case analysis opportunities on expressions we see being analyzed in [if] or [match] expressions. After that, we pattern-match to find opportunities to use the theorems we proved about balancing. Finally, we identify two variables that are asserted by some hypothesis to be equal, and we use that hypothesis to replace one variable with the other everywhere. *)
Theorem present_ins : forall c n (t : rbtree c n),
present_insResult t (ins t).
induction t; crush;
repeat (match goal with
| [ _ : context[if ?E then _ else _] |- _ ] => destruct E
| [ |- context[if ?E then _ else _] ] => destruct E
| [ _ : context[match ?C with Red => _ | Black => _ end]
|- _ ] => destruct C
end; crush);
try match goal with
| [ _ : context[balance1 ?A ?B ?C] |- _ ] =>
generalize (present_balance1 A B C)
end;
try match goal with
| [ _ : context[balance2 ?A ?B ?C] |- _ ] =>
generalize (present_balance2 A B C)
end;
try match goal with
| [ |- context[balance1 ?A ?B ?C] ] =>
generalize (present_balance1 A B C)
end;
try match goal with
| [ |- context[balance2 ?A ?B ?C] ] =>
generalize (present_balance2 A B C)
end;
crush;
match goal with
| [ z : nat, x : nat |- _ ] =>
match goal with
| [ H : z = x |- _ ] => rewrite H in *; clear H
end
end;
tauto.
Qed.
(** The hard work is done. The most readable way to state correctness of [insert] involves splitting the property into two color-specific theorems. We write a tactic to encapsulate the reasoning steps that work to establish both facts. *)
Ltac present_insert :=
unfold insert; intros n t; inversion t;
generalize (present_ins t); simpl;
dep_destruct (ins t); tauto.
Theorem present_insert_Red : forall n (t : rbtree Red n),
present z (insert t)
<-> (z = x \/ present z t).
present_insert.
Qed.
Theorem present_insert_Black : forall n (t : rbtree Black n),
present z (projT2 (insert t))
<-> (z = x \/ present z t).
present_insert.
Qed.
End present.
End insert.
(** We can generate executable OCaml code with the command %\index{Vernacular commands!Recursive Extraction}%[Recursive Extraction insert], which also automatically outputs the OCaml versions of all of [insert]'s dependencies. In our previous extractions, we wound up with clean OCaml code. Here, we find uses of %\index{Obj.magic}%<<Obj.magic>>, OCaml's unsafe cast operator for tweaking the apparent type of an expression in an arbitrary way. Casts appear for this example because the return type of [insert] depends on the _value_ of the function's argument, a pattern that OCaml cannot handle. Since Coq's type system is much more expressive than OCaml's, such casts are unavoidable in general. Since the OCaml type-checker is no longer checking full safety of programs, we must rely on Coq's extractor to use casts only in provably safe ways. *)
(* begin hide *)
Recursive Extraction insert.
(* end hide *)
(** * A Certified Regular Expression Matcher *)
(** Another interesting example is regular expressions with dependent types that express which predicates over strings particular regexps implement. We can then assign a dependent type to a regular expression matching function, guaranteeing that it always decides the string property that we expect it to decide.
Before defining the syntax of expressions, it is helpful to define an inductive type capturing the meaning of the Kleene star. That is, a string [s] matches regular expression [star e] if and only if [s] can be decomposed into a sequence of substrings that all match [e]. We use Coq's string support, which comes through a combination of the [String] library and some parsing notations built into Coq. Operators like [++] and functions like [length] that we know from lists are defined again for strings. Notation scopes help us control which versions we want to use in particular contexts.%\index{Vernacular commands!Open Scope}% *)
Require Import Ascii String.
Open Scope string_scope.
Section star.
Variable P : string -> Prop.
Inductive star : string -> Prop :=
| Empty : star ""
| Iter : forall s1 s2,
P s1
-> star s2
-> star (s1 ++ s2).
End star.
(** Now we can make our first attempt at defining a [regexp] type that is indexed by predicates on strings, such that the index of a [regexp] tells us which language (string predicate) it recognizes. Here is a reasonable-looking definition that is restricted to constant characters and concatenation. We use the constructor [String], which is the analogue of list cons for the type [string], where [""] is like list nil.
[[
Inductive regexp : (string -> Prop) -> Set :=
| Char : forall ch : ascii,
regexp (fun s => s = String ch "")
| Concat : forall (P1 P2 : string -> Prop) (r1 : regexp P1) (r2 : regexp P2),
regexp (fun s => exists s1, exists s2, s = s1 ++ s2 /\ P1 s1 /\ P2 s2).
]]
<<
User error: Large non-propositional inductive types must be in Type
>>
What is a %\index{large inductive types}%large inductive type? In Coq, it is an inductive type that has a constructor that quantifies over some type of type [Type]. We have not worked with [Type] very much to this point. Every term of CIC has a type, including [Set] and [Prop], which are assigned type [Type]. The type [string -> Prop] from the failed definition also has type [Type].
It turns out that allowing large inductive types in [Set] leads to contradictions when combined with certain kinds of classical logic reasoning. Thus, by default, such types are ruled out. There is a simple fix for our [regexp] definition, which is to place our new type in [Type]. While fixing the problem, we also expand the list of constructors to cover the remaining regular expression operators. *)
Inductive regexp : (string -> Prop) -> Type :=
| Char : forall ch : ascii,
regexp (fun s => s = String ch "")
| Concat : forall P1 P2 (r1 : regexp P1) (r2 : regexp P2),
regexp (fun s => exists s1, exists s2, s = s1 ++ s2 /\ P1 s1 /\ P2 s2)
| Or : forall P1 P2 (r1 : regexp P1) (r2 : regexp P2),
regexp (fun s => P1 s \/ P2 s)
| Star : forall P (r : regexp P),
regexp (star P).
(** Many theorems about strings are useful for implementing a certified regexp matcher, and few of them are in the [String] library. The book source includes statements, proofs, and hint commands for a handful of such omitted theorems. Since they are orthogonal to our use of dependent types, we hide them in the rendered versions of this book. *)
(* begin hide *)
Open Scope specif_scope.
Lemma length_emp : length "" <= 0.
crush.
Qed.
Lemma append_emp : forall s, s = "" ++ s.
crush.
Qed.
Ltac substring :=
crush;
repeat match goal with
| [ |- context[match ?N with O => _ | S _ => _ end] ] => destruct N; crush
end.
Lemma substring_le : forall s n m,
length (substring n m s) <= m.
induction s; substring.
Qed.
Lemma substring_all : forall s,
substring 0 (length s) s = s.
induction s; substring.
Qed.
Lemma substring_none : forall s n,
substring n 0 s = "".
induction s; substring.
Qed.
Hint Rewrite substring_all substring_none.
Lemma substring_split : forall s m,
substring 0 m s ++ substring m (length s - m) s = s.
induction s; substring.
Qed.
Lemma length_app1 : forall s1 s2,
length s1 <= length (s1 ++ s2).
induction s1; crush.
Qed.
Hint Resolve length_emp append_emp substring_le substring_split length_app1.
Lemma substring_app_fst : forall s2 s1 n,
length s1 = n
-> substring 0 n (s1 ++ s2) = s1.
induction s1; crush.
Qed.
Lemma substring_app_snd : forall s2 s1 n,
length s1 = n
-> substring n (length (s1 ++ s2) - n) (s1 ++ s2) = s2.
Hint Rewrite <- minus_n_O.
induction s1; crush.
Qed.
Hint Rewrite substring_app_fst substring_app_snd using solve [trivial].
(* end hide *)
(** A few auxiliary functions help us in our final matcher definition. The function [split] will be used to implement the regexp concatenation case. *)
Section split.
Variables P1 P2 : string -> Prop.
Variable P1_dec : forall s, {P1 s} + {~ P1 s}.
Variable P2_dec : forall s, {P2 s} + {~ P2 s}.
(** We require a choice of two arbitrary string predicates and functions for deciding them. *)
Variable s : string.
(** Our computation will take place relative to a single fixed string, so it is easiest to make it a [Variable], rather than an explicit argument to our functions. *)
(** The function [split'] is the workhorse behind [split]. It searches through the possible ways of splitting [s] into two pieces, checking the two predicates against each such pair. The execution of [split'] progresses right-to-left, from splitting all of [s] into the first piece to splitting all of [s] into the second piece. It takes an extra argument, [n], which specifies how far along we are in this search process. *)
Definition split' : forall n : nat, n <= length s
-> {exists s1, exists s2, length s1 <= n /\ s1 ++ s2 = s /\ P1 s1 /\ P2 s2}
+ {forall s1 s2, length s1 <= n -> s1 ++ s2 = s -> ~ P1 s1 \/ ~ P2 s2}.
refine (fix F (n : nat) : n <= length s
-> {exists s1, exists s2, length s1 <= n /\ s1 ++ s2 = s /\ P1 s1 /\ P2 s2}
+ {forall s1 s2, length s1 <= n -> s1 ++ s2 = s -> ~ P1 s1 \/ ~ P2 s2} :=
match n with
| O => fun _ => Reduce (P1_dec "" && P2_dec s)
| S n' => fun _ => (P1_dec (substring 0 (S n') s)
&& P2_dec (substring (S n') (length s - S n') s))
|| F n' _
end); clear F; crush; eauto 7;
match goal with
| [ _ : length ?S <= 0 |- _ ] => destruct S
| [ _ : length ?S' <= S ?N |- _ ] => destruct (eq_nat_dec (length S') (S N))
end; crush.
Defined.
(** There is one subtle point in the [split'] code that is worth mentioning. The main body of the function is a [match] on [n]. In the case where [n] is known to be [S n'], we write [S n'] in several places where we might be tempted to write [n]. However, without further work to craft proper [match] annotations, the type-checker does not use the equality between [n] and [S n']. Thus, it is common to see patterns repeated in [match] case bodies in dependently typed Coq code. We can at least use a [let] expression to avoid copying the pattern more than once, replacing the first case body with:
[[
| S n' => fun _ => let n := S n' in
(P1_dec (substring 0 n s)
&& P2_dec (substring n (length s - n) s))
|| F n' _
]]
The [split] function itself is trivial to implement in terms of [split']. We just ask [split'] to begin its search with [n = length s]. *)
Definition split : {exists s1, exists s2, s = s1 ++ s2 /\ P1 s1 /\ P2 s2}
+ {forall s1 s2, s = s1 ++ s2 -> ~ P1 s1 \/ ~ P2 s2}.
refine (Reduce (split' (n := length s) _)); crush; eauto.
Defined.
End split.
Implicit Arguments split [P1 P2].
(* begin hide *)
Lemma app_empty_end : forall s, s ++ "" = s.
induction s; crush.
Qed.
Hint Rewrite app_empty_end.
Lemma substring_self : forall s n,
n <= 0
-> substring n (length s - n) s = s.
induction s; substring.
Qed.
Lemma substring_empty : forall s n m,
m <= 0
-> substring n m s = "".
induction s; substring.
Qed.
Hint Rewrite substring_self substring_empty using omega.
Lemma substring_split' : forall s n m,
substring n m s ++ substring (n + m) (length s - (n + m)) s
= substring n (length s - n) s.
Hint Rewrite substring_split.
induction s; substring.
Qed.
Lemma substring_stack : forall s n2 m1 m2,
m1 <= m2
-> substring 0 m1 (substring n2 m2 s)
= substring n2 m1 s.
induction s; substring.
Qed.
Ltac substring' :=
crush;
repeat match goal with
| [ |- context[match ?N with O => _ | S _ => _ end] ] => case_eq N; crush
end.
Lemma substring_stack' : forall s n1 n2 m1 m2,
n1 + m1 <= m2
-> substring n1 m1 (substring n2 m2 s)
= substring (n1 + n2) m1 s.
induction s; substring';
match goal with
| [ |- substring ?N1 _ _ = substring ?N2 _ _ ] =>
replace N1 with N2; crush
end.
Qed.
Lemma substring_suffix : forall s n,
n <= length s
-> length (substring n (length s - n) s) = length s - n.
induction s; substring.
Qed.
Lemma substring_suffix_emp' : forall s n m,
substring n (S m) s = ""
-> n >= length s.
induction s; crush;
match goal with
| [ |- ?N >= _ ] => destruct N; crush
end;
match goal with
[ |- S ?N >= S ?E ] => assert (N >= E); [ eauto | omega ]
end.
Qed.
Lemma substring_suffix_emp : forall s n m,
substring n m s = ""
-> m > 0
-> n >= length s.
destruct m as [ | m]; [crush | intros; apply substring_suffix_emp' with m; assumption].
Qed.
Hint Rewrite substring_stack substring_stack' substring_suffix
using omega.
Lemma minus_minus : forall n m1 m2,
m1 + m2 <= n
-> n - m1 - m2 = n - (m1 + m2).
intros; omega.
Qed.
Lemma plus_n_Sm' : forall n m : nat, S (n + m) = m + S n.
intros; omega.
Qed.
Hint Rewrite minus_minus using omega.
(* end hide *)
(** One more helper function will come in handy: [dec_star], for implementing another linear search through ways of splitting a string, this time for implementing the Kleene star. *)
Section dec_star.
Variable P : string -> Prop.
Variable P_dec : forall s, {P s} + {~ P s}.
(** Some new lemmas and hints about the [star] type family are useful. We omit them here; they are included in the book source at this point. *)
(* begin hide *)
Hint Constructors star.
Lemma star_empty : forall s,
length s = 0
-> star P s.
destruct s; crush.
Qed.
Lemma star_singleton : forall s, P s -> star P s.
intros; rewrite <- (app_empty_end s); auto.
Qed.
Lemma star_app : forall s n m,
P (substring n m s)
-> star P (substring (n + m) (length s - (n + m)) s)
-> star P (substring n (length s - n) s).
induction n; substring;
match goal with
| [ H : P (substring ?N ?M ?S) |- _ ] =>
solve [ rewrite <- (substring_split S M); auto
| rewrite <- (substring_split' S N M); auto ]
end.
Qed.
Hint Resolve star_empty star_singleton star_app.
Variable s : string.
Lemma star_inv : forall s,
star P s
-> s = ""
\/ exists i, i < length s
/\ P (substring 0 (S i) s)
/\ star P (substring (S i) (length s - S i) s).
Hint Extern 1 (exists i : nat, _) =>
match goal with
| [ H : P (String _ ?S) |- _ ] => exists (length S); crush
end.
induction 1; [
crush
| match goal with
| [ _ : P ?S |- _ ] => destruct S; crush
end
].
Qed.
Lemma star_substring_inv : forall n,
n <= length s
-> star P (substring n (length s - n) s)
-> substring n (length s - n) s = ""
\/ exists l, l < length s - n
/\ P (substring n (S l) s)
/\ star P (substring (n + S l) (length s - (n + S l)) s).
Hint Rewrite plus_n_Sm'.
intros;
match goal with
| [ H : star _ _ |- _ ] => generalize (star_inv H); do 3 crush; eauto
end.
Qed.
(* end hide *)
(** The function [dec_star''] implements a single iteration of the star. That is, it tries to find a string prefix matching [P], and it calls a parameter function on the remainder of the string. *)
Section dec_star''.
Variable n : nat.
(** Variable [n] is the length of the prefix of [s] that we have already processed. *)
Variable P' : string -> Prop.
Variable P'_dec : forall n' : nat, n' > n
-> {P' (substring n' (length s - n') s)}
+ {~ P' (substring n' (length s - n') s)}.
(** When we use [dec_star''], we will instantiate [P'_dec] with a function for continuing the search for more instances of [P] in [s]. *)
(** Now we come to [dec_star''] itself. It takes as an input a natural [l] that records how much of the string has been searched so far, as we did for [split']. The return type expresses that [dec_star''] is looking for an index into [s] that splits [s] into a nonempty prefix and a suffix, such that the prefix satisfies [P] and the suffix satisfies [P']. *)
Definition dec_star'' : forall l : nat,
{exists l', S l' <= l
/\ P (substring n (S l') s) /\ P' (substring (n + S l') (length s - (n + S l')) s)}
+ {forall l', S l' <= l
-> ~ P (substring n (S l') s)
\/ ~ P' (substring (n + S l') (length s - (n + S l')) s)}.
refine (fix F (l : nat) : {exists l', S l' <= l
/\ P (substring n (S l') s) /\ P' (substring (n + S l') (length s - (n + S l')) s)}
+ {forall l', S l' <= l
-> ~ P (substring n (S l') s)
\/ ~ P' (substring (n + S l') (length s - (n + S l')) s)} :=
match l with
| O => _
| S l' =>
(P_dec (substring n (S l') s) && P'_dec (n' := n + S l') _)
|| F l'
end); clear F; crush; eauto 7;
match goal with
| [ H : ?X <= S ?Y |- _ ] => destruct (eq_nat_dec X (S Y)); crush
end.
Defined.
End dec_star''.
(* begin hide *)
Lemma star_length_contra : forall n,
length s > n
-> n >= length s
-> False.
crush.
Qed.
Lemma star_length_flip : forall n n',
length s - n <= S n'
-> length s > n
-> length s - n > 0.
crush.
Qed.
Hint Resolve star_length_contra star_length_flip substring_suffix_emp.
(* end hide *)
(** The work of [dec_star''] is nested inside another linear search by [dec_star'], which provides the final functionality we need, but for arbitrary suffixes of [s], rather than just for [s] overall. *)
Definition dec_star' : forall n n' : nat, length s - n' <= n
-> {star P (substring n' (length s - n') s)}
+ {~ star P (substring n' (length s - n') s)}.
refine (fix F (n n' : nat) : length s - n' <= n
-> {star P (substring n' (length s - n') s)}
+ {~ star P (substring n' (length s - n') s)} :=
match n with
| O => fun _ => Yes
| S n'' => fun _ =>
le_gt_dec (length s) n'
|| dec_star'' (n := n') (star P)
(fun n0 _ => Reduce (F n'' n0 _)) (length s - n')
end); clear F; crush; eauto;
match goal with
| [ H : star _ _ |- _ ] => apply star_substring_inv in H; crush; eauto
end;
match goal with
| [ H1 : _ < _ - _, H2 : forall l' : nat, _ <= _ - _ -> _ |- _ ] =>
generalize (H2 _ (lt_le_S _ _ H1)); tauto
end.
Defined.
(** Finally, we have [dec_star], defined by straightforward reduction from [dec_star']. *)
Definition dec_star : {star P s} + {~ star P s}.
refine (Reduce (dec_star' (n := length s) 0 _)); crush.
Defined.
End dec_star.
(* begin hide *)
Lemma app_cong : forall x1 y1 x2 y2,
x1 = x2
-> y1 = y2
-> x1 ++ y1 = x2 ++ y2.
congruence.
Qed.
Hint Resolve app_cong.
(* end hide *)
(** With these helper functions completed, the implementation of our [matches] function is refreshingly straightforward. We only need one small piece of specific tactic work beyond what [crush] does for us. *)
Definition matches : forall P (r : regexp P) s, {P s} + {~ P s}.
refine (fix F P (r : regexp P) s : {P s} + {~ P s} :=
match r with
| Char ch => string_dec s (String ch "")
| Concat _ _ r1 r2 => Reduce (split (F _ r1) (F _ r2) s)
| Or _ _ r1 r2 => F _ r1 s || F _ r2 s
| Star _ r => dec_star _ _ _
end); crush;
match goal with
| [ H : _ |- _ ] => generalize (H _ _ (eq_refl _))
end; tauto.
Defined.
(** It is interesting to pause briefly to consider alternate implementations of [matches]. Dependent types give us much latitude in how specific correctness properties may be encoded with types. For instance, we could have made [regexp] a non-indexed inductive type, along the lines of what is possible in traditional ML and Haskell. We could then have implemented a recursive function to map [regexp]s to their intended meanings, much as we have done with types and programs in other examples. That style is compatible with the [refine]-based approach that we have used here, and it might be an interesting exercise to redo the code from this subsection in that alternate style or some further encoding of the reader's choice. The main advantage of indexed inductive types is that they generally lead to the smallest amount of code. *)
(* begin hide *)
Example hi := Concat (Char "h"%char) (Char "i"%char).
Eval hnf in matches hi "hi".
Eval hnf in matches hi "bye".
Example a_b := Or (Char "a"%char) (Char "b"%char).
Eval hnf in matches a_b "".
Eval hnf in matches a_b "a".
Eval hnf in matches a_b "aa".
Eval hnf in matches a_b "b".
(* end hide *)
(** Many regular expression matching problems are easy to test. The reader may run each of the following queries to verify that it gives the correct answer. We use evaluation strategy %\index{tactics!hnf}%[hnf] to reduce each term to%\index{head-normal form}% _head-normal form_, where the datatype constructor used to build its value is known. (Further reduction would involve wasteful simplification of proof terms justifying the answers of our procedures.) *)
Example a_star := Star (Char "a"%char).
Eval hnf in matches a_star "".
Eval hnf in matches a_star "a".
Eval hnf in matches a_star "b".
Eval hnf in matches a_star "aa".
(** Evaluation inside Coq does not scale very well, so it is easy to build other tests that run for hours or more. Such cases are better suited to execution with the extracted OCaml code. *)
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream SRL-based FIFO register (64 bit datapath)
*/
module axis_srl_register_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_reg[1:0];
reg valid_reg[1:0];
reg ptr_reg = 0;
reg full_reg = 0;
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = data_reg[ptr_reg];
assign input_axis_tready = ~full_reg;
assign output_axis_tvalid = valid_reg[ptr_reg];
integer i;
initial begin
for (i = 0; i < 2; i = i + 1) begin
data_reg[i] <= 0;
valid_reg[i] <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
end else begin
// transfer empty to full
full_reg <= ~output_axis_tready & output_axis_tvalid;
// transfer in if not full
if (input_axis_tready) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
valid_reg[0] <= input_axis_tvalid;
for (i = 0; i < 1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
valid_reg[i+1] <= valid_reg[i];
end
ptr_reg <= valid_reg[0];
end
if (output_axis_tready) begin
ptr_reg <= 0;
end
end
end
endmodule
|
module inicial ( botao, aberto, fechado, motor, sentido, ledVerde, ledVermelho, display, clock );
input botao, aberto, fechado, motor, sentido, clock;
output ledVerde, ledVermelho;
output [6:0] display;
reg [1:0] estado;
reg [4:0] entrada;
reg [6:0] tmpDisplay;
reg tmpLedVerde, tmpLedVermelho;
parameter Fechado = 2'b00, Abrindo = 2'b01, Aberto = 2'b10, Fechando = 2'b11;
initial estado = Fechado;
always @(posedge clock)begin
entrada[4] = botao;
entrada[3] = aberto;
entrada[2] = fechado;
entrada[1] = motor;
entrada[0] = sentido;
case( estado )
Fechado: begin
tmpDisplay = 7'b0001110;
tmpLedVerde = 0;
tmpLedVermelho = 0;
if( entrada == 5'b10110 ) // botao == 1 && aberto == 0 && fechado == 1 && motor == 1 && sentido == 0
estado = Abrindo;
end
Abrindo: begin
tmpDisplay = 7'b1000000;
tmpLedVerde = 1;
tmpLedVermelho = 0;
if( entrada == 5'b10010 ) // botao == 1 && aberto == 0 && fechado == 0 && motor == 1 && sentido == 0
estado = Aberto;
if( entrada == 5'b00010 ) // botao == 0 && aberto == 0 && fechado == 0 && motor == 1 && sentido == 0
estado = Fechando;
end
Aberto: begin
tmpDisplay = 7'b0001000;
tmpLedVerde = 0;
tmpLedVermelho = 0;
if( entrada == 5'b01011 ) // botao == 0 && aberto == 1 && fechado == 0 && motor == 1 && sentido == 1
estado = Fechando;
end
Fechando: begin
tmpDisplay = 7'b1000000;
tmpLedVerde = 0;
tmpLedVermelho = 1;
if( entrada == 5'b10011 ) // botao == 1 && aberto == 0 && fechado == 0 && motor == 1 && sentido == 1
estado = Abrindo;
if( entrada == 5'b00011 ) // botao == 0 && aberto == 0 && fechado == 0 && motor == 1 && sentido == 1
estado = Fechado;
end
default: estado = Fechado;
endcase
end
assign display= tmpDisplay;
assign ledVerde = tmpLedVerde;
assign ledVermelho = tmpLedVermelho;
endmodule
module maquina(SW,LEDG,LEDR,HEX0, CLK);
input [4:0] SW;
input CLK;
output [0:0] LEDG, LEDR;
output [6:0] HEX0;
inicial a( SW[4], SW[3], SW[2], SW[1], SW[0], LEDG[0], LEDR[0], HEX0, CLK);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__EINVP_PP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVP_PP_SYMBOL_V
|
module regaccess(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output [6:0] regnum,
input [7:0] regdata_read,
output [7:0] regdata_write,
output read,
output write
);
wire done;
wire [7:0] din;
wire [7:0] dout;
reg [6:0] regnum_d, regnum_q;
reg we_d, we_q;
reg ss_d, ss_q;
reg first_d, first_q;
reg read_d, read_q;
reg write_d, write_q;
assign regnum = regnum_q;
assign read = read_q;
assign write = write_q;
assign regdata_write = dout;
assign din = (read_q? regdata_read : 8'b0);
spi_slave reg_spi
(
.clk(clk), .rst(rst),
.ss(ss), .mosi(mosi), .miso(miso), .sck(sck),
.done(done), .din(din), .din_update(read_q), .dout(dout)
);
always @(*) begin
ss_d = ss;
we_d = we_q;
first_d = first_q;
regnum_d = regnum_q;
read_d = 1'b0;
write_d = 1'b0;
if (ss_q) begin
we_d = 1'b0;
first_d = 1'b1;
end else if (done) begin
if (first_q) begin
regnum_d = dout[6:0];
we_d = !dout[7];
read_d = dout[7];
end else if (we_q) begin
write_d = 1'b1;
end else begin
regnum_d = dout[6:0];
read_d = 1'b1;
end
first_d = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
we_q <= 1'b0;
first_q <= 1'b1;
regnum_q <= 6'b0;
read_q <= 1'b0;
write_q <= 1'b0;
end else begin
we_q <= we_d;
first_q <= first_d;
regnum_q <= regnum_d;
read_q <= read_d;
write_q <= write_d;
end
ss_q <= ss_d;
end
endmodule // regaccess
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111A_SYMBOL_V
`define SKY130_FD_SC_LS__O2111A_SYMBOL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2111a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111A_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
reg [15:0] v1;
reg [15:0] v2;
reg [15:0] v3;
integer nosplit;
always @ (posedge clk) begin
// write needed so that V3Dead doesn't kill v0..v3
$write(" values %x %x %x\n", v1, v2, v3);
// Locally-set 'nosplit' will prevent the if from splitting
// in splitAlwaysAll(). This whole always block should still be
// intact when we call splitReorderAll() which is the subject
// of this test.
nosplit = cyc;
if (nosplit > 2) begin
/* S1 */ v1 <= 16'h0;
/* S2 */ v1 <= m_din;
/* S3 */ if (m_din == 16'h0) begin
/* X1 */ v2 <= v1;
/* X2 */ v3 <= v2;
end
end
// We expect to swap S2 and S3, and to swap X1 and X2.
// We can check that this worked by the absense of dly vars
// in the generated output; if the reorder fails (or is disabled)
// we should see dly vars for v1 and v2.
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
`timescale 1ns / 1ns
/*
* File : Divide.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Neil Russell
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 6-Nov-2012 NJR Initial design.
*
* Description:
* A multi-cycle 32-bit divider.
*
* On any cycle that one of OP_div or OP_divu are true, the Dividend and
* Divisor will be captured and a multi-cycle divide operation initiated.
* Stall will go true on the next cycle and the first cycle of the divide
* operation completed. After some time (about 32 cycles), Stall will go
* false on the same cycle that the result becomes valid. OP_div or OP_divu
* will abort any currently running divide operation and initiate a new one.
*/
module Divide(
input clock,
input reset,
input OP_div, // True to initiate a signed divide
input OP_divu, // True to initiate an unsigned divide
input [31:0] Dividend,
input [31:0] Divisor,
output [31:0] Quotient,
output [31:0] Remainder,
output Stall, // True while calculating
//Voter Signals for Registers
input active, // True if the divider is running
input neg, // True if the result will be negative
input [31:0] result, // Begin with dividend, end with quotient
input [31:0] denom, // Divisor
input [31:0] work,
output reg vote_active, // True if the divider is running
output reg vote_neg, // True if the result will be negative
output reg [31:0] vote_result, // Begin with dividend, end with quotient
output reg [31:0] vote_denom, // Divisor
output reg [31:0] vote_work
);
reg [4:0] cycle; // Number of cycles to go
// Calculate the current digit
wire [32:0] sub = { work[30:0], result[31] } - denom;
// Send the results to our master
assign Quotient = !neg ? result : -result;
assign Remainder = work;
assign Stall = active;
// The state machine
always @(posedge clock) begin
if (reset) begin
vote_active <= 0;
vote_neg <= 0;
cycle <= 0;
vote_result <= 0;
vote_denom <= 0;
vote_work <= 0;
end
else begin
if (OP_div) begin
// Set up for a signed divide. Remember the resulting sign,
// and make the operands positive.
cycle <= 5'd31;
vote_result <= (Dividend[31] == 0) ? Dividend : -Dividend;
vote_denom <= (Divisor[31] == 0) ? Divisor : -Divisor;
vote_work <= 32'b0;
vote_neg <= Dividend[31] ^ Divisor[31];
vote_active <= 1;
end
else if (OP_divu) begin
// Set up for an unsigned divide.
cycle <= 5'd31;
vote_result <= Dividend;
vote_denom <= Divisor;
vote_work <= 32'b0;
vote_neg <= 0;
vote_active <= 1;
end
else if (active) begin
// Run an iteration of the divide.
if (sub[32] == 0) begin
vote_work <= sub[31:0];
vote_result <= {result[30:0], 1'b1};
end
else begin
vote_work <= {work[30:0], result[31]};
vote_result <= {result[30:0], 1'b0};
end
if (cycle == 0) begin
vote_active <= 0;
end
cycle <= cycle - 5'd1;
end
end
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: pass_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pass_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/pass_new.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/pass_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/pass_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pass_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pass_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pass_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pass_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pass_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pass_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hd__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire clkn;
// Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , GATE, clkn );
and and0 (GCLK , m0, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V |
module UpCounter(clock,reset,count,data_o);
parameter Size = 8;
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
input wire [('b1) - ('b1):0] count;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (count) begin
data_o <= data_o + 1;
end
end
end
endmodule // UpCounter
module UDCounter(clock,reset,count,direction,data_o);
parameter Size = 8;
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
input wire [('b1) - ('b1):0] count;
input wire [('b1) - ('b1):0] direction;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (count) begin
case (direction)
'b0: data_o <= data_o + 1;
'b1: data_o <= data_o - 1;
endcase
end
end
end
endmodule // UDCounter
module Mux2(select,data_i00,data_i01,data_o);
parameter Size = 8;
input wire [('d1) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
output reg [(Size) - ('b1):0] data_o;
always @ (select or data_i00 or data_i01) begin
case (select)
'b0:data_o = data_i00;
'b1:data_o = data_i01;
endcase // case (select)
end
endmodule // Mux2
module Mux4(select,data_i00,data_i01,data_i02,data_i03,data_o);
parameter Size = 8;
input wire [('d2) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03) begin
case (select)
'b00: data_o = data_i00;
'b01: data_o = data_i01;
'b10: data_o = data_i02;
'b11: data_o = data_i03;
endcase
end
endmodule // Mux4
module Mux8(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_o);
parameter Size = 8;
input wire [('d3) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07) begin
case (select)
'b000: data_o = data_i00;
'b001: data_o = data_i01;
'b010: data_o = data_i02;
'b011: data_o = data_i03;
'b100: data_o = data_i04;
'b101: data_o = data_i05;
'b110: data_o = data_i06;
'b111: data_o = data_i07;
endcase
end
endmodule // Mux8
module Mux16(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_o);
parameter Size = 8;
input wire [('d4) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15) begin
case (select)
'b0000: data_o = data_i00;
'b0001: data_o = data_i01;
'b0010: data_o = data_i02;
'b0011: data_o = data_i03;
'b0100: data_o = data_i04;
'b0101: data_o = data_i05;
'b0110: data_o = data_i06;
'b0111: data_o = data_i07;
'b1000: data_o = data_i08;
'b1001: data_o = data_i09;
'b1010: data_o = data_i10;
'b1011: data_o = data_i11;
'b1100: data_o = data_i12;
'b1101: data_o = data_i13;
'b1110: data_o = data_i14;
'b1111: data_o = data_i15;
endcase
end
endmodule // Mux16
module Mux32(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_i16,data_i17,data_i18,data_i19,data_i20,data_i21,data_i22,data_i23,data_i24,data_i25,data_i26,data_i27,data_i28,data_i29,data_i30,data_i31,data_o);
parameter Size = 8;
input wire [('d5) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
input wire [(Size) - ('b1):0] data_i16;
input wire [(Size) - ('b1):0] data_i17;
input wire [(Size) - ('b1):0] data_i18;
input wire [(Size) - ('b1):0] data_i19;
input wire [(Size) - ('b1):0] data_i20;
input wire [(Size) - ('b1):0] data_i21;
input wire [(Size) - ('b1):0] data_i22;
input wire [(Size) - ('b1):0] data_i23;
input wire [(Size) - ('b1):0] data_i24;
input wire [(Size) - ('b1):0] data_i25;
input wire [(Size) - ('b1):0] data_i26;
input wire [(Size) - ('b1):0] data_i27;
input wire [(Size) - ('b1):0] data_i28;
input wire [(Size) - ('b1):0] data_i29;
input wire [(Size) - ('b1):0] data_i30;
input wire [(Size) - ('b1):0] data_i31;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15 or
data_i16 or data_i17 or data_i18 or data_i19 or data_i20 or data_i21 or data_i22 or data_i23 or
data_i24 or data_i25 or data_i26 or data_i27 or data_i28 or data_i29 or data_i30 or data_i31) begin
case (select)
'b00000: data_o = data_i00;
'b00001: data_o = data_i01;
'b00010: data_o = data_i02;
'b00011: data_o = data_i03;
'b00100: data_o = data_i04;
'b00101: data_o = data_i05;
'b00110: data_o = data_i06;
'b00111: data_o = data_i07;
'b01000: data_o = data_i08;
'b01001: data_o = data_i09;
'b01010: data_o = data_i10;
'b01011: data_o = data_i11;
'b01100: data_o = data_i12;
'b01101: data_o = data_i13;
'b01110: data_o = data_i14;
'b01111: data_o = data_i15;
'b10000: data_o = data_i16;
'b10001: data_o = data_i17;
'b10010: data_o = data_i18;
'b10011: data_o = data_i19;
'b10100: data_o = data_i20;
'b10101: data_o = data_i21;
'b10110: data_o = data_i22;
'b10111: data_o = data_i23;
'b11000: data_o = data_i24;
'b11001: data_o = data_i25;
'b11010: data_o = data_i26;
'b11011: data_o = data_i27;
'b11100: data_o = data_i28;
'b11101: data_o = data_i29;
'b11110: data_o = data_i30;
'b11111: data_o = data_i31;
endcase
end
endmodule // Mux32
module Reg(clock,reset,data_i,writeEn,data_o);
parameter Size = 8;
input wire [('d1) - ('b1):0] clock;
input wire [('d1) - ('b1):0] reset;
input wire [(Size) - ('b1):0] data_i;
input wire [('d1) - ('b1):0] writeEn;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (writeEn) begin
data_o <= data_i;
end
end
end
endmodule // Reg
module FPGADCM(clock,reset,locked,clock_o0,clock_o90,clock_o180,clock_o270,clock_o2x,clock_o2x180);
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
output wire [('b1) - ('b1):0] locked;
output wire [('b1) - ('b1):0] clock_o0;
output wire [('b1) - ('b1):0] clock_o90;
output wire [('b1) - ('b1):0] clock_o180;
output wire [('b1) - ('b1):0] clock_o270;
output wire [('b1) - ('b1):0] clock_o2x;
output wire [('b1) - ('b1):0] clock_o2x180;
wire FPGABUFG_o;
wire FPGASPDCM_CLK0;
assign clock_o0 = FPGASPDCM_CLK0;
DCM_SP #(.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(0.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE"))
FPGASPDCM (.CLKIN(clock),
.CLKFB(FPGABUFG_o),
.RST(reset),
.DSSEN(0),
.PSINCDEC(0),
.PSEN(0),
.PSCLK(0),
.LOCKED(locked),
.CLK0(FPGASPDCM_CLK0),
.CLK90(clock_o90),
.CLK180(clock_o180),
.CLK270(clock_o270),
.CLK2X(clock_o2x),
.CLK2X180(clock_o2x180));
BUFG
FPGABUFG (.I(FPGASPDCM_CLK0),
.O(FPGABUFG_o));
endmodule // DCM
module VGAVideo(
input wire [('b1) - ('b1):0] clock,
input wire [('b1) - ('b1):0] reset,
output wire [('b1) - ('b1):0] vga_r,
output wire [('b1) - ('b1):0] vga_g,
output wire [('b1) - ('b1):0] vga_b,
output wire [('b1) - ('b1):0] vga_hsync,
output wire [('b1) - ('b1):0] vga_vsync);
parameter hack_hcounter_Size = 'b1011;
parameter hack_vcounter_Size = 'b1010;
wire [(hack_hcounter_Size) - ('b1):0] hcounter_data_o;
wire [(hack_vcounter_Size) - ('b1):0] vcounter_data_o;
assign vga_r = 'b1;
assign vga_g = 'b0;
assign vga_b = 'b0;
assign vga_hsync = (hcounter_data_o['b1010:'b101] == 'b0);
assign vga_vsync = (vcounter_data_o == 'b0);
UpCounter #(
.Size('b1011))
hcounter(
.clock(clock),
.reset((hcounter_data_o == 'b1011111111)),
.count('b1),
.data_o(hcounter_data_o));
UpCounter #(
.Size('b1010))
vcounter(
.clock(clock),
.reset('b0),
.count('b1),
.data_o(vcounter_data_o));
endmodule // VGAVideo
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
// synchronize flag (signal lasts just one clock cycle) to new clock domain (CLK_B)
module flag_domain_crossing_ce(
input wire CLK_A,
input wire CLK_A_CE,
input wire CLK_B,
input wire CLK_B_CE,
input wire FLAG_IN_CLK_A,
output wire FLAG_OUT_CLK_B
);
reg FLAG_TOGGLE_CLK_A;
initial FLAG_TOGGLE_CLK_A = 0;
reg [2:0] SYNC_CLK_B;
always @ (posedge CLK_A)
begin
if (CLK_A_CE)
begin
if (FLAG_IN_CLK_A)
begin
FLAG_TOGGLE_CLK_A <= ~FLAG_TOGGLE_CLK_A;
end
end
end
always @ (posedge CLK_B)
begin
if (CLK_B_CE)
begin
SYNC_CLK_B <= {SYNC_CLK_B[1:0], FLAG_TOGGLE_CLK_A};
end
end
assign FLAG_OUT_CLK_B = (SYNC_CLK_B[2] ^ SYNC_CLK_B[1]); // XOR
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
wire [width-1:0] dec_test_expr = test_expr - {{width-1{1'b0}},1'b1};
wire zoh_test_expr = ((test_expr & dec_test_expr) == {width{1'b0}});
wire valid_test_expr = ((test_expr ^ test_expr) == {width{1'b0}});
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
reg fire_2state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_2state <= 1'b0;
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression contains more than 1 asserted bits");
fire_2state <= ovl_fire_2state_f(property_type);
end
else begin
fire_2state <= 1'b0;
end
end
end
assign fire_2state_1 = !zoh_test_expr;
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] one_hots_checked;
reg [width-1:0] prev_one_hots_checked;
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
prev_test_expr <= test_expr; // deliberately not reset
if (`OVL_RESET_SIGNAL == 1'b0) begin
one_hots_checked <= {width{1'b0}};
prev_one_hots_checked <= {width{1'b0}};
end
else begin
if (valid_test_expr && zoh_test_expr) begin
one_hots_checked <= one_hots_checked | test_expr;
end
prev_one_hots_checked <= one_hots_checked;
end
end
wire fire_cover_1, fire_cover_2, fire_cover_3;
reg fire_cover;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_cover <= 1'b0;
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("all_one_hots_checked covered"); // corner
end
if (fire_cover_3) begin
ovl_cover_t("test_expr_all_zeros covered"); // corner
end
if (fire_cover_1 || fire_cover_2 || fire_cover_3) begin
fire_cover <= 1'b1;
end
else begin
fire_cover <= 1'b0;
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (one_hots_checked == {width{1'b1}}) && (one_hots_checked != prev_one_hots_checked));
assign fire_cover_3 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == {width{1'b0}}) && (prev_test_expr != {width{1'b0}}));
`else
wire fire_cover = 1'b0;
`endif // OVL_COVER_ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXTP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFXTP_SYMBOL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXTP_SYMBOL_V
|
module ABRO_blif(clk, rst, O, A, B, R);
input clk, rst;
output O;
input A;
input B;
input R;
wire A;
wire B;
wire R;
wire O;
wire w_0;
wire w_1;
wire R_O;
wire SM1_chk_0;
wire w_7;
wire w_8;
wire w_9;
wire SM3_chk_0;
wire w_10;
wire SM3_chk_1;
wire w_11;
wire SM10_chk_0;
wire w_12;
wire SM10_chk_1;
wire w_13;
wire B_O;
wire w_14;
wire w_15;
wire w_16;
wire w_17;
wire SM6_chk_0;
wire w_18;
wire SM6_chk_1;
wire w_19;
wire A_O;
wire w_20;
wire w_21;
wire w_22;
wire w_23;
wire w_24;
wire tick_O;
wire w_30;
wire w_31;
wire SM1_chk_1;
wire w_32;
wire SM1_goto_0;
wire SM1_goto_1;
wire SM1_hold;
wire w_36;
wire SM3_goto_0;
wire w_38;
wire SM3_goto_1;
wire SM3_hold;
wire SM6_goto_0;
wire w_42;
wire SM6_goto_1;
wire SM6_hold;
wire SM10_goto_0;
wire w_46;
wire SM10_goto_1;
wire SM10_hold;
wire ff_1_0_q;
wire ff_1_0_d;
wire g57;
wire ff_3_0_q;
wire ff_3_0_d;
wire g60;
wire ff_6_0_q;
wire ff_6_0_d;
wire g63;
wire ff_10_0_q;
wire ff_10_0_d;
wire g66;
assign O = w_24;
assign w_0 = 0;
assign w_1 = 1;
assign R_O = R;
assign SM1_chk_0 = !ff_1_0_q;
assign w_7 = R_O & SM1_chk_0;
assign w_8 = !R_O;
assign w_9 = w_8 & SM1_chk_0;
assign SM3_chk_0 = !ff_3_0_q;
assign w_10 = w_9 & SM3_chk_0;
assign SM3_chk_1 = ff_3_0_q;
assign w_11 = w_9 & SM3_chk_1;
assign SM10_chk_0 = !ff_10_0_q;
assign w_12 = w_11 & SM10_chk_0;
assign SM10_chk_1 = ff_10_0_q;
assign w_13 = w_11 & SM10_chk_1;
assign B_O = B;
assign w_14 = w_13 & B_O;
assign w_15 = !B_O;
assign w_16 = w_13 & w_15;
assign w_17 = w_14 | w_12;
assign SM6_chk_0 = !ff_6_0_q;
assign w_18 = w_11 & SM6_chk_0;
assign SM6_chk_1 = ff_6_0_q;
assign w_19 = w_11 & SM6_chk_1;
assign A_O = A;
assign w_20 = w_19 & A_O;
assign w_21 = !A_O;
assign w_22 = w_21 & w_19;
assign w_23 = w_20 | w_18;
assign w_24 = w_17 & w_23;
assign tick_O = w_1;
assign w_30 = !w_24;
assign w_31 = w_11 & w_30;
assign SM1_chk_1 = ff_1_0_q;
assign w_32 = w_9 | w_7 | SM1_chk_1;
assign SM1_goto_0 = w_32;
assign SM1_goto_1 = w_0;
assign SM1_hold = w_0;
assign w_36 = w_10 | w_24;
assign SM3_goto_0 = w_36;
assign w_38 = w_7 | w_31 | SM1_chk_1;
assign SM3_goto_1 = w_38;
assign SM3_hold = w_0;
assign SM6_goto_0 = w_23;
assign w_42 = w_7 | w_22 | SM1_chk_1;
assign SM6_goto_1 = w_42;
assign SM6_hold = w_0;
assign SM10_goto_0 = w_17;
assign w_46 = w_7 | w_16 | SM1_chk_1;
assign SM10_goto_1 = w_46;
assign SM10_hold = w_0;
d_ff1 u0(rst, clk, ff_1_0_q, ff_1_0_d);
assign ff_1_0_d = g57 | SM1_goto_1;
assign g57 = SM1_hold & ff_1_0_q;
d_ff0 u1(rst, clk, ff_3_0_q, ff_3_0_d);
assign ff_3_0_d = g60 | SM3_goto_1;
assign g60 = SM3_hold & ff_3_0_q;
d_ff0 u2(rst, clk, ff_6_0_q, ff_6_0_d);
assign ff_6_0_d = g63 | SM6_goto_1;
assign g63 = SM6_hold & ff_6_0_q;
d_ff0 u3(rst, clk, ff_10_0_q, ff_10_0_d);
assign ff_10_0_d = g66 | SM10_goto_1;
assign g66 = SM10_hold & ff_10_0_q;
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
//`define VERBOSE
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
wire start;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_tx1_pcie s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21OI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A21OI_PP_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21OI_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's definitions ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Parameters of the OR1200 core ////
//// ////
//// To Do: ////
//// - add parameters that are missing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_defines.v,v $
// Revision 1.2 2006-12-22 08:34:00 vak
// The design is successfully compiled using on-chip RAM.
//
// Revision 1.1 2006/12/21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.45 2006/04/09 01:32:29 lampret
// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
//
// Revision 1.44 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.43 2005/01/07 09:23:39 andreje
// l.ff1 and l.cmov instructions added
//
// Revision 1.42 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.41 2004/05/09 20:03:20 lampret
// By default l.cust5 insns are disabled
//
// Revision 1.40 2004/05/09 19:49:04 lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.39 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
// Revision 1.38 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.35.4.6 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
// Revision 1.35.4.5 2004/01/15 06:46:38 markom
// interface to debug changed; no more opselect; stb-ack protocol
//
// Revision 1.35.4.4 2004/01/11 22:45:46 andreje
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
//
// Revision 1.35.4.3 2003/12/17 13:43:38 simons
// Exception prefix configuration changed.
//
// Revision 1.35.4.2 2003/12/05 00:05:03 lampret
// Static exception prefix.
//
// Revision 1.35.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.35 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.34 2003/04/20 22:23:57 lampret
// No functional change. Only added customization for exception vectors.
//
// Revision 1.33 2003/04/07 20:56:07 lampret
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
//
// Revision 1.32 2003/04/07 01:26:57 lampret
// RFRAM defines comments updated. Altera LPM option added.
//
// Revision 1.31 2002/12/08 08:57:56 lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
// Revision 1.30 2002/10/28 15:09:22 mohor
// Previous check-in was done by mistake.
//
// Revision 1.29 2002/10/28 15:03:50 mohor
// Signal scanb_sen renamed to scanb_en.
//
// Revision 1.28 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.27 2002/09/16 03:13:23 lampret
// Removed obsolete comment.
//
// Revision 1.26 2002/09/08 05:52:16 lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.25 2002/09/07 19:16:10 lampret
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
//
// Revision 1.24 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.23 2002/09/04 00:50:34 lampret
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
//
// Revision 1.22 2002/09/03 22:28:21 lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.21 2002/08/22 02:18:55 lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.20 2002/08/18 21:59:45 lampret
// Disable SB until it is tested
//
// Revision 1.19 2002/08/18 19:53:08 lampret
// Added store buffer.
//
// Revision 1.18 2002/08/15 06:04:11 lampret
// Fixed Xilinx trace buffer address. REported by Taylor Su.
//
// Revision 1.17 2002/08/12 05:31:44 lampret
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
//
// Revision 1.16 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.15 2002/06/08 16:20:21 lampret
// Added defines for enabling generic FF based memory macro for register file.
//
// Revision 1.14 2002/03/29 16:24:06 lampret
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
//
// Revision 1.13 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.12 2002/03/28 19:25:42 lampret
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
//
// Revision 1.11 2002/03/28 19:13:17 lampret
// Updated defines.
//
// Revision 1.10 2002/03/14 00:30:24 lampret
// Added alternative for critical path in DU.
//
// Revision 1.9 2002/03/11 01:26:26 lampret
// Fixed async loop. Changed multiplier type for ASIC.
//
// Revision 1.8 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.7 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.6 2002/01/19 14:10:22 lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.5 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.4 2002/01/14 09:44:12 lampret
// Default ASIC configuration does not sample WB inputs.
//
// Revision 1.3 2002/01/08 00:51:08 lampret
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
//
// Revision 1.2 2002/01/03 21:23:03 lampret
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.20 2001/12/04 05:02:36 lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.19 2001/11/27 19:46:57 lampret
// Now FPGA and ASIC target are separate.
//
// Revision 1.18 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.17 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.16 2001/11/20 21:30:38 lampret
// Added OR1200_REGISTERED_INPUTS.
//
// Revision 1.15 2001/11/19 14:29:48 simons
// Cashes disabled.
//
// Revision 1.14 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.13 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.12 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.11 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.8 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/17 08:01:19 lampret
// IC enable/disable.
//
// Revision 1.2 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
//
// Dump VCD
//
//`define OR1200_VCD_DUMP
//
// Generate debug messages during simulation
//
//`define OR1200_VERBOSE
// `define OR1200_ASIC
////////////////////////////////////////////////////////
//
// Typical configuration for an ASIC
//
`ifdef OR1200_ASIC
//
// Target ASIC memories
//
//`define OR1200_ARTISAN_SSP
//`define OR1200_ARTISAN_SDP
//`define OR1200_ARTISAN_STP
`define OR1200_VIRTUALSILICON_SSP
//`define OR1200_VIRTUALSILICON_STP_T1
//`define OR1200_VIRTUALSILICON_STP_T2
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
//
// Select between ASIC optimized and generic multiplier
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
//
// Size/type of insn/data cache if implemented
//
// `define OR1200_IC_1W_512B
// `define OR1200_IC_1W_4KB
`define OR1200_IC_1W_8KB
// `define OR1200_DC_1W_4KB
`define OR1200_DC_1W_8KB
`else
/////////////////////////////////////////////////////////
//
// Typical configuration for an FPGA
//
//
// Target FPGA memories
//
//`define OR1200_ALTERA_LPM
`define OR1200_XILINX_RAMB16
//`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
//
// Do not implement Data cache
//
`define OR1200_NO_DC
//
// Do not implement Insn cache
//
`define OR1200_NO_IC
//
// Do not implement Data MMU
//
`define OR1200_NO_DMMU
//
// Do not implement Insn MMU
//
`define OR1200_NO_IMMU
//
// Select between ASIC and generic multiplier
//
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
//
// Size/type of insn/data cache if implemented
// (consider available FPGA memory resources)
//
//`define OR1200_IC_1W_512B
`define OR1200_IC_1W_4KB
//`define OR1200_IC_1W_8KB
`define OR1200_DC_1W_4KB
//`define OR1200_DC_1W_8KB
`endif
//////////////////////////////////////////////////////////
//
// Do not change below unless you know what you are doing
//
//
// Enable RAM BIST
//
// At the moment this only works for Virtual Silicon
// single port RAMs. For other RAMs it has not effect.
// Special wrapper for VS RAMs needs to be provided
// with scan flops to facilitate bist scan.
//
//`define OR1200_BIST
//
// Register OR1200 WISHBONE outputs
// (must be defined/enabled)
//
`define OR1200_REGISTERED_OUTPUTS
//
// Register OR1200 WISHBONE inputs
//
// (must be undefined/disabled)
//
//`define OR1200_REGISTERED_INPUTS
//
// Disable bursts if they are not supported by the
// memory subsystem (only affect cache line fill)
//
//`define OR1200_NO_BURSTS
//
//
// WISHBONE retry counter range
//
// 2^value range for retry counter. Retry counter
// is activated whenever *wb_rty_i is asserted and
// until retry counter expires, corresponding
// WISHBONE interface is deactivated.
//
// To disable retry counters and *wb_rty_i all together,
// undefine this macro.
//
//`define OR1200_WB_RETRY 7
//
// WISHBONE Consecutive Address Burst
//
// This was used prior to WISHBONE B3 specification
// to identify bursts. It is no longer needed but
// remains enabled for compatibility with old designs.
//
// To remove *wb_cab_o ports undefine this macro.
//
`define OR1200_WB_CAB
//
// WISHBONE B3 compatible interface
//
// This follows the WISHBONE B3 specification.
// It is not enabled by default because most
// designs still don't use WB b3.
//
// To enable *wb_cti_o/*wb_bte_o ports,
// define this macro.
//
//`define OR1200_WB_B3
//
// Enable additional synthesis directives if using
// _Synopsys_ synthesis tool
//
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
//
// Enables default statement in some case blocks
// and disables Synopsys synthesis directive full_case
//
// By default it is enabled. When disabled it
// can increase clock frequency.
//
`define OR1200_CASE_DEFAULT
//
// Operand width / register file address width
//
// (DO NOT CHANGE)
//
`define OR1200_OPERAND_WIDTH 32
`define OR1200_REGFILE_ADDR_WIDTH 5
//
// l.add/l.addi/l.and and optional l.addc/l.addic
// also set (compare) flag when result of their
// operation equals zero
//
// At the time of writing this, default or32
// C/C++ compiler doesn't generate code that
// would benefit from this optimization.
//
// By default this optimization is disabled to
// save area.
//
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
//
// Implement l.addc/l.addic instructions
//
// By default implementation of l.addc/l.addic
// instructions is enabled in case you need them.
// If you don't use them, then disable implementation
// to save area.
//
`define OR1200_IMPL_ADDC
//
// Implement carry bit SR[CY]
//
// By default implementation of SR[CY] is enabled
// to be compliant with the simulator. However
// SR[CY] is explicitly only used by l.addc/l.addic
// instructions and if these two insns are not
// implemented there is not much point having SR[CY].
//
`define OR1200_IMPL_CY
//
// Implement optional l.div/l.divu instructions
//
// By default divide instructions are not implemented
// to save area and increase clock frequency. or32 C/C++
// compiler can use soft library for division.
//
// To implement divide, multiplier needs to be implemented.
//
//`define OR1200_IMPL_DIV
//
// Implement rotate in the ALU
//
// At the time of writing this, or32
// C/C++ compiler doesn't generate rotate
// instructions. However or32 assembler
// can assemble code that uses rotate insn.
// This means that rotate instructions
// must be used manually inserted.
//
// By default implementation of rotate
// is disabled to save area and increase
// clock frequency.
//
//`define OR1200_IMPL_ALU_ROTATE
//
// Type of ALU compare to implement
//
// Try either one to find what yields
// higher clock frequencyin your case.
//
//`define OR1200_IMPL_ALU_COMP1
`define OR1200_IMPL_ALU_COMP2
//
// Implement multiplier
//
// By default multiplier is implemented
//
`define OR1200_MULT_IMPLEMENTED
//
// Implement multiply-and-accumulate
//
// By default MAC is implemented. To
// implement MAC, multiplier needs to be
// implemented.
//
//`define OR1200_MAC_IMPLEMENTED
//
// Low power, slower multiplier
//
// Select between low-power (larger) multiplier
// and faster multiplier. The actual difference
// is only AND logic that prevents distribution
// of operands into the multiplier when instruction
// in execution is not multiply instruction
//
//`define OR1200_LOWPWR_MULT
//
// Clock ratio RISC clock versus WB clock
//
// If you plan to run WB:RISC clock fixed to 1:1, disable
// both defines
//
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
// and use clmode to set ratio
//
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
// clmode to set ratio
//
//`define OR1200_CLKDIV_2_SUPPORTED
//`define OR1200_CLKDIV_4_SUPPORTED
//
// Type of register file RAM
//
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
`define OR1200_RFRAM_TWOPORT
//
// Memory macro dual port (see or1200_dpram_32x32.v)
//`define OR1200_RFRAM_DUALPORT
//
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
//`define OR1200_RFRAM_GENERIC
//
// Type of mem2reg aligner to implement.
//
// Once OR1200_IMPL_MEM2REG2 yielded faster
// circuit, however with today tools it will
// most probably give you slower circuit.
//
`define OR1200_IMPL_MEM2REG1
//`define OR1200_IMPL_MEM2REG2
//
// ALUOPs
//
`define OR1200_ALUOP_WIDTH 4
`define OR1200_ALUOP_NOP 4'd4
/* Order defined by arith insns that have two source operands both in regs
(see binutils/include/opcode/or32.h) */
`define OR1200_ALUOP_ADD 4'd0
`define OR1200_ALUOP_ADDC 4'd1
`define OR1200_ALUOP_SUB 4'd2
`define OR1200_ALUOP_AND 4'd3
`define OR1200_ALUOP_OR 4'd4
`define OR1200_ALUOP_XOR 4'd5
`define OR1200_ALUOP_MUL 4'd6
`define OR1200_ALUOP_CUST5 4'd7
`define OR1200_ALUOP_SHROT 4'd8
`define OR1200_ALUOP_DIV 4'd9
`define OR1200_ALUOP_DIVU 4'd10
/* Order not specifically defined. */
`define OR1200_ALUOP_IMM 4'd11
`define OR1200_ALUOP_MOVHI 4'd12
`define OR1200_ALUOP_COMP 4'd13
`define OR1200_ALUOP_MTSR 4'd14
`define OR1200_ALUOP_MFSR 4'd15
`define OR1200_ALUOP_CMOV 4'd14
`define OR1200_ALUOP_FF1 4'd15
//
// MACOPs
//
`define OR1200_MACOP_WIDTH 2
`define OR1200_MACOP_NOP 2'b00
`define OR1200_MACOP_MAC 2'b01
`define OR1200_MACOP_MSB 2'b10
//
// Shift/rotate ops
//
`define OR1200_SHROTOP_WIDTH 2
`define OR1200_SHROTOP_NOP 2'd0
`define OR1200_SHROTOP_SLL 2'd0
`define OR1200_SHROTOP_SRL 2'd1
`define OR1200_SHROTOP_SRA 2'd2
`define OR1200_SHROTOP_ROR 2'd3
// Execution cycles per instruction
`define OR1200_MULTICYCLE_WIDTH 2
`define OR1200_ONE_CYCLE 2'd0
`define OR1200_TWO_CYCLES 2'd1
// Operand MUX selects
`define OR1200_SEL_WIDTH 2
`define OR1200_SEL_RF 2'd0
`define OR1200_SEL_IMM 2'd1
`define OR1200_SEL_EX_FORW 2'd2
`define OR1200_SEL_WB_FORW 2'd3
//
// BRANCHOPs
//
`define OR1200_BRANCHOP_WIDTH 3
`define OR1200_BRANCHOP_NOP 3'd0
`define OR1200_BRANCHOP_J 3'd1
`define OR1200_BRANCHOP_JR 3'd2
`define OR1200_BRANCHOP_BAL 3'd3
`define OR1200_BRANCHOP_BF 3'd4
`define OR1200_BRANCHOP_BNF 3'd5
`define OR1200_BRANCHOP_RFE 3'd6
//
// LSUOPs
//
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define OR1200_LSUOP_WIDTH 4
`define OR1200_LSUOP_NOP 4'b0000
`define OR1200_LSUOP_LBZ 4'b0010
`define OR1200_LSUOP_LBS 4'b0011
`define OR1200_LSUOP_LHZ 4'b0100
`define OR1200_LSUOP_LHS 4'b0101
`define OR1200_LSUOP_LWZ 4'b0110
`define OR1200_LSUOP_LWS 4'b0111
`define OR1200_LSUOP_LD 4'b0001
`define OR1200_LSUOP_SD 4'b1000
`define OR1200_LSUOP_SB 4'b1010
`define OR1200_LSUOP_SH 4'b1100
`define OR1200_LSUOP_SW 4'b1110
// FETCHOPs
`define OR1200_FETCHOP_WIDTH 1
`define OR1200_FETCHOP_NOP 1'b0
`define OR1200_FETCHOP_LW 1'b1
//
// Register File Write-Back OPs
//
// Bit 0: register file write enable
// Bits 2-1: write-back mux selects
`define OR1200_RFWBOP_WIDTH 3
`define OR1200_RFWBOP_NOP 3'b000
`define OR1200_RFWBOP_ALU 3'b001
`define OR1200_RFWBOP_LSU 3'b011
`define OR1200_RFWBOP_SPRS 3'b101
`define OR1200_RFWBOP_LR 3'b111
// Compare instructions
`define OR1200_COP_SFEQ 3'b000
`define OR1200_COP_SFNE 3'b001
`define OR1200_COP_SFGT 3'b010
`define OR1200_COP_SFGE 3'b011
`define OR1200_COP_SFLT 3'b100
`define OR1200_COP_SFLE 3'b101
`define OR1200_COP_X 3'b111
`define OR1200_SIGNED_COMPARE 'd3
`define OR1200_COMPOP_WIDTH 4
//
// TAGs for instruction bus
//
`define OR1200_ITAG_IDLE 4'h0 // idle bus
`define OR1200_ITAG_NI 4'h1 // normal insn
`define OR1200_ITAG_BE 4'hb // Bus error exception
`define OR1200_ITAG_PE 4'hc // Page fault exception
`define OR1200_ITAG_TE 4'hd // TLB miss exception
//
// TAGs for data bus
//
`define OR1200_DTAG_IDLE 4'h0 // idle bus
`define OR1200_DTAG_ND 4'h1 // normal data
`define OR1200_DTAG_AE 4'ha // Alignment exception
`define OR1200_DTAG_BE 4'hb // Bus error exception
`define OR1200_DTAG_PE 4'hc // Page fault exception
`define OR1200_DTAG_TE 4'hd // TLB miss exception
//////////////////////////////////////////////
//
// ORBIS32 ISA specifics
//
// SHROT_OP position in machine word
`define OR1200_SHROTOP_POS 7:6
// ALU instructions multicycle field in machine word
`define OR1200_ALUMCYC_POS 9:8
//
// Instruction opcode groups (basic)
//
`define OR1200_OR32_J 6'b000000
`define OR1200_OR32_JAL 6'b000001
`define OR1200_OR32_BNF 6'b000011
`define OR1200_OR32_BF 6'b000100
`define OR1200_OR32_NOP 6'b000101
`define OR1200_OR32_MOVHI 6'b000110
`define OR1200_OR32_XSYNC 6'b001000
`define OR1200_OR32_RFE 6'b001001
/* */
`define OR1200_OR32_JR 6'b010001
`define OR1200_OR32_JALR 6'b010010
`define OR1200_OR32_MACI 6'b010011
/* */
`define OR1200_OR32_LWZ 6'b100001
`define OR1200_OR32_LBZ 6'b100011
`define OR1200_OR32_LBS 6'b100100
`define OR1200_OR32_LHZ 6'b100101
`define OR1200_OR32_LHS 6'b100110
`define OR1200_OR32_ADDI 6'b100111
`define OR1200_OR32_ADDIC 6'b101000
`define OR1200_OR32_ANDI 6'b101001
`define OR1200_OR32_ORI 6'b101010
`define OR1200_OR32_XORI 6'b101011
`define OR1200_OR32_MULI 6'b101100
`define OR1200_OR32_MFSPR 6'b101101
`define OR1200_OR32_SH_ROTI 6'b101110
`define OR1200_OR32_SFXXI 6'b101111
/* */
`define OR1200_OR32_MTSPR 6'b110000
`define OR1200_OR32_MACMSB 6'b110001
/* */
`define OR1200_OR32_SW 6'b110101
`define OR1200_OR32_SB 6'b110110
`define OR1200_OR32_SH 6'b110111
`define OR1200_OR32_ALU 6'b111000
`define OR1200_OR32_SFXX 6'b111001
//`define OR1200_OR32_CUST5 6'b111100
/////////////////////////////////////////////////////
//
// Exceptions
//
//
// Exception vectors per OR1K architecture:
// 0xPPPPP100 - reset
// 0xPPPPP200 - bus error
// ... etc
// where P represents exception prefix.
//
// Exception vectors can be customized as per
// the following formula:
// 0xPPPPPNVV - exception N
//
// P represents exception prefix
// N represents exception N
// VV represents length of the individual vector space,
// usually it is 8 bits wide and starts with all bits zero
//
//
// PPPPP and VV parts
//
// Sum of these two defines needs to be 28
//
`define OR1200_EXCEPT_EPH0_P 20'h00000
`define OR1200_EXCEPT_EPH1_P 20'hF0000
`define OR1200_EXCEPT_V 8'h00
//
// N part width
//
`define OR1200_EXCEPT_WIDTH 4
//
// Definition of exception vectors
//
// To avoid implementation of a certain exception,
// simply comment out corresponding line
//
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd
`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7
`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6
`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5
`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4
`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3
`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2
`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1
`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0
/////////////////////////////////////////////////////
//
// SPR groups
//
// Bits that define the group
`define OR1200_SPR_GROUP_BITS 15:11
// Width of the group bits
`define OR1200_SPR_GROUP_WIDTH 5
// Bits that define offset inside the group
`define OR1200_SPR_OFS_BITS 10:0
// List of groups
`define OR1200_SPR_GROUP_SYS 5'd00
`define OR1200_SPR_GROUP_DMMU 5'd01
`define OR1200_SPR_GROUP_IMMU 5'd02
`define OR1200_SPR_GROUP_DC 5'd03
`define OR1200_SPR_GROUP_IC 5'd04
`define OR1200_SPR_GROUP_MAC 5'd05
`define OR1200_SPR_GROUP_DU 5'd06
`define OR1200_SPR_GROUP_PM 5'd08
`define OR1200_SPR_GROUP_PIC 5'd09
`define OR1200_SPR_GROUP_TT 5'd10
/////////////////////////////////////////////////////
//
// System group
//
//
// System registers
//
`define OR1200_SPR_CFGR 7'd0
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
`define OR1200_SPR_NPC 11'd16
`define OR1200_SPR_SR 11'd17
`define OR1200_SPR_PPC 11'd18
`define OR1200_SPR_EPCR 11'd32
`define OR1200_SPR_EEAR 11'd48
`define OR1200_SPR_ESR 11'd64
//
// SR bits
//
`define OR1200_SR_WIDTH 16
`define OR1200_SR_SM 0
`define OR1200_SR_TEE 1
`define OR1200_SR_IEE 2
`define OR1200_SR_DCE 3
`define OR1200_SR_ICE 4
`define OR1200_SR_DME 5
`define OR1200_SR_IME 6
`define OR1200_SR_LEE 7
`define OR1200_SR_CE 8
`define OR1200_SR_F 9
`define OR1200_SR_CY 10 // Unused
`define OR1200_SR_OV 11 // Unused
`define OR1200_SR_OVE 12 // Unused
`define OR1200_SR_DSX 13 // Unused
`define OR1200_SR_EPH 14
`define OR1200_SR_FO 15
`define OR1200_SR_CID 31:28 // Unimplemented
//
// Bits that define offset inside the group
//
`define OR1200_SPROFS_BITS 10:0
//
// Default Exception Prefix
//
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
//
`define OR1200_SR_EPH_DEF 1'b0
/////////////////////////////////////////////////////
//
// Power Management (PM)
//
// Define it if you want PM implemented
`define OR1200_PM_IMPLEMENTED
// Bit positions inside PMR (don't change)
`define OR1200_PM_PMR_SDF 3:0
`define OR1200_PM_PMR_DME 4
`define OR1200_PM_PMR_SME 5
`define OR1200_PM_PMR_DCGE 6
`define OR1200_PM_PMR_UNUSED 31:7
// PMR offset inside PM group of registers
`define OR1200_PM_OFS_PMR 11'b0
// PM group
`define OR1200_SPRGRP_PM 5'd8
// Define if PMR can be read/written at any address inside PM group
`define OR1200_PM_PARTIAL_DECODING
// Define if reading PMR is allowed
`define OR1200_PM_READREGS
// Define if unused PMR bits should be zero
`define OR1200_PM_UNUSED_ZERO
/////////////////////////////////////////////////////
//
// Debug Unit (DU)
//
// Define it if you want DU implemented
`define OR1200_DU_IMPLEMENTED
//
// Define if you want HW Breakpoints
// (if HW breakpoints are not implemented
// only default software trapping is
// possible with l.trap insn - this is
// however already enough for use
// with or32 gdb)
//
//`define OR1200_DU_HWBKPTS
// Number of DVR/DCR pairs if HW breakpoints enabled
`define OR1200_DU_DVRDCR_PAIRS 8
// Define if you want trace buffer
//`define OR1200_DU_TB_IMPLEMENTED
//
// Address offsets of DU registers inside DU group
//
// To not implement a register, doq not define its address
//
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DVR0 11'd0
`define OR1200_DU_DVR1 11'd1
`define OR1200_DU_DVR2 11'd2
`define OR1200_DU_DVR3 11'd3
`define OR1200_DU_DVR4 11'd4
`define OR1200_DU_DVR5 11'd5
`define OR1200_DU_DVR6 11'd6
`define OR1200_DU_DVR7 11'd7
`define OR1200_DU_DCR0 11'd8
`define OR1200_DU_DCR1 11'd9
`define OR1200_DU_DCR2 11'd10
`define OR1200_DU_DCR3 11'd11
`define OR1200_DU_DCR4 11'd12
`define OR1200_DU_DCR5 11'd13
`define OR1200_DU_DCR6 11'd14
`define OR1200_DU_DCR7 11'd15
`endif
`define OR1200_DU_DMR1 11'd16
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DMR2 11'd17
`define OR1200_DU_DWCR0 11'd18
`define OR1200_DU_DWCR1 11'd19
`endif
`define OR1200_DU_DSR 11'd20
`define OR1200_DU_DRR 11'd21
`ifdef OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_TBADR 11'h0ff
`define OR1200_DU_TBIA 11'h1xx
`define OR1200_DU_TBIM 11'h2xx
`define OR1200_DU_TBAR 11'h3xx
`define OR1200_DU_TBTS 11'h4xx
`endif
// Position of offset bits inside SPR address
`define OR1200_DUOFS_BITS 10:0
// DCR bits
`define OR1200_DU_DCR_DP 0
`define OR1200_DU_DCR_CC 3:1
`define OR1200_DU_DCR_SC 4
`define OR1200_DU_DCR_CT 7:5
// DMR1 bits
`define OR1200_DU_DMR1_CW0 1:0
`define OR1200_DU_DMR1_CW1 3:2
`define OR1200_DU_DMR1_CW2 5:4
`define OR1200_DU_DMR1_CW3 7:6
`define OR1200_DU_DMR1_CW4 9:8
`define OR1200_DU_DMR1_CW5 11:10
`define OR1200_DU_DMR1_CW6 13:12
`define OR1200_DU_DMR1_CW7 15:14
`define OR1200_DU_DMR1_CW8 17:16
`define OR1200_DU_DMR1_CW9 19:18
`define OR1200_DU_DMR1_CW10 21:20
`define OR1200_DU_DMR1_ST 22
`define OR1200_DU_DMR1_BT 23
`define OR1200_DU_DMR1_DXFW 24
`define OR1200_DU_DMR1_ETE 25
// DMR2 bits
`define OR1200_DU_DMR2_WCE0 0
`define OR1200_DU_DMR2_WCE1 1
`define OR1200_DU_DMR2_AWTC 12:2
`define OR1200_DU_DMR2_WGB 23:13
// DWCR bits
`define OR1200_DU_DWCR_COUNT 15:0
`define OR1200_DU_DWCR_MATCH 31:16
// DSR bits
`define OR1200_DU_DSR_WIDTH 14
`define OR1200_DU_DSR_RSTE 0
`define OR1200_DU_DSR_BUSEE 1
`define OR1200_DU_DSR_DPFE 2
`define OR1200_DU_DSR_IPFE 3
`define OR1200_DU_DSR_TTE 4
`define OR1200_DU_DSR_AE 5
`define OR1200_DU_DSR_IIE 6
`define OR1200_DU_DSR_IE 7
`define OR1200_DU_DSR_DME 8
`define OR1200_DU_DSR_IME 9
`define OR1200_DU_DSR_RE 10
`define OR1200_DU_DSR_SCE 11
`define OR1200_DU_DSR_BE 12
`define OR1200_DU_DSR_TE 13
// DRR bits
`define OR1200_DU_DRR_RSTE 0
`define OR1200_DU_DRR_BUSEE 1
`define OR1200_DU_DRR_DPFE 2
`define OR1200_DU_DRR_IPFE 3
`define OR1200_DU_DRR_TTE 4
`define OR1200_DU_DRR_AE 5
`define OR1200_DU_DRR_IIE 6
`define OR1200_DU_DRR_IE 7
`define OR1200_DU_DRR_DME 8
`define OR1200_DU_DRR_IME 9
`define OR1200_DU_DRR_RE 10
`define OR1200_DU_DRR_SCE 11
`define OR1200_DU_DRR_BE 12
`define OR1200_DU_DRR_TE 13
// Define if reading DU regs is allowed
`define OR1200_DU_READREGS
// Define if unused DU registers bits should be zero
`define OR1200_DU_UNUSED_ZERO
// Define if IF/LSU status is not needed by devel i/f
`define OR1200_DU_STATUS_UNIMPLEMENTED
/////////////////////////////////////////////////////
//
// Programmable Interrupt Controller (PIC)
//
// Define it if you want PIC implemented
`define OR1200_PIC_IMPLEMENTED
// Define number of interrupt inputs (2-31)
`define OR1200_PIC_INTS 20
// Address offsets of PIC registers inside PIC group
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICSR 2'd2
// Position of offset bits inside SPR address
`define OR1200_PICOFS_BITS 1:0
// Define if you want these PIC registers to be implemented
`define OR1200_PIC_PICMR
`define OR1200_PIC_PICSR
// Define if reading PIC registers is allowed
`define OR1200_PIC_READREGS
// Define if unused PIC register bits should be zero
`define OR1200_PIC_UNUSED_ZERO
/////////////////////////////////////////////////////
//
// Tick Timer (TT)
//
// Define it if you want TT implemented
`define OR1200_TT_IMPLEMENTED
// Address offsets of TT registers inside TT group
`define OR1200_TT_OFS_TTMR 1'd0
`define OR1200_TT_OFS_TTCR 1'd1
// Position of offset bits inside SPR group
`define OR1200_TTOFS_BITS 0
// Define if you want these TT registers to be implemented
`define OR1200_TT_TTMR
`define OR1200_TT_TTCR
// TTMR bits
`define OR1200_TT_TTMR_TP 27:0
`define OR1200_TT_TTMR_IP 28
`define OR1200_TT_TTMR_IE 29
`define OR1200_TT_TTMR_M 31:30
// Define if reading TT registers is allowed
`define OR1200_TT_READREGS
//////////////////////////////////////////////
//
// MAC
//
`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable
//
// Shift {MACHI,MACLO} into destination register when executing l.macrc
//
// According to architecture manual there is no shift, so default value is 0.
//
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
// dest_GPR = {MACHI,MACLO}[59:28]
`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility
//////////////////////////////////////////////
//
// Data MMU (DMMU)
//
//
// Address that selects between TLB TR and MR
//
`define OR1200_DTLB_TM_ADDR 7
//
// DTLBMR fields
//
`define OR1200_DTLBMR_V_BITS 0
`define OR1200_DTLBMR_CID_BITS 4:1
`define OR1200_DTLBMR_RES_BITS 11:5
`define OR1200_DTLBMR_VPN_BITS 31:13
//
// DTLBTR fields
//
`define OR1200_DTLBTR_CC_BITS 0
`define OR1200_DTLBTR_CI_BITS 1
`define OR1200_DTLBTR_WBC_BITS 2
`define OR1200_DTLBTR_WOM_BITS 3
`define OR1200_DTLBTR_A_BITS 4
`define OR1200_DTLBTR_D_BITS 5
`define OR1200_DTLBTR_URE_BITS 6
`define OR1200_DTLBTR_UWE_BITS 7
`define OR1200_DTLBTR_SRE_BITS 8
`define OR1200_DTLBTR_SWE_BITS 9
`define OR1200_DTLBTR_RES_BITS 11:10
`define OR1200_DTLBTR_PPN_BITS 31:13
//
// DTLB configuration
//
`define OR1200_DMMU_PS 13 // 13 for 8KB page size
`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries
`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13
`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19
`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13
`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12
`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20
`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20
`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit
`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI
//
// Cache inhibit while DMMU is not enabled/implemented
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !dcpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30]
// cache inhibited 2GB-4GB (default) dcpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_DMMU_CI dcpu_adr_i[31]
//////////////////////////////////////////////
//
// Insn MMU (IMMU)
//
//
// Address that selects between TLB TR and MR
//
`define OR1200_ITLB_TM_ADDR 7
//
// ITLBMR fields
//
`define OR1200_ITLBMR_V_BITS 0
`define OR1200_ITLBMR_CID_BITS 4:1
`define OR1200_ITLBMR_RES_BITS 11:5
`define OR1200_ITLBMR_VPN_BITS 31:13
//
// ITLBTR fields
//
`define OR1200_ITLBTR_CC_BITS 0
`define OR1200_ITLBTR_CI_BITS 1
`define OR1200_ITLBTR_WBC_BITS 2
`define OR1200_ITLBTR_WOM_BITS 3
`define OR1200_ITLBTR_A_BITS 4
`define OR1200_ITLBTR_D_BITS 5
`define OR1200_ITLBTR_SXE_BITS 6
`define OR1200_ITLBTR_UXE_BITS 7
`define OR1200_ITLBTR_RES_BITS 11:8
`define OR1200_ITLBTR_PPN_BITS 31:13
//
// ITLB configuration
//
`define OR1200_IMMU_PS 13 // 13 for 8KB page size
`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries
`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13
`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19
`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13
`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12
`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20
`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20
`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit
`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI
//
// Cache inhibit while IMMU is not enabled/implemented
// Note: all combinations that use icpu_adr_i cause async loop
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !icpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30]
// cache inhibited 2GB-4GB (default) icpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_IMMU_CI 1'b0
/////////////////////////////////////////////////
//
// Insn cache (IC)
//
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_ICLS 4
//
// IC configurations
//
`ifdef OR1200_IC_1W_512B
`define OR1200_ICSIZE 9 // 512
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
`define OR1200_ICTAG_W 24
`endif
`ifdef OR1200_IC_1W_4KB
`define OR1200_ICSIZE 12 // 4096
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8
`define OR1200_ICTAG_W 21
`endif
`ifdef OR1200_IC_1W_8KB
`define OR1200_ICSIZE 13 // 8192
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
`define OR1200_ICTAG_W 20
`endif
/////////////////////////////////////////////////
//
// Data cache (DC)
//
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_DCLS 4
// Define to perform store refill (potential performance penalty)
// `define OR1200_DC_STORE_REFILL
//
// DC configurations
//
`ifdef OR1200_DC_1W_4KB
`define OR1200_DCSIZE 12 // 4096
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8
`define OR1200_DCTAG_W 21
`endif
`ifdef OR1200_DC_1W_8KB
`define OR1200_DCSIZE 13 // 8192
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
`define OR1200_DCTAG_W 20
`endif
/////////////////////////////////////////////////
//
// Store buffer (SB)
//
//
// Store buffer
//
// It will improve performance by "caching" CPU stores
// using store buffer. This is most important for function
// prologues because DC can only work in write though mode
// and all stores would have to complete external WB writes
// to memory.
// Store buffer is between DC and data BIU.
// All stores will be stored into store buffer and immediately
// completed by the CPU, even though actual external writes
// will be performed later. As a consequence store buffer masks
// all data bus errors related to stores (data bus errors
// related to loads are delivered normally).
// All pending CPU loads will wait until store buffer is empty to
// ensure strict memory model. Right now this is necessary because
// we don't make destinction between cached and cache inhibited
// address space, so we simply empty store buffer until loads
// can begin.
//
// It makes design a bit bigger, depending what is the number of
// entries in SB FIFO. Number of entries can be changed further
// down.
//
//`define OR1200_SB_IMPLEMENTED
//
// Number of store buffer entries
//
// Verified number of entries are 4 and 8 entries
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
// always match 2**OR1200_SB_LOG.
// To disable store buffer, undefine
// OR1200_SB_IMPLEMENTED.
//
`define OR1200_SB_LOG 2 // 2 or 3
`define OR1200_SB_ENTRIES 4 // 4 or 8
/////////////////////////////////////////////////
//
// Quick Embedded Memory (QMEM)
//
//
// Quick Embedded Memory
//
// Instantiation of dedicated insn/data memory (RAM or ROM).
// Insn fetch has effective throughput 1insn / clock cycle.
// Data load takes two clock cycles / access, data store
// takes 1 clock cycle / access (if there is no insn fetch)).
// Memory instantiation is shared between insn and data,
// meaning if insn fetch are performed, data load/store
// performance will be lower.
//
// Main reason for QMEM is to put some time critical functions
// into this memory and to have predictable and fast access
// to these functions. (soft fpu, context switch, exception
// handlers, stack, etc)
//
// It makes design a bit bigger and slower. QMEM sits behind
// IMMU/DMMU so all addresses are physical (so the MMUs can be
// used with QMEM and QMEM is seen by the CPU just like any other
// memory in the system). IC/DC are sitting behind QMEM so the
// whole design timing might be worse with QMEM implemented.
//
`define OR1200_QMEM_IMPLEMENTED
//
// Base address and mask of QMEM
//
// Base address defines first address of QMEM. Mask defines
// QMEM range in address space. Actual size of QMEM is however
// determined with instantiated RAM/ROM. However bigger
// mask will reserve more address space for QMEM, but also
// make design faster, while more tight mask will take
// less address space but also make design slower. If
// instantiated RAM/ROM is smaller than space reserved with
// the mask, instatiated RAM/ROM will also be shadowed
// at higher addresses in reserved space.
//
`define OR1200_QMEM_IADDR 32'h0080_0000
`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB
`define OR1200_QMEM_DADDR 32'h0080_0000
`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB
//
// QMEM interface byte-select capability
//
// To enable qmem_sel* ports, define this macro.
//
//`define OR1200_QMEM_BSEL
//
// QMEM interface acknowledge
//
// To enable qmem_ack port, define this macro.
//
//`define OR1200_QMEM_ACK
/////////////////////////////////////////////////////
//
// VR, UPR and Configuration Registers
//
//
// VR, UPR and configuration registers are optional. If
// implemented, operating system can automatically figure
// out how to use the processor because it knows
// what units are available in the processor and how they
// are configured.
//
// This section must be last in or1200_defines.v file so
// that all units are already configured and thus
// configuration registers are properly set.
//
// Define if you want configuration registers implemented
`define OR1200_CFGR_IMPLEMENTED
// Define if you want full address decode inside SYS group
`define OR1200_SYS_FULL_DECODE
// Offsets of VR, UPR and CFGR registers
`define OR1200_SPRGRP_SYS_VR 4'h0
`define OR1200_SPRGRP_SYS_UPR 4'h1
`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2
`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3
`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4
`define OR1200_SPRGRP_SYS_DCCFGR 4'h5
`define OR1200_SPRGRP_SYS_ICCFGR 4'h6
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
// VR fields
`define OR1200_VR_REV_BITS 5:0
`define OR1200_VR_RES1_BITS 15:6
`define OR1200_VR_CFG_BITS 23:16
`define OR1200_VR_VER_BITS 31:24
// VR values
`define OR1200_VR_REV 6'h01
`define OR1200_VR_RES1 10'h000
`define OR1200_VR_CFG 8'h00
`define OR1200_VR_VER 8'h12
// UPR fields
`define OR1200_UPR_UP_BITS 0
`define OR1200_UPR_DCP_BITS 1
`define OR1200_UPR_ICP_BITS 2
`define OR1200_UPR_DMP_BITS 3
`define OR1200_UPR_IMP_BITS 4
`define OR1200_UPR_MP_BITS 5
`define OR1200_UPR_DUP_BITS 6
`define OR1200_UPR_PCUP_BITS 7
`define OR1200_UPR_PMP_BITS 8
`define OR1200_UPR_PICP_BITS 9
`define OR1200_UPR_TTP_BITS 10
`define OR1200_UPR_RES1_BITS 23:11
`define OR1200_UPR_CUP_BITS 31:24
// UPR values
`define OR1200_UPR_UP 1'b1
`ifdef OR1200_NO_DC
`define OR1200_UPR_DCP 1'b0
`else
`define OR1200_UPR_DCP 1'b1
`endif
`ifdef OR1200_NO_IC
`define OR1200_UPR_ICP 1'b0
`else
`define OR1200_UPR_ICP 1'b1
`endif
`ifdef OR1200_NO_DMMU
`define OR1200_UPR_DMP 1'b0
`else
`define OR1200_UPR_DMP 1'b1
`endif
`ifdef OR1200_NO_IMMU
`define OR1200_UPR_IMP 1'b0
`else
`define OR1200_UPR_IMP 1'b1
`endif
`define OR1200_UPR_MP 1'b1 // MAC always present
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_DUP 1'b1
`else
`define OR1200_UPR_DUP 1'b0
`endif
`define OR1200_UPR_PCUP 1'b0 // Performance counters not present
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_PMP 1'b1
`else
`define OR1200_UPR_PMP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_PICP 1'b1
`else
`define OR1200_UPR_PICP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_TTP 1'b1
`else
`define OR1200_UPR_TTP 1'b0
`endif
`define OR1200_UPR_RES1 13'h0000
`define OR1200_UPR_CUP 8'h00
// CPUCFGR fields
`define OR1200_CPUCFGR_NSGF_BITS 3:0
`define OR1200_CPUCFGR_HGF_BITS 4
`define OR1200_CPUCFGR_OB32S_BITS 5
`define OR1200_CPUCFGR_OB64S_BITS 6
`define OR1200_CPUCFGR_OF32S_BITS 7
`define OR1200_CPUCFGR_OF64S_BITS 8
`define OR1200_CPUCFGR_OV64S_BITS 9
`define OR1200_CPUCFGR_RES1_BITS 31:10
// CPUCFGR values
`define OR1200_CPUCFGR_NSGF 4'h0
`define OR1200_CPUCFGR_HGF 1'b0
`define OR1200_CPUCFGR_OB32S 1'b1
`define OR1200_CPUCFGR_OB64S 1'b0
`define OR1200_CPUCFGR_OF32S 1'b0
`define OR1200_CPUCFGR_OF64S 1'b0
`define OR1200_CPUCFGR_OV64S 1'b0
`define OR1200_CPUCFGR_RES1 22'h000000
// DMMUCFGR fields
`define OR1200_DMMUCFGR_NTW_BITS 1:0
`define OR1200_DMMUCFGR_NTS_BITS 4:2
`define OR1200_DMMUCFGR_NAE_BITS 7:5
`define OR1200_DMMUCFGR_CRI_BITS 8
`define OR1200_DMMUCFGR_PRI_BITS 9
`define OR1200_DMMUCFGR_TEIRI_BITS 10
`define OR1200_DMMUCFGR_HTR_BITS 11
`define OR1200_DMMUCFGR_RES1_BITS 31:12
// DMMUCFGR values
`ifdef OR1200_NO_DMMU
`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_RES1 20'h00000
`else
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl.
`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_DMMUCFGR_RES1 20'h00000
`endif
// IMMUCFGR fields
`define OR1200_IMMUCFGR_NTW_BITS 1:0
`define OR1200_IMMUCFGR_NTS_BITS 4:2
`define OR1200_IMMUCFGR_NAE_BITS 7:5
`define OR1200_IMMUCFGR_CRI_BITS 8
`define OR1200_IMMUCFGR_PRI_BITS 9
`define OR1200_IMMUCFGR_TEIRI_BITS 10
`define OR1200_IMMUCFGR_HTR_BITS 11
`define OR1200_IMMUCFGR_RES1_BITS 31:12
// IMMUCFGR values
`ifdef OR1200_NO_IMMU
`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_RES1 20'h00000
`else
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl
`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_IMMUCFGR_RES1 20'h00000
`endif
// DCCFGR fields
`define OR1200_DCCFGR_NCW_BITS 2:0
`define OR1200_DCCFGR_NCS_BITS 6:3
`define OR1200_DCCFGR_CBS_BITS 7
`define OR1200_DCCFGR_CWS_BITS 8
`define OR1200_DCCFGR_CCRI_BITS 9
`define OR1200_DCCFGR_CBIRI_BITS 10
`define OR1200_DCCFGR_CBPRI_BITS 11
`define OR1200_DCCFGR_CBLRI_BITS 12
`define OR1200_DCCFGR_CBFRI_BITS 13
`define OR1200_DCCFGR_CBWBRI_BITS 14
`define OR1200_DCCFGR_RES1_BITS 31:15
// DCCFGR values
`ifdef OR1200_NO_DC
`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant
`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant
`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CCRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBIRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBFRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_RES1 17'h00000
`else
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
`define OR1200_DCCFGR_RES1 17'h00000
`endif
// ICCFGR fields
`define OR1200_ICCFGR_NCW_BITS 2:0
`define OR1200_ICCFGR_NCS_BITS 6:3
`define OR1200_ICCFGR_CBS_BITS 7
`define OR1200_ICCFGR_CWS_BITS 8
`define OR1200_ICCFGR_CCRI_BITS 9
`define OR1200_ICCFGR_CBIRI_BITS 10
`define OR1200_ICCFGR_CBPRI_BITS 11
`define OR1200_ICCFGR_CBLRI_BITS 12
`define OR1200_ICCFGR_CBFRI_BITS 13
`define OR1200_ICCFGR_CBWBRI_BITS 14
`define OR1200_ICCFGR_RES1_BITS 31:15
// ICCFGR values
`ifdef OR1200_NO_IC
`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant
`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant
`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`else
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`endif
// DCFGR fields
`define OR1200_DCFGR_NDP_BITS 2:0
`define OR1200_DCFGR_WPCI_BITS 3
`define OR1200_DCFGR_RES1_BITS 31:4
// DCFGR values
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
`ifdef OR1200_DU_DWCR0
`define OR1200_DCFGR_WPCI 1'b1
`else
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`else
`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`define OR1200_DCFGR_RES1 28'h0000000
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311OI_BLACKBOX_V
`define SKY130_FD_SC_LS__A311OI_BLACKBOX_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a311oi (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311OI_BLACKBOX_V
|
// Double buffering with dual-port RAM
// Uses dual-port RAM to write switches to one section, while reading another to control LEDs.
// Flip SW0 to swap the buffers.
module top (
input clk,
input [15:0] sw,
output [15:0] led,
// not used
input rx,
output tx
);
assign tx = rx; // TODO(#658): Remove this work-around
wire [4:0] addr;
wire ram_out;
wire ram_in;
RAM_SHIFTER #(
.IO_WIDTH(16),
.ADDR_WIDTH(5)
) shifter (
.clk(clk),
.in(sw),
.out(led),
.addr(addr),
.ram_out(ram_out),
.ram_in(ram_in)
);
RAM64X1D #(
.INIT(64'h96A5_96A5_96A5_96A5)
) ram0 (
.WCLK(clk),
.A5(sw[0]),
.A4(addr[4]),
.A3(addr[3]),
.A2(addr[2]),
.A1(addr[1]),
.A0(addr[0]),
.DPRA5(~sw[0]),
.DPRA4(addr[4]),
.DPRA3(addr[3]),
.DPRA2(addr[2]),
.DPRA1(addr[1]),
.DPRA0(addr[0]),
.DPO(ram_out),
.D(ram_in),
.WE(1'b1)
);
endmodule
|
//======================================================================
//
// entropy.v
// ---------
// digital HW based entropy generator.
//
//
// Author: Bernd Paysan, Joachim Strombergson
// Copyright (c) 2014, Bernd Paysan, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module entropy(input wire clk,
input wire nreset,
input wire cs,
input wire we,
input wire [7:0] addr,
input wire [15:0] dwrite,
output wire [31:0] dread,
output wire [7 : 0] debug
);
//----------------------------------------------------------------
// Symbolic names.
//----------------------------------------------------------------
// Delay in cycles between sampling random values
// and updating the debug port.
// Corresponds to about 1/10s with clock @ 50 MHz.
parameter DELAY_MAX = 32'h004c4b40;
parameter ADDR_ENT_WR_RNG1 = 8'h00;
parameter ADDR_ENT_WR_RNG2 = 8'h01;
parameter ADDR_ENT_RD_RNG1_RNG2 = 8'h10;
parameter ADDR_ENT_RD_P = 8'h11;
parameter ADDR_ENT_RD_N = 8'h12;
parameter ADDR_ENT_MIX = 8'h20;
parameter ADDR_ENT_CONCAT = 8'h21;
//----------------------------------------------------------------
// Registers.
//----------------------------------------------------------------
reg [7:0] rng1, rng2; // must be inverse to each other
reg [31 : 0] delay_ctr_reg;
reg [31 : 0] delay_ctr_new;
reg [7 : 0] debug_reg;
reg [31 : 0] mix_reg;
reg [31 : 0] concat_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [31 : 0] p, n;
reg [31 : 0] tmp_dread;
//----------------------------------------------------------------
// Module instantiations.
//----------------------------------------------------------------
genvar i;
generate
for(i=0; i<32; i=i+1) begin: tworoscs
rosc px(clk, nreset, rng1, rng2, p[i]);
rosc nx(clk, nreset, rng1, rng2, n[i]);
end
endgenerate
//----------------------------------------------------------------
// Concurrent assignments to connect output ports.
//----------------------------------------------------------------
assign dread = tmp_dread;
assign debug = debug_reg;
//----------------------------------------------------------------
// reg updates
//----------------------------------------------------------------
always @(posedge clk or negedge nreset)
begin
if(!nreset)
begin
rng1 <= 8'h55;
rng2 <= 8'haa;
delay_ctr_reg <= 32'h00000000;
mix_reg <= 32'h00000000;
concat_reg <= 32'h00000000;
debug_reg <= 8'h00;
end
else
begin
delay_ctr_reg <= delay_ctr_new;
mix_reg <= n ^ p;
concat_reg <= {n[31 : 16] ^ n[15 : 0], p[31 : 16] ^ p[15 : 0]};
if (delay_ctr_reg == 32'h00000000)
begin
debug_reg <= n[7 : 0];
end
if(cs & we)
begin
case(addr)
ADDR_ENT_WR_RNG1: rng1 <= dwrite[15:8];
ADDR_ENT_WR_RNG2: rng2 <= dwrite[7:0];
default:;
endcase
end
end
end
//----------------------------------------------------------------
// read_data
//----------------------------------------------------------------
always @*
begin : read_data
tmp_dread = 16'h0000;
if(cs & ~we)
case(addr)
ADDR_ENT_RD_RNG1_RNG2: tmp_dread = {16'h0000, rng1, rng2};
ADDR_ENT_RD_P: tmp_dread = p;
ADDR_ENT_RD_N: tmp_dread = n;
ADDR_ENT_MIX: tmp_dread = mix_reg;
ADDR_ENT_CONCAT: tmp_dread = concat_reg;
default:;
endcase
end
//----------------------------------------------------------------
// delay_ctr
//
// Simple counter that counts to DELAY_MAC. Used to slow down
// the debug port updates to human speeds.
//----------------------------------------------------------------
always @*
begin : delay_ctr
if (delay_ctr_reg == DELAY_MAX)
begin
delay_ctr_new = 32'h00000000;
end
else
begin
delay_ctr_new = delay_ctr_reg + 1'b1;
end
end // delay_ctr
endmodule // entropy
//======================================================================
// EOF entropy.v
//======================================================================
|
module REG_OUT_INTERFACE(ow_od, r_address, iw_od_0x00, iw_od_0x01, iw_od_0x02, iw_od_0x03, iw_od_0x04, iw_od_0x05, iw_od_0x06, iw_od_0x07, iw_od_0x08, iw_od_0x09, iw_od_0x0A, iw_od_0x0B, iw_od_0x10, iw_od_0x11, iw_od_0x12, iw_od_0x13, iw_od_0x14, iw_od_0x15, iw_od_0x18, iw_od_0x19, iw_od_0x1A, iw_od_0x1B, iw_od_0x1C, iw_od_0x1D, iw_od_0x1E, iw_od_0x1F, iw_od_0x23, iw_od_0x24, iw_od_0x25, iw_od_0x26, iw_od_0x27, iw_od_0x28, iw_od_0x29, iw_od_0x2E, iw_od_0x2F, iw_od_0x30, iw_od_0x31, iw_od_0x32, iw_od_0x33, iw_od_0x34, iw_od_0x35, iw_od_0x36, iw_od_0x37, iw_od_0x38, iw_od_0x39, iw_od_0x3A, iw_od_0x3B, iw_od_0x3C, iw_od_0x3D, iw_od_0x3E, iw_od_0x3F, iw_od_0x40, iw_od_0x41, iw_od_0x42, iw_od_0x43, iw_od_0x44, iw_od_0x45, iw_od_0x46, iw_od_0x47, iw_od_0x48, iw_od_0x49, iw_od_0x4A, iw_od_0x4B, iw_od_0x4C, iw_od_0x4D, iw_od_0x4E, iw_od_0x4F, iw_od_0x50, iw_od_0x51, iw_od_0x52, iw_od_0x53, iw_od_0x54, iw_od_0x55, iw_od_0x56, iw_od_0x57, iw_od_0x58, iw_od_0x59, iw_od_0x5A, iw_od_0x5B, iw_od_0x5C, iw_od_0x5D, iw_od_0x5E, iw_od_0x5F, iw_od_0x60, iw_od_0x61, iw_od_0x62, iw_od_0x63, iw_od_0x64, iw_od_0x65, iw_od_0x66, iw_od_0x67, iw_od_0x68, iw_od_0x69, iw_od_0x6A, iw_od_0x6B, iw_od_0x6C, iw_od_0x6D, iw_od_0x6E, iw_od_0x6F);
output wire[7:0] ow_od;
input wire [7:0] r_address;
input wire [7:0] iw_od_0x00, iw_od_0x01, iw_od_0x02, iw_od_0x03, iw_od_0x04, iw_od_0x05, iw_od_0x06, iw_od_0x07, iw_od_0x08, iw_od_0x09, iw_od_0x0A, iw_od_0x0B, iw_od_0x10, iw_od_0x11, iw_od_0x12, iw_od_0x13, iw_od_0x14, iw_od_0x15, iw_od_0x18, iw_od_0x19, iw_od_0x1A, iw_od_0x1B, iw_od_0x1C, iw_od_0x1D, iw_od_0x1E, iw_od_0x1F, iw_od_0x23, iw_od_0x24, iw_od_0x25, iw_od_0x26, iw_od_0x27, iw_od_0x28, iw_od_0x29, iw_od_0x2E, iw_od_0x2F, iw_od_0x30, iw_od_0x31, iw_od_0x32, iw_od_0x33, iw_od_0x34, iw_od_0x35, iw_od_0x36, iw_od_0x37, iw_od_0x38, iw_od_0x39, iw_od_0x3A, iw_od_0x3B, iw_od_0x3C, iw_od_0x3D, iw_od_0x3E, iw_od_0x3F, iw_od_0x40, iw_od_0x41, iw_od_0x42, iw_od_0x43, iw_od_0x44, iw_od_0x45, iw_od_0x46, iw_od_0x47, iw_od_0x48, iw_od_0x49, iw_od_0x4A, iw_od_0x4B, iw_od_0x4C, iw_od_0x4D, iw_od_0x4E, iw_od_0x4F, iw_od_0x50, iw_od_0x51, iw_od_0x52, iw_od_0x53, iw_od_0x54, iw_od_0x55, iw_od_0x56, iw_od_0x57, iw_od_0x58, iw_od_0x59, iw_od_0x5A, iw_od_0x5B, iw_od_0x5C, iw_od_0x5D, iw_od_0x5E, iw_od_0x5F, iw_od_0x60, iw_od_0x61, iw_od_0x62, iw_od_0x63, iw_od_0x64, iw_od_0x65, iw_od_0x66, iw_od_0x67, iw_od_0x68, iw_od_0x69, iw_od_0x6A, iw_od_0x6B, iw_od_0x6C, iw_od_0x6D, iw_od_0x6E, iw_od_0x6F;
assign ow_od=(r_address==8'h00)? iw_od_0x00 : (r_address==8'h01)? iw_od_0x01 : (r_address==8'h02)? iw_od_0x02 : (r_address==8'h03)? iw_od_0x03 : (r_address==8'h04)? iw_od_0x04 : (r_address==8'h05)? iw_od_0x05 : (r_address==8'h06)? iw_od_0x06 : (r_address==8'h07)? iw_od_0x07 : (r_address==8'h08)? iw_od_0x08 : (r_address==8'h09)? iw_od_0x09 : (r_address==8'h0A)? iw_od_0x0A : (r_address==8'h0B)? iw_od_0x0B : (r_address==8'h10)? iw_od_0x10 : (r_address==8'h11)? iw_od_0x11 : (r_address==8'h12)? iw_od_0x12 : (r_address==8'h13)? iw_od_0x13 : (r_address==8'h14)? iw_od_0x14 : (r_address==8'h15)? iw_od_0x15 : (r_address==8'h18)? iw_od_0x18 : (r_address==8'h19)? iw_od_0x19 : (r_address==8'h1A)? iw_od_0x1A : (r_address==8'h1B)? iw_od_0x1B : (r_address==8'h1C)? iw_od_0x1C : (r_address==8'h1D)? iw_od_0x1D : (r_address==8'h1E)? iw_od_0x1E : (r_address==8'h1F)? iw_od_0x1F : (r_address==8'h23)? iw_od_0x23 : (r_address==8'h24)? iw_od_0x24 : (r_address==8'h25)? iw_od_0x25 : (r_address==8'h26)? iw_od_0x26 : (r_address==8'h27)? iw_od_0x27 : (r_address==8'h28)? iw_od_0x28 : (r_address==8'h29)? iw_od_0x29 : (r_address==8'h2E)? iw_od_0x2E : (r_address==8'h2F)? iw_od_0x2F : (r_address==8'h30)? iw_od_0x30 : (r_address==8'h31)? iw_od_0x31 : (r_address==8'h32)? iw_od_0x32 : (r_address==8'h33)? iw_od_0x33 : (r_address==8'h34)? iw_od_0x34 : (r_address==8'h35)? iw_od_0x35 : (r_address==8'h36)? iw_od_0x36 : (r_address==8'h37)? iw_od_0x37 : (r_address==8'h38)? iw_od_0x38 : (r_address==8'h39)? iw_od_0x39 : (r_address==8'h3A)? iw_od_0x3A : (r_address==8'h3B)? iw_od_0x3B : (r_address==8'h3C)? iw_od_0x3C : (r_address==8'h3D)? iw_od_0x3D : (r_address==8'h3E)? iw_od_0x3E : (r_address==8'h3F)? iw_od_0x3F : (r_address==8'h40)? iw_od_0x40 : (r_address==8'h41)? iw_od_0x41 : (r_address==8'h42)? iw_od_0x42 : (r_address==8'h43)? iw_od_0x43 : (r_address==8'h44)? iw_od_0x44 : (r_address==8'h45)? iw_od_0x45 : (r_address==8'h46)? iw_od_0x46 : (r_address==8'h47)? iw_od_0x47 : (r_address==8'h48)? iw_od_0x48 : (r_address==8'h49)? iw_od_0x49 : (r_address==8'h4A)? iw_od_0x4A : (r_address==8'h4B)? iw_od_0x4B : (r_address==8'h4C)? iw_od_0x4C : (r_address==8'h4D)? iw_od_0x4D : (r_address==8'h4E)? iw_od_0x4E : (r_address==8'h4F)? iw_od_0x4F : (r_address==8'h50)? iw_od_0x50 : (r_address==8'h51)? iw_od_0x51 : (r_address==8'h52)? iw_od_0x52 : (r_address==8'h53)? iw_od_0x53 : (r_address==8'h54)? iw_od_0x54 : (r_address==8'h55)? iw_od_0x55 : (r_address==8'h56)? iw_od_0x56 : (r_address==8'h57)? iw_od_0x57 : (r_address==8'h58)? iw_od_0x58 : (r_address==8'h59)? iw_od_0x59 : (r_address==8'h5A)? iw_od_0x5A : (r_address==8'h5B)? iw_od_0x5B : (r_address==8'h5C)? iw_od_0x5C : (r_address==8'h5D)? iw_od_0x5D : (r_address==8'h5E)? iw_od_0x5E : (r_address==8'h5F)? iw_od_0x5F : (r_address==8'h60)? iw_od_0x60 : (r_address==8'h61)? iw_od_0x61 : (r_address==8'h62)? iw_od_0x62 : (r_address==8'h63)? iw_od_0x63 : (r_address==8'h64)? iw_od_0x64 : (r_address==8'h65)? iw_od_0x65 : (r_address==8'h66)? iw_od_0x66 : (r_address==8'h67)? iw_od_0x67 : (r_address==8'h68)? iw_od_0x68 : (r_address==8'h69)? iw_od_0x69 : (r_address==8'h6A)? iw_od_0x6A : (r_address==8'h6B)? iw_od_0x6B : (r_address==8'h6C)? iw_od_0x6C : (r_address==8'h6D)? iw_od_0x6D : (r_address==8'h6E)? iw_od_0x6E : (r_address==8'h6F)? iw_od_0x6F : 8'bzzzzzzzz;
endmodule
module REG_IN_INTERFACE(ow_id_0x10, ow_id_0x11, ow_id_0x12, ow_id_0x13, ow_id_0x14, ow_id_0x15, ow_id_0x18, ow_id_0x19, ow_id_0x1A, ow_id_0x1B, ow_id_0x1C, ow_id_0x1D, ow_id_0x1E, ow_id_0x1F, ow_id_0x23, ow_id_0x24, ow_id_0x25, ow_id_0x26, ow_id_0x27, ow_id_0x28, ow_id_0x29, ow_id_0x2E, ow_id_0x2F, ow_id_0x30, ow_id_0x31, ow_id_0x32, ow_id_0x33, ow_id_0x34, ow_id_0x35, ow_id_0x36, ow_id_0x37, ow_id_0x38, ow_id_0x39, ow_id_0x3A, ow_id_0x3B, ow_id_0x3C, ow_id_0x3D, ow_id_0x3E, ow_id_0x3F, ow_id_0x40, ow_id_0x41, ow_id_0x42, ow_id_0x43, ow_id_0x44, ow_id_0x45, ow_id_0x46, ow_id_0x47, ow_id_0x48, ow_id_0x49, ow_id_0x4A, ow_id_0x4B, ow_id_0x4C, ow_id_0x4D, ow_id_0x4E, ow_id_0x4F, ow_id_0x50, ow_id_0x51, ow_id_0x52, ow_id_0x53, ow_id_0x54, ow_id_0x55, ow_id_0x56, ow_id_0x57, ow_id_0x58, ow_id_0x59, ow_id_0x5A, ow_id_0x5B, ow_id_0x5C, ow_id_0x5D, ow_id_0x5E, ow_id_0x5F, ow_id_0x60, ow_id_0x61, ow_id_0x62, ow_id_0x63, ow_id_0x64, ow_id_0x65, ow_id_0x66, ow_id_0x67, ow_id_0x68, ow_id_0x69, ow_id_0x6A, ow_id_0x6B, ow_id_0x6C, ow_id_0x6D, ow_id_0x6E, ow_id_0x6F, ow_enb_0x10, ow_enb_0x11, ow_enb_0x12, ow_enb_0x13, ow_enb_0x14, ow_enb_0x15, ow_enb_0x18, ow_enb_0x19, ow_enb_0x1A, ow_enb_0x1B, ow_enb_0x1C, ow_enb_0x1D, ow_enb_0x1E, ow_enb_0x1F, ow_enb_0x23, ow_enb_0x24, ow_enb_0x25, ow_enb_0x26, ow_enb_0x27, ow_enb_0x28, ow_enb_0x29, ow_enb_0x2E, ow_enb_0x2F, ow_enb_0x30, ow_enb_0x31, ow_enb_0x32, ow_enb_0x33, ow_enb_0x34, ow_enb_0x35, ow_enb_0x36, ow_enb_0x37, ow_enb_0x38, ow_enb_0x39, ow_enb_0x3A, ow_enb_0x3B, ow_enb_0x3C, ow_enb_0x3D, ow_enb_0x3E, ow_enb_0x3F, ow_enb_0x40, ow_enb_0x41, ow_enb_0x42, ow_enb_0x43, ow_enb_0x44, ow_enb_0x45, ow_enb_0x46, ow_enb_0x47, ow_enb_0x48, ow_enb_0x49, ow_enb_0x4A, ow_enb_0x4B, ow_enb_0x4C, ow_enb_0x4D, ow_enb_0x4E, ow_enb_0x4F, ow_enb_0x50, ow_enb_0x51, ow_enb_0x52, ow_enb_0x53, ow_enb_0x54, ow_enb_0x55, ow_enb_0x56, ow_enb_0x57, ow_enb_0x58, ow_enb_0x59, ow_enb_0x5A, ow_enb_0x5B, ow_enb_0x5C, ow_enb_0x5D, ow_enb_0x5E, ow_enb_0x5F, ow_enb_0x60, ow_enb_0x61, ow_enb_0x62, ow_enb_0x63, ow_enb_0x64, ow_enb_0x65, ow_enb_0x66, ow_enb_0x67, ow_enb_0x68, ow_enb_0x69, ow_enb_0x6A, ow_enb_0x6B, ow_enb_0x6C, ow_enb_0x6D, ow_enb_0x6E, ow_enb_0x6F, r_address, iw_id, iw_r_enb);
output wire [7:0] ow_id_0x10, ow_id_0x11, ow_id_0x12, ow_id_0x13, ow_id_0x14, ow_id_0x15, ow_id_0x18, ow_id_0x19, ow_id_0x1A, ow_id_0x1B, ow_id_0x1C, ow_id_0x1D, ow_id_0x1E, ow_id_0x1F, ow_id_0x23, ow_id_0x24, ow_id_0x25, ow_id_0x26, ow_id_0x27, ow_id_0x28, ow_id_0x29, ow_id_0x2E, ow_id_0x2F, ow_id_0x30, ow_id_0x31, ow_id_0x32, ow_id_0x33, ow_id_0x34, ow_id_0x35, ow_id_0x36, ow_id_0x37, ow_id_0x38, ow_id_0x39, ow_id_0x3A, ow_id_0x3B, ow_id_0x3C, ow_id_0x3D, ow_id_0x3E, ow_id_0x3F, ow_id_0x40, ow_id_0x41, ow_id_0x42, ow_id_0x43, ow_id_0x44, ow_id_0x45, ow_id_0x46, ow_id_0x47, ow_id_0x48, ow_id_0x49, ow_id_0x4A, ow_id_0x4B, ow_id_0x4C, ow_id_0x4D, ow_id_0x4E, ow_id_0x4F, ow_id_0x50, ow_id_0x51, ow_id_0x52, ow_id_0x53, ow_id_0x54, ow_id_0x55, ow_id_0x56, ow_id_0x57, ow_id_0x58, ow_id_0x59, ow_id_0x5A, ow_id_0x5B, ow_id_0x5C, ow_id_0x5D, ow_id_0x5E, ow_id_0x5F, ow_id_0x60, ow_id_0x61, ow_id_0x62, ow_id_0x63, ow_id_0x64, ow_id_0x65, ow_id_0x66, ow_id_0x67, ow_id_0x68, ow_id_0x69, ow_id_0x6A, ow_id_0x6B, ow_id_0x6C, ow_id_0x6D, ow_id_0x6E, ow_id_0x6F;
output wire ow_enb_0x10, ow_enb_0x11, ow_enb_0x12, ow_enb_0x13, ow_enb_0x14, ow_enb_0x15, ow_enb_0x18, ow_enb_0x19, ow_enb_0x1A, ow_enb_0x1B, ow_enb_0x1C, ow_enb_0x1D, ow_enb_0x1E, ow_enb_0x1F, ow_enb_0x23, ow_enb_0x24, ow_enb_0x25, ow_enb_0x26, ow_enb_0x27, ow_enb_0x28, ow_enb_0x29, ow_enb_0x2E, ow_enb_0x2F, ow_enb_0x30, ow_enb_0x31, ow_enb_0x32, ow_enb_0x33, ow_enb_0x34, ow_enb_0x35, ow_enb_0x36, ow_enb_0x37, ow_enb_0x38, ow_enb_0x39, ow_enb_0x3A, ow_enb_0x3B, ow_enb_0x3C, ow_enb_0x3D, ow_enb_0x3E, ow_enb_0x3F, ow_enb_0x40, ow_enb_0x41, ow_enb_0x42, ow_enb_0x43, ow_enb_0x44, ow_enb_0x45, ow_enb_0x46, ow_enb_0x47, ow_enb_0x48, ow_enb_0x49, ow_enb_0x4A, ow_enb_0x4B, ow_enb_0x4C, ow_enb_0x4D, ow_enb_0x4E, ow_enb_0x4F, ow_enb_0x50, ow_enb_0x51, ow_enb_0x52, ow_enb_0x53, ow_enb_0x54, ow_enb_0x55, ow_enb_0x56, ow_enb_0x57, ow_enb_0x58, ow_enb_0x59, ow_enb_0x5A, ow_enb_0x5B, ow_enb_0x5C, ow_enb_0x5D, ow_enb_0x5E, ow_enb_0x5F, ow_enb_0x60, ow_enb_0x61, ow_enb_0x62, ow_enb_0x63, ow_enb_0x64, ow_enb_0x65, ow_enb_0x66, ow_enb_0x67, ow_enb_0x68, ow_enb_0x69, ow_enb_0x6A, ow_enb_0x6B, ow_enb_0x6C, ow_enb_0x6D, ow_enb_0x6E, ow_enb_0x6F;
input wire [7:0] iw_id, r_address;
input wire iw_r_enb;
assign ow_id_0x10=(r_address==8'h10)?iw_id:8'h00;
assign ow_enb_0x10=(r_address==8'h10)?iw_r_enb:1'b1;
assign ow_id_0x11=(r_address==8'h11)?iw_id:8'h00;
assign ow_enb_0x11=(r_address==8'h11)?iw_r_enb:1'b1;
assign ow_id_0x12=(r_address==8'h12)?iw_id:8'h00;
assign ow_enb_0x12=(r_address==8'h12)?iw_r_enb:1'b1;
assign ow_id_0x13=(r_address==8'h13)?iw_id:8'h00;
assign ow_enb_0x13=(r_address==8'h13)?iw_r_enb:1'b1;
assign ow_id_0x14=(r_address==8'h14)?iw_id:8'h00;
assign ow_enb_0x14=(r_address==8'h14)?iw_r_enb:1'b1;
assign ow_id_0x15=(r_address==8'h15)?iw_id:8'h00;
assign ow_enb_0x15=(r_address==8'h15)?iw_r_enb:1'b1;
assign ow_id_0x18=(r_address==8'h18)?iw_id:8'h00;
assign ow_enb_0x18=(r_address==8'h18)?iw_r_enb:1'b1;
assign ow_id_0x19=(r_address==8'h19)?iw_id:8'h00;
assign ow_enb_0x19=(r_address==8'h19)?iw_r_enb:1'b1;
assign ow_id_0x1A=(r_address==8'h1A)?iw_id:8'h00;
assign ow_enb_0x1A=(r_address==8'h1A)?iw_r_enb:1'b1;
assign ow_id_0x1B=(r_address==8'h1B)?iw_id:8'h00;
assign ow_enb_0x1B=(r_address==8'h1B)?iw_r_enb:1'b1;
assign ow_id_0x1C=(r_address==8'h1C)?iw_id:8'h00;
assign ow_enb_0x1C=(r_address==8'h1C)?iw_r_enb:1'b1;
assign ow_id_0x1D=(r_address==8'h1D)?iw_id:8'h00;
assign ow_enb_0x1D=(r_address==8'h1D)?iw_r_enb:1'b1;
assign ow_id_0x1E=(r_address==8'h1E)?iw_id:8'h00;
assign ow_enb_0x1E=(r_address==8'h1E)?iw_r_enb:1'b1;
assign ow_id_0x1F=(r_address==8'h1F)?iw_id:8'h00;
assign ow_enb_0x1F=(r_address==8'h1F)?iw_r_enb:1'b1;
assign ow_id_0x23=(r_address==8'h23)?iw_id:8'h00;
assign ow_enb_0x23=(r_address==8'h23)?iw_r_enb:1'b1;
assign ow_id_0x24=(r_address==8'h24)?iw_id:8'h00;
assign ow_enb_0x24=(r_address==8'h24)?iw_r_enb:1'b1;
assign ow_id_0x25=(r_address==8'h25)?iw_id:8'h00;
assign ow_enb_0x25=(r_address==8'h25)?iw_r_enb:1'b1;
assign ow_id_0x26=(r_address==8'h26)?iw_id:8'h00;
assign ow_enb_0x26=(r_address==8'h26)?iw_r_enb:1'b1;
assign ow_id_0x27=(r_address==8'h27)?iw_id:8'h00;
assign ow_enb_0x27=(r_address==8'h27)?iw_r_enb:1'b1;
assign ow_id_0x28=(r_address==8'h28)?iw_id:8'h00;
assign ow_enb_0x28=(r_address==8'h28)?iw_r_enb:1'b1;
assign ow_id_0x29=(r_address==8'h29)?iw_id:8'h00;
assign ow_enb_0x29=(r_address==8'h29)?iw_r_enb:1'b1;
assign ow_id_0x2E=(r_address==8'h2E)?iw_id:8'h00;
assign ow_enb_0x2E=(r_address==8'h2E)?iw_r_enb:1'b1;
assign ow_id_0x2F=(r_address==8'h2F)?iw_id:8'h00;
assign ow_enb_0x2F=(r_address==8'h2F)?iw_r_enb:1'b1;
assign ow_id_0x30=(r_address==8'h30)?iw_id:8'h00;
assign ow_enb_0x30=(r_address==8'h30)?iw_r_enb:1'b1;
assign ow_id_0x31=(r_address==8'h31)?iw_id:8'h00;
assign ow_enb_0x31=(r_address==8'h31)?iw_r_enb:1'b1;
assign ow_id_0x32=(r_address==8'h32)?iw_id:8'h00;
assign ow_enb_0x32=(r_address==8'h32)?iw_r_enb:1'b1;
assign ow_id_0x33=(r_address==8'h33)?iw_id:8'h00;
assign ow_enb_0x33=(r_address==8'h33)?iw_r_enb:1'b1;
assign ow_id_0x34=(r_address==8'h34)?iw_id:8'h00;
assign ow_enb_0x34=(r_address==8'h34)?iw_r_enb:1'b1;
assign ow_id_0x35=(r_address==8'h35)?iw_id:8'h00;
assign ow_enb_0x35=(r_address==8'h35)?iw_r_enb:1'b1;
assign ow_id_0x36=(r_address==8'h36)?iw_id:8'h00;
assign ow_enb_0x36=(r_address==8'h36)?iw_r_enb:1'b1;
assign ow_id_0x37=(r_address==8'h37)?iw_id:8'h00;
assign ow_enb_0x37=(r_address==8'h37)?iw_r_enb:1'b1;
assign ow_id_0x38=(r_address==8'h38)?iw_id:8'h00;
assign ow_enb_0x38=(r_address==8'h38)?iw_r_enb:1'b1;
assign ow_id_0x39=(r_address==8'h39)?iw_id:8'h00;
assign ow_enb_0x39=(r_address==8'h39)?iw_r_enb:1'b1;
assign ow_id_0x3A=(r_address==8'h3A)?iw_id:8'h00;
assign ow_enb_0x3A=(r_address==8'h3A)?iw_r_enb:1'b1;
assign ow_id_0x3B=(r_address==8'h3B)?iw_id:8'h00;
assign ow_enb_0x3B=(r_address==8'h3B)?iw_r_enb:1'b1;
assign ow_id_0x3C=(r_address==8'h3C)?iw_id:8'h00;
assign ow_enb_0x3C=(r_address==8'h3C)?iw_r_enb:1'b1;
assign ow_id_0x3D=(r_address==8'h3D)?iw_id:8'h00;
assign ow_enb_0x3D=(r_address==8'h3D)?iw_r_enb:1'b1;
assign ow_id_0x3E=(r_address==8'h3E)?iw_id:8'h00;
assign ow_enb_0x3E=(r_address==8'h3E)?iw_r_enb:1'b1;
assign ow_id_0x3F=(r_address==8'h3F)?iw_id:8'h00;
assign ow_enb_0x3F=(r_address==8'h3F)?iw_r_enb:1'b1;
assign ow_id_0x40=(r_address==8'h40)?iw_id:8'h00;
assign ow_enb_0x40=(r_address==8'h40)?iw_r_enb:1'b1;
assign ow_id_0x41=(r_address==8'h41)?iw_id:8'h00;
assign ow_enb_0x41=(r_address==8'h41)?iw_r_enb:1'b1;
assign ow_id_0x42=(r_address==8'h42)?iw_id:8'h00;
assign ow_enb_0x42=(r_address==8'h42)?iw_r_enb:1'b1;
assign ow_id_0x43=(r_address==8'h43)?iw_id:8'h00;
assign ow_enb_0x43=(r_address==8'h43)?iw_r_enb:1'b1;
assign ow_id_0x44=(r_address==8'h44)?iw_id:8'h00;
assign ow_enb_0x44=(r_address==8'h44)?iw_r_enb:1'b1;
assign ow_id_0x45=(r_address==8'h45)?iw_id:8'h00;
assign ow_enb_0x45=(r_address==8'h45)?iw_r_enb:1'b1;
assign ow_id_0x46=(r_address==8'h46)?iw_id:8'h00;
assign ow_enb_0x46=(r_address==8'h46)?iw_r_enb:1'b1;
assign ow_id_0x47=(r_address==8'h47)?iw_id:8'h00;
assign ow_enb_0x47=(r_address==8'h47)?iw_r_enb:1'b1;
assign ow_id_0x48=(r_address==8'h48)?iw_id:8'h00;
assign ow_enb_0x48=(r_address==8'h48)?iw_r_enb:1'b1;
assign ow_id_0x49=(r_address==8'h49)?iw_id:8'h00;
assign ow_enb_0x49=(r_address==8'h49)?iw_r_enb:1'b1;
assign ow_id_0x4A=(r_address==8'h4A)?iw_id:8'h00;
assign ow_enb_0x4A=(r_address==8'h4A)?iw_r_enb:1'b1;
assign ow_id_0x4B=(r_address==8'h4B)?iw_id:8'h00;
assign ow_enb_0x4B=(r_address==8'h4B)?iw_r_enb:1'b1;
assign ow_id_0x4C=(r_address==8'h4C)?iw_id:8'h00;
assign ow_enb_0x4C=(r_address==8'h4C)?iw_r_enb:1'b1;
assign ow_id_0x4D=(r_address==8'h4D)?iw_id:8'h00;
assign ow_enb_0x4D=(r_address==8'h4D)?iw_r_enb:1'b1;
assign ow_id_0x4E=(r_address==8'h4E)?iw_id:8'h00;
assign ow_enb_0x4E=(r_address==8'h4E)?iw_r_enb:1'b1;
assign ow_id_0x4F=(r_address==8'h4F)?iw_id:8'h00;
assign ow_enb_0x4F=(r_address==8'h4F)?iw_r_enb:1'b1;
assign ow_id_0x50=(r_address==8'h50)?iw_id:8'h00;
assign ow_enb_0x50=(r_address==8'h50)?iw_r_enb:1'b1;
assign ow_id_0x51=(r_address==8'h51)?iw_id:8'h00;
assign ow_enb_0x51=(r_address==8'h51)?iw_r_enb:1'b1;
assign ow_id_0x52=(r_address==8'h52)?iw_id:8'h00;
assign ow_enb_0x52=(r_address==8'h52)?iw_r_enb:1'b1;
assign ow_id_0x53=(r_address==8'h53)?iw_id:8'h00;
assign ow_enb_0x53=(r_address==8'h53)?iw_r_enb:1'b1;
assign ow_id_0x54=(r_address==8'h54)?iw_id:8'h00;
assign ow_enb_0x54=(r_address==8'h54)?iw_r_enb:1'b1;
assign ow_id_0x55=(r_address==8'h55)?iw_id:8'h00;
assign ow_enb_0x55=(r_address==8'h55)?iw_r_enb:1'b1;
assign ow_id_0x56=(r_address==8'h56)?iw_id:8'h00;
assign ow_enb_0x56=(r_address==8'h56)?iw_r_enb:1'b1;
assign ow_id_0x57=(r_address==8'h57)?iw_id:8'h00;
assign ow_enb_0x57=(r_address==8'h57)?iw_r_enb:1'b1;
assign ow_id_0x58=(r_address==8'h58)?iw_id:8'h00;
assign ow_enb_0x58=(r_address==8'h58)?iw_r_enb:1'b1;
assign ow_id_0x59=(r_address==8'h59)?iw_id:8'h00;
assign ow_enb_0x59=(r_address==8'h59)?iw_r_enb:1'b1;
assign ow_id_0x5A=(r_address==8'h5A)?iw_id:8'h00;
assign ow_enb_0x5A=(r_address==8'h5A)?iw_r_enb:1'b1;
assign ow_id_0x5B=(r_address==8'h5B)?iw_id:8'h00;
assign ow_enb_0x5B=(r_address==8'h5B)?iw_r_enb:1'b1;
assign ow_id_0x5C=(r_address==8'h5C)?iw_id:8'h00;
assign ow_enb_0x5C=(r_address==8'h5C)?iw_r_enb:1'b1;
assign ow_id_0x5D=(r_address==8'h5D)?iw_id:8'h00;
assign ow_enb_0x5D=(r_address==8'h5D)?iw_r_enb:1'b1;
assign ow_id_0x5E=(r_address==8'h5E)?iw_id:8'h00;
assign ow_enb_0x5E=(r_address==8'h5E)?iw_r_enb:1'b1;
assign ow_id_0x5F=(r_address==8'h5F)?iw_id:8'h00;
assign ow_enb_0x5F=(r_address==8'h5F)?iw_r_enb:1'b1;
assign ow_id_0x60=(r_address==8'h60)?iw_id:8'h00;
assign ow_enb_0x60=(r_address==8'h60)?iw_r_enb:1'b1;
assign ow_id_0x61=(r_address==8'h61)?iw_id:8'h00;
assign ow_enb_0x61=(r_address==8'h61)?iw_r_enb:1'b1;
assign ow_id_0x62=(r_address==8'h62)?iw_id:8'h00;
assign ow_enb_0x62=(r_address==8'h62)?iw_r_enb:1'b1;
assign ow_id_0x63=(r_address==8'h63)?iw_id:8'h00;
assign ow_enb_0x63=(r_address==8'h63)?iw_r_enb:1'b1;
assign ow_id_0x64=(r_address==8'h64)?iw_id:8'h00;
assign ow_enb_0x64=(r_address==8'h64)?iw_r_enb:1'b1;
assign ow_id_0x65=(r_address==8'h65)?iw_id:8'h00;
assign ow_enb_0x65=(r_address==8'h65)?iw_r_enb:1'b1;
assign ow_id_0x66=(r_address==8'h66)?iw_id:8'h00;
assign ow_enb_0x66=(r_address==8'h66)?iw_r_enb:1'b1;
assign ow_id_0x67=(r_address==8'h67)?iw_id:8'h00;
assign ow_enb_0x67=(r_address==8'h67)?iw_r_enb:1'b1;
assign ow_id_0x68=(r_address==8'h68)?iw_id:8'h00;
assign ow_enb_0x68=(r_address==8'h68)?iw_r_enb:1'b1;
assign ow_id_0x69=(r_address==8'h69)?iw_id:8'h00;
assign ow_enb_0x69=(r_address==8'h69)?iw_r_enb:1'b1;
assign ow_id_0x6A=(r_address==8'h6A)?iw_id:8'h00;
assign ow_enb_0x6A=(r_address==8'h6A)?iw_r_enb:1'b1;
assign ow_id_0x6B=(r_address==8'h6B)?iw_id:8'h00;
assign ow_enb_0x6B=(r_address==8'h6B)?iw_r_enb:1'b1;
assign ow_id_0x6C=(r_address==8'h6C)?iw_id:8'h00;
assign ow_enb_0x6C=(r_address==8'h6C)?iw_r_enb:1'b1;
assign ow_id_0x6D=(r_address==8'h6D)?iw_id:8'h00;
assign ow_enb_0x6D=(r_address==8'h6D)?iw_r_enb:1'b1;
assign ow_id_0x6E=(r_address==8'h6E)?iw_id:8'h00;
assign ow_enb_0x6E=(r_address==8'h6E)?iw_r_enb:1'b1;
assign ow_id_0x6F=(r_address==8'h6F)?iw_id:8'h00;
assign ow_enb_0x6F=(r_address==8'h6F)?iw_r_enb:1'b1;
endmodule
module REG_INTERFACE(ow_od_0, ow_od_1, ow_od_2, ow_od_transmit, ow_od_TX_BUF_HEADER_BYTE_1, ow_od_RX_BUF_HEADER_BYTE_1, ow_od_RX_BUF_FRAME_TYPE, r_address_0, r_address_1, r_address_2, iw_id_0, iw_id_1, iw_id_2, iw_enb_0, iw_enb_1, iw_enb_2, reset, clk);
output wire [7:0] ow_od_0, ow_od_1, ow_od_2, ow_od_transmit, ow_od_TX_BUF_HEADER_BYTE_1, ow_od_RX_BUF_HEADER_BYTE_1, ow_od_RX_BUF_FRAME_TYPE;
input wire [7:0] r_address_0, r_address_1, r_address_2, iw_id_0, iw_id_1, iw_id_2;
input wire iw_enb_0, iw_enb_1, iw_enb_2;
input wire reset, clk;
wire [7:0] ow_reg_0x00, ow_reg_0x01, ow_reg_0x02, ow_reg_0x03, ow_reg_0x04, ow_reg_0x05, ow_reg_0x06, ow_reg_0x07, ow_reg_0x08, ow_reg_0x09, ow_reg_0x0A, ow_reg_0x0B, ow_reg_0x10, ow_reg_0x11, ow_reg_0x12, ow_reg_0x13, ow_reg_0x14, ow_reg_0x15, ow_reg_0x18, ow_reg_0x19, ow_reg_0x1A, ow_reg_0x1B, ow_reg_0x1C, ow_reg_0x1D, ow_reg_0x1E, ow_reg_0x1F, ow_reg_0x23, ow_reg_0x24, ow_reg_0x25, ow_reg_0x26, ow_reg_0x27, ow_reg_0x28, ow_reg_0x29, ow_reg_0x2E, ow_reg_0x2F, ow_reg_0x30, ow_reg_0x31, ow_reg_0x32, ow_reg_0x33, ow_reg_0x34, ow_reg_0x35, ow_reg_0x36, ow_reg_0x37, ow_reg_0x38, ow_reg_0x39, ow_reg_0x3A, ow_reg_0x3B, ow_reg_0x3C, ow_reg_0x3D, ow_reg_0x3E, ow_reg_0x3F, ow_reg_0x40, ow_reg_0x41, ow_reg_0x42, ow_reg_0x43, ow_reg_0x44, ow_reg_0x45, ow_reg_0x46, ow_reg_0x47, ow_reg_0x48, ow_reg_0x49, ow_reg_0x4A, ow_reg_0x4B, ow_reg_0x4C, ow_reg_0x4D, ow_reg_0x4E, ow_reg_0x4F, ow_reg_0x50, ow_reg_0x51, ow_reg_0x52, ow_reg_0x53, ow_reg_0x54, ow_reg_0x55, ow_reg_0x56, ow_reg_0x57, ow_reg_0x58, ow_reg_0x59, ow_reg_0x5A, ow_reg_0x5B, ow_reg_0x5C, ow_reg_0x5D, ow_reg_0x5E, ow_reg_0x5F, ow_reg_0x60, ow_reg_0x61, ow_reg_0x62, ow_reg_0x63, ow_reg_0x64, ow_reg_0x65, ow_reg_0x66, ow_reg_0x67, ow_reg_0x68, ow_reg_0x69, ow_reg_0x6A, ow_reg_0x6B, ow_reg_0x6C, ow_reg_0x6D, ow_reg_0x6E, ow_reg_0x6F;
wire [7:0] iw_reg_0x10, iw_reg_0x11, iw_reg_0x12, iw_reg_0x13, iw_reg_0x14, iw_reg_0x15, iw_reg_0x18, iw_reg_0x19, iw_reg_0x1A, iw_reg_0x1B, iw_reg_0x1C, iw_reg_0x1D, iw_reg_0x1E, iw_reg_0x1F, iw_reg_0x23, iw_reg_0x24, iw_reg_0x25, iw_reg_0x26, iw_reg_0x27, iw_reg_0x28, iw_reg_0x29, iw_reg_0x2E, iw_reg_0x2F, iw_reg_0x30, iw_reg_0x31, iw_reg_0x32, iw_reg_0x33, iw_reg_0x34, iw_reg_0x35, iw_reg_0x36, iw_reg_0x37, iw_reg_0x38, iw_reg_0x39, iw_reg_0x3A, iw_reg_0x3B, iw_reg_0x3C, iw_reg_0x3D, iw_reg_0x3E, iw_reg_0x3F, iw_reg_0x40, iw_reg_0x41, iw_reg_0x42, iw_reg_0x43, iw_reg_0x44, iw_reg_0x45, iw_reg_0x46, iw_reg_0x47, iw_reg_0x48, iw_reg_0x49, iw_reg_0x4A, iw_reg_0x4B, iw_reg_0x4C, iw_reg_0x4D, iw_reg_0x4E, iw_reg_0x4F, iw_reg_0x50, iw_reg_0x51, iw_reg_0x52, iw_reg_0x53, iw_reg_0x54, iw_reg_0x55, iw_reg_0x56, iw_reg_0x57, iw_reg_0x58, iw_reg_0x59, iw_reg_0x5A, iw_reg_0x5B, iw_reg_0x5C, iw_reg_0x5D, iw_reg_0x5E, iw_reg_0x5F, iw_reg_0x60, iw_reg_0x61, iw_reg_0x62, iw_reg_0x63, iw_reg_0x64, iw_reg_0x65, iw_reg_0x66, iw_reg_0x67, iw_reg_0x68, iw_reg_0x69, iw_reg_0x6A, iw_reg_0x6B, iw_reg_0x6C, iw_reg_0x6D, iw_reg_0x6E, iw_reg_0x6F;
wire enb_0x10, enb_0x11, enb_0x12, enb_0x13, enb_0x14, enb_0x15, enb_0x18, enb_0x19, enb_0x1A, enb_0x1B, enb_0x1C, enb_0x1D, enb_0x1E, enb_0x1F, enb_0x23, enb_0x24, enb_0x25, enb_0x26, enb_0x27, enb_0x28, enb_0x29, enb_0x2E, enb_0x2F, enb_0x30, enb_0x31, enb_0x32, enb_0x33, enb_0x34, enb_0x35, enb_0x36, enb_0x37, enb_0x38, enb_0x39, enb_0x3A, enb_0x3B, enb_0x3C, enb_0x3D, enb_0x3E, enb_0x3F, enb_0x40, enb_0x41, enb_0x42, enb_0x43, enb_0x44, enb_0x45, enb_0x46, enb_0x47, enb_0x48, enb_0x49, enb_0x4A, enb_0x4B, enb_0x4C, enb_0x4D, enb_0x4E, enb_0x4F, enb_0x50, enb_0x51, enb_0x52, enb_0x53, enb_0x54, enb_0x55, enb_0x56, enb_0x57, enb_0x58, enb_0x59, enb_0x5A, enb_0x5B, enb_0x5C, enb_0x5D, enb_0x5E, enb_0x5F, enb_0x60, enb_0x61, enb_0x62, enb_0x63, enb_0x64, enb_0x65, enb_0x66, enb_0x67, enb_0x68, enb_0x69, enb_0x6A, enb_0x6B, enb_0x6C, enb_0x6D, enb_0x6E, enb_0x6F;
wire [7:0] ow_i0_id_0x10, ow_i0_id_0x11, ow_i0_id_0x12, ow_i0_id_0x13, ow_i0_id_0x14, ow_i0_id_0x15, ow_i0_id_0x18, ow_i0_id_0x19, ow_i0_id_0x1A, ow_i0_id_0x1B, ow_i0_id_0x1C, ow_i0_id_0x1D, ow_i0_id_0x1E, ow_i0_id_0x1F, ow_i0_id_0x23, ow_i0_id_0x24, ow_i0_id_0x25, ow_i0_id_0x26, ow_i0_id_0x27, ow_i0_id_0x28, ow_i0_id_0x29, ow_i0_id_0x2E, ow_i0_id_0x2F, ow_i0_id_0x30, ow_i0_id_0x31, ow_i0_id_0x32, ow_i0_id_0x33, ow_i0_id_0x34, ow_i0_id_0x35, ow_i0_id_0x36, ow_i0_id_0x37, ow_i0_id_0x38, ow_i0_id_0x39, ow_i0_id_0x3A, ow_i0_id_0x3B, ow_i0_id_0x3C, ow_i0_id_0x3D, ow_i0_id_0x3E, ow_i0_id_0x3F, ow_i0_id_0x40, ow_i0_id_0x41, ow_i0_id_0x42, ow_i0_id_0x43, ow_i0_id_0x44, ow_i0_id_0x45, ow_i0_id_0x46, ow_i0_id_0x47, ow_i0_id_0x48, ow_i0_id_0x49, ow_i0_id_0x4A, ow_i0_id_0x4B, ow_i0_id_0x4C, ow_i0_id_0x4D, ow_i0_id_0x4E, ow_i0_id_0x4F, ow_i0_id_0x50, ow_i0_id_0x51, ow_i0_id_0x52, ow_i0_id_0x53, ow_i0_id_0x54, ow_i0_id_0x55, ow_i0_id_0x56, ow_i0_id_0x57, ow_i0_id_0x58, ow_i0_id_0x59, ow_i0_id_0x5A, ow_i0_id_0x5B, ow_i0_id_0x5C, ow_i0_id_0x5D, ow_i0_id_0x5E, ow_i0_id_0x5F, ow_i0_id_0x60, ow_i0_id_0x61, ow_i0_id_0x62, ow_i0_id_0x63, ow_i0_id_0x64, ow_i0_id_0x65, ow_i0_id_0x66, ow_i0_id_0x67, ow_i0_id_0x68, ow_i0_id_0x69, ow_i0_id_0x6A, ow_i0_id_0x6B, ow_i0_id_0x6C, ow_i0_id_0x6D, ow_i0_id_0x6E, ow_i0_id_0x6F, ow_i1_id_0x10, ow_i1_id_0x11, ow_i1_id_0x12, ow_i1_id_0x13, ow_i1_id_0x14, ow_i1_id_0x15, ow_i1_id_0x18, ow_i1_id_0x19, ow_i1_id_0x1A, ow_i1_id_0x1B, ow_i1_id_0x1C, ow_i1_id_0x1D, ow_i1_id_0x1E, ow_i1_id_0x1F, ow_i1_id_0x23, ow_i1_id_0x24, ow_i1_id_0x25, ow_i1_id_0x26, ow_i1_id_0x27, ow_i1_id_0x28, ow_i1_id_0x29, ow_i1_id_0x2E, ow_i1_id_0x2F, ow_i1_id_0x30, ow_i1_id_0x31, ow_i1_id_0x32, ow_i1_id_0x33, ow_i1_id_0x34, ow_i1_id_0x35, ow_i1_id_0x36, ow_i1_id_0x37, ow_i1_id_0x38, ow_i1_id_0x39, ow_i1_id_0x3A, ow_i1_id_0x3B, ow_i1_id_0x3C, ow_i1_id_0x3D, ow_i1_id_0x3E, ow_i1_id_0x3F, ow_i1_id_0x40, ow_i1_id_0x41, ow_i1_id_0x42, ow_i1_id_0x43, ow_i1_id_0x44, ow_i1_id_0x45, ow_i1_id_0x46, ow_i1_id_0x47, ow_i1_id_0x48, ow_i1_id_0x49, ow_i1_id_0x4A, ow_i1_id_0x4B, ow_i1_id_0x4C, ow_i1_id_0x4D, ow_i1_id_0x4E, ow_i1_id_0x4F, ow_i1_id_0x50, ow_i1_id_0x51, ow_i1_id_0x52, ow_i1_id_0x53, ow_i1_id_0x54, ow_i1_id_0x55, ow_i1_id_0x56, ow_i1_id_0x57, ow_i1_id_0x58, ow_i1_id_0x59, ow_i1_id_0x5A, ow_i1_id_0x5B, ow_i1_id_0x5C, ow_i1_id_0x5D, ow_i1_id_0x5E, ow_i1_id_0x5F, ow_i1_id_0x60, ow_i1_id_0x61, ow_i1_id_0x62, ow_i1_id_0x63, ow_i1_id_0x64, ow_i1_id_0x65, ow_i1_id_0x66, ow_i1_id_0x67, ow_i1_id_0x68, ow_i1_id_0x69, ow_i1_id_0x6A, ow_i1_id_0x6B, ow_i1_id_0x6C, ow_i1_id_0x6D, ow_i1_id_0x6E, ow_i1_id_0x6F, ow_i2_id_0x10, ow_i2_id_0x11, ow_i2_id_0x12, ow_i2_id_0x13, ow_i2_id_0x14, ow_i2_id_0x15, ow_i2_id_0x18, ow_i2_id_0x19, ow_i2_id_0x1A, ow_i2_id_0x1B, ow_i2_id_0x1C, ow_i2_id_0x1D, ow_i2_id_0x1E, ow_i2_id_0x1F, ow_i2_id_0x23, ow_i2_id_0x24, ow_i2_id_0x25, ow_i2_id_0x26, ow_i2_id_0x27, ow_i2_id_0x28, ow_i2_id_0x29, ow_i2_id_0x2E, ow_i2_id_0x2F, ow_i2_id_0x30, ow_i2_id_0x31, ow_i2_id_0x32, ow_i2_id_0x33, ow_i2_id_0x34, ow_i2_id_0x35, ow_i2_id_0x36, ow_i2_id_0x37, ow_i2_id_0x38, ow_i2_id_0x39, ow_i2_id_0x3A, ow_i2_id_0x3B, ow_i2_id_0x3C, ow_i2_id_0x3D, ow_i2_id_0x3E, ow_i2_id_0x3F, ow_i2_id_0x40, ow_i2_id_0x41, ow_i2_id_0x42, ow_i2_id_0x43, ow_i2_id_0x44, ow_i2_id_0x45, ow_i2_id_0x46, ow_i2_id_0x47, ow_i2_id_0x48, ow_i2_id_0x49, ow_i2_id_0x4A, ow_i2_id_0x4B, ow_i2_id_0x4C, ow_i2_id_0x4D, ow_i2_id_0x4E, ow_i2_id_0x4F, ow_i2_id_0x50, ow_i2_id_0x51, ow_i2_id_0x52, ow_i2_id_0x53, ow_i2_id_0x54, ow_i2_id_0x55, ow_i2_id_0x56, ow_i2_id_0x57, ow_i2_id_0x58, ow_i2_id_0x59, ow_i2_id_0x5A, ow_i2_id_0x5B, ow_i2_id_0x5C, ow_i2_id_0x5D, ow_i2_id_0x5E, ow_i2_id_0x5F, ow_i2_id_0x60, ow_i2_id_0x61, ow_i2_id_0x62, ow_i2_id_0x63, ow_i2_id_0x64, ow_i2_id_0x65, ow_i2_id_0x66, ow_i2_id_0x67, ow_i2_id_0x68, ow_i2_id_0x69, ow_i2_id_0x6A, ow_i2_id_0x6B, ow_i2_id_0x6C, ow_i2_id_0x6D, ow_i2_id_0x6E, ow_i2_id_0x6F;
wire ow_i0_enb_0x10, ow_i0_enb_0x11, ow_i0_enb_0x12, ow_i0_enb_0x13, ow_i0_enb_0x14, ow_i0_enb_0x15, ow_i0_enb_0x18, ow_i0_enb_0x19, ow_i0_enb_0x1A, ow_i0_enb_0x1B, ow_i0_enb_0x1C, ow_i0_enb_0x1D, ow_i0_enb_0x1E, ow_i0_enb_0x1F, ow_i0_enb_0x23, ow_i0_enb_0x24, ow_i0_enb_0x25, ow_i0_enb_0x26, ow_i0_enb_0x27, ow_i0_enb_0x28, ow_i0_enb_0x29, ow_i0_enb_0x2E, ow_i0_enb_0x2F, ow_i0_enb_0x30, ow_i0_enb_0x31, ow_i0_enb_0x32, ow_i0_enb_0x33, ow_i0_enb_0x34, ow_i0_enb_0x35, ow_i0_enb_0x36, ow_i0_enb_0x37, ow_i0_enb_0x38, ow_i0_enb_0x39, ow_i0_enb_0x3A, ow_i0_enb_0x3B, ow_i0_enb_0x3C, ow_i0_enb_0x3D, ow_i0_enb_0x3E, ow_i0_enb_0x3F, ow_i0_enb_0x40, ow_i0_enb_0x41, ow_i0_enb_0x42, ow_i0_enb_0x43, ow_i0_enb_0x44, ow_i0_enb_0x45, ow_i0_enb_0x46, ow_i0_enb_0x47, ow_i0_enb_0x48, ow_i0_enb_0x49, ow_i0_enb_0x4A, ow_i0_enb_0x4B, ow_i0_enb_0x4C, ow_i0_enb_0x4D, ow_i0_enb_0x4E, ow_i0_enb_0x4F, ow_i0_enb_0x50, ow_i0_enb_0x51, ow_i0_enb_0x52, ow_i0_enb_0x53, ow_i0_enb_0x54, ow_i0_enb_0x55, ow_i0_enb_0x56, ow_i0_enb_0x57, ow_i0_enb_0x58, ow_i0_enb_0x59, ow_i0_enb_0x5A, ow_i0_enb_0x5B, ow_i0_enb_0x5C, ow_i0_enb_0x5D, ow_i0_enb_0x5E, ow_i0_enb_0x5F, ow_i0_enb_0x60, ow_i0_enb_0x61, ow_i0_enb_0x62, ow_i0_enb_0x63, ow_i0_enb_0x64, ow_i0_enb_0x65, ow_i0_enb_0x66, ow_i0_enb_0x67, ow_i0_enb_0x68, ow_i0_enb_0x69, ow_i0_enb_0x6A, ow_i0_enb_0x6B, ow_i0_enb_0x6C, ow_i0_enb_0x6D, ow_i0_enb_0x6E, ow_i0_enb_0x6F, ow_i1_enb_0x10, ow_i1_enb_0x11, ow_i1_enb_0x12, ow_i1_enb_0x13, ow_i1_enb_0x14, ow_i1_enb_0x15, ow_i1_enb_0x18, ow_i1_enb_0x19, ow_i1_enb_0x1A, ow_i1_enb_0x1B, ow_i1_enb_0x1C, ow_i1_enb_0x1D, ow_i1_enb_0x1E, ow_i1_enb_0x1F, ow_i1_enb_0x23, ow_i1_enb_0x24, ow_i1_enb_0x25, ow_i1_enb_0x26, ow_i1_enb_0x27, ow_i1_enb_0x28, ow_i1_enb_0x29, ow_i1_enb_0x2E, ow_i1_enb_0x2F, ow_i1_enb_0x30, ow_i1_enb_0x31, ow_i1_enb_0x32, ow_i1_enb_0x33, ow_i1_enb_0x34, ow_i1_enb_0x35, ow_i1_enb_0x36, ow_i1_enb_0x37, ow_i1_enb_0x38, ow_i1_enb_0x39, ow_i1_enb_0x3A, ow_i1_enb_0x3B, ow_i1_enb_0x3C, ow_i1_enb_0x3D, ow_i1_enb_0x3E, ow_i1_enb_0x3F, ow_i1_enb_0x40, ow_i1_enb_0x41, ow_i1_enb_0x42, ow_i1_enb_0x43, ow_i1_enb_0x44, ow_i1_enb_0x45, ow_i1_enb_0x46, ow_i1_enb_0x47, ow_i1_enb_0x48, ow_i1_enb_0x49, ow_i1_enb_0x4A, ow_i1_enb_0x4B, ow_i1_enb_0x4C, ow_i1_enb_0x4D, ow_i1_enb_0x4E, ow_i1_enb_0x4F, ow_i1_enb_0x50, ow_i1_enb_0x51, ow_i1_enb_0x52, ow_i1_enb_0x53, ow_i1_enb_0x54, ow_i1_enb_0x55, ow_i1_enb_0x56, ow_i1_enb_0x57, ow_i1_enb_0x58, ow_i1_enb_0x59, ow_i1_enb_0x5A, ow_i1_enb_0x5B, ow_i1_enb_0x5C, ow_i1_enb_0x5D, ow_i1_enb_0x5E, ow_i1_enb_0x5F, ow_i1_enb_0x60, ow_i1_enb_0x61, ow_i1_enb_0x62, ow_i1_enb_0x63, ow_i1_enb_0x64, ow_i1_enb_0x65, ow_i1_enb_0x66, ow_i1_enb_0x67, ow_i1_enb_0x68, ow_i1_enb_0x69, ow_i1_enb_0x6A, ow_i1_enb_0x6B, ow_i1_enb_0x6C, ow_i1_enb_0x6D, ow_i1_enb_0x6E, ow_i1_enb_0x6F, ow_i2_enb_0x10,ow_i2_enb_0x11, ow_i2_enb_0x12, ow_i2_enb_0x13, ow_i2_enb_0x14, ow_i2_enb_0x15, ow_i2_enb_0x18, ow_i2_enb_0x19, ow_i2_enb_0x1A, ow_i2_enb_0x1B, ow_i2_enb_0x1C, ow_i2_enb_0x1D, ow_i2_enb_0x1E, ow_i2_enb_0x1F, ow_i2_enb_0x23, ow_i2_enb_0x24, ow_i2_enb_0x25, ow_i2_enb_0x26, ow_i2_enb_0x27, ow_i2_enb_0x28, ow_i2_enb_0x29, ow_i2_enb_0x2E, ow_i2_enb_0x2F, ow_i2_enb_0x30, ow_i2_enb_0x31, ow_i2_enb_0x32, ow_i2_enb_0x33, ow_i2_enb_0x34, ow_i2_enb_0x35, ow_i2_enb_0x36, ow_i2_enb_0x37, ow_i2_enb_0x38, ow_i2_enb_0x39, ow_i2_enb_0x3A, ow_i2_enb_0x3B, ow_i2_enb_0x3C, ow_i2_enb_0x3D, ow_i2_enb_0x3E, ow_i2_enb_0x3F, ow_i2_enb_0x40, ow_i2_enb_0x41, ow_i2_enb_0x42, ow_i2_enb_0x43, ow_i2_enb_0x44, ow_i2_enb_0x45, ow_i2_enb_0x46, ow_i2_enb_0x47, ow_i2_enb_0x48, ow_i2_enb_0x49, ow_i2_enb_0x4A, ow_i2_enb_0x4B, ow_i2_enb_0x4C, ow_i2_enb_0x4D, ow_i2_enb_0x4E, ow_i2_enb_0x4F, ow_i2_enb_0x50, ow_i2_enb_0x51, ow_i2_enb_0x52, ow_i2_enb_0x53, ow_i2_enb_0x54, ow_i2_enb_0x55, ow_i2_enb_0x56, ow_i2_enb_0x57, ow_i2_enb_0x58, ow_i2_enb_0x59, ow_i2_enb_0x5A, ow_i2_enb_0x5B, ow_i2_enb_0x5C, ow_i2_enb_0x5D, ow_i2_enb_0x5E, ow_i2_enb_0x5F, ow_i2_enb_0x60, ow_i2_enb_0x61, ow_i2_enb_0x62, ow_i2_enb_0x63, ow_i2_enb_0x64, ow_i2_enb_0x65, ow_i2_enb_0x66, ow_i2_enb_0x67, ow_i2_enb_0x68, ow_i2_enb_0x69, ow_i2_enb_0x6A, ow_i2_enb_0x6B, ow_i2_enb_0x6C, ow_i2_enb_0x6D, ow_i2_enb_0x6E, ow_i2_enb_0x6F;
r_VENDOR_ID_LOW reg_0x00(ow_reg_0x00);
r_VENDOR_ID_HIGH reg_0x01(ow_reg_0x01);
r_PRODUCT_ID_LOW reg_0x02(ow_reg_0x02);
r_PRODUCT_ID_HIGH reg_0x03(ow_reg_0x03);
r_DEVICE_ID_LOW reg_0x04(ow_reg_0x04);
r_DEVICE_ID_HIGH reg_0x05(ow_reg_0x05);
r_USBTYPEC_REV_LOW reg_0x06(ow_reg_0x06);
r_USBTYPEC_REV_HIGH reg_0x07(ow_reg_0x07);
r_USBPD_REV_VER_LOW reg_0x08(ow_reg_0x08);
r_USBPD_REV_VER_HIGH reg_0x09(ow_reg_0x09);
r_PD_INTERFACE_REV_LOW reg_0x0A(ow_reg_0x0A);
r_PD_INTERFACE_REV_HIGH reg_0x0B(ow_reg_0x0B);
r_ALERT_LOW reg_0x10(ow_reg_0x10, reset, enb_0x10, iw_reg_0x10, clk);
r_ALERT_HIGH reg_0x11(ow_reg_0x11, reset, enb_0x11, iw_reg_0x11, clk);
r_ALERT_MASK_LOW reg_0x12(ow_reg_0x12, reset, enb_0x12, iw_reg_0x12, clk);
r_ALERT_MASK_HIGH reg_0x13(ow_reg_0x13, reset, enb_0x13, iw_reg_0x13, clk);
r_POWER_STATUS_MASK reg_0x14(ow_reg_0x14, reset, enb_0x14, iw_reg_0x14, clk);
r_FAULT_STATUS_MASK reg_0x15(ow_reg_0x15, reset, enb_0x15, iw_reg_0x15, clk);
r_CONFIG_STANDARD_OUTPUT reg_0x18(ow_reg_0x18, reset, enb_0x18, iw_reg_0x18, clk);
r_TCPC_CONTROL reg_0x19(ow_reg_0x19, reset, enb_0x19, iw_reg_0x19, clk);
r_ROLE_CONTROL reg_0x1A(ow_reg_0x1A, reset, enb_0x1A, iw_reg_0x1A, clk);
r_FAULT_CONTROL reg_0x1B(ow_reg_0x1B, reset, enb_0x1B, iw_reg_0x1B, clk);
r_POWER_CONTROL reg_0x1C(ow_reg_0x1C, reset, enb_0x1C, iw_reg_0x1C, clk);
r_CC_STATUS reg_0x1D(ow_reg_0x1D, reset, enb_0x1D, iw_reg_0x1D, clk);
r_POWER_STATUS reg_0x1E(ow_reg_0x1E, reset, enb_0x1E, iw_reg_0x1E, clk);
r_FAULT_STATUS reg_0x1F(ow_reg_0x1F, reset, enb_0x1F, iw_reg_0x1F, clk);
r_COMMAND reg_0x23(ow_reg_0x23, reset, enb_0x23, iw_reg_0x23, clk);
r_DEVICE_CAPABILITIES_1_LOW reg_0x24(ow_reg_0x24, reset, enb_0x24, iw_reg_0x24, clk);
r_DEVICE_CAPABILITIES_1_HIGH reg_0x25(ow_reg_0x25, reset, enb_0x25, iw_reg_0x25, clk);
r_DEVICE_CAPABILITIES_2_LOW reg_0x26(ow_reg_0x26, reset, enb_0x26, iw_reg_0x26, clk);
r_DEVICE_CAPABILITIES_2_HIGH reg_0x27(ow_reg_0x27, reset, enb_0x27, iw_reg_0x27, clk);
r_STANDARD_INPUT_CAPABILITIES reg_0x28(ow_reg_0x28, reset, enb_0x28, iw_reg_0x28, clk);
r_STANDARD_OUTPUT_CAPABILITIES reg_0x29(ow_reg_0x29, reset, enb_0x29, iw_reg_0x29, clk);
r_MESSAGE_HEADER_INFO reg_0x2E(ow_reg_0x2E, reset, enb_0x2E, iw_reg_0x2E, clk);
r_RECEIVE_DETECT reg_0x2F(ow_reg_0x2F, reset, enb_0x2F, iw_reg_0x2F, clk);
r_RECEIVE_BYTE_COUNT reg_0x30(ow_reg_0x30, reset, enb_0x30, iw_reg_0x30, clk);
r_RX_BUF_FRAME_TYPE reg_0x31(ow_reg_0x31, reset, enb_0x31, iw_reg_0x31, clk);
r_RX_BUF_HEADER_BYTE_0 reg_0x32(ow_reg_0x32, reset, enb_0x32, iw_reg_0x32, clk);
r_RX_BUF_HEADER_BYTE_1 reg_0x33(ow_reg_0x33, reset, enb_0x33, iw_reg_0x33, clk);
r_RX_BUF_OBJ1_BYTE_0 reg_0x34(ow_reg_0x34, reset, enb_0x34, iw_reg_0x34, clk);
r_RX_BUF_OBJ1_BYTE_1 reg_0x35(ow_reg_0x35, reset, enb_0x35, iw_reg_0x35, clk);
r_RX_BUF_OBJ1_BYTE_2 reg_0x36(ow_reg_0x36, reset, enb_0x36, iw_reg_0x36, clk);
r_RX_BUF_OBJ1_BYTE_3 reg_0x37(ow_reg_0x37, reset, enb_0x37, iw_reg_0x37, clk);
r_RX_BUF_OBJ2_BYTE_0 reg_0x38(ow_reg_0x38, reset, enb_0x38, iw_reg_0x38, clk);
r_RX_BUF_OBJ2_BYTE_1 reg_0x39(ow_reg_0x39, reset, enb_0x39, iw_reg_0x39, clk);
r_RX_BUF_OBJ2_BYTE_2 reg_0x3A(ow_reg_0x3A, reset, enb_0x3A, iw_reg_0x3A, clk);
r_RX_BUF_OBJ2_BYTE_3 reg_0x3B(ow_reg_0x3B, reset, enb_0x3B, iw_reg_0x3B, clk);
r_RX_BUF_OBJ3_BYTE_0 reg_0x3C(ow_reg_0x3C, reset, enb_0x3C, iw_reg_0x3C, clk);
r_RX_BUF_OBJ3_BYTE_1 reg_0x3D(ow_reg_0x3D, reset, enb_0x3D, iw_reg_0x3D, clk);
r_RX_BUF_OBJ3_BYTE_2 reg_0x3E(ow_reg_0x3E, reset, enb_0x3E, iw_reg_0x3E, clk);
r_RX_BUF_OBJ3_BYTE_3 reg_0x3F(ow_reg_0x3F, reset, enb_0x3F, iw_reg_0x3F, clk);
r_RX_BUF_OBJ4_BYTE_0 reg_0x40(ow_reg_0x40, reset, enb_0x40, iw_reg_0x40, clk);
r_RX_BUF_OBJ4_BYTE_1 reg_0x41(ow_reg_0x41, reset, enb_0x41, iw_reg_0x41, clk);
r_RX_BUF_OBJ4_BYTE_2 reg_0x42(ow_reg_0x42, reset, enb_0x42, iw_reg_0x42, clk);
r_RX_BUF_OBJ4_BYTE_3 reg_0x43(ow_reg_0x43, reset, enb_0x43, iw_reg_0x43, clk);
r_RX_BUF_OBJ5_BYTE_0 reg_0x44(ow_reg_0x44, reset, enb_0x44, iw_reg_0x44, clk);
r_RX_BUF_OBJ5_BYTE_1 reg_0x45(ow_reg_0x45, reset, enb_0x45, iw_reg_0x45, clk);
r_RX_BUF_OBJ5_BYTE_2 reg_0x46(ow_reg_0x46, reset, enb_0x46, iw_reg_0x46, clk);
r_RX_BUF_OBJ5_BYTE_3 reg_0x47(ow_reg_0x47, reset, enb_0x47, iw_reg_0x47, clk);
r_RX_BUF_OBJ6_BYTE_0 reg_0x48(ow_reg_0x48, reset, enb_0x48, iw_reg_0x48, clk);
r_RX_BUF_OBJ6_BYTE_1 reg_0x49(ow_reg_0x49, reset, enb_0x49, iw_reg_0x49, clk);
r_RX_BUF_OBJ6_BYTE_2 reg_0x4A(ow_reg_0x4A, reset, enb_0x4A, iw_reg_0x4A, clk);
r_RX_BUF_OBJ6_BYTE_3 reg_0x4B(ow_reg_0x4B, reset, enb_0x4B, iw_reg_0x4B, clk);
r_RX_BUF_OBJ7_BYTE_0 reg_0x4C(ow_reg_0x4C, reset, enb_0x4C, iw_reg_0x4C, clk);
r_RX_BUF_OBJ7_BYTE_1 reg_0x4D(ow_reg_0x4D, reset, enb_0x4D, iw_reg_0x4D, clk);
r_RX_BUF_OBJ7_BYTE_2 reg_0x4E(ow_reg_0x4E, reset, enb_0x4E, iw_reg_0x4E, clk);
r_RX_BUF_OBJ7_BYTE_3 reg_0x4F(ow_reg_0x4F, reset, enb_0x4F, iw_reg_0x4F, clk);
r_TRANSMIT reg_0x50(ow_reg_0x50, reset, enb_0x50, iw_reg_0x50, clk);
r_TRANSMIT_BYTE_COUNT reg_0x51(ow_reg_0x51, reset, enb_0x51, iw_reg_0x51, clk);
r_TX_BUF_HEADER_BYTE_0 reg_0x52(ow_reg_0x52, reset, enb_0x52, iw_reg_0x52, clk);
r_TX_BUF_HEADER_BYTE_1 reg_0x53(ow_reg_0x53, reset, enb_0x53, iw_reg_0x53, clk);
r_TX_BUF_OBJ1_BYTE_0 reg_0x54(ow_reg_0x54, reset, enb_0x54, iw_reg_0x54, clk);
r_TX_BUF_OBJ1_BYTE_1 reg_0x55(ow_reg_0x55, reset, enb_0x55, iw_reg_0x55, clk);
r_TX_BUF_OBJ1_BYTE_2 reg_0x56(ow_reg_0x56, reset, enb_0x56, iw_reg_0x56, clk);
r_TX_BUF_OBJ1_BYTE_3 reg_0x57(ow_reg_0x57, reset, enb_0x57, iw_reg_0x57, clk);
r_TX_BUF_OBJ2_BYTE_0 reg_0x58(ow_reg_0x58, reset, enb_0x58, iw_reg_0x58, clk);
r_TX_BUF_OBJ2_BYTE_1 reg_0x59(ow_reg_0x59, reset, enb_0x59, iw_reg_0x59, clk);
r_TX_BUF_OBJ2_BYTE_2 reg_0x5A(ow_reg_0x5A, reset, enb_0x5A, iw_reg_0x5A, clk);
r_TX_BUF_OBJ2_BYTE_3 reg_0x5B(ow_reg_0x5B, reset, enb_0x5B, iw_reg_0x5B, clk);
r_TX_BUF_OBJ3_BYTE_0 reg_0x5C(ow_reg_0x5C, reset, enb_0x5C, iw_reg_0x5C, clk);
r_TX_BUF_OBJ3_BYTE_1 reg_0x5D(ow_reg_0x5D, reset, enb_0x5D, iw_reg_0x5D, clk);
r_TX_BUF_OBJ3_BYTE_2 reg_0x5E(ow_reg_0x5E, reset, enb_0x5E, iw_reg_0x5E, clk);
r_TX_BUF_OBJ3_BYTE_3 reg_0x5F(ow_reg_0x5F, reset, enb_0x5F, iw_reg_0x5F, clk);
r_TX_BUF_OBJ4_BYTE_0 reg_0x60(ow_reg_0x60, reset, enb_0x60, iw_reg_0x60, clk);
r_TX_BUF_OBJ4_BYTE_1 reg_0x61(ow_reg_0x61, reset, enb_0x61, iw_reg_0x61, clk);
r_TX_BUF_OBJ4_BYTE_2 reg_0x62(ow_reg_0x62, reset, enb_0x62, iw_reg_0x62, clk);
r_TX_BUF_OBJ4_BYTE_3 reg_0x63(ow_reg_0x63, reset, enb_0x63, iw_reg_0x63, clk);
r_TX_BUF_OBJ5_BYTE_0 reg_0x64(ow_reg_0x64, reset, enb_0x64, iw_reg_0x64, clk);
r_TX_BUF_OBJ5_BYTE_1 reg_0x65(ow_reg_0x65, reset, enb_0x65, iw_reg_0x65, clk);
r_TX_BUF_OBJ5_BYTE_2 reg_0x66(ow_reg_0x66, reset, enb_0x66, iw_reg_0x66, clk);
r_TX_BUF_OBJ5_BYTE_3 reg_0x67(ow_reg_0x67, reset, enb_0x67, iw_reg_0x67, clk);
r_TX_BUF_OBJ6_BYTE_0 reg_0x68(ow_reg_0x68, reset, enb_0x68, iw_reg_0x68, clk);
r_TX_BUF_OBJ6_BYTE_1 reg_0x69(ow_reg_0x69, reset, enb_0x69, iw_reg_0x69, clk);
r_TX_BUF_OBJ6_BYTE_2 reg_0x6A(ow_reg_0x6A, reset, enb_0x6A, iw_reg_0x6A, clk);
r_TX_BUF_OBJ6_BYTE_3 reg_0x6B(ow_reg_0x6B, reset, enb_0x6B, iw_reg_0x6B, clk);
r_TX_BUF_OBJ7_BYTE_0 reg_0x6C(ow_reg_0x6C, reset, enb_0x6C, iw_reg_0x6C, clk);
r_TX_BUF_OBJ7_BYTE_1 reg_0x6D(ow_reg_0x6D, reset, enb_0x6D, iw_reg_0x6D, clk);
r_TX_BUF_OBJ7_BYTE_2 reg_0x6E(ow_reg_0x6E, reset, enb_0x6E, iw_reg_0x6E, clk);
r_TX_BUF_OBJ7_BYTE_3 reg_0x6F(ow_reg_0x6F, reset, enb_0x6F, iw_reg_0x6F, clk);
assign ow_od_transmit=ow_reg_0x50;
assign ow_od_TX_BUF_HEADER_BYTE_1=ow_reg_0x53;
assign ow_od_RX_BUF_HEADER_BYTE_1=ow_reg_0x33;
assign ow_od_RX_BUF_FRAME_TYPE=ow_reg_0x31;
REG_OUT_INTERFACE rout_int0(ow_od_0, r_address_0, ow_reg_0x00, ow_reg_0x01, ow_reg_0x02, ow_reg_0x03, ow_reg_0x04, ow_reg_0x05, ow_reg_0x06, ow_reg_0x07, ow_reg_0x08, ow_reg_0x09, ow_reg_0x0A, ow_reg_0x0B, ow_reg_0x10, ow_reg_0x11, ow_reg_0x12, ow_reg_0x13, ow_reg_0x14, ow_reg_0x15, ow_reg_0x18, ow_reg_0x19, ow_reg_0x1A, ow_reg_0x1B, ow_reg_0x1C, ow_reg_0x1D, ow_reg_0x1E, ow_reg_0x1F, ow_reg_0x23, ow_reg_0x24, ow_reg_0x25, ow_reg_0x26, ow_reg_0x27, ow_reg_0x28, ow_reg_0x29, ow_reg_0x2E, ow_reg_0x2F, ow_reg_0x30, ow_reg_0x31, ow_reg_0x32, ow_reg_0x33, ow_reg_0x34, ow_reg_0x35, ow_reg_0x36, ow_reg_0x37, ow_reg_0x38, ow_reg_0x39, ow_reg_0x3A, ow_reg_0x3B, ow_reg_0x3C, ow_reg_0x3D, ow_reg_0x3E, ow_reg_0x3F, ow_reg_0x40, ow_reg_0x41, ow_reg_0x42, ow_reg_0x43, ow_reg_0x44, ow_reg_0x45, ow_reg_0x46, ow_reg_0x47, ow_reg_0x48, ow_reg_0x49, ow_reg_0x4A, ow_reg_0x4B, ow_reg_0x4C, ow_reg_0x4D, ow_reg_0x4E, ow_reg_0x4F, ow_reg_0x50, ow_reg_0x51, ow_reg_0x52, ow_reg_0x53, ow_reg_0x54, ow_reg_0x55, ow_reg_0x56, ow_reg_0x57, ow_reg_0x58, ow_reg_0x59, ow_reg_0x5A, ow_reg_0x5B, ow_reg_0x5C, ow_reg_0x5D, ow_reg_0x5E, ow_reg_0x5F, ow_reg_0x60, ow_reg_0x61, ow_reg_0x62, ow_reg_0x63, ow_reg_0x64, ow_reg_0x65, ow_reg_0x66, ow_reg_0x67, ow_reg_0x68, ow_reg_0x69, ow_reg_0x6A, ow_reg_0x6B, ow_reg_0x6C, ow_reg_0x6D, ow_reg_0x6E, ow_reg_0x6F);
REG_OUT_INTERFACE rout_int1(ow_od_1, r_address_1, ow_reg_0x00, ow_reg_0x01, ow_reg_0x02, ow_reg_0x03, ow_reg_0x04, ow_reg_0x05, ow_reg_0x06, ow_reg_0x07, ow_reg_0x08, ow_reg_0x09, ow_reg_0x0A, ow_reg_0x0B, ow_reg_0x10, ow_reg_0x11, ow_reg_0x12, ow_reg_0x13, ow_reg_0x14, ow_reg_0x15, ow_reg_0x18, ow_reg_0x19, ow_reg_0x1A, ow_reg_0x1B, ow_reg_0x1C, ow_reg_0x1D, ow_reg_0x1E, ow_reg_0x1F, ow_reg_0x23, ow_reg_0x24, ow_reg_0x25, ow_reg_0x26, ow_reg_0x27, ow_reg_0x28, ow_reg_0x29, ow_reg_0x2E, ow_reg_0x2F, ow_reg_0x30, ow_reg_0x31, ow_reg_0x32, ow_reg_0x33, ow_reg_0x34, ow_reg_0x35, ow_reg_0x36, ow_reg_0x37, ow_reg_0x38, ow_reg_0x39, ow_reg_0x3A, ow_reg_0x3B, ow_reg_0x3C, ow_reg_0x3D, ow_reg_0x3E, ow_reg_0x3F, ow_reg_0x40, ow_reg_0x41, ow_reg_0x42, ow_reg_0x43, ow_reg_0x44, ow_reg_0x45, ow_reg_0x46, ow_reg_0x47, ow_reg_0x48, ow_reg_0x49, ow_reg_0x4A, ow_reg_0x4B, ow_reg_0x4C, ow_reg_0x4D, ow_reg_0x4E, ow_reg_0x4F, ow_reg_0x50, ow_reg_0x51, ow_reg_0x52, ow_reg_0x53, ow_reg_0x54, ow_reg_0x55, ow_reg_0x56, ow_reg_0x57, ow_reg_0x58, ow_reg_0x59, ow_reg_0x5A, ow_reg_0x5B, ow_reg_0x5C, ow_reg_0x5D, ow_reg_0x5E, ow_reg_0x5F, ow_reg_0x60, ow_reg_0x61, ow_reg_0x62, ow_reg_0x63, ow_reg_0x64, ow_reg_0x65, ow_reg_0x66, ow_reg_0x67, ow_reg_0x68, ow_reg_0x69, ow_reg_0x6A, ow_reg_0x6B, ow_reg_0x6C, ow_reg_0x6D, ow_reg_0x6E, ow_reg_0x6F);
REG_OUT_INTERFACE rout_int2(ow_od_2, r_address_2, ow_reg_0x00, ow_reg_0x01, ow_reg_0x02, ow_reg_0x03, ow_reg_0x04, ow_reg_0x05, ow_reg_0x06, ow_reg_0x07, ow_reg_0x08, ow_reg_0x09, ow_reg_0x0A, ow_reg_0x0B, ow_reg_0x10, ow_reg_0x11, ow_reg_0x12, ow_reg_0x13, ow_reg_0x14, ow_reg_0x15, ow_reg_0x18, ow_reg_0x19, ow_reg_0x1A, ow_reg_0x1B, ow_reg_0x1C, ow_reg_0x1D, ow_reg_0x1E, ow_reg_0x1F, ow_reg_0x23, ow_reg_0x24, ow_reg_0x25, ow_reg_0x26, ow_reg_0x27, ow_reg_0x28, ow_reg_0x29, ow_reg_0x2E, ow_reg_0x2F, ow_reg_0x30, ow_reg_0x31, ow_reg_0x32, ow_reg_0x33, ow_reg_0x34, ow_reg_0x35, ow_reg_0x36, ow_reg_0x37, ow_reg_0x38, ow_reg_0x39, ow_reg_0x3A, ow_reg_0x3B, ow_reg_0x3C, ow_reg_0x3D, ow_reg_0x3E, ow_reg_0x3F, ow_reg_0x40, ow_reg_0x41, ow_reg_0x42, ow_reg_0x43, ow_reg_0x44, ow_reg_0x45, ow_reg_0x46, ow_reg_0x47, ow_reg_0x48, ow_reg_0x49, ow_reg_0x4A, ow_reg_0x4B, ow_reg_0x4C, ow_reg_0x4D, ow_reg_0x4E, ow_reg_0x4F, ow_reg_0x50, ow_reg_0x51, ow_reg_0x52, ow_reg_0x53, ow_reg_0x54, ow_reg_0x55, ow_reg_0x56, ow_reg_0x57, ow_reg_0x58, ow_reg_0x59, ow_reg_0x5A, ow_reg_0x5B, ow_reg_0x5C, ow_reg_0x5D, ow_reg_0x5E, ow_reg_0x5F, ow_reg_0x60, ow_reg_0x61, ow_reg_0x62, ow_reg_0x63, ow_reg_0x64, ow_reg_0x65, ow_reg_0x66, ow_reg_0x67, ow_reg_0x68, ow_reg_0x69, ow_reg_0x6A, ow_reg_0x6B, ow_reg_0x6C, ow_reg_0x6D, ow_reg_0x6E, ow_reg_0x6F);
REG_IN_INTERFACE rin_int0(ow_i0_id_0x10, ow_i0_id_0x11, ow_i0_id_0x12, ow_i0_id_0x13, ow_i0_id_0x14, ow_i0_id_0x15, ow_i0_id_0x18, ow_i0_id_0x19, ow_i0_id_0x1A, ow_i0_id_0x1B, ow_i0_id_0x1C, ow_i0_id_0x1D, ow_i0_id_0x1E, ow_i0_id_0x1F, ow_i0_id_0x23, ow_i0_id_0x24, ow_i0_id_0x25, ow_i0_id_0x26, ow_i0_id_0x27, ow_i0_id_0x28, ow_i0_id_0x29, ow_i0_id_0x2E, ow_i0_id_0x2F, ow_i0_id_0x30, ow_i0_id_0x31, ow_i0_id_0x32, ow_i0_id_0x33, ow_i0_id_0x34, ow_i0_id_0x35, ow_i0_id_0x36, ow_i0_id_0x37, ow_i0_id_0x38, ow_i0_id_0x39, ow_i0_id_0x3A, ow_i0_id_0x3B, ow_i0_id_0x3C, ow_i0_id_0x3D, ow_i0_id_0x3E, ow_i0_id_0x3F, ow_i0_id_0x40, ow_i0_id_0x41, ow_i0_id_0x42, ow_i0_id_0x43, ow_i0_id_0x44, ow_i0_id_0x45, ow_i0_id_0x46, ow_i0_id_0x47, ow_i0_id_0x48, ow_i0_id_0x49, ow_i0_id_0x4A, ow_i0_id_0x4B, ow_i0_id_0x4C, ow_i0_id_0x4D, ow_i0_id_0x4E, ow_i0_id_0x4F, ow_i0_id_0x50, ow_i0_id_0x51, ow_i0_id_0x52, ow_i0_id_0x53, ow_i0_id_0x54, ow_i0_id_0x55, ow_i0_id_0x56, ow_i0_id_0x57, ow_i0_id_0x58, ow_i0_id_0x59, ow_i0_id_0x5A, ow_i0_id_0x5B, ow_i0_id_0x5C, ow_i0_id_0x5D, ow_i0_id_0x5E, ow_i0_id_0x5F, ow_i0_id_0x60, ow_i0_id_0x61, ow_i0_id_0x62, ow_i0_id_0x63, ow_i0_id_0x64, ow_i0_id_0x65, ow_i0_id_0x66, ow_i0_id_0x67, ow_i0_id_0x68, ow_i0_id_0x69, ow_i0_id_0x6A, ow_i0_id_0x6B, ow_i0_id_0x6C, ow_i0_id_0x6D, ow_i0_id_0x6E, ow_i0_id_0x6F, ow_i0_enb_0x10, ow_i0_enb_0x11, ow_i0_enb_0x12, ow_i0_enb_0x13, ow_i0_enb_0x14, ow_i0_enb_0x15, ow_i0_enb_0x18, ow_i0_enb_0x19, ow_i0_enb_0x1A, ow_i0_enb_0x1B, ow_i0_enb_0x1C, ow_i0_enb_0x1D, ow_i0_enb_0x1E, ow_i0_enb_0x1F, ow_i0_enb_0x23, ow_i0_enb_0x24, ow_i0_enb_0x25, ow_i0_enb_0x26, ow_i0_enb_0x27, ow_i0_enb_0x28, ow_i0_enb_0x29, ow_i0_enb_0x2E, ow_i0_enb_0x2F, ow_i0_enb_0x30, ow_i0_enb_0x31, ow_i0_enb_0x32, ow_i0_enb_0x33, ow_i0_enb_0x34, ow_i0_enb_0x35, ow_i0_enb_0x36, ow_i0_enb_0x37, ow_i0_enb_0x38, ow_i0_enb_0x39, ow_i0_enb_0x3A, ow_i0_enb_0x3B, ow_i0_enb_0x3C, ow_i0_enb_0x3D, ow_i0_enb_0x3E, ow_i0_enb_0x3F, ow_i0_enb_0x40, ow_i0_enb_0x41, ow_i0_enb_0x42, ow_i0_enb_0x43, ow_i0_enb_0x44, ow_i0_enb_0x45, ow_i0_enb_0x46, ow_i0_enb_0x47, ow_i0_enb_0x48, ow_i0_enb_0x49, ow_i0_enb_0x4A, ow_i0_enb_0x4B, ow_i0_enb_0x4C, ow_i0_enb_0x4D, ow_i0_enb_0x4E, ow_i0_enb_0x4F, ow_i0_enb_0x50, ow_i0_enb_0x51, ow_i0_enb_0x52, ow_i0_enb_0x53, ow_i0_enb_0x54, ow_i0_enb_0x55, ow_i0_enb_0x56, ow_i0_enb_0x57, ow_i0_enb_0x58, ow_i0_enb_0x59, ow_i0_enb_0x5A, ow_i0_enb_0x5B, ow_i0_enb_0x5C, ow_i0_enb_0x5D, ow_i0_enb_0x5E, ow_i0_enb_0x5F, ow_i0_enb_0x60, ow_i0_enb_0x61, ow_i0_enb_0x62, ow_i0_enb_0x63, ow_i0_enb_0x64, ow_i0_enb_0x65, ow_i0_enb_0x66, ow_i0_enb_0x67, ow_i0_enb_0x68, ow_i0_enb_0x69, ow_i0_enb_0x6A, ow_i0_enb_0x6B, ow_i0_enb_0x6C, ow_i0_enb_0x6D, ow_i0_enb_0x6E, ow_i0_enb_0x6F, r_address_0, iw_id_0, iw_enb_0);
REG_IN_INTERFACE rin_int1(ow_i1_id_0x10, ow_i1_id_0x11, ow_i1_id_0x12, ow_i1_id_0x13, ow_i1_id_0x14, ow_i1_id_0x15, ow_i1_id_0x18, ow_i1_id_0x19, ow_i1_id_0x1A, ow_i1_id_0x1B, ow_i1_id_0x1C, ow_i1_id_0x1D, ow_i1_id_0x1E, ow_i1_id_0x1F, ow_i1_id_0x23, ow_i1_id_0x24, ow_i1_id_0x25, ow_i1_id_0x26, ow_i1_id_0x27, ow_i1_id_0x28, ow_i1_id_0x29, ow_i1_id_0x2E, ow_i1_id_0x2F, ow_i1_id_0x30, ow_i1_id_0x31, ow_i1_id_0x32, ow_i1_id_0x33, ow_i1_id_0x34, ow_i1_id_0x35, ow_i1_id_0x36, ow_i1_id_0x37, ow_i1_id_0x38, ow_i1_id_0x39, ow_i1_id_0x3A, ow_i1_id_0x3B, ow_i1_id_0x3C, ow_i1_id_0x3D, ow_i1_id_0x3E, ow_i1_id_0x3F, ow_i1_id_0x40, ow_i1_id_0x41, ow_i1_id_0x42, ow_i1_id_0x43, ow_i1_id_0x44, ow_i1_id_0x45, ow_i1_id_0x46, ow_i1_id_0x47, ow_i1_id_0x48, ow_i1_id_0x49, ow_i1_id_0x4A, ow_i1_id_0x4B, ow_i1_id_0x4C, ow_i1_id_0x4D, ow_i1_id_0x4E, ow_i1_id_0x4F, ow_i1_id_0x50, ow_i1_id_0x51, ow_i1_id_0x52, ow_i1_id_0x53, ow_i1_id_0x54, ow_i1_id_0x55, ow_i1_id_0x56, ow_i1_id_0x57, ow_i1_id_0x58, ow_i1_id_0x59, ow_i1_id_0x5A, ow_i1_id_0x5B, ow_i1_id_0x5C, ow_i1_id_0x5D, ow_i1_id_0x5E, ow_i1_id_0x5F, ow_i1_id_0x60, ow_i1_id_0x61, ow_i1_id_0x62, ow_i1_id_0x63, ow_i1_id_0x64, ow_i1_id_0x65, ow_i1_id_0x66, ow_i1_id_0x67, ow_i1_id_0x68, ow_i1_id_0x69, ow_i1_id_0x6A, ow_i1_id_0x6B, ow_i1_id_0x6C, ow_i1_id_0x6D, ow_i1_id_0x6E, ow_i1_id_0x6F, ow_i1_enb_0x10, ow_i1_enb_0x11, ow_i1_enb_0x12, ow_i1_enb_0x13, ow_i1_enb_0x14, ow_i1_enb_0x15, ow_i1_enb_0x18, ow_i1_enb_0x19, ow_i1_enb_0x1A, ow_i1_enb_0x1B, ow_i1_enb_0x1C, ow_i1_enb_0x1D, ow_i1_enb_0x1E, ow_i1_enb_0x1F, ow_i1_enb_0x23, ow_i1_enb_0x24, ow_i1_enb_0x25, ow_i1_enb_0x26, ow_i1_enb_0x27, ow_i1_enb_0x28, ow_i1_enb_0x29, ow_i1_enb_0x2E, ow_i1_enb_0x2F, ow_i1_enb_0x30, ow_i1_enb_0x31, ow_i1_enb_0x32, ow_i1_enb_0x33, ow_i1_enb_0x34, ow_i1_enb_0x35, ow_i1_enb_0x36, ow_i1_enb_0x37, ow_i1_enb_0x38, ow_i1_enb_0x39, ow_i1_enb_0x3A, ow_i1_enb_0x3B, ow_i1_enb_0x3C, ow_i1_enb_0x3D, ow_i1_enb_0x3E, ow_i1_enb_0x3F, ow_i1_enb_0x40, ow_i1_enb_0x41, ow_i1_enb_0x42, ow_i1_enb_0x43, ow_i1_enb_0x44, ow_i1_enb_0x45, ow_i1_enb_0x46, ow_i1_enb_0x47, ow_i1_enb_0x48, ow_i1_enb_0x49, ow_i1_enb_0x4A, ow_i1_enb_0x4B, ow_i1_enb_0x4C, ow_i1_enb_0x4D, ow_i1_enb_0x4E, ow_i1_enb_0x4F, ow_i1_enb_0x50, ow_i1_enb_0x51, ow_i1_enb_0x52, ow_i1_enb_0x53, ow_i1_enb_0x54, ow_i1_enb_0x55, ow_i1_enb_0x56, ow_i1_enb_0x57, ow_i1_enb_0x58, ow_i1_enb_0x59, ow_i1_enb_0x5A, ow_i1_enb_0x5B, ow_i1_enb_0x5C, ow_i1_enb_0x5D, ow_i1_enb_0x5E, ow_i1_enb_0x5F, ow_i1_enb_0x60, ow_i1_enb_0x61, ow_i1_enb_0x62, ow_i1_enb_0x63, ow_i1_enb_0x64, ow_i1_enb_0x65, ow_i1_enb_0x66, ow_i1_enb_0x67, ow_i1_enb_0x68, ow_i1_enb_0x69, ow_i1_enb_0x6A, ow_i1_enb_0x6B, ow_i1_enb_0x6C, ow_i1_enb_0x6D, ow_i1_enb_0x6E, ow_i1_enb_0x6F, r_address_1, iw_id_1, iw_enb_1);
REG_IN_INTERFACE rin_int2(ow_i2_id_0x10, ow_i2_id_0x11, ow_i2_id_0x12, ow_i2_id_0x13, ow_i2_id_0x14, ow_i2_id_0x15, ow_i2_id_0x18, ow_i2_id_0x19, ow_i2_id_0x1A, ow_i2_id_0x1B, ow_i2_id_0x1C, ow_i2_id_0x1D, ow_i2_id_0x1E, ow_i2_id_0x1F, ow_i2_id_0x23, ow_i2_id_0x24, ow_i2_id_0x25, ow_i2_id_0x26, ow_i2_id_0x27, ow_i2_id_0x28, ow_i2_id_0x29, ow_i2_id_0x2E, ow_i2_id_0x2F, ow_i2_id_0x30, ow_i2_id_0x31, ow_i2_id_0x32, ow_i2_id_0x33, ow_i2_id_0x34, ow_i2_id_0x35, ow_i2_id_0x36, ow_i2_id_0x37, ow_i2_id_0x38, ow_i2_id_0x39, ow_i2_id_0x3A, ow_i2_id_0x3B, ow_i2_id_0x3C, ow_i2_id_0x3D, ow_i2_id_0x3E, ow_i2_id_0x3F, ow_i2_id_0x40, ow_i2_id_0x41, ow_i2_id_0x42, ow_i2_id_0x43, ow_i2_id_0x44, ow_i2_id_0x45, ow_i2_id_0x46, ow_i2_id_0x47, ow_i2_id_0x48, ow_i2_id_0x49, ow_i2_id_0x4A, ow_i2_id_0x4B, ow_i2_id_0x4C, ow_i2_id_0x4D, ow_i2_id_0x4E, ow_i2_id_0x4F, ow_i2_id_0x50, ow_i2_id_0x51, ow_i2_id_0x52, ow_i2_id_0x53, ow_i2_id_0x54, ow_i2_id_0x55, ow_i2_id_0x56, ow_i2_id_0x57, ow_i2_id_0x58, ow_i2_id_0x59, ow_i2_id_0x5A, ow_i2_id_0x5B, ow_i2_id_0x5C, ow_i2_id_0x5D, ow_i2_id_0x5E, ow_i2_id_0x5F, ow_i2_id_0x60, ow_i2_id_0x61, ow_i2_id_0x62, ow_i2_id_0x63, ow_i2_id_0x64, ow_i2_id_0x65, ow_i2_id_0x66, ow_i2_id_0x67, ow_i2_id_0x68, ow_i2_id_0x69, ow_i2_id_0x6A, ow_i2_id_0x6B, ow_i2_id_0x6C, ow_i2_id_0x6D, ow_i2_id_0x6E, ow_i2_id_0x6F, ow_i2_enb_0x10, ow_i2_enb_0x11, ow_i2_enb_0x12, ow_i2_enb_0x13, ow_i2_enb_0x14, ow_i2_enb_0x15, ow_i2_enb_0x18, ow_i2_enb_0x19, ow_i2_enb_0x1A, ow_i2_enb_0x1B, ow_i2_enb_0x1C, ow_i2_enb_0x1D, ow_i2_enb_0x1E, ow_i2_enb_0x1F, ow_i2_enb_0x23, ow_i2_enb_0x24, ow_i2_enb_0x25, ow_i2_enb_0x26, ow_i2_enb_0x27, ow_i2_enb_0x28, ow_i2_enb_0x29, ow_i2_enb_0x2E, ow_i2_enb_0x2F, ow_i2_enb_0x30, ow_i2_enb_0x31, ow_i2_enb_0x32, ow_i2_enb_0x33, ow_i2_enb_0x34, ow_i2_enb_0x35, ow_i2_enb_0x36, ow_i2_enb_0x37, ow_i2_enb_0x38, ow_i2_enb_0x39, ow_i2_enb_0x3A, ow_i2_enb_0x3B, ow_i2_enb_0x3C, ow_i2_enb_0x3D, ow_i2_enb_0x3E, ow_i2_enb_0x3F, ow_i2_enb_0x40, ow_i2_enb_0x41, ow_i2_enb_0x42, ow_i2_enb_0x43, ow_i2_enb_0x44, ow_i2_enb_0x45, ow_i2_enb_0x46, ow_i2_enb_0x47, ow_i2_enb_0x48, ow_i2_enb_0x49, ow_i2_enb_0x4A, ow_i2_enb_0x4B, ow_i2_enb_0x4C, ow_i2_enb_0x4D, ow_i2_enb_0x4E, ow_i2_enb_0x4F, ow_i2_enb_0x50, ow_i2_enb_0x51, ow_i2_enb_0x52, ow_i2_enb_0x53, ow_i2_enb_0x54, ow_i2_enb_0x55, ow_i2_enb_0x56, ow_i2_enb_0x57, ow_i2_enb_0x58, ow_i2_enb_0x59, ow_i2_enb_0x5A, ow_i2_enb_0x5B, ow_i2_enb_0x5C, ow_i2_enb_0x5D, ow_i2_enb_0x5E, ow_i2_enb_0x5F, ow_i2_enb_0x60, ow_i2_enb_0x61, ow_i2_enb_0x62, ow_i2_enb_0x63, ow_i2_enb_0x64, ow_i2_enb_0x65, ow_i2_enb_0x66, ow_i2_enb_0x67, ow_i2_enb_0x68, ow_i2_enb_0x69, ow_i2_enb_0x6A, ow_i2_enb_0x6B, ow_i2_enb_0x6C, ow_i2_enb_0x6D, ow_i2_enb_0x6E, ow_i2_enb_0x6F, r_address_2, iw_id_2, iw_enb_2);
assign iw_reg_0x10=ow_i0_id_0x10+ow_i1_id_0x10+ow_i2_id_0x10;
assign enb_0x10=ow_i0_enb_0x10+ow_i1_enb_0x10+ow_i2_enb_0x10;
assign iw_reg_0x11=ow_i0_id_0x11+ow_i1_id_0x11+ow_i2_id_0x11;
assign enb_0x11=ow_i0_enb_0x11+ow_i1_enb_0x11+ow_i2_enb_0x11;
assign iw_reg_0x12=ow_i0_id_0x12+ow_i1_id_0x12+ow_i2_id_0x12;
assign enb_0x12=ow_i0_enb_0x12+ow_i1_enb_0x12+ow_i2_enb_0x12;
assign iw_reg_0x13=ow_i0_id_0x13+ow_i1_id_0x13+ow_i2_id_0x13;
assign enb_0x13=ow_i0_enb_0x13+ow_i1_enb_0x13+ow_i2_enb_0x13;
assign iw_reg_0x14=ow_i0_id_0x14+ow_i1_id_0x14+ow_i2_id_0x14;
assign enb_0x14=ow_i0_enb_0x14+ow_i1_enb_0x14+ow_i2_enb_0x14;
assign iw_reg_0x15=ow_i0_id_0x15+ow_i1_id_0x15+ow_i2_id_0x15;
assign enb_0x15=ow_i0_enb_0x15+ow_i1_enb_0x15+ow_i2_enb_0x15;
assign iw_reg_0x18=ow_i0_id_0x18+ow_i1_id_0x18+ow_i2_id_0x18;
assign enb_0x18=ow_i0_enb_0x18+ow_i1_enb_0x18+ow_i2_enb_0x18;
assign iw_reg_0x19=ow_i0_id_0x19+ow_i1_id_0x19+ow_i2_id_0x19;
assign enb_0x19=ow_i0_enb_0x19+ow_i1_enb_0x19+ow_i2_enb_0x19;
assign iw_reg_0x1A=ow_i0_id_0x1A+ow_i1_id_0x1A+ow_i2_id_0x1A;
assign enb_0x1A=ow_i0_enb_0x1A+ow_i1_enb_0x1A+ow_i2_enb_0x1A;
assign iw_reg_0x1B=ow_i0_id_0x1B+ow_i1_id_0x1B+ow_i2_id_0x1B;
assign enb_0x1B=ow_i0_enb_0x1B+ow_i1_enb_0x1B+ow_i2_enb_0x1B;
assign iw_reg_0x1C=ow_i0_id_0x1C+ow_i1_id_0x1C+ow_i2_id_0x1C;
assign enb_0x1C=ow_i0_enb_0x1C+ow_i1_enb_0x1C+ow_i2_enb_0x1C;
assign iw_reg_0x1D=ow_i0_id_0x1D+ow_i1_id_0x1D+ow_i2_id_0x1D;
assign enb_0x1D=ow_i0_enb_0x1D+ow_i1_enb_0x1D+ow_i2_enb_0x1D;
assign iw_reg_0x1E=ow_i0_id_0x1E+ow_i1_id_0x1E+ow_i2_id_0x1E;
assign enb_0x1E=ow_i0_enb_0x1E+ow_i1_enb_0x1E+ow_i2_enb_0x1E;
assign iw_reg_0x1F=ow_i0_id_0x1F+ow_i1_id_0x1F+ow_i2_id_0x1F;
assign enb_0x1F=ow_i0_enb_0x1F+ow_i1_enb_0x1F+ow_i2_enb_0x1F;
assign iw_reg_0x23=ow_i0_id_0x23+ow_i1_id_0x23+ow_i2_id_0x23;
assign enb_0x23=ow_i0_enb_0x23+ow_i1_enb_0x23+ow_i2_enb_0x23;
assign iw_reg_0x24=ow_i0_id_0x24+ow_i1_id_0x24+ow_i2_id_0x24;
assign enb_0x24=ow_i0_enb_0x24+ow_i1_enb_0x24+ow_i2_enb_0x24;
assign iw_reg_0x25=ow_i0_id_0x25+ow_i1_id_0x25+ow_i2_id_0x25;
assign enb_0x25=ow_i0_enb_0x25+ow_i1_enb_0x25+ow_i2_enb_0x25;
assign iw_reg_0x26=ow_i0_id_0x26+ow_i1_id_0x26+ow_i2_id_0x26;
assign enb_0x26=ow_i0_enb_0x26+ow_i1_enb_0x26+ow_i2_enb_0x26;
assign iw_reg_0x27=ow_i0_id_0x27+ow_i1_id_0x27+ow_i2_id_0x27;
assign enb_0x27=ow_i0_enb_0x27+ow_i1_enb_0x27+ow_i2_enb_0x27;
assign iw_reg_0x28=ow_i0_id_0x28+ow_i1_id_0x28+ow_i2_id_0x28;
assign enb_0x28=ow_i0_enb_0x28+ow_i1_enb_0x28+ow_i2_enb_0x28;
assign iw_reg_0x29=ow_i0_id_0x29+ow_i1_id_0x29+ow_i2_id_0x29;
assign enb_0x29=ow_i0_enb_0x29+ow_i1_enb_0x29+ow_i2_enb_0x29;
assign iw_reg_0x2E=ow_i0_id_0x2E+ow_i1_id_0x2E+ow_i2_id_0x2E;
assign enb_0x2E=ow_i0_enb_0x2E+ow_i1_enb_0x2E+ow_i2_enb_0x2E;
assign iw_reg_0x2F=ow_i0_id_0x2F+ow_i1_id_0x2F+ow_i2_id_0x2F;
assign enb_0x2F=ow_i0_enb_0x2F+ow_i1_enb_0x2F+ow_i2_enb_0x2F;
assign iw_reg_0x30=ow_i0_id_0x30+ow_i1_id_0x30+ow_i2_id_0x30;
assign enb_0x30=ow_i0_enb_0x30+ow_i1_enb_0x30+ow_i2_enb_0x30;
assign iw_reg_0x31=ow_i0_id_0x31+ow_i1_id_0x31+ow_i2_id_0x31;
assign enb_0x31=ow_i0_enb_0x31+ow_i1_enb_0x31+ow_i2_enb_0x31;
assign iw_reg_0x32=ow_i0_id_0x32+ow_i1_id_0x32+ow_i2_id_0x32;
assign enb_0x32=ow_i0_enb_0x32+ow_i1_enb_0x32+ow_i2_enb_0x32;
assign iw_reg_0x33=ow_i0_id_0x33+ow_i1_id_0x33+ow_i2_id_0x33;
assign enb_0x33=ow_i0_enb_0x33+ow_i1_enb_0x33+ow_i2_enb_0x33;
assign iw_reg_0x34=ow_i0_id_0x34+ow_i1_id_0x34+ow_i2_id_0x34;
assign enb_0x34=ow_i0_enb_0x34+ow_i1_enb_0x34+ow_i2_enb_0x34;
assign iw_reg_0x35=ow_i0_id_0x35+ow_i1_id_0x35+ow_i2_id_0x35;
assign enb_0x35=ow_i0_enb_0x35+ow_i1_enb_0x35+ow_i2_enb_0x35;
assign iw_reg_0x36=ow_i0_id_0x36+ow_i1_id_0x36+ow_i2_id_0x36;
assign enb_0x36=ow_i0_enb_0x36+ow_i1_enb_0x36+ow_i2_enb_0x36;
assign iw_reg_0x37=ow_i0_id_0x37+ow_i1_id_0x37+ow_i2_id_0x37;
assign enb_0x37=ow_i0_enb_0x37+ow_i1_enb_0x37+ow_i2_enb_0x37;
assign iw_reg_0x38=ow_i0_id_0x38+ow_i1_id_0x38+ow_i2_id_0x38;
assign enb_0x38=ow_i0_enb_0x38+ow_i1_enb_0x38+ow_i2_enb_0x38;
assign iw_reg_0x39=ow_i0_id_0x39+ow_i1_id_0x39+ow_i2_id_0x39;
assign enb_0x39=ow_i0_enb_0x39+ow_i1_enb_0x39+ow_i2_enb_0x39;
assign iw_reg_0x3A=ow_i0_id_0x3A+ow_i1_id_0x3A+ow_i2_id_0x3A;
assign enb_0x3A=ow_i0_enb_0x3A+ow_i1_enb_0x3A+ow_i2_enb_0x3A;
assign iw_reg_0x3B=ow_i0_id_0x3B+ow_i1_id_0x3B+ow_i2_id_0x3B;
assign enb_0x3B=ow_i0_enb_0x3B+ow_i1_enb_0x3B+ow_i2_enb_0x3B;
assign iw_reg_0x3C=ow_i0_id_0x3C+ow_i1_id_0x3C+ow_i2_id_0x3C;
assign enb_0x3C=ow_i0_enb_0x3C+ow_i1_enb_0x3C+ow_i2_enb_0x3C;
assign iw_reg_0x3D=ow_i0_id_0x3D+ow_i1_id_0x3D+ow_i2_id_0x3D;
assign enb_0x3D=ow_i0_enb_0x3D+ow_i1_enb_0x3D+ow_i2_enb_0x3D;
assign iw_reg_0x3E=ow_i0_id_0x3E+ow_i1_id_0x3E+ow_i2_id_0x3E;
assign enb_0x3E=ow_i0_enb_0x3E+ow_i1_enb_0x3E+ow_i2_enb_0x3E;
assign iw_reg_0x3F=ow_i0_id_0x3F+ow_i1_id_0x3F+ow_i2_id_0x3F;
assign enb_0x3F=ow_i0_enb_0x3F+ow_i1_enb_0x3F+ow_i2_enb_0x3F;
assign iw_reg_0x40=ow_i0_id_0x40+ow_i1_id_0x40+ow_i2_id_0x40;
assign enb_0x40=ow_i0_enb_0x40+ow_i1_enb_0x40+ow_i2_enb_0x40;
assign iw_reg_0x41=ow_i0_id_0x41+ow_i1_id_0x41+ow_i2_id_0x41;
assign enb_0x41=ow_i0_enb_0x41+ow_i1_enb_0x41+ow_i2_enb_0x41;
assign iw_reg_0x42=ow_i0_id_0x42+ow_i1_id_0x42+ow_i2_id_0x42;
assign enb_0x42=ow_i0_enb_0x42+ow_i1_enb_0x42+ow_i2_enb_0x42;
assign iw_reg_0x43=ow_i0_id_0x43+ow_i1_id_0x43+ow_i2_id_0x43;
assign enb_0x43=ow_i0_enb_0x43+ow_i1_enb_0x43+ow_i2_enb_0x43;
assign iw_reg_0x44=ow_i0_id_0x44+ow_i1_id_0x44+ow_i2_id_0x44;
assign enb_0x44=ow_i0_enb_0x44+ow_i1_enb_0x44+ow_i2_enb_0x44;
assign iw_reg_0x45=ow_i0_id_0x45+ow_i1_id_0x45+ow_i2_id_0x45;
assign enb_0x45=ow_i0_enb_0x45+ow_i1_enb_0x45+ow_i2_enb_0x45;
assign iw_reg_0x46=ow_i0_id_0x46+ow_i1_id_0x46+ow_i2_id_0x46;
assign enb_0x46=ow_i0_enb_0x46+ow_i1_enb_0x46+ow_i2_enb_0x46;
assign iw_reg_0x47=ow_i0_id_0x47+ow_i1_id_0x47+ow_i2_id_0x47;
assign enb_0x47=ow_i0_enb_0x47+ow_i1_enb_0x47+ow_i2_enb_0x47;
assign iw_reg_0x48=ow_i0_id_0x48+ow_i1_id_0x48+ow_i2_id_0x48;
assign enb_0x48=ow_i0_enb_0x48+ow_i1_enb_0x48+ow_i2_enb_0x48;
assign iw_reg_0x49=ow_i0_id_0x49+ow_i1_id_0x49+ow_i2_id_0x49;
assign enb_0x49=ow_i0_enb_0x49+ow_i1_enb_0x49+ow_i2_enb_0x49;
assign iw_reg_0x4A=ow_i0_id_0x4A+ow_i1_id_0x4A+ow_i2_id_0x4A;
assign enb_0x4A=ow_i0_enb_0x4A+ow_i1_enb_0x4A+ow_i2_enb_0x4A;
assign iw_reg_0x4B=ow_i0_id_0x4B+ow_i1_id_0x4B+ow_i2_id_0x4B;
assign enb_0x4B=ow_i0_enb_0x4B+ow_i1_enb_0x4B+ow_i2_enb_0x4B;
assign iw_reg_0x4C=ow_i0_id_0x4C+ow_i1_id_0x4C+ow_i2_id_0x4C;
assign enb_0x4C=ow_i0_enb_0x4C+ow_i1_enb_0x4C+ow_i2_enb_0x4C;
assign iw_reg_0x4D=ow_i0_id_0x4D+ow_i1_id_0x4D+ow_i2_id_0x4D;
assign enb_0x4D=ow_i0_enb_0x4D+ow_i1_enb_0x4D+ow_i2_enb_0x4D;
assign iw_reg_0x4E=ow_i0_id_0x4E+ow_i1_id_0x4E+ow_i2_id_0x4E;
assign enb_0x4E=ow_i0_enb_0x4E+ow_i1_enb_0x4E+ow_i2_enb_0x4E;
assign iw_reg_0x4F=ow_i0_id_0x4F+ow_i1_id_0x4F+ow_i2_id_0x4F;
assign enb_0x4F=ow_i0_enb_0x4F+ow_i1_enb_0x4F+ow_i2_enb_0x4F;
assign iw_reg_0x50=ow_i0_id_0x50+ow_i1_id_0x50+ow_i2_id_0x50;
assign enb_0x50=ow_i0_enb_0x50+ow_i1_enb_0x50+ow_i2_enb_0x50;
assign iw_reg_0x51=ow_i0_id_0x51+ow_i1_id_0x51+ow_i2_id_0x51;
assign enb_0x51=ow_i0_enb_0x51+ow_i1_enb_0x51+ow_i2_enb_0x51;
assign iw_reg_0x52=ow_i0_id_0x52+ow_i1_id_0x52+ow_i2_id_0x52;
assign enb_0x52=ow_i0_enb_0x52+ow_i1_enb_0x52+ow_i2_enb_0x52;
assign iw_reg_0x53=ow_i0_id_0x53+ow_i1_id_0x53+ow_i2_id_0x53;
assign enb_0x53=ow_i0_enb_0x53+ow_i1_enb_0x53+ow_i2_enb_0x53;
assign iw_reg_0x54=ow_i0_id_0x54+ow_i1_id_0x54+ow_i2_id_0x54;
assign enb_0x54=ow_i0_enb_0x54+ow_i1_enb_0x54+ow_i2_enb_0x54;
assign iw_reg_0x55=ow_i0_id_0x55+ow_i1_id_0x55+ow_i2_id_0x55;
assign enb_0x55=ow_i0_enb_0x55+ow_i1_enb_0x55+ow_i2_enb_0x55;
assign iw_reg_0x56=ow_i0_id_0x56+ow_i1_id_0x56+ow_i2_id_0x56;
assign enb_0x56=ow_i0_enb_0x56+ow_i1_enb_0x56+ow_i2_enb_0x56;
assign iw_reg_0x57=ow_i0_id_0x57+ow_i1_id_0x57+ow_i2_id_0x57;
assign enb_0x57=ow_i0_enb_0x57+ow_i1_enb_0x57+ow_i2_enb_0x57;
assign iw_reg_0x58=ow_i0_id_0x58+ow_i1_id_0x58+ow_i2_id_0x58;
assign enb_0x58=ow_i0_enb_0x58+ow_i1_enb_0x58+ow_i2_enb_0x58;
assign iw_reg_0x59=ow_i0_id_0x59+ow_i1_id_0x59+ow_i2_id_0x59;
assign enb_0x59=ow_i0_enb_0x59+ow_i1_enb_0x59+ow_i2_enb_0x59;
assign iw_reg_0x5A=ow_i0_id_0x5A+ow_i1_id_0x5A+ow_i2_id_0x5A;
assign enb_0x5A=ow_i0_enb_0x5A+ow_i1_enb_0x5A+ow_i2_enb_0x5A;
assign iw_reg_0x5B=ow_i0_id_0x5B+ow_i1_id_0x5B+ow_i2_id_0x5B;
assign enb_0x5B=ow_i0_enb_0x5B+ow_i1_enb_0x5B+ow_i2_enb_0x5B;
assign iw_reg_0x5C=ow_i0_id_0x5C+ow_i1_id_0x5C+ow_i2_id_0x5C;
assign enb_0x5C=ow_i0_enb_0x5C+ow_i1_enb_0x5C+ow_i2_enb_0x5C;
assign iw_reg_0x5D=ow_i0_id_0x5D+ow_i1_id_0x5D+ow_i2_id_0x5D;
assign enb_0x5D=ow_i0_enb_0x5D+ow_i1_enb_0x5D+ow_i2_enb_0x5D;
assign iw_reg_0x5E=ow_i0_id_0x5E+ow_i1_id_0x5E+ow_i2_id_0x5E;
assign enb_0x5E=ow_i0_enb_0x5E+ow_i1_enb_0x5E+ow_i2_enb_0x5E;
assign iw_reg_0x5F=ow_i0_id_0x5F+ow_i1_id_0x5F+ow_i2_id_0x5F;
assign enb_0x5F=ow_i0_enb_0x5F+ow_i1_enb_0x5F+ow_i2_enb_0x5F;
assign iw_reg_0x60=ow_i0_id_0x60+ow_i1_id_0x60+ow_i2_id_0x60;
assign enb_0x60=ow_i0_enb_0x60+ow_i1_enb_0x60+ow_i2_enb_0x60;
assign iw_reg_0x61=ow_i0_id_0x61+ow_i1_id_0x61+ow_i2_id_0x61;
assign enb_0x61=ow_i0_enb_0x61+ow_i1_enb_0x61+ow_i2_enb_0x61;
assign iw_reg_0x62=ow_i0_id_0x62+ow_i1_id_0x62+ow_i2_id_0x62;
assign enb_0x62=ow_i0_enb_0x62+ow_i1_enb_0x62+ow_i2_enb_0x62;
assign iw_reg_0x63=ow_i0_id_0x63+ow_i1_id_0x63+ow_i2_id_0x63;
assign enb_0x63=ow_i0_enb_0x63+ow_i1_enb_0x63+ow_i2_enb_0x63;
assign iw_reg_0x64=ow_i0_id_0x64+ow_i1_id_0x64+ow_i2_id_0x64;
assign enb_0x64=ow_i0_enb_0x64+ow_i1_enb_0x64+ow_i2_enb_0x64;
assign iw_reg_0x65=ow_i0_id_0x65+ow_i1_id_0x65+ow_i2_id_0x65;
assign enb_0x65=ow_i0_enb_0x65+ow_i1_enb_0x65+ow_i2_enb_0x65;
assign iw_reg_0x66=ow_i0_id_0x66+ow_i1_id_0x66+ow_i2_id_0x66;
assign enb_0x66=ow_i0_enb_0x66+ow_i1_enb_0x66+ow_i2_enb_0x66;
assign iw_reg_0x67=ow_i0_id_0x67+ow_i1_id_0x67+ow_i2_id_0x67;
assign enb_0x67=ow_i0_enb_0x67+ow_i1_enb_0x67+ow_i2_enb_0x67;
assign iw_reg_0x68=ow_i0_id_0x68+ow_i1_id_0x68+ow_i2_id_0x68;
assign enb_0x68=ow_i0_enb_0x68+ow_i1_enb_0x68+ow_i2_enb_0x68;
assign iw_reg_0x69=ow_i0_id_0x69+ow_i1_id_0x69+ow_i2_id_0x69;
assign enb_0x69=ow_i0_enb_0x69+ow_i1_enb_0x69+ow_i2_enb_0x69;
assign iw_reg_0x6A=ow_i0_id_0x6A+ow_i1_id_0x6A+ow_i2_id_0x6A;
assign enb_0x6A=ow_i0_enb_0x6A+ow_i1_enb_0x6A+ow_i2_enb_0x6A;
assign iw_reg_0x6B=ow_i0_id_0x6B+ow_i1_id_0x6B+ow_i2_id_0x6B;
assign enb_0x6B=ow_i0_enb_0x6B+ow_i1_enb_0x6B+ow_i2_enb_0x6B;
assign iw_reg_0x6C=ow_i0_id_0x6C+ow_i1_id_0x6C+ow_i2_id_0x6C;
assign enb_0x6C=ow_i0_enb_0x6C+ow_i1_enb_0x6C+ow_i2_enb_0x6C;
assign iw_reg_0x6D=ow_i0_id_0x6D+ow_i1_id_0x6D+ow_i2_id_0x6D;
assign enb_0x6D=ow_i0_enb_0x6D+ow_i1_enb_0x6D+ow_i2_enb_0x6D;
assign iw_reg_0x6E=ow_i0_id_0x6E+ow_i1_id_0x6E+ow_i2_id_0x6E;
assign enb_0x6E=ow_i0_enb_0x6E+ow_i1_enb_0x6E+ow_i2_enb_0x6E;
assign iw_reg_0x6F=ow_i0_id_0x6F+ow_i1_id_0x6F+ow_i2_id_0x6F;
assign enb_0x6F=ow_i0_enb_0x6F+ow_i1_enb_0x6F+ow_i2_enb_0x6F;
endmodule
|
module simuart(input wire clk,
input wire cs,
input wire [31:0] bus_addr,
input wire [31:0] bus_wr_val,
input wire [3:0] bus_bytesel,
output reg bus_ack,
output reg [31:0] bus_data,
output reg inter,
input wire intack
);
task write_data;
begin
$uart_put(bus_wr_val[7:0]);
end
endtask
task read_data;
begin
$uart_get(uart_buf);
end
endtask
reg [8:0] uart_buf = 9'b0;
wire uart_rdy = uart_buf[8];
wire [31:0] status_reg = (uart_rdy ? 32'b10 : 32'b0);
reg ff;
reg ffold;
initial begin
bus_ack = 1'b0;
bus_data = 32'b0;
inter = 1'b0;
end
always @(posedge clk) begin
bus_data <= 32'b0;
ff <= 1'b0;
ffold <= 1'b0;
if (~uart_rdy && ~cs)
read_data();
ff<=ffold;
if (uart_rdy && (uart_buf[7:0]==8'h3)) begin
if(intack==1'b0) begin
inter <=1'b1;
end else begin
uart_buf[8]<=1'b0;
end
end else begin
if (cs && bus_bytesel[3:0] == 4'b0001) begin
if (bus_addr[3:0] == 4'b0000) begin
write_data();
end
if (bus_addr[3:0] == 4'b1000) begin
inter<=1'b0;
end
end else if (cs) begin
if (bus_addr[3:0] == 4'b0000) begin
bus_data <= {24'b0, uart_buf[7:0]};
ff <= 1'b1;
if (ff && ~ffold) uart_buf[8] <= 1'b0;
end else if (bus_addr[3:0] == 4'b0100) begin
/* Status register read. */
bus_data <= status_reg;
end
end
end
bus_ack <= cs;
end
endmodule
|
module ascii (
input scan_ready,
input [7:0] scan_code,
output [7:0] ascii
);
// @todo: shift, alt etc
reg [7:0] r_ascii;
assign ascii = r_ascii;
reg keyup = 0;
always @(posedge scan_ready) begin
if (scan_code == 8'hf0) begin
keyup <= 1;
end else begin
if (keyup) begin
keyup <= 0;
r_ascii <= 8'd0;
end else
case (scan_code)
8'h29: r_ascii <= 8'd32; // [space]
8'h45: r_ascii <= 8'd48; // 0
8'h16: r_ascii <= 8'd49; // 1
8'h1e: r_ascii <= 8'd50; // 2
8'h26: r_ascii <= 8'd51; // 3
8'h25: r_ascii <= 8'd52; // 4
8'h2e: r_ascii <= 8'd53; // 5
8'h36: r_ascii <= 8'd54; // 6
8'h3d: r_ascii <= 8'd55; // 7
8'h3e: r_ascii <= 8'd56; // 8
8'h46: r_ascii <= 8'd57; // 9
8'h1c: r_ascii <= 8'd97; // a
8'h32: r_ascii <= 8'd98; // b
8'h21: r_ascii <= 8'd99; // c
8'h23: r_ascii <= 8'd100; // d
8'h24: r_ascii <= 8'd101; // e
8'h2b: r_ascii <= 8'd102; // f
8'h34: r_ascii <= 8'd103; // g
8'h33: r_ascii <= 8'd104; // h
8'h43: r_ascii <= 8'd105; // i
8'h3b: r_ascii <= 8'd106; // j
8'h42: r_ascii <= 8'd107; // k
8'h4b: r_ascii <= 8'd108; // l
8'h3a: r_ascii <= 8'd109; // m
8'h31: r_ascii <= 8'd110; // n
8'h44: r_ascii <= 8'd111; // o
8'h4d: r_ascii <= 8'd112; // p
8'h15: r_ascii <= 8'd113; // q
8'h2d: r_ascii <= 8'd114; // r
8'h1b: r_ascii <= 8'd115; // s
8'h2c: r_ascii <= 8'd116; // t
8'h3c: r_ascii <= 8'd117; // u
8'h2a: r_ascii <= 8'd118; // v
8'h1d: r_ascii <= 8'd119; // w
8'h22: r_ascii <= 8'd120; // x
8'h35: r_ascii <= 8'd121; // y
8'h1a: r_ascii <= 8'd122; // z
default: r_ascii <= 8'd0; // nothing
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:22:12 01/30/2016
// Design Name:
// Module Name: data_access
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_access
#(
parameter B=32, // ancho de la direccion
parameter W=5 //ancho de
)
(
input wire clk,
/*Data signals input*/
input wire [B-1:0] addr_in,
input wire [B-1:0] write_data,
/*Control signals input*/
input wire [5:0] opcode,
input wire mem_write,
//input wire mem_read,
//input wire zero,
//input wire branch_in,
//input wire branchNot_in,
/*Data signals output*/
output wire [B-1:0] data_out
/*Control signals output*/
//output wire pcSrc_out
);
wire [3:0] we;
assign we[3]=mem_write;
assign we[2]=mem_write;
assign we[1]=mem_write;
assign we[0]=mem_write;
//Manejo de los "store"
wire [B-1:0] sb;
wire [B-1:0] sh;
sig_extend #(8) sb_sign
(
.reg_in(write_data[7:0]),
.reg_out(sb)
);
sig_extend sh_sign
(
.reg_in(write_data[15:0]),
.reg_out(sh)
);
wire [B-1:0] write_data_mem;
mux4 mux_store
(
.sel(opcode[1:0]),
.item_a(sb),
.item_b(sh),
.item_c(),
.item_d(write_data),
.signal(write_data_mem)
);
wire [B-1:0] data_mem;
dataMemory dm( .clka(~clk),
.rsta(1'b0),
.ena(1'b1),
.wea(we),
.addra(addr_in),
.dina(write_data_mem),
.douta(data_mem));
//Manejo de los "load"
wire [B-1:0] lb;
wire [B-1:0] lh;
wire [B-1:0] lbu;
wire [B-1:0] lhu;
wire [B-1:0] l;
wire [B-1:0] lu;
sig_extend #(8) lb_sign
(
.reg_in(data_mem[7:0]),
.reg_out(lb)
);
sig_extend lh_sign
(
.reg_in(data_mem[15:0]),
.reg_out(lh)
);
assign lbu = {{(24){1'b0}}, data_mem[7:0]};
assign lhu = {{(16){1'b0}}, data_mem[15:0]};
mux4 mux_l
(
.sel(opcode[1:0]),
.item_a(lb),
.item_b(lh),
.item_c(),
.item_d(data_mem),
.signal(l)
);
mux4 mux_lu
(
.sel(opcode[1:0]),
.item_a(lbu),
.item_b(lhu),
.item_c(),
.item_d(data_mem),
.signal(lu)
);
mux mux_data_out
(
.select(opcode[2]),
.item_a(l),
.item_b(lu),
.signal(data_out)
);
/*
//Manejo de beq y bne
wire and1;
assign and1 = branch_in && zero;
wire and2;
assign and2 = branchNot_in && (~zero);
assign pcSrc_out = and1 || and2;
*/
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_12x16_la.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_12x16_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [11:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [11:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [11:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [11:0] q = sub_wire3[11:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 12,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 12,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "12"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "12"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "12"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_12x16_la.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_12x16_la.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_12x16_la.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_12x16_la.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_12x16_la_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_12x16_la_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND_TB_V
`define SKY130_FD_SC_HDLL__TAPVGND_TB_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__tapvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hdll__tapvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND_TB_V
|
//name : main_0
//output : output_rs232_tx:16
//source_file : /tmp/tmpEtvNgA/inline_c_file.c
///+============================================================================+
///| |
///| This file was generated by Chips |
///| |
///| Chips |
///| |
///| http://github.com/dawsonjon/Chips-2.0 |
///| |
///| Python powered |
///+============================================================================+
module main_0(output_rs232_tx_ack,clk,rst,output_rs232_tx,output_rs232_tx_stb,exception);
integer file_count;
parameter stop = 3'd0,
instruction_fetch = 3'd1,
operand_fetch = 3'd2,
execute = 3'd3,
load = 3'd4,
wait_state = 3'd5,
read = 3'd6,
write = 3'd7;
input output_rs232_tx_ack;
input clk;
input rst;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
reg [31:0] timer;
reg [63:0] timer_clock;
reg [15:0] program_counter;
reg [15:0] program_counter_1;
reg [15:0] program_counter_2;
reg [43:0] instruction;
reg [3:0] opcode_2;
reg [3:0] a;
reg [3:0] b;
reg [3:0] z;
reg write_enable;
reg [3:0] address_a_2;
reg [3:0] address_b_2;
reg [3:0] address_z_2;
reg [3:0] address_z_3;
reg [31:0] load_data;
reg [31:0] write_output;
reg [31:0] write_value;
reg [31:0] read_input;
reg [15:0] literal_2;
reg [31:0] a_hi;
reg [31:0] b_hi;
reg [31:0] a_lo;
reg [31:0] b_lo;
reg [63:0] long_result;
reg [31:0] result;
reg [15:0] address;
reg [31:0] data_out;
reg [31:0] data_in;
reg [31:0] carry;
reg [31:0] s_output_rs232_tx_stb;
reg [31:0] s_output_rs232_tx;
reg [7:0] state;
output reg exception;
reg [27:0] instructions [165:0];
reg [31:0] memory [4096:0];
reg [31:0] registers [15:0];
wire [31:0] operand_a;
wire [31:0] operand_b;
wire [31:0] register_a;
wire [31:0] register_b;
wire [15:0] literal;
wire [3:0] opcode;
wire [3:0] address_a;
wire [3:0] address_b;
wire [3:0] address_z;
wire [15:0] load_address;
wire [15:0] store_address;
wire [31:0] store_data;
wire store_enable;
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'literal': True, 'op': 'literal'}
// 1 {'literal': True, 'op': 'addl'}
// 2 {'literal': False, 'op': 'store'}
// 3 {'literal': True, 'op': 'call'}
// 4 {'literal': False, 'op': 'stop'}
// 5 {'literal': False, 'op': 'load'}
// 6 {'literal': False, 'op': 'return'}
// 7 {'literal': False, 'op': 'add'}
// 8 {'literal': True, 'op': 'jmp_if_false'}
// 9 {'literal': False, 'op': 'write'}
// 10 {'literal': True, 'op': 'goto'}
// Intructions
// ===========
initial
begin
instructions[0] = {4'd0, 4'd3, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'literal': 0, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'literal'}
instructions[1] = {4'd0, 4'd4, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'literal': 0, 'z': 4, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'literal'}
instructions[2] = {4'd1, 4'd3, 4'd3, 16'd16};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'a': 3, 'literal': 16, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'addl'}
instructions[3] = {4'd0, 4'd8, 4'd0, 16'd72};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 72, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[4] = {4'd0, 4'd2, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 0, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[5] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[6] = {4'd0, 4'd8, 4'd0, 16'd101};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 101, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[7] = {4'd0, 4'd2, 4'd0, 16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 1, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[8] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[9] = {4'd0, 4'd8, 4'd0, 16'd108};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 108, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[10] = {4'd0, 4'd2, 4'd0, 16'd2};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 2, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[11] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[12] = {4'd0, 4'd8, 4'd0, 16'd108};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 108, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[13] = {4'd0, 4'd2, 4'd0, 16'd3};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 3, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[14] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[15] = {4'd0, 4'd8, 4'd0, 16'd111};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 111, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[16] = {4'd0, 4'd2, 4'd0, 16'd4};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 4, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[17] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[18] = {4'd0, 4'd8, 4'd0, 16'd32};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 32, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[19] = {4'd0, 4'd2, 4'd0, 16'd5};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 5, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[20] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[21] = {4'd0, 4'd8, 4'd0, 16'd87};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 87, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[22] = {4'd0, 4'd2, 4'd0, 16'd6};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 6, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[23] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[24] = {4'd0, 4'd8, 4'd0, 16'd111};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 111, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[25] = {4'd0, 4'd2, 4'd0, 16'd7};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 7, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[26] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[27] = {4'd0, 4'd8, 4'd0, 16'd114};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 114, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[28] = {4'd0, 4'd2, 4'd0, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 8, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[29] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[30] = {4'd0, 4'd8, 4'd0, 16'd108};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 108, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[31] = {4'd0, 4'd2, 4'd0, 16'd9};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 9, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[32] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[33] = {4'd0, 4'd8, 4'd0, 16'd100};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 100, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[34] = {4'd0, 4'd2, 4'd0, 16'd10};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 10, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[35] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[36] = {4'd0, 4'd8, 4'd0, 16'd33};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 33, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[37] = {4'd0, 4'd2, 4'd0, 16'd11};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 11, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[38] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[39] = {4'd0, 4'd8, 4'd0, 16'd10};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 10, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[40] = {4'd0, 4'd2, 4'd0, 16'd12};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 12, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[41] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[42] = {4'd0, 4'd8, 4'd0, 16'd32};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 32, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[43] = {4'd0, 4'd2, 4'd0, 16'd13};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 13, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[44] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[45] = {4'd0, 4'd8, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 0, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[46] = {4'd0, 4'd2, 4'd0, 16'd14};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 14, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[47] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[48] = {4'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'literal'}
instructions[49] = {4'd0, 4'd2, 4'd0, 16'd15};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'literal': 15, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'literal'}
instructions[50] = {4'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'store'}
instructions[51] = {4'd1, 4'd7, 4'd4, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'a': 4, 'literal': 0, 'z': 7, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'addl'}
instructions[52] = {4'd1, 4'd4, 4'd3, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'a': 3, 'literal': 0, 'z': 4, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'addl'}
instructions[53] = {4'd3, 4'd6, 4'd0, 16'd55};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'z': 6, 'label': 55, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'call'}
instructions[54] = {4'd4, 4'd0, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'stop'}
instructions[55] = {4'd1, 4'd3, 4'd3, 16'd15};///tmp/tmpEtvNgA/inline_c_file.c : 4 {'a': 3, 'literal': 15, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 4, 'op': 'addl'}
instructions[56] = {4'd2, 4'd0, 4'd3, 16'd6};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'store'}
instructions[57] = {4'd1, 4'd3, 4'd3, 16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': 1, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[58] = {4'd2, 4'd0, 4'd3, 16'd7};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'store'}
instructions[59] = {4'd1, 4'd3, 4'd3, 16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': 1, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[60] = {4'd0, 4'd8, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 0, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[61] = {4'd2, 4'd0, 4'd3, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'store'}
instructions[62] = {4'd1, 4'd3, 4'd3, 16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': 1, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[63] = {4'd1, 4'd7, 4'd4, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 4, 'literal': 0, 'z': 7, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[64] = {4'd1, 4'd4, 4'd3, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': 0, 'z': 4, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[65] = {4'd3, 4'd6, 4'd0, 16'd75};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'z': 6, 'label': 75, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'call'}
instructions[66] = {4'd1, 4'd3, 4'd3, -16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': -1, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[67] = {4'd1, 4'd3, 4'd3, -16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'comment': 'pop', 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[68] = {4'd5, 4'd7, 4'd3, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'z': 7, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'load'}
instructions[69] = {4'd1, 4'd3, 4'd3, -16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'comment': 'pop', 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[70] = {4'd5, 4'd6, 4'd3, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'z': 6, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'load'}
instructions[71] = {4'd1, 4'd3, 4'd3, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': 0, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[72] = {4'd1, 4'd3, 4'd4, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 4 {'a': 4, 'literal': 0, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 4, 'op': 'addl'}
instructions[73] = {4'd1, 4'd4, 4'd7, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 4 {'a': 7, 'literal': 0, 'z': 4, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 4, 'op': 'addl'}
instructions[74] = {4'd6, 4'd0, 4'd6, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 4 {'a': 6, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 4, 'op': 'return'}
instructions[75] = {4'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[76] = {4'd2, 4'd0, 4'd3, 16'd6};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[77] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[78] = {4'd2, 4'd0, 4'd3, 16'd7};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[79] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[80] = {4'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[81] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[82] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[83] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[84] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[85] = {4'd0, 4'd8, 4'd0, 16'd15};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'literal': 15, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'literal'}
instructions[86] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[87] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[88] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[89] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[90] = {4'd1, 4'd7, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 4, 'literal': 0, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[91] = {4'd1, 4'd4, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[92] = {4'd3, 4'd6, 4'd0, 16'd102};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'z': 6, 'label': 102, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'call'}
instructions[93] = {4'd1, 4'd3, 4'd3, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': -2, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[94] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[95] = {4'd5, 4'd7, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[96] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[97] = {4'd5, 4'd6, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'z': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[98] = {4'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[99] = {4'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[100] = {4'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[101] = {4'd6, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'return'}
instructions[102] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[103] = {4'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'literal'}
instructions[104] = {4'd1, 4'd2, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'a': 4, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'addl'}
instructions[105] = {4'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'store'}
instructions[106] = {4'd1, 4'd8, 4'd4, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 4, 'literal': -2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[107] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[108] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[109] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'store'}
instructions[110] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[111] = {4'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[112] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[113] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[114] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[115] = {4'd5, 4'd2, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[116] = {4'd7, 4'd8, 4'd8, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'z': 8, 'b': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'add'}
instructions[117] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[118] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[119] = {4'd8, 4'd0, 4'd8, 16'd161};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'a': 8, 'label': 161, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'jmp_if_false'}
instructions[120] = {4'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[121] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[122] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[123] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'store'}
instructions[124] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[125] = {4'd1, 4'd8, 4'd4, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': -2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[126] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[127] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[128] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'store'}
instructions[129] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[130] = {4'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[131] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[132] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[133] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[134] = {4'd5, 4'd2, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[135] = {4'd7, 4'd8, 4'd8, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'z': 8, 'b': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'add'}
instructions[136] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[137] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[138] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[139] = {4'd5, 4'd0, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'z': 0, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[140] = {4'd9, 4'd0, 4'd0, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 0, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'write'}
instructions[141] = {4'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[142] = {4'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[143] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[144] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[145] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[146] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[147] = {4'd0, 4'd8, 4'd0, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'literal': 1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'literal'}
instructions[148] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[149] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[150] = {4'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[151] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[152] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[153] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[154] = {4'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[155] = {4'd7, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'add'}
instructions[156] = {4'd1, 4'd2, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[157] = {4'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[158] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[159] = {4'd5, 4'd8, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[160] = {4'd10, 4'd0, 4'd0, 16'd162};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'label': 162, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'goto'}
instructions[161] = {4'd10, 4'd0, 4'd0, 16'd163};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'label': 163, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'goto'}
instructions[162] = {4'd10, 4'd0, 4'd0, 16'd106};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'label': 106, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'goto'}
instructions[163] = {4'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[164] = {4'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[165] = {4'd6, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'return'}
end
always @(posedge clk)
begin
load_data <= memory[load_address];
if(store_enable && state == execute) begin
memory[store_address] <= store_data;
end
end
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 1 -- FETCH INSTRUCTION
//
always @(posedge clk)
begin
//implement memory for instructions
if (state == instruction_fetch || state == operand_fetch || state == execute) begin
instruction <= instructions[program_counter];
program_counter_1 <= program_counter;
end
end
assign opcode = instruction[27:24];
assign address_z = instruction[23:20];
assign address_a = instruction[19:16];
assign address_b = instruction[3:0];
assign literal = instruction[15:0];
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 2 -- FETCH OPERANDS
//
always @(posedge clk)
begin
if (write_enable) begin
registers[address_z_3] <= result;
end
if (state == operand_fetch || state == execute) begin
opcode_2 <= opcode;
literal_2 <= literal;
address_a_2 <= address_a;
address_b_2 <= address_b;
address_z_2 <= address_z;
program_counter_2 <= program_counter_1;
end
end
assign register_a = registers[address_a_2];
assign register_b = registers[address_b_2];
assign operand_a = (address_a_2 == address_z_3 && write_enable)?result:register_a;
assign operand_b = (address_b_2 == address_z_3 && write_enable)?result:register_b;
assign store_address = operand_a;
assign load_address = operand_a;
assign store_data = operand_b;
assign store_enable = (opcode_2==2);
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 3 -- EXECUTE
//
always @(posedge clk)
begin
write_enable <= 0;
timer_clock <= timer_clock + 1;
case(state)
//instruction_fetch
instruction_fetch: begin
program_counter <= program_counter + 1;
state <= operand_fetch;
end
//operand_fetch
operand_fetch: begin
program_counter <= program_counter + 1;
state <= execute;
end
//execute
execute: begin
program_counter <= program_counter + 1;
address_z_3 <= address_z_2;
case(opcode_2)
//literal
16'd0:
begin
result<=$signed(literal_2);
write_enable <= 1;
end
//addl
16'd1:
begin
result<=operand_a + literal_2;
write_enable <= 1;
end
//store
16'd2:
begin
end
//call
16'd3:
begin
result <= program_counter_2 + 1;
write_enable <= 1;
program_counter <= literal_2;
state <= instruction_fetch;
end
//stop
16'd4:
begin
state <= stop;
end
//load
16'd5:
begin
state <= load;
end
//return
16'd6:
begin
program_counter <= operand_a;
state <= instruction_fetch;
end
//add
16'd7:
begin
long_result = operand_a + operand_b;
result <= long_result[31:0];
carry[0] <= long_result[32];
write_enable <= 1;
end
//jmp_if_false
16'd8:
begin
if (operand_a == 0) begin
program_counter <= literal_2;
state <= instruction_fetch;
end
end
//write
16'd9:
begin
state <= write;
write_output <= operand_a;
write_value <= operand_b;
end
//goto
16'd10:
begin
program_counter <= literal_2;
state <= instruction_fetch;
end
endcase
end
write:
begin
case(write_output)
0:
begin
s_output_rs232_tx_stb <= 1;
s_output_rs232_tx <= write_value;
if (output_rs232_tx_ack && s_output_rs232_tx_stb) begin
s_output_rs232_tx_stb <= 0;
state <= execute;
end
end
endcase
end
load:
begin
result <= load_data;
write_enable <= 1;
state <= execute;
end
wait_state:
begin
if (timer) begin
timer <= timer - 1;
end else begin
state <= execute;
end
end
stop:
begin
end
endcase
if (rst == 1'b1) begin
timer <= 0;
timer_clock <= 0;
program_counter <= 0;
address_z_3 <= 0;
result <= 0;
a = 0;
b = 0;
z = 0;
state <= instruction_fetch;
s_output_rs232_tx_stb <= 0;
end
end
assign output_rs232_tx_stb = s_output_rs232_tx_stb;
assign output_rs232_tx = s_output_rs232_tx;
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
* Copyright (C) 2018 David Shah <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
function integer round_up2;
input integer N;
begin
round_up2 = ((N + 1) / 2) * 2;
end
endfunction
localparam Y_WIDTH2 = round_up2(Y_WIDTH);
(* force_downto *)
wire [Y_WIDTH2-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] BX = B_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] C = {CO, CI};
(* force_downto *)
wire [Y_WIDTH2-1:0] FCO, Y1;
genvar i;
generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
CCU2C #(
.INIT0(16'b1001011010101010),
.INIT1(16'b1001011010101010),
.INJECT1_0("NO"),
.INJECT1_1("NO")
) ccu2c_i (
.CIN(C[i]),
.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),
.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),
.S0(Y[i]), .S1(Y1[i]),
.COUT(FCO[i])
);
assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
if (i+1 < Y_WIDTH) begin
assign CO[i+1] = FCO[i];
assign Y[i+1] = Y1[i];
end
end endgenerate
assign X = AA ^ BB;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:49:55 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top DemoInterconnect_uart_transceiver_0_0 -prefix
// DemoInterconnect_uart_transceiver_0_0_ DemoInterconnect_uart_transceiver_0_0_stub.v
// Design : DemoInterconnect_uart_transceiver_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "uart_top,Vivado 2017.3" *)
module DemoInterconnect_uart_transceiver_0_0(i_Clk, i_RX_Serial, o_RX_Done, o_RX_Byte,
i_TX_Load, i_TX_Byte, o_TX_Active, o_TX_Serial, o_TX_Done)
/* synthesis syn_black_box black_box_pad_pin="i_Clk,i_RX_Serial,o_RX_Done,o_RX_Byte[7:0],i_TX_Load,i_TX_Byte[7:0],o_TX_Active,o_TX_Serial,o_TX_Done" */;
input i_Clk;
input i_RX_Serial;
output o_RX_Done;
output [7:0]o_RX_Byte;
input i_TX_Load;
input [7:0]i_TX_Byte;
output o_TX_Active;
output o_TX_Serial;
output o_TX_Done;
endmodule
|
/**
\file "channel-source-sink-b.v"
Chain a source and sink in prsim to verilog.
$Id: channel-source-sink.v,v 1.4 2010/04/06 00:08:26 fang Exp $
*/
`timescale 1ns/1ps
`include "standard.v"
`define inv_delay 0.020
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg l0, l1, re;
wire le, r0, r1;
DELAY #(.delay(`inv_delay)) d0(l0, r0);
DELAY #(.delay(`inv_delay)) d1(l1, r1);
DELAY #(.delay(`inv_delay)) de(re, le);
// prsim stuff
initial
begin
// @haco@ channel-source-sink.haco-c
$prsim_options("-I subdir");
$prsim("channel-source-sink.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("echo-commands on");
// $prsim_cmd("addpath subdir");
$from_prsim("L.d[0]","TOP.l0");
$from_prsim("L.d[1]","TOP.l1");
$to_prsim("TOP.le", "L.e");
$to_prsim("TOP.r0", "R.d[0]");
$to_prsim("TOP.r1", "R.d[1]");
$from_prsim("R.e", "TOP.re");
$prsim_cmd("breaks");
$prsim_cmd("watchall");
// $prsim_cmd("watchall-queue");
$prsim_cmd("channel L e:0 :0 d:2");
$prsim_cmd("channel R e:1 :0 d:2");
$prsim_cmd("channel-source-file-loop L channel-values-X.txt");
$prsim_cmd("channel-sink R");
$prsim_cmd("channel-watchall");
$prsim_cmd("channel-reset-all");
$prsim_cmd("channel-show-all");
$prsim_cmd("breaks");
end
initial #5 $prsim_cmd("channel-release-all");
initial #5 $prsim_cmd("channel-show-all");
initial #6 $prsim_cmd("nowatchall");
initial #9 $prsim_cmd("why-not-verbose R.e");
initial #9 $prsim_cmd("why-not-verbose R.d[0]");
initial #10 $finish;
/**
initial
$monitor("@%7.3f: l = %d,%d:%d; r = %d,%d:%d", $realtime,
l0, l1, le, r0, r1, re);
**/
endmodule
|
`timescale 1ns/1ns
module foc_cmd
(input c,
input udp_cmd_dv,
input [31:0] udp_target_reg,
input [31:0] udp_damping_reg,
input udp_foc_active_reg,
input [31:0] temperature,
input [31:0] temperature_limit,
input ignore_temperature,
input overtemp_rst,
input [7:0] submsg_rxd,
input submsg_rxdv,
input submsg_rxlast,
output [31:0] foc_target,
output [31:0] foc_damping,
output [31:0] control_id,
output foc_active,
output float);
wire [7:0] foc_cmd_rx_control_mode;
wire [31:0] foc_cmd_rx_control_id;
wire [31:0] foc_cmd_rx_target;
wire [31:0] foc_cmd_rx_damping; // = 32'hbf80_0000;
wire foc_cmd_rx_rx;
foc_cmd_rx foc_cmd_rx_inst
(.c(c),
.submsg_rxd(submsg_rxd), .submsg_rxdv(submsg_rxdv),
.submsg_rxlast(submsg_rxlast),
.control_mode(foc_cmd_rx_control_mode),
.control_id(control_id),
.target(foc_cmd_rx_target),
.damping(foc_cmd_rx_damping),
.cmd_rx(foc_cmd_rx_rx));
wire last_cmd_from_foc_cmd;
r last_cmd_from_foc_cmd_r
(.c(c), .d(1'b1), .q(last_cmd_from_foc_cmd),
.rst(udp_cmd_dv), .en(foc_cmd_rx_rx));
wire udp_cmd_dv_d1, udp_cmd_dv_d2;
d1 udp_cmd_dv_d1_r(.c(c), .d(udp_cmd_dv), .q(udp_cmd_dv_d1));
d1 udp_cmd_dv_d2_r(.c(c), .d(udp_cmd_dv_d1), .q(udp_cmd_dv_d2));
localparam [31:0] HARD_OVERTEMP_LIMIT = 32'h42d2_0000; // 105.0 celsius
wire hard_overtemp;
fp_compare hard_overtemp_compare_r
(.clock(c), .ageb(hard_overtemp),
.dataa(temperature),
.datab(HARD_OVERTEMP_LIMIT));
wire soft_overtemp_ageb;
wire soft_overtemp = soft_overtemp_ageb & |temperature_limit;
fp_compare soft_overtemp_compare_r
(.clock(c), .ageb(soft_overtemp_ageb),
.dataa(temperature),
.datab(temperature_limit));
wire [23:0] overtemp_cnt;
r #(24) overtemp_cnt_r
(.c(c), .rst(ignore_temperature), .en(1'b1),
.d((hard_overtemp | soft_overtemp) ? overtemp_cnt + 1'b1 :
(|overtemp_cnt ? overtemp_cnt - 1'b1 : overtemp_cnt)),
.q(overtemp_cnt));
`ifdef SIM
localparam TARGET_TIMEOUT = 24'd100_000; // 1 ms
localparam ZERO_TIMEOUT = 24'd001_000;
localparam OVERTEMP_TIMEOUT = 24'd000_100;
`else
localparam TARGET_TIMEOUT = 24'd10_000_000; // 100ms timeout
localparam ZERO_TIMEOUT = 24'd10_000_000; // command zero amps for 100ms
localparam OVERTEMP_TIMEOUT = 24'd01_000_000; // 10ms overtemp timeout
`endif
localparam ST_IDLE = 4'd0;
localparam ST_RUNNING = 4'd1;
localparam ST_DRIVE_ZERO = 4'd2;
localparam ST_OVERTEMP = 4'd3;
localparam SW=4, CW=4;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire state_cnt_rst = ctrl[0];
wire [17:0] state_cnt;
r #(18) state_cnt_r
(.c(c), .rst(state_cnt_rst), .en(1'b1), .d(state_cnt+1'b1), .q(state_cnt));
always @* begin
case (state)
ST_IDLE:
if (udp_cmd_dv_d2 | foc_cmd_rx_rx) ctrl = { ST_RUNNING , 4'b0000 };
else ctrl = { ST_IDLE , 4'b0000 };
ST_RUNNING:
if (overtemp_cnt > OVERTEMP_TIMEOUT) ctrl = { ST_DRIVE_ZERO, 4'b0010 };
else if (timeout) ctrl = { ST_DRIVE_ZERO, 4'b0001 };
else ctrl = { ST_RUNNING , 4'b0000 };
ST_DRIVE_ZERO:
if ((udp_cmd_dv_d2 | foc_cmd_rx_rx) &
~overtemp_latch) ctrl = { ST_RUNNING , 4'b0000 };
else if (state_cnt == ZERO_TIMEOUT)
if (overtemp_latch) ctrl = { ST_OVERTEMP , 4'b0000 };
else ctrl = { ST_IDLE , 4'b0000 };
else ctrl = { ST_DRIVE_ZERO, 4'b0000 };
ST_OVERTEMP:
if (~overtemp_latch) ctrl = { ST_IDLE , 4'b0000 };
else ctrl = { ST_OVERTEMP , 4'b0000 };
default: ctrl = { ST_IDLE , 4'b0000 };
endcase
end
wire overtemp_latch;
r overtemp_latch_r
(.c(c), .rst(overtemp_rst), .en(ctrl[1]), .d(1'b1), .q(overtemp_latch));
wire [23:0] timeout_cnt;
r #(24) timeout_cnt_r
(.c(c), .rst(udp_cmd_dv | foc_cmd_rx_rx), .en(1'b1),
.d(timeout_cnt+1'b1), .q(timeout_cnt));
wire timeout = timeout_cnt == TARGET_TIMEOUT;
wire [31:0] next_foc_target;
d1 #(32) next_foc_target_r
(.c(c), .d(last_cmd_from_foc_cmd ? foc_cmd_rx_target : udp_target_reg),
.q(next_foc_target));
wire [31:0] next_foc_damping;
d1 #(32) next_foc_damping_r
(.c(c), .d(last_cmd_from_foc_cmd ? foc_cmd_rx_damping : udp_damping_reg),
.q(next_foc_damping));
r #(32) foc_target_r
(.c(c), .rst(1'b0), .en(1'b1),
.d(state == ST_RUNNING ? next_foc_target : 32'h0), .q(foc_target));
r #(32) foc_damping_r
(.c(c), .rst(1'b0), .en(1'b1),
.d(state == ST_RUNNING ? next_foc_damping : 32'h0), .q(foc_damping));
//assign foc_damping = foc_cmd_rx_damping;
assign float = state == ST_IDLE | state == ST_OVERTEMP;
assign foc_active = udp_foc_active_reg &
(state == ST_RUNNING |
state == ST_DRIVE_ZERO);
endmodule
|
/*
Modified from John Loomis, http://www.johnloomis.org/
-------------------------------------------------------------------
-- ASCII HEX TABLE
-- Hex Low Hex Digit
-- Value 0 1 2 3 4 5 6 7 8 9 A B C D E F
------\----------------------------------------------------------------
--H 2 | SP ! " # $ % & ' ( ) * + , - . /
--i 3 | 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
--g 4 | @ A B C D E F G H I J K L M N O
--h 5 | P Q R S T U V W X Y Z [ \ ] ^ _
-- 6 | ` a b c d e f g h i j k l m n o
-- 7 | p q r s t u v w x y z { | } ~ DEL
-----------------------------------------------------------------------
-- Example "A" is row 4 column 1, so hex value is 8'h41"
-- *see LCD Controller's Datasheet for other graphics characters available
*/
module LCD_Display(iCLK_50MHZ, iRST_N, state_code,
LCD_RS,LCD_E,LCD_RW,DATA_BUS);
input iCLK_50MHZ, iRST_N; //In Feed Beep this reset will not be used, so need RST_N=1
input [4:0] state_code;
output LCD_RS, LCD_E, LCD_RW;
inout [7:0] DATA_BUS;
parameter
HOLD = 4'h0,
FUNC_SET = 4'h1,
DISPLAY_ON = 4'h2,
MODE_SET = 4'h3,
Print_String = 4'h4,
LINE2 = 4'h5,
RETURN_HOME = 4'h6,
DROP_LCD_E = 4'h7,
RESET1 = 4'h8,
RESET2 = 4'h9,
RESET3 = 4'ha,
DISPLAY_OFF = 4'hb,
DISPLAY_CLEAR = 4'hc;
reg [3:0] state, next_command;
// Enter new ASCII hex data above for LCD Display
reg [7:0] DATA_BUS_VALUE;
wire [7:0] Next_Char;
reg [19:0] CLK_COUNT_400HZ;
reg [4:0] CHAR_COUNT;
reg CLK_400HZ, LCD_RW_INT, LCD_E, LCD_RS;
// BIDIRECTIONAL TRI STATE LCD DATA BUS
assign DATA_BUS = (LCD_RW_INT? 8'bZZZZZZZZ: DATA_BUS_VALUE);
LCD_display_string u1(
.index(CHAR_COUNT),
.out(Next_Char),
.state_code(state_code));
assign LCD_RW = LCD_RW_INT;
always @(posedge iCLK_50MHZ or negedge iRST_N)
if (!iRST_N)
begin
CLK_COUNT_400HZ <= 20'h00000;
CLK_400HZ <= 1'b0;
end
else if (CLK_COUNT_400HZ < 20'h0F424)
begin
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1'b1;
end
else
begin
CLK_COUNT_400HZ <= 20'h00000;
CLK_400HZ <= ~CLK_400HZ;
end
// State Machine to send commands and data to LCD DISPLAY
always @(posedge CLK_400HZ or negedge iRST_N)
if (!iRST_N)
begin
state <= RESET1;
end
else
case (state)
RESET1:
// Set Function to 8-bit transfer and 2 line display with 5x8 Font size
// see Hitachi HD44780 family data sheet for LCD command and timing details
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= RESET2;
CHAR_COUNT <= 5'b00000;
end
RESET2:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= RESET3;
end
RESET3:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= FUNC_SET;
end
// EXTRA STATES ABOVE ARE NEEDED FOR RELIABLE PUSHBUTTON RESET OF LCD
FUNC_SET:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= DISPLAY_OFF;
end
// Turn off Display and Turn off cursor
DISPLAY_OFF:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h08;
state <= DROP_LCD_E;
next_command <= DISPLAY_CLEAR;
end
// Clear Display and Turn off cursor
DISPLAY_CLEAR:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h01;
state <= DROP_LCD_E;
next_command <= DISPLAY_ON;
end
// Turn on Display and Turn off cursor
DISPLAY_ON:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h0C;
state <= DROP_LCD_E;
next_command <= MODE_SET;
end
// Set write mode to auto increment address and move cursor to the right
MODE_SET:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h06;
state <= DROP_LCD_E;
next_command <= Print_String;
end
// Write ASCII hex character in first LCD character location
Print_String:
begin
state <= DROP_LCD_E;
LCD_E <= 1'b1;
LCD_RS <= 1'b1;
LCD_RW_INT <= 1'b0;
// ASCII character to output
if (Next_Char[7:4] != 4'h0)
DATA_BUS_VALUE <= Next_Char;
// Convert 4-bit value to an ASCII hex digit
else if (Next_Char[3:0] >9)
// ASCII A...F
DATA_BUS_VALUE <= {4'h4,Next_Char[3:0]-4'h9};
else
// ASCII 0...9
DATA_BUS_VALUE <= {4'h3,Next_Char[3:0]};
// Loop to send out 32 characters to LCD Display (16 by 2 lines)
if ((CHAR_COUNT < 31) && (Next_Char != 8'hFE))
CHAR_COUNT <= CHAR_COUNT + 1'b1;
else
CHAR_COUNT <= 5'b00000;
// Jump to second line?
if (CHAR_COUNT == 15)
next_command <= LINE2;
// Return to first line?
else if ((CHAR_COUNT == 31) || (Next_Char == 8'hFE))
next_command <= RETURN_HOME;
else
next_command <= Print_String;
end
// Set write address to line 2 character 1
LINE2:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'hC0;
state <= DROP_LCD_E;
next_command <= Print_String;
end
// Return write address to first character postion on line 1
RETURN_HOME:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h80;
state <= DROP_LCD_E;
next_command <= Print_String;
end
// The next three states occur at the end of each command or data transfer to the LCD
// Drop LCD E line - falling edge loads inst/data to LCD controller
DROP_LCD_E:
begin
LCD_E <= 1'b0;
state <= HOLD;
end
// Hold LCD inst/data valid after falling edge of E line
HOLD:
begin
state <= next_command;
end
endcase
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:frequency_analyzer_manager:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_frequency_analyzer_manager_0_1 (
data,
pixel_clock,
start,
stop,
clear,
irq,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready
);
input wire [7 : 0] data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 pixel_clock CLK" *)
input wire pixel_clock;
input wire start;
input wire stop;
input wire clear;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 irq INTERRUPT" *)
output wire irq;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
input wire s00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [9 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [9 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
frequency_analyzer_manager #(
.C_S00_AXI_DATA_WIDTH(32),
.C_S00_AXI_ADDR_WIDTH(10),
.PIXEL0_INDEX(63),
.PIXEL1_INDEX(511),
.PIXEL2_INDEX(1000),
.PIXEL0_FREQUENCY0(5000),
.PIXEL0_FREQUENCY1(10000),
.PIXEL1_FREQUENCY0(15000),
.PIXEL1_FREQUENCY1(20000),
.PIXEL2_FREQUENCY0(40000),
.PIXEL2_FREQUENCY1(50000),
.FREQUENCY_DEVIATION(20),
.CLOCK_FREQUENCY(100000000)
) inst (
.data(data),
.pixel_clock(pixel_clock),
.start(start),
.stop(stop),
.clear(clear),
.irq(irq),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
module artemis_pcie_interface #(
parameter CONTROL_FIFO_DEPTH = 7,
parameter DATA_FIFO_DEPTH = 9,
parameter SERIAL_NUMBER = 64'h000000000000C594
)(
input clk,
input rst,
//The Following Signals are clocked at 62.5MHz
// PCI Express Fabric Interface
input gtp_clk_p,
input gtp_clk_n,
output pci_exp_txp,
output pci_exp_txn,
input pci_exp_rxp,
input pci_exp_rxn,
// Transaction (TRN) Interface
output user_lnk_up,
output pcie_clk,
// Flow Control
input [2:0] fc_sel,
output [7:0] fc_nph,
output [11:0] fc_npd,
output [7:0] fc_ph,
output [11:0] fc_pd,
output [7:0] fc_cplh,
output [11:0] fc_cpld,
// Host (CFG) Interface
output [31:0] cfg_do,
output cfg_rd_wr_done,
input [9:0] cfg_dwaddr,
input cfg_rd_en,
// Configuration: Error
input cfg_err_ur,
input cfg_err_cor,
input cfg_err_ecrc,
input cfg_err_cpl_timeout,
input cfg_err_cpl_abort,
input cfg_err_posted,
input cfg_err_locked,
input [47:0] cfg_err_tlp_cpl_header,
output cfg_err_cpl_rdy,
// Conifguration: Interrupt
input cfg_interrupt,
output cfg_interrupt_rdy,
input cfg_interrupt_assert,
output [7:0] cfg_interrupt_do,
input [7:0] cfg_interrupt_di,
output [2:0] cfg_interrupt_mmenable,
output cfg_interrupt_msienable,
// Configuration: Power Management
input cfg_turnoff_ok,
output cfg_to_turnoff,
input cfg_pm_wake,
// Configuration: System/Status
output [2:0] cfg_pcie_link_state,
input cfg_trn_pending_stb,
output [7:0] cfg_bus_number,
output [4:0] cfg_device_number,
output [2:0] cfg_function_number,
output [15:0] cfg_status,
output [15:0] cfg_command,
output [15:0] cfg_dstatus,
output [15:0] cfg_dcommand,
output [15:0] cfg_lstatus,
output [15:0] cfg_lcommand,
// System Interface
output pcie_reset,
output pll_lock_detect,
output gtp_pll_lock_detect,
output gtp_reset_done,
output rx_elec_idle,
output received_hot_reset,
input i_cmd_in_rd_stb,
output o_cmd_in_rd_ready,
input i_cmd_in_rd_activate,
output [23:0] o_cmd_in_rd_count,
output [31:0] o_cmd_in_rd_data,
output [1:0] o_cmd_out_wr_ready,
input [1:0] i_cmd_out_wr_activate,
output [23:0] o_cmd_out_wr_size,
input i_cmd_out_wr_stb,
input [31:0] i_cmd_out_wr_data,
input i_data_in_rd_stb,
output o_data_in_rd_ready,
input i_data_in_rd_activate,
output [23:0] o_data_in_rd_count,
output [31:0] o_data_in_rd_data,
output [1:0] o_data_out_wr_ready,
input [1:0] i_data_out_wr_activate,
output [23:0] o_data_out_wr_size,
input i_data_out_wr_stb,
input [31:0] i_data_out_wr_data,
input [1:0] rx_equalizer_ctrl,
input [3:0] tx_diff_ctrl,
input [2:0] tx_pre_emphasis,
output [4:0] cfg_ltssm_state,
output dbg_reg_detected_correctable,
output dbg_reg_detected_fatal,
output dbg_reg_detected_non_fatal,
output dbg_reg_detected_unsupported,
output dbg_bad_dllp_status,
output dbg_bad_tlp_lcrc,
output dbg_bad_tlp_seq_num,
output dbg_bad_tlp_status,
output dbg_dl_protocol_status,
output dbg_fc_protocol_err_status,
output dbg_mlfrmd_length,
output dbg_mlfrmd_mps,
output dbg_mlfrmd_tcvc,
output dbg_mlfrmd_tlp_status,
output dbg_mlfrmd_unrec_type,
output dbg_poistlpstatus,
output dbg_rcvr_overflow_status,
output dbg_rply_rollover_status,
output dbg_rply_timeout_status,
output dbg_ur_no_bar_hit,
output dbg_ur_pois_cfg_wr,
output dbg_ur_status,
output dbg_ur_unsup_msg
);
//local parameters
localparam CONTROL_FIFO_SIZE = (2 ** CONTROL_FIFO_DEPTH);
localparam DATA_FIFO_SIZE = (2 ** DATA_FIFO_DEPTH);
localparam CONTROL_FUNCTION_ID = 1'b0;
localparam DATA_FUNCTION_ID = 1'b1;
//registes/wires
(* KEEP = "TRUE" *) wire clk_62p5;
//Control Signals
wire [1:0] c_in_wr_ready;
wire [1:0] c_in_wr_activate;
wire [23:0] c_in_wr_size;
wire c_in_wr_stb;
wire [31:0] c_in_wr_data;
wire c_out_rd_stb;
wire c_out_rd_ready;
wire c_out_rd_activate;
wire [23:0] c_out_rd_size;
wire [31:0] c_out_rd_data;
//Data
wire [1:0] d_in_wr_ready;
wire [1:0] d_in_wr_activate;
wire [23:0] d_in_wr_size;
wire d_in_wr_stb;
wire [31:0] d_in_wr_data;
wire d_out_rd_stb;
wire d_out_rd_ready;
wire d_out_rd_activate;
wire [23:0] d_out_rd_size;
wire [31:0] d_out_rd_data;
wire axi_clk;
//Control Signals
wire c_in_axi_ready;
wire [31:0] c_in_axi_data;
wire [3:0] c_in_axi_keep;
wire c_in_axi_last;
wire c_in_axi_valid;
wire c_out_axi_ready;
wire [31:0] c_out_axi_data;
wire [3:0] c_out_axi_keep;
wire c_out_axi_last;
wire c_out_axi_valid;
//Data Signals
wire d_in_axi_ready;
wire [31:0] d_in_axi_data;
wire [3:0] d_in_axi_keep;
wire d_in_axi_last;
wire d_in_axi_valid;
wire d_out_axi_ready;
wire [31:0] d_out_axi_data;
wire [3:0] d_out_axi_keep;
wire d_out_axi_last;
wire d_out_axi_valid;
wire [31:0] m_axis_rx_tdata;
wire [3:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire s_axis_tx_tready;
wire [31:0] s_axis_tx_tdata;
wire [3:0] s_axis_tx_tkeep;
wire [3:0] s_axis_tx_tuser;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
wire cfg_trn_pending;
assign s_axis_tx_tuser = 0;
//submodules
/*
cross_clock_strobe trn_pnd (
.rst (rst ),
.in_clk (clk ),
.in_stb (cfg_trn_pending_stb),
.out_clk (clk_62p5 ),
.out_stb (cfg_trn_pending )
);
*/
assign cfg_trn_pending = 0;
wire tx_cfg_gnt;
wire rx_np_ok;
/*** ALLOW THE Normal PRIORITIZATION! ***/
assign tx_cfg_gnt = 1'b1;
//READY TO ACCEPT NON POSTED THIMAGIGGERS
assign rx_np_ok = 1'b1;
pcie_axi_bridge pcie_interface (
// PCI Express Fabric Interface
.pci_exp_txp (pci_exp_txp ),
.pci_exp_txn (pci_exp_txn ),
.pci_exp_rxp (pci_exp_rxp ),
.pci_exp_rxn (pci_exp_rxn ),
// Transaction (TRN) Interface
.user_lnk_up (user_lnk_up ),
// Tx
.s_axis_tx_tready (s_axis_tx_tready ),
.s_axis_tx_tdata (s_axis_tx_tdata ),
.s_axis_tx_tkeep (s_axis_tx_tkeep ),
.s_axis_tx_tuser (s_axis_tx_tuser ),
.s_axis_tx_tlast (s_axis_tx_tlast ),
.s_axis_tx_tvalid (s_axis_tx_tvalid ),
/*
//TODO
output reg [5:0] tx_buf_av,
output reg tx_err_drop,
output reg tx_cfg_req,
*/
.tx_cfg_gnt (tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata (m_axis_rx_tdata ),
.m_axis_rx_tkeep (m_axis_rx_tkeep ),
.m_axis_rx_tlast (m_axis_rx_tlast ),
.m_axis_rx_tvalid (m_axis_rx_tvalid ),
.m_axis_rx_tready (m_axis_rx_tready ),
// output reg [21:0] m_axis_rx_tuser,
// input rx_np_ok,
.rx_np_ok (rx_np_ok ),
// Flow Control
.fc_sel (fc_sel ),
.fc_nph (fc_nph ),
.fc_npd (fc_npd ),
.fc_ph (fc_ph ),
.fc_pd (fc_pd ),
.fc_cplh (fc_cplh ),
.fc_cpld (fc_cpld ),
// Host Interface
.cfg_do (cfg_do ),
.cfg_rd_wr_done (cfg_rd_wr_done ),
.cfg_dwaddr (cfg_dwaddr ),
.cfg_rd_en (cfg_rd_en ),
// Configuration: Error
.cfg_err_ur (cfg_err_ur ),
.cfg_err_cor (cfg_err_cor ),
.cfg_err_ecrc (cfg_err_ecrc ),
.cfg_err_cpl_timeout (cfg_err_cpl_timeout ),
.cfg_err_cpl_abort (cfg_err_cpl_abort ),
.cfg_err_posted (cfg_err_posted ),
.cfg_err_locked (cfg_err_locked ),
.cfg_err_tlp_cpl_header (cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy (cfg_err_cpl_rdy ),
// Conifguration: Interrupt
.cfg_interrupt (cfg_interrupt ),
.cfg_interrupt_rdy (cfg_interrupt_rdy ),
.cfg_interrupt_assert (cfg_interrupt_assert ),
.cfg_interrupt_do (cfg_interrupt_do ),
.cfg_interrupt_di (cfg_interrupt_di ),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable ),
.cfg_interrupt_msienable (cfg_interrupt_msienable ),
// Configuration: Power Management
.cfg_turnoff_ok (cfg_turnoff_ok ),
.cfg_to_turnoff (cfg_to_turnoff ),
.cfg_pm_wake (cfg_pm_wake ),
// Configuration: System/Status
.cfg_pcie_link_state (cfg_pcie_link_state ),
.cfg_trn_pending (cfg_trn_pending ),
.cfg_dsn (SERIAL_NUMBER ),
.cfg_bus_number (cfg_bus_number ),
.cfg_device_number (cfg_device_number ),
.cfg_function_number (cfg_function_number ),
.cfg_status (cfg_status ),
.cfg_command (cfg_command ),
.cfg_dstatus (cfg_dstatus ),
.cfg_dcommand (cfg_dcommand ),
.cfg_lstatus (cfg_lstatus ),
.cfg_lcommand (cfg_lcommand ),
// System Interface
.sys_clk_p (gtp_clk_p ),
.sys_clk_n (gtp_clk_n ),
.sys_reset (rst ),
.user_clk_out (clk_62p5 ),
.user_reset_out (pcie_reset ),
.received_hot_reset (received_hot_reset ),
.pll_lock_detect (pll_lock_detect ),
.gtp_pll_lock_detect (gtp_pll_lock_detect ),
.gtp_reset_done (gtp_reset_done ),
.rx_elec_idle (rx_elec_idle ),
.rx_equalizer_ctrl (rx_equalizer_ctrl ),
.tx_diff_ctrl (tx_diff_ctrl ),
.tx_pre_emphasis (tx_pre_emphasis ),
.cfg_ltssm_state (cfg_ltssm_state ),
.dbg_reg_detected_correctable (dbg_reg_detected_correctable ),
.dbg_reg_detected_fatal (dbg_reg_detected_fatal ),
.dbg_reg_detected_non_fatal (dbg_reg_detected_non_fatal ),
.dbg_reg_detected_unsupported (dbg_reg_detected_unsupported ),
.dbg_bad_dllp_status (dbg_bad_dllp_status ),
.dbg_bad_tlp_lcrc (dbg_bad_tlp_lcrc ),
.dbg_bad_tlp_seq_num (dbg_bad_tlp_seq_num ),
.dbg_bad_tlp_status (dbg_bad_tlp_status ),
.dbg_dl_protocol_status (dbg_dl_protocol_status ),
.dbg_fc_protocol_err_status (dbg_fc_protocol_err_status ),
.dbg_mlfrmd_length (dbg_mlfrmd_length ),
.dbg_mlfrmd_mps (dbg_mlfrmd_mps ),
.dbg_mlfrmd_tcvc (dbg_mlfrmd_tcvc ),
.dbg_mlfrmd_tlp_status (dbg_mlfrmd_tlp_status ),
.dbg_mlfrmd_unrec_type (dbg_mlfrmd_unrec_type ),
.dbg_poistlpstatus (dbg_poistlpstatus ),
.dbg_rcvr_overflow_status (dbg_rcvr_overflow_status ),
.dbg_rply_rollover_status (dbg_rply_rollover_status ),
.dbg_rply_timeout_status (dbg_rply_timeout_status ),
.dbg_ur_no_bar_hit (dbg_ur_no_bar_hit ),
.dbg_ur_pois_cfg_wr (dbg_ur_pois_cfg_wr ),
.dbg_ur_status (dbg_ur_status ),
.dbg_ur_unsup_msg (dbg_ur_unsup_msg )
);
adapter_axi_stream_2_ppfifo cntrl_a2p (
.rst (pcie_reset ),
//AXI Stream Input
.i_axi_clk (axi_clk ),
.o_axi_ready (c_in_axi_ready ),
.i_axi_data (c_in_axi_data ),
.i_axi_keep (c_in_axi_keep ),
.i_axi_last (c_in_axi_last ),
.i_axi_valid (c_in_axi_valid ),
//Ping Pong FIFO Write Controller
.o_ppfifo_clk (axi_clk ),
.i_ppfifo_rdy (c_in_wr_ready ),
.o_ppfifo_act (c_in_wr_activate ),
.i_ppfifo_size (c_in_wr_size ),
.o_ppfifo_stb (c_in_wr_stb ),
.o_ppfifo_data (c_in_wr_data )
);
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (CONTROL_FIFO_DEPTH - 2)
) pcie_control_ingress (
//Control Signals
.reset (pcie_reset ),
//Write Side
.write_clock (axi_clk ),
.write_ready (c_in_wr_ready ),
.write_activate (c_in_wr_activate ),
.write_fifo_size (c_in_wr_size ),
.write_strobe (c_in_wr_stb ),
.write_data (c_in_wr_data ),
.starved ( ),
//Read Size
.read_clock (clk ),
.read_strobe (i_cmd_in_rd_stb ),
.read_ready (o_cmd_in_rd_ready ),
.read_activate (i_cmd_in_rd_activate ),
.read_count (o_cmd_in_rd_count ),
.read_data (o_cmd_in_rd_data ),
.inactive ( )
);
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (CONTROL_FIFO_DEPTH - 2)
) pcie_control_egress (
//Control Signals
.reset (pcie_reset ),
//Write Side
.write_clock (clk ),
.write_ready (o_cmd_out_wr_ready ),
.write_activate (i_cmd_out_wr_activate),
.write_fifo_size (o_cmd_out_wr_size ),
.write_strobe (i_cmd_out_wr_stb ),
.write_data (i_cmd_out_wr_data ),
.starved ( ),
//Read Size
.read_clock (axi_clk ),
.read_strobe (c_out_rd_stb ),
.read_ready (c_out_rd_ready ),
.read_activate (c_out_rd_activate),
.read_count (c_out_rd_size ),
.read_data (c_out_rd_data ),
.inactive ( )
);
adapter_ppfifo_2_axi_stream control_p2a (
.rst (pcie_reset ),
//Ping Poing FIFO Read Interface
.i_ppfifo_clk (axi_clk ),
.i_ppfifo_rdy (c_out_rd_ready ),
.o_ppfifo_act (c_out_rd_activate),
.i_ppfifo_size (c_out_rd_size ),
.i_ppfifo_data (c_out_rd_data ),
.o_ppfifo_stb (c_out_rd_stb ),
//AXI Stream Output
.o_axi_clk ( ),
.i_axi_ready (c_out_axi_ready ),
.o_axi_data (c_out_axi_data ),
.o_axi_keep (c_out_axi_keep ),
.o_axi_last (c_out_axi_last ),
.o_axi_valid (c_out_axi_valid )
);
//Data FIFOs
adapter_axi_stream_2_ppfifo data_a2p (
.rst (pcie_reset ),
//AXI Stream Input
.i_axi_clk (axi_clk ),
.o_axi_ready (d_in_axi_ready ),
.i_axi_data (d_in_axi_data ),
.i_axi_keep (d_in_axi_keep ),
.i_axi_last (d_in_axi_last ),
.i_axi_valid (d_in_axi_valid ),
//Ping Pong FIFO Write Controller
.o_ppfifo_clk ( ),
.i_ppfifo_rdy (d_in_wr_ready ),
.o_ppfifo_act (d_in_wr_activate ),
.i_ppfifo_size (d_in_wr_size ),
.o_ppfifo_stb (d_in_wr_stb ),
.o_ppfifo_data (d_in_wr_data )
);
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (DATA_FIFO_DEPTH - 2 )
) pcie_data_ingress (
//Control Signals
.reset (pcie_reset ),
//Write Side
.write_clock (axi_clk ),
.write_ready (d_in_wr_ready ),
.write_activate (d_in_wr_activate ),
.write_fifo_size (d_in_wr_size ),
.write_strobe (d_in_wr_stb ),
.write_data (d_in_wr_data ),
.starved (),
//Read Size
.read_clock (clk ),
.read_strobe (i_data_in_rd_stb ),
.read_ready (o_data_in_rd_ready ),
.read_activate (i_data_in_rd_activate ),
.read_count (o_data_in_rd_count ),
.read_data (o_data_in_rd_data ),
.inactive ()
);
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (DATA_FIFO_DEPTH - 2 )
) pcie_data_egress (
//Control Signals
.reset (pcie_reset ),
//Write Side
.write_clock (clk ),
.write_ready (o_data_out_wr_ready ),
.write_activate (i_data_out_wr_activate),
.write_fifo_size (o_data_out_wr_size ),
.write_strobe (i_data_out_wr_stb ),
.write_data (i_data_out_wr_data ),
.starved (),
//Read Size
.read_clock (axi_clk ),
.read_strobe (d_out_rd_stb ),
.read_ready (d_out_rd_ready ),
.read_activate (d_out_rd_activate),
.read_count (d_out_rd_size ),
.read_data (d_out_rd_data ),
.inactive ()
);
adapter_ppfifo_2_axi_stream data_p2a (
.rst (pcie_reset ),
//Ping Poing FIFO Read Interface
.i_ppfifo_clk (axi_clk ),
.i_ppfifo_rdy (d_out_rd_ready ),
.o_ppfifo_act (d_out_rd_activate),
.i_ppfifo_size (d_out_rd_size ),
.i_ppfifo_data (d_out_rd_data ),
.o_ppfifo_stb (d_out_rd_stb ),
//AXI Stream Output
.o_axi_clk ( ),
.i_axi_ready (d_out_axi_ready ),
.o_axi_data (d_out_axi_data ),
.o_axi_keep (d_out_axi_keep ),
.o_axi_last (d_out_axi_last ),
.o_axi_valid (d_out_axi_valid )
);
//asynchronous logic
assign axi_clk = clk_62p5;
assign pcie_clk = clk_62p5;
//Map the PCIE to PPFIFO FIFO
assign m_axis_rx_tready = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? c_in_axi_ready : d_in_axi_ready;
assign c_in_axi_data = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? m_axis_rx_tdata: 32'h00000000;
assign d_in_axi_data = (cfg_function_number[0] == DATA_FUNCTION_ID) ? m_axis_rx_tdata: 32'h00000000;
assign c_in_axi_keep = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? m_axis_rx_tkeep: 32'h00000000;
assign d_in_axi_keep = (cfg_function_number[0] == DATA_FUNCTION_ID) ? m_axis_rx_tkeep: 32'h00000000;
assign c_in_axi_last = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? m_axis_rx_tlast: 32'h00000000;
assign d_in_axi_last = (cfg_function_number[0] == DATA_FUNCTION_ID) ? m_axis_rx_tlast: 32'h00000000;
assign c_in_axi_valid = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? m_axis_rx_tvalid: 32'h00000000;
assign d_in_axi_valid = (cfg_function_number[0] == DATA_FUNCTION_ID) ? m_axis_rx_tvalid: 32'h00000000;
assign c_out_axi_ready = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? s_axis_tx_tready: 32'h00000000;
assign d_out_axi_ready = (cfg_function_number[0] == DATA_FUNCTION_ID) ? s_axis_tx_tready: 32'h00000000;
assign s_axis_tx_tdata = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? c_out_axi_data : d_out_axi_data;
assign s_axis_tx_tkeep = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? c_out_axi_keep : d_out_axi_keep;
assign s_axis_tx_tlast = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? c_out_axi_last : d_out_axi_last;
assign s_axis_tx_tvalid = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? c_out_axi_valid : d_out_axi_valid;
//synchronous logic
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:07:05 10/11/2015
// Design Name:
// Module Name: UART_fifo_interface
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_fifo_interface #(parameter bits_depth=4)(
input write_flag,
input read_next,
input [7:0] data_in,
input clock,
input reset,
output reg [7:0] data_out,
output reg empty_flag,
output reg full_flag
);
localparam depth= 1<<(bits_depth);
reg [7:0] FIFO [depth-1:0];
reg [(bits_depth-1):0] read_pointer,
write_pointer;
reg [(bits_depth):0] free_space;
always @* begin
full_flag = (free_space==0);
empty_flag = (free_space==depth);
data_out <= FIFO[read_pointer];
end
always @(posedge clock, posedge reset) begin
if(reset) begin
write_pointer <= 0;
read_pointer <= 0;
free_space <= depth;
end
else begin
if(read_next) begin
if(!empty_flag) begin
read_pointer <= read_pointer + 'b1;
free_space <= free_space + 'b1;
end
end
if(write_flag) begin
FIFO[write_pointer] <= data_in;
write_pointer <= write_pointer + 'b1;
if(!full_flag) begin
free_space <= (free_space - 'b1) ;
end
else if(!empty_flag) begin
read_pointer <= read_pointer + 'b1;
end
end
end
end
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_tb_test_data_gen.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module contains the data generation logic for the synthesizable
// testbench.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_tb_test_data_gen #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0
)
(
input clk,
input rst,
input wr_data_en,
input rd_data_valid,
output app_wdf_wren,
output reg [APPDATA_WIDTH-1:0] app_wdf_data,
output reg [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output [APPDATA_WIDTH-1:0] app_cmp_data
);
localparam WR_IDLE_FIRST_DATA = 2'b00;
localparam WR_SECOND_DATA = 2'b01;
localparam WR_THIRD_DATA = 2'b10;
localparam WR_FOURTH_DATA = 2'b11;
localparam RD_IDLE_FIRST_DATA = 2'b00;
localparam RD_SECOND_DATA = 2'b01;
localparam RD_THIRD_DATA = 2'b10;
localparam RD_FOURTH_DATA = 2'b11;
reg [APPDATA_WIDTH-1:0] app_wdf_data_r;
reg [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data_r;
wire app_wdf_wren_r;
reg [(APPDATA_WIDTH/2)-1:0] rd_data_pat_fall;
reg [(APPDATA_WIDTH/2)-1:0] rd_data_pat_rise;
wire rd_data_valid_r;
reg [1:0] rd_state;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
wire [APPDATA_WIDTH-1:0] wr_data;
reg wr_data_en_r;
reg [(APPDATA_WIDTH/2)-1:0] wr_data_fall
/* synthesis syn_maxfan = 2 */;
reg [(APPDATA_WIDTH/2)-1:0] wr_data_rise
/* synthesis syn_maxfan = 2 */;
wire [(APPDATA_WIDTH/8)-1:0] wr_mask_data;
wire [(APPDATA_WIDTH/16)-1:0] wr_mask_data_fall;
wire [(APPDATA_WIDTH/16)-1:0] wr_mask_data_rise;
reg [1:0] wr_state;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//***************************************************************************
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
// used for fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
always @(posedge clk) begin
app_wdf_data_r <= wr_data;
app_wdf_mask_data_r <= wr_mask_data;
app_wdf_data <= app_wdf_data_r;
app_wdf_mask_data <= app_wdf_mask_data_r;
end
// inst ff for timing
FDRSE ff_wdf_wren
(
.Q (app_wdf_wren_r),
.C (clk),
.CE (1'b1),
.D (wr_data_en_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_wdf_wren_r
(
.Q (app_wdf_wren),
.C (clk),
.CE (1'b1),
.D (app_wdf_wren_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_rd_data_valid_r
(
.Q (rd_data_valid_r),
.C (clk),
.CE (1'b1),
.D (rd_data_valid),
.R (1'b0),
.S (1'b0)
);
//***************************************************************************
// DATA generation for WRITE DATA FIFOs & for READ DATA COMPARE
//***************************************************************************
assign wr_data = {wr_data_fall, wr_data_rise};
assign wr_mask_data = {wr_mask_data_fall, wr_mask_data_rise};
//*****************************************************************
// For now, don't vary data masks
//*****************************************************************
assign wr_mask_data_rise = {(APPDATA_WIDTH/8){1'b0}};
assign wr_mask_data_fall = {(APPDATA_WIDTH/8){1'b0}};
//*****************************************************************
// Write data logic
//*****************************************************************
// write data generation
//synthesis attribute max_fanout of wr_data_fall is 2
//synthesis attribute max_fanout of wr_data_rise is 2
always @(posedge clk) begin
if (rst_r1) begin
wr_data_rise <= {(APPDATA_WIDTH/2){1'bx}};
wr_data_fall <= {(APPDATA_WIDTH/2){1'bx}};
wr_state <= WR_IDLE_FIRST_DATA;
end else begin
case (wr_state)
WR_IDLE_FIRST_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/2){1'b1}}; // 0xF
wr_data_fall <= {(APPDATA_WIDTH/2){1'b0}}; // 0x0
wr_state <= WR_SECOND_DATA;
end
WR_SECOND_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
wr_data_fall <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
wr_state <= WR_THIRD_DATA;
end
WR_THIRD_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
wr_data_fall <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
wr_state <= WR_FOURTH_DATA;
end
WR_FOURTH_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/8){4'b1001}}; // 0x9
wr_data_fall <= {(APPDATA_WIDTH/8){4'b0110}}; // 0x6
wr_state <= WR_IDLE_FIRST_DATA;
end
endcase
end
end
always @(posedge clk)
if (rst_r1)
wr_data_en_r <= 1'b0;
else
wr_data_en_r <= wr_data_en;
//*****************************************************************
// Read data logic
//*****************************************************************
// read comparison data generation
always @(posedge clk)
if (rst_r1) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/2){1'bx}};
rd_data_pat_fall <= {(APPDATA_WIDTH/2){1'bx}};
rd_state <= RD_IDLE_FIRST_DATA;
end else begin
case (rd_state)
RD_IDLE_FIRST_DATA:
if (rd_data_valid_r)
begin
rd_data_pat_rise <= {(APPDATA_WIDTH/2){1'b1}}; // 0xF
rd_data_pat_fall <= {(APPDATA_WIDTH/2){1'b0}}; // 0x0
rd_state <= RD_SECOND_DATA;
end
RD_SECOND_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
rd_data_pat_fall <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
rd_state <= RD_THIRD_DATA;
end
RD_THIRD_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
rd_data_pat_fall <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
rd_state <= RD_FOURTH_DATA;
end
RD_FOURTH_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/8){4'b1001}}; // 0x9
rd_data_pat_fall <= {(APPDATA_WIDTH/8){4'b0110}}; // 0x6
rd_state <= RD_IDLE_FIRST_DATA;
end
endcase
end
//data to the compare circuit during read
assign app_cmp_data = {rd_data_pat_fall, rd_data_pat_rise};
endmodule
|
module HaarFilter_tb ();
parameter STAGES = 8;
parameter INTERNAL_WIDTH = 18;
parameter IN_WIDTH = 16;
parameter OUT_WIDTH = 16;
reg clk; ///< System clock
reg rst; ///< Reset, synchronous and active high
reg en; ///< Enable (once per new sample)
reg signed [IN_WIDTH-1:0] dataIn; ///< Input samples
wire [STAGES:0] outStrobes; ///< Strobes for each output
wire [OUT_WIDTH*(STAGES+1)-1:0] dataOut; ///< Outputs from analysis filter
integer i;
integer j;
reg [OUT_WIDTH-1:0] results [STAGES:0];
always #1 clk = ~clk;
initial begin
clk = 1'b0;
rst = 1'b0;
en = 1'b0;
dataIn = 'd0;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b0;
@(posedge clk) rst = 1'b0;
@(posedge clk) en = 1'b0;
@(posedge clk) en = 1'b1; dataIn = 'd0;
@(posedge clk) en = 1'b0;
for (i=0; i<2**8; i=i+2) begin
@(posedge clk) en = 1'b1; dataIn = i;
@(posedge clk) en = 1'b0;
end
for (i=0; i<2**8; i=i+2) begin
@(posedge clk) en = 1'b1; dataIn = 2**8-i;
@(posedge clk) en = 1'b0;
end
for (i=0; i<2**8; i=i+2) begin
@(posedge clk) en = 1'b1; dataIn = -i;
@(posedge clk) en = 1'b0;
end
for (i=0; i<2**8; i=i+2) begin
@(posedge clk) en = 1'b1; dataIn = -(2**8)+i;
@(posedge clk) en = 1'b0;
end
for (i=0; i<2**20; i=i+1) begin
@(posedge clk) en = 1'b1; dataIn = $rtoi((2.0**(IN_WIDTH-1)-1)*$sin(3.141259*2.0*($itor(i)/2.0**15 + $itor(i)**2/2.0**23)));
@(posedge clk) en = 1'b0;
end
#1000 $stop;
end
always @(dataOut) begin
for (j=0; j<=STAGES; j=j+1) begin
results[j] = dataOut[(OUT_WIDTH*j)+:OUT_WIDTH];
end
end
HaarFilter #(
.STAGES(STAGES),
.INTERNAL_WIDTH(INTERNAL_WIDTH),
.IN_WIDTH(IN_WIDTH),
.OUT_WIDTH(OUT_WIDTH)
)
uut (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, synchronous and active high
.en(en), ///< Enable (once per new sample)
.dataIn(dataIn), ///< [IN_WIDTH-1:0] Input samples
.outStrobes(outStrobes), ///< [STAGES:0] Strobes for each output
.dataOut(dataOut) ///< [OUT_WIDTH*(STAGES+1)-1:0] Outputs from analysis filter
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_SYMBOL_V
`define SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_SYMBOL_V
/**
* sleep_pargate_plv: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sleep_pargate_plv (
//# {{power|Power}}
input SLEEP ,
output VIRTPWR
);
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_SYMBOL_V
|
`timescale 1ns / 1ps
/*
* Spartan3AN_PicoBlaze_Leds.v
*
* ___ _ _ _ _ ___ _ _ ___
* | __._ _ _| |_ ___ _| |_| |___ _| | . | \ |_ _|
* | _>| ' ' | . / ._/ . / . / ._/ . | | || |
* |___|_|_|_|___\___\___\___\___\___|_|_|_\_||_|
*
*
* Created on : 20/07/2015
* Author : Ernesto Andres Rincon Cruz
* Web : www.embeddedant.org
* Device : EP4CE22F17C6N
* Board : DEO-NANO
*
* Revision History:
* Rev 1.0.0 - (ErnestoARC) First release 19/06/2015.
*/
//////////////////////////////////////////////////////////////////////////////////
module PicoBlaze_OutReg
#(parameter LOCAL_PORT_ID = 8'h00)
(
clk,
reset,
port_id,
write_strobe,
out_port,
new_out_port);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
input wire clk;
input wire reset;
input wire [7:0] port_id;
input wire write_strobe;
input wire [7:0] out_port;
output reg [7:0] new_out_port;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg RegEnable=1;
//=======================================================
// Structural coding
//=======================================================
always @ (*)
begin
if (write_strobe == 1)
begin
case (port_id)
LOCAL_PORT_ID: RegEnable = 1;
default: RegEnable = 0;
endcase
end
else
RegEnable=0;
end
always @ (posedge clk, posedge reset)
begin
if(reset == 1)
new_out_port <= 8'h00;
else
begin
if(RegEnable == 1)
new_out_port <= out_port;
else
new_out_port <= new_out_port;
end
end
//=======================================================
// Connections & assigns
//=======================================================
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:40:46 05/12/2015
// Design Name:
// Module Name: ID_EX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ID_EX(
clk,rst,
id_a, id_b, id_td, id_d2, id_Aluc, id_WREG, id_WMEM, id_LW,id_instr,
ex_a, ex_b, ex_td, ex_d2, ex_Aluc, ex_WREG, ex_WMEM, ex_LW,ex_instr
);
input clk,rst;
input wire [31:0] id_a,id_b,id_d2,id_instr;
input wire [4:0] id_td,id_Aluc;
input wire id_WREG,id_WMEM,id_LW;
output reg [31:0] ex_a,ex_b,ex_d2,ex_instr;
output reg [4:0] ex_td,ex_Aluc;
output reg ex_WREG,ex_WMEM,ex_LW;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
ex_a <= 0;
ex_b <= 0;
ex_d2 <= 0;
ex_td <= 0;
ex_Aluc <= 0;
ex_WREG <= 0;
ex_WMEM <= 0;
ex_LW <= 0;
ex_instr<=32'b100000;
end
// else if(BJ)
// begin
// ex_a <= 0;
// ex_b <= 0;
// ex_d2 <= 0;
// ex_td <= 0;
// ex_Aluc <= 0;
// ex_WREG <= 0;
// ex_WMEM <= 0;
// ex_LW <= 0;
// ex_instr<=32'b100000;
// end
else
begin
ex_a <= id_a;
ex_b <= id_b;
ex_d2 <= id_d2;
ex_td <= id_td;
ex_Aluc <= id_Aluc;
ex_WREG <= id_WREG;
ex_WMEM <= id_WMEM;
ex_LW <= id_LW;
ex_instr<=id_instr;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__TAPVPWRVGND_BEHAVIORAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVPWRVGND_BEHAVIORAL_PP_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:17:24 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81,
n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95,
n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107,
n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118,
n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,
n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140,
n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151,
n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162,
n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173,
n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184,
n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206,
n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228,
n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239,
n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250,
n251, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261,
n262, n263, n264, n265, n266, n267, n268, n269, n270, n271, n272,
n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, n283,
n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, n294,
n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305,
n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316,
n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327,
n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338,
n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360,
n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371,
n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382,
n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393,
n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493;
AO21XLTS U95 ( .A0(n476), .A1(n444), .B0(n443), .Y(res[6]) );
NAND2X1TS U96 ( .A(n95), .B(n317), .Y(n318) );
NAND2X1TS U97 ( .A(n334), .B(n333), .Y(n335) );
NAND2X1TS U98 ( .A(n312), .B(n311), .Y(n313) );
NAND2X1TS U99 ( .A(n342), .B(n341), .Y(n343) );
NAND2X1TS U100 ( .A(n326), .B(n325), .Y(n327) );
NAND2X1TS U101 ( .A(n263), .B(n337), .Y(n264) );
NAND2X1TS U102 ( .A(n358), .B(n357), .Y(n359) );
NAND2X1TS U103 ( .A(n399), .B(n398), .Y(n400) );
NAND2XLTS U104 ( .A(n381), .B(n380), .Y(n383) );
NAND2XLTS U105 ( .A(n369), .B(n368), .Y(n370) );
NAND2XLTS U106 ( .A(n376), .B(n375), .Y(n377) );
NAND2X1TS U107 ( .A(n365), .B(n364), .Y(n366) );
NAND2X1TS U108 ( .A(n351), .B(n350), .Y(n352) );
NAND2XLTS U109 ( .A(n393), .B(n392), .Y(n394) );
NAND2XLTS U110 ( .A(n80), .B(n406), .Y(n407) );
NOR2X6TS U111 ( .A(n69), .B(n294), .Y(n304) );
OAI21X2TS U112 ( .A0(n382), .A1(n379), .B0(n380), .Y(n378) );
NAND2X1TS U113 ( .A(n329), .B(n334), .Y(n323) );
NAND2X2TS U114 ( .A(n300), .B(in1[31]), .Y(n303) );
NOR2X1TS U115 ( .A(n441), .B(in1[6]), .Y(n475) );
INVX2TS U116 ( .A(n320), .Y(n334) );
NOR2X2TS U117 ( .A(n293), .B(n316), .Y(n295) );
AOI2BB1X2TS U118 ( .A0N(n291), .A1N(n317), .B0(n290), .Y(n292) );
OAI21X1TS U119 ( .A0(n489), .A1(n435), .B0(n434), .Y(n470) );
OAI21X2TS U120 ( .A0(n333), .A1(n324), .B0(n325), .Y(n286) );
NAND2X2TS U121 ( .A(n289), .B(in1[30]), .Y(n311) );
NAND2XLTS U122 ( .A(n479), .B(in1[8]), .Y(n450) );
NOR2X1TS U123 ( .A(n297), .B(in2[30]), .Y(n298) );
NAND2X4TS U124 ( .A(n252), .B(in1[21]), .Y(n368) );
CLKMX2X2TS U125 ( .A(n271), .B(in2[29]), .S0(n276), .Y(n288) );
NOR2X4TS U126 ( .A(n235), .B(in1[19]), .Y(n379) );
NAND2X2TS U127 ( .A(n283), .B(in1[26]), .Y(n341) );
NAND2X2TS U128 ( .A(n253), .B(in1[22]), .Y(n364) );
NAND2X2TS U129 ( .A(n285), .B(in1[28]), .Y(n325) );
NOR2X1TS U130 ( .A(n447), .B(n446), .Y(n469) );
CLKMX2X4TS U131 ( .A(n277), .B(in2[28]), .S0(n276), .Y(n285) );
NOR2X4TS U132 ( .A(n356), .B(n349), .Y(n257) );
CLKMX2X4TS U133 ( .A(n230), .B(in2[19]), .S0(n276), .Y(n235) );
INVX2TS U134 ( .A(n402), .Y(n213) );
MXI2X2TS U135 ( .A(n234), .B(n239), .S0(n423), .Y(n236) );
NOR2X4TS U136 ( .A(n223), .B(in1[17]), .Y(n391) );
NAND2X6TS U137 ( .A(n81), .B(n80), .Y(n76) );
NAND2X2TS U138 ( .A(n209), .B(in1[14]), .Y(n406) );
NOR2X6TS U139 ( .A(n254), .B(in1[23]), .Y(n356) );
NAND2X2TS U140 ( .A(n223), .B(in1[17]), .Y(n392) );
XOR2X1TS U141 ( .A(n245), .B(in2[20]), .Y(n234) );
NAND2X2TS U142 ( .A(n212), .B(in1[15]), .Y(n402) );
CLKMX2X4TS U143 ( .A(n211), .B(in2[15]), .S0(n276), .Y(n212) );
NOR2X2TS U144 ( .A(n279), .B(n278), .Y(n280) );
NOR2X2TS U145 ( .A(n279), .B(in2[24]), .Y(n260) );
XNOR2X1TS U146 ( .A(n268), .B(in2[16]), .Y(n221) );
XNOR2X1TS U147 ( .A(n228), .B(in2[18]), .Y(n217) );
XOR2X2TS U148 ( .A(n279), .B(n266), .Y(n251) );
OR2X6TS U149 ( .A(n268), .B(n267), .Y(n279) );
NAND2X2TS U150 ( .A(n202), .B(in1[13]), .Y(n413) );
XOR2X1TS U151 ( .A(n428), .B(in2[3]), .Y(n429) );
INVX2TS U152 ( .A(n484), .Y(n455) );
NAND2X1TS U153 ( .A(in2[0]), .B(in1[0]), .Y(n422) );
NOR2X2TS U154 ( .A(n479), .B(in1[8]), .Y(n451) );
NAND2X2TS U155 ( .A(n266), .B(n265), .Y(n278) );
CLKINVX6TS U156 ( .A(n268), .Y(n233) );
NAND2X1TS U157 ( .A(n190), .B(n187), .Y(n456) );
INVX2TS U158 ( .A(in2[24]), .Y(n266) );
INVX2TS U159 ( .A(in2[25]), .Y(n265) );
NOR2X1TS U160 ( .A(in2[23]), .B(in2[22]), .Y(n248) );
NAND2X2TS U161 ( .A(n91), .B(n89), .Y(n484) );
NOR2X1TS U162 ( .A(n161), .B(in2[7]), .Y(n167) );
NOR2X2TS U163 ( .A(in2[21]), .B(in2[20]), .Y(n249) );
NOR2X1TS U164 ( .A(n431), .B(n139), .Y(n437) );
XNOR2X2TS U165 ( .A(n215), .B(in2[12]), .Y(n200) );
NAND2X1TS U166 ( .A(n190), .B(n92), .Y(n91) );
NOR4X2TS U167 ( .A(in2[9]), .B(n111), .C(in2[2]), .D(n109), .Y(n121) );
AOI21X1TS U168 ( .A0(n97), .A1(n181), .B0(n90), .Y(n89) );
NOR2X2TS U169 ( .A(in2[17]), .B(in2[16]), .Y(n232) );
NAND2X1TS U170 ( .A(n205), .B(n204), .Y(n214) );
NOR2X2TS U171 ( .A(n112), .B(n111), .Y(n118) );
BUFX3TS U172 ( .A(n438), .Y(n276) );
NAND4X1TS U173 ( .A(n110), .B(in2[9]), .C(n113), .D(n426), .Y(n112) );
OR2X2TS U174 ( .A(in2[5]), .B(n73), .Y(n135) );
INVX4TS U175 ( .A(in2[13]), .Y(n204) );
CLKINVX6TS U176 ( .A(n431), .Y(n164) );
NAND2X2TS U177 ( .A(add_sub), .B(in2[4]), .Y(n134) );
INVX12TS U178 ( .A(add_sub), .Y(n438) );
INVX2TS U179 ( .A(in2[6]), .Y(n439) );
INVX12TS U180 ( .A(n139), .Y(n157) );
NOR2X4TS U181 ( .A(in2[3]), .B(in2[2]), .Y(n85) );
INVX8TS U182 ( .A(in2[5]), .Y(n141) );
INVX12TS U183 ( .A(in2[4]), .Y(n142) );
NOR2XLTS U184 ( .A(in2[19]), .B(in2[18]), .Y(n231) );
OAI21XLTS U185 ( .A0(in2[6]), .A1(add_sub), .B0(in1[6]), .Y(n158) );
NOR2X6TS U186 ( .A(in2[9]), .B(in2[8]), .Y(n177) );
CLKINVX3TS U187 ( .A(in2[2]), .Y(n426) );
NAND3X2TS U188 ( .A(n439), .B(n142), .C(n141), .Y(n144) );
INVX2TS U189 ( .A(in2[12]), .Y(n205) );
BUFX8TS U190 ( .A(n438), .Y(n423) );
NAND2X1TS U191 ( .A(n181), .B(n180), .Y(n182) );
NAND2X1TS U192 ( .A(n441), .B(in1[6]), .Y(n474) );
NAND2X4TS U193 ( .A(n82), .B(n79), .Y(n75) );
AOI21X1TS U194 ( .A0(n330), .A1(n334), .B0(n321), .Y(n322) );
NAND2X1TS U195 ( .A(n94), .B(n388), .Y(n389) );
INVX8TS U196 ( .A(n296), .Y(n339) );
OR2X4TS U197 ( .A(n431), .B(n144), .Y(n161) );
NAND2X2TS U198 ( .A(n94), .B(n384), .Y(n227) );
NAND2X1TS U199 ( .A(n414), .B(n413), .Y(n415) );
NAND2X1TS U200 ( .A(n93), .B(n402), .Y(n403) );
INVX2TS U201 ( .A(in2[20]), .Y(n239) );
INVX2TS U202 ( .A(n355), .Y(n345) );
INVX2TS U203 ( .A(n315), .Y(n308) );
INVX2TS U204 ( .A(n388), .Y(n225) );
INVX4TS U205 ( .A(n291), .Y(n312) );
NOR2X4TS U206 ( .A(n320), .B(n324), .Y(n287) );
NOR2X4TS U207 ( .A(n262), .B(in1[25]), .Y(n338) );
NOR2X6TS U208 ( .A(n285), .B(in1[28]), .Y(n324) );
NOR2X4TS U209 ( .A(n284), .B(in1[27]), .Y(n320) );
MXI2X4TS U210 ( .A(n217), .B(n216), .S0(n423), .Y(n224) );
NOR2X4TS U211 ( .A(n255), .B(in1[24]), .Y(n349) );
NAND2X4TS U212 ( .A(n233), .B(n232), .Y(n228) );
NAND3X2TS U213 ( .A(n164), .B(in2[5]), .C(n142), .Y(n126) );
NAND2X4TS U214 ( .A(n355), .B(n257), .Y(n259) );
NAND2X4TS U215 ( .A(n287), .B(n329), .Y(n316) );
NOR2X4TS U216 ( .A(n379), .B(n374), .Y(n238) );
NAND2X4TS U217 ( .A(n312), .B(n95), .Y(n293) );
NOR2X4TS U218 ( .A(n300), .B(in1[31]), .Y(n305) );
NAND2X4TS U219 ( .A(n254), .B(in1[23]), .Y(n357) );
NOR2X6TS U220 ( .A(n253), .B(in1[22]), .Y(n363) );
NOR2X6TS U221 ( .A(n252), .B(in1[21]), .Y(n361) );
NOR2X6TS U222 ( .A(n338), .B(n340), .Y(n329) );
NOR2X6TS U223 ( .A(n78), .B(n196), .Y(n82) );
NOR2X4TS U224 ( .A(n236), .B(in1[20]), .Y(n374) );
NOR2X4TS U225 ( .A(n391), .B(n397), .Y(n384) );
MXI2X4TS U226 ( .A(n243), .B(n244), .S0(n423), .Y(n253) );
MX2X4TS U227 ( .A(n241), .B(in2[21]), .S0(n276), .Y(n252) );
NOR2X4TS U228 ( .A(n289), .B(in1[30]), .Y(n291) );
NAND2X4TS U229 ( .A(n262), .B(in1[25]), .Y(n337) );
NAND2X4TS U230 ( .A(n284), .B(in1[27]), .Y(n333) );
XOR2X2TS U231 ( .A(n240), .B(in2[21]), .Y(n241) );
INVX2TS U232 ( .A(n473), .Y(n453) );
NAND2X4TS U233 ( .A(n288), .B(in1[29]), .Y(n317) );
INVX2TS U234 ( .A(n397), .Y(n399) );
NAND2X2TS U235 ( .A(n245), .B(n239), .Y(n240) );
OR2X4TS U236 ( .A(n212), .B(in1[15]), .Y(n93) );
NOR2X4TS U237 ( .A(n222), .B(in1[16]), .Y(n397) );
NAND2X4TS U238 ( .A(n222), .B(in1[16]), .Y(n398) );
NAND2X2TS U239 ( .A(n245), .B(n249), .Y(n242) );
NOR2X2TS U240 ( .A(n228), .B(in2[18]), .Y(n229) );
NOR3X4TS U241 ( .A(n279), .B(in2[26]), .C(n278), .Y(n272) );
NAND2X4TS U242 ( .A(n201), .B(in1[12]), .Y(n417) );
NOR2X4TS U243 ( .A(n201), .B(in1[12]), .Y(n410) );
NAND2X6TS U244 ( .A(n168), .B(n96), .Y(n448) );
XOR2X2TS U245 ( .A(n206), .B(in2[14]), .Y(n208) );
NOR2X4TS U246 ( .A(n140), .B(n437), .Y(n446) );
AND2X4TS U247 ( .A(n187), .B(n184), .Y(n185) );
AND2X4TS U248 ( .A(n232), .B(n231), .Y(n250) );
NAND2X2TS U249 ( .A(n100), .B(n426), .Y(n104) );
INVX4TS U250 ( .A(n177), .Y(n179) );
INVX4TS U251 ( .A(n373), .Y(n382) );
NOR2X1TS U252 ( .A(n345), .B(n356), .Y(n348) );
NAND3X6TS U253 ( .A(n76), .B(n75), .C(n406), .Y(n404) );
XOR2X1TS U254 ( .A(n408), .B(n407), .Y(res[14]) );
XOR2X1TS U255 ( .A(n486), .B(n485), .Y(res[10]) );
XOR2X1TS U256 ( .A(n416), .B(n415), .Y(res[13]) );
NAND2X6TS U257 ( .A(n77), .B(n70), .Y(n81) );
INVX2TS U258 ( .A(n385), .Y(n386) );
NAND2X4TS U259 ( .A(n235), .B(in1[19]), .Y(n380) );
OR2X6TS U260 ( .A(n224), .B(in1[18]), .Y(n94) );
MX2X4TS U261 ( .A(n247), .B(in2[23]), .S0(n276), .Y(n254) );
INVX2TS U262 ( .A(n317), .Y(n307) );
NAND2X2TS U263 ( .A(n236), .B(in1[20]), .Y(n375) );
NAND2X4TS U264 ( .A(n224), .B(in1[18]), .Y(n388) );
NAND2X2TS U265 ( .A(n255), .B(in1[24]), .Y(n350) );
OR2X6TS U266 ( .A(n288), .B(in1[29]), .Y(n95) );
MX2X4TS U267 ( .A(n269), .B(in2[30]), .S0(n276), .Y(n289) );
XOR2X1TS U268 ( .A(n473), .B(n472), .Y(res[9]) );
MX2X4TS U269 ( .A(n273), .B(in2[27]), .S0(n276), .Y(n284) );
MXI2X1TS U270 ( .A(n482), .B(n481), .S0(n480), .Y(res[8]) );
XNOR2X2TS U271 ( .A(n272), .B(in2[27]), .Y(n273) );
XNOR2X2TS U272 ( .A(n275), .B(in2[28]), .Y(n277) );
XOR2X2TS U273 ( .A(n297), .B(in2[30]), .Y(n269) );
MXI2X4TS U274 ( .A(n208), .B(n207), .S0(n423), .Y(n209) );
XNOR2X2TS U275 ( .A(n218), .B(in2[17]), .Y(n219) );
NAND2BX2TS U276 ( .AN(in2[29]), .B(n270), .Y(n297) );
OAI21X1TS U277 ( .A0(n476), .A1(n475), .B0(n474), .Y(n478) );
XOR2X1TS U278 ( .A(n470), .B(n469), .Y(res[5]) );
NOR2X4TS U279 ( .A(n489), .B(n488), .Y(n487) );
XOR2XLTS U280 ( .A(n468), .B(n467), .Y(res[3]) );
XOR2X1TS U281 ( .A(n441), .B(in1[6]), .Y(n444) );
NAND3X2TS U282 ( .A(n138), .B(in1[5]), .C(n137), .Y(n140) );
XOR2XLTS U283 ( .A(n464), .B(n463), .Y(res[2]) );
NOR2BX2TS U284 ( .AN(n116), .B(n115), .Y(n117) );
NOR2X6TS U285 ( .A(n179), .B(in2[10]), .Y(n187) );
NAND2BX1TS U286 ( .AN(n491), .B(n490), .Y(n492) );
OR3X2TS U287 ( .A(n278), .B(in2[27]), .C(in2[26]), .Y(n274) );
NAND3X2TS U288 ( .A(n250), .B(n249), .C(n248), .Y(n267) );
NAND2BX1TS U289 ( .AN(in1[1]), .B(n422), .Y(n490) );
NOR2X1TS U290 ( .A(n73), .B(in1[7]), .Y(n160) );
INVX2TS U291 ( .A(in2[9]), .Y(n114) );
INVX4TS U292 ( .A(n72), .Y(n68) );
XOR2XLTS U293 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
XNOR2X2TS U294 ( .A(n328), .B(n327), .Y(res[28]) );
NOR2X2TS U295 ( .A(n146), .B(n145), .Y(n147) );
NAND2X2TS U296 ( .A(n301), .B(n303), .Y(n302) );
MX2X4TS U297 ( .A(n299), .B(in2[31]), .S0(n438), .Y(n300) );
XNOR2X2TS U298 ( .A(n319), .B(n318), .Y(res[29]) );
XNOR2X2TS U299 ( .A(n314), .B(n313), .Y(res[30]) );
MXI2X8TS U300 ( .A(n199), .B(n204), .S0(n423), .Y(n202) );
AOI21X2TS U301 ( .A0(n486), .A1(n483), .B0(n455), .Y(n460) );
AOI211X4TS U302 ( .A0(n149), .A1(n431), .B0(n148), .C0(n147), .Y(n477) );
OAI21X2TS U303 ( .A0(n305), .A1(n304), .B0(n303), .Y(res[32]) );
XNOR2X1TS U304 ( .A(n378), .B(n377), .Y(res[20]) );
AND2X8TS U305 ( .A(n250), .B(n233), .Y(n245) );
AOI211X4TS U306 ( .A0(n132), .A1(n128), .B0(n127), .C0(in1[5]), .Y(n447) );
NAND2X6TS U307 ( .A(n141), .B(n142), .Y(n139) );
INVX16TS U308 ( .A(n181), .Y(n190) );
XOR2X1TS U309 ( .A(n383), .B(n382), .Y(res[19]) );
NOR2X8TS U310 ( .A(n361), .B(n363), .Y(n355) );
MXI2X4TS U311 ( .A(n266), .B(n251), .S0(add_sub), .Y(n255) );
NAND2X6TS U312 ( .A(n84), .B(n83), .Y(n371) );
NAND2X4TS U313 ( .A(n372), .B(n238), .Y(n84) );
NOR2X6TS U314 ( .A(in2[7]), .B(in2[6]), .Y(n103) );
NAND2X8TS U315 ( .A(n157), .B(n103), .Y(n111) );
OR4X8TS U316 ( .A(n215), .B(in2[15]), .C(in2[14]), .D(n214), .Y(n268) );
NAND2X2TS U317 ( .A(n110), .B(n103), .Y(n102) );
INVX2TS U318 ( .A(in2[8]), .Y(n99) );
AND2X2TS U319 ( .A(n484), .B(n176), .Y(n194) );
NOR2XLTS U320 ( .A(n72), .B(in2[6]), .Y(n150) );
NAND2BX1TS U321 ( .AN(n445), .B(in1[4]), .Y(n434) );
CLKAND2X2TS U322 ( .A(n445), .B(n433), .Y(n435) );
NAND3X4TS U323 ( .A(n197), .B(n448), .C(n203), .Y(n77) );
NAND2X1TS U324 ( .A(add_sub), .B(in2[6]), .Y(n163) );
NOR2X4TS U325 ( .A(n215), .B(in2[12]), .Y(n198) );
XNOR2X1TS U326 ( .A(in2[1]), .B(in2[0]), .Y(n420) );
NOR2BX2TS U327 ( .AN(in1[3]), .B(n430), .Y(n465) );
INVX2TS U328 ( .A(n447), .Y(n436) );
XNOR2X1TS U329 ( .A(in2[9]), .B(add_sub), .Y(n120) );
NOR2X2TS U330 ( .A(n118), .B(n117), .Y(n119) );
AND2X2TS U331 ( .A(n177), .B(in2[10]), .Y(n92) );
XOR2X1TS U332 ( .A(n456), .B(in2[11]), .Y(n457) );
INVX2TS U333 ( .A(n410), .Y(n418) );
INVX2TS U334 ( .A(n417), .Y(n411) );
INVX2TS U335 ( .A(n405), .Y(n79) );
INVX2TS U336 ( .A(n333), .Y(n321) );
INVX2TS U337 ( .A(n316), .Y(n306) );
NOR2X2TS U338 ( .A(in2[0]), .B(in2[8]), .Y(n113) );
INVX2TS U339 ( .A(n471), .Y(n174) );
NAND3X1TS U340 ( .A(n479), .B(in1[8]), .C(in1[9]), .Y(n173) );
NAND3X1TS U341 ( .A(n124), .B(n123), .C(n122), .Y(n176) );
NAND2X1TS U342 ( .A(n73), .B(in2[11]), .Y(n124) );
NOR4X2TS U343 ( .A(n268), .B(in2[28]), .C(n267), .D(n274), .Y(n270) );
INVX2TS U344 ( .A(n259), .Y(n87) );
OAI21X1TS U345 ( .A0(n357), .A1(n349), .B0(n350), .Y(n256) );
INVX2TS U346 ( .A(n144), .Y(n145) );
XNOR2X1TS U347 ( .A(in2[7]), .B(in1[7]), .Y(n143) );
OAI21X1TS U348 ( .A0(n164), .A1(n135), .B0(n126), .Y(n127) );
INVX2TS U349 ( .A(in2[0]), .Y(n100) );
AND2X2TS U350 ( .A(n157), .B(n103), .Y(n106) );
NOR2X4TS U351 ( .A(in2[1]), .B(in2[3]), .Y(n110) );
OAI21X1TS U352 ( .A0(n98), .A1(n177), .B0(n71), .Y(n90) );
NOR2X4TS U353 ( .A(n412), .B(n410), .Y(n203) );
XNOR2X1TS U354 ( .A(n229), .B(in2[19]), .Y(n230) );
INVX2TS U355 ( .A(n311), .Y(n290) );
CLKXOR2X2TS U356 ( .A(n445), .B(in1[4]), .Y(n488) );
CLKBUFX2TS U357 ( .A(n372), .Y(n373) );
INVX2TS U358 ( .A(n361), .Y(n369) );
INVX2TS U359 ( .A(n368), .Y(n362) );
OAI21X1TS U360 ( .A0(n346), .A1(n356), .B0(n357), .Y(n347) );
INVX2TS U361 ( .A(n237), .Y(n83) );
NAND2BX1TS U362 ( .AN(n462), .B(n461), .Y(n464) );
NOR2BX1TS U363 ( .AN(n466), .B(n465), .Y(n468) );
XNOR2X1TS U364 ( .A(n479), .B(in1[8]), .Y(n481) );
XOR2X1TS U365 ( .A(n471), .B(in1[9]), .Y(n472) );
NAND2X1TS U366 ( .A(n484), .B(n483), .Y(n485) );
XOR2X1TS U367 ( .A(n460), .B(n459), .Y(res[11]) );
NAND2X1TS U368 ( .A(n418), .B(n417), .Y(n419) );
AOI21X1TS U369 ( .A0(n409), .A1(n418), .B0(n411), .Y(n416) );
INVX2TS U370 ( .A(n412), .Y(n414) );
NOR2XLTS U371 ( .A(n81), .B(n82), .Y(n408) );
OAI21XLTS U372 ( .A0(n397), .A1(n396), .B0(n398), .Y(n395) );
INVX2TS U373 ( .A(n391), .Y(n393) );
OAI21XLTS U374 ( .A0(n387), .A1(n396), .B0(n386), .Y(n390) );
INVX2TS U375 ( .A(n384), .Y(n387) );
INVX2TS U376 ( .A(n379), .Y(n381) );
INVX2TS U377 ( .A(n374), .Y(n376) );
XNOR2X1TS U378 ( .A(n371), .B(n370), .Y(res[21]) );
XOR2X1TS U379 ( .A(n367), .B(n366), .Y(res[22]) );
AOI21X2TS U380 ( .A0(n371), .A1(n369), .B0(n362), .Y(n367) );
INVX2TS U381 ( .A(n363), .Y(n365) );
XOR2X1TS U382 ( .A(n360), .B(n359), .Y(res[23]) );
AOI21X2TS U383 ( .A0(n371), .A1(n355), .B0(n354), .Y(n360) );
INVX2TS U384 ( .A(n356), .Y(n358) );
XOR2X1TS U385 ( .A(n353), .B(n352), .Y(res[24]) );
AOI21X2TS U386 ( .A0(n371), .A1(n348), .B0(n347), .Y(n353) );
INVX2TS U387 ( .A(n349), .Y(n351) );
XOR2X1TS U388 ( .A(n339), .B(n264), .Y(res[25]) );
INVX2TS U389 ( .A(n338), .Y(n263) );
XNOR2X2TS U390 ( .A(n344), .B(n343), .Y(res[26]) );
INVX2TS U391 ( .A(n340), .Y(n342) );
XNOR2X2TS U392 ( .A(n336), .B(n335), .Y(res[27]) );
INVX2TS U393 ( .A(n329), .Y(n332) );
INVX2TS U394 ( .A(n324), .Y(n326) );
NAND2X1TS U395 ( .A(n306), .B(n95), .Y(n310) );
INVX2TS U396 ( .A(n305), .Y(n301) );
CLKINVX3TS U397 ( .A(n72), .Y(n74) );
INVX4TS U398 ( .A(add_sub), .Y(n72) );
AND2X4TS U399 ( .A(n296), .B(n295), .Y(n69) );
OA21X2TS U400 ( .A0(n412), .A1(n417), .B0(n413), .Y(n70) );
AOI21X1TS U401 ( .A0(n438), .A1(in2[10]), .B0(in1[10]), .Y(n71) );
NOR2X4TS U402 ( .A(n209), .B(in1[14]), .Y(n405) );
INVX2TS U403 ( .A(n405), .Y(n80) );
XOR2X1TS U404 ( .A(in2[8]), .B(add_sub), .Y(n101) );
NAND2X2TS U405 ( .A(n114), .B(n74), .Y(n115) );
NOR3X4TS U406 ( .A(n455), .B(n451), .C(n125), .Y(n197) );
NAND3X4TS U407 ( .A(n372), .B(n87), .C(n238), .Y(n86) );
INVX2TS U408 ( .A(add_sub), .Y(n73) );
OAI21X2TS U409 ( .A0(n192), .A1(n483), .B0(n191), .Y(n193) );
NOR2X2TS U410 ( .A(n215), .B(n214), .Y(n206) );
NAND4X2TS U411 ( .A(n106), .B(in2[8]), .C(n105), .D(n110), .Y(n107) );
AOI21X4TS U412 ( .A0(n404), .A1(n93), .B0(n213), .Y(n396) );
INVX2TS U413 ( .A(n203), .Y(n78) );
OAI2BB1X1TS U414 ( .A0N(n448), .A1N(n197), .B0(n196), .Y(n409) );
NAND2X8TS U415 ( .A(n427), .B(n85), .Y(n431) );
NOR2X8TS U416 ( .A(in2[1]), .B(in2[0]), .Y(n427) );
XOR2X4TS U417 ( .A(n304), .B(n302), .Y(res[31]) );
NAND3X8TS U418 ( .A(n88), .B(n86), .C(n258), .Y(n296) );
NAND2BX4TS U419 ( .AN(n259), .B(n237), .Y(n88) );
OAI21X4TS U420 ( .A0(n467), .A1(n465), .B0(n466), .Y(n489) );
AOI21X4TS U421 ( .A0(n463), .A1(n461), .B0(n462), .Y(n467) );
NOR2X6TS U422 ( .A(n477), .B(n151), .Y(n449) );
OAI21X4TS U423 ( .A0(n121), .A1(n120), .B0(n119), .Y(n471) );
OAI21X2TS U424 ( .A0(n315), .A1(n293), .B0(n292), .Y(n294) );
XNOR2X4TS U425 ( .A(n242), .B(in2[22]), .Y(n243) );
NOR2X4TS U426 ( .A(n279), .B(n274), .Y(n275) );
XOR2X4TS U427 ( .A(n280), .B(in2[26]), .Y(n282) );
XOR2X4TS U428 ( .A(n260), .B(in2[25]), .Y(n261) );
NOR2X4TS U429 ( .A(in2[16]), .B(n268), .Y(n218) );
AOI31X4TS U430 ( .A0(n449), .A1(n487), .A2(n469), .B0(n448), .Y(n480) );
CLKINVX1TS U431 ( .A(n396), .Y(n401) );
MXI2X4TS U432 ( .A(n221), .B(n220), .S0(n423), .Y(n222) );
OA21X4TS U433 ( .A0(n167), .A1(n166), .B0(n165), .Y(n96) );
NOR2X6TS U434 ( .A(n283), .B(in1[26]), .Y(n340) );
NOR2BX1TS U435 ( .AN(in1[1]), .B(n422), .Y(n491) );
MXI2X1TS U436 ( .A(in2[11]), .B(n457), .S0(n74), .Y(n458) );
XNOR2X1TS U437 ( .A(n390), .B(n389), .Y(res[18]) );
OR2X8TS U438 ( .A(n111), .B(n431), .Y(n181) );
NOR2X2TS U439 ( .A(n438), .B(in2[10]), .Y(n97) );
INVX2TS U440 ( .A(n97), .Y(n98) );
NAND2X2TS U441 ( .A(n99), .B(n74), .Y(n171) );
OAI31X2TS U442 ( .A0(n102), .A1(in2[8]), .A2(n104), .B0(n101), .Y(n108) );
INVX2TS U443 ( .A(n104), .Y(n105) );
OAI211X4TS U444 ( .A0(n157), .A1(n171), .B0(n108), .C0(n107), .Y(n479) );
INVX2TS U445 ( .A(n110), .Y(n109) );
INVX2TS U446 ( .A(n113), .Y(n116) );
INVX2TS U447 ( .A(in2[11]), .Y(n184) );
NAND2X1TS U448 ( .A(n184), .B(n68), .Y(n123) );
INVX2TS U449 ( .A(in1[11]), .Y(n122) );
OAI21X2TS U450 ( .A0(n471), .A1(in1[9]), .B0(n176), .Y(n125) );
NAND2X4TS U451 ( .A(n74), .B(in2[5]), .Y(n132) );
NAND2X1TS U452 ( .A(n134), .B(n141), .Y(n128) );
INVX2TS U453 ( .A(n134), .Y(n129) );
NAND2X1TS U454 ( .A(n431), .B(n129), .Y(n130) );
OAI211X1TS U455 ( .A0(in2[4]), .A1(n68), .B0(n130), .C0(in1[4]), .Y(n131) );
AOI211X2TS U456 ( .A0(n142), .A1(n164), .B0(n447), .C0(n131), .Y(n152) );
INVX2TS U457 ( .A(n132), .Y(n133) );
NAND2X1TS U458 ( .A(n431), .B(n133), .Y(n138) );
NAND2X1TS U459 ( .A(n134), .B(in2[5]), .Y(n136) );
NAND2X1TS U460 ( .A(n136), .B(n135), .Y(n137) );
NAND2X2TS U461 ( .A(n143), .B(n68), .Y(n146) );
INVX2TS U462 ( .A(n146), .Y(n149) );
AOI21X1TS U463 ( .A0(n161), .A1(n68), .B0(n143), .Y(n148) );
AOI211X1TS U464 ( .A0(in2[6]), .A1(n276), .B0(n150), .C0(in1[6]), .Y(n151)
);
OAI21X4TS U465 ( .A0(n152), .A1(n446), .B0(n449), .Y(n168) );
INVX2TS U466 ( .A(n161), .Y(n155) );
NAND2X1TS U467 ( .A(n68), .B(in2[7]), .Y(n154) );
INVX2TS U468 ( .A(in2[7]), .Y(n153) );
NAND2X1TS U469 ( .A(n153), .B(n438), .Y(n156) );
OAI211X1TS U470 ( .A0(n155), .A1(n154), .B0(in1[7]), .C0(n156), .Y(n166) );
OAI22X1TS U471 ( .A0(n157), .A1(n163), .B0(n156), .B1(in1[7]), .Y(n159) );
AOI211X1TS U472 ( .A0(in2[7]), .A1(n160), .B0(n159), .C0(n158), .Y(n162) );
OAI211X1TS U473 ( .A0(n164), .A1(n163), .B0(n162), .C0(n161), .Y(n165) );
INVX2TS U474 ( .A(in1[8]), .Y(n170) );
AOI31X1TS U475 ( .A0(n73), .A1(in2[8]), .A2(in1[8]), .B0(in1[9]), .Y(n169)
);
OAI31X1TS U476 ( .A0(n190), .A1(n171), .A2(n170), .B0(n169), .Y(n172) );
AOI31X1TS U477 ( .A0(n190), .A1(in2[8]), .A2(in1[8]), .B0(n172), .Y(n175) );
OAI21X2TS U478 ( .A0(n175), .A1(n174), .B0(n173), .Y(n195) );
INVX2TS U479 ( .A(n176), .Y(n192) );
AND2X4TS U480 ( .A(in2[10]), .B(n68), .Y(n180) );
OAI21X1TS U481 ( .A0(in2[10]), .A1(n74), .B0(in1[10]), .Y(n178) );
AOI21X1TS U482 ( .A0(n179), .A1(n180), .B0(n178), .Y(n183) );
NAND3X2TS U483 ( .A(n456), .B(n183), .C(n182), .Y(n483) );
NAND2X1TS U484 ( .A(add_sub), .B(in2[11]), .Y(n189) );
NAND2X8TS U485 ( .A(n190), .B(n185), .Y(n215) );
OAI21X1TS U486 ( .A0(n68), .A1(in2[11]), .B0(in1[11]), .Y(n186) );
AOI2BB1X1TS U487 ( .A0N(n187), .A1N(n189), .B0(n186), .Y(n188) );
OAI211X1TS U488 ( .A0(n190), .A1(n189), .B0(n215), .C0(n188), .Y(n191) );
AOI21X4TS U489 ( .A0(n195), .A1(n194), .B0(n193), .Y(n196) );
XNOR2X4TS U490 ( .A(n198), .B(n204), .Y(n199) );
NOR2X8TS U491 ( .A(n202), .B(in1[13]), .Y(n412) );
MXI2X4TS U492 ( .A(n200), .B(n205), .S0(n423), .Y(n201) );
INVX2TS U493 ( .A(in2[14]), .Y(n207) );
NOR3X1TS U494 ( .A(n215), .B(in2[14]), .C(n214), .Y(n210) );
XNOR2X1TS U495 ( .A(n210), .B(in2[15]), .Y(n211) );
INVX2TS U496 ( .A(in2[18]), .Y(n216) );
MX2X4TS U497 ( .A(n219), .B(in2[17]), .S0(n276), .Y(n223) );
INVX2TS U498 ( .A(in2[16]), .Y(n220) );
OAI21X4TS U499 ( .A0(n391), .A1(n398), .B0(n392), .Y(n385) );
AOI21X4TS U500 ( .A0(n94), .A1(n385), .B0(n225), .Y(n226) );
OAI21X4TS U501 ( .A0(n396), .A1(n227), .B0(n226), .Y(n372) );
OAI21X4TS U502 ( .A0(n380), .A1(n374), .B0(n375), .Y(n237) );
INVX2TS U503 ( .A(in2[22]), .Y(n244) );
NAND3X4TS U504 ( .A(n245), .B(n249), .C(n244), .Y(n246) );
XOR2X4TS U505 ( .A(n246), .B(in2[23]), .Y(n247) );
OAI21X4TS U506 ( .A0(n368), .A1(n363), .B0(n364), .Y(n354) );
AOI21X4TS U507 ( .A0(n257), .A1(n354), .B0(n256), .Y(n258) );
MXI2X4TS U508 ( .A(n261), .B(n265), .S0(n423), .Y(n262) );
XNOR2X1TS U509 ( .A(n270), .B(in2[29]), .Y(n271) );
INVX2TS U510 ( .A(in2[26]), .Y(n281) );
MXI2X4TS U511 ( .A(n282), .B(n281), .S0(n423), .Y(n283) );
OAI21X4TS U512 ( .A0(n340), .A1(n337), .B0(n341), .Y(n330) );
AOI21X4TS U513 ( .A0(n330), .A1(n287), .B0(n286), .Y(n315) );
XNOR2X1TS U514 ( .A(n298), .B(in2[31]), .Y(n299) );
AOI21X4TS U515 ( .A0(n308), .A1(n95), .B0(n307), .Y(n309) );
OAI21X4TS U516 ( .A0(n339), .A1(n310), .B0(n309), .Y(n314) );
OAI21X4TS U517 ( .A0(n339), .A1(n316), .B0(n315), .Y(n319) );
OAI21X4TS U518 ( .A0(n339), .A1(n323), .B0(n322), .Y(n328) );
INVX2TS U519 ( .A(n330), .Y(n331) );
OAI21X4TS U520 ( .A0(n339), .A1(n332), .B0(n331), .Y(n336) );
OAI21X4TS U521 ( .A0(n339), .A1(n338), .B0(n337), .Y(n344) );
INVX2TS U522 ( .A(n354), .Y(n346) );
XNOR2X1TS U523 ( .A(n395), .B(n394), .Y(res[17]) );
XNOR2X1TS U524 ( .A(n401), .B(n400), .Y(res[16]) );
XNOR2X1TS U525 ( .A(n404), .B(n403), .Y(res[15]) );
XNOR2X1TS U526 ( .A(n409), .B(n419), .Y(res[12]) );
INVX2TS U527 ( .A(in2[1]), .Y(n421) );
MXI2X2TS U528 ( .A(n421), .B(n420), .S0(n68), .Y(n493) );
OAI21X2TS U529 ( .A0(n493), .A1(n491), .B0(n490), .Y(n463) );
XOR2X1TS U530 ( .A(in2[2]), .B(n427), .Y(n424) );
MXI2X2TS U531 ( .A(n424), .B(n426), .S0(n423), .Y(n425) );
NAND2X2TS U532 ( .A(n425), .B(in1[2]), .Y(n461) );
NOR2X2TS U533 ( .A(n425), .B(in1[2]), .Y(n462) );
NAND2X1TS U534 ( .A(n427), .B(n426), .Y(n428) );
MXI2X2TS U535 ( .A(n429), .B(in2[3]), .S0(n438), .Y(n430) );
NAND2BX2TS U536 ( .AN(in1[3]), .B(n430), .Y(n466) );
XOR2X1TS U537 ( .A(n431), .B(in2[4]), .Y(n432) );
MXI2X2TS U538 ( .A(n432), .B(in2[4]), .S0(n438), .Y(n445) );
INVX2TS U539 ( .A(in1[4]), .Y(n433) );
OAI21X2TS U540 ( .A0(n470), .A1(n446), .B0(n436), .Y(n476) );
XNOR2X1TS U541 ( .A(n437), .B(n439), .Y(n440) );
MXI2X2TS U542 ( .A(n440), .B(n439), .S0(n438), .Y(n441) );
INVX2TS U543 ( .A(n475), .Y(n442) );
AOI21X1TS U544 ( .A0(n474), .A1(n442), .B0(n476), .Y(n443) );
OAI21X4TS U545 ( .A0(n480), .A1(n451), .B0(n450), .Y(n473) );
INVX2TS U546 ( .A(in1[9]), .Y(n452) );
NAND2X2TS U547 ( .A(n453), .B(n452), .Y(n454) );
AOI22X2TS U548 ( .A0(n473), .A1(in1[9]), .B0(n471), .B1(n454), .Y(n486) );
XNOR2X1TS U549 ( .A(n458), .B(in1[11]), .Y(n459) );
XNOR2X1TS U550 ( .A(n478), .B(n477), .Y(res[7]) );
INVX2TS U551 ( .A(n481), .Y(n482) );
AOI21X1TS U552 ( .A0(n489), .A1(n488), .B0(n487), .Y(res[4]) );
XNOR2X1TS U553 ( .A(n493), .B(n492), .Y(res[1]) );
initial $sdf_annotate("Approx_adder_GDAN16M4P8_syn.sdf");
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
sys_clk,
sys_resetn,
// ddr3
ddr3_a,
ddr3_ba,
ddr3_clk_p,
ddr3_clk_n,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_ras_n,
ddr3_cas_n,
ddr3_we_n,
ddr3_reset_n,
ddr3_dq,
ddr3_dqs_p,
ddr3_dqs_n,
ddr3_odt,
ddr3_rzq,
// ethernet
eth_rx_clk,
eth_rx_data,
eth_rx_cntrl,
eth_tx_clk_out,
eth_tx_data,
eth_tx_cntrl,
eth_mdc,
eth_mdio_i,
eth_mdio_o,
eth_mdio_t,
eth_phy_resetn,
// board gpio
led_grn,
led_red,
push_buttons,
dip_switches,
// lane interface
ref_clk,
rx_data,
rx_sync,
rx_sysref,
// spi
spi_csn,
spi_clk,
spi_sdio);
// clock and resets
input sys_clk;
input sys_resetn;
// ddr3
output [ 13:0] ddr3_a;
output [ 2:0] ddr3_ba;
output ddr3_clk_p;
output ddr3_clk_n;
output ddr3_cke;
output ddr3_cs_n;
output [ 7:0] ddr3_dm;
output ddr3_ras_n;
output ddr3_cas_n;
output ddr3_we_n;
output ddr3_reset_n;
inout [ 63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_p;
inout [ 7:0] ddr3_dqs_n;
output ddr3_odt;
input ddr3_rzq;
// ethernet
input eth_rx_clk;
input [ 3:0] eth_rx_data;
input eth_rx_cntrl;
output eth_tx_clk_out;
output [ 3:0] eth_tx_data;
output eth_tx_cntrl;
output eth_mdc;
input eth_mdio_i;
output eth_mdio_o;
output eth_mdio_t;
output eth_phy_resetn;
// board gpio
output [ 7:0] led_grn;
output [ 7:0] led_red;
input [ 2:0] push_buttons;
input [ 7:0] dip_switches;
// lane interface
input ref_clk;
input [ 3:0] rx_data;
output rx_sync;
output rx_sysref;
// spi
output spi_csn;
output spi_clk;
inout spi_sdio;
// internal registers
reg rx_sysref_m1 = 'd0;
reg rx_sysref_m2 = 'd0;
reg rx_sysref_m3 = 'd0;
reg rx_sysref = 'd0;
reg [ 3:0] phy_rst_cnt = 0;
reg phy_rst_reg = 0;
// internal clocks and resets
wire sys_125m_clk;
wire sys_25m_clk;
wire sys_2m5_clk;
wire eth_tx_clk;
wire rx_clk;
// internal signals
wire sys_pll_locked_s;
wire eth_tx_reset_s;
wire eth_tx_mode_1g_s;
wire eth_tx_mode_10m_100m_n_s;
wire spi_mosi;
wire spi_miso;
wire [ 3:0] rx_ip_sof_s;
wire [127:0] rx_ip_data_s;
wire [127:0] rx_data_s;
wire rx_sw_rstn_s;
wire rx_sysref_s;
wire rx_err_s;
wire rx_ready_s;
wire [ 3:0] rx_rst_state_s;
wire rx_lane_aligned_s;
wire [ 3:0] rx_analog_reset_s;
wire [ 3:0] rx_digital_reset_s;
wire [ 3:0] rx_cdr_locked_s;
wire [ 3:0] rx_cal_busy_s;
wire rx_pll_locked_s;
wire [ 15:0] rx_xcvr_status_s;
// ethernet transmit clock
assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk :
(eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk;
assign eth_phy_resetn = phy_rst_reg;
always@ (posedge eth_mdc) begin
phy_rst_cnt <= phy_rst_cnt + 4'd1;
if (phy_rst_cnt == 4'h0) begin
phy_rst_reg <= sys_pll_locked_s;
end
end
altddio_out #(.width(1)) i_eth_tx_clk_out (
.aset (1'b0),
.sset (1'b0),
.sclr (1'b0),
.oe (1'b1),
.oe_out (),
.datain_h (1'b1),
.datain_l (1'b0),
.outclocken (1'b1),
.aclr (eth_tx_reset_s),
.outclock (eth_tx_clk),
.dataout (eth_tx_clk_out));
assign eth_tx_reset_s = ~sys_pll_locked_s;
always @(posedge rx_clk) begin
rx_sysref_m1 <= rx_sysref_s;
rx_sysref_m2 <= rx_sysref_m1;
rx_sysref_m3 <= rx_sysref_m2;
rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
end
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_align_1
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_ip_sof (rx_ip_sof_s),
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
.rx_data (rx_data_s[n*32+31:n*32]));
end
endgenerate
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
.sld_data_bits (130),
.sld_data_bit_cntr_bits (8),
.sld_enable_advanced_trigger (0),
.sld_mem_address_bits (10),
.sld_node_crc_bits (32),
.sld_node_crc_hiword (10311),
.sld_node_crc_loword (14297),
.sld_node_info (1076736),
.sld_ram_block_type ("AUTO"),
.sld_sample_depth (1024),
.sld_storage_qualifier_gap_record (0),
.sld_storage_qualifier_mode ("OFF"),
.sld_trigger_bits (2),
.sld_trigger_in_enabled (0),
.sld_trigger_level (1),
.sld_trigger_level_pipeline (1))
i_signaltap (
.acq_clk (rx_clk),
.acq_data_in ({ rx_sysref,
rx_sync,
rx_ip_data_s}),
.acq_trigger_in ({rx_sysref, rx_sync}));
assign rx_xcvr_status_s[15:15] = 1'd0;
assign rx_xcvr_status_s[14:14] = rx_sync;
assign rx_xcvr_status_s[13:13] = rx_ready_s;
assign rx_xcvr_status_s[12:12] = rx_pll_locked_s;
assign rx_xcvr_status_s[11: 8] = rx_rst_state_s;
assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s;
assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s;
ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst (
.rx_clk (rx_clk),
.rx_rstn (sys_resetn),
.rx_sw_rstn (rx_sw_rstn_s),
.rx_pll_locked (rx_pll_locked_s),
.rx_cal_busy (rx_cal_busy_s),
.rx_cdr_locked (rx_cdr_locked_s),
.rx_analog_reset (rx_analog_reset_s),
.rx_digital_reset (rx_digital_reset_s),
.rx_ready (rx_ready_s),
.rx_rst_state (rx_rst_state_s));
fmcjesdadc1_spi i_fmcjesdadc1_spi (
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_reset_reset_n (sys_resetn),
.sys_125m_clk_clk (sys_125m_clk),
.sys_25m_clk_clk (sys_25m_clk),
.sys_2m5_clk_clk (sys_2m5_clk),
.sys_ddr3_phy_mem_a (ddr3_a),
.sys_ddr3_phy_mem_ba (ddr3_ba),
.sys_ddr3_phy_mem_ck (ddr3_clk_p),
.sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
.sys_ddr3_phy_mem_cke (ddr3_cke),
.sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
.sys_ddr3_phy_mem_dm (ddr3_dm),
.sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
.sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
.sys_ddr3_phy_mem_we_n (ddr3_we_n),
.sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
.sys_ddr3_phy_mem_dq (ddr3_dq),
.sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
.sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
.sys_ddr3_phy_mem_odt (ddr3_odt),
.sys_ddr3_oct_rzqin (ddr3_rzq),
.sys_ethernet_tx_clk_clk (eth_tx_clk),
.sys_ethernet_rx_clk_clk (eth_rx_clk),
.sys_ethernet_status_set_10 (),
.sys_ethernet_status_set_1000 (),
.sys_ethernet_status_eth_mode (eth_tx_mode_1g_s),
.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s),
.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
.sys_ethernet_mdio_mdc (eth_mdc),
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_gpio_in_export ({rx_xcvr_status_s, 5'd0, push_buttons, dip_switches}),
.sys_gpio_out_export ({14'd0, rx_sw_rstn_s, rx_sysref_s, led_grn, led_red}),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn),
.axi_ad9250_0_xcvr_clk_clk (rx_clk),
.axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]),
.axi_ad9250_1_xcvr_clk_clk (rx_clk),
.axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]),
.sys_jesd204b_s1_rx_link_data (rx_ip_data_s),
.sys_jesd204b_s1_rx_link_valid (),
.sys_jesd204b_s1_rx_link_ready (1'b1),
.sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s),
.sys_jesd204b_s1_sysref_export (rx_sysref),
.sys_jesd204b_s1_rx_ferr_export (rx_err_s),
.sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s),
.sys_jesd204b_s1_sync_n_export (rx_sync),
.sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s),
.sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data),
.sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
.sys_jesd204b_s1_locked_rx_is_lockedtodata (rx_cdr_locked_s),
.sys_jesd204b_s1_rx_cal_busy_rx_cal_busy (rx_cal_busy_s),
.sys_jesd204b_s1_ref_clk_clk (ref_clk),
.sys_jesd204b_s1_rx_clk_clk (rx_clk),
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
.sys_pll_locked_export (sys_pll_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_SYMBOL_V
`define SKY130_FD_SC_HD__NAND3_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V |
//======================================================================
//
// mult.v
// --------
// Module for testing how multipliers are implemented in different
// technologies with different operand widths. The core has a 32 bit
// API to ensure that I/O are not constraining the implementation.
// Operands and products are registered.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2017 Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module mult(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] addr,
input wire [(API_WIDTH - 1) : 0] write_data,
output wire [(API_WIDTH - 1) : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter API_WIDTH = 16;
parameter OPA_WIDTH = 256;
parameter OPB_WIDTH = 64;
localparam OPA_WORDS = OPA_WIDTH / API_WIDTH;
localparam OPA_BASE_ADDR = 8'h00;
localparam OPA_TOP_ADDR = (OPA_BASE_ADDR + OPA_WORDS - 1);
localparam OPB_WORDS = OPB_WIDTH / API_WIDTH;
localparam OPB_BASE_ADDR = 8'h40;
localparam OPB_TOP_ADDR = (OPB_BASE_ADDR + OPB_WORDS - 1);
localparam PROD_WIDTH = OPA_WIDTH + OPB_WIDTH;
localparam PROD_WORDS = PROD_WIDTH / API_WIDTH;
localparam PROD_BASE_ADDR = 8'h80;
localparam PROD_TOP_ADDR = (PROD_BASE_ADDR + PROD_WORDS - 1);
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [(OPA_WIDTH - 1) : 0] opa_reg;
reg [(OPA_WIDTH - 1) : 0] opa_new;
reg opa_we;
reg [(OPA_WIDTH - 1) : 0] opb_reg;
reg [(OPA_WIDTH - 1) : 0] opb_new;
reg opb_we;
reg [(PROD_WIDTH - 1) : 0] prod_reg;
reg [(PROD_WIDTH - 1) : 0] prod_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [(API_WIDTH -1) : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
opa_reg <= {(OPA_WIDTH){1'h0}};
opb_reg <= {(OPB_WIDTH){1'h0}};
prod_reg <= {(PROD_WIDTH){1'h0}};
end
else
begin
prod_reg <= prod_new;
if (opa_we)
opa_reg <= opa_new;
if (opb_we)
opb_reg <= opb_new;
end
end // reg_update
//----------------------------------------------------------------
// mult_logic
//
// This is where the action is.
//----------------------------------------------------------------
always @*
begin : mult_logic
prod_new = opa_reg * opb_reg;
end
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
tmp_read_data = {(API_WIDTH){1'h0}};
opa_new = opa_reg;
opa_we = 0;
opb_new = opb_reg;
opb_we = 0;
if (cs)
begin
if (we)
begin
if ((addr >= OPA_BASE_ADDR) && (addr <= OPA_TOP_ADDR))
begin
opa_new[API_WIDTH * (addr - OPA_BASE_ADDR) +: API_WIDTH] = write_data;
opa_we = 1;
end
if ((addr >= OPB_BASE_ADDR) && (addr <= OPB_TOP_ADDR))
begin
opb_new[API_WIDTH * (addr - OPB_BASE_ADDR) +: API_WIDTH] = write_data;
opb_we = 1;
end
end
else
begin
if ((addr >= PROD_BASE_ADDR) && (addr <= PROD_TOP_ADDR))
tmp_read_data = prod_reg[API_WIDTH * (addr - PROD_BASE_ADDR) +: API_WIDTH];
end
end
end // addr_decoder
endmodule // mult
//======================================================================
// EOF mult.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRBP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDFRBP_BLACKBOX_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRBP_BLACKBOX_V
|
//TODO: make memory do... something... when given an address not in range 0x80020000 -> (0x80020000 + Memory Size)
module data_memory2 (clk, addr, din, dout, pc, access_size, rw, busy, enable);
parameter ROM_FILE = "SimpleAdd.x";
`define MEMSIZE 1024
`define START_ADDR 32'h8002_0000
// input
input clk;
input [31:0] addr;
input [31:0] din;
input [2:0] access_size;
input rw; //1 is write, 0 is read
input enable;
// output
output reg busy;
output reg [31:0] dout;
output reg [31:0] pc;
// memory
reg [7:0] mem[0:`MEMSIZE];
// local
reg [31:0] reg_cur_addr = 'hffff; // current address
reg [5:0] reg_counter = 0; // number of cycles remaining
reg reg_rw = 0; // rw status
reg [31:0] reg_din = 'hffff; // prev datain
// comb
initial
begin
$readmemh(ROM_FILE, mem);
end
// proc
always @(posedge clk)
begin
reg_din = din;
// update current address
if (reg_counter > 1)
begin
reg_cur_addr = reg_cur_addr + 4;
end
else if (enable == 'b1) // + check address
begin
reg_cur_addr = addr - `START_ADDR;
end
else
begin
reg_cur_addr = reg_cur_addr; // no change
end
// update counter/rw
if (!(reg_counter > 1) && enable == 'b1)
begin
case (access_size)
3'b000 : reg_counter = 'd1; // word
3'b001 : reg_counter = 'd4; // 4 words
3'b010 : reg_counter = 'd8; // 8 words
3'b011 : reg_counter = 'd16; // 16 words
3'b100 : reg_counter = 'd1; // byte
3'b101 : reg_counter = 'd1; // half word
default : reg_counter = 'd0;
endcase
reg_rw = rw;
end
else
begin
reg_counter = reg_counter == 0 ? 0 : reg_counter - 1;
reg_rw = reg_rw;
end
// read
if ((reg_counter != 0) && reg_rw == 'b0)
begin
if (access_size == 3'b100)
begin
dout[31:24] = 0;
dout[23:16] = 0;
dout[15:8] = 0;
dout[7:0] = mem[reg_cur_addr]; // LSB
end
else if (access_size == 3'b101)
begin
dout[31:24] = 0;
dout[23:16] = 0;
dout[15:8] = mem[reg_cur_addr];
dout[7:0] = mem[reg_cur_addr+1]; // LSB
end
else
begin
dout[31:24] = mem[reg_cur_addr]; // MSB
dout[23:16] = mem[reg_cur_addr+1];
dout[15:8] = mem[reg_cur_addr+2];
dout[7:0] = mem[reg_cur_addr+3]; // LSB
end
pc = reg_cur_addr + `START_ADDR;
end
else
begin
dout[31:0] = 'bx;
end
// write
if ((reg_counter != 0) && reg_rw == 'b1)
begin
if (access_size == 3'b100)
begin
mem[reg_cur_addr] = reg_din[7:0];
end
else if (access_size == 3'b101)
begin
mem[reg_cur_addr] = reg_din[15:8]; // MSB
mem[reg_cur_addr+1] = reg_din[7:0];
end
else
begin
mem[reg_cur_addr] = reg_din[31:24]; // MSB
mem[reg_cur_addr+1] = reg_din[23:16];
mem[reg_cur_addr+2] = reg_din[15:8];
mem[reg_cur_addr+3] = reg_din[7:0]; // LSB
end
end
busy = (reg_counter > 1);
end
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/03/2015 09:08:56 PM
// Design Name:
// Module Name: debouncer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module debouncer(
input clk,
input I0,
input I1,
output reg O0,
output reg O1
);
reg [4:0]cnt0, cnt1;
reg Iv0=0,Iv1=0;
reg out0, out1;
always@(posedge(clk))begin
if (I0==Iv0)begin
if (cnt0==19)O0<=I0;
else cnt0<=cnt0+1;
end
else begin
cnt0<="00000";
Iv0<=I0;
end
if (I1==Iv1)begin
if (cnt1==19)O1<=I1;
else cnt1<=cnt1+1;
end
else begin
cnt1<="00000";
Iv1<=I1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBN_LP_V
`define SKY130_FD_SC_LP__DLRBN_LP_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbn with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbn_lp (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbn_lp (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBN_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTP_4_V
`define SKY130_FD_SC_MS__DLRTP_4_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTP_4_V
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : spm.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/cpu/spm.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-12-08 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
//File Include : system header file
`include "../sys_include.h"
//File Include : module header file
`include "spm.h"
module spm (
//1.clock and reset if
input wire clk ,//clock
//2.port a if stage
input wire [`SpmAddrBus] if_spm_addr ,//address
input wire if_spm_as_n ,//address strobe
input wire if_spm_rw ,//read/write
input wire [`WordDataBus] if_spm_wr_data ,//write in data
output wire [`WordDataBus] if_spm_rd_data ,//read out data
//3.port b mem stage
input wire [`SpmAddrBus] mem_spm_addr ,//address
input wire mem_spm_as_n ,//address strobe
input wire mem_spm_rw ,//read/write
input wire [`WordDataBus] mem_spm_wr_data ,//write in data
output wire [`WordDataBus] mem_spm_rd_data // read out data
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
reg wea ;//write enable A
reg web ;//write enable B
//************************************************************************************************
// 3.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the generate of write enable
//------------------------------------------------------------------------------------------------
always @(*) begin
/* port A */
if ((if_spm_as_n == `ENABLE_N) && (if_spm_rw == `WRITE))
begin
wea = `MEM_ENABLE; //write in valid
end
else
begin
wea = `MEM_DISABLE; //write in disable
end
/* port B */
if ((mem_spm_as_n == `ENABLE_N) && (mem_spm_rw == `WRITE))
begin
web = `MEM_ENABLE; //write in valid
end
else
begin
web = `MEM_DISABLE; //write in disable
end
end
//************************************************************************************************
// 4.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the clk generate module
//------------------------------------------------------------------------------------------------
/********** Xilinx FPGA Block RAM : two ports RAM **********/
symmetric_mem_core x_s3e_dpram (
/********** port A : IF stage **********/
.clockA (clk), //clock
.addressA (if_spm_addr), //address
.input_dataA (if_spm_wr_data), //
.write_enableA (wea), //
.output_dataA (if_spm_rd_data), //
/********** port B : MEM Stage **********/
.clockB (clk), //
.addressB (mem_spm_addr), //
.input_dataB (mem_spm_wr_data), //
.write_enableB (web), //
.output_dataB (mem_spm_rd_data) //read data
);
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
/******************************************************************************/
/* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
`include "user_logic.v"
`include "sorter.v"
/******************************************************************************/
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase_a==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase_a==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase_a==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase_a==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase_a==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase_a==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase_a==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase_a==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase_a==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase_a==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|Pa%dPb%d|%d%d%d|%d", cnt[19:0], u.core.elem_a, u.core.phase_a[2:0], u.core.phase_b[2:0], u.core.iter_done_a, u.core.pchange_a, u.core.irst_a, u.core.ecnt_a);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("(%d)", u.core.state);
$write("| %d %d %d %d %d %d %d %d| %d %d %d %d %d %d %d %d|",
u.core.im00_a.imf.cnt, u.core.im01_a.imf.cnt, u.core.im02_a.imf.cnt, u.core.im03_a.imf.cnt,
u.core.im04_a.imf.cnt, u.core.im05_a.imf.cnt, u.core.im06_a.imf.cnt, u.core.im07_a.imf.cnt,
u.core.im00_b.imf.cnt, u.core.im01_b.imf.cnt, u.core.im02_b.imf.cnt, u.core.im03_b.imf.cnt,
u.core.im04_b.imf.cnt, u.core.im05_b.imf.cnt, u.core.im06_b.imf.cnt, u.core.im07_b.imf.cnt);
$write(" ");
if (u.core.F01_deq_a) $write("%08x %08x %08x %08x ", u.core.F01_dot_a[127:96], u.core.F01_dot_a[95:64], u.core.F01_dot_a[63:32], u.core.F01_dot_a[31:0]); else $write(" ");
if (u.core.F01_deq_b) $write("%08x %08x %08x %08x ", u.core.F01_dot_b[127:96], u.core.F01_dot_b[95:64], u.core.F01_dot_b[63:32], u.core.F01_dot_b[31:0]); else $write(" ");
// $write("| ");
// $write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/**************************************************************************************************/
module Host_to_FPGA(input wire CLK,
input wire RST,
input wire ren,
output reg chnl_rx,
output wire [`MERGW-1:0] dot,
output wire doten,
output wire [31:0] length);
reg rst_buf; always @(posedge CLK) rst_buf <= RST;
wire enq;
wire deq;
wire [`MERGW-1:0] din;
wire emp;
wire ful;
wire [4:0] cnt;
reg [`SORTW-1:0] i_d,i_c,i_b,i_a;
reg onetime;
reg [31:0] enqcnt;
reg enqstop;
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
reg [1:0] selector;
wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} :
(selector == 1) ? {r07,r06,r05,r04} :
(selector == 2) ? {r11,r10,r09,r08} :
(selector == 3) ? {r15,r14,r13,r12} : 0;
SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt);
assign enq = (!enqstop && !ful);
assign deq = (ren && !emp);
assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a};
assign doten = deq;
assign length = `SORT_ELM;
always @(posedge CLK) begin
if (rst_buf) begin
chnl_rx <= 0;
onetime <= 1;
end else begin
chnl_rx <= onetime;
onetime <= 0;
end
end
always @(posedge CLK) begin
if (rst_buf) enqcnt <= 0;
else if (enq) enqcnt <= enqcnt + 4;
end
always @(posedge CLK) begin
if (rst_buf) enqstop <= 0;
else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1;
end
always @(posedge CLK) begin
if (rst_buf) selector <= 0;
else if (enq) selector <= selector + 1;
end
generate
if (`INITTYPE=="sorted") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
end else begin
if (enq) begin
i_a <= i_a+4;
i_b <= i_b+4;
i_c <= i_c+4;
i_d <= i_d+4;
end
end
end
end else if (`INITTYPE=="reverse") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= `SORT_ELM;
i_b <= `SORT_ELM-1;
i_c <= `SORT_ELM-2;
i_d <= `SORT_ELM-3;
end else begin
if (enq) begin
i_a <= i_a-4;
i_b <= i_b-4;
i_c <= i_c-4;
i_d <= i_d-4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15);
end
endgenerate
endmodule
/**************************************************************************************************/
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
`timescale 1ns/10ps
module soc_system_system_pll(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("125.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("25.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.1
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module ARM_FIFO_out (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_rst_busy,
rd_rst_busy
);
input wire rst;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
input wire wr_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [31 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [15 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
output wire [10 : 0] rd_data_count;
output wire wr_rst_busy;
output wire rd_rst_busy;
fifo_generator_v13_1_2 #(
.C_COMMON_CLOCK(0),
.C_SELECT_XPM(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(16),
.C_ENABLE_RLOCS(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(509),
.C_PROG_FULL_THRESH_NEGATE_VAL(508),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(11),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(1),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(512),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_EN_SAFETY_CKT(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(8),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(1),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(rst),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(10'B0),
.prog_empty_thresh_assert(10'B0),
.prog_empty_thresh_negate(10'B0),
.prog_full_thresh(9'B0),
.prog_full_thresh_assert(9'B0),
.prog_full_thresh_negate(9'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(rd_data_count),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(wr_rst_busy),
.rd_rst_busy(rd_rst_busy),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
`timescale 1 ns / 1 ps
module gpio_delayed_trigger #
(
parameter integer GPIO_DATA_WIDTH = 8,
parameter integer GPIO_INPUT_WIDTH = 4,
parameter integer GPIO_OUTPUT_WIDTH = 4
)
(
// System signals
input wire aclk,
input wire aresetn,
inout wire [GPIO_DATA_WIDTH-1:0] gpio_data,
input wire [GPIO_OUTPUT_WIDTH-1:0] out_data,
input wire soft_trig,
input wire [31:0] delay,
output wire trigger,
output wire instant_trigger,
output wire delay_pulse
);
reg [GPIO_DATA_WIDTH-1:0] int_data_reg [1:0];
reg triggered, int_trig_reg, int_trig_reg_next,out_trig, out_trig_next;
reg [31:0] counter, counter_next;
wire [GPIO_DATA_WIDTH-1:0] int_data_wire;
wire int_comp_wire;
wire [GPIO_OUTPUT_WIDTH-1:0] int_output;
genvar j;
// input pins
generate
for(j = 0; j < GPIO_INPUT_WIDTH; j = j + 1)
begin : GPIO
IOBUF gpio_iobuf (.O(int_data_wire[j]), .IO(gpio_data[j]), .I({(GPIO_INPUT_WIDTH){1'b0}}), .T(1'b1));
end
endgenerate
// output pins
generate
for(j = GPIO_INPUT_WIDTH; j < GPIO_DATA_WIDTH; j = j + 1)
begin : GPIO_OUT
IOBUF gpio_iobuf (.O(int_data_wire[j]), .IO(gpio_data[j]), .I(int_output[j-GPIO_INPUT_WIDTH]), .T(1'b0));
end
endgenerate
assign int_comp_wire = counter < delay;
always @(posedge aclk)
begin
int_data_reg[0] <= int_data_wire;
int_data_reg[1] <= int_data_reg[0];
if(~aresetn)
begin
int_trig_reg <= 1'b0;
out_trig <= 1'b0;
counter <= 32'b0;
end
else
begin
int_trig_reg <= int_trig_reg_next;
out_trig <= out_trig_next;
counter <= counter_next;
end
end
always @*
begin
int_trig_reg_next = int_trig_reg;
out_trig_next = out_trig;
counter_next = counter;
if(soft_trig | int_data_reg[1][0:0])
int_trig_reg_next = 1'b1;
if ( int_comp_wire & int_trig_reg)
counter_next=counter + 1'b1;
if ( ~int_comp_wire)
out_trig_next = 1'b1;
end
assign trigger = out_trig;
assign instant_trigger = int_trig_reg;
assign delay_pulse = instant_trigger&~trigger;
assign int_output = {{(GPIO_OUTPUT_WIDTH-1){1'b0}},delay_pulse};
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_SHARED_CODE
reg window = 0;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (!window && start_event == 1'b1)
window <= 1'b1;
else if (window && end_event == 1'b1)
window <= 1'b0;
end
else begin
window <= 1'b0;
end
end
`endif // OVL_SHARED_CODE
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
wire xzdetect_test_expr;
assign xzdetect_test_expr = ((^test_expr) ^ (^test_expr) == 1'b0);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_win_change_assert #(
.width(width))
assert_win_change_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.end_event(end_event),
.test_expr(test_expr),
.window(window),
.xzdetect_test_expr(xzdetect_test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_win_change_assume #(
.width(width))
assert_win_change_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.end_event(end_event),
.test_expr(test_expr),
.window(window),
.xzdetect_test_expr(xzdetect_test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_win_change_cover #(
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON))
assert_win_change_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.end_event(end_event),
.window(window));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_win_change.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_win_change_assert (clk, reset_n, start_event, end_event, test_expr, window,
xzdetect_test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n, start_event, end_event, window;
input [width-1:0] test_expr;
input xzdetect_test_expr, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_win_change_assume (clk, reset_n, start_event, end_event, test_expr, window,
xzdetect_test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n, start_event, end_event, window;
input [width-1:0] test_expr;
input xzdetect_test_expr, xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_win_change_cover (clk, reset_n, start_event, end_event, window);
parameter OVL_COVER_BASIC_ON = 1;
input clk, reset_n, start_event, end_event, window;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DLRTP_PP_SYMBOL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A2111OI_FUNCTIONAL_PP_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111OI_FUNCTIONAL_PP_V |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright 2010-2012 by Michael A. Morris, dba M. A. Morris & Associates
//
// All rights reserved. The source code contained herein is publicly released
// under the terms and conditions of the GNU Lesser Public License. No part of
// this source code may be reproduced or transmitted in any form or by any
// means, electronic or mechanical, including photocopying, recording, or any
// information storage and retrieval system in violation of the license under
// which the source code is released.
//
// The souce code contained herein is free; it may be redistributed and/or
// modified in accordance with the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either version 2.1 of
// the GNU Lesser General Public License, or any later version.
//
// The souce code contained herein is freely released WITHOUT ANY WARRANTY;
// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
// more details.)
//
// A copy of the GNU Lesser General Public License should have been received
// along with the source code contained herein; if not, a copy can be obtained
// by writing to:
//
// Free Software Foundation, Inc.
// 51 Franklin Street, Fifth Floor
// Boston, MA 02110-1301 USA
//
// Further, no use of this source code is permitted in any form or means
// without inclusion of this banner prominently in any derived works.
//
// Michael A. Morris
// Huntsville, AL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: M. A. Morris & Associates
// Engineer: Michael A. Morris
//
// Create Date: 12:59:58 10/02/2010
// Design Name: Fast 4-bit Booth Multiplier
// Module Name: Booth_Multiplier_4xA.v
// Project Name: Booth_Multiplier
// Target Devices: Spartan-3AN
// Tool versions: Xilinx ISE 10.1 SP3
//
// Description:
//
// This module implements a parameterized multiplier which uses a Modified
// Booth algorithm for its implementation. The implementation is based on the
// algorithm described in "Computer Organization", Hamacher et al, McGraw-
// Hill Book Company, New York, NY, 1978, ISBN: 0-07-025681-0.
//
// Compared to the standard, 1-bit at a time Booth algorithm, this modified
// Booth multiplier algorithm shifts the multiplier 4 bits at a time. Thus,
// this algorithm will compute a 2's complement product four times as fast as
// the base algorithm.
//
// This particular module attempts to optimize the synthesis and implementation
// results relative to those of the Booth_Multiplier_4x.v module. Examination
// of the synthesis results of that module indicate that 16 20-bit adders and
// 16 20-bit subtractors are needed to implement the partial products. This
// module uses a different approach to eliminate the large number of adders
// and subtractors such that only two cascaded adders are required; When sub-
// traction is required, complementing the input and adding a carry into the
// sum is how the subtractions are implemented. 32:1 multiplexers are used to
// evaluated the Booth recoding value and determine the value and operation to
// be performed by the two cascaded adders.
//
// Dependencies:
//
// Revision:
//
// 0.01 10J02 MAM File Created
//
// 1.0 12I02 MAM Changed the implementation of the base module to
// reduced the number of inferred adders and reduce
// the number of multiplexers required.
//
// Additional Comments:
//
// The basic operations follow those of the standard Booth multiplier except
// that the transitions are being tracked across 4 bits plus the guard bit.
// The result is that the operations required are 0, ±1, ±2, ±3, ±4, ±5, ±6,
// ±7, and ±8 times the multiplicand (M). However, it is possible to reduce
// the number of partial products required to implement the multiplication to
// two. That is, ±3, ±5, ±6, and ±7 can be written in terms of combinations of
// ±1, ±2, ±4, and ±8. For example, 3M = (2M + 1M), 5M = (4M + M), 6M = (4M
// + 2M), and 7M = (8M - M). Thus, the following 32 entry table defines the
// operations required for generating the partial products through each pass
// of the algorithm over the multiplier:
//
// Prod[4:0] Operation
// 00000 Prod <= (Prod + 0*M + 0*M) >> 4;
// 00001 Prod <= (Prod + 0*M + 1*M) >> 4;
// 00010 Prod <= (Prod + 0*M + 1*M) >> 4;
// 00011 Prod <= (Prod + 2*M + 0*M) >> 4;
// 00100 Prod <= (Prod + 2*M + 0*M) >> 4;
// 00101 Prod <= (Prod + 2*M + 1*M) >> 4;
// 00110 Prod <= (Prod + 2*M + 1*M) >> 4;
// 00111 Prod <= (Prod + 4*M + 0*M) >> 4;
// 01000 Prod <= (Prod + 4*M + 0*M) >> 4;
// 01001 Prod <= (Prod + 4*M + 1*M) >> 4;
// 01010 Prod <= (Prod + 4*M + 1*M) >> 4;
// 01011 Prod <= (Prod + 4*M + 2*M) >> 4;
// 01100 Prod <= (Prod + 4*M + 2*M) >> 4;
// 01101 Prod <= (Prod + 8*M - 1*M) >> 4;
// 01110 Prod <= (Prod + 8*M - 1*M) >> 4;
// 01111 Prod <= (Prod + 8*M + 0*M) >> 4;
// 10000 Prod <= (Prod - 8*M - 0*M) >> 4;
// 10001 Prod <= (Prod - 8*M + 1*M) >> 4;
// 10010 Prod <= (Prod - 8*M + 1*M) >> 4;
// 10011 Prod <= (Prod - 4*M - 2*M) >> 4;
// 10100 Prod <= (Prod - 4*M - 2*M) >> 4;
// 10101 Prod <= (Prod - 4*M - 1*M) >> 4;
// 10110 Prod <= (Prod - 4*M - 1*M) >> 4;
// 10111 Prod <= (Prod - 4*M - 0*M) >> 4;
// 11000 Prod <= (Prod - 4*M - 0*M) >> 4;
// 11001 Prod <= (Prod - 2*M - 1*M) >> 4;
// 11010 Prod <= (Prod - 2*M - 1*M) >> 4;
// 11011 Prod <= (Prod - 2*M - 0*M) >> 4;
// 11100 Prod <= (Prod - 2*M - 0*M) >> 4;
// 11101 Prod <= (Prod - 0*M - 1*M) >> 4;
// 11110 Prod <= (Prod - 0*M - 1*M) >> 4;
// 11111 Prod <= (Prod - 0*M - 0*M) >> 4;
//
// One approach to implementing the recoding table is to use a 32:1 multiplexer
// and simply write out the necessary operations. This is the approach used in
// the first version of the 4 bits at a time Booth multiplier. The problem is
// that the implementation of the preceding recoding table in a first prin-
// ciples manner results in a large number of adders and subtractors being
// synthesized. Apparently, the structure and character of the RTL code is such
// that the synthesizer is unable to use multiplexers to determine the operands
// of the two adders which are required.
//
// Examining the previous recoding table shows that seven multiples of the
// multiplicand (M) are represented in the first multiplicand column, 0x, ±2x,
// ±4x, and ±8x, and five are represented in the second multiplicand column,
// 0x, ±1x, and ±2. The synthesizer is able to identify the need for adders and
// subractors, but is unable to morph the structure from one embedded in a 32:1
// multiplexer into one where an 8:1 multiplexer feeds the first multiplicand
// products into one adder, and another 8:1 multiplexer feeds the second multi-
// plicand product into another adder cascaded with the first.
//
// A review of the corresponding synthesis report shows that the synthesizer
// extracted 8 adders and 8 subtractors. Refering to the 32 line recoding table
// above, shows that there are 8 diffent combinations of the multiplicand pro-
// ducts that must be added/subtracted to the partial product, Prod, to deter-
// mine the final product. The resulting implementation is correct, as deter-
// mined by its testbench, but the implementation certainly uses more resources
// than would be expected when increasing the number of bits processed per
// stage/iteration from 2 to 4. A natural assumption is that the resources uti-
// lized would increase by a factor close to 2 as the number of bits processed
// is increased by powers of 2: 1, 2, 4, etc.
//
// It is now clear that the synthesizer is unable to transform the multiplexed
// adder structure inherent in the current specification into a structure which
// is composed of multiplexers followed by two cascaded adders. Therefore, that
// simpler structure must be explcitly specified in this module's RTL. In order
// to minimize the multiplexers, the recoding table needs to be modified from
// its current definition to an equivalent definition that can be implemented
// using just two multiplicand products. The following recoding table can be
// compared to the one above to see the adjustments made. In essence, the first
// multiplicand column allows only five multiplicand product values, 0M, ±4M,
// and ±8M, and the second multiplicand column also allows only five values,
// 0M, ±1M, and ±2M.
//
// Prod[4:0] Operation
// 00000 Prod <= (Prod + 0*M + 0*M) >> 4;
// 00001 Prod <= (Prod + 0*M + 1*M) >> 4;
// 00010 Prod <= (Prod + 0*M + 1*M) >> 4;
// 00011 Prod <= (Prod + 0*M + 2*M) >> 4;
// 00100 Prod <= (Prod + 0*M + 2*M) >> 4;
// 00101 Prod <= (Prod + 4*M - 1*M) >> 4;
// 00110 Prod <= (Prod + 4*M - 1*M) >> 4;
// 00111 Prod <= (Prod + 4*M + 0*M) >> 4;
// 01000 Prod <= (Prod + 4*M + 0*M) >> 4;
// 01001 Prod <= (Prod + 4*M + 1*M) >> 4;
// 01010 Prod <= (Prod + 4*M + 1*M) >> 4;
// 01011 Prod <= (Prod + 4*M + 2*M) >> 4;
// 01100 Prod <= (Prod + 4*M + 2*M) >> 4;
// 01101 Prod <= (Prod + 8*M - 1*M) >> 4
// 01110 Prod <= (Prod + 8*M - 1*M) >> 4;
// 01111 Prod <= (Prod + 8*M + 0*M) >> 4;
// 10000 Prod <= (Prod - 8*M - 0*M) >> 4;
// 10001 Prod <= (Prod - 8*M + 1*M) >> 4;
// 10010 Prod <= (Prod - 8*M + 1*M) >> 4;
// 10011 Prod <= (Prod - 4*M - 2*M) >> 4;
// 10100 Prod <= (Prod - 4*M - 2*M) >> 4;
// 10101 Prod <= (Prod - 4*M - 1*M) >> 4;
// 10110 Prod <= (Prod - 4*M - 1*M) >> 4;
// 10111 Prod <= (Prod - 4*M - 0*M) >> 4;
// 11000 Prod <= (Prod - 4*M - 0*M) >> 4;
// 11001 Prod <= (Prod - 4*M + 1*M) >> 4;
// 11010 Prod <= (Prod - 4*M + 1*M) >> 4;
// 11011 Prod <= (Prod - 0*M - 2*M) >> 4;
// 11100 Prod <= (Prod - 0*M - 2*M) >> 4;
// 11101 Prod <= (Prod - 0*M - 1*M) >> 4;
// 11110 Prod <= (Prod - 0*M - 1*M) >> 4;
// 11111 Prod <= (Prod - 0*M - 0*M) >> 4;
//
// The zero terms and the subtractions will be implemented using logic: bus AND
// for 0, and bus XOR and carry input for subtraction, i.e. 2sC add. With this
// additional reduction of operands, the multiplexers at the input to the adder
// tree only multiplex two values each, {4M, 8M} or {1M, 2M}, respectively. The
// operations required of the multiplexer and adder for each multiplicand
// column can be defined by the triple: {PnM, M_Sel, En}. En is the control for
// the bus AND which forms 0*M. M_Sel is the control for the multiplexer that
// selects {4M, 8M} or {1M, 2M}, respectively. PnM is the input to the bus XOR
// and carry input of the adder, and if 0 an addition is performed with the
// operand at the output of the bus AND, and if 1, the adder is presented with
// the complement of that operand plus an input carry. The bus AND can be built
// explicitly after the multiplexer, or it can be included as the default case
// of the multiplexer itself.
//
// In either case, the triples {PnM, M_Sel, En} can be constructed using a 32x6
// ROM. The first triple refers to the control signals for the first multipli-
// cand column and the second refers to the control signals for the second
// multiplicand column. To force the synthesizer to infer a ROM, a fully defin-
// ed case statement of 32 entries for each column is required:
//
// For the first column - B
//
// case(Booth)
// 5'b00000 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 0*M) >> 4;
// 5'b00001 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 1*M) >> 4;
// 5'b00010 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 1*M) >> 4;
// 5'b00011 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 2*M) >> 4;
// 5'b00100 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 2*M) >> 4;
// 5'b00101 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M - 1*M) >> 4;
// 5'b00110 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M - 1*M) >> 4;
// 5'b00111 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 0*M) >> 4;
// 5'b01000 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 0*M) >> 4;
// 5'b01001 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
// 5'b01010 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
// 5'b01011 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 2*M) >> 4;
// 5'b01100 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 2*M) >> 4;
// 5'b01101 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M - 1*M) >> 4
// 5'b01110 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M - 1*M) >> 4;
// 5'b01111 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M + 0*M) >> 4;
// 5'b10000 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M - 0*M) >> 4;
// 5'b10001 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M + 1*M) >> 4;
// 5'b10010 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M + 1*M) >> 4;
// 5'b10011 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 2*M) >> 4;
// 5'b10100 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 2*M) >> 4;
// 5'b10101 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
// 5'b10110 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
// 5'b10111 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 0*M) >> 4;
// 5'b11000 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 0*M) >> 4;
// 5'b11001 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M + 1*M) >> 4;
// 5'b11010 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M + 1*M) >> 4;
// 5'b11011 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 2*M) >> 4;
// 5'b11100 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 2*M) >> 4;
// 5'b11101 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 1*M) >> 4;
// 5'b11110 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 1*M) >> 4;
// 5'b11111 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
// default : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
// endcase
//
// For the second column - C
//
// case(Booth)
// 5'b00000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 0*M + 0*M) >> 4;
// 5'b00001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 0*M + 1*M) >> 4;
// 5'b00010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 0*M + 1*M) >> 4;
// 5'b00011 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 0*M + 2*M) >> 4;
// 5'b00100 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 0*M + 2*M) >> 4;
// 5'b00101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 4*M - 1*M) >> 4;
// 5'b00110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 4*M - 1*M) >> 4;
// 5'b00111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 4*M + 0*M) >> 4;
// 5'b01000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 4*M + 0*M) >> 4;
// 5'b01001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
// 5'b01010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
// 5'b01011 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 4*M + 2*M) >> 4;
// 5'b01100 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 4*M + 2*M) >> 4;
// 5'b01101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 8*M - 1*M) >> 4
// 5'b01110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 8*M - 1*M) >> 4;
// 5'b01111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 8*M + 0*M) >> 4;
// 5'b10000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 8*M - 0*M) >> 4;
// 5'b10001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 8*M + 1*M) >> 4;
// 5'b10010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 8*M + 1*M) >> 4;
// 5'b10011 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 4*M - 2*M) >> 4;
// 5'b10100 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 4*M - 2*M) >> 4;
// 5'b10101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
// 5'b10110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
// 5'b10111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 4*M - 0*M) >> 4;
// 5'b11000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 4*M - 0*M) >> 4;
// 5'b11001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 4*M + 1*M) >> 4;
// 5'b11010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 4*M + 1*M) >> 4;
// 5'b11011 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 0*M - 2*M) >> 4;
// 5'b11100 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 0*M - 2*M) >> 4;
// 5'b11101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 0*M - 1*M) >> 4;
// 5'b11110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 0*M - 1*M) >> 4;
// 5'b11111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
// default : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
// endcase
//
////////////////////////////////////////////////////////////////////////////////
module Booth_Multiplier_4xA #(
parameter N = 16 // Width = N: multiplicand & multiplier
)(
input Rst, // Reset
input Clk, // Clock
input Ld, // Load Registers and Start Multiplier
input [(N - 1):0] M, // Multiplicand
input [(N - 1):0] R, // Multiplier
output reg Valid, // Product Valid
output reg [((2*N) - 1):0] P // Product <= M * R
);
////////////////////////////////////////////////////////////////////////////////
//
// Local Parameters
//
localparam pNumCycles = ((N + 1)/4); // No. of cycles required for product
////////////////////////////////////////////////////////////////////////////////
//
// Declarations
//
reg [4:0] Cntr; // Operation Counter
reg [4:0] Booth; // Booth Recoding Field
reg Guard; // Shift Bit for Booth Recoding
reg [(N + 3):0] A; // Multiplicand w/ guards
wire [(N + 3):0] Mx8, Mx4, Mx2, Mx1; // Multiplicand products w/ guards
reg PnM_B, M_Sel_B, En_B; // Operand B Control Triple
reg PnM_C, M_Sel_C, En_C; // Operand C Control Triple
wire [(N + 3):0] Hi; // Upper Half of Product w/ guards
reg [(N + 3):0] B, C; // Adder tree Operand Inputs
reg Ci_B, Ci_C; // Adder tree Carry Inputs
wire [(N + 3):0] T, S; // Adder Tree Outputs w/ guards
reg [((2*N) + 3):0] Prod; // Double Length Product w/ guards
////////////////////////////////////////////////////////////////////////////////
//
// Implementation
//
always @(posedge Clk)
begin
if(Rst)
Cntr <= #1 0;
else if(Ld)
Cntr <= #1 pNumCycles;
else if(|Cntr)
Cntr <= #1 (Cntr - 1);
end
// Multiplicand Register
// includes 4 bits to guard sign of multiplicand in the event the most
// negative value is provided as the input.
always @(posedge Clk)
begin
if(Rst)
A <= #1 0;
else if(Ld)
A <= #1 {{4{M[(N - 1)]}}, M};
end
assign Mx8 = {A, 3'b0};
assign Mx4 = {A, 2'b0};
assign Mx2 = {A, 1'b0};
assign Mx1 = A;
// Compute Upper Partial Product: (N + 4) bits in width
always @(*) Booth <= {Prod[3:0], Guard}; // Booth's Multiplier Recoding field
assign Hi = Prod[((2*N) + 3):N]; // Upper Half of Product Register
// Compute the Control Triples for the First and Second Multiplicand Columns
// For the first column - B
always @(*)
begin
case(Booth)
5'b00000 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 0*M) >> 4;
5'b00001 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 1*M) >> 4;
5'b00010 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 1*M) >> 4;
5'b00011 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 2*M) >> 4;
5'b00100 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 2*M) >> 4;
5'b00101 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M - 1*M) >> 4;
5'b00110 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M - 1*M) >> 4;
5'b00111 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 0*M) >> 4;
5'b01000 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 0*M) >> 4;
5'b01001 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
5'b01010 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
5'b01011 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 2*M) >> 4;
5'b01100 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 2*M) >> 4;
5'b01101 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M - 1*M) >> 4;
5'b01110 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M - 1*M) >> 4;
5'b01111 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M + 0*M) >> 4;
5'b10000 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M - 0*M) >> 4;
5'b10001 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M + 1*M) >> 4;
5'b10010 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M + 1*M) >> 4;
5'b10011 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 2*M) >> 4;
5'b10100 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 2*M) >> 4;
5'b10101 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
5'b10110 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
5'b10111 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 0*M) >> 4;
5'b11000 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 0*M) >> 4;
5'b11001 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M + 1*M) >> 4;
5'b11010 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M + 1*M) >> 4;
5'b11011 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 2*M) >> 4;
5'b11100 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 2*M) >> 4;
5'b11101 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 1*M) >> 4;
5'b11110 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 1*M) >> 4;
5'b11111 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
default : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
endcase
end
// For the second column - C
always @(*)
begin
case(Booth)
5'b00000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 0*M + 0*M) >> 4;
5'b00001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 0*M + 1*M) >> 4;
5'b00010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 0*M + 1*M) >> 4;
5'b00011 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 0*M + 2*M) >> 4;
5'b00100 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 0*M + 2*M) >> 4;
5'b00101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 4*M - 1*M) >> 4;
5'b00110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 4*M - 1*M) >> 4;
5'b00111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 4*M + 0*M) >> 4;
5'b01000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 4*M + 0*M) >> 4;
5'b01001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
5'b01010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
5'b01011 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 4*M + 2*M) >> 4;
5'b01100 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 4*M + 2*M) >> 4;
5'b01101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 8*M - 1*M) >> 4;
5'b01110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 8*M - 1*M) >> 4;
5'b01111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 8*M + 0*M) >> 4;
5'b10000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 8*M - 0*M) >> 4;
5'b10001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 8*M + 1*M) >> 4;
5'b10010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 8*M + 1*M) >> 4;
5'b10011 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 4*M - 2*M) >> 4;
5'b10100 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 4*M - 2*M) >> 4;
5'b10101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
5'b10110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
5'b10111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 4*M - 0*M) >> 4;
5'b11000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 4*M - 0*M) >> 4;
5'b11001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 4*M + 1*M) >> 4;
5'b11010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 4*M + 1*M) >> 4;
5'b11011 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 0*M - 2*M) >> 4;
5'b11100 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 0*M - 2*M) >> 4;
5'b11101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 0*M - 1*M) >> 4;
5'b11110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 0*M - 1*M) >> 4;
5'b11111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
default : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
endcase
end
// Compute the first operand - B
always @(*)
begin
case({PnM_B, M_Sel_B, En_B})
3'b001 : {Ci_B, B} <= {1'b0, Mx4};
3'b011 : {Ci_B, B} <= {1'b0, Mx8};
3'b101 : {Ci_B, B} <= {1'b1, ~Mx4};
3'b111 : {Ci_B, B} <= {1'b1, ~Mx8};
default : {Ci_B, B} <= 0;
endcase
end
// Compute the second operand - C
always @(*)
begin
case({PnM_C, M_Sel_C, En_C})
3'b001 : {Ci_C, C} <= {1'b0, Mx1};
3'b011 : {Ci_C, C} <= {1'b0, Mx2};
3'b101 : {Ci_C, C} <= {1'b1, ~Mx1};
3'b111 : {Ci_C, C} <= {1'b1, ~Mx2};
default : {Ci_C, C} <= 0;
endcase
end
// Compute Partial Sum - Cascaded Adders
assign T = Hi + B + Ci_B;
assign S = T + C + Ci_C;
// Double Length Product Register
// Multiplier, R, is loaded into the least significant half on load, Ld
// Shifted right four places as the product is computed iteratively.
always @(posedge Clk)
begin
if(Rst)
Prod <= #1 0;
else if(Ld)
Prod <= #1 R;
else if(|Cntr) // Shift right four bits
Prod <= #1 {{4{S[(N + 3)]}}, S, Prod[(N - 1):4]};
end
always @(posedge Clk)
begin
if(Rst)
Guard <= #1 0;
else if(Ld)
Guard <= #1 0;
else if(|Cntr)
Guard <= #1 Prod[3];
end
// Assign the product less the four guard bits to the output port
// A 4-bit right shift is required since the output product is stored
// into a synchronous register on the last cycle of the multiply.
always @(posedge Clk)
begin
if(Rst)
P <= #1 0;
else if(Cntr == 1)
P <= #1 {S, Prod[(N - 1):4]};
end
// Count the number of shifts
// This implementation does not use any optimizations to perform multiple
// bit shifts to skip over runs of 1s or 0s.
always @(posedge Clk)
begin
if(Rst)
Valid <= #1 0;
else
Valid <= #1 (Cntr == 1);
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// A simple adder/substracter width preconfigured input ports width and turn-around value
// Output = A - B_constant or A + B_constant
// Constraints: Awidth >= Bwidth
`timescale 1ns/1ps
module ad_addsub (
clk,
A,
Amax,
out,
CE
);
// parameters
parameter A_DATA_WIDTH = 32;
parameter B_DATA_VALUE = 32'h1;
parameter ADD_OR_SUB_N = 0;
localparam ADDER = 1;
localparam SUBSTRACTER = 0;
// I/O definitions
input clk;
input [(A_DATA_WIDTH-1):0] A;
input [(A_DATA_WIDTH-1):0] Amax;
output [(A_DATA_WIDTH-1):0] out;
input CE;
// registers
reg [(A_DATA_WIDTH-1):0] out = 'b0;
reg [A_DATA_WIDTH:0] out_d = 'b0;
reg [A_DATA_WIDTH:0] out_d2 = 'b0;
reg [(A_DATA_WIDTH-1):0] A_d = 'b0;
reg [(A_DATA_WIDTH-1):0] A_d2 = 'b0;
reg [(A_DATA_WIDTH-1):0] Amax_d = 'b0;
reg [(A_DATA_WIDTH-1):0] Amax_d2 = 'b0;
// constant regs
reg [(A_DATA_WIDTH-1):0] B_reg = B_DATA_VALUE;
// latch the inputs
always @(posedge clk) begin
A_d <= A;
A_d2 <= A_d;
Amax_d <= Amax;
Amax_d2 <= Amax_d;
end
// ADDER/SUBSTRACTER
always @(posedge clk) begin
if ( ADD_OR_SUB_N == ADDER ) begin
out_d <= A_d + B_reg;
end else begin
out_d <= A_d - B_reg;
end
end
// Resolve
always @(posedge clk) begin
if ( ADD_OR_SUB_N == ADDER ) begin
if ( out_d > Amax_d2 ) begin
out_d2 <= out_d - Amax_d2;
end else begin
out_d2 <= out_d;
end
end else begin // SUBSTRACTER
if ( out_d[A_DATA_WIDTH] == 1'b1 ) begin
out_d2 <= Amax_d2 + out_d;
end else begin
out_d2 <= out_d;
end
end
end
// output logic
always @(posedge clk) begin
if ( CE ) begin
out <= out_d2;
end else begin
out <= 'b0;
end
end
endmodule
|
module mem_access(IRfrompipe4, IRfrompipe5, RAFromPipe, ALUOut, RAMemSelectInput, WAMemSelectInput, MemData, DataInSelect, WriteMem, RAFromPipeInc,SignalB, SignalC
, Rfout1, Rfout2, mem_wb_CCR_write, ex_mem_CCR_write);
output [15:0] MemData, RAFromPipeInc;
wire [15:0] DataIn;
input [15:0] ALUOut, RAFromPipe, Rfout1, Rfout2, SignalC, SignalB, IRfrompipe5, IRfrompipe4;
input RAMemSelectInput, WAMemSelectInput, WriteMem, DataInSelect, mem_wb_CCR_write, ex_mem_CCR_write;
wire [15:0] readAddSelected, writeAddSelected, DataInSelected;
wire [1:0] F3;
mux16x2 RASelect(.data0(RAFromPipe), .data1(ALUOut), .selectInput(RAMemSelectInput), .out(readAddSelected));
mux16x2 WASelect(.data0(RAFromPipe), .data1(ALUOut), .selectInput(WAMemSelectInput), .out(writeAddSelected));
mux16x4 DataSelect2(.data0(DataInSelected), .data1(SignalB), .data2(SignalC), .data3(16'b0), .selectInput(F3), .out(DataIn));
mux16x2 DataSelect1(.data0(Rfout1), .data1(Rfout2), .selectInput(DataInSelect), .out(DataInSelected));
data_mem DataMemory(.readAdd(readAddSelected), .out(MemData), .writeAdd(writeAddSelected), .in(DataIn), .write(WriteMem));
plus_one Inc(.in(RAFromPipe), .out(RAFromPipeInc));
forward_mem_stage f_mem(.mem_wb_op({IRfrompipe5[15:12],IRfrompipe5[1:0]}), .mem_wb_regA(IRfrompipe5[11:9]), .mem_wb_regC(IRfrompipe5[5:3]), .ex_mem_op({IRfrompipe4[15:12],IRfrompipe4[1:0]}),
.ex_mem_regA(IRfrompipe4[11:9]), .F3(F3) ,.mem_wb_CCR_write(mem_wb_CCR_write), .ex_mem_CCR_write(ex_mem_CCR_write));
endmodule
module forward_mem_stage(mem_wb_op,mem_wb_regA,mem_wb_regC,ex_mem_op,ex_mem_regA,F3,mem_wb_CCR_write,ex_mem_CCR_write);
parameter ADD = 6'b000000;
parameter NDU = 6'b001000;
parameter ADC = 6'b000010;
parameter ADZ = 6'b000001;
parameter ADI = 4'b0001;
parameter NDC = 6'b001010;
parameter NDZ = 6'b001001;
parameter LHI = 4'b0011;
parameter LW = 4'b0100;
parameter SW = 4'b0101;
parameter LM = 4'b0110;
parameter SM = 4'b0111;
parameter BEQ = 4'b1100;
parameter JAL = 4'b1000;
parameter JLR = 4'b1001;
input [2:0] mem_wb_regA,mem_wb_regC,ex_mem_regA;
input [5:0]mem_wb_op,ex_mem_op;
input mem_wb_CCR_write,ex_mem_CCR_write;
output reg [1:0]F3;
always @(*)
begin
if(ex_mem_op[5:2]==SW)
begin
if((ex_mem_regA == mem_wb_regC)&&(mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC||mem_wb_op==ADZ
||mem_wb_op==NDC||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
F3 = 2'd1;//b
else if((ex_mem_regA==mem_wb_regA)&&(mem_wb_op[5:2]==LW))
F3 = 2'd2;//c
else
F3 = 2'b0;
end
else
F3 = 2'b0;
end
endmodule
|
module wb_stream_reader
#(parameter WB_DW = 32,
parameter WB_AW = 32,
parameter FIFO_AW = 0,
parameter MAX_BURST_LEN = 2**FIFO_AW)
(input clk,
input rst,
//Wisbhone memory interface
output [WB_AW-1:0] wbm_adr_o,
output [WB_DW-1:0] wbm_dat_o,
output [WB_DW/8-1:0] wbm_sel_o,
output wbm_we_o ,
output wbm_cyc_o,
output wbm_stb_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
input [WB_DW-1:0] wbm_dat_i,
input wbm_ack_i,
input wbm_err_i,
//Stream interface
input [WB_DW-1:0] stream_s_data_i,
input stream_s_valid_i,
output stream_s_ready_o,
output irq_o,
//Configuration interface
input [4:0] wbs_adr_i,
input [WB_DW-1:0] wbs_dat_i,
input [WB_DW/8-1:0] wbs_sel_i,
input wbs_we_i ,
input wbs_cyc_i,
input wbs_stb_i,
input [2:0] wbs_cti_i,
input [1:0] wbs_bte_i,
output [WB_DW-1:0] wbs_dat_o,
output wbs_ack_o,
output wbs_err_o);
//FIFO interface
wire [WB_DW-1:0] fifo_dout;
wire [FIFO_AW:0] fifo_cnt;
wire fifo_rd;
//Configuration parameters
wire enable;
wire [WB_DW-1:0] tx_cnt;
wire [WB_AW-1:0] start_adr;
wire [WB_AW-1:0] buf_size;
wire [WB_AW-1:0] burst_size;
wire busy;
wb_stream_reader_ctrl
#(.WB_AW (WB_AW),
.WB_DW (WB_DW),
.FIFO_AW (FIFO_AW),
.MAX_BURST_LEN (MAX_BURST_LEN))
ctrl
(.wb_clk_i (clk),
.wb_rst_i (rst),
//Stream data output
.wbm_adr_o (wbm_adr_o),
.wbm_dat_o (wbm_dat_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_cyc_o (wbm_cyc_o),
.wbm_stb_o (wbm_stb_o),
.wbm_cti_o (wbm_cti_o),
.wbm_bte_o (wbm_bte_o),
.wbm_dat_i (wbm_dat_i),
.wbm_ack_i (wbm_ack_i),
.wbm_err_i (wbm_err_i),
//FIFO interface
.fifo_d (fifo_dout),
.fifo_cnt (fifo_cnt),
.fifo_rd (fifo_rd),
//Configuration interface
.busy (busy),
.enable (enable),
.tx_cnt (tx_cnt),
.start_adr (start_adr),
.buf_size (buf_size),
.burst_size (burst_size));
wb_stream_reader_cfg
#(.WB_AW (WB_AW),
.WB_DW (WB_DW))
cfg
(.wb_clk_i (clk),
.wb_rst_i (rst),
//Wishbone IF
.wb_adr_i (wbs_adr_i),
.wb_dat_i (wbs_dat_i),
.wb_sel_i (wbs_sel_i),
.wb_we_i (wbs_we_i),
.wb_cyc_i (wbs_cyc_i),
.wb_stb_i (wbs_stb_i),
.wb_cti_i (wbs_cti_i),
.wb_bte_i (wbs_bte_i),
.wb_dat_o (wbs_dat_o),
.wb_ack_o (wbs_ack_o),
.wb_err_o (wbs_err_o),
//Application IF
.irq (irq_o),
.busy (busy),
.enable (enable),
.tx_cnt (tx_cnt),
.start_adr (start_adr),
.buf_size (buf_size),
.burst_size (burst_size));
wb_stream_writer_fifo
#(.DW (WB_DW),
.AW (FIFO_AW))
fifo
(.clk (clk),
.rst (rst),
.stream_s_data_i (stream_s_data_i),
.stream_s_valid_i (stream_s_valid_i),
.stream_s_ready_o (stream_s_ready_o),
.stream_m_data_o (fifo_dout),
.stream_m_valid_o (),
.stream_m_ready_i (fifo_rd),
.cnt (fifo_cnt));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: MossbauerLab
// Engineer: EvilLord666 (Ushakov MV)
//
// Create Date: 21:01:28 08/30/2017
// Design Name: messbauer_test_environment
// Module Name: messbauer_diff_discriminator_signals
// Project Name:
// Target Devices: Spartan 6
// Tool versions: ISE 14.7
// Description: ALINX AX309 MESSBAUER DIFF DISCRIMINATOR SIGNALS
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module messbauer_diff_discriminator_signals #
(
parameter GCLK_PERIOD = 20, // nanoseconds
parameter LOWER_THRESHOLD_DURATION = 3, // GCLK_PERIOD
parameter UPPER_THRESHOLD_DURATION = 1, // GCLK_PERIOD
parameter DISCRIMINATOR_IMPULSES_PAUSE = 10, // GCLK_PERIOD
parameter IMPULSES_PER_CHANNEL = 16,
parameter IMPULSES_FOR_SELECTION = 4 // number of impulses passes through diff disriminator MUST be smaller than IMPULSES_PER_CHANNEL
)
(
input wire aclk,
input wire areset_n,
input wire channel,
output reg lower_threshold,
output reg upper_threshold
);
localparam INITIAL_STATE = 0;
localparam LOWER_THRESHOLD_HIGH_PHASE = 1;
localparam UPPER_THRESHOLD_HIGH_PHASE = 2;
localparam UPPER_THRESHOLD_LOW_PHASE = 3;
localparam LOWER_THRESHOLD_LOW_PHASE = 4;
localparam FINAL_STATE = 5;
localparam PAUSE_DURATION = 4;
reg enable;
reg first_enable;
reg[15:0] clk_counter;
reg[15:0] impulse_counter;
reg[15:0] total_impulse_counter;
reg[2:0] state;
reg impulse_rejected;
reg period_done;
always @(posedge aclk)
begin
if(~areset_n)
begin
clk_counter <= 0;
impulse_counter <= 0;
total_impulse_counter <= 0;
state <= INITIAL_STATE;
lower_threshold <= 0;
upper_threshold <= 0;
first_enable <= 1;
impulse_rejected <= 1;
end
else
begin
if(first_enable || enable)
begin
clk_counter <= clk_counter + 1'b1;
case (state)
INITIAL_STATE:
begin
clk_counter <= 0;
state <= LOWER_THRESHOLD_HIGH_PHASE;
impulse_rejected <= 0;
period_done <= 0;
end
LOWER_THRESHOLD_HIGH_PHASE:
begin
lower_threshold <= 1;
if(clk_counter == 1)
begin
// check should we generate upper
if(impulse_counter <= IMPULSES_FOR_SELECTION)
state <= LOWER_THRESHOLD_LOW_PHASE;
else state <= UPPER_THRESHOLD_HIGH_PHASE;;
end
end
UPPER_THRESHOLD_HIGH_PHASE:
begin
impulse_rejected <= 1;
upper_threshold <= 1;
if(clk_counter == UPPER_THRESHOLD_DURATION + 1)
state <= UPPER_THRESHOLD_LOW_PHASE;
end
UPPER_THRESHOLD_LOW_PHASE:
begin
state <= LOWER_THRESHOLD_LOW_PHASE;
upper_threshold <= 0;
end
LOWER_THRESHOLD_LOW_PHASE:
begin
lower_threshold <= 0;
if(clk_counter >= LOWER_THRESHOLD_DURATION)
begin
if(impulse_rejected == 0)
impulse_counter <= impulse_counter + 1'b1;
total_impulse_counter <= total_impulse_counter + 1'b1;
if(total_impulse_counter < IMPULSES_PER_CHANNEL)
state <= INITIAL_STATE;
else state <= FINAL_STATE;
end
end
FINAL_STATE:
begin
impulse_counter <= 0;
total_impulse_counter <= 0;
period_done <= 1;
first_enable <= 0;
end
default:
begin
end
endcase
end
else state <= INITIAL_STATE;
end
end
always @(posedge channel or negedge areset_n)
begin
if(~areset_n)
enable = 0;
else
begin
if(period_done)
enable = ~enable;
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 3.4
// \ \ Application : 7 Series FPGAs Transceivers Wizard
// / / Filename : srio_gen2_0_rx_startup_fsm.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Description : This module performs RX reset and initialization.
//
//
//
// Module srio_gen2_0_rx_startup_fsm
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
//
//
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//*****************************************************************************
`timescale 1ns / 1ps
`define DLY #1
module srio_gen2_0_RX_STARTUP_FSM #
(
parameter EXAMPLE_SIMULATION = 0, // Set to 1 for Simulation
parameter EQ_MODE = "DFE", //Rx Equalization Mode - Set to DFE or LPM
parameter STABLE_CLOCK_PERIOD = 8, //Period of the stable clock driving this state-machine, unit is [ns]
parameter RETRY_COUNTER_BITWIDTH = 8,
parameter TX_QPLL_USED = "FALSE", // the TX and RX Reset FSMs must
parameter RX_QPLL_USED = "FALSE", // share these two generic values
parameter PHASE_ALIGNMENT_MANUAL = "TRUE" // Decision if a manual phase-alignment is necessary or the automatic
// is enough. For single-lane applications the automatic alignment is
// sufficient
)
(
input wire STABLE_CLOCK, //Stable Clock, either a stable clock from the PCB
//or reference-clock present at startup.
input wire RXUSERCLK, //RXUSERCLK as used in the design
input wire SOFT_RESET, //User Reset, can be pulled any time
input wire QPLLREFCLKLOST, //QPLL Reference-clock for the GT is lost
input wire CPLLREFCLKLOST, //CPLL Reference-clock for the GT is lost
input wire QPLLLOCK, //Lock Detect from the QPLL of the GT
input wire CPLLLOCK, //Lock Detect from the CPLL of the GT
input wire RXRESETDONE,
input wire MMCM_LOCK,
input wire RECCLK_STABLE,
input wire RECCLK_MONITOR_RESTART,
input wire DATA_VALID,
input wire TXUSERRDY, //TXUSERRDY from GT
input wire DONT_RESET_ON_DATA_ERROR, //Used to control the Auto-Reset of FSM when Data Error is detected
output GTRXRESET ,
output MMCM_RESET ,
output reg QPLL_RESET = 1'b0, //Reset QPLL (only if RX usese QPLL)
output reg CPLL_RESET = 1'b0, //Reset CPLL (only if RX usese CPLL)
output RX_FSM_RESET_DONE, //Reset-sequence has sucessfully been finished.
output reg RXUSERRDY = 1'b0,
output wire RUN_PHALIGNMENT,
input wire PHALIGNMENT_DONE,
output reg RESET_PHALIGNMENT = 1'b0,
output reg RXDFEAGCHOLD = 1'b0,
output reg RXDFELFHOLD = 1'b0,
output reg RXLPMLFHOLD = 1'b0,
output reg RXLPMHFHOLD = 1'b0,
output wire [RETRY_COUNTER_BITWIDTH-1:0] RETRY_COUNTER // Number of
// Retries it took to get the transceiver up and running
);
//Interdependencies:
// * Timing depends on the frequency of the stable clock. Hence counters-sizes
// are calculated at design-time based on the Generics
//
// * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
// => signal which PLL has been reset
// *
localparam [3:0]
INIT = 4'b0000,
ASSERT_ALL_RESETS = 4'b0001,
WAIT_FOR_PLL_LOCK = 4'b0010,
RELEASE_PLL_RESET = 4'b0011,
VERIFY_RECCLK_STABLE = 4'b0100,
RELEASE_MMCM_RESET = 4'b0101,
WAIT_FOR_RXUSRCLK = 4'b0110,
WAIT_RESET_DONE = 4'b0111,
DO_PHASE_ALIGNMENT = 4'b1000,
MONITOR_DATA_VALID = 4'b1001,
FSM_DONE = 4'b1010;
reg [3:0] rx_state = INIT;
//This function decides how many clock-cycle need to be waited until
// a time-out occurs for bypassing the TX-Buffer
function [12:0] get_max_wait_bypass;
input manual_mode;
reg [12:0] max_wait_cnt;
begin
if (manual_mode == "TRUE")
max_wait_cnt = 5000;
else
max_wait_cnt = 3100;
get_max_wait_bypass = max_wait_cnt;
end
endfunction
localparam integer MMCM_LOCK_CNT_MAX = 1024;
localparam integer STARTUP_DELAY = 500;//AR43482: Transceiver needs to wait for 500 ns after configuration
localparam integer WAIT_CYCLES = STARTUP_DELAY / STABLE_CLOCK_PERIOD; // Number of Clock-Cycles to wait after configuration
localparam integer WAIT_MAX = WAIT_CYCLES + 10; // 500 ns plus some additional margin
localparam integer WAIT_TIMEOUT_2ms = 2000000 / STABLE_CLOCK_PERIOD; //2 ms time-out
localparam integer WAIT_TLOCK_MAX = 100000 / STABLE_CLOCK_PERIOD; //100 us time-out
localparam integer WAIT_TIMEOUT_500us = 500000 / STABLE_CLOCK_PERIOD; //500 us time-out
localparam integer WAIT_TIMEOUT_1us = 1000 / STABLE_CLOCK_PERIOD; //1 us time-out
localparam integer WAIT_TIMEOUT_100us = 100000 / STABLE_CLOCK_PERIOD; //100us time-out
integer WAIT_TIME_ADAPT = (37000000 /1.25)/STABLE_CLOCK_PERIOD;
localparam integer WAIT_TIME_MAX = EXAMPLE_SIMULATION? 100 : 10000 / STABLE_CLOCK_PERIOD;
reg [7:0] init_wait_count = 0;
reg init_wait_done = 1'b0;
reg pll_reset_asserted = 1'b0;
reg rx_fsm_reset_done_int = 1'b0;
wire rx_fsm_reset_done_int_s2;
reg rx_fsm_reset_done_int_s3 = 1'b0;
localparam integer MAX_RETRIES = 2**RETRY_COUNTER_BITWIDTH-1;
reg [7:0] retry_counter_int = 0;
reg [18:0] time_out_counter = 0;
reg [1:0] recclk_mon_restart_count = 0 ;
reg recclk_mon_count_reset = 0;
reg reset_time_out = 1'b0;
reg time_out_2ms = 1'b0; //--\Flags that the various time-out points
reg time_tlock_max = 1'b0; //--|have been reached.
reg time_out_500us = 1'b0; //--|
reg time_out_1us = 1'b0; //--|
reg time_out_100us = 1'b0; //--/
reg check_tlock_max = 1'b0;
reg [9:0] mmcm_lock_count = 1'b0;
reg mmcm_lock_int = 1'b0;
wire mmcm_lock_i;
reg mmcm_lock_reclocked = 1'b0;
reg run_phase_alignment_int = 1'b0;
wire run_phase_alignment_int_s2;
reg run_phase_alignment_int_s3 = 1'b0;
localparam integer MAX_WAIT_BYPASS = 5000;//5000 RXUSRCLK cycles is the max time for Multi Lane designs
reg [12:0] wait_bypass_count = 0;
reg time_out_wait_bypass = 1'b0;
wire time_out_wait_bypass_s2;
reg time_out_wait_bypass_s3 = 1'b0;
reg gtrxreset_i = 1'b0;
reg mmcm_reset_i = 1'b1;
reg rxpmaresetdone_i = 1'b0;
reg txpmaresetdone_i = 1'b0;
wire refclk_lost;
wire rxpmaresetdone_sync;
wire txpmaresetdone_sync;
wire rxpmaresetdone_s;
reg rxpmaresetdone_ss = 1'b0;
reg pmaresetdone_fallingedge_detect = 1'b0;
wire rxresetdone_s2;
reg rxresetdone_s3 = 1'b0;
wire data_valid_sync;
wire cplllock_sync;
wire qplllock_sync;
reg cplllock_ris_edge = 1'b0;
reg qplllock_ris_edge = 1'b0;
reg cplllock_prev;
reg qplllock_prev;
integer adapt_count = 0;
reg time_out_adapt = 1'b0;
reg adapt_count_reset = 1'b0;
reg [15:0] wait_time_cnt;
wire wait_time_done;
//Alias section, signals used within this module mapped to output ports:
assign RETRY_COUNTER = retry_counter_int;
assign RUN_PHALIGNMENT = run_phase_alignment_int;
assign RX_FSM_RESET_DONE = rx_fsm_reset_done_int;
assign GTRXRESET = gtrxreset_i;
assign MMCM_RESET = mmcm_reset_i;
always @(posedge STABLE_CLOCK or posedge SOFT_RESET)
begin
// The counter starts running when configuration has finished and
// the clock is stable. When its maximum count-value has been reached,
// the 500 ns from Answer Record 43482 have been passed.
if(SOFT_RESET)
begin
init_wait_count <= `DLY 8'h0;
init_wait_done <= `DLY 1'b0;
end
else if (init_wait_count == WAIT_MAX)
init_wait_done <= `DLY 1'b1;
else
init_wait_count <= `DLY init_wait_count + 1;
end
always @(posedge STABLE_CLOCK)
begin
//This counter monitors, how many retries the CDR Lock Detection
//runs. If during startup too many retries are necessary, the whole
//initialisation-process of the transceivers gets restarted.
if (recclk_mon_count_reset == 1)
recclk_mon_restart_count <= `DLY 0;
else if (RECCLK_MONITOR_RESTART == 1)
begin
if (recclk_mon_restart_count == 3)
recclk_mon_restart_count <= `DLY 0;
else
recclk_mon_restart_count <= `DLY recclk_mon_restart_count + 1;
end
end
generate
if(EXAMPLE_SIMULATION == 1)
begin
always @(posedge STABLE_CLOCK)
begin
time_out_adapt <= `DLY 1'b1;
end
end
else
begin
always @(posedge STABLE_CLOCK)
begin
if (adapt_count_reset == 1'b1)
begin
adapt_count <= `DLY 0;
time_out_adapt <= `DLY 1'b0;
end
else
begin
if (adapt_count == WAIT_TIME_ADAPT -1)
time_out_adapt <= `DLY 1'b1;
else
adapt_count <= `DLY adapt_count + 1;
end
end
end
endgenerate
always @(posedge STABLE_CLOCK)
begin
// One common large counter for generating three time-out signals.
// Intermediate time-outs are derived from calculated values, based
// on the period of the provided clock.
if (reset_time_out == 1)
begin
time_out_counter <= `DLY 0;
time_out_2ms <= `DLY 1'b0;
time_tlock_max <= `DLY 1'b0;
time_out_500us <= `DLY 1'b0;
time_out_1us <= `DLY 1'b0;
time_out_100us <= `DLY 1'b0;
end
else
begin
if (time_out_counter == WAIT_TIMEOUT_2ms)
time_out_2ms <= `DLY 1'b1;
else
time_out_counter <= `DLY time_out_counter + 1;
if (time_out_counter > WAIT_TLOCK_MAX && check_tlock_max == 1)
begin
time_tlock_max <= `DLY 1'b1;
end
if (time_out_counter == WAIT_TIMEOUT_500us)
begin
time_out_500us <= `DLY 1'b1;
end
if (time_out_counter == WAIT_TIMEOUT_1us)
begin
time_out_1us <= `DLY 1'b1;
end
if (time_out_counter == WAIT_TIMEOUT_100us)
begin
time_out_100us <= `DLY 1'b1;
end
end
end
always @(posedge STABLE_CLOCK)
begin
//The lock-signal from the MMCM is not immediately used but
//enabling a counter. Only when the counter hits its maximum,
//the MMCM is considered as "really" locked.
//The counter avoids that the FSM already starts on only a
//coarse lock of the MMCM (=toggling of the LOCK-signal).
if (mmcm_lock_i == 1'b0)
begin
mmcm_lock_count <= `DLY 0;
mmcm_lock_reclocked <= `DLY 1'b0;
end
else
begin
if (mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1)
mmcm_lock_count <= `DLY mmcm_lock_count + 1;
else
mmcm_lock_reclocked <= `DLY 1'b1;
end
end
//Clock Domain Crossing
srio_gen2_0_sync_block sync_run_phase_alignment_int
(
.clk (RXUSERCLK),
.data_in (run_phase_alignment_int),
.data_out (run_phase_alignment_int_s2)
);
srio_gen2_0_sync_block sync_rx_fsm_reset_done_int
(
.clk (RXUSERCLK),
.data_in (rx_fsm_reset_done_int),
.data_out (rx_fsm_reset_done_int_s2)
);
always @(posedge RXUSERCLK)
begin
run_phase_alignment_int_s3 <= `DLY run_phase_alignment_int_s2;
rx_fsm_reset_done_int_s3 <= `DLY rx_fsm_reset_done_int_s2;
end
srio_gen2_0_sync_block sync_time_out_wait_bypass
(
.clk (STABLE_CLOCK),
.data_in (time_out_wait_bypass),
.data_out (time_out_wait_bypass_s2)
);
srio_gen2_0_sync_block sync_RXRESETDONE
(
.clk (STABLE_CLOCK),
.data_in (RXRESETDONE),
.data_out (rxresetdone_s2)
);
srio_gen2_0_sync_block sync_mmcm_lock_reclocked
(
.clk (STABLE_CLOCK),
.data_in (MMCM_LOCK),
.data_out (mmcm_lock_i)
);
srio_gen2_0_sync_block sync_data_valid
(
.clk (STABLE_CLOCK),
.data_in (DATA_VALID),
.data_out (data_valid_sync)
);
srio_gen2_0_sync_block sync_cplllock
(
.clk (STABLE_CLOCK),
.data_in (CPLLLOCK),
.data_out (cplllock_sync)
);
srio_gen2_0_sync_block sync_qplllock
(
.clk (STABLE_CLOCK),
.data_in (QPLLLOCK),
.data_out (qplllock_sync)
);
always @(posedge STABLE_CLOCK)
begin
time_out_wait_bypass_s3 <= `DLY time_out_wait_bypass_s2;
rxresetdone_s3 <= `DLY rxresetdone_s2;
end
always @(posedge RXUSERCLK)
begin
if (run_phase_alignment_int_s3 == 1'b0)
begin
wait_bypass_count <= `DLY 0;
time_out_wait_bypass <= `DLY 1'b0;
end
else if ((run_phase_alignment_int_s3 == 1'b1) && (rx_fsm_reset_done_int_s3 == 1'b0))
begin
if (wait_bypass_count == MAX_WAIT_BYPASS - 1)
time_out_wait_bypass <= `DLY 1'b1;
else
wait_bypass_count <= `DLY wait_bypass_count + 1;
end
end
assign refclk_lost = ( RX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b1) ? 1'b1 :
( RX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b1) ? 1'b1 : 1'b0;
always @(posedge STABLE_CLOCK )
begin
if((rx_state == ASSERT_ALL_RESETS) |
(rx_state == RELEASE_MMCM_RESET))
begin
wait_time_cnt <= `DLY WAIT_TIME_MAX;
end else if (wait_time_cnt != 16'h0)
begin
wait_time_cnt <= wait_time_cnt - 16'h1;
end
end
assign wait_time_done = (wait_time_cnt == 16'h0);
//FSM for resetting the GTX/GTH/GTP in the 7-series.
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//
// Following steps are performed:
// 1) After configuration wait for approximately 500 ns as specified in
// answer-record 43482
// 2) Assert all resets on the GT and on an MMCM potentially connected.
// After that wait until a reference-clock has been detected.
// 3) Release the reset to the GT and wait until the GT-PLL has locked.
// 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
// Also get info from the TX-side which PLL has been reset.
// 5) Wait for the RESET_DONE-signal from the GT.
// 6) Signal to start the phase-alignment procedure and wait for it to
// finish.
// 7) Reset-sequence has successfully run through. Signal this to the
// rest of the design by asserting RX_FSM_RESET_DONE.
always @(posedge STABLE_CLOCK)
begin
if (SOFT_RESET == 1'b1)
//if (SOFT_RESET == 1'b1 || (rx_state != INIT && rx_state != ASSERT_ALL_RESETS && refclk_lost == 1'b1))
begin
rx_state <= `DLY INIT;
RXUSERRDY <= `DLY 1'b0;
gtrxreset_i <= `DLY 1'b0;
mmcm_reset_i <= `DLY 1'b0;
rx_fsm_reset_done_int <= `DLY 1'b0;
QPLL_RESET <= `DLY 1'b0;
CPLL_RESET <= `DLY 1'b0;
pll_reset_asserted <= `DLY 1'b0;
reset_time_out <= `DLY 1'b1;
retry_counter_int <= `DLY 0;
run_phase_alignment_int <= `DLY 1'b0;
check_tlock_max <= `DLY 1'b0;
RESET_PHALIGNMENT <= `DLY 1'b1;
recclk_mon_count_reset <= `DLY 1'b1;
adapt_count_reset <= `DLY 1'b1;
RXDFEAGCHOLD <= `DLY 1'b0;
RXDFELFHOLD <= `DLY 1'b0;
RXLPMLFHOLD <= `DLY 1'b0;
RXLPMHFHOLD <= `DLY 1'b0;
end
else
begin
case (rx_state)
INIT :
begin
//Initial state after configuration. This state will be left after
//approx. 500 ns and not be re-entered.
if (init_wait_done == 1'b1)
rx_state <= `DLY ASSERT_ALL_RESETS;
end
ASSERT_ALL_RESETS :
begin
//This is the state into which the FSM will always jump back if any
//time-outs will occur.
//The number of retries is reported on the output RETRY_COUNTER. In
//case the transceiver never comes up for some reason, this machine
//will still continue its best and rerun until the FPGA is turned off
//or the transceivers come up correctly.
if (RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "FALSE")
begin
if (pll_reset_asserted == 1'b0)
begin
QPLL_RESET <= `DLY 1'b1;
pll_reset_asserted <= `DLY 1'b1;
end
else
QPLL_RESET <= `DLY 1'b0;
end
else if (RX_QPLL_USED == "FALSE" && TX_QPLL_USED == "TRUE")
begin
if (pll_reset_asserted == 1'b0)
begin
CPLL_RESET <= `DLY 1'b1;
pll_reset_asserted <= `DLY 1'b1;
end
else
CPLL_RESET <= `DLY 1'b0;
end
RXUSERRDY <= `DLY 1'b0;
gtrxreset_i <= `DLY 1'b1;
mmcm_reset_i <= `DLY 1'b1;
run_phase_alignment_int <= `DLY 1'b0;
RESET_PHALIGNMENT <= `DLY 1'b1;
check_tlock_max <= `DLY 1'b0;
recclk_mon_count_reset <= `DLY 1'b1;
adapt_count_reset <= `DLY 1'b1;
if ((RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "FALSE" && qplllock_sync == 1'b0 && pll_reset_asserted) ||
(RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "TRUE" && cplllock_sync == 1'b0 && pll_reset_asserted) ||
(RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "TRUE" ) ||
(RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "FALSE" )
)
begin
rx_state <= `DLY WAIT_FOR_PLL_LOCK;
reset_time_out <= `DLY 1'b1;
end
end
WAIT_FOR_PLL_LOCK :
begin
if(wait_time_done)
rx_state <= `DLY RELEASE_PLL_RESET;
end
RELEASE_PLL_RESET :
begin
//PLL-Reset of the GTX gets released and the time-out counter
//starts running.
pll_reset_asserted <= `DLY 1'b0;
reset_time_out <= `DLY 1'b0;
if ((RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "FALSE" && qplllock_sync == 1'b1) ||
(RX_QPLL_USED == "FALSE" && TX_QPLL_USED == "TRUE" && cplllock_sync == 1'b1))
begin
rx_state <= `DLY VERIFY_RECCLK_STABLE;
reset_time_out <= `DLY 1'b1;
recclk_mon_count_reset <= `DLY 1'b0;
adapt_count_reset <= `DLY 1'b0;
end
else if ((RX_QPLL_USED == "TRUE" && qplllock_sync == 1'b1) ||
(RX_QPLL_USED == "FALSE" && cplllock_sync == 1'b1))
begin
rx_state <= `DLY VERIFY_RECCLK_STABLE;
reset_time_out <= `DLY 1'b1;
recclk_mon_count_reset <= `DLY 1'b0;
adapt_count_reset <= `DLY 1'b0;
end
if (time_out_2ms == 1'b1)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
begin
retry_counter_int <= `DLY retry_counter_int + 1;
end
rx_state <= `DLY ASSERT_ALL_RESETS;
end
end
VERIFY_RECCLK_STABLE :
begin
//reset_time_out <= `DLY '0';
//Time-out counter is not released in this state as here the FSM
//does not wait for a certain period of time but checks on the number
//of retries in the CDR PPM detector.
gtrxreset_i <= `DLY 1'b0;
if (RECCLK_STABLE == 1'b1)
begin
rx_state <= `DLY RELEASE_MMCM_RESET;
reset_time_out <= `DLY 1'b1;
end
if (recclk_mon_restart_count == 2)
begin
//If two retries are performed in the CDR "Lock" (=CDR PPM-detector)
//the whole initialisation-sequence gets restarted.
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
begin
retry_counter_int <= `DLY retry_counter_int + 1;
end
rx_state <= `DLY ASSERT_ALL_RESETS;
end
end
RELEASE_MMCM_RESET :
begin
//Release of the MMCM-reset. Waiting for the MMCM to lock.
check_tlock_max <= `DLY 1'b1;
mmcm_reset_i <= `DLY 1'b0;
reset_time_out <= `DLY 1'b0;
if (mmcm_lock_reclocked == 1'b1)
begin
rx_state <= `DLY WAIT_FOR_RXUSRCLK;
reset_time_out <= `DLY 1'b1;
end
if (time_tlock_max == 1'b1 && reset_time_out == 1'b0 )
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
begin
retry_counter_int <= `DLY retry_counter_int + 1;
end
rx_state <= `DLY ASSERT_ALL_RESETS;
end
end
WAIT_FOR_RXUSRCLK :
begin
if(wait_time_done)
rx_state <= `DLY WAIT_RESET_DONE;
end
WAIT_RESET_DONE :
begin
//When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
//If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
if(TXUSERRDY)
RXUSERRDY <= `DLY 1'b1;
reset_time_out <= `DLY 1'b0;
if (rxresetdone_s3 == 1'b1)
begin
rx_state <= `DLY DO_PHASE_ALIGNMENT;
reset_time_out <= `DLY 1'b1;
end
if (time_out_2ms == 1'b1 && reset_time_out == 1'b0)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
begin
retry_counter_int <= `DLY retry_counter_int + 1;
end
rx_state <= `DLY ASSERT_ALL_RESETS;
end
end
DO_PHASE_ALIGNMENT :
begin
//The direct handling of the signals for the Phase Alignment is done outside
//this state-machine.
RESET_PHALIGNMENT <= `DLY 1'b0;
run_phase_alignment_int <= `DLY 1'b1;
reset_time_out <= `DLY 1'b0;
if (PHALIGNMENT_DONE == 1'b1)
begin
rx_state <= `DLY MONITOR_DATA_VALID;
reset_time_out <= `DLY 1'b1;
end
if (time_out_wait_bypass_s3 == 1'b1)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
begin
retry_counter_int <= `DLY retry_counter_int + 1;
end
rx_state <= `DLY ASSERT_ALL_RESETS;
end
end
MONITOR_DATA_VALID :
begin
reset_time_out <= `DLY 1'b0;
if (data_valid_sync == 1'b0 && time_out_100us == 1'b1 && DONT_RESET_ON_DATA_ERROR == 1'b0 && reset_time_out == 1'b0)
begin
rx_state <= `DLY ASSERT_ALL_RESETS;
rx_fsm_reset_done_int <= `DLY 1'b0;
end
else if (data_valid_sync == 1'b1)
begin
rx_state <= `DLY FSM_DONE;
rx_fsm_reset_done_int <= `DLY 1'b0;
reset_time_out <= `DLY 1'b1;
end
end
FSM_DONE :
begin
reset_time_out <= `DLY 1'b0;
if (data_valid_sync == 1'b0)
begin
rx_fsm_reset_done_int <= `DLY 1'b0;
reset_time_out <= `DLY 1'b1;
rx_state <= `DLY MONITOR_DATA_VALID;
end
else if(time_out_1us == 1'b1 && reset_time_out == 1'b0)
rx_fsm_reset_done_int <= `DLY 1'b1;
if(time_out_adapt)
begin
if(EQ_MODE == "DFE")
begin
RXDFEAGCHOLD <= `DLY 1'b1;
RXDFELFHOLD <= `DLY 1'b1;
end
else
begin
RXDFEAGCHOLD <= `DLY 1'b0;
RXDFELFHOLD <= `DLY 1'b0;
RXLPMHFHOLD <= `DLY 1'b0;
RXLPMLFHOLD <= `DLY 1'b0;
end
end
end
default:
rx_state <= `DLY INIT;
endcase
end
end
endmodule
|
/*
Copyright (c) 2016-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* I2C for board management
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_125mhz_ibufg;
wire clk_125mhz_mmcm_out;
// Internal 125 MHz clock
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 625 MHz (in range)
// Divide by 5 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
wire i2c_scl_i;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_i;
wire i2c_sda_o;
wire i2c_sda_t;
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire [15:0] pcspma_status_vector;
wire pcspma_status_link_status = pcspma_status_vector[0];
wire pcspma_status_link_synchronization = pcspma_status_vector[1];
wire pcspma_status_rudi_c = pcspma_status_vector[2];
wire pcspma_status_rudi_i = pcspma_status_vector[3];
wire pcspma_status_rudi_invalid = pcspma_status_vector[4];
wire pcspma_status_rxdisperr = pcspma_status_vector[5];
wire pcspma_status_rxnotintable = pcspma_status_vector[6];
wire pcspma_status_phy_link_status = pcspma_status_vector[7];
wire [1:0] pcspma_status_remote_fault_encdg = pcspma_status_vector[9:8];
wire [1:0] pcspma_status_speed = pcspma_status_vector[11:10];
wire pcspma_status_duplex = pcspma_status_vector[12];
wire pcspma_status_remote_fault = pcspma_status_vector[13];
wire [1:0] pcspma_status_pause = pcspma_status_vector[15:14];
wire [4:0] pcspma_config_vector;
assign pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign pcspma_config_vector[3] = 1'b0; // isolate
assign pcspma_config_vector[2] = 1'b0; // power down
assign pcspma_config_vector[1] = 1'b0; // loopback enable
assign pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] pcspma_an_config_vector;
assign pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign pcspma_an_config_vector[9] = 1'b0; // reserved
assign pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign pcspma_an_config_vector[6] = 1'b0; // reserved
assign pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_ethernet_pcs_pma_0
eth_pcspma (
// SGMII
.txp (phy_sgmii_tx_p),
.txn (phy_sgmii_tx_n),
.rxp (phy_sgmii_rx_p),
.rxn (phy_sgmii_rx_n),
// Ref clock from PHY
.refclk625_p (phy_sgmii_clk_p),
.refclk625_n (phy_sgmii_clk_n),
// async reset
.reset (rst_125mhz_int),
// clock and reset outputs
.clk125_out (phy_gmii_clk_int),
.clk625_out (),
.clk312_out (),
.rst_125_out (phy_gmii_rst_int),
.idelay_rdy_out (),
.mmcm_locked_out (),
// MAC clocking
.sgmii_clk_r (),
.sgmii_clk_f (),
.sgmii_clk_en (phy_gmii_clk_en_int),
// Speed control
.speed_is_10_100 (pcspma_status_speed != 2'b10),
.speed_is_100 (pcspma_status_speed == 2'b01),
// Internal GMII
.gmii_txd (phy_gmii_txd_int),
.gmii_tx_en (phy_gmii_tx_en_int),
.gmii_tx_er (phy_gmii_tx_er_int),
.gmii_rxd (phy_gmii_rxd_int),
.gmii_rx_dv (phy_gmii_rx_dv_int),
.gmii_rx_er (phy_gmii_rx_er_int),
.gmii_isolate (),
// Configuration
.configuration_vector (pcspma_config_vector),
.an_interrupt (),
.an_adv_config_vector (pcspma_an_config_vector),
.an_restart_config (1'b0),
// Status
.status_vector (pcspma_status_vector),
.signal_detect (1'b1)
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* I2C
*/
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR3_4_V
`define SKY130_FD_SC_HS__XNOR3_4_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog wrapper for xnor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xnor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xnor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xnor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR3_4_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: Cmul.v
// /___/ /\ Timestamp: Mon May 1 10:30:08 2017
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Cmul.ngc /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Cmul.v
// Device : 3s500efg320-5
// Input file : /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Cmul.ngc
// Output file : /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Cmul.v
// # of Modules : 1
// Design Name : Cmul
// Xilinx : /opt/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module Cmul (
p, a
)/* synthesis syn_black_box syn_noprune=1 */;
output [7 : 0] p;
input [7 : 0] a;
// synthesis translate_off
wire [7 : 2] NlwRenamedSignal_a;
wire [6 : 6] NlwRenamedSignal_p;
assign
p[7] = NlwRenamedSignal_p[6],
p[6] = NlwRenamedSignal_p[6],
p[5] = NlwRenamedSignal_a[7],
p[4] = NlwRenamedSignal_a[6],
p[3] = NlwRenamedSignal_a[5],
p[2] = NlwRenamedSignal_a[4],
p[1] = NlwRenamedSignal_a[3],
p[0] = NlwRenamedSignal_a[2],
NlwRenamedSignal_a[7] = a[7],
NlwRenamedSignal_a[6] = a[6],
NlwRenamedSignal_a[5] = a[5],
NlwRenamedSignal_a[4] = a[4],
NlwRenamedSignal_a[3] = a[3],
NlwRenamedSignal_a[2] = a[2];
GND \blk00000001/blk00000002 (
.G(NlwRenamedSignal_p[6])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A221O_FUNCTIONAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_FUNCTIONAL_V |
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [7:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output r213f_enable,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output obc1_enable
);
parameter [2:0]
FEAT_MSU1 = 3,
FEAT_213F = 4
;
wire [23:0] SRAM_SNES_ADDR;
/* currently supported mappers:
Index Mapper
000 HiROM
001 LoROM
010 ExHiROM (48-64Mbit)
*/
/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
Offset 6000-7fff */
assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]));
assign IS_SAVERAM = SAVERAM_MASK[0]
&(((MAPPER == 3'b000
|| MAPPER == 3'b010)
? (!SNES_ADDR[22]
& SNES_ADDR[21]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
)
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd
* Offset 0000-7fff for ROM >= 32 MBit, otherwise 0000-ffff */
:(MAPPER == 3'b001)
? (&SNES_ADDR[22:20]
& (SNES_ADDR[19:16] < 4'b1110)
& (~SNES_ADDR[15] | ~ROM_MASK[21])
)
: 1'b0));
assign IS_WRITABLE = IS_SAVERAM;
assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
:(MAPPER == 3'b001)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[14:0]}
& SAVERAM_MASK)
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK))
:(MAPPER == 3'b010)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
& ROM_MASK))
: 24'b0);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_SEL = 1'b0;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign obc1_enable = (~SNES_ADDR[22]) & (SNES_ADDR[15:11] == 5'b01111);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A5A);
assign branch1_enable = (SNES_ADDR == 24'h002A13);
assign branch2_enable = (SNES_ADDR == 24'h002A4D);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp1(/*AUTOARG*/
// Outputs
scan_out, pcx_scache1_data_px_l,
// Inputs
shiftenable, scan_in, rclk, arbpc1_pcxdp_shift_px,
arbpc1_pcxdp_qsel1_pa, arbpc1_pcxdp_qsel0_pa,
arbpc1_pcxdp_q0_hold_pa, arbpc1_pcxdp_grant_pa, spc0_pcx_data_pa,
spc1_pcx_data_pa, spc2_pcx_data_pa, spc3_pcx_data_pa,
spc4_pcx_data_pa, spc5_pcx_data_pa, spc6_pcx_data_pa,
spc7_pcx_data_pa
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [7:0] scan_out; // From mac0 of pcx_dp_maca_r.v, ...
// End of automatics
output [`PCX_WIDTH-1:0] pcx_scache1_data_px_l; // From mac3 of pcx_dp_macc.v
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0] arbpc1_pcxdp_grant_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc1_pcxdp_q0_hold_pa;// To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc1_pcxdp_qsel0_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc1_pcxdp_qsel1_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc1_pcxdp_shift_px; // To mac0 of pcx_dp_maca_r.v, ...
input rclk; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] scan_in; // To mac0 of pcx_dp_maca_r.v, ...
input shiftenable; // To mac7 of pcx_dp_maca_l.v
// End of automatics
input [`PCX_WIDTH-1:0] spc0_pcx_data_pa; // To mac0 of pcx_dp_maca.v
input [`PCX_WIDTH-1:0] spc1_pcx_data_pa; // To mac1 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc2_pcx_data_pa; // To mac2 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc3_pcx_data_pa; // To mac3 of pcx_dp_macc.v
input [`PCX_WIDTH-1:0] spc4_pcx_data_pa; // To mac4 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc5_pcx_data_pa; // To mac5 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc6_pcx_data_pa; // To mac6 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc7_pcx_data_pa; // To mac7 of pcx_dp_maca.v
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [129:0] pcx_col0_data_px_l; // From mac0 of pcx_dp_maca_r.v
wire [129:0] pcx_col1_data_px_l; // From mac1 of pcx_dp_macb_r.v
wire [129:0] pcx_col2_data_px_l; // From mac2 of pcx_dp_macb_r.v
wire [129:0] pcx_col4_data_px_l; // From mac4 of pcx_dp_macb_l.v
wire [129:0] pcx_col5_data_px_l; // From mac5 of pcx_dp_macb_l.v
wire [129:0] pcx_col6_data_px_l; // From mac6 of pcx_dp_macb_l.v
wire [129:0] pcx_col7_data_px_l; // From mac7 of pcx_dp_maca_l.v
wire [7:1] shiftenable_buf; // From mac1 of pcx_dp_macb_r.v, ...
// End of automatics
wire [5:0] unused;
/*
// DATAPATH ORGANISATION(pcx_dp1)
sparc0 sparc1 sparc2 sparc3 sparc4 sparc5 sparc6 sparc7
| | | | | | | |
v v v v v v v v
mac0 -> mac1 ->mac2 ->mac3 <- mac4 <- mac5 <- mac6 <- mac7
(new)ar br br cr bl bl bl al
(old)a b c b b b b a
|
v
to sctag1
*/
/*
pcx_dp_maca_r AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_maca_r mac0(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col0_data_px_l[129:0]), // Templated
.scan_out (scan_out[0]), // Templated
.shiftenable_buf (), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[0]), // Templated
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[0]), // Templated
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[0]), // Templated
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[0]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[0]), // Templated
.src_pcx_data_pa ({6'b000000,spc0_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.rclk (rclk),
.scan_in (scan_in[0]), // Templated
.shiftenable (shiftenable_buf[1])); // Templated
/*
pcx_dp_macb_r AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_prev_px_l (pcx_col@"(- @ 1)"_data_px_l[129:0]),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macb_r mac1(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col1_data_px_l[129:0]), // Templated
.scan_out (scan_out[1]), // Templated
.shiftenable_buf (shiftenable_buf[1]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[1]), // Templated
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[1]), // Templated
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[1]), // Templated
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[1]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[1]), // Templated
.src_pcx_data_pa ({6'b000000,spc1_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col0_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[1]), // Templated
.shiftenable (shiftenable_buf[2])); // Templated
pcx_dp_macb_r mac2(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col2_data_px_l[129:0]), // Templated
.scan_out (scan_out[2]), // Templated
.shiftenable_buf (shiftenable_buf[2]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[2]), // Templated
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[2]), // Templated
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[2]), // Templated
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[2]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[2]), // Templated
.src_pcx_data_pa ({6'b000000,spc2_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col1_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[2]), // Templated
.shiftenable (shiftenable_buf[3])); // Templated
/*
pcx_dp_macc_r AUTO_TEMPLATE(
// Outputs
.data_out_px_l ({unused[5:0],pcx_scache1_data_px_l[`PCX_WIDTH-1:0]}),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_crit_px_l (pcx_col@"(+ @ 1)"_data_px_l[129:0]),
.data_ncrit_px_l(pcx_col@"(- @ 1)"_data_px_l[129:0]),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macc_r mac3(/*AUTOINST*/
// Outputs
.data_out_px_l ({unused[5:0],pcx_scache1_data_px_l[`PCX_WIDTH-1:0]}), // Templated
.scan_out (scan_out[3]), // Templated
.shiftenable_buf (shiftenable_buf[3]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[3]), // Templated
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[3]), // Templated
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[3]), // Templated
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[3]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[3]), // Templated
.src_pcx_data_pa ({6'b000000,spc3_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_crit_px_l (pcx_col4_data_px_l[129:0]), // Templated
.data_ncrit_px_l (pcx_col2_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[3]), // Templated
.shiftenable (shiftenable_buf[4])); // Templated
/*
pcx_dp_macb_l AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_prev_px_l (pcx_col@"(+ @ 1)"_data_px_l[129:0]),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macb_l mac4(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col4_data_px_l[129:0]), // Templated
.scan_out (scan_out[4]), // Templated
.shiftenable_buf (shiftenable_buf[4]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[4]), // Templated
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[4]), // Templated
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[4]), // Templated
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[4]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[4]), // Templated
.src_pcx_data_pa ({6'b000000,spc4_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col5_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[4]), // Templated
.shiftenable (shiftenable_buf[5])); // Templated
pcx_dp_macb_l mac5(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col5_data_px_l[129:0]), // Templated
.scan_out (scan_out[5]), // Templated
.shiftenable_buf (shiftenable_buf[5]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[5]), // Templated
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[5]), // Templated
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[5]), // Templated
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[5]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[5]), // Templated
.src_pcx_data_pa ({6'b000000,spc5_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col6_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[5]), // Templated
.shiftenable (shiftenable_buf[6])); // Templated
pcx_dp_macb_l mac6(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col6_data_px_l[129:0]), // Templated
.scan_out (scan_out[6]), // Templated
.shiftenable_buf (shiftenable_buf[6]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[6]), // Templated
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[6]), // Templated
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[6]), // Templated
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[6]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[6]), // Templated
.src_pcx_data_pa ({6'b000000,spc6_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col7_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[6]), // Templated
.shiftenable (shiftenable_buf[7])); // Templated
/*
pcx_dp_maca_l AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable));
*/
pcx_dp_maca_l mac7(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col7_data_px_l[129:0]), // Templated
.scan_out (scan_out[7]), // Templated
.shiftenable_buf (shiftenable_buf[7]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[7]), // Templated
.arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[7]), // Templated
.arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[7]), // Templated
.arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[7]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[7]), // Templated
.src_pcx_data_pa ({6'b000000,spc7_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.rclk (rclk),
.scan_in (scan_in[7]), // Templated
.shiftenable (shiftenable)); // Templated
// Code start here
//
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
endmodule
|
// Memory configuration map
module memcfg(
input clk,
input reset,
output reset_hold,
input s,
input [0:7] cfg_page,
input [0:7] cfg_frame,
input [0:7] page,
output cfgok,
output [0:7] frame,
output pvalid
);
parameter MODULE_ADDR_WIDTH;
parameter FRAME_ADDR_WIDTH;
/*
Memory configuration: "OU r, n": OU=s_, r=rdt_, n=ad_
page -------- segment ------- frame module 1
rrrr rrrrrrrr rrrr nnnnnnn nnnn nnnn n
NOTE: frame address is 3 bits long for Elwro 32K modules
*/
// --- address selector ----------------------------------------------------
wire [0:7] addr;
always @ (*) begin
case ({reset, s})
2'b00: addr = page; // memory read
2'b01: addr = cfg_page; // memory configuration
2'b10: addr = clr_cnt; // map reset
2'b11: addr = clr_cnt; // map reset
endcase
end
// --- memory map initialization -------------------------------------------
initial begin
reg [8:0] i;
for (i=0 ; i<9'd256 ; i=i+9'd1) begin
if (i == 1) map[i] = 1;
else map[i] = 0;
end
end
// --- frame[page] memory map ----------------------------------------------
reg map_wr = 0;
reg [0:7] rd_addr;
reg [0:7] map [0:255] /* synthesis ramstyle = "M4K" */;
always @ (posedge clk) begin
if (map_wr) map[addr] <= cfg_frame & frame_clear;
rd_addr <= addr;
end
assign frame = map[rd_addr];
// --- configuration process -----------------------------------------------
localparam mmask = 2**MODULE_ADDR_WIDTH - 1;
localparam fmask = 2**FRAME_ADDR_WIDTH - 1;
localparam [3:0] frame_addr_mask = fmask[3:0];
localparam [3:0] module_addr_mask = mmask[3:0];
localparam [7:0] invalidity_mask = ~{module_addr_mask, frame_addr_mask};
assign pvalid = (addr < 2) || (frame != 0);
wire frame_addr_valid = (cfg_frame & invalidity_mask) == 8'd0;
wire cfg_cmd_valid = s && (cfg_page > 1) && frame_addr_valid;
localparam CIDLE = 3'd0;
localparam CCFG = 3'd1;
localparam COK = 3'd2;
localparam RESET = 3'd3;
localparam CLEAR = 3'd4;
reg [2:0] cstate = CIDLE;
reg [7:0] clr_cnt;
reg [7:0] frame_clear;
assign reset_hold = (cstate == CLEAR) | (cstate == RESET);
always @ (posedge clk) begin
if (reset & ~reset_hold) cstate <= RESET;
else case (cstate)
CIDLE: begin
frame_clear <= 8'hff;
if (cfg_cmd_valid) begin
map_wr <= 1;
cstate <= CCFG;
end
end
CCFG: begin
map_wr <= 0;
cfgok <= 1;
cstate <= COK;
end
COK: begin
if (~s) begin
cfgok <= 0;
cstate <= CIDLE;
end
end
RESET: begin
clr_cnt <= 2;
map_wr <= 1;
frame_clear <= 8'd0;
cstate <= CLEAR;
end
CLEAR: begin
if (clr_cnt == 8'hff) begin
cstate <= CIDLE;
map_wr <= 0;
end else begin
clr_cnt <= clr_cnt + 1'b1;
end
end
endcase
end
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_1_V
`define SKY130_FD_SC_LP__EINVN_1_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_1 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_1_V
`define SKY130_FD_SC_LS__O41A_1_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41a_1 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41a_1 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_1_V
|
/*
* usart.v - Serial interface to supervisor chip
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
`define BAUD 115200
`define CLOCK 48000000
//(`CLOCK/`BAUD)
//`define SPAN 103
`define SPAN (`CLOCK/`BAUD)
module usart #(
parameter fifo_log2 = 9,
parameter divisor = `SPAN
) (
// Uart signals
output tx_o,
input rx_i,
// Bus signals
input n_reset_i,
input busclk_i, // Clock for bus signals
input [3:0] A_i, // Only 2 registers, buffer(0) and status(1)
input [7:0] D_i,
output [7:0] D_o,
input nWR_i,
input nRD_i,
// Host interrupt, cleared by a read to the status register
output interrupt_o,
// DMA interface for Initial Program Load
input dma_en_i, // DMA enable
output [15:0] dma_adr_o, // DMA address
output [7:0] dma_dat_o,
output dma_wr_o // To memory
);
// Wire definitions ===========================================================================
wire dma_rd, dma_reset_n;
wire [7:0] outbound_data, inbound_data, status_reg;
wire inbound_empty, outbound_empty, outbound_full, inbound_full;
wire rx_fall, rx;
wire inb_read_data;
// Registers ==================================================================================
reg clear_buffers; // Buffer reset flag
reg interrupt; // Interrupt flag
reg rd = 0, wr = 0; // Read and write flags
reg [15:0] inbound_timer = 0, outbound_timer = 0;
reg [3:0] inbound_counter = 0, outbound_counter = 0;
// Edge tracking and synchronizer chain
reg [3:0] track_rx = 4'b1111;
// Inbound Registers
reg [7:0] rdr = 0; // Receive data register, dont record stop bit
// Outbound Registers
reg [9:0] sdr = 10'b1111111111; // Send data register
// Assignments ================================================================================
assign D_o = (A_i[0] == 0) ? inbound_data : status_reg; // Data register or status register based on LSB
assign status_reg = {4'b1111,outbound_full,outbound_empty,inbound_full,inbound_empty};
assign interrupt_o = interrupt;
assign rx_fall = (track_rx[3:2] == 2'b10);
assign rx = track_rx[2];
assign inb_read_data = !nRD_i && (A_i[0] == 0);
// Module connections =========================================================================
// Normalise the CPU signals, RD only active for one cycle, starting on negedge
// Delay the read signal by 2 clocks, then current state AND delayed state will overlap on only one clock
reg [1:0] track_rd = 2'b00;
reg inb_rd = 0;
always @(posedge busclk_i) track_rd <= {track_rd[0],inb_read_data};
always @(negedge busclk_i) inb_rd <= (inb_rd) ? 1'b0 : (track_rd[1] & inb_read_data);
// Inbound FIFO
fifo #(
.log2_addr(fifo_log2),
.data_width(8)
) inbound (
.n_reset_i(!clear_buffers & dma_reset_n), // Reset on request or DMA start
.rclk_i(busclk_i),
.data_i(rdr),
.wclk_i(busclk_i),
.wr_i(wr),
.data_o(inbound_data),
.rd_i(inb_rd | dma_rd), // Read - when RD goes low
.fifo_empty_o(inbound_empty),
.fifo_full_o(inbound_full)
);
// Outbound FIFO
fifo #(
.log2_addr(fifo_log2),
.data_width(8)
) outbound (
.n_reset_i(!clear_buffers),
.wclk_i(busclk_i),
.data_i(D_i),
.wr_i(!nWR_i & (A_i[0] == 0)), // Only write when addressing the outbound reg
.rclk_i(busclk_i),
.data_o(outbound_data),
.rd_i(rd),
.fifo_empty_o(outbound_empty),
.fifo_full_o(outbound_full)
);
// =============================================================
// Support memory DMA in from SPI - allows in-system programming
// =============================================================
support_dma support_dma(
.clk_i(busclk_i),
.n_reset_o( dma_reset_n ),
.enable_i(dma_en_i),
.d_avail_i(!inbound_empty),
.data_i( inbound_data ),
.adr_o( dma_adr_o ),
.data_o( dma_dat_o ),
.wr_o(dma_wr_o),
.rd_o(dma_rd)
);
// Control ============================================================
// Delay the reset signal for the outbound logic as read has to happen before engine starts
// reg [1:0] delayed_reset = 0;
// always @(negedge busclk_i) delayed_reset <= {delayed_reset[0],n_reset_i};
// wire delayed_reset_sig = delayed_reset[1];
// Delay the outbound_empty signal for the outbound logic as read has to happen before engine starts transmitting
reg delayed_read = 0;
always @(posedge busclk_i) delayed_read <= rd;
reg delayed_read2 = 0;
always @(negedge busclk_i) delayed_read2 <= delayed_read;
// Outbound logic =================================================
always @(posedge busclk_i)
begin
if( n_reset_i & dma_reset_n)
begin
// Outbound timer
if( outbound_timer != 0 )
outbound_timer <= outbound_timer - 1'b1;
else begin
// Outbound counter
if( outbound_counter != 0 )
begin
outbound_counter <= outbound_counter - 1'b1;
outbound_timer <= divisor;
sdr <= {1'd1,sdr[9:1]}; // Move to the next bit, fill with 1's
end
else
begin
if( delayed_read2 )
begin
outbound_counter <= 4'd9; // Send 10 bits, including framing
outbound_timer <= divisor; // Sample every bit width
sdr <= {1'b1,outbound_data,1'b0}; // Send outbound framed by start and stop bits
end
end
end
end
else begin // Abort any transmission
outbound_timer <= 0;
outbound_counter <= 0;
end
end
// Outbound memory read - if RD is high then make it low, then cycle starting will prevent RD signal from rising again
always @(negedge busclk_i)
rd <= ( rd ) ? 1'b0 : ((outbound_timer == 16'd0) && (outbound_counter == 4'd0) && n_reset_i && !outbound_empty);
// Outbound transmit line
assign tx_o = sdr[0];
// Inbound logic ============================================
// Synchronize and track the received signal
always @(posedge busclk_i) track_rx <= {track_rx[2:0], rx_i};
always @(negedge busclk_i)
begin
if( n_reset_i & dma_reset_n)
begin
// inbound timer
if( inbound_timer != 0 )
inbound_timer <= inbound_timer - 1'b1;
else begin
// inbound counter
if( inbound_counter != 0 )
begin
inbound_counter <= inbound_counter - 1'b1;
inbound_timer <= divisor;
rdr <= {rx,rdr[7:1]}; // Sample to the next bit
end
else
begin
if( rx_fall ) // Start the process on the first fall
begin
inbound_counter <= 4'd9; // Receive 10 bits, including framing
inbound_timer <= (divisor>>1); // Sample every bit width, starting at half bit width
end
end
end
end
else begin // Abort any reception
inbound_timer <= 0;
inbound_counter <= 0;
end
end
// Inbound memory write logic
reg [1:0] track_finish = 2'b11;
always @(posedge busclk_i) track_finish <= {track_finish[0],((inbound_timer == 16'd0) && (inbound_counter==0))};
always @(negedge busclk_i) wr <= (track_finish == 2'b01);
// Other logic ================================================================================
// Clear the buffers
reg [1:0] track_clear;
wire rs = !nWR_i & (A_i[0] == 1'b1) & D_i[7];
always @(posedge busclk_i) track_clear <= {track_clear[0],rs};
always @(negedge busclk_i) clear_buffers <= (track_clear == 2'b01);
// ================================================================================
// Interrupt line - registered
// ================================================================================
reg [15:0] old_reg = 0;
always @(negedge busclk_i) old_reg <= {old_reg[7:0],status_reg}; // Shift down 8 bits
always @(posedge busclk_i) interrupt = (old_reg[15:8] != status_reg);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32AI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O32AI_BEHAVIORAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32AI_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////////////////
// Company: LKB
// Engineer: Leonhard Neuhaus
//
// Create Date: 12.08.2015 17:40:42
// Design Name:
// Module Name: i_adv_trigger
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
// Usage of the module:
// feed the on_clockcycles into hysteresis_i
// feed the raw trigger input into trig_i
// connect trig_o to the device to be triggered
// optionally set invert flag and the flag rearm_i if you want the trigger to rearm by itself
// set reset flag to true to reset the trigger. set it then to false to arm it.
// once trig_i goes high, trig_o will remain high for hysteresis_i cycles and then go low
// if the rearl_i flag is set, trigger will automatically rearm
// otherwise, reset must be manually set to true and then to false to rearm the trigger
module red_pitaya_adv_trigger #(
parameter COUNTERSZ = 64
)
(
input dac_clk_i,
input reset_i,
input trig_i,
output trig_o,
input rearm_i,
input invert_i,
input [COUNTERSZ-1:0] hysteresis_i //stay on for hysteresis_i cycles
);
reg [COUNTERSZ-1:0] counter;
reg triggered;
reg armed;
always @(posedge dac_clk_i) begin
//reset
if (reset_i == 1'b1) begin
triggered <= 1'b0;
armed <= 1'b1;
counter <= hysteresis_i;
end
//system is armed, and therefore copies the incident trigger
else if (armed&(!triggered)) begin
triggered <= trig_i;
counter <= hysteresis_i;
end
//system has been triggered in a previous cycle
else if (triggered) begin
if ( counter != {COUNTERSZ{1'b0}} ) //normal countdown in progress, nothing to change
counter <= counter - {{COUNTERSZ-1{1'b0}},1'b1};
else begin //countdown arrived at zero
if (rearm_i) begin //automatic rearming is configured
triggered <= trig_i; // prepare for the next trigger. This can already happen next cycle, i.e. without interruption
armed <= 1'b1; //
counter <= hysteresis_i; //reset the counter nevertheless
end
else begin //no auto rearm. Stall the trigger until it is reset
triggered <= 1'b0; //un-trigger
armed <= 1'b0; //un-arm
//counter <= hysteresis_i
end
end
end
end
assign trig_o = reset_i ? trig_i : (invert_i ^ triggered);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVPWRVGND_BLACKBOX_V
`define SKY130_FD_SC_MS__TAPVPWRVGND_BLACKBOX_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVPWRVGND_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 10:40:00 09/11/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #3 Project
// Module Name: TF_CLS_LED_Output_Fader
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: CLS LED Output Fader Test Bench
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_CLS_LED_Output_Fader();
//
// System Clock Emulation
//
// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal
//
localparam CLK_RATE_HZ = 50000000; // Hz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * 1000000000.0) / 2.0; // ns
reg CLOCK_50;
initial
begin
CLOCK_50 = 1'b0;
forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
end
//
// Unit Under Test: CLS_LED_Output_Fader
//
reg LED_FULL_ON;
wire [6:0] PWM_CHANNEL_SIGS;
wire PWM_TIMER_TICK;
wire FADE_TIMER_TICK;
wire LEDR;
CLS_LED_Output_Fader uut
(
// Input Signals
.LED_FULL_ON( LED_FULL_ON ),
.PWM_CHANNEL_SIGS( PWM_CHANNEL_SIGS ),
.PWM_TIMER_TICK( PWM_TIMER_TICK ),
.FADE_TIMER_TICK( FADE_TIMER_TICK ),
// Output Signals
.LEDR( LEDR ),
// System Signals
.CLK( CLOCK_50 )
);
//
// Fadeout Timer Emulation
//
// Use the CLS_Fadeout_Timer module to generate the FADE_TIMER_TICK
//
localparam FADE_RATE_HZ = 10000; // 10 kHz
CLS_Fadeout_Timer
#(
.CLK_RATE_HZ( CLK_RATE_HZ ),
.FADE_RATE_HZ( FADE_RATE_HZ )
)
fadeout_timer
(
// Output Signals
.FADEOUT_TICK( FADE_TIMER_TICK ),
// System Signals
.CLK( CLOCK_50 )
);
//
// PWM Channel Emulation
//
// Generate PWM waveform signals for each PWM channel
//
localparam PWM_DUTY_RATE = 100000; // 100 kHz
//
// PWM Interval Timer
//
CLS_PWM_Interval_Timer
#(
.CLK_RATE_HZ( CLK_RATE_HZ ), // Hz
.DUTY_RATE_HZ( PWM_DUTY_RATE ) // Hz
)
pwm_interval_timer
(
// Output Signals
.PWM_TICK( PWM_TIMER_TICK ),
// System Signals
.CLK( CLOCK_50 )
);
//
// PWM Duty Cycle Timer (one per LED channel)
//
// Note: A generate block is used here to simplify instantiating 8
// instances of the same module.
//
localparam [7*7-1:0] PWM_DutyCycle_List = { 7'd100, 7'd50, 7'd25, 7'd13, 7'd6, 7'd3, 7'd1 };
genvar i; // General purpose variable used by generate for loops
generate
begin
for (i=0; i < 7; i=i+1)
begin : PWM_Channels
//
// PWM Duty Cycle Timer
//
CLS_PWM_DutyCycle_Timer
#(
.CLK_RATE_HZ( CLK_RATE_HZ ), // MHz
.DUTY_RATE_HZ( PWM_DUTY_RATE ), // Hz
.DUTY_PERCENT( PWM_DutyCycle_List[7*i +:7] ) // Cycle On-time %
)
pwm_dutycycle_timer
(
// Input Signals
.PWM_INTERVAL_TICK( PWM_TIMER_TICK ),
// Output Signals
.PWM_OUT( PWM_CHANNEL_SIGS[i] ),
// System Signals
.CLK( CLOCK_50 )
);
end
end
endgenerate
//
// Test Stimulus
//
initial
begin
// Initialize Signals
LED_FULL_ON = 1'b0;
#1000;
//
// Begin Testing
//
// Wait for two PWM Timer cycles
@(posedge PWM_TIMER_TICK);
@(posedge PWM_TIMER_TICK);
// Activate the LED for one Fade Timer cycle
@(posedge CLOCK_50); // Align input signals with Clock
LED_FULL_ON = 1'b1;
@(posedge FADE_TIMER_TICK);
// Deassert the LED_FULL_ON signal
@(posedge CLOCK_50);
LED_FULL_ON = 1'b0;
// Verify Fadeout Sequence
//
// Simulate 1 mS of time for full sequence
end
endmodule
|
module emesh_readback (/*AUTOARG*/
// Outputs
ready_out, access_out, packet_out,
// Inputs
nreset, clk, access_in, packet_in, read_data, ready_in
);
parameter AW = 32; // address width
parameter PW = 104; // packet width
//clk, reset
input nreset; // asynchronous active low reset
input clk; // clock
// input transaction
input access_in; // register access
input [PW-1:0] packet_in; // data/address
output ready_out; // pushback from mesh
// register/memory data (already pipelined)
input [63:0] read_data; // data from register/memory
// output transaction
output access_out; // register access
output [PW-1:0] packet_out; // data/address
input ready_in; // pushback from mesh
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [12:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
reg [1:0] datamode_out;
reg [4:0] ctrlmode_out;
reg [AW-1:0] dstaddr_out;
wire [AW-1:0] data_out;
wire [AW-1:0] srcaddr_out;
reg access_out;
//########################################
//# Parse packet
//#######################################
packet2emesh #(.AW(AW),
.PW(PW))
p2e (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[12:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
//########################################
//# Pipeline
//#######################################
//access
always @ (posedge clk or negedge nreset)
if(!nreset)
access_out <= 1'b0;
else if(ready_in)
access_out <= access_in & ~write_in;
//packet
always @ (posedge clk)
if(ready_in & access_in & ~write_in)
begin
datamode_out[1:0] <= datamode_in[1:0];
ctrlmode_out[4:0] <= ctrlmode_in[4:0];
dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
end
assign data_out[AW-1:0] = read_data[31:0];
assign srcaddr_out[AW-1:0] = read_data[63:32];
//ready signal
assign ready_out = ready_in;
//########################################
//# Convert to Packet
//#######################################
emesh2packet #(.AW(AW),
.PW(PW))
e2p (.write_out (1'b1),
/*AUTOINST*/
// Outputs
.packet_out (packet_out[PW-1:0]),
// Inputs
.datamode_out (datamode_out[1:0]),
.ctrlmode_out (ctrlmode_out[12:0]),
.dstaddr_out (dstaddr_out[AW-1:0]),
.data_out (data_out[AW-1:0]),
.srcaddr_out (srcaddr_out[AW-1:0]));
endmodule // emesh_readback
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End:
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:30 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_0_sim_netlist.v
// Design : zynq_design_1_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg484" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "zynq_design_1_processing_system7_0_0.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
(* CHECK_LICENSE_TYPE = "zynq_design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIGGER_IN_0 TRIG" *) input FTMT_F2P_TRIG_0;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIGGER_IN_0 ACK" *) output FTMT_F2P_TRIGACK_0;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIGGER_OUT_0 ACK" *) input FTMT_P2F_TRIGACK_0;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIGGER_OUT_0 TRIG" *) output FTMT_P2F_TRIG_0;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIG_0;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIG_0;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "zynq_design_1_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(FTMT_F2P_TRIGACK_0),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(FTMT_F2P_TRIG_0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(FTMT_P2F_TRIGACK_0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(FTMT_P2F_TRIG_0),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_TB_V
`define SKY130_FD_SC_HD__A211OI_TB_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a211oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__a211oi dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_TB_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: async_fifo_256x72_to_36.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module async_fifo_256x72_to_36 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull);
input aclr;
input [71:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [35:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [35:0] sub_wire1;
wire sub_wire2;
wire [8:0] sub_wire3;
wire wrfull = sub_wire0;
wire [35:0] q = sub_wire1[35:0];
wire rdempty = sub_wire2;
wire [8:0] rdusedw = sub_wire3[8:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.rdusedw (sub_wire3),
.rdfull (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Stratix IV",
dcfifo_mixed_widths_component.lpm_numwords = 256,
dcfifo_mixed_widths_component.lpm_showahead = "ON",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 72,
dcfifo_mixed_widths_component.lpm_widthu = 8,
dcfifo_mixed_widths_component.lpm_widthu_r = 9,
dcfifo_mixed_widths_component.lpm_width_r = 36,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 3,
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "72"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "36"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "36"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL "q[35..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 36 0 @q 0 0 36 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`include "registroDesplazable.v"
`include "startStop.v"
`include "i2cSlave.v"
`include "tcpci.v"
`include "clock.v"
module test_registros;
wire Start_tHardResetComplete_timer;
wire Request_PHY_to_Send_Hard_Reset;
wire Request_PHY_to_Send_Cable_Reset;
wire Stop_PHY_attempting_to_send_Hard_Reset;
wire Stop_PHY_attempting_to_send_Cable_Reset;
wire Stop_tHardResetComplete_timer;
wire Start_CRCReceiveTimer;
wire Stop_CRCReceiverTimer;
wire MessageIDCounter;
wire MessageID;
wire MessageID_mismatch;
wire SOP_mismatch;
wire MessageID_SOP_match;
wire [7:0] TRANSMIT_BYTE_COUNT;
wire [7:0] TRANSMIT_HEADER_LOW;
wire [7:0] TRANSMIT_HEADER_HIGH;
wire [7:0] TRANSMIT_DATA_OBJECTS;
wire [7:0] I2C_slave_reg_out;
wire [7:0] ALERT_LOW;
reg tHard_Reset_Complete_expires;
reg Hard_Reset_sent;
reg Cable_Reset_sent;
reg tHardResetComplete_expires;
reg PRL_Rx_Message_Discard;
reg Hard_Reset_received;
reg Cable_Reset_received;
reg RetryCounter;
reg CRCReceiveTimer_Timeout;
reg GoodCRC_Response_from_PHY;
reg Message_discarded_bus_Idle;
reg [7:0] I2C_slave_reg_in;
reg [7:0] I2C_slave_reg_addr;
reg I2C_slave_reg_in_enb;
reg reset;
wire clk;
///I2C
/// creacion del i2c, concetar lo que es requerido
wire pull_Down;
wire [2:0] cuenta;
wire [8:0] estado;
wire read_write;
reg ir_ri2_enb;
wire [7:0] ow_ri2_out_data;
reg [7:0] ir_ri2_in_data, ir_ri2_address;
reg SCL,SDA;
clock c(clk);
tcpci TCPCI(Start_tHardResetComplete_timer, Request_PHY_to_Send_Hard_Reset, Request_PHY_to_Send_Cable_Reset, Stop_PHY_attempting_to_send_Hard_Reset, Stop_PHY_attempting_to_send_Cable_Reset, Stop_tHardResetComplete_timer, Start_CRCReceiveTimer, Stop_CRCReceiverTimer, MessageIDCounter, MessageID, MessageID_mismatch, SOP_mismatch, MessageID_SOP_match, TRANSMIT_BYTE_COUNT, TRANSMIT_HEADER_LOW, TRANSMIT_HEADER_HIGH, TRANSMIT_DATA_OBJECTS, I2C_slave_reg_out, ALERT_LOW, tHard_Reset_Complete_expires, Hard_Reset_sent, Cable_Reset_sent, tHardResetComplete_expires, PRL_Rx_Message_Discard, Hard_Reset_received, Cable_Reset_received, RetryCounter, CRCReceiveTimer_Timeout, GoodCRC_Response_from_PHY, Message_discarded_bus_Idle, I2C_slave_reg_in, I2C_slave_reg_addr, I2C_slave_reg_in_enb, reset, clk);
i2cSlave i2c_Slave(reset,SCL,SDA,pull_Down,ir_ri2_address,ir_ri2_enb,read_write,ow_ri2_out_data,ir_ri2_in_data,estado,cuenta);
initial
begin
$dumpfile("test_registros.vcd");
$dumpvars;
tHard_Reset_Complete_expires=0;
Hard_Reset_sent=0;
Cable_Reset_sent=0;
tHardResetComplete_expires=0;
PRL_Rx_Message_Discard=0;
Hard_Reset_received=0;
Cable_Reset_received=0;
RetryCounter=0;
CRCReceiveTimer_Timeout=0;
GoodCRC_Response_from_PHY=0;
Message_discarded_bus_Idle=0;
I2C_slave_reg_in=0;
I2C_slave_reg_addr=0;
I2C_slave_reg_in_enb=0;
reset=1;
#(2*`PERIODO) reset=0;
I2C_slave_reg_addr=8'h10; //direccion de alert parte alta y baja
I2C_slave_reg_in=8'h00;
#(`PERIODO)I2C_slave_reg_addr=8'h11; //
I2C_slave_reg_in=8'h04; //escribimos la alerta de mensaje recibido
#(`PERIODO) force I2C_slave_reg_in=ow_ri2_out_data;
#(`PERIODO) force I2C_slave_reg_addr=ir_ri2_address;
SCL=0; SDA=1;
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
// Poner las transiciones requeridas para la lectura del alert
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
#(3*`PERIODO/4)
SDA=0;#(`PERIODO/2) //Start
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO//dir slave
SDA=0;#`PERIODO//Reg/write
SDA=1;#`PERIODO//ACK
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO //50 la dir de registro
SDA=1;#`PERIODO//ACK
///
SDA=1;#`PERIODO
SDA=0;#`PERIODO//repeated start
///
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //dir slave
SDA=1;#`PERIODO //ACK tercero
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //liberar linea para recibir byte
SDA=0;#`PERIODO //Master hace ACK de recibido de primer byte
SDA=1;#`PERIODO //liberado de linea para recibir segundo byte
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //fin de recepcion de segundo byte
SDA=1;#`PERIODO //NACK
SDA=0;#(`PERIODO/2)
SDA=1;#`PERIODO //y hacer stop
///////////////////////////////////////////////////////////////
////// Lectura de RECEIVE_BYTE_COUNT y RX_BUF_FRAME_TYPE /////
///////////////////////////////////////////////////////////////
SDA=0;#(`PERIODO/2) //hacer start para leer RECEIVE_BYTE_COUNT y RX_BUF_FRAME_TYPE
////Segunda lectura
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO//dir slave
SDA=0;#`PERIODO//Reg/write
SDA=1;#`PERIODO//ACK
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO //50 la dir de registro
SDA=1;#`PERIODO//ACK
///
SDA=1;#`PERIODO
SDA=0;#`PERIODO//repeated start
///
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //dir slave
SDA=1;#`PERIODO //ACK tercero
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //liberar linea para recibir byte
SDA=0;#`PERIODO //Master hace ACK de recibido de primer byte
SDA=1;#`PERIODO //liberado de linea para recibir segundo byte
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //fin de recepcion de segundo byte
SDA=1;#`PERIODO //NACK
SDA=0;#(`PERIODO/2)
SDA=1;#`PERIODO //y hacer stop
///////////////////////////////
////// Lectura de Rxbuff /////
///////////////////////////////
SDA=0;#(`PERIODO/2) //hacer start para leer RX_BUF
////Tercera lectura
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO//dir slave
SDA=0;#`PERIODO//Reg/write
SDA=1;#`PERIODO//ACK
SDA=0;#`PERIODO //inicio dir
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO //fin dir de registro
SDA=1;#`PERIODO //ACK
///
SDA=1;#`PERIODO
SDA=0;#`PERIODO//repeated start
///
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //dir slave
SDA=1;#`PERIODO //ACK tercero
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //liberar linea para recibir byte
SDA=0;#`PERIODO //Master hace ACK de recibido de primer byte
SDA=1;#`PERIODO //liberado de linea para recibir segundo byte
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //fin de recepcion de segundo byte
SDA=0;#`PERIODO //Master hace ACK de recibido de primer byte
SDA=1;#`PERIODO //liberado de linea para recibir segundo byte
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //fin de recepcion de tercer byte
SDA=1;#`PERIODO //NACK
SDA=0;#(`PERIODO/2)
SDA=1;#`PERIODO //y hacer stop
#`PERIODO $finish;
end
always begin #(`PERIODO/2) SCL=!SCL; end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_data_fifo:1.1
// IP Revision: 8
(* X_CORE_INFO = "axis_data_fifo_v1_1_8_axis_data_fifo,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_SWandHW_standalone_axis_data_fifo_4_0,axis_data_fifo_v1_1_8_axis_data_fifo,{}" *)
(* CORE_GENERATION_INFO = "design_SWandHW_standalone_axis_data_fifo_4_0,axis_data_fifo_v1_1_8_axis_data_fifo,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_data_fifo,x_ipVersion=1.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000011011,C_FIFO_DEPTH=256,C_FIFO_MODE=1,C_IS_ACLK_ASYNC=0,C_SYNCHRONIZER_STAGE=2,C_ACLKEN_CONV_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_SWandHW_standalone_axis_data_fifo_4_0 (
s_axis_aresetn,
s_axis_aclk,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tkeep,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
input wire [3 : 0] s_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
output wire [3 : 0] m_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
output wire [31 : 0] axis_data_count;
output wire [31 : 0] axis_wr_data_count;
output wire [31 : 0] axis_rd_data_count;
axis_data_fifo_v1_1_8_axis_data_fifo #(
.C_FAMILY("zynq"),
.C_AXIS_TDATA_WIDTH(32),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET('B00000000000000000000000000011011),
.C_FIFO_DEPTH(256),
.C_FIFO_MODE(1),
.C_IS_ACLK_ASYNC(0),
.C_SYNCHRONIZER_STAGE(2),
.C_ACLKEN_CONV_MODE(0)
) inst (
.s_axis_aresetn(s_axis_aresetn),
.m_axis_aresetn(1'H0),
.s_axis_aclk(s_axis_aclk),
.s_axis_aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(4'HF),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_aclk(1'H0),
.m_axis_aclken(1'H1),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axis_data_count(axis_data_count),
.axis_wr_data_count(axis_wr_data_count),
.axis_rd_data_count(axis_rd_data_count)
);
endmodule
|
// file: core_dcm.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____30.000______0.000______50.0______380.769____232.277
// CLK_OUT2___100.001______0.000______50.0______284.057____232.277
// CLK_OUT3___100.001____315.000______50.0______284.057____232.277
// CLK_OUT4___200.002____315.000______50.0______239.188____232.277
// CLK_OUT5___100.001______0.000______50.0______284.057____232.277
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________30.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "core_dcm,clk_wiz_v3_2,{component_name=core_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=5,clkin1_period=33.333,clkin2_period=33.333,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module core_dcm
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
output CLK_OUT5,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (20),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (20),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (6),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (6),
.CLKOUT2_PHASE (315.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DIVIDE (3),
.CLKOUT3_PHASE (315.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DIVIDE (6),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (33.333),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2),
.CLKOUT3 (clkout3),
.CLKOUT4 (clkout4),
.CLKOUT5 (clkout5_unused),
// Status and control signals
.LOCKED (LOCKED),
.RST (RESET),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
assign CLK_OUT3 = clkout2;
assign CLK_OUT4 = clkout3;
BUFG clkout5_buf
(.O (CLK_OUT5),
.I (clkout4));
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
parameter WIDTH_START = 2'b00;
parameter WIDTH_CKMIN = 2'b01;
parameter WIDTH_CKMAX = 2'b10;
parameter WIDTH_IDLE = 2'b11;
reg r_test_expr;
reg [1:0] r_state;
integer num_cks;
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=WIDTH_START;
num_cks = 0;
end
`endif
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
assign valid_test_expr = ~(test_expr ^ test_expr);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
always @(posedge clk) begin
r_test_expr <= test_expr;
if (`OVL_RESET_SIGNAL != 1'b0) begin
case (r_state)
WIDTH_START:
if ((r_test_expr == 1'b0) && (test_expr == 1'b1)) begin
num_cks <= 1;
if (min_cks > 0) r_state <= WIDTH_CKMIN;
else if (max_cks > 0) r_state <= WIDTH_CKMAX;
end
WIDTH_CKMIN:
if (test_expr == 1'b1) begin
num_cks <= num_cks + 1;
if (num_cks >= min_cks-1) begin
if (max_cks > 0) r_state <= WIDTH_CKMAX;
else r_state <= WIDTH_IDLE;
end
end
else begin
if (num_cks < min_cks) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression was held TRUE for less than specified minimum min_cks cycles");
end
r_state <= WIDTH_START;
end
WIDTH_CKMAX:
if (test_expr == 1'b1) begin
num_cks <= num_cks + 1;
if (num_cks >= max_cks) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression was held TRUE for more than specified maximum max_cks cycles");
r_state <= WIDTH_IDLE;
end
end
else begin
if (num_cks > max_cks) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression was held TRUE for more than specified maximum max_cks cycles");
end
r_state <= WIDTH_START;
end
WIDTH_IDLE:
if (test_expr == 1'b0) begin
r_state <= WIDTH_START;
end
endcase
end
else begin
r_state <= WIDTH_START;
num_cks <= 0;
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @(posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_test_expr == 1'b1)
begin
// Do Nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
reg r_test_expr_cover;
reg timer_started;
integer num_cks_cover;
`ifdef OVL_SYNTHESIS
`else
initial begin
num_cks_cover = 0;
end
`endif
always @(posedge clk) begin
r_test_expr_cover <= test_expr;
if (`OVL_RESET_SIGNAL != 1'b0 && coverage_level != `OVL_COVER_NONE) begin
if ((r_test_expr_cover == 1'b0) && (test_expr == 1'b1)) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
num_cks_cover <= 1;
timer_started <= 1;
ovl_cover_t("test_expr_asserts covered");
end //basic coverage
end
else if (timer_started && test_expr == 1'b1)
num_cks_cover <= num_cks_cover + 1;
else if (timer_started && (r_test_expr_cover == 1'b1) && (test_expr == 1'b0)) begin
num_cks_cover <= 0;
timer_started <= 0;
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (min_cks > 0 && num_cks_cover == min_cks) begin
ovl_cover_t("test_expr_asserted_for_min_cks covered");
end
if (max_cks > 0 && num_cks_cover == max_cks) begin
ovl_cover_t("test_expr_asserted_for_max_cks covered");
end
end //corner coverage
end
end // OVL_COVER_NONE
else begin // reset condition
num_cks_cover <= 0;
timer_started <= 0;
end // OVL_COVER_NONE
end // always
`endif // OVL_COVER_ON
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:06:46 12/12/2016
// Design Name:
// Module Name: Renderer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Renderer(
input wire clk, clr,
input wire [ 3: 0] status,
input wire video_on,
input wire [ 9: 0] pixel_x, pixel_y,
input wire btn_pos, mycar_pos, explode_pos, game_over_pos, score_pos,
input wire btn_visible, explode_visible,
input wire obstacle_pos0, obstacle_pos1, obstacle_pos2, obstacle_pos3, obstacle_pos4,
input wire digit_pos0, digit_pos1, digit_pos2, digit_pos3,
input wire iscollide0, iscollide1, iscollide2, iscollide3, iscollide4,
input wire signed [31:0] scroll,
input wire [16: 0] back_addr, side_addr,
input wire [15:0] explode_addr,
input wire [14:0] game_over_addr,
input wire [13: 0] btn_addr,score_addr,
input wire [13:0] digit_addr0, digit_addr1, digit_addr2, digit_addr3,
input wire [12: 0] mycar_addr,
input wire [12: 0] obstacle_addr0, obstacle_addr1, obstacle_addr2, obstacle_addr3, obstacle_addr4,
output reg [ 3: 0] red, green, blue
);
// Game status signal declaration
localparam [3:0]
prepare = 4'b1000,
activate = 4'b0100,
pause = 4'b0010,
terminate = 4'b0001;
//============================================================================
// Instantiation
//============================================================================
// Instantiate bmp's pixel data
wire [11:0] back_data, btn_data, side_data, mycar_data, explode_data, game_over_data, score_data;
wire [11:0] obstacle_data [0:4];
wire [11:0] digit_data [0:3];
background P1 (.clka(clk), .addra(back_addr), .douta(back_data));
startBtn P2 (.clka(clk), .addra(btn_addr), .douta(btn_data));
side P3 (.clka(clk), .addra(side_addr), .douta(side_data));
car mycar (.clka(clk), .addra(mycar_addr), .douta(mycar_data));
police obstacle0 (.clka(clk), .addra(obstacle_addr0), .douta(obstacle_data[0]));
police obstacle1 (.clka(clk), .addra(obstacle_addr1), .douta(obstacle_data[1]));
car obstacle2 (.clka(clk), .addra(obstacle_addr2), .douta(obstacle_data[2]));
car obstacle3 (.clka(clk), .addra(obstacle_addr3), .douta(obstacle_data[3]));
car obstacle4 (.clka(clk), .addra(obstacle_addr4), .douta(obstacle_data[4]));
explosion explode (.clka(clk), .addra(explode_addr), .douta(explode_data));
game_over game_over_prompt (.clka(clk), .addra(game_over_addr), .douta(game_over_data));
score score_prompt (.clka(clk), .addra(score_addr), .douta(score_data));
digit digit0 (.clka(clk), .addra(digit_addr0), .douta(digit_data[0]));
digit digit1 (.clka(clk), .addra(digit_addr1), .douta(digit_data[1]));
digit digit2 (.clka(clk), .addra(digit_addr2), .douta(digit_data[2]));
digit digit3 (.clka(clk), .addra(digit_addr3), .douta(digit_data[3]));
//=======================================================================================================================
// Render
// Layer 0: Game-over prompt, Score and digits (in TERMINATE status)
// Layer 1: Explosion animation (in ACTIVATE/PAUSE/TERMINATE status)
// Layer 2: My car and other obstacles (in ACTIVATE/PAUSE/TERMINATE status)
// Layer 3: Road, sildes and side (in ACTIVATE/PAUSE/TERMINATE status) OR background and start button (in PREPARE status)
//=======================================================================================================================
// Road's properities
parameter slide_x = 10;
parameter slide_y = 40;
parameter interval = 20;
parameter lane_x = 96;
integer i;
wire [9:0] dot_y;
wire slide_pos, road_pos;
assign dot_y = (pixel_y + scroll) % 480;
assign slide_pos = (pixel_x >= 74 && pixel_x < 85) || (pixel_x >= 554 && pixel_x < 565);
assign road_pos = pixel_x >= 85 && pixel_x < 554;
// Layer definition
wire layer0, layer2; // Other layers do NOT need being specially definited
assign layer0 = game_over_pos || score_pos || digit_pos0 || digit_pos1 || digit_pos2 || digit_pos3;
assign layer2 = mycar_pos || obstacle_pos0 || obstacle_pos1 || obstacle_pos2 || obstacle_pos3 || obstacle_pos4;
always @*
begin
if (video_on)
begin
//=================================================================================
// Use FSM to render differnet status
//=================================================================================
case (status)
prepare: // Render the prepare status
begin
if (btn_pos && btn_visible) // Render the button
begin
if (btn_data == 12'hfff) // Filter the background color
begin
red <= back_data[ 3: 0];
green <= back_data[ 7: 4];
blue <= back_data[11: 8];
end
else
begin
red <= btn_data[ 3: 0];
green <= btn_data[ 7: 4];
blue <= btn_data[11: 8];
end
end
else
begin
red <= back_data[ 3: 0];
green <= back_data[ 7: 4];
blue <= back_data[11: 8];
end
end
activate: // Render the activate status
begin
if (explode_pos && explode_visible) //================================================ Layer 1
begin
if (explode_data == 12'h0f0 || explode_data == 12'h1f1 || explode_data == 12'h2f2 || explode_data == 12'h0e0)
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= mycar_data[ 3: 0];
green <= mycar_data[ 7: 4];
blue <= mycar_data[11: 8];
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= obstacle_data[0][ 3: 0];
green <= obstacle_data[0][ 7: 4];
blue <= obstacle_data[0][11: 8];
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= obstacle_data[1][ 3: 0];
green <= obstacle_data[1][ 7: 4];
blue <= obstacle_data[1][11: 8];
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= obstacle_data[2][ 3: 0];
green <= obstacle_data[2][ 7: 4];
blue <= obstacle_data[2][11: 8];
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= obstacle_data[3][ 3: 0];
green <= obstacle_data[3][ 7: 4];
blue <= obstacle_data[3][11: 8];
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= obstacle_data[4][ 3: 0];
green <= obstacle_data[4][ 7: 4];
blue <= obstacle_data[4][11: 8];
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= explode_data[ 3: 0];
green <= explode_data[ 7: 4];
blue <= explode_data[11: 8];
end
end
else if (layer2) //=================================================== Layer 2
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= mycar_data[ 3: 0];
green <= mycar_data[ 7: 4];
blue <= mycar_data[11: 8];
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= obstacle_data[0][ 3: 0];
green <= obstacle_data[0][ 7: 4];
blue <= obstacle_data[0][11: 8];
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= obstacle_data[1][ 3: 0];
green <= obstacle_data[1][ 7: 4];
blue <= obstacle_data[1][11: 8];
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= obstacle_data[2][ 3: 0];
green <= obstacle_data[2][ 7: 4];
blue <= obstacle_data[2][11: 8];
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= obstacle_data[3][ 3: 0];
green <= obstacle_data[3][ 7: 4];
blue <= obstacle_data[3][11: 8];
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
else
begin
red <= obstacle_data[4][ 3: 0];
green <= obstacle_data[4][ 7: 4];
blue <= obstacle_data[4][11: 8];
end
end
end
else //===================================================== Layer 3
begin
//=======================================================================
// Render the rolling road line:
// || || || || || ||
// || || || || || ||
// || ||
// || || || || || ||
// || || || || || ||
// || ||
// || || || || || ||
// || || || || || ||
//=======================================================================
if ((pixel_x >= 74 && pixel_x < 85) || (pixel_x >= 554 && pixel_x < 565))
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
if (((pixel_x >= 74 + lane_x) && (pixel_x < 85 + lane_x)) || ((pixel_x >= 74 + 2 * lane_x) && (pixel_x < 85 + 2 * lane_x)) || ((pixel_x >= 74 + 3 * lane_x) && (pixel_x < 85 + 3 * lane_x)) || ((pixel_x >= 74 + 4 * lane_x) && (pixel_x < 85 + 4 * lane_x)))
begin
for (i = 0; i < 480; i = i + 60)
begin
if (dot_y >= i && dot_y < i + slide_y)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 15;
end
else if (dot_y >= i + slide_y && dot_y < i + slide_y + interval)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
end
end
else
begin
if (pixel_x >= 74 && pixel_x < 565)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 15;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 15;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 15;
end
else
begin
red <= side_data[ 3: 0];
green <= side_data[ 7: 4];
blue <= side_data[11: 8];
end
end
end
end
end
pause:
begin
if (explode_pos && explode_visible) //================================================ Layer 1
begin
if (explode_data == 12'h0f0 || explode_data == 12'h1f1 || explode_data == 12'h2f2 || explode_data == 12'h0e0)
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= explode_data[ 3: 0] / 5;
green <= explode_data[ 7: 4] / 5;
blue <= explode_data[11: 8] / 5;
end
end
else if (layer2) //=================================================== Layer 2
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
end
else //===================================================== Layer 3
begin
//=======================================================================
// Render the rolling road line:
// || || || || || ||
// || || || || || ||
// || ||
// || || || || || ||
// || || || || || ||
// || ||
// || || || || || ||
// || || || || || ||
//=======================================================================
if ((pixel_x >= 74 && pixel_x < 85) || (pixel_x >= 554 && pixel_x < 565))
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
if (((pixel_x >= 74 + lane_x) && (pixel_x < 85 + lane_x)) || ((pixel_x >= 74 + 2 * lane_x) && (pixel_x < 85 + 2 * lane_x)) || ((pixel_x >= 74 + 3 * lane_x) && (pixel_x < 85 + 3 * lane_x)) || ((pixel_x >= 74 + 4 * lane_x) && (pixel_x < 85 + 4 * lane_x)))
begin
for (i = 0; i < 480; i = i + 60)
begin
if (dot_y >= i && dot_y < i + slide_y)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (dot_y >= i + slide_y && dot_y < i + slide_y + interval)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
end
end
else
begin
if (pixel_x >= 74 && pixel_x < 565)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
end
end
end
terminate:
begin
if (layer0) //================================================ Layer 0
begin
if (game_over_pos)
begin
if (game_over_data == 12'h000)
begin
if (explode_pos && explode_visible)
begin
if (explode_data == 12'h0f0 || explode_data == 12'h1f1 || explode_data == 12'h2f2 || explode_data == 12'h0e0)
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= explode_data[ 3: 0] / 5;
green <= explode_data[ 7: 4] / 5;
blue <= explode_data[11: 8] / 5;
end
end
else if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
end
else
begin
red <= game_over_data[ 3: 0];
green <= game_over_data[ 7: 4];
blue <= game_over_data[11: 8];
end
end
if (score_pos)
begin
if (score_data == 12'h000)
begin
if (explode_pos && explode_visible)
begin
if (explode_data == 12'h0f0 || explode_data == 12'h1f1 || explode_data == 12'h2f2 || explode_data == 12'h0e0)
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= explode_data[ 3: 0] / 5;
green <= explode_data[ 7: 4] / 5;
blue <= explode_data[11: 8] / 5;
end
end
else if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
end
else
begin
red <= score_data[ 3: 0];
green <= score_data[ 7: 4];
blue <= score_data[11: 8];
end
end
if (digit_pos0)
begin
if (digit_data[0] == 12'h000)
begin
if (explode_pos && explode_visible)
begin
if (explode_data == 12'h0f0 || explode_data == 12'h1f1 || explode_data == 12'h2f2 || explode_data == 12'h0e0)
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= explode_data[ 3: 0] / 5;
green <= explode_data[ 7: 4] / 5;
blue <= explode_data[11: 8] / 5;
end
end
else if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
end
else
begin
red <= digit_data[0][ 3: 0];
green <= digit_data[0][ 7: 4];
blue <= digit_data[0][11: 8];
end
end
if (digit_pos1)
begin
if (digit_data[1] == 12'h000)
begin
if (explode_pos && explode_visible)
begin
if (explode_data == 12'h0f0 || explode_data == 12'h1f1 || explode_data == 12'h2f2 || explode_data == 12'h0e0)
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= explode_data[ 3: 0] / 5;
green <= explode_data[ 7: 4] / 5;
blue <= explode_data[11: 8] / 5;
end
end
else if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
end
else
begin
red <= digit_data[1][ 3: 0];
green <= digit_data[1][ 7: 4];
blue <= digit_data[1][11: 8];
end
end
if (digit_pos2)
begin
if (digit_data[2] == 12'h000)
begin
if (explode_pos && explode_visible)
begin
if (explode_data == 12'h0f0 || explode_data == 12'h1f1 || explode_data == 12'h2f2 || explode_data == 12'h0e0)
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= explode_data[ 3: 0] / 5;
green <= explode_data[ 7: 4] / 5;
blue <= explode_data[11: 8] / 5;
end
end
else if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
end
else
begin
red <= digit_data[2][ 3: 0];
green <= digit_data[2][ 7: 4];
blue <= digit_data[2][11: 8];
end
end
if (digit_pos3)
begin
if (digit_data[3] == 12'h000)
begin
if (explode_pos && explode_visible)
begin
if (explode_data == 12'h0f0 || explode_data == 12'h1f1 || explode_data == 12'h2f2 || explode_data == 12'h0e0)
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= explode_data[ 3: 0] / 5;
green <= explode_data[ 7: 4] / 5;
blue <= explode_data[11: 8] / 5;
end
end
else if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
end
else
begin
red <= digit_data[3][ 3: 0];
green <= digit_data[3][ 7: 4];
blue <= digit_data[3][11: 8];
end
end
end
else if (explode_pos && explode_visible) //================================================ Layer 1
begin
if (explode_data == 12'h0f0 || explode_data == 12'h1f1 || explode_data == 12'h2f2 || explode_data == 12'h0e0)
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
else if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= explode_data[ 3: 0] / 5;
green <= explode_data[ 7: 4] / 5;
blue <= explode_data[11: 8] / 5;
end
end
else if (layer2) //=================================================== Layer 2
begin
if (mycar_pos)
begin
if (mycar_data == 12'h0f0 || mycar_data == 12'h1f1 || mycar_data == 12'h2f2 || mycar_data == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= mycar_data[ 3: 0] / 5;
green <= mycar_data[ 7: 4] / 5;
blue <= mycar_data[11: 8] / 5;
end
end
else if (obstacle_pos0)
begin
if (obstacle_data[0] == 12'h0f0 || obstacle_data[0] == 12'h1f1 || obstacle_data[0] == 12'h2f2 || obstacle_data[0] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[0][ 3: 0] / 5;
green <= obstacle_data[0][ 7: 4] / 5;
blue <= obstacle_data[0][11: 8] / 5;
end
end
else if (obstacle_pos1)
begin
if (obstacle_data[1] == 12'h0f0 || obstacle_data[1] == 12'h1f1 || obstacle_data[1] == 12'h2f2 || obstacle_data[1] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[1][ 3: 0] / 5;
green <= obstacle_data[1][ 7: 4] / 5;
blue <= obstacle_data[1][11: 8] / 5;
end
end
else if (obstacle_pos2)
begin
if (obstacle_data[2] == 12'h0f0 || obstacle_data[2] == 12'h1f1 || obstacle_data[2] == 12'h2f2 || obstacle_data[2] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[2][ 3: 0] / 5;
green <= obstacle_data[2][ 7: 4] / 5;
blue <= obstacle_data[2][11: 8] / 5;
end
end
else if (obstacle_pos3)
begin
if (obstacle_data[3] == 12'h0f0 || obstacle_data[3] == 12'h1f1 || obstacle_data[3] == 12'h2f2 || obstacle_data[3] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[3][ 3: 0] / 5;
green <= obstacle_data[3][ 7: 4] / 5;
blue <= obstacle_data[3][11: 8] / 5;
end
end
else if (obstacle_pos4)
begin
if (obstacle_data[4] == 12'h0f0 || obstacle_data[4] == 12'h1f1 || obstacle_data[4] == 12'h2f2 || obstacle_data[4] == 12'h0e0)
begin
if (slide_pos)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (road_pos)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
else
begin
red <= obstacle_data[4][ 3: 0] / 5;
green <= obstacle_data[4][ 7: 4] / 5;
blue <= obstacle_data[4][11: 8] / 5;
end
end
end
else //===================================================== Layer 3
begin
//=======================================================================
// Render the rolling road line:
// || || || || || ||
// || || || || || ||
// || ||
// || || || || || ||
// || || || || || ||
// || ||
// || || || || || ||
// || || || || || ||
//=======================================================================
if ((pixel_x >= 74 && pixel_x < 85) || (pixel_x >= 554 && pixel_x < 565))
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
if (((pixel_x >= 74 + lane_x) && (pixel_x < 85 + lane_x)) || ((pixel_x >= 74 + 2 * lane_x) && (pixel_x < 85 + 2 * lane_x)) || ((pixel_x >= 74 + 3 * lane_x) && (pixel_x < 85 + 3 * lane_x)) || ((pixel_x >= 74 + 4 * lane_x) && (pixel_x < 85 + 4 * lane_x)))
begin
for (i = 0; i < 480; i = i + 60)
begin
if (dot_y >= i && dot_y < i + slide_y)
begin
red <= (4'b1111 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b1111 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b1111 * 12 + side_data[11: 8] * 3) / 75;
end
else if (dot_y >= i + slide_y && dot_y < i + slide_y + interval)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
end
end
else
begin
if (pixel_x >= 74 && pixel_x < 565)
begin
red <= (4'b0101 * 12 + side_data[ 3: 0] * 3) / 75;
green <= (4'b0101 * 12 + side_data[ 7: 4] * 3) / 75;
blue <= (4'b0100 * 12 + side_data[11: 8] * 3) / 75;
end
else
begin
red <= side_data[ 3: 0] / 5;
green <= side_data[ 7: 4] / 5;
blue <= side_data[11: 8] / 5;
end
end
end
end
end
endcase
end
else
begin
red <= 4'b0;
green <= 4'b0;
blue <= 4'b0;
end
end
endmodule
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