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stringlengths 938
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module var14_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N;
output valid;
wire [7:0] min_value = 8'd120;
wire [7:0] max_weight = 8'd60;
wire [7:0] max_volume = 8'd60;
wire [7:0] total_value =
A * 8'd4
+ B * 8'd8
+ C * 8'd0
+ D * 8'd20
+ E * 8'd10
+ F * 8'd12
+ G * 8'd18
+ H * 8'd14
+ I * 8'd6
+ J * 8'd15
+ K * 8'd30
+ L * 8'd8
+ M * 8'd16
+ N * 8'd18;
wire [7:0] total_weight =
A * 8'd28
+ B * 8'd8
+ C * 8'd27
+ D * 8'd18
+ E * 8'd27
+ F * 8'd28
+ G * 8'd6
+ H * 8'd1
+ I * 8'd20
+ J * 8'd0
+ K * 8'd5
+ L * 8'd13
+ M * 8'd8
+ N * 8'd14;
wire [7:0] total_volume =
A * 8'd27
+ B * 8'd27
+ C * 8'd4
+ D * 8'd4
+ E * 8'd0
+ F * 8'd24
+ G * 8'd4
+ H * 8'd20
+ I * 8'd12
+ J * 8'd15
+ K * 8'd5
+ L * 8'd2
+ M * 8'd9
+ N * 8'd28;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_SYMBOL_V
`define SKY130_FD_SC_HS__CLKINV_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_SYMBOL_V
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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_csr_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// The following registers are maintained here.
// A8, B8 - L2 BIST control register.
// A9, B9 - L2 control register
// AA, BA - L2 Error Enable Register
// AB, BB - L2 Error Status register.
// AC, BC - L2 Error Address register.
// AD, BD - L2 Error Injection Register.
// AE,AF, BE, BF - L2 Tag SelF time MArgin Register
// The L2 diagnostic addresses are as follows
// A0-A3, B0-B3 - L2 data
// A4,A5, B0,B5 - L2 Address
// A6,A7,B6,B7 - L2 VUAD
`include "iop.h"
`include "sctag.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module sctag_csr_ctl( /*AUTOARG*/
// Outputs
fbctl_decc_scrd_corr_err_c8, fbctl_decc_scrd_uncorr_err_c8,
mbctl_decc_spcfb_corr_err_c8, mbctl_decc_spcd_corr_err_c8,
fbctl_decc_bscd_corr_err_c8, fbctl_decc_bscd_uncorr_err_c8,
arbctl_data_ecc_active_c3, decc_data_ecc_active_c3,
tagdp_l2_dir_map_on, mbctl_l2_dir_map_on, fbctl_l2_dir_map_on,
arbctl_dbginit_l, mbctl_dbginit_l, fbctl_dbginit_l,
tagctl_dbginit_l, tagdp_ctl_dbginit_l, csr_dbginit_l,
wbctl_dbginit_l, so, csr_ctl_wr_en_c8, csr_erren_wr_en_c8,
csr_errstate_wr_en_c8, csr_errinj_wr_en_c8, err_state_in_rw,
err_state_in_mec, err_state_in_meu, err_state_in, csr_synd_wr_en,
mux1_synd_sel, mux2_synd_sel, wr_enable_tid_c9, csr_tid_wr_en,
csr_async_wr_en, set_async_c9, error_rw_en, diag_wr_en,
mux1_addr_sel, mux2_addr_sel, csr_addr_wr_en, csr_rd_mux1_sel_c7,
csr_rd_mux2_sel_c7, csr_rd_mux3_sel_c7, sctag_por_req,
csr_bist_wr_en_c8,
// Inputs
arbctl_csr_wr_en_c7, arbdp_word_addr_c6, rclk, si, se, rst_tri_en,
vuad_error_c8, dir_error_c8, decc_spcd_corr_err_c8,
decc_spcd_uncorr_err_c8, decc_scrd_corr_err_c8,
decc_scrd_uncorr_err_c8, decc_spcfb_corr_err_c8,
decc_spcfb_uncorr_err_c8, decc_bscd_corr_err_c8,
decc_bscd_uncorr_err_c8, tag_error_c8, data_ecc_active_c3,
l2_dir_map_on, dbginit_l, dram_scb_secc_err_d1,
dram_scb_mecc_err_d1, fbctl_uncorr_err_c8, fbctl_corr_err_c8,
fbctl_bsc_corr_err_c12, fbctl_ld64_fb_hit_c12, ev_uerr_r6,
ev_cerr_r6, rdmard_uerr_c12, rdmard_cerr_c12, error_status_vec,
error_status_veu, store_err_c8, arbdp_async_bit_c8, str_ld_hit_c7
);
input arbctl_csr_wr_en_c7;
input [2:0] arbdp_word_addr_c6;
input rclk;
input si, se;
input rst_tri_en;
// from vuaddp
input vuad_error_c8; // from vuad dp.
// from arbctl.
input dir_error_c8 ; // from the directory
// from decc_ctl.v
input decc_spcd_corr_err_c8 ; // error in 156 bit data
input decc_spcd_uncorr_err_c8 ; // error in 156 bit data
input decc_scrd_corr_err_c8 ;// error in 156 bit data
input decc_scrd_uncorr_err_c8 ;// error in 156 bit data
input decc_spcfb_corr_err_c8 ; // error in 156 bit data or error
input decc_spcfb_uncorr_err_c8 ; // error in 156 bit data or error
input decc_bscd_corr_err_c8; // error in 156 bit data ( for WR8s)
input decc_bscd_uncorr_err_c8; // error in 156 bit data ( for WR8s)
// from tagdp.v
input tag_error_c8;
input data_ecc_active_c3 ; // POST_4.2 ( Right)
output fbctl_decc_scrd_corr_err_c8; // POST_4.2 ( Top)
output fbctl_decc_scrd_uncorr_err_c8; // POST_4.2 ( Top)
output mbctl_decc_spcfb_corr_err_c8; // POST_4.2 (Top)
output mbctl_decc_spcd_corr_err_c8 ; // POST_4.2 (Top)
output fbctl_decc_bscd_corr_err_c8; // POST_4.2 ( Top)
output fbctl_decc_bscd_uncorr_err_c8; // POST_4.2 ( Top)
output arbctl_data_ecc_active_c3; // POST_4.2 ( Top)
output decc_data_ecc_active_c3; // POST_4.2 ( Top)
input l2_dir_map_on; // POST_4.2 ( Left)
output tagdp_l2_dir_map_on; // POST_4.2 ( Left/Bottom)
output mbctl_l2_dir_map_on; // POST_4.2 ( Top)
output fbctl_l2_dir_map_on; // POST_4.2 ( Top)
input dbginit_l ; // POST_4.2 Bottom
output arbctl_dbginit_l ; // POST_4.2 TOp
output mbctl_dbginit_l ; // POST_4.2 Top
output fbctl_dbginit_l ; // POST_4.2 Top
output tagctl_dbginit_l ; // POST_4.2 Top
output tagdp_ctl_dbginit_l ; // POST_4.2 Left
output csr_dbginit_l ; // POST_4.2 Left
output wbctl_dbginit_l ; // POST_4.2 Top
// from fbctl.v
input dram_scb_secc_err_d1; // scrub error from DRAM
input dram_scb_mecc_err_d1; // scrub error from DRAM
input fbctl_uncorr_err_c8 ; // Errors from DRAM in response to a read
input fbctl_corr_err_c8 ; // Errors from DRAM in response to a read
input fbctl_bsc_corr_err_c12; // Errors from DRAM in response to a rd64 miss.
input fbctl_ld64_fb_hit_c12; // qualification for errors found in
// rdma rd stream out data path.
// from rdmatctl.v
input ev_uerr_r6;// wb errors from the evict dp.
input ev_cerr_r6;// wb errors from the evict dp.
input rdmard_uerr_c12;
input rdmard_cerr_c12;
// from csr
input error_status_vec;
input error_status_veu;
// from arbdec
input store_err_c8;
input arbdp_async_bit_c8; // ADDED POST_4.0
input str_ld_hit_c7; // from oqctl.
// csr_ctl
output so;
output csr_ctl_wr_en_c8 ;
output csr_erren_wr_en_c8;
output csr_errstate_wr_en_c8;
output csr_errinj_wr_en_c8;
//output csr_stm_wr_en_c8; // REMOVED POST_4.0
// 21 control bits in Status register.
output err_state_in_rw ;
output err_state_in_mec ;
output err_state_in_meu ;
output [`ERR_LDAC:`ERR_VEU] err_state_in ;
output csr_synd_wr_en;
output [1:0] mux1_synd_sel;
output [1:0] mux2_synd_sel;
output wr_enable_tid_c9;
output csr_tid_wr_en;
output csr_async_wr_en;
// output wr_enable_async_c9; REMOVED POST_4.0
output set_async_c9 ; // ADDED POST_4.0
output error_rw_en ; // ADDED POST_4.0
output diag_wr_en; // ADDED POST_4.0
output [3:0] mux1_addr_sel;
output [2:0] mux2_addr_sel;
output csr_addr_wr_en;
// output csr_erraddr_wr_en_c8; // REMOVED POST_4.0
// read enables.
output [3:0] csr_rd_mux1_sel_c7;
output csr_rd_mux2_sel_c7;
output [1:0] csr_rd_mux3_sel_c7;
// these outputs need to be removed.
output sctag_por_req; // POST_4.2
output csr_bist_wr_en_c8; // POST_2.0
wire control_reg_write_en, control_reg_write_en_d1;
wire erren_reg_write_en, erren_reg_write_en_d1;
wire errst_reg_write_en, errst_reg_write_en_d1;
wire erraddr_reg_write_en, erraddr_reg_write_en_d1;
wire errinj_reg_write_en, errinj_reg_write_en_d1;
//wire stm_reg_write_en, stm_reg_write_en_d1;
wire [2:0] word_addr_c7;
wire [2:0] mux1_sel_c6, mux1_sel_c7;
wire [63:0] err_status_in;
wire [63:0] err_state_new_c9;
wire [63:0] err_state_new_c8;
wire [7:0] new_uerr_vec_c9 ;
wire [7:0] wr_uerr_vec_c9 ;
wire [6:0] new_cerr_vec_c9 ;
wire [6:0] wr_cerr_vec_c9 ;
wire rdma_pst_err_c9;
wire store_error_c9 ;
wire rdmard_uerr_c13, rdmard_cerr_c13 ;
wire str_ld_hit_c8, str_ld_hit_c9 ;
wire err_sel, new_err_sel;
wire rdmard_addr_sel_c13;
wire bsc_corr_err_c13;
wire en_por_c7, en_por_c7_d1;
wire bist_reg_write_en, bist_reg_write_en_d1;
wire [3:0] mux1_addr_sel_tmp;
wire [2:0] mux2_addr_sel_tmp ;
wire pipe_addr_sel;
wire bscd_uncorr_err_c9, bscd_corr_err_c9 ;
wire csr_erraddr_wr_en_c8;
wire async_bit_c9, wr_enable_async_c9;
wire error_spc, error_bsc ;
// --------------\/------- Added repeaters post_4.2 ---\/ --------
assign arbctl_dbginit_l = dbginit_l ;
assign mbctl_dbginit_l = dbginit_l ;
assign fbctl_dbginit_l = dbginit_l ;
assign wbctl_dbginit_l = dbginit_l ;
assign csr_dbginit_l = dbginit_l ;
assign tagctl_dbginit_l = dbginit_l ;
assign tagdp_ctl_dbginit_l = dbginit_l ;
//decc_spcd_uncorr_err_c8 repeater not needed.
//decc_spcfb_corr_err_c8 repeater not needed.
assign fbctl_decc_scrd_corr_err_c8 = decc_scrd_corr_err_c8;
assign fbctl_decc_scrd_uncorr_err_c8 = decc_scrd_uncorr_err_c8 ;
assign fbctl_decc_bscd_corr_err_c8 = decc_bscd_corr_err_c8 ;
assign fbctl_decc_bscd_uncorr_err_c8 = decc_bscd_uncorr_err_c8 ;
assign mbctl_decc_spcd_corr_err_c8 = decc_spcd_corr_err_c8 ;
assign mbctl_decc_spcfb_corr_err_c8 = decc_spcfb_corr_err_c8 ;
assign arbctl_data_ecc_active_c3 = data_ecc_active_c3 ;
assign decc_data_ecc_active_c3 = data_ecc_active_c3 ;
assign tagdp_l2_dir_map_on = l2_dir_map_on ;
assign mbctl_l2_dir_map_on = l2_dir_map_on ;
assign fbctl_l2_dir_map_on = l2_dir_map_on ;
// --------------\/------- Added repeaters post_4.2 ---\/ --------
/////////////////////////////////////////////////////
// Exception cases:
//
// - Wr8s will cause DAU to be set in OFF mode. ( if an uncorr err
// is signalled by DRAM).
// - Wr8 will cause DAC to be set. in OFF/ON mode.
/////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// CSR pipeline.
//
//============================================================
// C7 C8 C9
//============================================================
// generate mux out xmit
// mux selects rd data to
// ccx
//
// enable
// a write
//
//============================================================
//
// Eventhough the Write and Read operations do not happen in the
// same cycle, no data forwarding is required because the write
// is followed by ATLEAST one bubble
//
// Errors update the ESR and EAR in the C10 cycle.
// Hence a CSR load may actually miss the error that occurred
// just before it.
////////////////////////////////////////////////////////////////////////////////
//////////////////////////
// I) WR ENABLE GENERATION
//
// Write pipeline.
// A CSR store is performed
// in the C8 cycle.
//////////////////////////
dff_s #(3) ff_word_addr_c7 (.din(arbdp_word_addr_c6[2:0]),
.clk(rclk),
.q(word_addr_c7[2:0]),
.se(se), .si(), .so());
//////////////////////////
// BIST REG A8
// This register can be written by software or
// by JTAG via the CTU
//////////////////////////
assign bist_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h0 ) ; // A8
dff_s #(1) ff_bist_reg_write_en_d1 (.din(bist_reg_write_en),
.clk(rclk),
.q(bist_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_bist_wr_en_c8 = bist_reg_write_en_d1 ;
//////////////////////////
// CONTROL REG A9
//////////////////////////
assign control_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h1 ) ; // A9
dff_s #(1) ff_control_reg_write_en_d1 (.din(control_reg_write_en),
.clk(rclk),
.q(control_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_ctl_wr_en_c8 = control_reg_write_en_d1 ;
//////////////////////////
// ERR ENABLE REG AA
//////////////////////////
assign erren_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h2) ; // AA
dff_s #(1) ff_erren_reg_write_en_d1 (.din(erren_reg_write_en),
.clk(rclk),
.q(erren_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_erren_wr_en_c8 = erren_reg_write_en_d1 ;
//////////////////////////
// ERR STATE REG AB
//////////////////////////
assign errst_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h3) ; // AB
dff_s #(1) ff_errst_reg_write_en_d1 (.din(errst_reg_write_en), .clk(rclk),
.q(errst_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_errstate_wr_en_c8 = errst_reg_write_en_d1 ;
//////////////////////////
// ERR ADDR REG AC
//////////////////////////
assign erraddr_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h4) ; // AC
dff_s #(1) ff_erraddr_reg_write_en_d1 (.din(erraddr_reg_write_en), .clk(rclk),
.q(erraddr_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_erraddr_wr_en_c8 = erraddr_reg_write_en_d1 ;
//////////////////////////
// ERR INJ REG AD
//////////////////////////
assign errinj_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h5) ; // AD
dff_s #(1) ff_errinj_reg_write_en_d1 (.din(errinj_reg_write_en), .clk(rclk),
.q(errinj_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_errinj_wr_en_c8 = errinj_reg_write_en_d1 ;
//////////////////////////
// THIS REGISTER HAS BEEN REMOVED FROM THE SPEC
// STM REG AE or AF
//////////////////////////
//assign stm_reg_write_en = arbctl_csr_wr_en_c7 &
//( (word_addr_c7==3'h6) |
//(word_addr_c7==3'h7)
//) ;
//dff #(1) ff_stm_reg_write_en_d1 (.din(stm_reg_write_en), .clk(rclk),
//.q(stm_reg_write_en_d1),
//.se(se), .si(), .so());
//
//
//assign csr_stm_wr_en_c8 = stm_reg_write_en_d1 ;
//////////////////////////
// RD enable generation.
//////////////////////////
assign mux1_sel_c6[0] = ( arbdp_word_addr_c6[1:0] == 2'd0 ) ; // A8 or Ac
assign mux1_sel_c6[1] = ( arbdp_word_addr_c6[1:0] == 2'd1 ) ; // A9 or Ad
assign mux1_sel_c6[2] = ( arbdp_word_addr_c6[1:0] == 2'd2 ) ; //Aa or Ae
dff_s #(3) ff_mux1_sel_c7 (.din(mux1_sel_c6[2:0]), .clk(rclk),
.q(mux1_sel_c7[2:0]),
.se(se), .si(), .so());
assign csr_rd_mux1_sel_c7[0] = mux1_sel_c7[0] & ~rst_tri_en ;
assign csr_rd_mux1_sel_c7[1] = mux1_sel_c7[1] & ~rst_tri_en ;
assign csr_rd_mux1_sel_c7[2] = mux1_sel_c7[2] & ~rst_tri_en ;
assign csr_rd_mux1_sel_c7[3] = ~(|(mux1_sel_c7[2:0])) | rst_tri_en;
assign csr_rd_mux2_sel_c7 = ~( mux1_sel_c7[0] |
mux1_sel_c7[1] ) | rst_tri_en ;
assign csr_rd_mux3_sel_c7[0] = ~word_addr_c7[2] ;
assign csr_rd_mux3_sel_c7[1] = word_addr_c7[2] ;
//////////////////////////
// ERROR LOGGING LOGIC.
// UNCORR ERRORS.
//////////////////////////
/////////////////////////////////////////////////////
// LVU bit
// vuad parity. Addr=C9, syndrome = parity_c9<3:0>
// set this bit, if there is no pending uncorr err.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LVU] = vuad_error_c8 ;
dff_s #(1) ff_err_state_new_c9_lvu
(.din(err_state_new_c8[`ERR_LVU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LVU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LVU] = ~error_status_veu &
err_state_new_c9[`ERR_LVU] ;
/////////////////////////////////////////////////////
// LRU bit
// dir parity. Addr=index syndrome = X
// set this bit if no lvu occurs and no pending uncorr err.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LRU] = dir_error_c8 ; // directory error
dff_s #(1) ff_err_state_new_c9_lru
(.din(err_state_new_c8[`ERR_LRU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LRU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LRU] = ~( err_state_new_c9[`ERR_LVU] |
error_status_veu ) &
err_state_new_c9[`ERR_LRU] ;
/////////////////////////////////////////////////////
// LDSU bit
// set for a scrub
// Address=C7. Syndrome = data_syndrome from decc
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDSU] = decc_scrd_uncorr_err_c8 ; // scrub uncorr err
dff_s #(1) ff_err_state_new_c9_ldsu
(.din(err_state_new_c8[`ERR_LDSU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDSU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDSU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
error_status_veu ) &
err_state_new_c9[`ERR_LDSU] ;
/////////////////////////////////////////////////////
// LDAU bit
// set for any kind of access LD/ST/ATOMIC/PST
// Address=C9. Syndrome = data_syndrome from decc
// Only set for accesses that hit the $
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDAU] = decc_spcd_uncorr_err_c8 ; // data uncorr err
dff_s #(1) ff_err_state_new_c9_ldau
(.din(err_state_new_c8[`ERR_LDAU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDAU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDAU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
error_status_veu ) &
err_state_new_c9[`ERR_LDAU] ;
/////////////////////////////////////////////////////
// LDWU bit
// eviction error logging done in cycles r7 through r14
// of an evict. Address logging is also done in the
// same 8 cycle window
// ??? may need to change leave_state2 counter to 13
// in wbctl.v
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDWU] = ev_uerr_r6 ; // eviction uncorr err
dff_s #(1) ff_err_state_new_c9_ldwu
(.din(err_state_new_c8[`ERR_LDWU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDWU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDWU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
err_state_new_c9[`ERR_LDAU] |
err_state_new_c9[`ERR_LDSU] |
error_status_veu ) &
err_state_new_c9[`ERR_LDWU] ;
/////////////////////////////////////////////////////
// LDRU bit
// Set for an RDMA Read or an RDMA Write ( Partial )
// or RDMA Write which
// returns with an error from the DRAM.
// Only set for accesses that hit the $
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDRU] = decc_bscd_uncorr_err_c8 |
( rdmard_uerr_c12 &
~fbctl_ld64_fb_hit_c12 ) ;
dff_s #(1) ff_err_state_new_c9_ldru
(.din(err_state_new_c8[`ERR_LDRU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDRU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDRU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
err_state_new_c9[`ERR_LDAU] |
err_state_new_c9[`ERR_LDSU] |
err_state_new_c9[`ERR_LDWU] |
error_status_veu ) &
err_state_new_c9[`ERR_LDRU] ;
/////////////////////////////////////////////////////
// DRU bit
// FB hit only for LD64/
// Wr8s will cause DAU to be set in OFF mode.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DRU] =
( rdmard_uerr_c12 &
fbctl_ld64_fb_hit_c12) ;
dff_s #(1) ff_err_state_new_c9_dru
(.din(err_state_new_c8[`ERR_DRU]), .clk(rclk),
.q(err_state_new_c9[`ERR_DRU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DRU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
err_state_new_c9[`ERR_LDAU] |
err_state_new_c9[`ERR_LDRU] |
err_state_new_c9[`ERR_LDSU] |
err_state_new_c9[`ERR_LDRU] |
err_state_new_c9[`ERR_LDWU] |
error_status_veu) &
err_state_new_c9[`ERR_DRU] ;
/////////////////////////////////////////////////////
// DAU bit
// only set for a FB hit or a FILL
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DAU] =
( decc_spcfb_uncorr_err_c8 | // from a spc instruction
fbctl_uncorr_err_c8 ) ; // from a fill.
dff_s #(1) ff_err_state_new_c9_dau
(.din(err_state_new_c8[`ERR_DAU]), .clk(rclk),
.q(err_state_new_c9[`ERR_DAU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DAU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
err_state_new_c9[`ERR_LDAU] |
err_state_new_c9[`ERR_LDRU] |
err_state_new_c9[`ERR_LDSU] |
err_state_new_c9[`ERR_LDRU] |
err_state_new_c9[`ERR_LDWU] |
err_state_new_c9[`ERR_DRU] |
error_status_veu ) &
err_state_new_c9[`ERR_DAU] ;
/////////////////////////////////////////////////////
// DSU bit
// This bit does not influence MEU
// and does not need to go through the
// priority logic
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DSU] = dram_scb_mecc_err_d1 ;
// scrub in DRAM causing an error.
dff_s #(1) ff_err_state_new_c9_dsu
(.din(err_state_new_c8[`ERR_DSU]), .clk(rclk),
.q(err_state_new_c9[`ERR_DSU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DSU] = err_state_new_c9[`ERR_DSU] ;
/////////////////////////////////////////////////////
// MEU bit
// Multiple error uncorrectable bit is set if multiple
// uncorrectable errors happen in the same cycle or
// are separated in time.
// This bit is set if the vector being written in
// is different from the vector that is detected
/////////////////////////////////////////////////////
assign new_uerr_vec_c9 = { err_state_new_c9[`ERR_LDAU],
err_state_new_c9[`ERR_LDWU],
err_state_new_c9[`ERR_LDRU],
err_state_new_c9[`ERR_LDSU],
err_state_new_c9[`ERR_LRU],
err_state_new_c9[`ERR_LVU],
err_state_new_c9[`ERR_DAU],
err_state_new_c9[`ERR_DRU] } ;
// atleast 10 gates to do the priority.
assign wr_uerr_vec_c9 = { err_status_in[`ERR_LDAU],
err_status_in[`ERR_LDWU],
err_status_in[`ERR_LDRU],
err_status_in[`ERR_LDSU],
err_status_in[`ERR_LRU],
err_status_in[`ERR_LVU],
err_status_in[`ERR_DAU],
err_status_in[`ERR_DRU] } ;
assign err_status_in[`ERR_MEU] = |( ~wr_uerr_vec_c9 & new_uerr_vec_c9 ) ;
/////////////////////////////////////////////////////
// VEU bit
/////////////////////////////////////////////////////
assign err_status_in[`ERR_VEU] = |(new_uerr_vec_c9) ;
/////////////////////////////////////////////////////
// ERROR LOGGING LOGIC.
// CORR ERRORS.
// correctible errors are logged if
// * there is no uncorr err in the same cycle.
// * there is no pending corr or uncorr err.
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
// LTC bit
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LTC] = tag_error_c8 ;
dff_s #(1) ff_err_state_new_c9_ltc
(.din(err_state_new_c8[`ERR_LTC]), .clk(rclk),
.q(err_state_new_c9[`ERR_LTC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LTC] = ~( err_status_in[`ERR_VEU] |
& error_status_veu |
error_status_vec ) &
err_state_new_c9[`ERR_LTC] ;
/////////////////////////////////////////////////////
// LDSC bit
// addr=C9 and syndrome = data synd.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDSC] = decc_scrd_corr_err_c8 ;
dff_s #(1) ff_err_state_new_c9_ldsc
(.din(err_state_new_c8[`ERR_LDSC]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDSC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDSC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] ) &
err_state_new_c9[`ERR_LDSC] ; // LDAC and LDSC are mutex
/////////////////////////////////////////////////////
// LDAC bit
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDAC] = decc_spcd_corr_err_c8 ;
dff_s #(1) ff_err_state_new_c9_ldac
(.din(err_state_new_c8[`ERR_LDAC]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDAC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDAC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] ) &
err_state_new_c9[`ERR_LDAC] ;
/////////////////////////////////////////////////////
// LDWC bit
// comes from a Wback
// addr = evicted address and syndrome = datasyndrome.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDWC] = ev_cerr_r6 ;
dff_s #(1) ff_err_state_new_c9_ldwc
(.din(err_state_new_c8[`ERR_LDWC]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDWC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDWC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] |
err_state_new_c9[`ERR_LDSC] |
err_state_new_c9[`ERR_LDAC] ) &
err_state_new_c9[`ERR_LDWC] ; // LDAC and LDSC are mutex
/////////////////////////////////////////////////////
// LDRC bit
// comes from an RDMA Read access and
// only for a $ hit
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDRC] = decc_bscd_corr_err_c8 |
( rdmard_cerr_c12 &
~fbctl_ld64_fb_hit_c12 ) ;
dff_s #(1) ff_err_state_new_c9_ldrc
(.din(err_state_new_c8[`ERR_LDRC]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDRC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDRC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] |
err_state_new_c9[`ERR_LDSC] |
err_state_new_c9[`ERR_LDWC] |
err_state_new_c9[`ERR_LDAC] ) &
err_state_new_c9[`ERR_LDRC] ;
/////////////////////////////////////////////////////
// DRC bit
// ld 64 will cause DRC to be set.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DRC] = fbctl_bsc_corr_err_c12 ;
dff_s #(1) ff_err_state_new_c9_drc
(.din(err_state_new_c8[`ERR_DRC]), .clk(rclk),
.q(err_state_new_c9[`ERR_DRC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DRC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] |
err_state_new_c9[`ERR_LDSC] |
err_state_new_c9[`ERR_LDAC] |
err_state_new_c9[`ERR_LDWC] |
err_state_new_c9[`ERR_LDRC]
) &
err_state_new_c9[`ERR_DRC];
/////////////////////////////////////////////////////
// DAC bit
// Only an fb hit or a fill
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DAC] = ( decc_spcfb_corr_err_c8 |
fbctl_corr_err_c8 ) ;
dff_s #(1) ff_err_state_new_c9_dac
(.din(err_state_new_c8[`ERR_DAC]), .clk(rclk),
.q(err_state_new_c9[`ERR_DAC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DAC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] |
err_state_new_c9[`ERR_LDSC] |
err_state_new_c9[`ERR_LDAC] |
err_state_new_c9[`ERR_LDWC] |
err_state_new_c9[`ERR_LDRC] |
err_state_new_c9[`ERR_DRC]
) &
err_state_new_c9[`ERR_DAC];
/////////////////////////////////////////////////////
// DSC bit
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DSC] = dram_scb_secc_err_d1 ;
dff_s #(1) ff_err_state_new_c9_dsc
(.din(err_state_new_c8[`ERR_DSC]), .clk(rclk),
.q(err_state_new_c9[`ERR_DSC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DSC] = err_state_new_c9[`ERR_DSC] ;
/////////////////////////////////////////////////////
// MEC bit
// set if the corr err detected is unable to record in the L2 esr
// OR if an uncorrectable err happens when a corr err has already occurred.
/////////////////////////////////////////////////////
assign wr_cerr_vec_c9 = { err_status_in[`ERR_LTC],
err_status_in[`ERR_LDAC],
err_status_in[`ERR_LDRC],
err_status_in[`ERR_LDWC],
err_status_in[`ERR_LDSC],
err_status_in[`ERR_DAC],
err_status_in[`ERR_DRC] } ;
assign new_cerr_vec_c9 = { err_state_new_c9[`ERR_LTC],
err_state_new_c9[`ERR_LDAC],
err_state_new_c9[`ERR_LDRC],
err_state_new_c9[`ERR_LDWC],
err_state_new_c9[`ERR_LDSC],
err_state_new_c9[`ERR_DAC],
err_state_new_c9[`ERR_DRC] } ;
assign err_status_in[`ERR_MEC] = (|( ~wr_cerr_vec_c9 & new_cerr_vec_c9 )) |
( err_status_in[`ERR_VEU] & error_status_vec ) ;
/////////////////////////////////////////////////////
// VEC bit
/////////////////////////////////////////////////////
assign err_status_in[`ERR_VEC] = |( new_cerr_vec_c9 ) ;
/////////////////////////////////////////////////////
// RW bit
// 1 for a write access
// Set to 1 for Stores, strm stores, CAs, SWAP, LDSTUB
// or rdma psts that encounter an error.
/////////////////////////////////////////////////////
assign rdma_pst_err_c9 = bscd_uncorr_err_c9 | bscd_corr_err_c9 ;
dff_s #(1) ff_store_error_c9
(.din(store_err_c8), .clk(rclk),
.q(store_error_c9),
.se(se), .si(), .so());
assign error_spc = ( err_status_in[`ERR_LDAU] | err_status_in[`ERR_LDAC] |
err_status_in[`ERR_DAU] | err_status_in[`ERR_DAC]) ;
assign error_bsc = ( err_status_in[`ERR_LDRU] | err_status_in[`ERR_LDRC] |
err_status_in[`ERR_DRU] | err_status_in[`ERR_DRC] );
assign err_status_in[`ERR_RW] = ( store_error_c9 & error_spc) |
( rdma_pst_err_c9 & error_bsc &
~( rdmard_uerr_c13 | rdmard_cerr_c13 ) ) ;
assign error_rw_en = ( error_spc | error_bsc ) |
( diag_wr_en ) ;
/////////////////////////////////////////////////////
// ERROR STATUS BITS to CSR from csr_ctl.
/////////////////////////////////////////////////////
assign err_state_in_mec = err_status_in[`ERR_MEC];
assign err_state_in_meu = err_status_in[`ERR_MEU];
assign err_state_in_rw = err_status_in[`ERR_RW];
assign err_state_in[`ERR_LDAC:`ERR_VEU] = err_status_in[`ERR_LDAC:`ERR_VEU] ;
/////////////////////////////////////////////////////
// SYNDROME
// recorded for
// * vuad errors
// * ldac/ldau
// * ldrc/ldru for rdma writes only.
/////////////////////////////////////////////////////
dff_s #(1) ff_rdmard_uerr_c13
(.din(rdmard_uerr_c12), .clk(rclk),
.q(rdmard_uerr_c13),
.se(1'b0), .si(), .so());
dff_s #(1) ff_rdmard_cerr_c13
(.din(rdmard_cerr_c12), .clk(rclk),
.q(rdmard_cerr_c13),
.se(1'b0), .si(), .so());
assign mux1_synd_sel[0] = err_status_in[`ERR_LVU];
assign mux1_synd_sel[1] = ~err_status_in[`ERR_LVU];
assign mux2_synd_sel[0] = ((err_state_new_c9[`ERR_LDAU] |
err_state_new_c9[`ERR_LDAC]) |
(( err_state_new_c9[`ERR_LDRU] |
err_state_new_c9[`ERR_LDRC] ) &
~( rdmard_uerr_c13 | rdmard_cerr_c13 ))
) ;
assign mux2_synd_sel[1] = ~mux2_synd_sel[0] ;
assign csr_synd_wr_en = diag_wr_en |
( new_err_sel & ( mux1_synd_sel[0] | mux2_synd_sel[0] )) ;
/////////////////////////////////////////////////////
// TID
// reported for
// * ldac/ldau errors
// * dac/dau errors when they are
// detected/reported by an instruction other than a FILL
/////////////////////////////////////////////////////
assign wr_enable_tid_c9 = ( err_status_in[`ERR_LDAC] |
err_status_in[`ERR_LDAU] |
err_status_in[`ERR_DAC] |
err_status_in[`ERR_DAU] ) ;
assign csr_tid_wr_en = ( wr_enable_tid_c9 | diag_wr_en ) ;
/////////////////////////////////////////////////////
// ASYNC
// reported for only ldac/ldau errors.
/////////////////////////////////////////////////////
dff_s #(1) ff_str_ld_hit_c8 (.din(str_ld_hit_c7), .clk(rclk),
.q(str_ld_hit_c8),
.se(1'b0), .si(), .so());
dff_s #(1) ff_str_ld_hit_c9 (.din(str_ld_hit_c8), .clk(rclk),
.q(str_ld_hit_c9),
.se(1'b0), .si(), .so());
dff_s #(1) ff_async_bit_c9 (.q(async_bit_c9), .clk(rclk),
.din(arbdp_async_bit_c8),
.se(se), .si(), .so());
assign wr_enable_async_c9 = (err_status_in[`ERR_LDAC] |
err_status_in[`ERR_DAC] |
err_status_in[`ERR_DAU] |
err_status_in[`ERR_LDAU] ) ;
assign set_async_c9 = str_ld_hit_c9 & async_bit_c9 ;
assign csr_async_wr_en = ( wr_enable_async_c9 |
diag_wr_en ) ;
/////////////////////////////////////////////////////
// ADDRESS PRIORITIES
/////////////////////////////////////////////////////
//
// 1. LVU pipe-addr
// 2. LRU dir_addr
// 3a. LDSU scrub addr
// 3b. LDAU pipe_addr.
// 4. LDWU evict_addr
// 5a. LDRU rdma rd addr.
// 5b. LDRU pipe_addr.
// 6a. DRU rdma rd addr.
// 6b. DRU pipe addr
// 6c. DAU pipe_addr
// 7. LTC pipe_addr
// 8a. LDSC scrub addr.
// 8b. LDAC pipe_addr
// 9. LDWC evict_addr
// 10a. LDRC rdma rd addr.
// 10b. LDRC pipe_addr.
// 11a DRC rdma rd addr.
// 11b DRC pipe addr
// 11c DAC pipe_addr.
/////////////////////////////////////////////////////
dff_s #(1) ff_bscd_uncorr_err_c9
(.din(decc_bscd_uncorr_err_c8), .clk(rclk),
.q(bscd_uncorr_err_c9),
.se(se), .si(), .so());
dff_s #(1) ff_bscd_corr_err_c9
(.din(decc_bscd_corr_err_c8), .clk(rclk),
.q(bscd_corr_err_c9),
.se(se), .si(), .so());
dff_s #(1) ff_bsc_corr_err_c13
(.din(fbctl_bsc_corr_err_c12), .clk(rclk),
.q(bsc_corr_err_c13),
.se(1'b0), .si(), .so());
assign mux1_addr_sel_tmp[0] = err_state_new_c9[`ERR_LRU] ; // sel dir addr.
assign mux1_addr_sel_tmp[1] =
(( err_state_new_c9[`ERR_LDSU] & ~err_state_new_c9[`ERR_LRU] ) |
( err_state_new_c9[`ERR_LDSC] & ~err_status_in[`ERR_VEU]) ) ; // scrub addr.
assign mux1_addr_sel_tmp[2] = (( err_state_new_c9[`ERR_LDWU] & ~err_state_new_c9[`ERR_LDSU]
& ~err_state_new_c9[`ERR_LRU] ) |
( err_state_new_c9[`ERR_LDWC] &
~err_status_in[`ERR_VEU] &
~err_state_new_c9[`ERR_LDSC]) ) ; // evict addr.
assign mux1_addr_sel_tmp[3] = ~|(mux1_addr_sel_tmp[2:0]);
assign mux1_addr_sel[0] = mux1_addr_sel_tmp[0] & ~rst_tri_en ;
assign mux1_addr_sel[1] = mux1_addr_sel_tmp[1] & ~rst_tri_en ;
assign mux1_addr_sel[2] = mux1_addr_sel_tmp[2] & ~rst_tri_en ;
assign mux1_addr_sel[3] = ( mux1_addr_sel_tmp[3] | rst_tri_en ) ;
assign err_sel = ( err_status_in[`ERR_VEC] |
err_status_in[`ERR_VEU] ) ;
assign diag_wr_en = csr_errstate_wr_en_c8 & ~err_sel ;
assign rdmard_addr_sel_c13 = ( (err_state_new_c9[`ERR_LDRU] | err_state_new_c9[`ERR_DRU] ) |
(( err_state_new_c9[`ERR_LDRC] | err_state_new_c9[`ERR_DRC])
& ~err_status_in[`ERR_VEU])) &
(rdmard_uerr_c13 |
rdmard_cerr_c13 |
bsc_corr_err_c13 ); // rdma rd addr only
// Fix for bug#4375
// when an error is detected in a rdma rd and a wr8 in the same cycle,
// the wr8 address is discarded and the rdma rd address is selected.
// the pipe_addr_sel expression needed appropriate qualifications with
// rdmard_uerr_c13 & ( rdmard_cerr_c13 | bsc_corr_err_c13 )
assign pipe_addr_sel = ( err_state_new_c9[`ERR_LVU] |
(~err_state_new_c9[`ERR_LRU] & err_state_new_c9[`ERR_LDAU] ) |
(~err_state_new_c9[`ERR_LRU] & ~err_state_new_c9[`ERR_LDWU] & bscd_uncorr_err_c9 & ~rdmard_uerr_c13)) |
(~err_status_in[`ERR_VEU] &
(err_state_new_c9[`ERR_LTC] |
err_state_new_c9[`ERR_LDAC] |
( bscd_corr_err_c9 & ~err_state_new_c9[`ERR_LDWC] & ~rdmard_cerr_c13 & ~bsc_corr_err_c13 ))
); // pipe addr only
assign mux2_addr_sel_tmp[0] = ( rdmard_addr_sel_c13 |
(|(mux1_addr_sel_tmp[2:0])) ) &
~pipe_addr_sel ; // sel mux1
// if err
// or rdma rd
assign mux2_addr_sel_tmp[1] = err_sel & ~mux2_addr_sel_tmp[0] ; // sel pipe addr
// a9
assign mux2_addr_sel_tmp[2] = ~(mux2_addr_sel_tmp[1] | mux2_addr_sel_tmp[0] ) ;
// sel wr data.
assign mux2_addr_sel[0] = mux2_addr_sel_tmp[0] & ~rst_tri_en ;
assign mux2_addr_sel[1] = mux2_addr_sel_tmp[1] & ~rst_tri_en ;
assign mux2_addr_sel[2] = ( mux2_addr_sel_tmp[2] | rst_tri_en ) ;
assign new_err_sel = |(wr_uerr_vec_c9) | (|(wr_cerr_vec_c9) ) ;
// An error gets priority to write into the EAR if an error
// and a diagnostic write try to update the EAR in the same cycle.
// Bug #3986.
// err_addr_sel indicates that an error occurred. In this case,
// any diagnostic write is disabled.
assign csr_addr_wr_en = ( csr_erraddr_wr_en_c8 & ~err_sel ) | new_err_sel ;
/////////////////////////////////////////////////////
// POR signalled for LVU/LRU
// PMB requires reset assertion for 6 cycles.
// The following signal is not a C8 signal but
// that is the name it has been given.
//
// This request is conditioned in JBI with an enable bit
// before actually causing a POR.
/////////////////////////////////////////////////////
assign en_por_c7 = ( err_state_new_c9[`ERR_LVU] | err_state_new_c9[`ERR_LRU] ) ;
dff_s #(1) ff_en_por_c7_d1 (.din(en_por_c7), .clk(rclk),
.q(en_por_c7_d1),
.se(1'b0), .si(), .so());
assign sctag_por_req = en_por_c7_d1 ;
endmodule
|
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*
********************* REGISTER MAP ************************************
*
* ******** Motor channel registers ********
*
* There are 3 sets of motor channel registers:
*
* Channel 0 has addresses 0,1, and 2
* Channel 1 has addresses 4,5, and 6
* Channel 2 has addresses 8,9 and a
*
*
*** Address 0,4,8 : Tach Low Byte (R), PWM Register (W) ***
*
* Read
*
* Least significant byte of tach register. Reading automatically
* latches the high byte for future access.
*
* Write
*
* PWM value. 8'h80 corresponds to a 50% duty cycle. The motor would
* be off in this case. 8'h80 is the default at power on.
*
*** Address 1,5,9 : Tach High Byte(R) ***
*
* Most significant byte of tach register. This has to be latched by
* reading the low byte first.
*
*
*** Address 2,6,a : Motor Config Register (W) ***
*
* Bit 7 : Reserved set to 0
* Bit 6 : Reserved set to 0
* Bit 5 : invert tach
* Bit 4 : invert pwm
* Bit 3 : Tach filter divisor msb
* Bit 2 : Tach filter divisor lsb
* Bit 1 : PWM clock divisor msb
* Bit 0 : PWM clock divisor lsb
*
* Tach filter bits. number of 32 cycle system clock periods to use for
* the tach filter
*
* 00 - Multiply by 1
* 01 - Multiply by 2
* 10 - Multiply by 4
* 11 - Multiply by 8
*
* PWM Generator clock divisor bits. Number of system clock periods
* to use for one increment of the PWM counter
*
* 00 - Multiply by 1
* 01 - Multiply by 2
* 10 - Multiply by 4
* 11 - Multiply by 8
*
******** Control Registers *********
*
*** Address d : Hardware Config Register (R) ***
*
* Bits 7,6 : Reserved, set to 0.
* Bits 5,4 : Number of motor channels supported
* Bits 3-0 : FPGA code level.
*
*
*** Address e : Watchdog divisor (W) ***
*
* Programs the watchdog trip time in counts of 16384 system clocks.
* This register must be written when motor enable is false. All
* writes to this register will be ignored when motor enable is true.
*
*
*** Address f : Control Register (R/W) ***
*
* Bit 7 : Watchdog tripped
* Bit 6 : Watchdog disabled
* Bit 5 : Reserved, reads back as 0
* Bit 4 : Reserved, reads back as 0
* Bit 3 : Master Motor Enable
* Bit 2 : Run2/~Brake2
* Bit 1 : Run1/~Brake1
* Bit 0 : Run0/~Brake0
*
* 1. The watchdog timer is reset when this register is read.
*
* 2. The watchdog timer is enabled whenever the motor is enabled,
* and the wdogdisn pin is high. If the watchdog timer is enabled,
* the control register must be read periodically so that the
* watchdog does not trip.
*
* 3. If the watchdog is tripped, motor enable will be masked
* even though it is set true. To reset the watchdog, write a
* 8'h80 to the port, then re-enable the motor by setting bit 3.
* A watchdog trip event is noted by bit 7 being set high.
*
* 4. Runx/~Brakex
*
* When these bits are high, the motor is in run mode and will respond
* to pwm commands if the master motor enable is also set. If these
* bits get set to 0, then the motor dynamic brake circuit will be
* activated.
*/
/*
* Top level with all I/O polarities adjusted, and tristate outputs added
*/
`default_nettype none
module root(
input clk,
input sclk,
input ssn,
input mosi,
input tstn,
input wdogdisn,
input currentlimit0,
input currentlimit1,
input currentlimit2,
input [1:0] tach0,
input [1:0] tach1,
input [1:0] tach2,
output miso,
output motorena,
output ledaliven,
output redled0,
output redled1,
output redled2,
output redled3,
output [1:0] pwm0,
output [3:0] pwm40,
output [1:0] pwm1,
output [3:0] pwm41,
output [1:0] pwm2,
output [3:0] pwm42);
wire misoi;
wire ledalive;
wire spioe;
wire ss;
wire tst;
wire wdogdis;
reg misoreg;
reg redledreg1 = 0;
reg redledreg2 = 0;
reg redledreg3 = 0;
system sys0(
.clk(clk),
.sclk(sclk),
.ss(ss),
.mosi(mosi),
.spioe(spioe),
.tst(tst),
.wdogdis(wdogdis),
.currentlimit0(currentlimit0),
.currentlimit1(currentlimit1),
.currentlimit2(currentlimit2),
.tach0(tach0),
.tach1(tach1),
.tach2(tach2),
.miso(misoi),
.motorena(motorena),
.ledalive(ledalive),
.pwm0(pwm0),
.pwm40(pwm40),
.pwm1(pwm1),
.pwm41(pwm41),
.pwm2(pwm2),
.pwm42(pwm42));
assign miso = misoreg;
assign tst = ~tstn;
assign ss = ~ssn;
assign wdogdis = ~wdogdisn;
assign ledaliven = ~ledalive;
assign redled0 = motorena;
assign redled1 = redledreg1;
assign redled2 = redledreg2;
assign redled3 = redledreg3;
always @(*) begin
if(spioe)
misoreg <= misoi;
else
misoreg <= 1'bz;
end
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
(** We allow to unfold the [relation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind relational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : relation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : relation A) : relation A := fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : relation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : relation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : relation A) :=
asymmetry : forall {x y}, R x y -> R y x -> False.
Class Transitive (R : relation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : relation A) : Prop := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : relation A) : Prop := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence relation is Symmetric and Transitive. *)
Class PER (R : relation A) : Prop := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence relations. *)
Class Equivalence (R : relation A) : Prop := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(E:Equivalence R) : PER R | 10 :=
{ }.
(** An Equivalence is a PreOrder plus symmetry. *)
Global Instance Equivalence_PreOrder {R} `(E:Equivalence R) : PreOrder R | 10 :=
{ }.
(** We can now define antisymmetry w.r.t. an equivalence relation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : relation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : relation A) : Prop :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric relation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros. red in H0. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite relation on a given support: declares a relation as a rewrite
relation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
relations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : relation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite relation. *)
Global Instance equivalence_rewrite_relation `(Equivalence eqA) : RewriteRelation eqA.
Defined.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence relation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite relations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Defined.
Instance: RewriteRelation iff.
Defined.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Arguments irreflexivity {A R Irreflexive} [x] _.
Arguments symmetry {A} {R} {_} [x] [y] _.
Arguments asymmetry {A} {R} {_} [x] [y] _ _.
Arguments transitivity {A} {R} {_} [x] [y] [z] _ _.
Arguments Antisymmetric A eqA {_} _.
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for relations. *)
Ltac solve_relation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_relation : relations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_relation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_relation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence relation. *)
Program Instance iff_equivalence : Equivalence iff.
(** We now develop a generalization of results on relations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary relations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(* Note, we do not use [list Type] because it imposes unnecessary universe constraints *)
#[universes(template)]
Inductive Tlist : Type := Tnil : Tlist | Tcons : Type -> Tlist -> Tlist.
Local Infix "::" := Tcons.
Fixpoint arrows (l : Tlist) (r : Type) : Type :=
match l with
| Tnil => r
| A :: l' => A -> arrows l' r
end.
(** We can define abbreviations for operation and relation types based on [arrows]. *)
Definition unary_operation A := arrows (A::Tnil) A.
Definition binary_operation A := arrows (A::A::Tnil) A.
Definition ternary_operation A := arrows (A::A::A::Tnil) A.
(** We define n-ary [predicate]s as functions into [Prop]. *)
Notation predicate l := (arrows l Prop).
(** Unary predicates, or sets. *)
Definition unary_predicate A := predicate (A::Tnil).
(** Homogeneous binary relations, equivalent to [relation A]. *)
Definition binary_relation A := predicate (A::A::Tnil).
(** We can close a predicate by universal or existential quantification. *)
Fixpoint predicate_all (l : Tlist) : predicate l -> Prop :=
match l with
| Tnil => fun f => f
| A :: tl => fun f => forall x : A, predicate_all tl (f x)
end.
Fixpoint predicate_exists (l : Tlist) : predicate l -> Prop :=
match l with
| Tnil => fun f => f
| A :: tl => fun f => exists x : A, predicate_exists tl (f x)
end.
(** Pointwise extension of a binary operation on [T] to a binary operation
on functions whose codomain is [T].
For an operator on [Prop] this lifts the operator to a binary operation. *)
Fixpoint pointwise_extension {T : Type} (op : binary_operation T)
(l : Tlist) : binary_operation (arrows l T) :=
match l with
| Tnil => fun R R' => op R R'
| A :: tl => fun R R' =>
fun x => pointwise_extension op tl (R x) (R' x)
end.
(** Pointwise lifting, equivalent to doing [pointwise_extension] and closing using [predicate_all]. *)
Fixpoint pointwise_lifting (op : binary_relation Prop) (l : Tlist) : binary_relation (predicate l) :=
match l with
| Tnil => fun R R' => op R R'
| A :: tl => fun R R' =>
forall x, pointwise_lifting op tl (R x) (R' x)
end.
(** The n-ary equivalence relation, defined by lifting the 0-ary [iff] relation. *)
Definition predicate_equivalence {l : Tlist} : binary_relation (predicate l) :=
pointwise_lifting iff l.
(** The n-ary implication relation, defined by lifting the 0-ary [impl] relation. *)
Definition predicate_implication {l : Tlist} :=
pointwise_lifting impl l.
(** Notations for pointwise equivalence and implication of predicates. *)
Declare Scope predicate_scope.
Infix "<∙>" := predicate_equivalence (at level 95, no associativity) : predicate_scope.
Infix "-∙>" := predicate_implication (at level 70, right associativity) : predicate_scope.
Local Open Scope predicate_scope.
(** The pointwise liftings of conjunction and disjunctions.
Note that these are [binary_operation]s, building new relations out of old ones. *)
Definition predicate_intersection := pointwise_extension and.
Definition predicate_union := pointwise_extension or.
Infix "/∙\" := predicate_intersection (at level 80, right associativity) : predicate_scope.
Infix "\∙/" := predicate_union (at level 85, right associativity) : predicate_scope.
(** The always [True] and always [False] predicates. *)
Fixpoint true_predicate {l : Tlist} : predicate l :=
match l with
| Tnil => True
| A :: tl => fun _ => @true_predicate tl
end.
Fixpoint false_predicate {l : Tlist} : predicate l :=
match l with
| Tnil => False
| A :: tl => fun _ => @false_predicate tl
end.
Notation "∙⊤∙" := true_predicate : predicate_scope.
Notation "∙⊥∙" := false_predicate : predicate_scope.
(** Predicate equivalence is an equivalence, and predicate implication defines a preorder. *)
Program Instance predicate_equivalence_equivalence :
Equivalence (@predicate_equivalence l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
fold pointwise_lifting.
induction l.
- firstorder.
- intros. simpl in *. pose (IHl (x x0) (y x0) (z x0)).
firstorder.
Qed.
Program Instance predicate_implication_preorder :
PreOrder (@predicate_implication l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l.
- firstorder.
- unfold predicate_implication in *. simpl in *.
intro. pose (IHl (x x0) (y x0) (z x0)). firstorder.
Qed.
(** We define the various operations which define the algebra on binary relations,
from the general ones. *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : relation (relation A) :=
@predicate_equivalence (_::_::Tnil).
Global Instance: RewriteRelation relation_equivalence.
Defined.
Definition relation_conjunction (R : relation A) (R' : relation A) : relation A :=
@predicate_intersection (A::A::Tnil) R R'.
Definition relation_disjunction (R : relation A) (R' : relation A) : relation A :=
@predicate_union (A::A::Tnil) R R'.
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof. exact (@predicate_equivalence_equivalence (A::A::Tnil)). Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. exact (@predicate_implication_preorder (A::A::Tnil)). Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence relation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
pose proof partial_order_equivalence as poe. do 3 red in poe.
apply <- poe. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof. firstorder. Qed.
End Binary.
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and relation equivalence. *)
Program Instance subrelation_partial_order :
! PartialOrder (relation A) relation_equivalence subrelation.
Next Obligation.
Proof.
unfold relation_equivalence in *. compute; firstorder.
Qed.
Typeclasses Opaque arrows predicate_implication predicate_equivalence
relation_equivalence pointwise_lifting.
|
// UC Berkeley CS251
// Spring 2018
// Arya Reais-Parsi ([email protected])
`include "const.vh"
module no_cache_mem #(
parameter CPU_WIDTH = `CPU_INST_BITS,
parameter WORD_ADDR_BITS = `CPU_ADDR_BITS-`ceilLog2(`CPU_INST_BITS/8)
) (
input clk,
input reset,
input cpu_req_val,
output cpu_req_rdy,
input [WORD_ADDR_BITS-1:0] cpu_req_addr,
input [CPU_WIDTH-1:0] cpu_req_data,
input [3:0] cpu_req_write,
output reg cpu_resp_val,
output reg [CPU_WIDTH-1:0] cpu_resp_data
);
localparam DEPTH = 2*512*512;
localparam WORDS = `MEM_DATA_BITS/CPU_WIDTH;
reg [`MEM_DATA_BITS-1:0] ram [DEPTH-1:0];
wire [WORD_ADDR_BITS-`ceilLog2(WORDS)-1:0] upper_addr;
assign upper_addr = cpu_req_addr[WORD_ADDR_BITS-1:`ceilLog2(WORDS)];
wire [`ceilLog2(WORDS)-1:0] lower_addr;
assign lower_addr = cpu_req_addr[`ceilLog2(WORDS)-1:0];
wire [`MEM_DATA_BITS-1:0] read_data;
assign read_data = (ram[upper_addr] >> CPU_WIDTH*lower_addr);
assign cpu_req_rdy = 1'b1;
wire [CPU_WIDTH-1:0] wmask;
assign wmask = {{8{cpu_req_write[3]}},{8{cpu_req_write[2]}},{8{cpu_req_write[1]}},{8{cpu_req_write[0]}}};
wire [`MEM_DATA_BITS-1:0] write_data;
assign write_data = (ram[upper_addr] & ~({{`MEM_DATA_BITS-CPU_WIDTH{1'b0}},wmask} << CPU_WIDTH*lower_addr)) | ((cpu_req_data & wmask) << CPU_WIDTH*lower_addr);
always @(posedge clk) begin
if (reset)
cpu_resp_val <= 1'b0;
else if (cpu_req_val && cpu_req_rdy) begin
if (cpu_req_write) begin
cpu_resp_val <= 1'b0;
ram[upper_addr] <= write_data;
end else begin
cpu_resp_val <= 1'b1;
cpu_resp_data <= read_data[CPU_WIDTH-1:0];
end
end else
cpu_resp_val <= 1'b0;
end
initial
begin : zero
integer i;
for (i = 0; i < DEPTH; i = i + 1)
ram[i] = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_1_V
`define SKY130_FD_SC_MS__O2111AI_1_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111ai_1 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Oct 29 01:04:43 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch3_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
overflow_flag, underflow_flag, zero_flag, busy, data_output );
input [63:0] data_in;
input [1:0] shift_region_flag;
output [63:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag, zero_flag, busy;
wire ready_add_subt, d_ff1_operation_out, d_ff3_sign_out,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_intAS,
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5,
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6,
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_,
n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693,
n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703,
n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713,
n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723,
n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733,
n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743,
n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753,
n1754, n1755, n1756, n1757, n1758, n1759, n1761, n1762, n1763, n1764,
n1765, n1766, n1767, n1769, n1770, n1771, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1821, n1822, n1823, n1825, n1826, n1827, n1829, n1830,
n1831, n1833, n1834, n1835, n1837, n1838, n1839, n1841, n1842, n1843,
n1845, n1846, n1847, n1849, n1850, n1851, n1853, n1854, n1855, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1870, n1871, n1872, n1873, n1874, n1875, n1877, n1878, n1879,
n1880, n1881, n1882, n1884, n1885, n1886, n1887, n1888, n1889, n1891,
n1892, n1893, n1894, n1895, n1896, n1898, n1899, n1900, n1902, n1903,
n1904, n1906, n1907, n1908, n1910, n1911, n1912, n1914, n1915, n1916,
n1918, n1919, n1920, n1921, n1922, n1923, n1925, n1926, n1927, n1928,
n1929, n1930, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939,
n1940, n1941, n1942, n1943, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1955, n1956, n1957, n1958, n1959, n1960, n1962,
n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1972, n1973,
n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1982, n1983, n1984,
n1985, n1986, n1987, n1989, n1990, n1991, n1992, n1993, n1994, n1996,
n1997, n1998, n1999, n2000, n2001, n2003, n2004, n2005, n2006, n2007,
n2008, n2010, n2011, n2012, n2013, n2014, n2015, n2017, n2018, n2019,
n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029,
n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039,
n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049,
n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059,
n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069,
n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079,
n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089,
n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099,
n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109,
n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119,
n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129,
n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139,
n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149,
n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159,
n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169,
n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179,
n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189,
n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199,
n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209,
n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219,
n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229,
n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239,
n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249,
n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259,
n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269,
n2270, n2271, n2272, n2273, n2274, n2276, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331,
n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341,
n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351,
n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361,
n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371,
n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381,
n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391,
n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401,
n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411,
n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421,
n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531,
n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541,
n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551,
n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561,
n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571,
n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581,
n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591,
n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601,
n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611,
n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621,
n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631,
n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641,
n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651,
n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661,
n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671,
n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681,
n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691,
n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701,
n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711,
n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721,
n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731,
n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741,
n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751,
n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761,
n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771,
n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781,
n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791,
n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801,
n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811,
n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821,
n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831,
n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841,
n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851,
n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861,
n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871,
n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881,
n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921,
n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931,
n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941,
n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951,
n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961,
n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971,
n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981,
n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991,
n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001,
n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011,
n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021,
n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031,
n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041,
n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051,
n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061,
n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071,
n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081,
n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091,
n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101,
n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111,
n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121,
n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131,
n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141,
n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151,
n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161,
n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171,
n3172, n3173, DP_OP_33J12_122_5452_n22, DP_OP_33J12_122_5452_n21,
DP_OP_33J12_122_5452_n20, DP_OP_33J12_122_5452_n19,
DP_OP_33J12_122_5452_n18, DP_OP_33J12_122_5452_n17,
DP_OP_33J12_122_5452_n11, DP_OP_33J12_122_5452_n10,
DP_OP_33J12_122_5452_n9, DP_OP_33J12_122_5452_n8,
DP_OP_33J12_122_5452_n7, DP_OP_33J12_122_5452_n6,
DP_OP_33J12_122_5452_n5, DP_OP_33J12_122_5452_n4,
DP_OP_33J12_122_5452_n3, DP_OP_33J12_122_5452_n2,
DP_OP_33J12_122_5452_n1, intadd_22_CI, intadd_22_SUM_2_,
intadd_22_SUM_1_, intadd_22_SUM_0_, intadd_22_n3, intadd_22_n2,
intadd_22_n1, intadd_23_CI, intadd_23_SUM_2_, intadd_23_SUM_1_,
intadd_23_SUM_0_, intadd_23_n3, intadd_23_n2, intadd_23_n1,
intadd_24_CI, intadd_24_SUM_2_, intadd_24_SUM_1_, intadd_24_SUM_0_,
intadd_24_n3, intadd_24_n2, intadd_24_n1, n3176, n3177, n3178, n3179,
n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189,
n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199,
n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209,
n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219,
n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229,
n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239,
n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249,
n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259,
n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269,
n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279,
n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289,
n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299,
n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309,
n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319,
n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329,
n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339,
n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349,
n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359,
n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369,
n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379,
n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389,
n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399,
n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409,
n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419,
n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429,
n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439,
n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449,
n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459,
n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469,
n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479,
n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489,
n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499,
n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509,
n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519,
n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529,
n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539,
n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549,
n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559,
n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569,
n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579,
n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589,
n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599,
n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609,
n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619,
n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629,
n3630, n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639,
n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649,
n3650, n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659,
n3660, n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669,
n3670, n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679,
n3680, n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689,
n3690, n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699,
n3700, n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709,
n3710, n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719,
n3720, n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729,
n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739,
n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749,
n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759,
n3760, n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769,
n3770, n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779,
n3780, n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789,
n3790, n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799,
n3800, n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809,
n3810, n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819,
n3820, n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829,
n3830, n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839,
n3840, n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849,
n3850, n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859,
n3860, n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869,
n3870, n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879,
n3880, n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889,
n3890, n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899,
n3900, n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909,
n3910, n3911, n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919,
n3920, n3921, n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929,
n3930, n3931, n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939,
n3940, n3941, n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949,
n3950, n3951, n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959,
n3960, n3961, n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969,
n3970, n3971, n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979,
n3980, n3981, n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989,
n3990, n3991, n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999,
n4000, n4001, n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009,
n4010, n4011, n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019,
n4020, n4021, n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029,
n4030, n4031, n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039,
n4040, n4041, n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049,
n4050, n4051, n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059,
n4060, n4061, n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069,
n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079,
n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089,
n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099,
n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109,
n4110, n4111, n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119,
n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129,
n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139,
n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149,
n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159,
n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169,
n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179,
n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189,
n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199,
n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209,
n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219,
n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229,
n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239,
n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249,
n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259,
n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269,
n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279,
n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289,
n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299,
n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309,
n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319,
n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329,
n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339,
n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349,
n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359,
n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369,
n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379,
n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389,
n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399,
n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409,
n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419,
n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429,
n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439,
n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449,
n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459,
n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469,
n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479,
n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487, n4488, n4489,
n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499,
n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509,
n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519,
n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529,
n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539,
n4540, n4541, n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549,
n4550, n4551, n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559,
n4560, n4561, n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569,
n4570, n4571, n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579,
n4580, n4581, n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589,
n4590, n4591, n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599,
n4600, n4601, n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609,
n4610, n4611, n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619,
n4620, n4621, n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629,
n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639,
n4640, n4641, n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649,
n4650, n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659,
n4660, n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669,
n4670, n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679,
n4680, n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689,
n4690, n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699,
n4700, n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709,
n4710, n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719,
n4720, n4721, n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729,
n4730, n4731, n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739,
n4740, n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749,
n4750, n4751, n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759,
n4760, n4761, n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769,
n4770, n4771, n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779,
n4780, n4781, n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789,
n4790, n4791, n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799,
n4800, n4801, n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809,
n4810, n4811, n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819,
n4820, n4821, n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829,
n4830, n4831, n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839,
n4840, n4841, n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849,
n4850, n4851, n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859,
n4860, n4861, n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869,
n4870, n4871, n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879,
n4880, n4881, n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889,
n4890, n4891, n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899,
n4900, n4901, n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909,
n4910, n4911, n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919,
n4920, n4921, n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929,
n4930, n4931, n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939,
n4940, n4941, n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949,
n4950, n4951, n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959,
n4960, n4961, n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969,
n4970, n4971, n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979,
n4980, n4981, n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989,
n4990, n4991, n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999,
n5000, n5001, n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009,
n5010, n5011, n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019,
n5020, n5021, n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029,
n5030, n5031, n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039,
n5040, n5041, n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049,
n5050, n5051, n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059,
n5060, n5061, n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069,
n5070, n5071, n5072, n5073, n5074, n5075, n5076, n5077, n5078, n5079,
n5080, n5081, n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089,
n5090, n5091, n5092, n5093, n5094, n5095, n5096, n5097, n5098, n5099,
n5100, n5101, n5102, n5103, n5104, n5105, n5106, n5107, n5108, n5109,
n5110, n5111, n5112, n5113, n5114, n5115, n5116, n5117, n5118, n5119,
n5120, n5121, n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129,
n5130, n5131, n5132, n5133, n5134, n5135, n5136, n5137, n5138, n5139,
n5140, n5141, n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149,
n5150, n5151, n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159,
n5160, n5161, n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169,
n5170, n5171, n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179,
n5180, n5181, n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189,
n5190, n5191, n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199,
n5200, n5201, n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209,
n5210, n5211, n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219,
n5220, n5221, n5222, n5223, n5224, n5225, n5226, n5227, n5228, n5229,
n5230, n5231, n5232, n5233, n5234, n5235, n5236, n5237, n5238, n5239,
n5240, n5241, n5242, n5243, n5244, n5245, n5246, n5247, n5248, n5249,
n5250, n5251, n5252, n5253, n5254, n5255, n5256, n5257, n5258, n5259,
n5260, n5261, n5262, n5263, n5264, n5265, n5266, n5267, n5268, n5269,
n5270, n5271, n5272, n5273, n5274, n5275, n5276, n5277, n5278, n5279,
n5280, n5281, n5282, n5283, n5284, n5285, n5286, n5287, n5288, n5289,
n5290, n5291, n5292, n5293, n5294, n5295, n5296, n5297, n5298, n5299,
n5300, n5301, n5302, n5303, n5304, n5305, n5306, n5307, n5308, n5309,
n5310, n5311, n5312, n5313, n5314, n5315, n5316, n5317, n5318, n5319,
n5320, n5321, n5322, n5323, n5324, n5325, n5326, n5327, n5328, n5329,
n5330, n5331, n5332, n5333, n5334, n5335, n5336, n5337, n5338, n5339,
n5340, n5341, n5342, n5343, n5344, n5345, n5346, n5347, n5348, n5349,
n5350, n5351, n5352, n5353, n5354, n5355, n5356, n5357, n5358, n5359,
n5360, n5361, n5362, n5363, n5364, n5365, n5366, n5367, n5368, n5369,
n5370, n5371, n5372, n5373, n5374, n5375, n5376, n5377, n5378, n5379,
n5380, n5381, n5382, n5383, n5384, n5385, n5386, n5387, n5388, n5389,
n5390, n5391, n5392, n5393, n5394, n5395, n5396, n5397, n5398, n5399,
n5400, n5401, n5402, n5403, n5404, n5405, n5406, n5407, n5408, n5409,
n5410, n5411, n5412, n5413, n5414, n5415, n5416, n5417, n5418, n5419,
n5420, n5421, n5422, n5423, n5424, n5425, n5426, n5427, n5428, n5429,
n5430, n5431, n5432, n5433, n5434, n5435, n5436, n5437, n5438, n5439,
n5440, n5441, n5442, n5443, n5444, n5445, n5446, n5447, n5448, n5449,
n5450, n5451, n5452, n5453, n5454, n5455, n5456, n5457, n5458, n5459,
n5460, n5461, n5462, n5463, n5464, n5465, n5466, n5467, n5468, n5469,
n5470, n5471, n5472, n5473, n5474, n5475, n5476, n5477, n5478, n5479,
n5480, n5481, n5482, n5483, n5484, n5485, n5486, n5487, n5488, n5489,
n5490, n5491, n5492, n5493, n5494, n5495, n5496, n5497, n5498, n5499,
n5500, n5501, n5502, n5503, n5504, n5505, n5506, n5507, n5508, n5509,
n5510, n5511, n5512, n5513, n5514, n5515, n5516, n5517, n5518, n5519,
n5520, n5521, n5522, n5523, n5524, n5525, n5526, n5527, n5528, n5529,
n5530, n5531, n5532, n5533, n5534, n5535, n5536, n5537, n5538, n5539,
n5540, n5541, n5542, n5543, n5544, n5545, n5546, n5547, n5548, n5549,
n5550, n5551, n5552, n5553, n5554, n5555, n5556, n5557, n5558, n5559,
n5560, n5561, n5562, n5563, n5564, n5565, n5566, n5567, n5568, n5569,
n5570, n5571, n5572, n5573, n5574, n5575, n5576, n5577, n5578, n5579,
n5580, n5581, n5582, n5583, n5584, n5585, n5586, n5587, n5588, n5589,
n5590, n5591, n5592, n5593, n5594, n5595, n5596, n5597, n5598, n5599,
n5600, n5601, n5602, n5603, n5604, n5605, n5606, n5607, n5608, n5609,
n5610, n5611, n5612, n5613, n5614, n5615, n5616, n5617, n5618, n5619,
n5620, n5621, n5622, n5623, n5624, n5625, n5626, n5627, n5628, n5629,
n5630, n5631, n5632, n5633, n5634, n5635, n5636, n5637, n5638, n5639,
n5640, n5641, n5642, n5643, n5644, n5645, n5646, n5647, n5648, n5649,
n5650, n5651, n5652, n5653, n5654, n5655, n5656, n5657, n5658, n5659,
n5660, n5661, n5662, n5663, n5664, n5665, n5666, n5667, n5668, n5669,
n5670, n5671, n5672, n5673, n5674, n5675, n5676, n5677, n5678, n5679,
n5680, n5681, n5682, n5683, n5684, n5685, n5686, n5687, n5688, n5689,
n5690, n5691, n5692, n5693, n5694, n5695, n5696, n5697, n5698, n5699,
n5700, n5701, n5702, n5703, n5704, n5705, n5706, n5707, n5708, n5709,
n5710, n5711, n5712, n5713, n5714, n5715, n5716, n5717, n5718, n5719,
n5720, n5721, n5722, n5723, n5724, n5725, n5726, n5727, n5728, n5729,
n5730, n5731, n5732, n5733, n5734, n5735, n5736, n5737, n5738, n5739,
n5740, n5741, n5742, n5743, n5744, n5745, n5746, n5747, n5748, n5749,
n5750, n5751, n5752, n5753, n5754, n5755, n5756, n5757, n5758, n5759,
n5760, n5761, n5762, n5763, n5764, n5765, n5766, n5767, n5768, n5769,
n5770, n5771, n5772, n5773, n5774, n5775, n5776, n5777, n5778, n5779,
n5780, n5781, n5782, n5783, n5784, n5785, n5786, n5787, n5788, n5789,
n5790, n5791, n5792, n5793, n5794, n5795, n5796, n5797, n5798, n5799,
n5800, n5801, n5802, n5803, n5804, n5805, n5806, n5807, n5808, n5809,
n5810, n5811, n5812, n5813, n5814, n5815, n5816, n5817, n5818, n5819,
n5820, n5821, n5822, n5823, n5824, n5825, n5826, n5827, n5828, n5829,
n5830, n5831, n5832, n5833, n5834, n5835, n5836, n5837, n5838, n5839,
n5840, n5841, n5842, n5843, n5844, n5845, n5846, n5847, n5848, n5849,
n5850, n5851, n5852, n5853, n5854, n5855, n5856, n5857, n5858, n5859,
n5860, n5861, n5862, n5863, n5864, n5865, n5866, n5867, n5868, n5869,
n5870, n5871, n5872, n5873, n5874, n5875, n5876, n5877, n5878, n5879,
n5880, n5881, n5882, n5883, n5884, n5885, n5886, n5887, n5888, n5889,
n5890, n5891, n5892, n5893, n5894, n5895, n5896, n5897, n5898, n5899,
n5900, n5901, n5902, n5903, n5904, n5905, n5906, n5907, n5908, n5909,
n5910, n5911, n5912, n5913, n5914, n5915, n5916, n5917, n5918, n5919,
n5920, n5921, n5922, n5923, n5924, n5925, n5926, n5927, n5928, n5929,
n5930, n5931, n5932, n5933, n5934, n5935, n5936, n5937, n5938, n5939,
n5940, n5941, n5942, n5943, n5944, n5945, n5946, n5947, n5948, n5949,
n5950, n5951, n5952, n5953, n5954, n5955, n5956, n5957, n5958, n5959,
n5960, n5961, n5962, n5963, n5964, n5965, n5966, n5967, n5968, n5969,
n5970, n5971, n5972, n5973, n5974, n5975, n5976, n5977, n5978, n5979,
n5980, n5981, n5982, n5983, n5984, n5985, n5986, n5987, n5988, n5989,
n5990, n5991, n5992, n5993, n5994, n5995, n5996, n5997, n5998, n5999,
n6000, n6001, n6002, n6003, n6004, n6005, n6006, n6007, n6008, n6009,
n6010, n6011, n6012, n6013, n6014, n6015, n6016, n6017, n6018, n6019,
n6020, n6021, n6022, n6023, n6024, n6025, n6026, n6027, n6028, n6029,
n6030, n6031, n6032, n6033, n6034, n6035, n6036, n6037, n6038, n6039,
n6040, n6041, n6042, n6043, n6044, n6045, n6046, n6047, n6048, n6049,
n6050, n6051, n6052, n6053, n6054, n6055, n6056, n6057, n6058, n6059,
n6060, n6061, n6062, n6063, n6064, n6065, n6066, n6067, n6068, n6069,
n6070, n6071, n6072, n6073, n6074, n6075, n6076, n6077, n6078, n6079,
n6080, n6081, n6082, n6083, n6084, n6085, n6086, n6087, n6088, n6089,
n6090, n6091, n6092, n6093, n6094, n6095, n6096, n6097, n6098, n6099,
n6100, n6101, n6102, n6103, n6104, n6105, n6106, n6107, n6108, n6109,
n6110, n6111, n6112, n6113, n6114, n6115, n6116, n6117, n6118, n6119,
n6120, n6121, n6122, n6123, n6124, n6125, n6126, n6127, n6128, n6129,
n6130, n6131, n6132, n6133, n6134, n6135, n6136, n6137, n6138, n6139,
n6140, n6141, n6142, n6143, n6144, n6145, n6146, n6147, n6148, n6149,
n6150, n6151, n6152, n6153, n6154, n6155, n6156, n6157, n6158, n6159,
n6160, n6161, n6162, n6163, n6164, n6165, n6166, n6167, n6168, n6169,
n6170, n6171, n6172, n6173, n6174, n6175, n6176, n6177, n6178, n6179,
n6180, n6181, n6182, n6183, n6184, n6185, n6186, n6187, n6188, n6189,
n6190, n6191, n6192, n6193, n6194, n6195, n6196, n6197, n6198, n6199,
n6200, n6201, n6202, n6203, n6204, n6205, n6206, n6207, n6208, n6209,
n6210, n6211, n6212, n6213, n6214, n6215, n6216, n6217, n6218, n6219,
n6220, n6221, n6222, n6223, n6224, n6225, n6226, n6227, n6228, n6229,
n6230, n6231, n6232, n6233, n6234, n6235, n6236, n6237, n6238, n6239,
n6240, n6241, n6242, n6243, n6244, n6245, n6246, n6248, n6249, n6250,
n6251, n6252, n6253, n6254, n6255, n6256, n6257, n6258, n6259, n6260,
n6261, n6262, n6263, n6264, n6265, n6266, n6267, n6268, n6269, n6270,
n6271, n6272, n6273, n6274, n6275, n6276, n6277, n6278, n6279, n6280,
n6281, n6282, n6283, n6284, n6285, n6286, n6287, n6288, n6289, n6290,
n6291, n6292, n6293, n6294, n6295, n6296, n6297, n6298, n6299, n6300,
n6301, n6302, n6303, n6304, n6305, n6306, n6307, n6308, n6309, n6310,
n6311, n6312, n6313, n6314, n6315, n6316, n6317, n6318, n6319, n6320,
n6321, n6322, n6323, n6324;
wire [3:0] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] d_ff_Yn;
wire [63:0] d_ff_Zn;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [63:0] result_add_subt;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
wire [54:0] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR;
wire [62:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SFG;
wire [10:0] inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1;
wire [5:0] inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW;
wire [10:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW;
wire [10:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW;
wire [5:2] inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR;
wire [62:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW;
wire [54:0] inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR;
wire [54:0] inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR;
wire [5:1] inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR;
wire [51:0] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW;
wire [62:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW;
wire [57:0] inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW;
wire [62:0] inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW;
wire [63:0] inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW;
wire [63:0] inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW;
wire [3:0] inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7;
wire [2:0] inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n3193), .CK(clk), .RN(n6166), .Q(ready_add_subt) );
DFFRXLTS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n6312), .Q(
inst_CORDIC_FSM_v3_state_reg[7]), .QN(n5929) );
DFFRXLTS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n6246), .CK(clk), .RN(
n6312), .Q(inst_CORDIC_FSM_v3_state_reg[3]), .QN(n5903) );
DFFRXLTS reg_operation_Q_reg_0_ ( .D(n3110), .CK(clk), .RN(n6312), .Q(
d_ff1_operation_out), .QN(n6040) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(n3109), .CK(clk), .RN(n6312), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n5922) );
DFFRXLTS reg_region_flag_Q_reg_1_ ( .D(n3108), .CK(clk), .RN(n6312), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n5896) );
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n3107), .CK(clk), .RN(n6312), .Q(d_ff1_Z[62])
);
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(n3106), .CK(clk), .RN(n6312), .Q(d_ff1_Z[61])
);
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(n3105), .CK(clk), .RN(n6312), .Q(d_ff1_Z[60])
);
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(n3104), .CK(clk), .RN(n6311), .Q(d_ff1_Z[59])
);
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(n3103), .CK(clk), .RN(n6311), .Q(d_ff1_Z[58])
);
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n3102), .CK(clk), .RN(n6311), .Q(d_ff1_Z[57])
);
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(n3101), .CK(clk), .RN(n6311), .Q(d_ff1_Z[56])
);
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(n3100), .CK(clk), .RN(n6311), .Q(d_ff1_Z[55])
);
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(n3099), .CK(clk), .RN(n6311), .Q(d_ff1_Z[54])
);
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(n3098), .CK(clk), .RN(n6311), .Q(d_ff1_Z[53])
);
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(n3097), .CK(clk), .RN(n6311), .Q(d_ff1_Z[52])
);
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(n3096), .CK(clk), .RN(n6311), .Q(d_ff1_Z[51])
);
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(n3095), .CK(clk), .RN(n6311), .Q(d_ff1_Z[50])
);
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n3094), .CK(clk), .RN(n6310), .Q(d_ff1_Z[49])
);
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(n3093), .CK(clk), .RN(n6310), .Q(d_ff1_Z[48])
);
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(n3092), .CK(clk), .RN(n6310), .Q(d_ff1_Z[47])
);
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(n3091), .CK(clk), .RN(n6310), .Q(d_ff1_Z[46])
);
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(n3090), .CK(clk), .RN(n6310), .Q(d_ff1_Z[45])
);
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(n3089), .CK(clk), .RN(n6310), .Q(d_ff1_Z[44])
);
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(n3088), .CK(clk), .RN(n6310), .Q(d_ff1_Z[43])
);
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(n3087), .CK(clk), .RN(n6310), .Q(d_ff1_Z[42])
);
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(n3086), .CK(clk), .RN(n6310), .Q(d_ff1_Z[41])
);
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(n3085), .CK(clk), .RN(n6310), .Q(d_ff1_Z[40])
);
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(n3084), .CK(clk), .RN(n6309), .Q(d_ff1_Z[39])
);
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(n3083), .CK(clk), .RN(n6309), .Q(d_ff1_Z[38])
);
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(n3082), .CK(clk), .RN(n6309), .Q(d_ff1_Z[37])
);
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(n3081), .CK(clk), .RN(n6309), .Q(d_ff1_Z[36])
);
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(n3080), .CK(clk), .RN(n6309), .Q(d_ff1_Z[35])
);
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(n3079), .CK(clk), .RN(n6309), .Q(d_ff1_Z[34])
);
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(n3078), .CK(clk), .RN(n6309), .Q(d_ff1_Z[33])
);
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(n3077), .CK(clk), .RN(n6309), .Q(d_ff1_Z[32])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n3076), .CK(clk), .RN(n6309), .Q(d_ff1_Z[31])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n3075), .CK(clk), .RN(n6309), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n3074), .CK(clk), .RN(n6308), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n3073), .CK(clk), .RN(n6308), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n3072), .CK(clk), .RN(n6308), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n3071), .CK(clk), .RN(n6308), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n3070), .CK(clk), .RN(n6308), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n3069), .CK(clk), .RN(n6308), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n3068), .CK(clk), .RN(n6308), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n3067), .CK(clk), .RN(n6308), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n3066), .CK(clk), .RN(n6308), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n3065), .CK(clk), .RN(n6308), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n3064), .CK(clk), .RN(n6307), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n3063), .CK(clk), .RN(n6307), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n3062), .CK(clk), .RN(n6307), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n3061), .CK(clk), .RN(n6307), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n3060), .CK(clk), .RN(n6307), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n3059), .CK(clk), .RN(n6307), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n3058), .CK(clk), .RN(n6307), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n3057), .CK(clk), .RN(n6307), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n3056), .CK(clk), .RN(n6307), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n3055), .CK(clk), .RN(n6307), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n3054), .CK(clk), .RN(n6306), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n3053), .CK(clk), .RN(n6306), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n3052), .CK(clk), .RN(n6306), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n3051), .CK(clk), .RN(n6306), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n3050), .CK(clk), .RN(n6306), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n3049), .CK(clk), .RN(n6306), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n3048), .CK(clk), .RN(n6306), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n3047), .CK(clk), .RN(n6306), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n3046), .CK(clk), .RN(n6306), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n3045), .CK(clk), .RN(n6306), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(n3044), .CK(clk), .RN(n6305), .Q(d_ff1_Z[63])
);
DFFRXLTS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n6305), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRXLTS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n6305), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRXLTS VAR_CONT_temp_reg_0_ ( .D(n3160), .CK(clk), .RN(n6305), .Q(
cont_var_out[0]), .QN(n5892) );
DFFRXLTS VAR_CONT_temp_reg_1_ ( .D(n3159), .CK(clk), .RN(n6305), .Q(
cont_var_out[1]), .QN(n5984) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ (
.D(n3172), .CK(clk), .RN(n6166), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(
n6038) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ (
.D(inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_),
.CK(clk), .RN(n6166), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(
n6093) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ (
.D(n3173), .CK(clk), .RN(n6166), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(
n5944) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n3171),
.CK(clk), .RN(n6166), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n6039) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n3170),
.CK(clk), .RN(n6166), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n6035) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n3168),
.CK(clk), .RN(n6245), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .QN(n6032) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n3167),
.CK(clk), .RN(n6245), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n6042) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n3166),
.CK(clk), .RN(n6244), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n5906) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n3165),
.CK(clk), .RN(n6244), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n6043) );
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(n3158), .CK(clk), .RN(n6305), .Q(
d_ff3_LUT_out[56]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n3154), .CK(clk), .RN(n6305), .Q(
d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_48_ ( .D(n3152), .CK(clk), .RN(n6305), .Q(
d_ff3_LUT_out[48]) );
DFFRXLTS reg_LUT_Q_reg_42_ ( .D(n3149), .CK(clk), .RN(n6305), .Q(
d_ff3_LUT_out[42]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n3146), .CK(clk), .RN(n6305), .Q(
d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n3132), .CK(clk), .RN(n6304), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_32_ ( .D(n3142), .CK(clk), .RN(n6304), .Q(
d_ff3_LUT_out[32]) );
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n3148), .CK(clk), .RN(n6304), .Q(
d_ff3_LUT_out[41]), .QN(n6130) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n3115), .CK(clk), .RN(n6304), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_54_ ( .D(n3156), .CK(clk), .RN(n6304), .Q(
d_ff3_LUT_out[54]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n3134), .CK(clk), .RN(n6304), .Q(
d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n3121), .CK(clk), .RN(n6304), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(n3155), .CK(clk), .RN(n6304), .Q(
d_ff3_LUT_out[53]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n3117), .CK(clk), .RN(n6304), .Q(
d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n3114), .CK(clk), .RN(n6304), .Q(
d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n3130), .CK(clk), .RN(n6303), .Q(
d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n3118), .CK(clk), .RN(n6303), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(n3153), .CK(clk), .RN(n6303), .Q(
d_ff3_LUT_out[50]), .QN(n6129) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n3150), .CK(clk), .RN(n6303), .Q(
d_ff3_LUT_out[44]), .QN(n6136) );
DFFRXLTS reg_LUT_Q_reg_28_ ( .D(n3139), .CK(clk), .RN(n6303), .Q(
d_ff3_LUT_out[28]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n3128), .CK(clk), .RN(n6303), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n3125), .CK(clk), .RN(n6303), .Q(
d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n3131), .CK(clk), .RN(n6303), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(n3145), .CK(clk), .RN(n6303), .Q(
d_ff3_LUT_out[35]), .QN(n6131) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n3129), .CK(clk), .RN(n6303), .Q(
d_ff3_LUT_out[18]), .QN(n6134) );
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(n3151), .CK(clk), .RN(n6302), .Q(
d_ff3_LUT_out[45]), .QN(n6126) );
DFFRXLTS reg_LUT_Q_reg_55_ ( .D(n3157), .CK(clk), .RN(n6302), .Q(
d_ff3_LUT_out[55]), .QN(n6128) );
DFFRXLTS reg_LUT_Q_reg_39_ ( .D(n3147), .CK(clk), .RN(n6302), .Q(
d_ff3_LUT_out[39]) );
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(n3141), .CK(clk), .RN(n6302), .Q(
d_ff3_LUT_out[31]), .QN(n6132) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n3136), .CK(clk), .RN(n6302), .Q(
d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n3135), .CK(clk), .RN(n6302), .Q(
d_ff3_LUT_out[24]), .QN(n6133) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n3133), .CK(clk), .RN(n6302), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n3124), .CK(clk), .RN(n6302), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n3123), .CK(clk), .RN(n6302), .Q(
d_ff3_LUT_out[12]), .QN(n6135) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n3137), .CK(clk), .RN(n6302), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n3119), .CK(clk), .RN(n6301), .Q(
d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n3116), .CK(clk), .RN(n6301), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_34_ ( .D(n3144), .CK(clk), .RN(n6301), .Q(
d_ff3_LUT_out[34]), .QN(n6137) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n3127), .CK(clk), .RN(n6301), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n3113), .CK(clk), .RN(n6301), .Q(
d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n3138), .CK(clk), .RN(n6301), .Q(
d_ff3_LUT_out[27]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n3126), .CK(clk), .RN(n6301), .Q(
d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(n3122), .CK(clk), .RN(n6301), .Q(
d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n3120), .CK(clk), .RN(n6301), .Q(
d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_33_ ( .D(n3143), .CK(clk), .RN(n6301), .Q(
d_ff3_LUT_out[33]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n3112), .CK(clk), .RN(n6300), .Q(
d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n3111), .CK(clk), .RN(n6300), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(n2766), .CK(clk), .RN(n6300), .Q(
d_ff3_sh_x_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(n2765), .CK(clk), .RN(n6300), .Q(
d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(n2764), .CK(clk), .RN(n6300), .Q(
d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(n2763), .CK(clk), .RN(n6300), .Q(
d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(n2762), .CK(clk), .RN(n6300), .Q(
d_ff3_sh_x_out[56]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(n2761), .CK(clk), .RN(n6300), .Q(
d_ff3_sh_x_out[57]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(n2760), .CK(clk), .RN(n6300), .Q(
d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_59_ ( .D(n2759), .CK(clk), .RN(n6300), .Q(
d_ff3_sh_x_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(n2758), .CK(clk), .RN(n6299), .Q(
d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(n2757), .CK(clk), .RN(n6299), .Q(
d_ff3_sh_x_out[61]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(n2756), .CK(clk), .RN(n6299), .Q(
d_ff3_sh_x_out[62]) );
DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(n2583), .CK(clk), .RN(n6299), .Q(
d_ff3_sh_y_out[52]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(n2581), .CK(clk), .RN(n6299), .Q(
d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(n2579), .CK(clk), .RN(n6299), .Q(
d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(n2577), .CK(clk), .RN(n6299), .Q(
d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(n2575), .CK(clk), .RN(n6299), .Q(
d_ff3_sh_y_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(n2573), .CK(clk), .RN(n6299), .Q(
d_ff3_sh_y_out[57]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(n2571), .CK(clk), .RN(n6299), .Q(
d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(n2569), .CK(clk), .RN(n6298), .Q(
d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(n2567), .CK(clk), .RN(n6298), .Q(
d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(n2565), .CK(clk), .RN(n6298), .Q(
d_ff3_sh_y_out[61]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(n2563), .CK(clk), .RN(n6298), .Q(
d_ff3_sh_y_out[62]) );
DFFRXLTS reg_LUT_Q_reg_29_ ( .D(n3140), .CK(clk), .RN(n6298), .Q(
d_ff3_LUT_out[29]), .QN(n6127) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(n2505), .CK(clk), .RN(n6298), .Q(
d_ff_Zn[52]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n2370), .CK(clk), .RN(n6298),
.Q(d_ff2_Z[52]) );
DFFRXLTS d_ff4_Yn_Q_reg_52_ ( .D(n2504), .CK(clk), .RN(n6298), .Q(
d_ff_Yn[52]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_52_ ( .D(n2594), .CK(clk), .RN(n6298),
.Q(d_ff2_Y[52]), .QN(n5937) );
DFFRXLTS d_ff4_Xn_Q_reg_52_ ( .D(n2503), .CK(clk), .RN(n6298), .Q(
d_ff_Xn[52]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_52_ ( .D(n2777), .CK(clk), .RN(n6297),
.Q(d_ff2_X[52]), .QN(n5938) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(
n2369), .CK(clk), .RN(n6166), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .QN(n6014) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(n2502), .CK(clk), .RN(n6297), .Q(
d_ff_Zn[53]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n2368), .CK(clk), .RN(n6297),
.Q(d_ff2_Z[53]) );
DFFRXLTS d_ff4_Yn_Q_reg_53_ ( .D(n2501), .CK(clk), .RN(n6297), .Q(
d_ff_Yn[53]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_53_ ( .D(n2593), .CK(clk), .RN(n6297),
.Q(d_ff2_Y[53]) );
DFFRXLTS d_ff4_Xn_Q_reg_53_ ( .D(n2500), .CK(clk), .RN(n6297), .Q(
d_ff_Xn[53]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_53_ ( .D(n2776), .CK(clk), .RN(n6297),
.Q(d_ff2_X[53]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(
n2367), .CK(clk), .RN(n6166), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[53]), .QN(n6003) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n2499), .CK(clk), .RN(n6297), .Q(
d_ff_Zn[54]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n2366), .CK(clk), .RN(n6296),
.Q(d_ff2_Z[54]) );
DFFRXLTS d_ff4_Yn_Q_reg_54_ ( .D(n2498), .CK(clk), .RN(n6296), .Q(
d_ff_Yn[54]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_54_ ( .D(n2592), .CK(clk), .RN(n6296),
.Q(d_ff2_Y[54]) );
DFFRXLTS d_ff4_Xn_Q_reg_54_ ( .D(n2497), .CK(clk), .RN(n6296), .Q(
d_ff_Xn[54]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_54_ ( .D(n2775), .CK(clk), .RN(n6296),
.Q(d_ff2_X[54]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(
n2365), .CK(clk), .RN(n6166), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[54]), .QN(n5917) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(n2496), .CK(clk), .RN(n6296), .Q(
d_ff_Zn[55]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n2364), .CK(clk), .RN(n6296),
.Q(d_ff2_Z[55]) );
DFFRXLTS d_ff4_Yn_Q_reg_55_ ( .D(n2495), .CK(clk), .RN(n6296), .Q(
d_ff_Yn[55]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_55_ ( .D(n2591), .CK(clk), .RN(n6296),
.Q(d_ff2_Y[55]) );
DFFRXLTS d_ff4_Xn_Q_reg_55_ ( .D(n2494), .CK(clk), .RN(n6295), .Q(
d_ff_Xn[55]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_55_ ( .D(n2774), .CK(clk), .RN(n6295),
.Q(d_ff2_X[55]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(
n2363), .CK(clk), .RN(n6167), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[55]), .QN(n6011) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(n2493), .CK(clk), .RN(n6295), .Q(
d_ff_Zn[56]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n2362), .CK(clk), .RN(n6295),
.Q(d_ff2_Z[56]) );
DFFRXLTS d_ff4_Yn_Q_reg_56_ ( .D(n2492), .CK(clk), .RN(n6295), .Q(
d_ff_Yn[56]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_56_ ( .D(n2590), .CK(clk), .RN(n6295),
.Q(d_ff2_Y[56]) );
DFFRXLTS d_ff4_Xn_Q_reg_56_ ( .D(n2491), .CK(clk), .RN(n6295), .Q(
d_ff_Xn[56]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_56_ ( .D(n2773), .CK(clk), .RN(n6295),
.Q(d_ff2_X[56]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(
n2361), .CK(clk), .RN(n6167), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[56]), .QN(n5914) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(n2490), .CK(clk), .RN(n6294), .Q(
d_ff_Zn[57]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n2360), .CK(clk), .RN(n6294),
.Q(d_ff2_Z[57]) );
DFFRXLTS d_ff4_Yn_Q_reg_57_ ( .D(n2489), .CK(clk), .RN(n6294), .Q(
d_ff_Yn[57]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_57_ ( .D(n2589), .CK(clk), .RN(n6294),
.Q(d_ff2_Y[57]) );
DFFRXLTS d_ff4_Xn_Q_reg_57_ ( .D(n2488), .CK(clk), .RN(n6294), .Q(
d_ff_Xn[57]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_57_ ( .D(n2772), .CK(clk), .RN(n6294),
.Q(d_ff2_X[57]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(
n2359), .CK(clk), .RN(n6167), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .QN(n5935) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(n2487), .CK(clk), .RN(n6294), .Q(
d_ff_Zn[58]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n2358), .CK(clk), .RN(n6294),
.Q(d_ff2_Z[58]) );
DFFRXLTS d_ff4_Yn_Q_reg_58_ ( .D(n2486), .CK(clk), .RN(n6294), .Q(
d_ff_Yn[58]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_58_ ( .D(n2588), .CK(clk), .RN(n6293),
.Q(d_ff2_Y[58]), .QN(n6026) );
DFFRXLTS d_ff4_Xn_Q_reg_58_ ( .D(n2485), .CK(clk), .RN(n6293), .Q(
d_ff_Xn[58]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_58_ ( .D(n2771), .CK(clk), .RN(n6293),
.Q(d_ff2_X[58]), .QN(n6018) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(
n2357), .CK(clk), .RN(n6167), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[58]), .QN(n5905) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(n2484), .CK(clk), .RN(n6293), .Q(
d_ff_Zn[59]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n2356), .CK(clk), .RN(n6293),
.Q(d_ff2_Z[59]) );
DFFRXLTS d_ff4_Yn_Q_reg_59_ ( .D(n2483), .CK(clk), .RN(n6293), .Q(
d_ff_Yn[59]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_59_ ( .D(n2587), .CK(clk), .RN(n6293),
.Q(d_ff2_Y[59]) );
DFFRXLTS d_ff4_Xn_Q_reg_59_ ( .D(n2482), .CK(clk), .RN(n6293), .Q(
d_ff_Xn[59]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_59_ ( .D(n2770), .CK(clk), .RN(n6293),
.Q(d_ff2_X[59]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(
n2355), .CK(clk), .RN(n6167), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .QN(n5949) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(n2481), .CK(clk), .RN(n6292), .Q(
d_ff_Zn[60]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n2354), .CK(clk), .RN(n6292),
.Q(d_ff2_Z[60]) );
DFFRXLTS d_ff4_Yn_Q_reg_60_ ( .D(n2480), .CK(clk), .RN(n6292), .Q(
d_ff_Yn[60]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_60_ ( .D(n2586), .CK(clk), .RN(n6292),
.Q(d_ff2_Y[60]), .QN(n6027) );
DFFRXLTS d_ff4_Xn_Q_reg_60_ ( .D(n2479), .CK(clk), .RN(n6292), .Q(
d_ff_Xn[60]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_60_ ( .D(n2769), .CK(clk), .RN(n6292),
.Q(d_ff2_X[60]), .QN(n6019) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(
n2353), .CK(clk), .RN(n6167), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[60]), .QN(n5931) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(n2478), .CK(clk), .RN(n6292), .Q(
d_ff_Zn[61]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n2352), .CK(clk), .RN(n6292),
.Q(d_ff2_Z[61]) );
DFFRXLTS d_ff4_Yn_Q_reg_61_ ( .D(n2477), .CK(clk), .RN(n6291), .Q(
d_ff_Yn[61]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_61_ ( .D(n2585), .CK(clk), .RN(n6291),
.Q(d_ff2_Y[61]) );
DFFRXLTS d_ff4_Xn_Q_reg_61_ ( .D(n2476), .CK(clk), .RN(n6291), .Q(
d_ff_Xn[61]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_61_ ( .D(n2768), .CK(clk), .RN(n6291),
.Q(d_ff2_X[61]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(
n2351), .CK(clk), .RN(n6167), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(n2475), .CK(clk), .RN(n6291), .Q(
d_ff_Zn[62]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n2350), .CK(clk), .RN(n6291),
.Q(d_ff2_Z[62]) );
DFFRXLTS d_ff4_Yn_Q_reg_62_ ( .D(n2346), .CK(clk), .RN(n6291), .Q(
d_ff_Yn[62]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_62_ ( .D(n2584), .CK(clk), .RN(n6291),
.Q(d_ff2_Y[62]) );
DFFRXLTS d_ff4_Xn_Q_reg_62_ ( .D(n2345), .CK(clk), .RN(n6291), .Q(
d_ff_Xn[62]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_62_ ( .D(n2767), .CK(clk), .RN(n6290),
.Q(d_ff2_X[62]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(
n2561), .CK(clk), .RN(n6167), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(
n2582), .CK(clk), .RN(n6167), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .QN(n5942) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(
n2580), .CK(clk), .RN(n6167), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(
n2578), .CK(clk), .RN(n6168), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(
n2576), .CK(clk), .RN(n6168), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(
n2574), .CK(clk), .RN(n6168), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(
n2572), .CK(clk), .RN(n6168), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[57]), .QN(n5962) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(
n2570), .CK(clk), .RN(n6168), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[58]), .QN(n5989) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(
n2568), .CK(clk), .RN(n6168), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[59]), .QN(n5990) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(
n2566), .CK(clk), .RN(n6168), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[60]), .QN(n5988) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(
n2564), .CK(clk), .RN(n6168), .QN(n5985) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(
n2562), .CK(clk), .RN(n6168), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[62]), .QN(n5995) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n2507),
.CK(clk), .RN(n6168), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(n2884), .CK(clk), .RN(n6290), .Q(
d_ff_Zn[51]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n2372), .CK(clk), .RN(n6290),
.Q(d_ff2_Z[51]) );
DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(n2883), .CK(clk), .RN(n6290), .Q(
d_ff_Yn[51]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_51_ ( .D(n2597), .CK(clk), .RN(n6290),
.Q(d_ff2_Y[51]) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n2596), .CK(clk), .RN(n6290), .Q(
d_ff3_sh_y_out[51]) );
DFFRXLTS d_ff4_Xn_Q_reg_51_ ( .D(n2882), .CK(clk), .RN(n6290), .Q(
d_ff_Xn[51]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_51_ ( .D(n2779), .CK(clk), .RN(n6290),
.Q(d_ff2_X[51]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n2778), .CK(clk), .RN(n6290), .Q(
d_ff3_sh_x_out[51]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(
n2595), .CK(clk), .RN(n6169), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .QN(n6085) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(
n2371), .CK(clk), .RN(n6169), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[51]), .QN(n5998) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n2556),
.CK(clk), .RN(n6169), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n2887), .CK(clk), .RN(n6323), .Q(
d_ff_Zn[50]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n2374), .CK(clk), .RN(n6322),
.Q(d_ff2_Z[50]) );
DFFRXLTS d_ff4_Yn_Q_reg_50_ ( .D(n2886), .CK(clk), .RN(n6317), .Q(
d_ff_Yn[50]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_50_ ( .D(n2600), .CK(clk), .RN(n6314),
.Q(d_ff2_Y[50]) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(n2599), .CK(clk), .RN(n6323), .Q(
d_ff3_sh_y_out[50]) );
DFFRXLTS d_ff4_Xn_Q_reg_50_ ( .D(n2885), .CK(clk), .RN(n6322), .Q(
d_ff_Xn[50]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_50_ ( .D(n2781), .CK(clk), .RN(n6317),
.Q(d_ff2_X[50]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(n2780), .CK(clk), .RN(n6323), .Q(
d_ff3_sh_x_out[50]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(
n2598), .CK(clk), .RN(n6169), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(
n2373), .CK(clk), .RN(n6169), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[50]), .QN(n5908) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n2555),
.CK(clk), .RN(n6169), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n2896), .CK(clk), .RN(n6321), .Q(
d_ff_Zn[47]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n2380), .CK(clk), .RN(n6321),
.Q(d_ff2_Z[47]) );
DFFRXLTS d_ff4_Yn_Q_reg_47_ ( .D(n2895), .CK(clk), .RN(n6289), .Q(
d_ff_Yn[47]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_47_ ( .D(n2609), .CK(clk), .RN(n6289),
.Q(d_ff2_Y[47]) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(n2608), .CK(clk), .RN(n6289), .Q(
d_ff3_sh_y_out[47]) );
DFFRXLTS d_ff4_Xn_Q_reg_47_ ( .D(n2894), .CK(clk), .RN(n6289), .Q(
d_ff_Xn[47]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_47_ ( .D(n2787), .CK(clk), .RN(n6289),
.Q(d_ff2_X[47]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n2786), .CK(clk), .RN(n6289), .Q(
d_ff3_sh_x_out[47]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(
n2607), .CK(clk), .RN(n6169), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .QN(n6091) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(
n2379), .CK(clk), .RN(n6169), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[47]), .QN(n6006) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n2509),
.CK(clk), .RN(n6169), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(n2890), .CK(clk), .RN(n6289), .Q(
d_ff_Zn[49]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n2376), .CK(clk), .RN(n6289),
.Q(d_ff2_Z[49]) );
DFFRXLTS d_ff4_Yn_Q_reg_49_ ( .D(n2889), .CK(clk), .RN(n6289), .Q(
d_ff_Yn[49]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_49_ ( .D(n2603), .CK(clk), .RN(n6289),
.Q(d_ff2_Y[49]) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(n2602), .CK(clk), .RN(n6288), .Q(
d_ff3_sh_y_out[49]) );
DFFRXLTS d_ff4_Xn_Q_reg_49_ ( .D(n2888), .CK(clk), .RN(n6288), .Q(
d_ff_Xn[49]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_49_ ( .D(n2783), .CK(clk), .RN(n6288),
.Q(d_ff2_X[49]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(n2782), .CK(clk), .RN(n6288), .Q(
d_ff3_sh_x_out[49]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(
n2601), .CK(clk), .RN(n6169), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]), .QN(n6084) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(
n2375), .CK(clk), .RN(n6170), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[49]), .QN(n6009) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n2554),
.CK(clk), .RN(n6170), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(n2893), .CK(clk), .RN(n6288), .Q(
d_ff_Zn[48]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n2378), .CK(clk), .RN(n6288),
.Q(d_ff2_Z[48]) );
DFFRXLTS d_ff4_Yn_Q_reg_48_ ( .D(n2892), .CK(clk), .RN(n6288), .Q(
d_ff_Yn[48]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_48_ ( .D(n2606), .CK(clk), .RN(n6288),
.Q(d_ff2_Y[48]) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n2605), .CK(clk), .RN(n6288), .Q(
d_ff3_sh_y_out[48]) );
DFFRXLTS d_ff4_Xn_Q_reg_48_ ( .D(n2891), .CK(clk), .RN(n6288), .Q(
d_ff_Xn[48]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_48_ ( .D(n2785), .CK(clk), .RN(n6287),
.Q(d_ff2_X[48]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n2784), .CK(clk), .RN(n6287), .Q(
d_ff3_sh_x_out[48]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(
n2604), .CK(clk), .RN(n6170), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[48]), .QN(n6081) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(
n2377), .CK(clk), .RN(n6170), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[48]), .QN(n5996) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n2553),
.CK(clk), .RN(n6170), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(n2938), .CK(clk), .RN(n6287), .Q(
d_ff_Zn[33]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n2408), .CK(clk), .RN(n6287),
.Q(d_ff2_Z[33]) );
DFFRXLTS d_ff4_Yn_Q_reg_33_ ( .D(n2937), .CK(clk), .RN(n6287), .Q(
d_ff_Yn[33]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_33_ ( .D(n2651), .CK(clk), .RN(n6287),
.Q(d_ff2_Y[33]) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(n2650), .CK(clk), .RN(n6287), .Q(
d_ff3_sh_y_out[33]) );
DFFRXLTS d_ff4_Xn_Q_reg_33_ ( .D(n2936), .CK(clk), .RN(n6287), .Q(
d_ff_Xn[33]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_33_ ( .D(n2815), .CK(clk), .RN(n6287),
.Q(d_ff2_X[33]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n2814), .CK(clk), .RN(n6287), .Q(
d_ff3_sh_x_out[33]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(
n2649), .CK(clk), .RN(n6170), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(
n2407), .CK(clk), .RN(n6170), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[33]), .QN(n5970) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n2522),
.CK(clk), .RN(n6170), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n2905), .CK(clk), .RN(n6286), .Q(
d_ff_Zn[44]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n2386), .CK(clk), .RN(n6286),
.Q(d_ff2_Z[44]) );
DFFRXLTS d_ff4_Yn_Q_reg_44_ ( .D(n2904), .CK(clk), .RN(n6286), .Q(
d_ff_Yn[44]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_44_ ( .D(n2618), .CK(clk), .RN(n6286),
.Q(d_ff2_Y[44]) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(n2617), .CK(clk), .RN(n6286), .Q(
d_ff3_sh_y_out[44]) );
DFFRXLTS d_ff4_Xn_Q_reg_44_ ( .D(n2903), .CK(clk), .RN(n6286), .Q(
d_ff_Xn[44]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_44_ ( .D(n2793), .CK(clk), .RN(n6286),
.Q(d_ff2_X[44]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n2792), .CK(clk), .RN(n6286), .Q(
d_ff3_sh_x_out[44]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(
n2616), .CK(clk), .RN(n6170), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[44]), .QN(n6080) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(
n2385), .CK(clk), .RN(n6170), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[44]), .QN(n5997) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n2511),
.CK(clk), .RN(n6171), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n3028), .CK(clk), .RN(n6286), .Q(d_ff_Zn[3])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n2468), .CK(clk), .RN(n6286), .Q(
d_ff2_Z[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n3027), .CK(clk), .RN(n6285), .Q(d_ff_Yn[3])
);
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(n2741), .CK(clk), .RN(n6285), .Q(
d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n2740), .CK(clk), .RN(n6285), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(n3026), .CK(clk), .RN(n6285), .Q(d_ff_Xn[3])
);
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(n2875), .CK(clk), .RN(n6285), .Q(
d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n2874), .CK(clk), .RN(n6285), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(
n2739), .CK(clk), .RN(n6171), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(
n2467), .CK(clk), .RN(n6171), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .QN(n5983) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n2552),
.CK(clk), .RN(n6171), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(n2935), .CK(clk), .RN(n6285), .Q(
d_ff_Zn[34]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n2406), .CK(clk), .RN(n6285),
.Q(d_ff2_Z[34]) );
DFFRXLTS d_ff4_Yn_Q_reg_34_ ( .D(n2934), .CK(clk), .RN(n6285), .Q(
d_ff_Yn[34]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_34_ ( .D(n2648), .CK(clk), .RN(n6285),
.Q(d_ff2_Y[34]) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(n2647), .CK(clk), .RN(n6284), .Q(
d_ff3_sh_y_out[34]) );
DFFRXLTS d_ff4_Xn_Q_reg_34_ ( .D(n2933), .CK(clk), .RN(n6284), .Q(
d_ff_Xn[34]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_34_ ( .D(n2813), .CK(clk), .RN(n6284),
.Q(d_ff2_X[34]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n2812), .CK(clk), .RN(n6284), .Q(
d_ff3_sh_x_out[34]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(
n2646), .CK(clk), .RN(n6171), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]), .QN(n6087) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(
n2405), .CK(clk), .RN(n6171), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[34]), .QN(n6005) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n2521),
.CK(clk), .RN(n6171), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n2902), .CK(clk), .RN(n6284), .Q(
d_ff_Zn[45]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n2384), .CK(clk), .RN(n6284),
.Q(d_ff2_Z[45]) );
DFFRXLTS d_ff4_Yn_Q_reg_45_ ( .D(n2901), .CK(clk), .RN(n6284), .Q(
d_ff_Yn[45]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_45_ ( .D(n2615), .CK(clk), .RN(n6284),
.Q(d_ff2_Y[45]) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(n2614), .CK(clk), .RN(n6284), .Q(
d_ff3_sh_y_out[45]) );
DFFRXLTS d_ff4_Xn_Q_reg_45_ ( .D(n2900), .CK(clk), .RN(n6284), .Q(
d_ff_Xn[45]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_45_ ( .D(n2791), .CK(clk), .RN(n6283),
.Q(d_ff2_X[45]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n2790), .CK(clk), .RN(n6283), .Q(
d_ff3_sh_x_out[45]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(
n2613), .CK(clk), .RN(n6171), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(
n2383), .CK(clk), .RN(n6171), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[45]), .QN(n5993) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n2512),
.CK(clk), .RN(n6171), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n2899), .CK(clk), .RN(n6283), .Q(
d_ff_Zn[46]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n2382), .CK(clk), .RN(n6283),
.Q(d_ff2_Z[46]) );
DFFRXLTS d_ff4_Yn_Q_reg_46_ ( .D(n2898), .CK(clk), .RN(n6283), .Q(
d_ff_Yn[46]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_46_ ( .D(n2612), .CK(clk), .RN(n6283),
.Q(d_ff2_Y[46]) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n2611), .CK(clk), .RN(n6283), .Q(
d_ff3_sh_y_out[46]) );
DFFRXLTS d_ff4_Xn_Q_reg_46_ ( .D(n2897), .CK(clk), .RN(n6283), .Q(
d_ff_Xn[46]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_46_ ( .D(n2789), .CK(clk), .RN(n6283),
.Q(d_ff2_X[46]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n2788), .CK(clk), .RN(n6283), .Q(
d_ff3_sh_x_out[46]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(
n2610), .CK(clk), .RN(n6172), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .QN(n6016) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(
n2381), .CK(clk), .RN(n6172), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[46]), .QN(n6000) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(n2932), .CK(clk), .RN(n6282), .Q(
d_ff_Zn[35]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n2404), .CK(clk), .RN(n6282),
.Q(d_ff2_Z[35]) );
DFFRXLTS d_ff4_Yn_Q_reg_35_ ( .D(n2931), .CK(clk), .RN(n6282), .Q(
d_ff_Yn[35]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_35_ ( .D(n2645), .CK(clk), .RN(n6282),
.Q(d_ff2_Y[35]) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(n2644), .CK(clk), .RN(n6282), .Q(
d_ff3_sh_y_out[35]) );
DFFRXLTS d_ff4_Xn_Q_reg_35_ ( .D(n2930), .CK(clk), .RN(n6282), .Q(
d_ff_Xn[35]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_35_ ( .D(n2811), .CK(clk), .RN(n6282),
.Q(d_ff2_X[35]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(n2810), .CK(clk), .RN(n6282), .Q(
d_ff3_sh_x_out[35]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(
n2643), .CK(clk), .RN(n6172), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(
n2403), .CK(clk), .RN(n6172), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[35]), .QN(n5910) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n2520),
.CK(clk), .RN(n6172), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(n2911), .CK(clk), .RN(n6282), .Q(
d_ff_Zn[42]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n2390), .CK(clk), .RN(n6282),
.Q(d_ff2_Z[42]) );
DFFRXLTS d_ff4_Yn_Q_reg_42_ ( .D(n2910), .CK(clk), .RN(n6281), .Q(
d_ff_Yn[42]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_42_ ( .D(n2624), .CK(clk), .RN(n6281),
.Q(d_ff2_Y[42]) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(n2623), .CK(clk), .RN(n6281), .Q(
d_ff3_sh_y_out[42]) );
DFFRXLTS d_ff4_Xn_Q_reg_42_ ( .D(n2909), .CK(clk), .RN(n6281), .Q(
d_ff_Xn[42]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_42_ ( .D(n2797), .CK(clk), .RN(n6281),
.Q(d_ff2_X[42]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(n2796), .CK(clk), .RN(n6281), .Q(
d_ff3_sh_x_out[42]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(
n2622), .CK(clk), .RN(n6172), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]), .QN(n6088) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(
n2389), .CK(clk), .RN(n6172), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[42]), .QN(n5918) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n2515),
.CK(clk), .RN(n6172), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n2908), .CK(clk), .RN(n6281), .Q(
d_ff_Zn[43]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n2388), .CK(clk), .RN(n6281),
.Q(d_ff2_Z[43]) );
DFFRXLTS d_ff4_Yn_Q_reg_43_ ( .D(n2907), .CK(clk), .RN(n6281), .Q(
d_ff_Yn[43]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_43_ ( .D(n2621), .CK(clk), .RN(n6281),
.Q(d_ff2_Y[43]) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(n2620), .CK(clk), .RN(n6280), .Q(
d_ff3_sh_y_out[43]) );
DFFRXLTS d_ff4_Xn_Q_reg_43_ ( .D(n2906), .CK(clk), .RN(n6280), .Q(
d_ff_Xn[43]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_43_ ( .D(n2795), .CK(clk), .RN(n6280),
.Q(d_ff2_X[43]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(n2794), .CK(clk), .RN(n6280), .Q(
d_ff3_sh_x_out[43]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(
n2619), .CK(clk), .RN(n6172), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .QN(n6083) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(
n2387), .CK(clk), .RN(n6173), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[43]), .QN(n6010) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n2548),
.CK(clk), .RN(n6173), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(n2929), .CK(clk), .RN(n6280), .Q(
d_ff_Zn[36]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n2402), .CK(clk), .RN(n6280),
.Q(d_ff2_Z[36]) );
DFFRXLTS d_ff4_Yn_Q_reg_36_ ( .D(n2928), .CK(clk), .RN(n6280), .Q(
d_ff_Yn[36]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_36_ ( .D(n2642), .CK(clk), .RN(n6280),
.Q(d_ff2_Y[36]) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(n2641), .CK(clk), .RN(n6280), .Q(
d_ff3_sh_y_out[36]) );
DFFRXLTS d_ff4_Xn_Q_reg_36_ ( .D(n2927), .CK(clk), .RN(n6280), .Q(
d_ff_Xn[36]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_36_ ( .D(n2809), .CK(clk), .RN(n6279),
.Q(d_ff2_X[36]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n2808), .CK(clk), .RN(n6279), .Q(
d_ff3_sh_x_out[36]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(
n2640), .CK(clk), .RN(n6173), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .QN(n6017) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(
n2401), .CK(clk), .RN(n6173), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[36]), .QN(n6001) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n2519),
.CK(clk), .RN(n6173), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(n2920), .CK(clk), .RN(n6279), .Q(
d_ff_Zn[39]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n2396), .CK(clk), .RN(n6279),
.Q(d_ff2_Z[39]) );
DFFRXLTS d_ff4_Yn_Q_reg_39_ ( .D(n2919), .CK(clk), .RN(n6279), .Q(
d_ff_Yn[39]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_39_ ( .D(n2633), .CK(clk), .RN(n6279),
.Q(d_ff2_Y[39]) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(n2632), .CK(clk), .RN(n6279), .Q(
d_ff3_sh_y_out[39]) );
DFFRXLTS d_ff4_Xn_Q_reg_39_ ( .D(n2918), .CK(clk), .RN(n6279), .Q(
d_ff_Xn[39]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_39_ ( .D(n2803), .CK(clk), .RN(n6279),
.Q(d_ff2_X[39]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n2802), .CK(clk), .RN(n6279), .Q(
d_ff3_sh_x_out[39]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(
n2631), .CK(clk), .RN(n6173), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(
n2395), .CK(clk), .RN(n6173), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[39]), .QN(n5976) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n2517),
.CK(clk), .RN(n6173), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n2914), .CK(clk), .RN(n6278), .Q(
d_ff_Zn[41]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n2392), .CK(clk), .RN(n6278),
.Q(d_ff2_Z[41]) );
DFFRXLTS d_ff4_Yn_Q_reg_41_ ( .D(n2913), .CK(clk), .RN(n6278), .Q(
d_ff_Yn[41]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_41_ ( .D(n2627), .CK(clk), .RN(n6278),
.Q(d_ff2_Y[41]) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(n2626), .CK(clk), .RN(n6278), .Q(
d_ff3_sh_y_out[41]) );
DFFRXLTS d_ff4_Xn_Q_reg_41_ ( .D(n2912), .CK(clk), .RN(n6278), .Q(
d_ff_Xn[41]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_41_ ( .D(n2799), .CK(clk), .RN(n6278),
.Q(d_ff2_X[41]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n2798), .CK(clk), .RN(n6278), .Q(
d_ff3_sh_x_out[41]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(
n2625), .CK(clk), .RN(n6173), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(
n2391), .CK(clk), .RN(n6173), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[41]), .QN(n5966) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n2546),
.CK(clk), .RN(n6174), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(n2923), .CK(clk), .RN(n6278), .Q(
d_ff_Zn[38]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n2398), .CK(clk), .RN(n6278),
.Q(d_ff2_Z[38]) );
DFFRXLTS d_ff4_Yn_Q_reg_38_ ( .D(n2922), .CK(clk), .RN(n6277), .Q(
d_ff_Yn[38]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_38_ ( .D(n2636), .CK(clk), .RN(n6277),
.Q(d_ff2_Y[38]) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(n2635), .CK(clk), .RN(n6277), .Q(
d_ff3_sh_y_out[38]) );
DFFRXLTS d_ff4_Xn_Q_reg_38_ ( .D(n2921), .CK(clk), .RN(n6277), .Q(
d_ff_Xn[38]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_38_ ( .D(n2805), .CK(clk), .RN(n6277),
.Q(d_ff2_X[38]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n2804), .CK(clk), .RN(n6277), .Q(
d_ff3_sh_x_out[38]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(
n2634), .CK(clk), .RN(n6174), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[38]), .QN(n6092) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(
n2397), .CK(clk), .RN(n6174), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[38]), .QN(n6002) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n2518),
.CK(clk), .RN(n6174), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n2917), .CK(clk), .RN(n6277), .Q(
d_ff_Zn[40]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n2394), .CK(clk), .RN(n6277),
.Q(d_ff2_Z[40]) );
DFFRXLTS d_ff4_Yn_Q_reg_40_ ( .D(n2916), .CK(clk), .RN(n6277), .Q(
d_ff_Yn[40]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_40_ ( .D(n2630), .CK(clk), .RN(n6277),
.Q(d_ff2_Y[40]) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(n2629), .CK(clk), .RN(n6276), .Q(
d_ff3_sh_y_out[40]) );
DFFRXLTS d_ff4_Xn_Q_reg_40_ ( .D(n2915), .CK(clk), .RN(n6276), .Q(
d_ff_Xn[40]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_40_ ( .D(n2801), .CK(clk), .RN(n6276),
.Q(d_ff2_X[40]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n2800), .CK(clk), .RN(n6276), .Q(
d_ff3_sh_x_out[40]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(
n2628), .CK(clk), .RN(n6174), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .QN(n6090) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(
n2393), .CK(clk), .RN(n6174), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[40]), .QN(n6007) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n2545),
.CK(clk), .RN(n6174), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(n2926), .CK(clk), .RN(n6276), .Q(
d_ff_Zn[37]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n2400), .CK(clk), .RN(n6276),
.Q(d_ff2_Z[37]) );
DFFRXLTS d_ff4_Yn_Q_reg_37_ ( .D(n2925), .CK(clk), .RN(n6276), .Q(
d_ff_Yn[37]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_37_ ( .D(n2639), .CK(clk), .RN(n6276),
.Q(d_ff2_Y[37]) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(n2638), .CK(clk), .RN(n6276), .Q(
d_ff3_sh_y_out[37]) );
DFFRXLTS d_ff4_Xn_Q_reg_37_ ( .D(n2924), .CK(clk), .RN(n6276), .Q(
d_ff_Xn[37]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_37_ ( .D(n2807), .CK(clk), .RN(n6275),
.Q(d_ff2_X[37]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n2806), .CK(clk), .RN(n6275), .Q(
d_ff3_sh_x_out[37]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(
n2637), .CK(clk), .RN(n6174), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .QN(n5933) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(
n2399), .CK(clk), .RN(n6174), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[37]), .QN(n5965) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n2542),
.CK(clk), .RN(n6174), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n2953), .CK(clk), .RN(n6275), .Q(
d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n2418), .CK(clk), .RN(n6275),
.Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n2952), .CK(clk), .RN(n6275), .Q(
d_ff_Yn[28]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(n2666), .CK(clk), .RN(n6275),
.Q(d_ff2_Y[28]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n2665), .CK(clk), .RN(n6275), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(n2951), .CK(clk), .RN(n6275), .Q(
d_ff_Xn[28]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(n2825), .CK(clk), .RN(n6275),
.Q(d_ff2_X[28]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n2824), .CK(clk), .RN(n6275), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(
n2664), .CK(clk), .RN(n6175), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .QN(n6082) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(
n2417), .CK(clk), .RN(n6175), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .QN(n6004) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n2527),
.CK(clk), .RN(n6175), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n2944), .CK(clk), .RN(n6274), .Q(
d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n2412), .CK(clk), .RN(n6274),
.Q(d_ff2_Z[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n2943), .CK(clk), .RN(n6274), .Q(
d_ff_Yn[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(n2657), .CK(clk), .RN(n6274),
.Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n2656), .CK(clk), .RN(n6274), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(n2942), .CK(clk), .RN(n6274), .Q(
d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(n2819), .CK(clk), .RN(n6274),
.Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n2818), .CK(clk), .RN(n6274), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(
n2655), .CK(clk), .RN(n6175), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(
n2411), .CK(clk), .RN(n6175), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .QN(n5916) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n2524),
.CK(clk), .RN(n6175), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n3001), .CK(clk), .RN(n6274), .Q(
d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n2450), .CK(clk), .RN(n6274),
.Q(d_ff2_Z[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n3000), .CK(clk), .RN(n6273), .Q(
d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(n2714), .CK(clk), .RN(n6273),
.Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n2713), .CK(clk), .RN(n6273), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(n2999), .CK(clk), .RN(n6273), .Q(
d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(n2857), .CK(clk), .RN(n6273),
.Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n2856), .CK(clk), .RN(n6273), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(
n2712), .CK(clk), .RN(n6175), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(
n2449), .CK(clk), .RN(n6175), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .QN(n5975) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n2543),
.CK(clk), .RN(n6175), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n2992), .CK(clk), .RN(n6273), .Q(
d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n2444), .CK(clk), .RN(n6273),
.Q(d_ff2_Z[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n2991), .CK(clk), .RN(n6273), .Q(
d_ff_Yn[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(n2705), .CK(clk), .RN(n6273),
.Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n2704), .CK(clk), .RN(n6272), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(n2990), .CK(clk), .RN(n6272), .Q(
d_ff_Xn[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(n2851), .CK(clk), .RN(n6272),
.Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n2850), .CK(clk), .RN(n6272), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(
n2703), .CK(clk), .RN(n6175), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(
n2443), .CK(clk), .RN(n6176), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .QN(n5994) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n2540),
.CK(clk), .RN(n6176), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n2947), .CK(clk), .RN(n6272), .Q(
d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n2414), .CK(clk), .RN(n6272),
.Q(d_ff2_Z[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n2946), .CK(clk), .RN(n6272), .Q(
d_ff_Yn[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(n2660), .CK(clk), .RN(n6272),
.Q(d_ff2_Y[30]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n2659), .CK(clk), .RN(n6272), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(n2945), .CK(clk), .RN(n6272), .Q(
d_ff_Xn[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(n2821), .CK(clk), .RN(n6271),
.Q(d_ff2_X[30]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n2820), .CK(clk), .RN(n6271), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(
n2658), .CK(clk), .RN(n6176), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .QN(n6089) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(
n2413), .CK(clk), .RN(n6176), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .QN(n6008) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n2525),
.CK(clk), .RN(n6176), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n2986), .CK(clk), .RN(n6271), .Q(
d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n2440), .CK(clk), .RN(n6271),
.Q(d_ff2_Z[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n2985), .CK(clk), .RN(n6271), .Q(
d_ff_Yn[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(n2699), .CK(clk), .RN(n6271),
.Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n2698), .CK(clk), .RN(n6271), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(n2984), .CK(clk), .RN(n6271), .Q(
d_ff_Xn[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(n2847), .CK(clk), .RN(n6271),
.Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n2846), .CK(clk), .RN(n6271), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(
n2697), .CK(clk), .RN(n6176), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(
n2439), .CK(clk), .RN(n6176), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .QN(n5982) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n2538),
.CK(clk), .RN(n6176), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(n2941), .CK(clk), .RN(n6270), .Q(
d_ff_Zn[32]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n2410), .CK(clk), .RN(n6270),
.Q(d_ff2_Z[32]) );
DFFRXLTS d_ff4_Yn_Q_reg_32_ ( .D(n2940), .CK(clk), .RN(n6270), .Q(
d_ff_Yn[32]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_32_ ( .D(n2654), .CK(clk), .RN(n6270),
.Q(d_ff2_Y[32]) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(n2653), .CK(clk), .RN(n6270), .Q(
d_ff3_sh_y_out[32]) );
DFFRXLTS d_ff4_Xn_Q_reg_32_ ( .D(n2939), .CK(clk), .RN(n6270), .Q(
d_ff_Xn[32]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_32_ ( .D(n2817), .CK(clk), .RN(n6270),
.Q(d_ff2_X[32]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(n2816), .CK(clk), .RN(n6270), .Q(
d_ff3_sh_x_out[32]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(
n2652), .CK(clk), .RN(n6176), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .QN(n6086) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(
n2409), .CK(clk), .RN(n6176), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[32]), .QN(n5999) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n2526),
.CK(clk), .RN(n6177), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n2995), .CK(clk), .RN(n6270), .Q(
d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n2446), .CK(clk), .RN(n6270),
.Q(d_ff2_Z[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n2994), .CK(clk), .RN(n6269), .Q(
d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(n2708), .CK(clk), .RN(n6269),
.Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n2707), .CK(clk), .RN(n6269), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(n2993), .CK(clk), .RN(n6269), .Q(
d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(n2853), .CK(clk), .RN(n6269),
.Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n2852), .CK(clk), .RN(n6269), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(
n2706), .CK(clk), .RN(n6177), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(
n2445), .CK(clk), .RN(n6177), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .QN(n5915) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n2541),
.CK(clk), .RN(n6177), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n2950), .CK(clk), .RN(n6269), .Q(
d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n2416), .CK(clk), .RN(n6269),
.Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n2949), .CK(clk), .RN(n6269), .Q(
d_ff_Yn[29]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_29_ ( .D(n2663), .CK(clk), .RN(n6269),
.Q(d_ff2_Y[29]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n2662), .CK(clk), .RN(n6268), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(n2948), .CK(clk), .RN(n6268), .Q(
d_ff_Xn[29]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_29_ ( .D(n2823), .CK(clk), .RN(n6268),
.Q(d_ff2_X[29]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n2822), .CK(clk), .RN(n6268), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(
n2661), .CK(clk), .RN(n6177), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(
n2415), .CK(clk), .RN(n6177), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .QN(n5971) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n2529),
.CK(clk), .RN(n6177), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n2998), .CK(clk), .RN(n6268), .Q(
d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n2448), .CK(clk), .RN(n6268),
.Q(d_ff2_Z[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n2997), .CK(clk), .RN(n6268), .Q(
d_ff_Yn[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(n2711), .CK(clk), .RN(n6268),
.Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n2710), .CK(clk), .RN(n6268), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(n2996), .CK(clk), .RN(n6268), .Q(
d_ff_Xn[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(n2855), .CK(clk), .RN(n6267),
.Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n2854), .CK(clk), .RN(n6267), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(
n2709), .CK(clk), .RN(n6177), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(
n2447), .CK(clk), .RN(n6177), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .QN(n5986) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n2752), .CK(clk), .RN(n6267), .Q(
d_ff_Zn[63]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n2349), .CK(clk), .RN(n6267),
.Q(d_ff2_Z[63]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(n2348), .CK(clk), .RN(n6267), .Q(
d_ff3_sign_out) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n2347),
.CK(clk), .RN(n6177), .Q(inst_FPU_PIPELINED_FPADDSUB_intAS) );
DFFRXLTS d_ff4_Yn_Q_reg_63_ ( .D(n2751), .CK(clk), .RN(n6267), .Q(
d_ff_Yn[63]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_63_ ( .D(n2344), .CK(clk), .RN(n6267),
.Q(d_ff2_Y[63]) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n2343), .CK(clk), .RN(n6267), .Q(
d_ff3_sh_y_out[63]) );
DFFRXLTS d_ff4_Xn_Q_reg_63_ ( .D(n2341), .CK(clk), .RN(n6267), .Q(
d_ff_Xn[63]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_63_ ( .D(n2755), .CK(clk), .RN(n6267),
.Q(d_ff2_X[63]) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n2754), .CK(clk), .RN(n6266), .Q(
d_ff3_sh_x_out[63]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(
n2342), .CK(clk), .RN(n6178), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[63]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(
n2753), .CK(clk), .RN(n6178), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[63]), .QN(n6022) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(
n3043), .CK(clk), .RN(n6178), .Q(
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .QN(n5907) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(
n3042), .CK(clk), .RN(n6232), .Q(n5895), .QN(n6041) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
n3040), .CK(clk), .RN(n6178), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n2560),
.CK(clk), .RN(n6178), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[54]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n2558),
.CK(clk), .RN(n6178), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n2980), .CK(clk), .RN(n6266), .Q(
d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n2436), .CK(clk), .RN(n6266),
.Q(d_ff2_Z[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n2979), .CK(clk), .RN(n6266), .Q(
d_ff_Yn[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(n2693), .CK(clk), .RN(n6266),
.Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n2692), .CK(clk), .RN(n6266), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(n2978), .CK(clk), .RN(n6266), .Q(
d_ff_Xn[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(n2843), .CK(clk), .RN(n6266),
.Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n2842), .CK(clk), .RN(n6266), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(
n2691), .CK(clk), .RN(n6179), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(
n2435), .CK(clk), .RN(n6179), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .QN(n5911) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n2983), .CK(clk), .RN(n6265), .Q(
d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n2438), .CK(clk), .RN(n6265),
.Q(d_ff2_Z[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n2982), .CK(clk), .RN(n6265), .Q(
d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(n2696), .CK(clk), .RN(n6265),
.Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n2695), .CK(clk), .RN(n6265), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(n2981), .CK(clk), .RN(n6265), .Q(
d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(n2845), .CK(clk), .RN(n6265),
.Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n2844), .CK(clk), .RN(n6265), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(
n2694), .CK(clk), .RN(n6179), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(
n2437), .CK(clk), .RN(n6179), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .QN(n5991) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n2989), .CK(clk), .RN(n6265), .Q(
d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n2442), .CK(clk), .RN(n6317),
.Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n2988), .CK(clk), .RN(n6322), .Q(
d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(n2702), .CK(clk), .RN(n6314),
.Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n2701), .CK(clk), .RN(n6318), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(n2987), .CK(clk), .RN(n6315), .Q(
d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(n2849), .CK(clk), .RN(n6316),
.Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n2848), .CK(clk), .RN(n6323), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(
n2700), .CK(clk), .RN(n6179), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .QN(n5943) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(
n2441), .CK(clk), .RN(n6179), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .QN(n5963) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n2539),
.CK(clk), .RN(n6179), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n3007), .CK(clk), .RN(n6317), .Q(
d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n2454), .CK(clk), .RN(n6322),
.Q(d_ff2_Z[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n3006), .CK(clk), .RN(n6318), .Q(
d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(n2720), .CK(clk), .RN(n6315),
.Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n2719), .CK(clk), .RN(n6316), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(n3005), .CK(clk), .RN(n6323), .Q(
d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(n2861), .CK(clk), .RN(n6322),
.Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n2860), .CK(clk), .RN(n6317), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(
n2718), .CK(clk), .RN(n6179), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .QN(n5930) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(
n2453), .CK(clk), .RN(n6179), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .QN(n5979) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n3016), .CK(clk), .RN(n6318), .Q(d_ff_Zn[7])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n2460), .CK(clk), .RN(n6315), .Q(
d_ff2_Z[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n3015), .CK(clk), .RN(n6316), .Q(d_ff_Yn[7])
);
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(n2729), .CK(clk), .RN(n6264), .Q(
d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n2728), .CK(clk), .RN(n6264), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(n3014), .CK(clk), .RN(n6264), .Q(d_ff_Xn[7])
);
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(n2867), .CK(clk), .RN(n6264), .Q(
d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n2866), .CK(clk), .RN(n6264), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(
n2727), .CK(clk), .RN(n6180), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .QN(n5904) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(
n2459), .CK(clk), .RN(n6180), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .QN(n5913) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n3019), .CK(clk), .RN(n6264), .Q(d_ff_Zn[6])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n2462), .CK(clk), .RN(n6264), .Q(
d_ff2_Z[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n3018), .CK(clk), .RN(n6264), .Q(d_ff_Yn[6])
);
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(n2732), .CK(clk), .RN(n6264), .Q(
d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n2731), .CK(clk), .RN(n6263), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(n3017), .CK(clk), .RN(n6263), .Q(d_ff_Xn[6])
);
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(n2869), .CK(clk), .RN(n6263), .Q(
d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n2868), .CK(clk), .RN(n6263), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(
n2730), .CK(clk), .RN(n6180), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .QN(n5945) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(
n2461), .CK(clk), .RN(n6180), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .QN(n5978) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n3022), .CK(clk), .RN(n6263), .Q(d_ff_Zn[5])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n2464), .CK(clk), .RN(n6263), .Q(
d_ff2_Z[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n3021), .CK(clk), .RN(n6263), .Q(d_ff_Yn[5])
);
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(n2735), .CK(clk), .RN(n6263), .Q(
d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n2734), .CK(clk), .RN(n6263), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(n3020), .CK(clk), .RN(n6262), .Q(d_ff_Xn[5])
);
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(n2871), .CK(clk), .RN(n6262), .Q(
d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n2870), .CK(clk), .RN(n6262), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(
n2733), .CK(clk), .RN(n6180), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .QN(n5902) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(
n2463), .CK(clk), .RN(n6180), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .QN(n5977) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n2550),
.CK(clk), .RN(n6180), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n2977), .CK(clk), .RN(n6262), .Q(
d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n2434), .CK(clk), .RN(n6262),
.Q(d_ff2_Z[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n2976), .CK(clk), .RN(n6262), .Q(
d_ff_Yn[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(n2690), .CK(clk), .RN(n6262),
.Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n2689), .CK(clk), .RN(n6262), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(n2975), .CK(clk), .RN(n6262), .Q(
d_ff_Xn[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(n2841), .CK(clk), .RN(n6262),
.Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n2840), .CK(clk), .RN(n6261), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(
n2688), .CK(clk), .RN(n6180), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(
n2433), .CK(clk), .RN(n6180), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .QN(n5974) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n3013), .CK(clk), .RN(n6261), .Q(d_ff_Zn[8])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n2458), .CK(clk), .RN(n6261), .Q(
d_ff2_Z[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n3012), .CK(clk), .RN(n6261), .Q(d_ff_Yn[8])
);
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(n2726), .CK(clk), .RN(n6261), .Q(
d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n2725), .CK(clk), .RN(n6261), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(n3011), .CK(clk), .RN(n6261), .Q(d_ff_Xn[8])
);
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(n2865), .CK(clk), .RN(n6261), .Q(
d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n2864), .CK(clk), .RN(n6261), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(
n2724), .CK(clk), .RN(n6180), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(
n2457), .CK(clk), .RN(n6181), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .QN(n5969) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n2549),
.CK(clk), .RN(n6181), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n2974), .CK(clk), .RN(n6260), .Q(
d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n2432), .CK(clk), .RN(n6260),
.Q(d_ff2_Z[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n2973), .CK(clk), .RN(n6260), .Q(
d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(n2687), .CK(clk), .RN(n6260),
.Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n2686), .CK(clk), .RN(n6260), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(n2972), .CK(clk), .RN(n6260), .Q(
d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(n2839), .CK(clk), .RN(n6260),
.Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n2838), .CK(clk), .RN(n6260), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(
n2685), .CK(clk), .RN(n6181), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(
n2431), .CK(clk), .RN(n6181), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .QN(n5967) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n2537),
.CK(clk), .RN(n6181), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n3010), .CK(clk), .RN(n6260), .Q(d_ff_Zn[9])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n2456), .CK(clk), .RN(n6259), .Q(
d_ff2_Z[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n3009), .CK(clk), .RN(n6259), .Q(d_ff_Yn[9])
);
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(n2723), .CK(clk), .RN(n6259), .Q(
d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n2722), .CK(clk), .RN(n6259), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(n3008), .CK(clk), .RN(n6259), .Q(d_ff_Xn[9])
);
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(n2863), .CK(clk), .RN(n6259), .Q(
d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n2862), .CK(clk), .RN(n6259), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(
n2721), .CK(clk), .RN(n6181), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .QN(n6012) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(
n2455), .CK(clk), .RN(n6181), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .QN(n5919) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n2547),
.CK(clk), .RN(n6181), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n3004), .CK(clk), .RN(n6259), .Q(
d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n2452), .CK(clk), .RN(n6259),
.Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n3003), .CK(clk), .RN(n6258), .Q(
d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(n2717), .CK(clk), .RN(n6258),
.Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n2716), .CK(clk), .RN(n6258), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(n3002), .CK(clk), .RN(n6258), .Q(
d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(n2859), .CK(clk), .RN(n6258),
.Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n2858), .CK(clk), .RN(n6258), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(
n2715), .CK(clk), .RN(n6181), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(
n2451), .CK(clk), .RN(n6181), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .QN(n5981) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n2544),
.CK(clk), .RN(n6182), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n2971), .CK(clk), .RN(n6258), .Q(
d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n2430), .CK(clk), .RN(n6258),
.Q(d_ff2_Z[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n2970), .CK(clk), .RN(n6258), .Q(
d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(n2684), .CK(clk), .RN(n6258),
.Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n2683), .CK(clk), .RN(n6257), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(n2969), .CK(clk), .RN(n6257), .Q(
d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(n2837), .CK(clk), .RN(n6257),
.Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n2836), .CK(clk), .RN(n6257), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(
n2682), .CK(clk), .RN(n6182), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(
n2429), .CK(clk), .RN(n6182), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .QN(n5987) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n2536),
.CK(clk), .RN(n6182), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n2959), .CK(clk), .RN(n6257), .Q(
d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n2422), .CK(clk), .RN(n6257),
.Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n2958), .CK(clk), .RN(n6257), .Q(
d_ff_Yn[26]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_26_ ( .D(n2672), .CK(clk), .RN(n6257),
.Q(d_ff2_Y[26]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n2671), .CK(clk), .RN(n6257), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(n2957), .CK(clk), .RN(n6256), .Q(
d_ff_Xn[26]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_26_ ( .D(n2829), .CK(clk), .RN(n6256),
.Q(d_ff2_X[26]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n2828), .CK(clk), .RN(n6256), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(
n2670), .CK(clk), .RN(n6182), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(
n2421), .CK(clk), .RN(n6182), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .QN(n5980) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n2531),
.CK(clk), .RN(n6182), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n2956), .CK(clk), .RN(n6256), .Q(
d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n2420), .CK(clk), .RN(n6256),
.Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n2955), .CK(clk), .RN(n6256), .Q(
d_ff_Yn[27]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_27_ ( .D(n2669), .CK(clk), .RN(n6256),
.Q(d_ff2_Y[27]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n2668), .CK(clk), .RN(n6256), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(n2954), .CK(clk), .RN(n6256), .Q(
d_ff_Xn[27]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_27_ ( .D(n2827), .CK(clk), .RN(n6256),
.Q(d_ff2_X[27]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n2826), .CK(clk), .RN(n6255), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(
n2667), .CK(clk), .RN(n6182), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(
n2419), .CK(clk), .RN(n6182), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .QN(n5912) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n2535),
.CK(clk), .RN(n6182), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n2968), .CK(clk), .RN(n6255), .Q(
d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n2428), .CK(clk), .RN(n6255),
.Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n2967), .CK(clk), .RN(n6255), .Q(
d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(n2681), .CK(clk), .RN(n6255),
.Q(d_ff2_Y[23]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n2680), .CK(clk), .RN(n6255), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(n2966), .CK(clk), .RN(n6255), .Q(
d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(n2835), .CK(clk), .RN(n6255),
.Q(d_ff2_X[23]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n2834), .CK(clk), .RN(n6255), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(
n2679), .CK(clk), .RN(n6183), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(
n2427), .CK(clk), .RN(n6183), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .QN(n5909) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n2534),
.CK(clk), .RN(n6183), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n2965), .CK(clk), .RN(n6254), .Q(
d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n2426), .CK(clk), .RN(n6254),
.Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n2964), .CK(clk), .RN(n6254), .Q(
d_ff_Yn[24]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_24_ ( .D(n2678), .CK(clk), .RN(n6254),
.Q(d_ff2_Y[24]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n2677), .CK(clk), .RN(n6254), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(n2963), .CK(clk), .RN(n6254), .Q(
d_ff_Xn[24]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_24_ ( .D(n2833), .CK(clk), .RN(n6254),
.Q(d_ff2_X[24]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n2832), .CK(clk), .RN(n6254), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(
n2676), .CK(clk), .RN(n6183), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(
n2425), .CK(clk), .RN(n6183), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .QN(n5972) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n2533),
.CK(clk), .RN(n6183), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n2962), .CK(clk), .RN(n6254), .Q(
d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n2424), .CK(clk), .RN(n6320),
.Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n2961), .CK(clk), .RN(n6320), .Q(
d_ff_Yn[25]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_25_ ( .D(n2675), .CK(clk), .RN(n6320),
.Q(d_ff2_Y[25]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n2674), .CK(clk), .RN(n6320), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(n2960), .CK(clk), .RN(n6319), .Q(
d_ff_Xn[25]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_25_ ( .D(n2831), .CK(clk), .RN(n6319),
.Q(d_ff2_X[25]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n2830), .CK(clk), .RN(n6319), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(
n2673), .CK(clk), .RN(n6183), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(
n2423), .CK(clk), .RN(n6183), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .QN(n5992) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n2532),
.CK(clk), .RN(n6183), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n2530),
.CK(clk), .RN(n6183), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n3025), .CK(clk), .RN(n6253), .Q(d_ff_Zn[4])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n2466), .CK(clk), .RN(n6253), .Q(
d_ff2_Z[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n3024), .CK(clk), .RN(n6253), .Q(d_ff_Yn[4])
);
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(n2738), .CK(clk), .RN(n6253), .Q(
d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n2737), .CK(clk), .RN(n6253), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(n3023), .CK(clk), .RN(n6253), .Q(d_ff_Xn[4])
);
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(n2873), .CK(clk), .RN(n6253), .Q(
d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n2872), .CK(clk), .RN(n6252), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(
n2736), .CK(clk), .RN(n6184), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .QN(n5961) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(
n2465), .CK(clk), .RN(n6184), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n3031), .CK(clk), .RN(n6252), .Q(d_ff_Zn[2])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n2470), .CK(clk), .RN(n6252), .Q(
d_ff2_Z[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n3030), .CK(clk), .RN(n6252), .Q(d_ff_Yn[2])
);
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(n2744), .CK(clk), .RN(n6252), .Q(
d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n2743), .CK(clk), .RN(n6252), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(n3029), .CK(clk), .RN(n6252), .Q(d_ff_Xn[2])
);
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(n2877), .CK(clk), .RN(n6252), .Q(
d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n2876), .CK(clk), .RN(n6252), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(
n2742), .CK(clk), .RN(n6184), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(
n2469), .CK(clk), .RN(n6184), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .QN(n5973) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n3034), .CK(clk), .RN(n6251), .Q(d_ff_Zn[1])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n2472), .CK(clk), .RN(n6251), .Q(
d_ff2_Z[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n3033), .CK(clk), .RN(n6251), .Q(d_ff_Yn[1])
);
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(n2747), .CK(clk), .RN(n6251), .Q(
d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n2746), .CK(clk), .RN(n6251), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(n3032), .CK(clk), .RN(n6251), .Q(d_ff_Xn[1])
);
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(n2879), .CK(clk), .RN(n6251), .Q(
d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n2878), .CK(clk), .RN(n6251), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(
n2745), .CK(clk), .RN(n6184), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .QN(n5925) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(
n2471), .CK(clk), .RN(n6184), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .QN(n5964) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n3037), .CK(clk), .RN(n6250), .Q(d_ff_Zn[0])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n2474), .CK(clk), .RN(n6250), .Q(
d_ff2_Z[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n3036), .CK(clk), .RN(n6250), .Q(d_ff_Yn[0])
);
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(n2750), .CK(clk), .RN(n6250), .Q(
d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n2749), .CK(clk), .RN(n6250), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(n3035), .CK(clk), .RN(n6250), .Q(d_ff_Xn[0])
);
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(n2881), .CK(clk), .RN(n6250), .Q(
d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n2880), .CK(clk), .RN(n6250), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(
n2748), .CK(clk), .RN(n6184), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(
n2473), .CK(clk), .RN(n6184), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .QN(n5968) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n2528),
.CK(clk), .RN(n6184), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n2523),
.CK(clk), .RN(n6184), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n2516),
.CK(clk), .RN(n6185), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n2514),
.CK(clk), .RN(n6185), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n2513),
.CK(clk), .RN(n6185), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n2510),
.CK(clk), .RN(n6185), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n2508),
.CK(clk), .RN(n6185), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n2506),
.CK(clk), .RN(n6219), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
n2274), .CK(clk), .RN(n6185), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
n2273), .CK(clk), .RN(n6185), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
n2272), .CK(clk), .RN(n6185), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
n2271), .CK(clk), .RN(n6185), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
n2270), .CK(clk), .RN(n6185), .QN(n5920) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(
n2269), .CK(clk), .RN(n6186), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n2268), .CK(clk), .RN(n6216), .Q(result_add_subt[52]), .QN(n6160) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n2267), .CK(clk), .RN(n6215), .Q(result_add_subt[53]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n2266), .CK(clk), .RN(n6215), .Q(result_add_subt[54]), .QN(n6161) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n2265), .CK(clk), .RN(n6215), .Q(result_add_subt[55]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n2264), .CK(clk), .RN(n6215), .Q(result_add_subt[56]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n2263), .CK(clk), .RN(n6215), .Q(result_add_subt[57]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n2262), .CK(clk), .RN(n6215), .Q(result_add_subt[58]), .QN(n6162) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n2261), .CK(clk), .RN(n6215), .Q(result_add_subt[59]), .QN(n6163) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n2260), .CK(clk), .RN(n6215), .Q(result_add_subt[60]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n2259), .CK(clk), .RN(n6215), .Q(result_add_subt[61]), .QN(n6164) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n2258), .CK(clk), .RN(n6215), .Q(result_add_subt[62]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_52_ ( .D(n2257),
.CK(clk), .RN(n6186), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[52]),
.QN(n5955) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_53_ ( .D(n2256),
.CK(clk), .RN(n6186), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[53])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_54_ ( .D(n2255),
.CK(clk), .RN(n6186), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[54])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_55_ ( .D(n2254),
.CK(clk), .RN(n6186), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[55])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_56_ ( .D(n2253),
.CK(clk), .RN(n6186), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_57_ ( .D(n2252),
.CK(clk), .RN(n6186), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[57])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_58_ ( .D(n2251),
.CK(clk), .RN(n6186), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[58])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_59_ ( .D(n2250),
.CK(clk), .RN(n6186), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[59])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_60_ ( .D(n2249),
.CK(clk), .RN(n6186), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[60])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_61_ ( .D(n2248),
.CK(clk), .RN(n6187), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[61])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_62_ ( .D(n2247),
.CK(clk), .RN(n6187), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[62])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_52_ ( .D(n2246),
.CK(clk), .RN(n6187), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[52]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_52_ ( .D(n2245),
.CK(clk), .RN(n6187), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[52]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_52_ ( .D(n2244),
.CK(clk), .RN(n6187), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[52]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n2243),
.CK(clk), .RN(n6216), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n2242), .CK(clk), .RN(n6216), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_53_ ( .D(n2241),
.CK(clk), .RN(n6187), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[53]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_53_ ( .D(n2240),
.CK(clk), .RN(n6187), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[53]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_53_ ( .D(n2239),
.CK(clk), .RN(n6187), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[53]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n2238),
.CK(clk), .RN(n6217), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n2237), .CK(clk), .RN(n6217), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_54_ ( .D(n2236),
.CK(clk), .RN(n6187), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[54]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_54_ ( .D(n2235),
.CK(clk), .RN(n6187), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[54]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_54_ ( .D(n2234),
.CK(clk), .RN(n6188), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[54]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n2233),
.CK(clk), .RN(n6217), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n2232), .CK(clk), .RN(n6217), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_55_ ( .D(n2231),
.CK(clk), .RN(n6188), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[55]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_55_ ( .D(n2230),
.CK(clk), .RN(n6188), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[55]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_55_ ( .D(n2229),
.CK(clk), .RN(n6188), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[55]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n2228),
.CK(clk), .RN(n6217), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n2227), .CK(clk), .RN(n6217), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_56_ ( .D(n2226),
.CK(clk), .RN(n6188), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[56]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_56_ ( .D(n2225),
.CK(clk), .RN(n6188), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[56]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_56_ ( .D(n2224),
.CK(clk), .RN(n6188), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[56]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n2223),
.CK(clk), .RN(n6217), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n2222), .CK(clk), .RN(n6217), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_57_ ( .D(n2221),
.CK(clk), .RN(n6188), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[57]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_57_ ( .D(n2220),
.CK(clk), .RN(n6188), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[57]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_57_ ( .D(n2219),
.CK(clk), .RN(n6188), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[57]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n2218),
.CK(clk), .RN(n6217), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n2217), .CK(clk), .RN(n6217), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_58_ ( .D(n2216),
.CK(clk), .RN(n6189), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[58]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_58_ ( .D(n2215),
.CK(clk), .RN(n6189), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[58]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_58_ ( .D(n2214),
.CK(clk), .RN(n6189), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[58]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n2213),
.CK(clk), .RN(n6218), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n2212), .CK(clk), .RN(n6218), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_59_ ( .D(n2211),
.CK(clk), .RN(n6189), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[59]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_59_ ( .D(n2210),
.CK(clk), .RN(n6189), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[59]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_59_ ( .D(n2209),
.CK(clk), .RN(n6189), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[59]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n2208),
.CK(clk), .RN(n6218), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n2207), .CK(clk), .RN(n6218), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_60_ ( .D(n2206),
.CK(clk), .RN(n6189), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[60]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_60_ ( .D(n2205),
.CK(clk), .RN(n6189), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[60]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_60_ ( .D(n2204),
.CK(clk), .RN(n6189), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[60]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n2203),
.CK(clk), .RN(n6218), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n2202), .CK(clk), .RN(n6218), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_61_ ( .D(n2201),
.CK(clk), .RN(n6189), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[61]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_61_ ( .D(n2200),
.CK(clk), .RN(n6190), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[61]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_61_ ( .D(n2199),
.CK(clk), .RN(n6190), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[61]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n2198),
.CK(clk), .RN(n6218), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n2197), .CK(clk), .RN(n6218), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_62_ ( .D(n2196),
.CK(clk), .RN(n6190), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[62]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_62_ ( .D(n2195),
.CK(clk), .RN(n6190), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[62]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_62_ ( .D(n2194),
.CK(clk), .RN(n6190), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[62]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n2193),
.CK(clk), .RN(n6218), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
n2192), .CK(clk), .RN(n6218), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_52_ ( .D(n2191),
.CK(clk), .RN(n6190), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[52])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_53_ ( .D(n2190),
.CK(clk), .RN(n6190), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[53]),
.QN(n5954) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_54_ ( .D(n2189),
.CK(clk), .RN(n6190), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[54]),
.QN(n5953) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_55_ ( .D(n2188),
.CK(clk), .RN(n6190), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[55]),
.QN(n6015) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_56_ ( .D(n2187),
.CK(clk), .RN(n6190), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[56])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_57_ ( .D(n2186),
.CK(clk), .RN(n6191), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[57])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n2183), .CK(clk), .RN(n6227), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
n2182), .CK(clk), .RN(n6216), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n2181), .CK(clk), .RN(n6191), .Q(result_add_subt[51]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_51_ ( .D(n2180),
.CK(clk), .RN(n6191), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[51])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(
n2179), .CK(clk), .RN(n6223), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[51]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n2178), .CK(clk), .RN(n6191), .Q(result_add_subt[50]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_50_ ( .D(n2177),
.CK(clk), .RN(n6191), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[50])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(
n2176), .CK(clk), .RN(n6222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[50]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n2175), .CK(clk), .RN(n6191), .Q(result_add_subt[47]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_47_ ( .D(n2174),
.CK(clk), .RN(n6191), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[47])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(
n2173), .CK(clk), .RN(n6222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[47]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n2172), .CK(clk), .RN(n6191), .Q(result_add_subt[49]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_49_ ( .D(n2171),
.CK(clk), .RN(n6191), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[49])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(
n2170), .CK(clk), .RN(n6192), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[49]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n2169), .CK(clk), .RN(n6192), .Q(result_add_subt[48]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_48_ ( .D(n2168),
.CK(clk), .RN(n6192), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[48])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(
n2167), .CK(clk), .RN(n6192), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[48]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n2166), .CK(clk), .RN(n6192), .Q(result_add_subt[33]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_33_ ( .D(n2165),
.CK(clk), .RN(n6192), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[33])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(
n2164), .CK(clk), .RN(n6221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[33]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n2163), .CK(clk), .RN(n6192), .Q(result_add_subt[44]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_44_ ( .D(n2162),
.CK(clk), .RN(n6192), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[44])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(
n2161), .CK(clk), .RN(n6192), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[44]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n2160),
.CK(clk), .RN(n6192), .Q(result_add_subt[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n2159),
.CK(clk), .RN(n6193), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n2158), .CK(clk), .RN(n6219), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n2157), .CK(clk), .RN(n6193), .Q(result_add_subt[34]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_34_ ( .D(n2156),
.CK(clk), .RN(n6193), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[34])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(
n2155), .CK(clk), .RN(n6222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[34]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n2154), .CK(clk), .RN(n6193), .Q(result_add_subt[45]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_45_ ( .D(n2153),
.CK(clk), .RN(n6193), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[45])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(
n2152), .CK(clk), .RN(n6193), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[45]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n2151), .CK(clk), .RN(n6193), .Q(result_add_subt[46]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_46_ ( .D(n2150),
.CK(clk), .RN(n6193), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[46])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(
n2149), .CK(clk), .RN(n6222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[46]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n2148), .CK(clk), .RN(n6193), .Q(result_add_subt[35]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_35_ ( .D(n2147),
.CK(clk), .RN(n6193), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[35])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(
n2146), .CK(clk), .RN(n6222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[35]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n2145), .CK(clk), .RN(n6194), .Q(result_add_subt[42]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_42_ ( .D(n2144),
.CK(clk), .RN(n6194), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[42])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(
n2143), .CK(clk), .RN(n6222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[42]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n2142), .CK(clk), .RN(n6194), .Q(result_add_subt[43]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_43_ ( .D(n2141),
.CK(clk), .RN(n6194), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[43])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(
n2140), .CK(clk), .RN(n6222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[43]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n2139), .CK(clk), .RN(n6194), .Q(result_add_subt[36]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_36_ ( .D(n2138),
.CK(clk), .RN(n6194), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[36])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(
n2137), .CK(clk), .RN(n6194), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[36]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n2136), .CK(clk), .RN(n6194), .Q(result_add_subt[39]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_39_ ( .D(n2135),
.CK(clk), .RN(n6194), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[39])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(
n2134), .CK(clk), .RN(n6222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[39]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n2133), .CK(clk), .RN(n6194), .Q(result_add_subt[41]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_41_ ( .D(n2132),
.CK(clk), .RN(n6195), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[41])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(
n2131), .CK(clk), .RN(n6222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[41]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n2130), .CK(clk), .RN(n6195), .Q(result_add_subt[38]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_38_ ( .D(n2129),
.CK(clk), .RN(n6195), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[38])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(
n2128), .CK(clk), .RN(n6195), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[38]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n2127), .CK(clk), .RN(n6195), .Q(result_add_subt[40]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_40_ ( .D(n2126),
.CK(clk), .RN(n6195), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[40])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(
n2125), .CK(clk), .RN(n6195), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[40]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n2124), .CK(clk), .RN(n6195), .Q(result_add_subt[37]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_37_ ( .D(n2123),
.CK(clk), .RN(n6195), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[37])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(
n2122), .CK(clk), .RN(n6222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[37]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n2121), .CK(clk), .RN(n6195), .Q(result_add_subt[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_28_ ( .D(n2120),
.CK(clk), .RN(n6196), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[28])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(
n2119), .CK(clk), .RN(n6221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n2118), .CK(clk), .RN(n6196), .Q(result_add_subt[31]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_31_ ( .D(n2117),
.CK(clk), .RN(n6196), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[31])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(
n2116), .CK(clk), .RN(n6221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[31]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n2115), .CK(clk), .RN(n6196), .Q(result_add_subt[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n2114),
.CK(clk), .RN(n6196), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
n2113), .CK(clk), .RN(n6219), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n2112), .CK(clk), .RN(n6196), .Q(result_add_subt[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n2111),
.CK(clk), .RN(n6196), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
n2110), .CK(clk), .RN(n6220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n2109), .CK(clk), .RN(n6196), .Q(result_add_subt[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_30_ ( .D(n2108),
.CK(clk), .RN(n6196), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[30])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(
n2107), .CK(clk), .RN(n6221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n2106), .CK(clk), .RN(n6196), .Q(result_add_subt[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n2105),
.CK(clk), .RN(n6197), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
n2104), .CK(clk), .RN(n6220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n2103), .CK(clk), .RN(n6197), .Q(result_add_subt[32]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_32_ ( .D(n2102),
.CK(clk), .RN(n6197), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[32])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(
n2101), .CK(clk), .RN(n6221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[32]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n2100), .CK(clk), .RN(n6197), .Q(result_add_subt[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n2099),
.CK(clk), .RN(n6197), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
n2098), .CK(clk), .RN(n6197), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n2097), .CK(clk), .RN(n6197), .Q(result_add_subt[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_29_ ( .D(n2096),
.CK(clk), .RN(n6197), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[29])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(
n2095), .CK(clk), .RN(n6221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n2094), .CK(clk), .RN(n6197), .Q(result_add_subt[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n2093),
.CK(clk), .RN(n6197), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n2092),
.CK(clk), .RN(n6198), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n2091),
.CK(clk), .RN(n6198), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n2090),
.CK(clk), .RN(n6198), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n2089),
.CK(clk), .RN(n6198), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(
n2088), .CK(clk), .RN(n6214), .Q(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n2087), .CK(clk), .RN(n6198), .Q(result_add_subt[63]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n2086),
.CK(clk), .RN(n6198), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n2085),
.CK(clk), .RN(n6198), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n2084),
.CK(clk), .RN(n6198), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n2083),
.CK(clk), .RN(n6228), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n2080),
.CK(clk), .RN(n6223), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n2079),
.CK(clk), .RN(n6223), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n5891) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n2078),
.CK(clk), .RN(n6223), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .QN(n5941) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n2077),
.CK(clk), .RN(n6223), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n6029) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n2076),
.CK(clk), .RN(n6224), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n2075),
.CK(clk), .RN(n6224), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n5901) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n2074),
.CK(clk), .RN(n6224), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n5936) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n2073),
.CK(clk), .RN(n6223), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n6034) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n2072),
.CK(clk), .RN(n6223), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n5947) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n2071),
.CK(clk), .RN(n6223), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n6025) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n2070), .CK(clk), .RN(n6223), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]),
.QN(n5932) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n2069), .CK(clk), .RN(n6223), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.QN(n6028) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n2068), .CK(clk), .RN(n6228), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n2067), .CK(clk), .RN(n6228), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]),
.QN(n5900) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n2066), .CK(clk), .RN(n6228), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]),
.QN(n5926) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n2065), .CK(clk), .RN(n6224), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]),
.QN(n5927) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n2064), .CK(clk), .RN(n6224), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]),
.QN(n5948) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n2063), .CK(clk), .RN(n6228), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]),
.QN(n6033) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n2062), .CK(clk), .RN(n6224), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n2061), .CK(clk), .RN(n6227), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n2060), .CK(clk), .RN(n6227), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]),
.QN(n6031) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n2059), .CK(clk), .RN(n6228), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]),
.QN(n5924) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n2058), .CK(clk), .RN(n6227), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]),
.QN(n6030) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n2057), .CK(clk), .RN(n6228), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]),
.QN(n5946) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n2056), .CK(clk), .RN(n6224), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]),
.QN(n5923) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n2055), .CK(clk), .RN(n6224), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]),
.QN(n5952) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n2054), .CK(clk), .RN(n6224), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[26]),
.QN(n5898) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n2053), .CK(clk), .RN(n6224), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[27])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n2050), .CK(clk), .RN(n6225), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]),
.QN(n3203) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n2047), .CK(clk), .RN(n6225), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n2045), .CK(clk), .RN(n6225), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[35])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n2044), .CK(clk), .RN(n6225), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[36])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n2043), .CK(clk), .RN(n6226), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[37])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n2042), .CK(clk), .RN(n6225), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[38])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n2041), .CK(clk), .RN(n6226), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[39])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n2039), .CK(clk), .RN(n6226), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[41]),
.QN(n3204) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n2038), .CK(clk), .RN(n6226), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[42]),
.QN(n3205) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n2037), .CK(clk), .RN(n6226), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n2036), .CK(clk), .RN(n6227), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[44]),
.QN(n3206) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n2032), .CK(clk), .RN(n6226), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[48]),
.QN(n3208) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n2029), .CK(clk), .RN(n6227), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[51])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n2028), .CK(clk), .RN(n6227), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[52])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n2027), .CK(clk), .RN(n6227), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[53])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(
n2026), .CK(clk), .RN(n6216), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(
n2025), .CK(clk), .RN(n6216), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(
n2024), .CK(clk), .RN(n6216), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
n2023), .CK(clk), .RN(n6216), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(
n2022), .CK(clk), .RN(n6216), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n2021), .CK(clk), .RN(n6198), .Q(result_add_subt[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n2020),
.CK(clk), .RN(n6198), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
n2019), .CK(clk), .RN(n6220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n2018),
.CK(clk), .RN(n6199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n2017),
.CK(clk), .RN(n6199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n6073),
.CK(clk), .RN(n6238), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n2014), .CK(clk), .RN(n6199), .Q(result_add_subt[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n2013),
.CK(clk), .RN(n6199), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
n2012), .CK(clk), .RN(n6220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n2011),
.CK(clk), .RN(n6199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n2010),
.CK(clk), .RN(n6199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n6072),
.CK(clk), .RN(n6238), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n2008),
.CK(clk), .RN(n6238), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n2007), .CK(clk), .RN(n6199), .Q(result_add_subt[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n2006),
.CK(clk), .RN(n6199), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
n2005), .CK(clk), .RN(n6220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n2004),
.CK(clk), .RN(n6199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n2003),
.CK(clk), .RN(n6199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n6071),
.CK(clk), .RN(n6237), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n2000), .CK(clk), .RN(n6200), .Q(result_add_subt[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1999),
.CK(clk), .RN(n6200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
n1998), .CK(clk), .RN(n6200), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1997),
.CK(clk), .RN(n6200), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1996),
.CK(clk), .RN(n6200), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n6070),
.CK(clk), .RN(n6236), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1994),
.CK(clk), .RN(n6236), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1993),
.CK(clk), .RN(n6200), .Q(result_add_subt[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1992),
.CK(clk), .RN(n6200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1991), .CK(clk), .RN(n6219), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1990),
.CK(clk), .RN(n6200), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1989),
.CK(clk), .RN(n6200), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n6053),
.CK(clk), .RN(n6235), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1987),
.CK(clk), .RN(n6235), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1986),
.CK(clk), .RN(n6200), .Q(result_add_subt[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1985),
.CK(clk), .RN(n6201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1984), .CK(clk), .RN(n6219), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1983),
.CK(clk), .RN(n6201), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1982),
.CK(clk), .RN(n6201), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n6052),
.CK(clk), .RN(n6235), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1980),
.CK(clk), .RN(n6235), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1979),
.CK(clk), .RN(n6201), .Q(result_add_subt[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1978),
.CK(clk), .RN(n6201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1977), .CK(clk), .RN(n6201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1976), .CK(clk), .RN(n6201), .Q(result_add_subt[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1975),
.CK(clk), .RN(n6201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
n1974), .CK(clk), .RN(n6220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1973),
.CK(clk), .RN(n6201), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1972),
.CK(clk), .RN(n6201), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n6069),
.CK(clk), .RN(n6238), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1970),
.CK(clk), .RN(n6238), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1969),
.CK(clk), .RN(n6202), .Q(result_add_subt[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1968),
.CK(clk), .RN(n6202), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1967), .CK(clk), .RN(n6219), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1966), .CK(clk), .RN(n6202), .Q(result_add_subt[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1965),
.CK(clk), .RN(n6202), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
n1964), .CK(clk), .RN(n6220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1963),
.CK(clk), .RN(n6202), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1962),
.CK(clk), .RN(n6202), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n6068),
.CK(clk), .RN(n6238), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1960),
.CK(clk), .RN(n6238), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1959),
.CK(clk), .RN(n6202), .Q(result_add_subt[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1958),
.CK(clk), .RN(n6202), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1957), .CK(clk), .RN(n6219), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1956),
.CK(clk), .RN(n6202), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1955),
.CK(clk), .RN(n6202), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n6051),
.CK(clk), .RN(n6236), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1952), .CK(clk), .RN(n6203), .Q(result_add_subt[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1951),
.CK(clk), .RN(n6203), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
n1950), .CK(clk), .RN(n6219), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1949), .CK(clk), .RN(n6203), .Q(result_add_subt[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1948),
.CK(clk), .RN(n6203), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
n1947), .CK(clk), .RN(n6220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1946),
.CK(clk), .RN(n6203), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1945),
.CK(clk), .RN(n6203), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n6067),
.CK(clk), .RN(n6238), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1943),
.CK(clk), .RN(n6238), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1942), .CK(clk), .RN(n6203), .Q(result_add_subt[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1941),
.CK(clk), .RN(n6203), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(
n1940), .CK(clk), .RN(n6221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1939), .CK(clk), .RN(n6203), .Q(result_add_subt[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1938),
.CK(clk), .RN(n6203), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(
n1937), .CK(clk), .RN(n6221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1936), .CK(clk), .RN(n6204), .Q(result_add_subt[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1935),
.CK(clk), .RN(n6204), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(
n1934), .CK(clk), .RN(n6220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1933),
.CK(clk), .RN(n6204), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1932),
.CK(clk), .RN(n6204), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n6066),
.CK(clk), .RN(n6239), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1930),
.CK(clk), .RN(n6239), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1929), .CK(clk), .RN(n6204), .Q(result_add_subt[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1928),
.CK(clk), .RN(n6204), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(
n1927), .CK(clk), .RN(n6221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1926),
.CK(clk), .RN(n6204), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1925),
.CK(clk), .RN(n6204), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n6065),
.CK(clk), .RN(n6239), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1923),
.CK(clk), .RN(n6239), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1922), .CK(clk), .RN(n6204), .Q(result_add_subt[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1921),
.CK(clk), .RN(n6204), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(
n1920), .CK(clk), .RN(n6221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1919),
.CK(clk), .RN(n6205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1918),
.CK(clk), .RN(n6205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n6064),
.CK(clk), .RN(n6239), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1916),
.CK(clk), .RN(n6239), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1915),
.CK(clk), .RN(n6205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1914),
.CK(clk), .RN(n6205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n6063),
.CK(clk), .RN(n6239), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1912),
.CK(clk), .RN(n6239), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1911),
.CK(clk), .RN(n6205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1910),
.CK(clk), .RN(n6205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n6062),
.CK(clk), .RN(n6239), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1908),
.CK(clk), .RN(n6239), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1907),
.CK(clk), .RN(n6205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1906),
.CK(clk), .RN(n6205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n6061),
.CK(clk), .RN(n6236), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1904),
.CK(clk), .RN(n6236), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1903),
.CK(clk), .RN(n6205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1902),
.CK(clk), .RN(n6205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n6050),
.CK(clk), .RN(n6236), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1899),
.CK(clk), .RN(n6206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1898),
.CK(clk), .RN(n6206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n6049),
.CK(clk), .RN(n6235), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1896),
.CK(clk), .RN(n6235), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1895),
.CK(clk), .RN(n6206), .Q(result_add_subt[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1894),
.CK(clk), .RN(n6206), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1893), .CK(clk), .RN(n6219), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1892),
.CK(clk), .RN(n6206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1891),
.CK(clk), .RN(n6206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n6048),
.CK(clk), .RN(n6235), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1889),
.CK(clk), .RN(n6235), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1888),
.CK(clk), .RN(n6206), .Q(result_add_subt[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1887),
.CK(clk), .RN(n6206), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1886), .CK(clk), .RN(n6206), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1885),
.CK(clk), .RN(n6206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1884),
.CK(clk), .RN(n6207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n6047),
.CK(clk), .RN(n6234), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1882),
.CK(clk), .RN(n6234), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1881),
.CK(clk), .RN(n6207), .Q(result_add_subt[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1880),
.CK(clk), .RN(n6207), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1879), .CK(clk), .RN(n6207), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1878),
.CK(clk), .RN(n6207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1877),
.CK(clk), .RN(n6207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n6046),
.CK(clk), .RN(n6234), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1875),
.CK(clk), .RN(n6234), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1874),
.CK(clk), .RN(n6207), .Q(result_add_subt[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1873),
.CK(clk), .RN(n6207), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1872), .CK(clk), .RN(n6219), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1871),
.CK(clk), .RN(n6207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1870),
.CK(clk), .RN(n6207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n6045),
.CK(clk), .RN(n6234), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1867),
.CK(clk), .RN(n6208), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1866),
.CK(clk), .RN(n6208), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1865),
.CK(clk), .RN(n6208), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1864),
.CK(clk), .RN(n6208), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1863),
.CK(clk), .RN(n6208), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(
n1862), .CK(clk), .RN(n6208), .Q(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1860),
.CK(clk), .RN(n6208), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
n1859), .CK(clk), .RN(n6220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1858),
.CK(clk), .RN(n6208), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1857),
.CK(clk), .RN(n6208), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n6060),
.CK(clk), .RN(n6237), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1855),
.CK(clk), .RN(n6237), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1854),
.CK(clk), .RN(n6209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1853),
.CK(clk), .RN(n6209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n6079),
.CK(clk), .RN(n6240), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1851),
.CK(clk), .RN(n6240), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1850),
.CK(clk), .RN(n6209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1849),
.CK(clk), .RN(n6209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n6059),
.CK(clk), .RN(n6237), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1847),
.CK(clk), .RN(n6237), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_32_ ( .D(n1846),
.CK(clk), .RN(n6209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[32])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1845),
.CK(clk), .RN(n6209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[32]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_32_ ( .D(n6078),
.CK(clk), .RN(n6240), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[32]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_32_ ( .D(n1843),
.CK(clk), .RN(n6240), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1842),
.CK(clk), .RN(n6209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1841),
.CK(clk), .RN(n6209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n6058),
.CK(clk), .RN(n6237), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1839),
.CK(clk), .RN(n6237), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1838),
.CK(clk), .RN(n6209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1837),
.CK(clk), .RN(n6209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n6077),
.CK(clk), .RN(n6240), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1835),
.CK(clk), .RN(n6240), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1834),
.CK(clk), .RN(n6210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1833),
.CK(clk), .RN(n6210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n6057),
.CK(clk), .RN(n6237), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1830),
.CK(clk), .RN(n6210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1829),
.CK(clk), .RN(n6210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n6056),
.CK(clk), .RN(n6236), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1827),
.CK(clk), .RN(n6236), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_31_ ( .D(n1826),
.CK(clk), .RN(n6210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[31])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1825),
.CK(clk), .RN(n6210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[31]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_31_ ( .D(n6076),
.CK(clk), .RN(n6240), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[31]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_31_ ( .D(n1823),
.CK(clk), .RN(n6240), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[31]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1822),
.CK(clk), .RN(n6210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1821),
.CK(clk), .RN(n6210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n6055),
.CK(clk), .RN(n6240), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1819),
.CK(clk), .RN(n6240), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_37_ ( .D(n1818),
.CK(clk), .RN(n6210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[37])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1817),
.CK(clk), .RN(n6210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[37]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1816),
.CK(clk), .RN(n6241), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[37]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_37_ ( .D(n1815),
.CK(clk), .RN(n6241), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[37]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_40_ ( .D(n1814),
.CK(clk), .RN(n6211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[40])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1813),
.CK(clk), .RN(n6211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[40]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1812),
.CK(clk), .RN(n6242), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[40]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_40_ ( .D(n1811),
.CK(clk), .RN(n6242), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[40]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_38_ ( .D(n1810),
.CK(clk), .RN(n6211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[38])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1809),
.CK(clk), .RN(n6211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[38]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1808),
.CK(clk), .RN(n6242), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[38]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_38_ ( .D(n1807),
.CK(clk), .RN(n6242), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_41_ ( .D(n1806),
.CK(clk), .RN(n6211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[41])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1805),
.CK(clk), .RN(n6211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[41]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1804),
.CK(clk), .RN(n6242), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[41]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_41_ ( .D(n1803),
.CK(clk), .RN(n6242), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[41]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_39_ ( .D(n1802),
.CK(clk), .RN(n6211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[39])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1801),
.CK(clk), .RN(n6211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[39]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1800),
.CK(clk), .RN(n6242), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[39]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_39_ ( .D(n1799),
.CK(clk), .RN(n6242), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[39]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_36_ ( .D(n1798),
.CK(clk), .RN(n6211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[36])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1797),
.CK(clk), .RN(n6211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[36]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1796),
.CK(clk), .RN(n6241), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[36]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_36_ ( .D(n1795),
.CK(clk), .RN(n6241), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_43_ ( .D(n1794),
.CK(clk), .RN(n6212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[43])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1793),
.CK(clk), .RN(n6212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[43]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1792),
.CK(clk), .RN(n6243), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[43]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_43_ ( .D(n1791),
.CK(clk), .RN(n6243), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[43]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_42_ ( .D(n1790),
.CK(clk), .RN(n6212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[42])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1789),
.CK(clk), .RN(n6212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[42]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1788),
.CK(clk), .RN(n6242), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[42]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_42_ ( .D(n1787),
.CK(clk), .RN(n6242), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_35_ ( .D(n1786),
.CK(clk), .RN(n6212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[35])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1785),
.CK(clk), .RN(n6212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[35]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_35_ ( .D(n6054),
.CK(clk), .RN(n6241), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[35]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_35_ ( .D(n1783),
.CK(clk), .RN(n6241), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[35]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_46_ ( .D(n1782),
.CK(clk), .RN(n6212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[46])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1781),
.CK(clk), .RN(n6212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[46]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1780),
.CK(clk), .RN(n6243), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[46]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_46_ ( .D(n1779),
.CK(clk), .RN(n6243), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]),
.QN(n3200) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_45_ ( .D(n1778),
.CK(clk), .RN(n6212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[45])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1777),
.CK(clk), .RN(n6212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[45]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1776),
.CK(clk), .RN(n6243), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[45]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_45_ ( .D(n1775),
.CK(clk), .RN(n6243), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[45]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_34_ ( .D(n1774),
.CK(clk), .RN(n6213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[34])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1773),
.CK(clk), .RN(n6213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[34]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_34_ ( .D(n6075),
.CK(clk), .RN(n6241), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[34]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_34_ ( .D(n1771),
.CK(clk), .RN(n6241), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1770),
.CK(clk), .RN(n6213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1769),
.CK(clk), .RN(n6213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n6044),
.CK(clk), .RN(n6235), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1767),
.CK(clk), .RN(n6235), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_44_ ( .D(n1766),
.CK(clk), .RN(n6213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[44])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1765),
.CK(clk), .RN(n6213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[44]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1764),
.CK(clk), .RN(n6243), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[44]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_44_ ( .D(n1763),
.CK(clk), .RN(n6243), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_33_ ( .D(n1762),
.CK(clk), .RN(n6213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[33])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1761),
.CK(clk), .RN(n6213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[33]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_33_ ( .D(n6074),
.CK(clk), .RN(n6241), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[33]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_33_ ( .D(n1759),
.CK(clk), .RN(n6241), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[33]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_48_ ( .D(n1758),
.CK(clk), .RN(n6213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[48])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1757),
.CK(clk), .RN(n6213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[48]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1756),
.CK(clk), .RN(n6244), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[48]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_48_ ( .D(n1755),
.CK(clk), .RN(n6244), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_49_ ( .D(n1754),
.CK(clk), .RN(n6214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[49])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1753),
.CK(clk), .RN(n6214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[49]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1752),
.CK(clk), .RN(n6244), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[49]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_49_ ( .D(n1751),
.CK(clk), .RN(n6244), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[49]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_47_ ( .D(n1750),
.CK(clk), .RN(n6214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[47])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1749),
.CK(clk), .RN(n6214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[47]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1748),
.CK(clk), .RN(n6243), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[47]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_47_ ( .D(n1747),
.CK(clk), .RN(n6243), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[47]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_50_ ( .D(n1746),
.CK(clk), .RN(n6214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[50])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1745),
.CK(clk), .RN(n6214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[50]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1744),
.CK(clk), .RN(n6244), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[50]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_50_ ( .D(n1743),
.CK(clk), .RN(n6244), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]),
.QN(n3201) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_51_ ( .D(n1742),
.CK(clk), .RN(n6214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[51])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1741),
.CK(clk), .RN(n6214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[51]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1740),
.CK(clk), .RN(n6244), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[51]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_51_ ( .D(n1739),
.CK(clk), .RN(n6244), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[51]),
.QN(n3202) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1737),
.CK(clk), .RN(n6228), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n3207) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1708), .CK(clk), .RN(n6231), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[30]),
.QN(n6155) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1707), .CK(clk), .RN(n6231), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[31]),
.QN(n6159) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1706), .CK(clk), .RN(n6232), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[32]),
.QN(n6154) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1705), .CK(clk), .RN(n6232), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[33]),
.QN(n6158) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1704), .CK(clk), .RN(n6232), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[34]),
.QN(n6153) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1703), .CK(clk), .RN(n6232), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[35]),
.QN(n6157) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1702), .CK(clk), .RN(n6232), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[36]),
.QN(n6152) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1701), .CK(clk), .RN(n6232), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[37]),
.QN(n6156) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1700), .CK(clk), .RN(n6232), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[38]),
.QN(n6144) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1699), .CK(clk), .RN(n6232), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[39]),
.QN(n6151) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1698), .CK(clk), .RN(n6232), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[40]),
.QN(n6143) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1697), .CK(clk), .RN(n6233), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[41]),
.QN(n6150) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1696), .CK(clk), .RN(n6233), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[42]),
.QN(n6142) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1695), .CK(clk), .RN(n6233), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[43]),
.QN(n6149) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1694), .CK(clk), .RN(n6233), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[44]),
.QN(n6141) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1693), .CK(clk), .RN(n6233), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[45]),
.QN(n6148) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1692), .CK(clk), .RN(n6233), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[46]),
.QN(n6140) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1691), .CK(clk), .RN(n6233), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[47]),
.QN(n6147) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1690), .CK(clk), .RN(n6233), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[48]),
.QN(n6139) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1689), .CK(clk), .RN(n6233), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[49]),
.QN(n6146) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1688), .CK(clk), .RN(n6233), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[50]),
.QN(n6138) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1687), .CK(clk), .RN(n6234), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[51]),
.QN(n6145) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1686), .CK(clk), .RN(n6234), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[52]),
.QN(n6125) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1685), .CK(clk), .RN(n6234), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[53]),
.QN(n6124) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1684), .CK(clk), .RN(n6234), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[54]),
.QN(n6123) );
CMPR32X2TS intadd_22_U4 ( .A(n5954), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[53]), .C(intadd_22_CI), .CO(
intadd_22_n3), .S(intadd_22_SUM_0_) );
CMPR32X2TS intadd_22_U3 ( .A(n5953), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[54]), .C(intadd_22_n3), .CO(
intadd_22_n2), .S(intadd_22_SUM_1_) );
CMPR32X2TS intadd_22_U2 ( .A(n6015), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[55]), .C(intadd_22_n2), .CO(
intadd_22_n1), .S(intadd_22_SUM_2_) );
CMPR32X2TS intadd_23_U4 ( .A(d_ff2_Y[53]), .B(n5899), .C(intadd_23_CI), .CO(
intadd_23_n3), .S(intadd_23_SUM_0_) );
CMPR32X2TS intadd_23_U3 ( .A(d_ff2_Y[54]), .B(n5928), .C(intadd_23_n3), .CO(
intadd_23_n2), .S(intadd_23_SUM_1_) );
CMPR32X2TS intadd_23_U2 ( .A(d_ff2_Y[55]), .B(n3184), .C(intadd_23_n2), .CO(
intadd_23_n1), .S(intadd_23_SUM_2_) );
CMPR32X2TS intadd_24_U4 ( .A(d_ff2_X[53]), .B(n5899), .C(intadd_24_CI), .CO(
intadd_24_n3), .S(intadd_24_SUM_0_) );
CMPR32X2TS intadd_24_U3 ( .A(d_ff2_X[54]), .B(n5928), .C(intadd_24_n3), .CO(
intadd_24_n2), .S(intadd_24_SUM_1_) );
CMPR32X2TS intadd_24_U2 ( .A(d_ff2_X[55]), .B(n3184), .C(intadd_24_n2), .CO(
intadd_24_n1), .S(intadd_24_SUM_2_) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n3169),
.CK(clk), .RN(n6166), .Q(n5894), .QN(n6094) );
DFFRXLTS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n6312), .Q(
inst_CORDIC_FSM_v3_state_reg[1]), .QN(n5959) );
DFFRXLTS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n6312), .Q(
inst_CORDIC_FSM_v3_state_reg[2]), .QN(n5950) );
DFFRX1TS ITER_CONT_temp_reg_1_ ( .D(n3163), .CK(clk), .RN(n6313), .Q(
cont_iter_out[1]), .QN(n5899) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n2557),
.CK(clk), .RN(n6178), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[51]), .QN(n6021) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n2551),
.CK(clk), .RN(n6172), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .QN(n5921) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n2559),
.CK(clk), .RN(n6178), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[53]), .QN(n6020) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1861),
.CK(clk), .RN(n6208), .Q(zero_flag) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n2185),
.CK(clk), .RN(n6191), .Q(underflow_flag) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(n2276), .CK(clk), .RN(n6250), .Q(
data_output[63]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n2184),
.CK(clk), .RN(n6214), .Q(overflow_flag) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n2288), .CK(clk), .RN(n6297), .Q(
data_output[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n2287), .CK(clk), .RN(n6297), .Q(
data_output[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n2286), .CK(clk), .RN(n6296), .Q(
data_output[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n2285), .CK(clk), .RN(n6295), .Q(
data_output[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n2284), .CK(clk), .RN(n6295), .Q(
data_output[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n2283), .CK(clk), .RN(n6294), .Q(
data_output[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n2282), .CK(clk), .RN(n6293), .Q(
data_output[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n2281), .CK(clk), .RN(n6292), .Q(
data_output[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n2280), .CK(clk), .RN(n6292), .Q(
data_output[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n2279), .CK(clk), .RN(n6291), .Q(
data_output[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n2278), .CK(clk), .RN(n6290), .Q(
data_output[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n2321), .CK(clk), .RN(n6266), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n2322), .CK(clk), .RN(n6265), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n2324), .CK(clk), .RN(n6323), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n2330), .CK(clk), .RN(n6314), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n2333), .CK(clk), .RN(n6264), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n2334), .CK(clk), .RN(n6263), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n2320), .CK(clk), .RN(n6261), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n2319), .CK(clk), .RN(n6260), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n2331), .CK(clk), .RN(n6259), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n2318), .CK(clk), .RN(n6257), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n2317), .CK(clk), .RN(n6255), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n2316), .CK(clk), .RN(n6254), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n2315), .CK(clk), .RN(n6320), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n2313), .CK(clk), .RN(n6320), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n2314), .CK(clk), .RN(n6320), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n2329), .CK(clk), .RN(n6253), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n2332), .CK(clk), .RN(n6253), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n2335), .CK(clk), .RN(n6253), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n2336), .CK(clk), .RN(n6252), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n2338), .CK(clk), .RN(n6251), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n2339), .CK(clk), .RN(n6251), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n2340), .CK(clk), .RN(n6250), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n2327), .CK(clk), .RN(n6249), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n2311), .CK(clk), .RN(n6249), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n2326), .CK(clk), .RN(n6249), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n2308), .CK(clk), .RN(n6249), .Q(
data_output[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n2323), .CK(clk), .RN(n6249), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n2310), .CK(clk), .RN(n6249), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n2325), .CK(clk), .RN(n6249), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n2328), .CK(clk), .RN(n6249), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n2309), .CK(clk), .RN(n6249), .Q(
data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n2312), .CK(clk), .RN(n6249), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n2303), .CK(clk), .RN(n6324), .Q(
data_output[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n2300), .CK(clk), .RN(n6324), .Q(
data_output[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n2302), .CK(clk), .RN(n6319), .Q(
data_output[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n2299), .CK(clk), .RN(n6324), .Q(
data_output[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n2301), .CK(clk), .RN(n6319), .Q(
data_output[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n2304), .CK(clk), .RN(n6313), .Q(
data_output[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n2297), .CK(clk), .RN(n6324), .Q(
data_output[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n2298), .CK(clk), .RN(n6319), .Q(
data_output[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n2305), .CK(clk), .RN(n6313), .Q(
data_output[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n2294), .CK(clk), .RN(n6313), .Q(
data_output[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n2295), .CK(clk), .RN(n6248), .Q(
data_output[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n2306), .CK(clk), .RN(n6248), .Q(
data_output[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n2337), .CK(clk), .RN(n6248), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n2296), .CK(clk), .RN(n6248), .Q(
data_output[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n2307), .CK(clk), .RN(n6248), .Q(
data_output[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n2292), .CK(clk), .RN(n6248), .Q(
data_output[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n2291), .CK(clk), .RN(n6248), .Q(
data_output[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n2293), .CK(clk), .RN(n6248), .Q(
data_output[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n2290), .CK(clk), .RN(n6248), .Q(
data_output[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n2289), .CK(clk), .RN(n6248), .Q(
data_output[51]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
n3039), .CK(clk), .RN(n6178), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n6013) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
n3041), .CK(clk), .RN(n6178), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n5940) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(
n3038), .CK(clk), .RN(n6179), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[5]), .QN(n5893) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n2082),
.CK(clk), .RN(n6228), .Q(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM),
.QN(n5958) );
DFFRXLTS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n6313), .Q(
inst_CORDIC_FSM_v3_state_reg[6]) );
DFFSX1TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n6313), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
CMPR32X2TS DP_OP_33J12_122_5452_U10 ( .A(DP_OP_33J12_122_5452_n20), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]), .C(
DP_OP_33J12_122_5452_n10), .CO(DP_OP_33J12_122_5452_n9), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_33J12_122_5452_U12 ( .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]), .B(n3183), .C(
DP_OP_33J12_122_5452_n22), .CO(DP_OP_33J12_122_5452_n11), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]) );
ADDFX1TS DP_OP_33J12_122_5452_U2 ( .A(n5897), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[10]), .CI(
DP_OP_33J12_122_5452_n2), .CO(DP_OP_33J12_122_5452_n1), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n2052), .CK(clk), .RN(n6225), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]),
.QN(n6036) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1728), .CK(clk), .RN(n6229), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]),
.QN(n6114) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1713), .CK(clk), .RN(n6231), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]),
.QN(n6099) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n2033), .CK(clk), .RN(n6226), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]),
.QN(n5934) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n2015),
.CK(clk), .RN(n6238), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]) );
DFFRXLTS ITER_CONT_temp_reg_0_ ( .D(n3164), .CK(clk), .RN(n6313), .Q(
cont_iter_out[0]), .QN(n5960) );
DFFRXLTS ITER_CONT_temp_reg_2_ ( .D(n3162), .CK(clk), .RN(n6313), .Q(
cont_iter_out[2]), .QN(n5928) );
DFFRXLTS ITER_CONT_temp_reg_3_ ( .D(n3161), .CK(clk), .RN(n6313), .Q(
cont_iter_out[3]), .QN(n3176) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(
n2081), .CK(clk), .RN(n6216), .Q(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .QN(n5897) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1736),
.CK(clk), .RN(n6229), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n6122) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1735),
.CK(clk), .RN(n6229), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n6121) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1734),
.CK(clk), .RN(n6229), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n6120) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1733),
.CK(clk), .RN(n6229), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n6119) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1732),
.CK(clk), .RN(n6229), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n6118) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1731),
.CK(clk), .RN(n6229), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n6117) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1730),
.CK(clk), .RN(n6229), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n6116) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1729),
.CK(clk), .RN(n6229), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n6115) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1726), .CK(clk), .RN(n6230), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]),
.QN(n6112) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1725), .CK(clk), .RN(n6230), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]),
.QN(n6111) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1724), .CK(clk), .RN(n6230), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]),
.QN(n6110) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1723), .CK(clk), .RN(n6230), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]),
.QN(n6109) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1722), .CK(clk), .RN(n6230), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]),
.QN(n6108) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1721), .CK(clk), .RN(n6230), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]),
.QN(n6107) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1720), .CK(clk), .RN(n6230), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]),
.QN(n6106) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1719), .CK(clk), .RN(n6230), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]),
.QN(n6105) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1718), .CK(clk), .RN(n6230), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]),
.QN(n6104) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1717), .CK(clk), .RN(n6230), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]),
.QN(n6103) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1716), .CK(clk), .RN(n6231), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]),
.QN(n6102) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1715), .CK(clk), .RN(n6231), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]),
.QN(n6101) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1714), .CK(clk), .RN(n6231), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]),
.QN(n6100) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1712), .CK(clk), .RN(n6231), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[26]),
.QN(n6098) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1711), .CK(clk), .RN(n6231), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[27]),
.QN(n6097) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1710), .CK(clk), .RN(n6231), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[28]),
.QN(n6096) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1709), .CK(clk), .RN(n6231), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[29]),
.QN(n6095) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n2049), .CK(clk), .RN(n6225), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[31]),
.QN(n6037) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n2046), .CK(clk), .RN(n6225), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]),
.QN(n6023) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n2034), .CK(clk), .RN(n6227), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[46]),
.QN(n5957) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n2030), .CK(clk), .RN(n6226), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]),
.QN(n5956) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n2048), .CK(clk), .RN(n6225), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[32]),
.QN(n5951) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n2040), .CK(clk), .RN(n6226), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40]),
.QN(n5939) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n2051), .CK(clk), .RN(n6225), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]),
.QN(n6024) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1868),
.CK(clk), .RN(n6234), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1900),
.CK(clk), .RN(n6236), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1738),
.CK(clk), .RN(n6228), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[0]), .QN(n6165) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n2001),
.CK(clk), .RN(n6237), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1831),
.CK(clk), .RN(n6237), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1727), .CK(clk), .RN(n6229), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]),
.QN(n6113) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1953),
.CK(clk), .RN(n6236), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]) );
ADDFX1TS DP_OP_33J12_122_5452_U11 ( .A(DP_OP_33J12_122_5452_n21), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]), .CI(
DP_OP_33J12_122_5452_n11), .CO(DP_OP_33J12_122_5452_n10), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_33J12_122_5452_U9 ( .A(DP_OP_33J12_122_5452_n19), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]), .CI(
DP_OP_33J12_122_5452_n9), .CO(DP_OP_33J12_122_5452_n8), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_33J12_122_5452_U7 ( .A(DP_OP_33J12_122_5452_n17), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]), .CI(
DP_OP_33J12_122_5452_n7), .CO(DP_OP_33J12_122_5452_n6), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]) );
ADDFX1TS DP_OP_33J12_122_5452_U3 ( .A(n3183), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[9]), .CI(
DP_OP_33J12_122_5452_n3), .CO(DP_OP_33J12_122_5452_n2), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[9]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n2035), .CK(clk), .RN(n6227), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n2031), .CK(clk), .RN(n6226), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[49])
);
ADDFX1TS DP_OP_33J12_122_5452_U8 ( .A(DP_OP_33J12_122_5452_n18), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]), .CI(
DP_OP_33J12_122_5452_n8), .CO(DP_OP_33J12_122_5452_n7), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_33J12_122_5452_U6 ( .A(n5897), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]), .C(
DP_OP_33J12_122_5452_n6), .CO(DP_OP_33J12_122_5452_n5), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_33J12_122_5452_U5 ( .A(n3183), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]), .C(
DP_OP_33J12_122_5452_n5), .CO(DP_OP_33J12_122_5452_n4), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS DP_OP_33J12_122_5452_U4 ( .A(n5897), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[8]), .C(
DP_OP_33J12_122_5452_n4), .CO(DP_OP_33J12_122_5452_n3), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[8]) );
AO22X1TS U3188 ( .A0(n3312), .A1(n4864), .B0(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM), .B1(n5872), .Y(n2082) );
XNOR2X1TS U3189 ( .A(n3307), .B(n6123), .Y(n3308) );
OR3X1TS U3190 ( .A(inst_CORDIC_FSM_v3_state_reg[7]), .B(n5903), .C(n3645),
.Y(n5496) );
CLKBUFX2TS U3191 ( .A(cont_iter_out[2]), .Y(n3180) );
OAI21XLTS U3192 ( .A0(n5026), .A1(n5041), .B0(n5027), .Y(n3227) );
INVX2TS U3193 ( .A(n3434), .Y(n3440) );
NOR2XLTS U3194 ( .A(n5935), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[57]),
.Y(n3386) );
INVX2TS U3195 ( .A(n3451), .Y(n3427) );
OAI211XLTS U3196 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .A1(
n6004), .B0(n3330), .C0(n3321), .Y(n3380) );
NOR2XLTS U3197 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[39]), .Y(n3536) );
NOR2XLTS U3198 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n3525) );
AOI211XLTS U3199 ( .A0(n3330), .A1(n3329), .B0(n3328), .C0(n3327), .Y(n3385)
);
NOR2XLTS U3200 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]),
.B(n5893), .Y(n4568) );
INVX2TS U3201 ( .A(n5756), .Y(n5755) );
NOR2XLTS U3202 ( .A(n5011), .B(n3290), .Y(n4985) );
CLKBUFX2TS U3203 ( .A(n4530), .Y(n3191) );
INVX2TS U3204 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[10]), .Y(
n5228) );
NOR2BX2TS U3205 ( .AN(n3489), .B(n3488), .Y(n4164) );
NOR2XLTS U3206 ( .A(n4320), .B(n5958), .Y(n3634) );
NOR2XLTS U3207 ( .A(n5249), .B(n5252), .Y(n3902) );
NAND2X1TS U3208 ( .A(n5959), .B(inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3640)
);
INVX2TS U3209 ( .A(n3544), .Y(n4181) );
AFHCINX2TS U3210 ( .CIN(n4887), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[37]),
.A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[39]), .S(n4888), .CO(
n4893) );
INVX2TS U3211 ( .A(n4681), .Y(n5160) );
INVX2TS U3212 ( .A(n5828), .Y(n5830) );
OAI211XLTS U3213 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]),
.A1(n3541), .B0(n4176), .C0(n3540), .Y(n3542) );
NOR3XLTS U3214 ( .A(n5228), .B(n5244), .C(n5227), .Y(n5229) );
NOR2X2TS U3215 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
n3544), .Y(n4166) );
NOR2XLTS U3216 ( .A(n3601), .B(n3600), .Y(n4358) );
INVX2TS U3217 ( .A(n4232), .Y(n4234) );
NOR2XLTS U3218 ( .A(n3624), .B(n3623), .Y(n4281) );
INVX2TS U3219 ( .A(n5439), .Y(n5442) );
INVX2TS U3220 ( .A(n5585), .Y(n5503) );
CLKBUFX2TS U3221 ( .A(n4203), .Y(n4225) );
CLKBUFX2TS U3222 ( .A(n4203), .Y(n4276) );
INVX2TS U3223 ( .A(n5585), .Y(n5582) );
INVX2TS U3224 ( .A(n5379), .Y(n3865) );
NOR2XLTS U3225 ( .A(d_ff2_Y[61]), .B(n5546), .Y(n5550) );
NAND2X1TS U3226 ( .A(cont_iter_out[0]), .B(n5938), .Y(intadd_24_CI) );
NOR2XLTS U3227 ( .A(cont_iter_out[0]), .B(n4298), .Y(n4113) );
NOR2XLTS U3228 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n3643) );
NOR2XLTS U3229 ( .A(n5899), .B(n5259), .Y(n5260) );
INVX2TS U3230 ( .A(n4057), .Y(n4135) );
INVX2TS U3231 ( .A(n5869), .Y(n5870) );
INVX2TS U3232 ( .A(n5241), .Y(n5866) );
INVX2TS U3233 ( .A(n4347), .Y(n4343) );
OR2X1TS U3234 ( .A(n5821), .B(n4118), .Y(n4013) );
INVX2TS U3235 ( .A(n4347), .Y(n5883) );
NOR2XLTS U3236 ( .A(n5216), .B(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .Y(
n5036) );
INVX2TS U3237 ( .A(n4347), .Y(n5825) );
INVX2TS U3238 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[9]), .Y(
n5244) );
NAND2X1TS U3239 ( .A(n3566), .B(n4331), .Y(n4332) );
INVX2TS U3240 ( .A(n3565), .Y(n4238) );
AOI31XLTS U3241 ( .A0(n5771), .A1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]), .A2(n5873),
.B0(n3568), .Y(n4335) );
OR2X1TS U3242 ( .A(n4320), .B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM),
.Y(n4185) );
INVX2TS U3243 ( .A(n5379), .Y(n5466) );
INVX2TS U3244 ( .A(n5435), .Y(n5486) );
INVX2TS U3245 ( .A(n5412), .Y(n5460) );
INVX2TS U3246 ( .A(n5435), .Y(n5372) );
INVX2TS U3247 ( .A(n5491), .Y(n5499) );
OR2X1TS U3248 ( .A(n4335), .B(n4232), .Y(n3210) );
INVX2TS U3249 ( .A(n5491), .Y(n5510) );
INVX2TS U3250 ( .A(n5412), .Y(n5513) );
INVX2TS U3251 ( .A(n5435), .Y(n5405) );
OR2X1TS U3252 ( .A(n5267), .B(n5518), .Y(n5423) );
INVX2TS U3253 ( .A(n5412), .Y(n5515) );
NOR2XLTS U3254 ( .A(n5262), .B(n5284), .Y(n5306) );
NOR2XLTS U3255 ( .A(n5305), .B(n4096), .Y(n5267) );
NAND2X1TS U3256 ( .A(n4112), .B(n5305), .Y(n5277) );
INVX2TS U3257 ( .A(n4080), .Y(n5873) );
OAI21XLTS U3258 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(
n4381), .Y(n5247) );
NAND2X1TS U3259 ( .A(n3643), .B(n3720), .Y(n3645) );
OAI211XLTS U3260 ( .A0(n3195), .A1(n4372), .B0(n4371), .C0(n4370), .Y(n2544)
);
OAI211XLTS U3261 ( .A0(n3195), .A1(n4362), .B0(n4361), .C0(n4360), .Y(n2524)
);
OAI211XLTS U3262 ( .A0(n3195), .A1(n4353), .B0(n4352), .C0(n4351), .Y(n2520)
);
OAI31X1TS U3263 ( .A0(n4103), .A1(n3905), .A2(n5295), .B0(n3646), .Y(n3117)
);
OAI31X1TS U3264 ( .A0(n5261), .A1(cont_var_out[1]), .A2(n5892), .B0(n4291),
.Y(n3159) );
INVX2TS U3265 ( .A(n5846), .Y(n3193) );
NOR3XLTS U3266 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(n5929), .C(n3645),
.Y(ready_cordic) );
OAI211XLTS U3267 ( .A0(n4290), .A1(n4280), .B0(n4279), .C0(n4278), .Y(n2549)
);
NOR2X1TS U3268 ( .A(n4232), .B(n4238), .Y(n3566) );
OAI2BB1X1TS U3269 ( .A0N(n5036), .A1N(n3310), .B0(n3309), .Y(n2183) );
OAI2BB1X1TS U3270 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[51]), .A1N(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[53]), .B0(n3244), .Y(
n3311) );
NOR2X1TS U3271 ( .A(n4319), .B(n4185), .Y(n3568) );
CLKINVX2TS U3272 ( .A(n4177), .Y(n3485) );
XOR2XLTS U3273 ( .A(n4872), .B(n4871), .Y(n4873) );
NAND2X2TS U3274 ( .A(n4166), .B(n3525), .Y(n4177) );
AFHCINX2TS U3275 ( .CIN(n4855), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[47]),
.A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[49]), .S(n4857), .CO(
n4872) );
XOR2XLTS U3276 ( .A(n4863), .B(n4862), .Y(n4865) );
OAI2BB2X2TS U3277 ( .B0(n4863), .B1(n3241), .A0N(n3200), .A1N(n6139), .Y(
n4855) );
AOI211X1TS U3278 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]),
.A1(n5900), .B0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]),
.C0(n3511), .Y(n4169) );
NAND2X2TS U3279 ( .A(n3529), .B(n5927), .Y(n3511) );
NOR2BX2TS U3280 ( .AN(n3543), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n3529) );
NOR2BX2TS U3281 ( .AN(n4168), .B(n4170), .Y(n3543) );
NAND3X2TS U3282 ( .A(n3509), .B(n4157), .C(n3519), .Y(n4170) );
CLKINVX2TS U3283 ( .A(n3500), .Y(n3509) );
OR2X2TS U3284 ( .A(n3747), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3500) );
AND2X2TS U3285 ( .A(n5829), .B(n5828), .Y(n5241) );
NOR2X1TS U3286 ( .A(n3546), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n3521) );
INVX1TS U3287 ( .A(n4155), .Y(n4156) );
CLKINVX2TS U3288 ( .A(n3490), .Y(n3493) );
NAND2BXLTS U3289 ( .AN(n3502), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]), .Y(n3541) );
NOR2X1TS U3290 ( .A(n5234), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[8]), .Y(n5235) );
CLKINVX2TS U3291 ( .A(n3491), .Y(n3492) );
NOR2X2TS U3292 ( .A(n3491), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[31]), .Y(n4154) );
NOR2X1TS U3293 ( .A(n3180), .B(n4099), .Y(n5272) );
NAND2X2TS U3294 ( .A(n3495), .B(n3479), .Y(n3491) );
INVX1TS U3295 ( .A(n5491), .Y(n3831) );
AND2X2TS U3296 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .B(
n5821), .Y(n3668) );
INVX1TS U3297 ( .A(n5491), .Y(n3829) );
NOR2X1TS U3298 ( .A(n5899), .B(n5269), .Y(n5307) );
NOR2X1TS U3299 ( .A(n5743), .B(n5250), .Y(n5691) );
NOR3X1TS U3300 ( .A(cont_var_out[0]), .B(n5984), .C(n5743), .Y(n5427) );
NOR3X1TS U3301 ( .A(cont_var_out[1]), .B(n5743), .C(n5892), .Y(n3835) );
NOR2X1TS U3302 ( .A(d_ff2_X[61]), .B(n5395), .Y(n5397) );
NOR2X2TS U3303 ( .A(n3503), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]), .Y(n3495) );
AOI211X1TS U3304 ( .A0(n3455), .A1(n3454), .B0(n3453), .C0(n3452), .Y(n5821)
);
AFHCINX2TS U3305 ( .CIN(n4952), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]),
.A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[31]), .S(n4953), .CO(
n4947) );
NAND2X2TS U3306 ( .A(n3554), .B(n3515), .Y(n3503) );
CLKINVX2TS U3307 ( .A(n5439), .Y(n5468) );
INVX1TS U3308 ( .A(n5423), .Y(n5420) );
INVX1TS U3309 ( .A(n5423), .Y(n5449) );
CLKINVX2TS U3310 ( .A(n5585), .Y(n5669) );
INVX1TS U3311 ( .A(n5370), .Y(n5742) );
NOR2X1TS U3312 ( .A(d_ff2_Y[59]), .B(n5542), .Y(n5544) );
NOR2X1TS U3313 ( .A(d_ff2_X[59]), .B(n5391), .Y(n5393) );
AND2X2TS U3314 ( .A(n5267), .B(n6246), .Y(n3843) );
NOR2X2TS U3315 ( .A(n3741), .B(n3209), .Y(n3554) );
NOR2X1TS U3316 ( .A(n3621), .B(n3620), .Y(n4368) );
NOR2X1TS U3317 ( .A(cont_iter_out[1]), .B(n5741), .Y(n5311) );
INVX1TS U3318 ( .A(n5379), .Y(n3886) );
NAND2X1TS U3319 ( .A(n3558), .B(n3204), .Y(n3741) );
INVX1TS U3320 ( .A(n5379), .Y(n3880) );
INVX1TS U3321 ( .A(n5379), .Y(n3875) );
INVX1TS U3322 ( .A(n5412), .Y(n5519) );
INVX1TS U3323 ( .A(n5412), .Y(n5749) );
INVX1TS U3324 ( .A(n4006), .Y(n5752) );
INVX1TS U3325 ( .A(n4295), .Y(n4211) );
CLKINVX2TS U3326 ( .A(n3902), .Y(n4292) );
NOR2X2TS U3327 ( .A(n3537), .B(n3478), .Y(n3558) );
INVX1TS U3328 ( .A(n4295), .Y(n5557) );
INVX1TS U3329 ( .A(n5249), .Y(n5251) );
NAND3X1TS U3330 ( .A(n3434), .B(n3443), .C(n3317), .Y(n3451) );
OAI21X1TS U3331 ( .A0(n3519), .A1(n3518), .B0(n3517), .Y(n3520) );
NOR3BX1TS U3332 ( .AN(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[4]), .C(n3721), .Y(n5252) );
INVX1TS U3333 ( .A(n4152), .Y(n3547) );
NOR3BX1TS U3334 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(n3721), .Y(n5249) );
INVX1TS U3335 ( .A(n4157), .Y(n3518) );
CLKBUFX2TS U3336 ( .A(n4577), .Y(n3192) );
NOR3X1TS U3337 ( .A(n4152), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]), .Y(n3477) );
XOR2X1TS U3338 ( .A(d_ff1_shift_region_flag_out[0]), .B(n3681), .Y(n5756) );
INVX1TS U3339 ( .A(n4347), .Y(n4345) );
OAI211X1TS U3340 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[60]), .A1(
n5931), .B0(n3396), .C0(n3392), .Y(n3398) );
INVX1TS U3341 ( .A(n5773), .Y(n3194) );
NOR2X1TS U3342 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[49]), .Y(n3533) );
NAND3X1TS U3343 ( .A(n5984), .B(n5892), .C(ready_add_subt), .Y(n5748) );
XOR2XLTS U3344 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[48]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]), .Y(n4862) );
NOR2X1TS U3345 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n4168) );
CLKAND2X2TS U3346 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[30]),
.B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .Y(n3236) );
INVX1TS U3347 ( .A(cont_iter_out[3]), .Y(n3184) );
NOR2X1TS U3348 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[36]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[35]), .Y(n3515) );
CLKAND2X2TS U3349 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[48]),
.B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]), .Y(n3241) );
NOR2X1TS U3350 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[32]), .Y(n3479) );
NOR2X1TS U3351 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n3519) );
NOR2X1TS U3352 ( .A(cont_iter_out[1]), .B(cont_iter_out[0]), .Y(n3905) );
NAND3X1TS U3353 ( .A(cont_var_out[1]), .B(ready_add_subt), .C(n5892), .Y(
n5336) );
NOR2X1TS U3354 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[46]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45]), .Y(n3531) );
NAND2XLTS U3355 ( .A(cont_iter_out[0]), .B(n5937), .Y(intadd_23_CI) );
NAND3X1TS U3356 ( .A(n5984), .B(cont_var_out[0]), .C(ready_add_subt), .Y(
n5577) );
NAND2BX1TS U3357 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[59]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .Y(n3388) );
NAND2BX1TS U3358 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[62]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .Y(n3396) );
AFHCINX2TS U3359 ( .CIN(n4854), .B(n6146), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[47]), .S(n4859), .CO(n4870) );
AFHCINX4TS U3360 ( .CIN(n4908), .B(n6156), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[35]), .S(n4914), .CO(n4916) );
AFHCINX4TS U3361 ( .CIN(n4876), .B(n6147), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[45]), .S(n4880), .CO(n4861) );
OAI22X2TS U3362 ( .A0(n4872), .A1(n3242), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[50]), .Y(n4837) );
OAI21X1TS U3363 ( .A0(n5198), .A1(n5208), .B0(n5199), .Y(n5103) );
NOR2X2TS U3364 ( .A(n3490), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[27]), .Y(n4155) );
OR3X4TS U3365 ( .A(n3502), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]), .Y(n3490) );
OAI211X1TS U3366 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]),
.A1(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n3485), .C0(
n3484), .Y(n3489) );
NOR4X2TS U3367 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .C(n3511), .D(n3481), .Y(n4160) );
NOR2XLTS U3368 ( .A(n5173), .B(n5156), .Y(n3214) );
NAND2X1TS U3369 ( .A(n3521), .B(n5923), .Y(n3747) );
AND3X1TS U3370 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(n5225), .Y(n5226) );
AND3X1TS U3371 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .C(n5224), .Y(n5225) );
AND3X1TS U3372 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n5224) );
NOR2XLTS U3373 ( .A(n4686), .B(n3262), .Y(n3264) );
NAND2X1TS U3374 ( .A(n3208), .B(n3533), .Y(n3501) );
OAI21XLTS U3375 ( .A0(n4752), .A1(n4810), .B0(n4753), .Y(n3225) );
NOR2XLTS U3376 ( .A(n6102), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .Y(
n3282) );
OAI21XLTS U3377 ( .A0(n3278), .A1(n4806), .B0(n3277), .Y(n3279) );
NOR2XLTS U3378 ( .A(n5069), .B(n3268), .Y(n3270) );
NOR2XLTS U3379 ( .A(n5013), .B(n4999), .Y(n4993) );
OR2X1TS U3380 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[28]), .Y(n4989) );
OAI21XLTS U3381 ( .A0(n3292), .A1(n4986), .B0(n3291), .Y(n3293) );
NAND2X1TS U3382 ( .A(n3476), .B(n3475), .Y(n3506) );
NOR2XLTS U3383 ( .A(n4726), .B(n3222), .Y(n3224) );
OAI21XLTS U3384 ( .A0(n4725), .A1(n3222), .B0(n3221), .Y(n3223) );
NAND4BXLTS U3385 ( .AN(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]),
.B(n5233), .C(n5242), .D(n5232), .Y(n5234) );
NOR2XLTS U3386 ( .A(n5231), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(n5233) );
NAND4BXLTS U3387 ( .AN(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]),
.B(n5239), .C(n5240), .D(n5230), .Y(n5231) );
OAI31X1TS U3388 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .A2(n3526), .B0(
n3525), .Y(n3530) );
XNOR2X1TS U3389 ( .A(DP_OP_33J12_122_5452_n1), .B(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5238) );
XOR2XLTS U3390 ( .A(n5897), .B(n4378), .Y(DP_OP_33J12_122_5452_n20) );
AOI31XLTS U3391 ( .A0(n4153), .A1(n3547), .A2(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]), .B0(n3743), .Y(
n3548) );
CLKAND2X2TS U3392 ( .A(n6143), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]),
.Y(n3303) );
CLKAND2X2TS U3393 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[36]),
.B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]), .Y(n3238) );
NOR2XLTS U3394 ( .A(n4809), .B(n4752), .Y(n3226) );
NOR2XLTS U3395 ( .A(n4690), .B(n4704), .Y(n3218) );
NAND2BXLTS U3396 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .Y(n3368) );
NAND2BXLTS U3397 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .Y(n3323) );
NAND2BXLTS U3398 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .Y(n3348) );
OAI211XLTS U3399 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .A1(
n5975), .B0(n3358), .C0(n3332), .Y(n3362) );
NAND2BXLTS U3400 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .Y(n3332) );
OAI211XLTS U3401 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .A1(
n5974), .B0(n3377), .C0(n3331), .Y(n3371) );
NAND2BXLTS U3402 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .Y(n3331) );
OAI21XLTS U3403 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .A1(n5991), .B0(n3368), .Y(n3372) );
NOR2XLTS U3404 ( .A(n6095), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .Y(
n3296) );
NOR2XLTS U3405 ( .A(n4736), .B(n4738), .Y(n3220) );
OAI21XLTS U3406 ( .A0(n4795), .A1(n5055), .B0(n4796), .Y(n4757) );
NOR2XLTS U3407 ( .A(n4799), .B(n4795), .Y(n4758) );
NOR2XLTS U3408 ( .A(n6106), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .Y(
n3276) );
NOR2XLTS U3409 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n4799) );
OAI21XLTS U3410 ( .A0(n3268), .A1(n5070), .B0(n3267), .Y(n3269) );
NOR2XLTS U3411 ( .A(n6110), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .Y(
n3266) );
NOR2XLTS U3412 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n4722) );
OAI21XLTS U3413 ( .A0(n3262), .A1(n4687), .B0(n3261), .Y(n3263) );
NOR2XLTS U3414 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n4690) );
OAI21XLTS U3415 ( .A0(n5134), .A1(n5147), .B0(n5135), .Y(n4695) );
NOR2XLTS U3416 ( .A(n5146), .B(n5134), .Y(n4694) );
NOR2XLTS U3417 ( .A(n6118), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .Y(
n3252) );
AOI211XLTS U3418 ( .A0(n4513), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .B0(n4492), .C0(n4487), .Y(n4603) );
NAND4BXLTS U3419 ( .AN(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]),
.B(n3509), .C(n4157), .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n3486) );
AOI211XLTS U3420 ( .A0(n4512), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[51]), .B0(n4493), .C0(n4492), .Y(n4613) );
NOR2XLTS U3421 ( .A(n3551), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]), .Y(n3552) );
AOI2BB1XLTS U3422 ( .A0N(n3550), .A1N(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[52]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[53]), .Y(n3551) );
OAI21XLTS U3423 ( .A0(n3284), .A1(n5037), .B0(n3283), .Y(n3285) );
NOR2XLTS U3424 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[27]), .Y(n4999) );
OAI21XLTS U3425 ( .A0(n3290), .A1(n5010), .B0(n3289), .Y(n4984) );
INVX2TS U3426 ( .A(n4756), .Y(n5060) );
OAI21XLTS U3427 ( .A0(n5083), .A1(n5088), .B0(n5084), .Y(n4732) );
NOR2XLTS U3428 ( .A(n4722), .B(n5083), .Y(n4731) );
NOR2XLTS U3429 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n5083) );
OAI211XLTS U3430 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .A1(
n6001), .B0(n3425), .C0(n3414), .Y(n3416) );
NAND2BXLTS U3431 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[32]), .Y(n3318) );
NOR2XLTS U3432 ( .A(n3433), .B(n3432), .Y(n3446) );
AOI211XLTS U3433 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .A1(
n3413), .B0(n3412), .C0(n3411), .Y(n3450) );
NAND4XLTS U3434 ( .A(n3407), .B(n3405), .C(n3314), .D(n3313), .Y(n3449) );
NAND2BXLTS U3435 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[40]), .Y(n3313) );
NAND2BXLTS U3436 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[41]), .Y(n3314) );
NAND2BXLTS U3437 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[62]), .Y(n3394) );
NAND3XLTS U3438 ( .A(n5931), .B(n3392), .C(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[60]), .Y(n3393) );
AOI211XLTS U3439 ( .A0(n3377), .A1(n3376), .B0(n3375), .C0(n3374), .Y(n3383)
);
NAND3XLTS U3440 ( .A(n3532), .B(n3208), .C(n5934), .Y(n3534) );
OAI21XLTS U3441 ( .A0(n3516), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]), .B0(n3515), .Y(
n3522) );
XOR2X1TS U3442 ( .A(n3183), .B(n3656), .Y(DP_OP_33J12_122_5452_n22) );
OR2X1TS U3443 ( .A(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3656) );
OAI21XLTS U3444 ( .A0(n5003), .A1(n4987), .B0(n4986), .Y(n4991) );
NOR2X1TS U3445 ( .A(n3789), .B(n5756), .Y(n3761) );
XOR2XLTS U3446 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[50]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]), .Y(n4871) );
NAND3BXLTS U3447 ( .AN(n3898), .B(inst_CORDIC_FSM_v3_state_reg[0]), .C(n5950), .Y(n5248) );
NAND4XLTS U3448 ( .A(n4394), .B(n4393), .C(n4392), .D(n4391), .Y(n4678) );
CLKBUFX2TS U3449 ( .A(n3668), .Y(n4057) );
AOI31XLTS U3450 ( .A0(n4172), .A1(n5926), .A2(n4171), .B0(n4170), .Y(n4180)
);
OAI211XLTS U3451 ( .A0(n3512), .A1(n3511), .B0(n4163), .C0(n3510), .Y(n5223)
);
XNOR2X1TS U3452 ( .A(n4850), .B(n4849), .Y(n4851) );
CLKAND2X2TS U3453 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[50]),
.B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]), .Y(n3242) );
OAI22X2TS U3454 ( .A0(n4861), .A1(n3304), .B0(n6139), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]), .Y(n4854) );
CLKAND2X2TS U3455 ( .A(n6139), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]),
.Y(n3304) );
OAI22X1TS U3456 ( .A0(n4826), .A1(n3240), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[46]), .Y(n4877) );
CLKAND2X2TS U3457 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[46]),
.B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]), .Y(n3240) );
AFHCINX2TS U3458 ( .CIN(n4820), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[43]),
.A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[45]), .S(n4821), .CO(
n4826) );
OAI22X1TS U3459 ( .A0(n4832), .A1(n3239), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[44]), .Y(n4820) );
CLKAND2X2TS U3460 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[44]),
.B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]), .Y(n3239) );
ACHCINX2TS U3461 ( .CIN(n4904), .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[39]),
.B(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[41]), .CO(n4898) );
CLKAND2X2TS U3462 ( .A(n6144), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]),
.Y(n3302) );
CLKAND2X2TS U3463 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[34]),
.B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]), .Y(n3237) );
OAI21X1TS U3464 ( .A0(n4756), .A1(n3235), .B0(n3234), .Y(n4958) );
NOR2XLTS U3465 ( .A(n4975), .B(n4968), .Y(n3233) );
NAND2BX1TS U3466 ( .AN(n5238), .B(n5237), .Y(n5828) );
NOR2BX1TS U3467 ( .AN(n5236), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[10]), .Y(n5237) );
AOI21X1TS U3468 ( .A0(n5238), .A1(n5229), .B0(n5875), .Y(n5829) );
NAND3BX1TS U3469 ( .AN(n5243), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[8]), .C(n5226), .Y(n5227) );
XOR2XLTS U3470 ( .A(n5897), .B(n4376), .Y(DP_OP_33J12_122_5452_n18) );
NOR2XLTS U3471 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[56]), .B(n5763),
.Y(n5766) );
OAI21XLTS U3472 ( .A0(n6036), .A1(n4211), .B0(n4208), .Y(n4235) );
OAI21XLTS U3473 ( .A0(n6024), .A1(n4211), .B0(n4210), .Y(n4244) );
NOR2XLTS U3474 ( .A(n5874), .B(n5554), .Y(n4183) );
NAND4XLTS U3475 ( .A(n4164), .B(n4163), .C(n4162), .D(n4161), .Y(n4165) );
OAI21XLTS U3476 ( .A0(n5952), .A1(n4211), .B0(n3583), .Y(n4328) );
AOI2BB1XLTS U3477 ( .A0N(n4071), .A1N(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(n3589), .Y(
n4255) );
OAI21XLTS U3478 ( .A0(n5951), .A1(n4294), .B0(n3590), .Y(n4246) );
OAI21XLTS U3479 ( .A0(n6023), .A1(n4211), .B0(n3595), .Y(n4256) );
OAI21XLTS U3480 ( .A0(n6031), .A1(n4211), .B0(n3603), .Y(n4354) );
OAI21XLTS U3481 ( .A0(n6030), .A1(n4211), .B0(n3602), .Y(n4251) );
OAI21XLTS U3482 ( .A0(n5932), .A1(n4294), .B0(n3570), .Y(n4226) );
OAI21XLTS U3483 ( .A0(n5926), .A1(n4294), .B0(n3575), .Y(n4349) );
CLKAND2X2TS U3484 ( .A(n4085), .B(n4084), .Y(n4339) );
NOR2XLTS U3485 ( .A(n4080), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n4081) );
OAI21XLTS U3486 ( .A0(n5947), .A1(n4294), .B0(n3567), .Y(n4224) );
NAND3XLTS U3487 ( .A(n3196), .B(n5265), .C(n3184), .Y(n5299) );
AO21XLTS U3488 ( .A0(n5960), .A1(n3184), .B0(n5312), .Y(n4108) );
NAND4XLTS U3489 ( .A(n5311), .B(n5960), .C(n4112), .D(n5305), .Y(n5291) );
XNOR2X1TS U3490 ( .A(n3311), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[54]), .Y(n3310) );
AOI22X1TS U3491 ( .A0(n3308), .A1(n5215), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]), .B1(n4856), .Y(
n3309) );
NAND3XLTS U3492 ( .A(n5969), .B(n3348), .C(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .Y(n3349) );
NOR2XLTS U3493 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .B(n3346),
.Y(n3347) );
NOR2XLTS U3494 ( .A(n4807), .B(n3278), .Y(n3280) );
NOR2XLTS U3495 ( .A(n6112), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .Y(
n3262) );
OAI21XLTS U3496 ( .A0(n5156), .A1(n5174), .B0(n5157), .Y(n3213) );
NAND2BXLTS U3497 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[51]), .Y(n3437) );
NAND2X1TS U3498 ( .A(n4155), .B(n5898), .Y(n3546) );
NOR2XLTS U3499 ( .A(n5951), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .Y(n3514) );
INVX2TS U3500 ( .A(n3502), .Y(n3494) );
NOR2XLTS U3501 ( .A(n6100), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .Y(
n3284) );
NOR2XLTS U3502 ( .A(n5038), .B(n3284), .Y(n3286) );
OAI21XLTS U3503 ( .A0(n4738), .A1(n5073), .B0(n4739), .Y(n3219) );
NOR2XLTS U3504 ( .A(n5040), .B(n5026), .Y(n3228) );
NOR2XLTS U3505 ( .A(n6098), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .Y(
n3290) );
OAI21XLTS U3506 ( .A0(n4767), .A1(n4784), .B0(n4768), .Y(n5023) );
NOR2XLTS U3507 ( .A(n4783), .B(n4767), .Y(n5024) );
NOR2XLTS U3508 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n4736) );
OAI21XLTS U3509 ( .A0(n4704), .A1(n4708), .B0(n4705), .Y(n3217) );
NOR2XLTS U3510 ( .A(n6114), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .Y(
n3260) );
NOR2XLTS U3511 ( .A(n6116), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .Y(
n3254) );
NOR2XLTS U3512 ( .A(n5172), .B(n3254), .Y(n3256) );
OAI21XLTS U3513 ( .A0(n5184), .A1(n5189), .B0(n5185), .Y(n5161) );
NOR2XLTS U3514 ( .A(n5125), .B(n5184), .Y(n5162) );
NOR2XLTS U3515 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n5125) );
OAI21XLTS U3516 ( .A0(n5109), .A1(n5113), .B0(n5110), .Y(n3211) );
NOR2XLTS U3517 ( .A(n6009), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]),
.Y(n3435) );
AOI2BB2XLTS U3518 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .B1(
n6003), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .A1N(n3431),
.Y(n3433) );
NAND3XLTS U3519 ( .A(n6001), .B(n3414), .C(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .Y(n3415) );
NAND2BXLTS U3520 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[47]), .Y(n3399) );
AOI211XLTS U3521 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[44]), .A1(
n6080), .B0(n3400), .C0(n3409), .Y(n3407) );
OAI21XLTS U3522 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[58]), .A1(n5905), .B0(n3388), .Y(n3390) );
NOR2XLTS U3523 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B(n3378),
.Y(n3322) );
NOR2XLTS U3524 ( .A(n3366), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]),
.Y(n3367) );
NAND2BXLTS U3525 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .Y(n3321) );
OAI21XLTS U3526 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .A1(n5980), .B0(n3323), .Y(n3381) );
NAND3BXLTS U3527 ( .AN(n3371), .B(n3364), .C(n3363), .Y(n3384) );
AOI211XLTS U3528 ( .A0(n4503), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .B0(n4492), .C0(n4478), .Y(n4595) );
AOI2BB1XLTS U3529 ( .A0N(n4477), .A1N(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[54]), .B0(n4415), .Y(n4534)
);
OAI21XLTS U3530 ( .A0(n6021), .A1(n4458), .B0(n4457), .Y(n4459) );
OAI21XLTS U3531 ( .A0(n5921), .A1(n4476), .B0(n4432), .Y(n4433) );
NAND3XLTS U3532 ( .A(n5903), .B(n3643), .C(n5929), .Y(n3650) );
OAI21XLTS U3533 ( .A0(n4603), .A1(n4612), .B0(n4602), .Y(n4617) );
OAI21XLTS U3534 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]),
.A1(n3514), .B0(n3504), .Y(n3505) );
INVX2TS U3535 ( .A(n3503), .Y(n3504) );
INVX2TS U3536 ( .A(n3501), .Y(n3507) );
OAI21XLTS U3537 ( .A0(n4965), .A1(n3296), .B0(n3295), .Y(n3297) );
NOR2XLTS U3538 ( .A(n4748), .B(n3288), .Y(n4963) );
NOR2XLTS U3539 ( .A(n4964), .B(n3296), .Y(n3298) );
OAI21XLTS U3540 ( .A0(n4976), .A1(n4968), .B0(n4969), .Y(n3232) );
NOR2XLTS U3541 ( .A(n4771), .B(n3230), .Y(n4974) );
NOR2XLTS U3542 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[26]), .Y(n5013) );
NOR2XLTS U3543 ( .A(n6099), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .Y(
n5011) );
NOR2XLTS U3544 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n5026) );
NOR2XLTS U3545 ( .A(n6101), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .Y(
n5038) );
INVX2TS U3546 ( .A(n4771), .Y(n4774) );
INVX2TS U3547 ( .A(n4772), .Y(n4773) );
OAI21XLTS U3548 ( .A0(n3282), .A1(n4780), .B0(n3281), .Y(n4764) );
NOR2XLTS U3549 ( .A(n4781), .B(n3282), .Y(n4765) );
NOR2XLTS U3550 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n4783) );
NOR2XLTS U3551 ( .A(n6103), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .Y(
n4781) );
NOR2XLTS U3552 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n4752) );
NOR2XLTS U3553 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n4795) );
OAI21XLTS U3554 ( .A0(n3276), .A1(n5051), .B0(n3275), .Y(n4793) );
NOR2XLTS U3555 ( .A(n5050), .B(n3276), .Y(n4794) );
NOR2XLTS U3556 ( .A(n4703), .B(n3272), .Y(n3274) );
OAI21XLTS U3557 ( .A0(n4702), .A1(n3272), .B0(n3271), .Y(n3273) );
NOR2XLTS U3558 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n4738) );
NOR2XLTS U3559 ( .A(n6109), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .Y(
n5069) );
OAI21XLTS U3560 ( .A0(n5152), .A1(n4726), .B0(n4725), .Y(n5091) );
OAI21XLTS U3561 ( .A0(n3266), .A1(n4718), .B0(n3265), .Y(n5065) );
NOR2XLTS U3562 ( .A(n4717), .B(n3266), .Y(n5064) );
NOR2XLTS U3563 ( .A(n6111), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .Y(
n4717) );
NOR2XLTS U3564 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n4704) );
OAI21XLTS U3565 ( .A0(n5152), .A1(n4697), .B0(n4696), .Y(n4711) );
NOR2XLTS U3566 ( .A(n6113), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .Y(
n4686) );
NOR2XLTS U3567 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n5134) );
NOR2XLTS U3568 ( .A(n5145), .B(n3260), .Y(n4682) );
NOR2XLTS U3569 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n5146) );
INVX2TS U3570 ( .A(n4693), .Y(n5152) );
NOR2XLTS U3571 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n5156) );
NOR2XLTS U3572 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n5173) );
NOR2XLTS U3573 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n5184) );
NOR2XLTS U3574 ( .A(n5121), .B(n3252), .Y(n5169) );
OAI21XLTS U3575 ( .A0(n3252), .A1(n5122), .B0(n3251), .Y(n5168) );
INVX2TS U3576 ( .A(n5128), .Y(n5192) );
NOR2XLTS U3577 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n5109) );
NOR2XLTS U3578 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n5114) );
NOR2XLTS U3579 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n5198) );
OAI21XLTS U3580 ( .A0(n4583), .A1(n4612), .B0(n4582), .Y(n4623) );
OAI211XLTS U3581 ( .A0(n4561), .A1(n4570), .B0(n4560), .C0(n4577), .Y(n4630)
);
OAI21XLTS U3582 ( .A0(n4574), .A1(n4612), .B0(n4573), .Y(n4625) );
OAI211XLTS U3583 ( .A0(n4571), .A1(n4570), .B0(n4569), .C0(n3192), .Y(n4628)
);
NAND4XLTS U3584 ( .A(n4529), .B(n4528), .C(n4527), .D(n3192), .Y(n4643) );
NAND4XLTS U3585 ( .A(n4501), .B(n4500), .C(n4499), .D(n4577), .Y(n4649) );
NAND4XLTS U3586 ( .A(n4519), .B(n4518), .C(n4517), .D(n4577), .Y(n4645) );
AOI2BB2XLTS U3587 ( .B0(n4543), .B1(n4587), .A0N(n4589), .A1N(n4580), .Y(
n4517) );
NAND4XLTS U3588 ( .A(n4496), .B(n4495), .C(n4494), .D(n3192), .Y(n4651) );
NAND4XLTS U3589 ( .A(n4509), .B(n4508), .C(n4507), .D(n3192), .Y(n4647) );
NAND4XLTS U3590 ( .A(n4475), .B(n4474), .C(n4473), .D(n3192), .Y(n4655) );
NAND4XLTS U3591 ( .A(n4486), .B(n4485), .C(n4484), .D(n4577), .Y(n4653) );
NAND4XLTS U3592 ( .A(n4449), .B(n4448), .C(n4447), .D(n4446), .Y(n4664) );
NAND4XLTS U3593 ( .A(n4456), .B(n4455), .C(n4454), .D(n4577), .Y(n4661) );
NAND4XLTS U3594 ( .A(n4466), .B(n4465), .C(n4464), .D(n4577), .Y(n4657) );
OAI211XLTS U3595 ( .A0(n4438), .A1(n4542), .B0(n4429), .C0(n4428), .Y(n4430)
);
NAND4XLTS U3596 ( .A(n4423), .B(n4422), .C(n4421), .D(n4420), .Y(n4670) );
OAI211XLTS U3597 ( .A0(n4438), .A1(n4537), .B0(n4437), .C0(n4436), .Y(n4439)
);
NAND4XLTS U3598 ( .A(n4414), .B(n4413), .C(n4412), .D(n4411), .Y(n4672) );
NAND2X1TS U3599 ( .A(n3531), .B(n3206), .Y(n4152) );
NOR2XLTS U3600 ( .A(n3545), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]), .Y(n4153) );
INVX2TS U3601 ( .A(n3553), .Y(n3545) );
CLKBUFX2TS U3602 ( .A(n4006), .Y(n5374) );
NAND3XLTS U3603 ( .A(n3720), .B(n5903), .C(n5929), .Y(n3721) );
INVX2TS U3604 ( .A(n4968), .Y(n4970) );
XOR2XLTS U3605 ( .A(n4980), .B(n4979), .Y(n4981) );
INVX2TS U3606 ( .A(n4975), .Y(n4978) );
INVX2TS U3607 ( .A(n4976), .Y(n4977) );
INVX2TS U3608 ( .A(n4964), .Y(n4967) );
NOR2X1TS U3609 ( .A(n3789), .B(n5755), .Y(n3796) );
NAND2BXLTS U3610 ( .AN(n3640), .B(n3641), .Y(n3644) );
NAND3BXLTS U3611 ( .AN(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[1]), .C(n3641), .Y(n3899) );
XOR2XLTS U3612 ( .A(n4937), .B(n4936), .Y(n4938) );
XOR2XLTS U3613 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[34]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]), .Y(n4936) );
OAI22X2TS U3614 ( .A0(n4958), .A1(n3236), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[30]), .Y(n4952) );
NAND4XLTS U3615 ( .A(n4405), .B(n4404), .C(n4403), .D(n4402), .Y(n4674) );
MXI2XLTS U3616 ( .A(n4672), .B(n4671), .S0(n4676), .Y(n5867) );
MXI2XLTS U3617 ( .A(n4670), .B(n4669), .S0(n4676), .Y(n5865) );
MXI2XLTS U3618 ( .A(n4668), .B(n4667), .S0(n4676), .Y(n5864) );
MXI2XLTS U3619 ( .A(n4664), .B(n4663), .S0(n4676), .Y(n5859) );
OAI21XLTS U3620 ( .A0(n4613), .A1(n4612), .B0(n4611), .Y(n4614) );
MXI2XLTS U3621 ( .A(n4618), .B(n4617), .S0(n4636), .Y(n5855) );
MXI2XLTS U3622 ( .A(n4620), .B(n4619), .S0(n4636), .Y(n5852) );
MXI2XLTS U3623 ( .A(n4619), .B(n4620), .S0(n4609), .Y(n5851) );
MXI2XLTS U3624 ( .A(n4617), .B(n4618), .S0(n4609), .Y(n5850) );
MXI2XLTS U3625 ( .A(n4622), .B(n4621), .S0(n4636), .Y(n5849) );
MXI2XLTS U3626 ( .A(n4647), .B(n4646), .S0(n4659), .Y(n5848) );
INVX2TS U3627 ( .A(n5241), .Y(n5863) );
MXI2XLTS U3628 ( .A(n4651), .B(n4650), .S0(n4659), .Y(n5847) );
CLKBUFX2TS U3629 ( .A(n3668), .Y(n4038) );
MXI2XLTS U3630 ( .A(n4624), .B(n4623), .S0(n4636), .Y(n5845) );
MXI2XLTS U3631 ( .A(n4653), .B(n4652), .S0(n4659), .Y(n5842) );
MXI2XLTS U3632 ( .A(n4626), .B(n4625), .S0(n4636), .Y(n5841) );
MXI2XLTS U3633 ( .A(n4661), .B(n4660), .S0(n4659), .Y(n5840) );
MXI2XLTS U3634 ( .A(n4657), .B(n4656), .S0(n4659), .Y(n5839) );
MXI2XLTS U3635 ( .A(n4655), .B(n4654), .S0(n4659), .Y(n5837) );
MXI2XLTS U3636 ( .A(n4649), .B(n4648), .S0(n4659), .Y(n5835) );
MXI2XLTS U3637 ( .A(n4634), .B(n4633), .S0(n4636), .Y(n5834) );
MXI2XLTS U3638 ( .A(n4630), .B(n4629), .S0(n4636), .Y(n5833) );
INVX2TS U3639 ( .A(n5241), .Y(n5844) );
MXI2XLTS U3640 ( .A(n4628), .B(n4627), .S0(n4636), .Y(n5832) );
NAND4X1TS U3641 ( .A(n3561), .B(n3560), .C(n4175), .D(n3559), .Y(n3562) );
NAND3BXLTS U3642 ( .AN(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[38]),
.B(n3558), .C(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[37]), .Y(
n3559) );
OAI2BB1X1TS U3643 ( .A0N(n6125), .A1N(n3201), .B0(n4848), .Y(n3243) );
CLKAND2X2TS U3644 ( .A(n6138), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]),
.Y(n3305) );
XOR2XLTS U3645 ( .A(n6139), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]), .Y(
n4860) );
AFHCINX2TS U3646 ( .CIN(n4881), .B(n6149), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[41]), .S(n4885), .CO(n4830) );
AFHCINX2TS U3647 ( .CIN(n4882), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[41]),
.A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[43]), .S(n4883), .CO(
n4832) );
CLKAND2X2TS U3648 ( .A(n6153), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]),
.Y(n3301) );
AFHCINX2TS U3649 ( .CIN(n4942), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[31]),
.A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[33]), .S(n4943), .CO(
n4937) );
AFHCINX2TS U3650 ( .CIN(n4941), .B(n6158), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[31]), .S(n4945), .CO(n4935) );
INVX2TS U3651 ( .A(n4999), .Y(n5001) );
OAI21XLTS U3652 ( .A0(n5046), .A1(n5040), .B0(n5041), .Y(n5029) );
XOR2XLTS U3653 ( .A(n5046), .B(n5045), .Y(n5047) );
OAI21XLTS U3654 ( .A0(n5039), .A1(n5038), .B0(n5037), .Y(n5044) );
OAI21XLTS U3655 ( .A0(n4788), .A1(n4783), .B0(n4784), .Y(n4776) );
OAI21XLTS U3656 ( .A0(n4815), .A1(n4809), .B0(n4810), .Y(n4760) );
XOR2XLTS U3657 ( .A(n4815), .B(n4814), .Y(n4816) );
XOR2XLTS U3658 ( .A(n4802), .B(n4801), .Y(n4803) );
INVX2TS U3659 ( .A(n4731), .Y(n4734) );
XOR2XLTS U3660 ( .A(n4735), .B(n4727), .Y(n4728) );
XOR2XLTS U3661 ( .A(n4713), .B(n4712), .Y(n4714) );
OAI221XLTS U3662 ( .A0(n3451), .A1(n3450), .B0(n3449), .B1(n3448), .C0(n3447), .Y(n3452) );
MXI2XLTS U3663 ( .A(n4643), .B(n4642), .S0(n4659), .Y(n5817) );
MXI2XLTS U3664 ( .A(n4623), .B(n4624), .S0(n4609), .Y(n5813) );
MXI2XLTS U3665 ( .A(n4641), .B(n4640), .S0(n4659), .Y(n5812) );
MXI2XLTS U3666 ( .A(n4629), .B(n4630), .S0(n4609), .Y(n5811) );
MXI2XLTS U3667 ( .A(n4632), .B(n4631), .S0(n4636), .Y(n5810) );
MXI2XLTS U3668 ( .A(n4625), .B(n4626), .S0(n4609), .Y(n5809) );
MXI2XLTS U3669 ( .A(n4638), .B(n4637), .S0(n4636), .Y(n5808) );
MXI2XLTS U3670 ( .A(n4645), .B(n4644), .S0(n4659), .Y(n5807) );
MXI2XLTS U3671 ( .A(n4627), .B(n4628), .S0(n4609), .Y(n5806) );
INVX2TS U3672 ( .A(n5241), .Y(n5816) );
MXI2XLTS U3673 ( .A(n4621), .B(n4622), .S0(n4609), .Y(n5805) );
MXI2XLTS U3674 ( .A(n4637), .B(n4638), .S0(n4609), .Y(n5793) );
INVX2TS U3675 ( .A(n5241), .Y(n5802) );
MXI2XLTS U3676 ( .A(n4633), .B(n4634), .S0(n4609), .Y(n5788) );
MXI2XLTS U3677 ( .A(n4666), .B(n4665), .S0(n4676), .Y(n5787) );
MXI2XLTS U3678 ( .A(n4631), .B(n4632), .S0(n4609), .Y(n5785) );
AOI211XLTS U3679 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]),
.A1(n3543), .B0(n3749), .C0(n3542), .Y(n4319) );
OAI2BB1X1TS U3680 ( .A0N(n6124), .A1N(n3202), .B0(n4842), .Y(n3244) );
CLKBUFX2TS U3681 ( .A(n4013), .Y(n4016) );
XOR2XLTS U3682 ( .A(n3183), .B(n4375), .Y(DP_OP_33J12_122_5452_n17) );
XOR2XLTS U3683 ( .A(n3183), .B(n4377), .Y(DP_OP_33J12_122_5452_n19) );
XOR2XLTS U3684 ( .A(n3183), .B(n4379), .Y(DP_OP_33J12_122_5452_n21) );
OAI21XLTS U3685 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56]), .A1(
intadd_22_n1), .B0(n5762), .Y(n5763) );
AND2X2TS U3686 ( .A(n4292), .B(n5247), .Y(n5585) );
CLKBUFX2TS U3687 ( .A(n5423), .Y(n5380) );
CLKBUFX2TS U3688 ( .A(n5380), .Y(n5491) );
NAND3XLTS U3689 ( .A(cont_iter_out[1]), .B(n3196), .C(n5268), .Y(n5296) );
CLKBUFX2TS U3690 ( .A(n4006), .Y(n5369) );
CLKBUFX2TS U3691 ( .A(n5369), .Y(n5370) );
NAND2X1TS U3692 ( .A(n5260), .B(n5262), .Y(n3931) );
MXI2XLTS U3693 ( .A(n5847), .B(n6113), .S0(n4658), .Y(n1727) );
MXI2XLTS U3694 ( .A(n5852), .B(n6099), .S0(n4635), .Y(n1713) );
MXI2XLTS U3695 ( .A(n5842), .B(n6114), .S0(n4658), .Y(n1728) );
XOR2XLTS U3696 ( .A(n4995), .B(n4994), .Y(n4996) );
MXI2XLTS U3697 ( .A(n4679), .B(n6165), .S0(n5772), .Y(n1738) );
MXI2XLTS U3698 ( .A(n4678), .B(n4677), .S0(n4676), .Y(n4679) );
OAI21XLTS U3699 ( .A0(beg_fsm_cordic), .A1(n5248), .B0(n3903), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
OAI21XLTS U3700 ( .A0(n4186), .A1(n4185), .B0(n4184), .Y(n3038) );
OAI21XLTS U3701 ( .A0(n4296), .A1(n5940), .B0(n3513), .Y(n3041) );
OAI21XLTS U3702 ( .A0(n4322), .A1(n4185), .B0(n3752), .Y(n3039) );
AOI2BB1XLTS U3703 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]),
.A1N(overflow_flag), .B0(n5829), .Y(n2184) );
OAI21XLTS U3704 ( .A0(n4296), .A1(n6020), .B0(n4206), .Y(n2559) );
OAI211XLTS U3705 ( .A0(n4267), .A1(n4214), .B0(n4188), .C0(n4187), .Y(n2551)
);
XOR2XLTS U3706 ( .A(n4892), .B(n4891), .Y(n4896) );
XNOR2X1TS U3707 ( .A(n4870), .B(n4869), .Y(n4875) );
XNOR2X1TS U3708 ( .A(n4826), .B(n4825), .Y(n4827) );
MXI2XLTS U3709 ( .A(n5851), .B(n6095), .S0(n4610), .Y(n1709) );
MXI2XLTS U3710 ( .A(n5850), .B(n6096), .S0(n4610), .Y(n1710) );
MXI2XLTS U3711 ( .A(n5857), .B(n6097), .S0(n4635), .Y(n1711) );
MXI2XLTS U3712 ( .A(n5855), .B(n6098), .S0(n4635), .Y(n1712) );
MXI2XLTS U3713 ( .A(n5849), .B(n6100), .S0(n4635), .Y(n1714) );
MXI2XLTS U3714 ( .A(n5845), .B(n6101), .S0(n4635), .Y(n1715) );
MXI2XLTS U3715 ( .A(n5841), .B(n6102), .S0(n4635), .Y(n1716) );
MXI2XLTS U3716 ( .A(n5832), .B(n6103), .S0(n4635), .Y(n1717) );
MXI2XLTS U3717 ( .A(n5833), .B(n6104), .S0(n4635), .Y(n1718) );
MXI2XLTS U3718 ( .A(n5810), .B(n6105), .S0(n4635), .Y(n1719) );
MXI2XLTS U3719 ( .A(n5834), .B(n6106), .S0(n4635), .Y(n1720) );
MXI2XLTS U3720 ( .A(n5808), .B(n6107), .S0(n4658), .Y(n1721) );
MXI2XLTS U3721 ( .A(n5812), .B(n6108), .S0(n4658), .Y(n1722) );
MXI2XLTS U3722 ( .A(n5817), .B(n6109), .S0(n4658), .Y(n1723) );
MXI2XLTS U3723 ( .A(n5807), .B(n6110), .S0(n4658), .Y(n1724) );
MXI2XLTS U3724 ( .A(n5848), .B(n6111), .S0(n4658), .Y(n1725) );
MXI2XLTS U3725 ( .A(n5835), .B(n6112), .S0(n4658), .Y(n1726) );
MXI2XLTS U3726 ( .A(n5837), .B(n6115), .S0(n4658), .Y(n1729) );
MXI2XLTS U3727 ( .A(n5839), .B(n6116), .S0(n4658), .Y(n1730) );
MXI2XLTS U3728 ( .A(n5840), .B(n6117), .S0(n5772), .Y(n1731) );
MXI2XLTS U3729 ( .A(n5859), .B(n6118), .S0(n5772), .Y(n1732) );
MXI2XLTS U3730 ( .A(n5787), .B(n6119), .S0(n5772), .Y(n1733) );
MXI2XLTS U3731 ( .A(n5864), .B(n6120), .S0(n5772), .Y(n1734) );
MXI2XLTS U3732 ( .A(n5865), .B(n6121), .S0(n5772), .Y(n1735) );
MXI2XLTS U3733 ( .A(n5867), .B(n6122), .S0(n5772), .Y(n1736) );
MXI2XLTS U3734 ( .A(n6123), .B(n4395), .S0(n5777), .Y(n1684) );
MXI2XLTS U3735 ( .A(n6124), .B(n5779), .S0(n4662), .Y(n1685) );
MXI2XLTS U3736 ( .A(n6125), .B(n5780), .S0(n4680), .Y(n1686) );
MXI2XLTS U3737 ( .A(n6145), .B(n5783), .S0(n4662), .Y(n1687) );
MXI2XLTS U3738 ( .A(n6138), .B(n5784), .S0(n4510), .Y(n1688) );
MXI2XLTS U3739 ( .A(n6146), .B(n5781), .S0(n4510), .Y(n1689) );
MXI2XLTS U3740 ( .A(n6139), .B(n5792), .S0(n4510), .Y(n1690) );
MXI2XLTS U3741 ( .A(n6147), .B(n5791), .S0(n4510), .Y(n1691) );
MXI2XLTS U3742 ( .A(n6140), .B(n5786), .S0(n4680), .Y(n1692) );
MXI2XLTS U3743 ( .A(n6148), .B(n5795), .S0(n4510), .Y(n1693) );
MXI2XLTS U3744 ( .A(n6141), .B(n5794), .S0(n4510), .Y(n1694) );
MXI2XLTS U3745 ( .A(n6149), .B(n5798), .S0(n4680), .Y(n1695) );
MXI2XLTS U3746 ( .A(n6142), .B(n5800), .S0(n5777), .Y(n1696) );
MXI2XLTS U3747 ( .A(n6150), .B(n5797), .S0(n4510), .Y(n1697) );
MXI2XLTS U3748 ( .A(n6143), .B(n5799), .S0(n4680), .Y(n1698) );
MXI2XLTS U3749 ( .A(n6151), .B(n5803), .S0(n4662), .Y(n1699) );
MXI2XLTS U3750 ( .A(n6144), .B(n5796), .S0(n4680), .Y(n1700) );
MXI2XLTS U3751 ( .A(n5793), .B(n6156), .S0(n4610), .Y(n1701) );
MXI2XLTS U3752 ( .A(n5788), .B(n6152), .S0(n4610), .Y(n1702) );
MXI2XLTS U3753 ( .A(n5785), .B(n6157), .S0(n4610), .Y(n1703) );
MXI2XLTS U3754 ( .A(n5811), .B(n6153), .S0(n4610), .Y(n1704) );
MXI2XLTS U3755 ( .A(n5806), .B(n6158), .S0(n4610), .Y(n1705) );
MXI2XLTS U3756 ( .A(n5809), .B(n6154), .S0(n4610), .Y(n1706) );
MXI2XLTS U3757 ( .A(n5813), .B(n6159), .S0(n4610), .Y(n1707) );
MXI2XLTS U3758 ( .A(n5805), .B(n6155), .S0(n4610), .Y(n1708) );
MXI2XLTS U3759 ( .A(n4675), .B(n3207), .S0(n5772), .Y(n1737) );
MXI2XLTS U3760 ( .A(n4674), .B(n4673), .S0(n4676), .Y(n4675) );
OAI21XLTS U3761 ( .A0(n5998), .A1(n4135), .B0(n4124), .Y(n1742) );
OAI21XLTS U3762 ( .A0(n6006), .A1(n4135), .B0(n4134), .Y(n1750) );
OAI21XLTS U3763 ( .A0(n6009), .A1(n4151), .B0(n4138), .Y(n1754) );
OAI21XLTS U3764 ( .A0(n5996), .A1(n4151), .B0(n4144), .Y(n1758) );
OAI21XLTS U3765 ( .A0(n5997), .A1(n4151), .B0(n4145), .Y(n1766) );
OAI21XLTS U3766 ( .A0(n6005), .A1(n4151), .B0(n4141), .Y(n1774) );
OAI21XLTS U3767 ( .A0(n6000), .A1(n4151), .B0(n4147), .Y(n1782) );
OAI21XLTS U3768 ( .A0(n5918), .A1(n4151), .B0(n4150), .Y(n1790) );
OAI21XLTS U3769 ( .A0(n6010), .A1(n4143), .B0(n4139), .Y(n1794) );
OAI21XLTS U3770 ( .A0(n6002), .A1(n4143), .B0(n4140), .Y(n1810) );
OAI21XLTS U3771 ( .A0(n6007), .A1(n4143), .B0(n4142), .Y(n1814) );
OAI21XLTS U3772 ( .A0(n6004), .A1(n4143), .B0(n4137), .Y(n1822) );
OAI21XLTS U3773 ( .A0(n6008), .A1(n4133), .B0(n4126), .Y(n1838) );
OAI21XLTS U3774 ( .A0(n5999), .A1(n4133), .B0(n4132), .Y(n1846) );
OAI21XLTS U3775 ( .A0(n5968), .A1(n4040), .B0(n3459), .Y(n1873) );
OAI21XLTS U3776 ( .A0(n5964), .A1(n4040), .B0(n3461), .Y(n1880) );
OAI21XLTS U3777 ( .A0(n5973), .A1(n4040), .B0(n3460), .Y(n1887) );
OAI21XLTS U3778 ( .A0(n5919), .A1(n4130), .B0(n4129), .Y(n1956) );
OAI21XLTS U3779 ( .A0(n6012), .A1(n4130), .B0(n4125), .Y(n1958) );
OAI21XLTS U3780 ( .A0(n4186), .A1(n5873), .B0(n4182), .Y(n2022) );
MX2X1TS U3781 ( .A(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]), .B(
n5223), .S0(n5222), .Y(n2024) );
XOR2XLTS U3782 ( .A(n4848), .B(n4847), .Y(n4853) );
XOR2XLTS U3783 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[52]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]), .Y(n4847) );
XOR2XLTS U3784 ( .A(n4861), .B(n4860), .Y(n4867) );
XNOR2X1TS U3785 ( .A(n4832), .B(n4831), .Y(n4833) );
XOR2XLTS U3786 ( .A(n4904), .B(n4903), .Y(n4905) );
XOR2XLTS U3787 ( .A(n4916), .B(n4915), .Y(n4921) );
XOR2XLTS U3788 ( .A(n4910), .B(n4909), .Y(n4912) );
XOR2XLTS U3789 ( .A(n4930), .B(n4929), .Y(n4931) );
XOR2XLTS U3790 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[36]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]), .Y(n4929) );
XOR2XLTS U3791 ( .A(n4958), .B(n4957), .Y(n4959) );
XOR2XLTS U3792 ( .A(n5093), .B(n5092), .Y(n5094) );
OAI21XLTS U3793 ( .A0(n5915), .A1(n4034), .B0(n3458), .Y(n2099) );
OAI21XLTS U3794 ( .A0(n6086), .A1(n3734), .B0(n3473), .Y(n2102) );
OAI21XLTS U3795 ( .A0(n6082), .A1(n3734), .B0(n3467), .Y(n2120) );
OAI21XLTS U3796 ( .A0(n5965), .A1(n4034), .B0(n3456), .Y(n2123) );
OAI21XLTS U3797 ( .A0(n6090), .A1(n3734), .B0(n3469), .Y(n2126) );
OAI21XLTS U3798 ( .A0(n6017), .A1(n3734), .B0(n3472), .Y(n2138) );
OAI21XLTS U3799 ( .A0(n6083), .A1(n3734), .B0(n3464), .Y(n2141) );
OAI21XLTS U3800 ( .A0(n6088), .A1(n3734), .B0(n3470), .Y(n2144) );
OAI21XLTS U3801 ( .A0(n6016), .A1(n3734), .B0(n3463), .Y(n2150) );
OAI21XLTS U3802 ( .A0(n6087), .A1(n3734), .B0(n3471), .Y(n2156) );
OAI21XLTS U3803 ( .A0(n6084), .A1(n4121), .B0(n3466), .Y(n2171) );
OAI21XLTS U3804 ( .A0(n6091), .A1(n4121), .B0(n3465), .Y(n2174) );
OAI21XLTS U3805 ( .A0(n6085), .A1(n4121), .B0(n3468), .Y(n2180) );
OAI21XLTS U3806 ( .A0(n5988), .A1(n4021), .B0(n3639), .Y(n2249) );
OAI21XLTS U3807 ( .A0(n5990), .A1(n4021), .B0(n3638), .Y(n2250) );
OAI21XLTS U3808 ( .A0(n5917), .A1(n4121), .B0(n4120), .Y(n2255) );
OAI21XLTS U3809 ( .A0(n6003), .A1(n4121), .B0(n3462), .Y(n2256) );
AO22XLTS U3810 ( .A0(n5829), .A1(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[10]), .B0(
result_add_subt[62]), .B1(n5875), .Y(n2258) );
XOR2XLTS U3811 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[57]), .B(n5768),
.Y(n5769) );
XOR2XLTS U3812 ( .A(n5767), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[57]),
.Y(n5768) );
NAND3XLTS U3813 ( .A(n5567), .B(n5566), .C(n5565), .Y(n2506) );
OAI211XLTS U3814 ( .A0(n3609), .A1(n4342), .B0(n4079), .C0(n4078), .Y(n2508)
);
OAI211XLTS U3815 ( .A0(n4273), .A1(n4229), .B0(n4228), .C0(n4227), .Y(n2513)
);
OAI211XLTS U3816 ( .A0(n4223), .A1(n4273), .B0(n4222), .C0(n4221), .Y(n2516)
);
OAI211XLTS U3817 ( .A0(n4273), .A1(n4362), .B0(n4095), .C0(n4094), .Y(n2523)
);
OAI211XLTS U3818 ( .A0(n4241), .A1(n4273), .B0(n4240), .C0(n4239), .Y(n2528)
);
OAI211XLTS U3819 ( .A0(n4327), .A1(n4238), .B0(n4231), .C0(n4230), .Y(n2533)
);
OAI211XLTS U3820 ( .A0(n4214), .A1(n4249), .B0(n4213), .C0(n4212), .Y(n2534)
);
OAI211XLTS U3821 ( .A0(n4273), .A1(n4249), .B0(n4248), .C0(n4247), .Y(n2535)
);
OAI211XLTS U3822 ( .A0(n4290), .A1(n4289), .B0(n4288), .C0(n4287), .Y(n2547)
);
OAI211XLTS U3823 ( .A0(n4290), .A1(n4249), .B0(n4243), .C0(n4242), .Y(n2537)
);
OAI211XLTS U3824 ( .A0(n4273), .A1(n4260), .B0(n4259), .C0(n4258), .Y(n2539)
);
OAI211XLTS U3825 ( .A0(n4274), .A1(n3587), .B0(n4199), .C0(n4198), .Y(n2558)
);
OAI21XLTS U3826 ( .A0(n4317), .A1(n4185), .B0(n4167), .Y(n3040) );
OAI21XLTS U3827 ( .A0(n4296), .A1(n4639), .B0(n4185), .Y(n3042) );
OAI211XLTS U3828 ( .A0(n4195), .A1(n4214), .B0(n4194), .C0(n4193), .Y(n2541)
);
OAI211XLTS U3829 ( .A0(n4214), .A1(n4260), .B0(n4197), .C0(n4196), .Y(n2538)
);
OAI211XLTS U3830 ( .A0(n4290), .A1(n4362), .B0(n4091), .C0(n4090), .Y(n2525)
);
OAI211XLTS U3831 ( .A0(n4273), .A1(n4372), .B0(n4093), .C0(n4092), .Y(n2543)
);
OAI211XLTS U3832 ( .A0(n4290), .A1(n4254), .B0(n4253), .C0(n4252), .Y(n2527)
);
OAI211XLTS U3833 ( .A0(n4214), .A1(n4372), .B0(n4068), .C0(n4067), .Y(n2542)
);
OAI211XLTS U3834 ( .A0(n4290), .A1(n4372), .B0(n3665), .C0(n3664), .Y(n2545)
);
OAI211XLTS U3835 ( .A0(n3609), .A1(n4353), .B0(n4064), .C0(n4063), .Y(n2518)
);
OAI211XLTS U3836 ( .A0(n4223), .A1(n4214), .B0(n4202), .C0(n4201), .Y(n2515)
);
OAI211XLTS U3837 ( .A0(n4214), .A1(n4229), .B0(n4205), .C0(n4204), .Y(n2512)
);
OAI211XLTS U3838 ( .A0(n3587), .A1(n4353), .B0(n4089), .C0(n4088), .Y(n2521)
);
OAI211XLTS U3839 ( .A0(n4267), .A1(n4273), .B0(n4266), .C0(n4265), .Y(n2552)
);
OAI211XLTS U3840 ( .A0(n3587), .A1(n4342), .B0(n4087), .C0(n4086), .Y(n2511)
);
OAI211XLTS U3841 ( .A0(n4214), .A1(n4362), .B0(n4076), .C0(n4075), .Y(n2522)
);
OAI211XLTS U3842 ( .A0(n4267), .A1(n4290), .B0(n4262), .C0(n4261), .Y(n2554)
);
OAI211XLTS U3843 ( .A0(n4274), .A1(n4214), .B0(n4190), .C0(n4189), .Y(n2555)
);
OAI211XLTS U3844 ( .A0(n4274), .A1(n4273), .B0(n4272), .C0(n4271), .Y(n2556)
);
AOI2BB2XLTS U3845 ( .B0(n5381), .B1(n6019), .A0N(d_ff_Xn[60]), .A1N(n5380),
.Y(n2769) );
AOI2BB2XLTS U3846 ( .B0(n5381), .B1(n6018), .A0N(d_ff_Xn[58]), .A1N(n5380),
.Y(n2771) );
AO22XLTS U3847 ( .A0(n5742), .A1(n5551), .B0(n5751), .B1(d_ff3_sh_y_out[62]),
.Y(n2563) );
XOR2XLTS U3848 ( .A(d_ff2_Y[62]), .B(n5550), .Y(n5551) );
AOI2BB2XLTS U3849 ( .B0(n5549), .B1(n5548), .A0N(d_ff3_sh_y_out[61]), .A1N(
n5547), .Y(n2565) );
OAI21XLTS U3850 ( .A0(n5544), .A1(n6027), .B0(n5546), .Y(n5545) );
AOI2BB2XLTS U3851 ( .B0(n5549), .B1(n5543), .A0N(d_ff3_sh_y_out[59]), .A1N(
n5547), .Y(n2569) );
AO22XLTS U3852 ( .A0(n5752), .A1(n5398), .B0(n5741), .B1(d_ff3_sh_x_out[62]),
.Y(n2756) );
XOR2XLTS U3853 ( .A(d_ff2_X[62]), .B(n5397), .Y(n5398) );
AOI2BB2XLTS U3854 ( .B0(n5549), .B1(n5396), .A0N(d_ff3_sh_x_out[61]), .A1N(
n5537), .Y(n2757) );
OAI21XLTS U3855 ( .A0(n5393), .A1(n6019), .B0(n5395), .Y(n5394) );
AOI2BB2XLTS U3856 ( .B0(n5549), .B1(n5392), .A0N(d_ff3_sh_x_out[59]), .A1N(
n5537), .Y(n2759) );
OAI21XLTS U3857 ( .A0(n5388), .A1(n6018), .B0(n5391), .Y(n5389) );
OAI211XLTS U3858 ( .A0(n5309), .A1(n4298), .B0(n3834), .C0(n5291), .Y(n3112)
);
OAI211XLTS U3859 ( .A0(n5274), .A1(n4107), .B0(n4106), .C0(n4108), .Y(n3143)
);
NAND3XLTS U3860 ( .A(n5301), .B(n5300), .C(n5299), .Y(n3120) );
OAI211XLTS U3861 ( .A0(n5301), .A1(n5281), .B0(n4104), .C0(n5299), .Y(n3122)
);
NAND4XLTS U3862 ( .A(n5293), .B(n5292), .C(n5291), .D(n5290), .Y(n3126) );
NAND3XLTS U3863 ( .A(n3180), .B(n5289), .C(n3176), .Y(n5292) );
AOI2BB2XLTS U3864 ( .B0(d_ff3_LUT_out[15]), .B1(n5406), .A0N(n5305), .A1N(
n5288), .Y(n5293) );
NAND3XLTS U3865 ( .A(n5314), .B(n5313), .C(n5312), .Y(n3113) );
OAI211XLTS U3866 ( .A0(n4110), .A1(n6137), .B0(n5287), .C0(n5288), .Y(n3144)
);
OAI21XLTS U3867 ( .A0(n5549), .A1(d_ff3_LUT_out[5]), .B0(n5315), .Y(n5304)
);
OAI21XLTS U3868 ( .A0(n5309), .A1(n5361), .B0(n3904), .Y(n3124) );
OAI211XLTS U3869 ( .A0(n4110), .A1(n6133), .B0(n5269), .C0(n5263), .Y(n3135)
);
OAI211XLTS U3870 ( .A0(n4110), .A1(n6132), .B0(n5271), .C0(n5296), .Y(n3141)
);
OAI211XLTS U3871 ( .A0(n4110), .A1(n6128), .B0(n4102), .C0(n5278), .Y(n3157)
);
OAI211XLTS U3872 ( .A0(n4110), .A1(n6134), .B0(n4109), .C0(n5312), .Y(n3129)
);
NAND2BXLTS U3873 ( .AN(n5298), .B(n5286), .Y(n3128) );
OAI211XLTS U3874 ( .A0(n4110), .A1(n6136), .B0(n5269), .C0(n4298), .Y(n3150)
);
OAI211XLTS U3875 ( .A0(n4110), .A1(n6129), .B0(n5266), .C0(n4298), .Y(n3153)
);
OAI21XLTS U3876 ( .A0(n5276), .A1(n5277), .B0(n4114), .Y(n3118) );
OAI211XLTS U3877 ( .A0(n5262), .A1(n5288), .B0(n4117), .C0(n4116), .Y(n3114)
);
OAI21XLTS U3878 ( .A0(n4101), .A1(n5263), .B0(n4100), .Y(n3134) );
AOI2BB2XLTS U3879 ( .B0(n5289), .B1(n5269), .A0N(n5742), .A1N(
d_ff3_LUT_out[32]), .Y(n3142) );
NAND2BXLTS U3880 ( .AN(d_ff3_LUT_out[48]), .B(n5741), .Y(n3152) );
MXI2XLTS U3881 ( .A(n6032), .B(n5216), .S0(n5256), .Y(n3167) );
OAI21XLTS U3882 ( .A0(ack_cordic), .A1(n3901), .B0(n3931), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
OR2X1TS U3883 ( .A(n4477), .B(n4545), .Y(n3177) );
OR2X1TS U3884 ( .A(n4467), .B(n4545), .Y(n3178) );
OR2X1TS U3885 ( .A(n4458), .B(n4545), .Y(n3179) );
AFHCINX2TS U3886 ( .CIN(n4819), .B(n6148), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[43]), .S(n4823), .CO(n4824) );
AFHCINX2TS U3887 ( .CIN(n4836), .B(n6145), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[49]), .S(n4840), .CO(n4850) );
AFHCINX2TS U3888 ( .CIN(n4886), .B(n6151), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[37]), .S(n4890), .CO(n4892) );
AFHCINX2TS U3889 ( .CIN(n4922), .B(n6157), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[33]), .S(n4926), .CO(n4928) );
INVX2TS U3890 ( .A(n4568), .Y(n3181) );
INVX2TS U3891 ( .A(n3181), .Y(n3182) );
INVX2TS U3892 ( .A(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3183)
);
INVX2TS U3893 ( .A(n3177), .Y(n3185) );
INVX2TS U3894 ( .A(n3177), .Y(n3186) );
INVX2TS U3895 ( .A(n3178), .Y(n3187) );
INVX2TS U3896 ( .A(n3178), .Y(n3188) );
INVX2TS U3897 ( .A(n3179), .Y(n3189) );
INVX2TS U3898 ( .A(n3179), .Y(n3190) );
OAI21XLTS U3899 ( .A0(n4561), .A1(n3181), .B0(n4431), .Y(n4668) );
OAI21XLTS U3900 ( .A0(n4571), .A1(n3181), .B0(n4440), .Y(n4666) );
OAI211XLTS U3901 ( .A0(n4580), .A1(n4579), .B0(n4578), .C0(n3192), .Y(n4626)
);
OAI211XLTS U3902 ( .A0(n4554), .A1(n4580), .B0(n4553), .C0(n3192), .Y(n4632)
);
OAI211XLTS U3903 ( .A0(n4548), .A1(n4580), .B0(n4547), .C0(n3192), .Y(n4634)
);
OAI211XLTS U3904 ( .A0(n4541), .A1(n4580), .B0(n4540), .C0(n3192), .Y(n4638)
);
OAI211XLTS U3905 ( .A0(n4574), .A1(n4580), .B0(n4533), .C0(n3192), .Y(n4641)
);
INVX2TS U3906 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(
n5846) );
INVX2TS U3907 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(
n5773) );
INVX2TS U3908 ( .A(n4203), .Y(n3195) );
INVX2TS U3909 ( .A(n4373), .Y(n4203) );
INVX2TS U3910 ( .A(n5960), .Y(n3196) );
NAND2X1TS U3911 ( .A(n6013), .B(n5893), .Y(n3197) );
OAI21XLTS U3912 ( .A0(n3197), .A1(n4579), .B0(n4530), .Y(n4677) );
OAI21XLTS U3913 ( .A0(n3197), .A1(n4554), .B0(n3191), .Y(n4669) );
OAI21XLTS U3914 ( .A0(n3197), .A1(n4542), .B0(n4530), .Y(n4671) );
OAI21XLTS U3915 ( .A0(n4603), .A1(n3197), .B0(n4530), .Y(n4652) );
OAI21XLTS U3916 ( .A0(n4583), .A1(n3197), .B0(n3191), .Y(n4660) );
OAI21XLTS U3917 ( .A0(n4548), .A1(n3197), .B0(n3191), .Y(n4667) );
OAI21XLTS U3918 ( .A0(n4541), .A1(n3197), .B0(n4530), .Y(n4665) );
OAI21XLTS U3919 ( .A0(n4571), .A1(n3197), .B0(n4538), .Y(n4637) );
OAI21XLTS U3920 ( .A0(n4561), .A1(n3197), .B0(n4544), .Y(n4633) );
OAI21XLTS U3921 ( .A0(n4613), .A1(n4545), .B0(n3191), .Y(n4650) );
OAI21XLTS U3922 ( .A0(n4574), .A1(n4545), .B0(n3191), .Y(n4663) );
NAND2X1TS U3923 ( .A(n6013), .B(n5893), .Y(n4545) );
OAI2BB1X1TS U3924 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]), .A1N(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[52]), .B0(n3243), .Y(
n4842) );
OAI22X1TS U3925 ( .A0(n4850), .A1(n3306), .B0(n6125), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]), .Y(n4843) );
XNOR2X1TS U3926 ( .A(n6125), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]),
.Y(n4849) );
OAI22X1TS U3927 ( .A0(n4892), .A1(n3303), .B0(n6143), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]), .Y(n4902) );
OAI22X1TS U3928 ( .A0(n4916), .A1(n3302), .B0(n6144), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]), .Y(n4886) );
OAI22X1TS U3929 ( .A0(n4870), .A1(n3305), .B0(n6138), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]), .Y(n4836) );
OR2X1TS U3930 ( .A(n4476), .B(n3197), .Y(n4520) );
INVX2TS U3931 ( .A(n4520), .Y(n3198) );
INVX2TS U3932 ( .A(n4520), .Y(n3199) );
OAI22X1TS U3933 ( .A0(n4937), .A1(n3237), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[34]), .Y(n4923) );
OAI22X1TS U3934 ( .A0(n4935), .A1(n3301), .B0(n6153), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]), .Y(n4922) );
OR2X1TS U3935 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[38]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[37]), .Y(n3209) );
OAI21XLTS U3936 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n5925),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .Y(n3335) );
NOR2XLTS U3937 ( .A(n6108), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .Y(
n3268) );
NOR2XLTS U3938 ( .A(n6104), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .Y(
n3278) );
NOR2XLTS U3939 ( .A(n6096), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .Y(
n3292) );
AOI211XLTS U3940 ( .A0(n3358), .A1(n3357), .B0(n3356), .C0(n3355), .Y(n3359)
);
OAI21XLTS U3941 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .A1(n6000), .B0(n3399), .Y(n3409) );
NOR2XLTS U3942 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[29]), .Y(n4968) );
NAND2X1TS U3943 ( .A(n3536), .B(n3205), .Y(n3478) );
NOR2XLTS U3944 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n4767) );
AOI21X1TS U3945 ( .A0(n3218), .A1(n4695), .B0(n3217), .Y(n4725) );
OAI21XLTS U3946 ( .A0(n3254), .A1(n5171), .B0(n3253), .Y(n3255) );
OAI21XLTS U3947 ( .A0(n3410), .A1(n3409), .B0(n3408), .Y(n3412) );
AOI211XLTS U3948 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .A1(
n5943), .B0(n3366), .C0(n3372), .Y(n3363) );
AOI211XLTS U3949 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .A1(
n5942), .B0(n3315), .C0(n3432), .Y(n3434) );
OAI21XLTS U3950 ( .A0(n4999), .A1(n5014), .B0(n5000), .Y(n4992) );
NOR2XLTS U3951 ( .A(n5924), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3480) );
NOR2XLTS U3952 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n4809) );
NOR2XLTS U3953 ( .A(n6107), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .Y(
n5050) );
OAI31X1TS U3954 ( .A0(n3527), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .A2(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B0(n5927), .Y(
n3528) );
NOR2BX1TS U3955 ( .AN(n5235), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[9]), .Y(n5236) );
NOR2XLTS U3956 ( .A(n6097), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .Y(
n4987) );
XNOR2X1TS U3957 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[46]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]), .Y(n4825) );
OAI21XLTS U3958 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]),
.A1(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B0(n4169), .Y(
n4171) );
OAI31X1TS U3959 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]),
.A1(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]), .A2(n3739),
.B0(n4154), .Y(n3746) );
XNOR2X1TS U3960 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[44]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]), .Y(n4831) );
OAI21XLTS U3961 ( .A0(n5004), .A1(n5013), .B0(n5014), .Y(n5006) );
NOR2XLTS U3962 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n5040) );
NOR2XLTS U3963 ( .A(n6105), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .Y(
n4807) );
OAI21XLTS U3964 ( .A0(n4735), .A1(n4734), .B0(n4733), .Y(n5078) );
OAI21XLTS U3965 ( .A0(n5160), .A1(n4703), .B0(n4702), .Y(n4721) );
OAI21XLTS U3966 ( .A0(n5179), .A1(n5173), .B0(n5174), .Y(n5164) );
OAI21XLTS U3967 ( .A0(n5115), .A1(n5114), .B0(n5113), .Y(n5117) );
NOR4XLTS U3968 ( .A(n3416), .B(n3449), .C(n3451), .D(n3319), .Y(n3455) );
AOI211XLTS U3969 ( .A0(n4503), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .B0(n4492), .C0(n4468), .Y(n4589) );
NOR2XLTS U3970 ( .A(n3539), .B(n3538), .Y(n3540) );
NOR2XLTS U3971 ( .A(n3629), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[41]), .Y(n3620) );
CLKBUFX2TS U3972 ( .A(n3753), .Y(n3789) );
AFHCINX2TS U3973 ( .CIN(n4877), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[45]),
.A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[47]), .S(n4878), .CO(
n4863) );
OAI21XLTS U3974 ( .A0(n4595), .A1(n4612), .B0(n4594), .Y(n4619) );
OAI21XLTS U3975 ( .A0(n4808), .A1(n4807), .B0(n4806), .Y(n4813) );
OAI21XLTS U3976 ( .A0(n5068), .A1(n5067), .B0(n5066), .Y(n5087) );
OAI21XLTS U3977 ( .A0(n5160), .A1(n5145), .B0(n5144), .Y(n5150) );
OAI21XLTS U3978 ( .A0(n4589), .A1(n4612), .B0(n4588), .Y(n4621) );
OAI21XLTS U3979 ( .A0(n4595), .A1(n4545), .B0(n3191), .Y(n4654) );
OAI21XLTS U3980 ( .A0(n4589), .A1(n4545), .B0(n3191), .Y(n4656) );
OAI21XLTS U3981 ( .A0(n4545), .A1(n4537), .B0(n3191), .Y(n4673) );
INVX2TS U3982 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .Y(
n5838) );
NOR2XLTS U3983 ( .A(n3594), .B(n3593), .Y(n4191) );
CLKBUFX2TS U3984 ( .A(n4203), .Y(n4329) );
OAI21XLTS U3985 ( .A0(n5936), .A1(n4294), .B0(n3659), .Y(n4337) );
OAI21XLTS U3986 ( .A0(n5941), .A1(n4294), .B0(n4077), .Y(n5561) );
CLKBUFX2TS U3987 ( .A(n5496), .Y(n4006) );
XOR2XLTS U3988 ( .A(n4935), .B(n4934), .Y(n4940) );
AOI211XLTS U3989 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]),
.A1(n4181), .B0(n4180), .C0(n4179), .Y(n4186) );
INVX2TS U3990 ( .A(n5241), .Y(n5790) );
CLKBUFX2TS U3991 ( .A(n4013), .Y(n4021) );
INVX2TS U3992 ( .A(n5439), .Y(n5743) );
CLKBUFX2TS U3993 ( .A(n5370), .Y(n5366) );
CLKBUFX2TS U3994 ( .A(n5585), .Y(n5439) );
NAND2X1TS U3995 ( .A(n3565), .B(n4232), .Y(n4373) );
CLKBUFX2TS U3996 ( .A(n3609), .Y(n4214) );
CLKBUFX2TS U3997 ( .A(n3210), .Y(n4273) );
CLKBUFX2TS U3998 ( .A(n3587), .Y(n4290) );
CLKBUFX2TS U3999 ( .A(n5491), .Y(n5378) );
OAI21XLTS U4000 ( .A0(n5539), .A1(n6026), .B0(n5542), .Y(n5540) );
OAI32X1TS U4001 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(
n4381), .B1(n6038), .Y(n5256) );
INVX2TS U4002 ( .A(rst), .Y(n5246) );
OAI21XLTS U4003 ( .A0(n6089), .A1(n3734), .B0(n3474), .Y(n2108) );
OAI21XLTS U4004 ( .A0(n5976), .A1(n4034), .B0(n3457), .Y(n2135) );
OAI211XLTS U4005 ( .A0(n4334), .A1(n4238), .B0(n4237), .C0(n4236), .Y(n2532)
);
OAI211XLTS U4006 ( .A0(n5567), .A1(n4290), .B0(n4218), .C0(n4217), .Y(n2507)
);
OAI211XLTS U4007 ( .A0(n4110), .A1(n6135), .B0(n5269), .C0(n4097), .Y(n3123)
);
OAI211XLTS U4008 ( .A0(n4110), .A1(n6131), .B0(n4109), .C0(n4108), .Y(n3145)
);
OAI211XLTS U4009 ( .A0(n4110), .A1(n6130), .B0(n5280), .C0(n5288), .Y(n3148)
);
CLKBUFX2TS U4010 ( .A(n5773), .Y(n5216) );
NOR2XLTS U4011 ( .A(n5114), .B(n5109), .Y(n3212) );
NAND2X1TS U4012 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n5208) );
NAND2X1TS U4013 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n5199) );
NAND2X1TS U4014 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n5113) );
NAND2X1TS U4015 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n5110) );
AOI21X1TS U4016 ( .A0(n3212), .A1(n5103), .B0(n3211), .Y(n5128) );
NAND2X1TS U4017 ( .A(n5162), .B(n3214), .Y(n3216) );
NAND2X1TS U4018 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n5189) );
NAND2X1TS U4019 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n5185) );
NAND2X1TS U4020 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n5174) );
NAND2X1TS U4021 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n5157) );
AOI21X1TS U4022 ( .A0(n3214), .A1(n5161), .B0(n3213), .Y(n3215) );
OAI21X1TS U4023 ( .A0(n5128), .A1(n3216), .B0(n3215), .Y(n4693) );
NAND2X1TS U4024 ( .A(n4694), .B(n3218), .Y(n4726) );
NAND2X1TS U4025 ( .A(n4731), .B(n3220), .Y(n3222) );
NAND2X1TS U4026 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n5147) );
NAND2X1TS U4027 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n5135) );
NAND2X1TS U4028 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n4708) );
NAND2X1TS U4029 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n4705) );
NAND2X1TS U4030 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n5088) );
NAND2X1TS U4031 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n5084) );
NAND2X1TS U4032 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n5073) );
NAND2X1TS U4033 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n4739) );
AOI21X1TS U4034 ( .A0(n3220), .A1(n4732), .B0(n3219), .Y(n3221) );
AOI21X1TS U4035 ( .A0(n4693), .A1(n3224), .B0(n3223), .Y(n4756) );
NAND2X1TS U4036 ( .A(n4758), .B(n3226), .Y(n4771) );
NAND2X1TS U4037 ( .A(n5024), .B(n3228), .Y(n3230) );
NAND2X1TS U4038 ( .A(n4993), .B(n4989), .Y(n4975) );
NAND2X1TS U4039 ( .A(n4974), .B(n3233), .Y(n3235) );
NAND2X1TS U4040 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n5055) );
NAND2X1TS U4041 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n4796) );
NAND2X1TS U4042 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n4810) );
NAND2X1TS U4043 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n4753) );
AOI21X1TS U4044 ( .A0(n3226), .A1(n4757), .B0(n3225), .Y(n4772) );
NAND2X1TS U4045 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n4784) );
NAND2X1TS U4046 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n4768) );
NAND2X1TS U4047 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n5041) );
NAND2X1TS U4048 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n5027) );
AOI21X1TS U4049 ( .A0(n3228), .A1(n5023), .B0(n3227), .Y(n3229) );
OAI21X1TS U4050 ( .A0(n4772), .A1(n3230), .B0(n3229), .Y(n4973) );
NAND2X1TS U4051 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[26]), .Y(n5014) );
NAND2X1TS U4052 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[27]), .Y(n5000) );
NAND2X1TS U4053 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[28]), .Y(n4988) );
INVX2TS U4054 ( .A(n4988), .Y(n3231) );
AOI21X1TS U4055 ( .A0(n4992), .A1(n4989), .B0(n3231), .Y(n4976) );
NAND2X1TS U4056 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[29]), .Y(n4969) );
AOI21X1TS U4057 ( .A0(n4973), .A1(n3233), .B0(n3232), .Y(n3234) );
OAI22X2TS U4058 ( .A0(n4930), .A1(n3238), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[36]), .Y(n4910) );
ACHCINX2TS U4059 ( .CIN(n4910), .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[35]),
.B(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[37]), .CO(n4917) );
NAND2X1TS U4060 ( .A(n3207), .B(n6165), .Y(n5210) );
NOR2XLTS U4061 ( .A(n6122), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .Y(
n3246) );
NAND2X1TS U4062 ( .A(n6122), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .Y(
n3245) );
OAI21X1TS U4063 ( .A0(n5210), .A1(n3246), .B0(n3245), .Y(n5097) );
NOR2XLTS U4064 ( .A(n6121), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .Y(
n5099) );
NOR2XLTS U4065 ( .A(n6120), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .Y(
n3248) );
NOR2XLTS U4066 ( .A(n5099), .B(n3248), .Y(n3250) );
NAND2X1TS U4067 ( .A(n6121), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .Y(
n5098) );
NAND2X1TS U4068 ( .A(n6120), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .Y(
n3247) );
OAI21XLTS U4069 ( .A0(n3248), .A1(n5098), .B0(n3247), .Y(n3249) );
AOI21X1TS U4070 ( .A0(n5097), .A1(n3250), .B0(n3249), .Y(n5108) );
NOR2XLTS U4071 ( .A(n6119), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .Y(
n5121) );
NOR2XLTS U4072 ( .A(n6117), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .Y(
n5172) );
NAND2X1TS U4073 ( .A(n5169), .B(n3256), .Y(n3258) );
NAND2X1TS U4074 ( .A(n6119), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .Y(
n5122) );
NAND2X1TS U4075 ( .A(n6118), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .Y(
n3251) );
NAND2X1TS U4076 ( .A(n6117), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .Y(
n5171) );
NAND2X1TS U4077 ( .A(n6116), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .Y(
n3253) );
AOI21X1TS U4078 ( .A0(n3256), .A1(n5168), .B0(n3255), .Y(n3257) );
OAI21X1TS U4079 ( .A0(n5108), .A1(n3258), .B0(n3257), .Y(n4681) );
NOR2XLTS U4080 ( .A(n6115), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .Y(
n5145) );
NAND2X1TS U4081 ( .A(n4682), .B(n3264), .Y(n4703) );
NAND2X1TS U4082 ( .A(n5064), .B(n3270), .Y(n3272) );
NAND2X1TS U4083 ( .A(n6115), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .Y(
n5144) );
NAND2X1TS U4084 ( .A(n6114), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .Y(
n3259) );
OAI21X1TS U4085 ( .A0(n3260), .A1(n5144), .B0(n3259), .Y(n4683) );
NAND2X1TS U4086 ( .A(n6113), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .Y(
n4687) );
NAND2X1TS U4087 ( .A(n6112), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]),
.Y(n3261) );
AOI21X1TS U4088 ( .A0(n3264), .A1(n4683), .B0(n3263), .Y(n4702) );
NAND2X1TS U4089 ( .A(n6111), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]),
.Y(n4718) );
NAND2X1TS U4090 ( .A(n6110), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]),
.Y(n3265) );
NAND2X1TS U4091 ( .A(n6109), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]),
.Y(n5070) );
NAND2X1TS U4092 ( .A(n6108), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]),
.Y(n3267) );
AOI21X1TS U4093 ( .A0(n3270), .A1(n5065), .B0(n3269), .Y(n3271) );
AOI21X1TS U4094 ( .A0(n4681), .A1(n3274), .B0(n3273), .Y(n4742) );
NAND2X1TS U4095 ( .A(n4794), .B(n3280), .Y(n4748) );
NAND2X1TS U4096 ( .A(n4765), .B(n3286), .Y(n3288) );
NOR2X1TS U4097 ( .A(n4987), .B(n3292), .Y(n3294) );
NAND2X1TS U4098 ( .A(n4985), .B(n3294), .Y(n4964) );
NAND2X1TS U4099 ( .A(n4963), .B(n3298), .Y(n3300) );
NAND2X1TS U4100 ( .A(n6107), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]),
.Y(n5051) );
NAND2X1TS U4101 ( .A(n6106), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]),
.Y(n3275) );
NAND2X1TS U4102 ( .A(n6105), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]),
.Y(n4806) );
NAND2X1TS U4103 ( .A(n6104), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]),
.Y(n3277) );
AOI21X1TS U4104 ( .A0(n3280), .A1(n4793), .B0(n3279), .Y(n4749) );
NAND2X1TS U4105 ( .A(n6103), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]),
.Y(n4780) );
NAND2X1TS U4106 ( .A(n6102), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]),
.Y(n3281) );
NAND2X1TS U4107 ( .A(n6101), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]),
.Y(n5037) );
NAND2X1TS U4108 ( .A(n6100), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]),
.Y(n3283) );
AOI21X1TS U4109 ( .A0(n3286), .A1(n4764), .B0(n3285), .Y(n3287) );
OAI21X1TS U4110 ( .A0(n4749), .A1(n3288), .B0(n3287), .Y(n4962) );
NAND2X1TS U4111 ( .A(n6099), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]),
.Y(n5010) );
NAND2X1TS U4112 ( .A(n6098), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]),
.Y(n3289) );
NAND2X1TS U4113 ( .A(n6097), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]),
.Y(n4986) );
NAND2X1TS U4114 ( .A(n6096), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]),
.Y(n3291) );
AOI21X1TS U4115 ( .A0(n3294), .A1(n4984), .B0(n3293), .Y(n4965) );
NAND2X1TS U4116 ( .A(n6095), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]),
.Y(n3295) );
AOI21X1TS U4117 ( .A0(n4962), .A1(n3298), .B0(n3297), .Y(n3299) );
OAI21X2TS U4118 ( .A0(n4742), .A1(n3300), .B0(n3299), .Y(n4956) );
CLKAND2X2TS U4119 ( .A(n6125), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]),
.Y(n3306) );
CLKBUFX2TS U4120 ( .A(n5773), .Y(n5872) );
NOR2BX1TS U4121 ( .AN(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .B(n5872),
.Y(n5219) );
CLKBUFX2TS U4122 ( .A(n5219), .Y(n5215) );
CLKBUFX2TS U4123 ( .A(n5773), .Y(n4856) );
OR2X2TS U4124 ( .A(n3311), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[54]), .Y(n3312) );
CLKBUFX2TS U4125 ( .A(n5036), .Y(n4864) );
NOR2BX1TS U4126 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[39]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .Y(n3426) );
AOI21X1TS U4127 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[38]), .A1(n6092), .B0(n3426), .Y(n3425) );
NAND2X1TS U4128 ( .A(n5933), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[37]),
.Y(n3414) );
NOR2XLTS U4129 ( .A(n5993), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]),
.Y(n3400) );
OA22X1TS U4130 ( .A0(n5918), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]),
.B0(n6010), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .Y(n3405)
);
NOR2XLTS U4131 ( .A(n6003), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]),
.Y(n3315) );
OAI22X1TS U4132 ( .A0(n6011), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .B1(n5917), .Y(n3432) );
NOR2BX1TS U4133 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[56]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .Y(n3316) );
NAND2X1TS U4134 ( .A(n5985), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]),
.Y(n3392) );
NOR4XLTS U4135 ( .A(n3386), .B(n3316), .C(n3398), .D(n3390), .Y(n3443) );
OAI21XLTS U4136 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .A1(n5908), .B0(n3437), .Y(n3441) );
AOI211XLTS U4137 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[48]), .A1(
n6081), .B0(n3435), .C0(n3441), .Y(n3317) );
OA22X1TS U4138 ( .A0(n6005), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]),
.B0(n5910), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .Y(n3420)
);
OAI211XLTS U4139 ( .A0(n5970), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .B0(n3318), .C0(n3420),
.Y(n3319) );
OA22X1TS U4140 ( .A0(n6008), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]),
.B0(n5916), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .Y(n3330)
);
OAI21XLTS U4141 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .A1(n5971), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .Y(n3320) );
OAI2BB2XLTS U4142 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .B1(
n3320), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .A1N(n5971),
.Y(n3329) );
NOR2XLTS U4143 ( .A(n5992), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]),
.Y(n3378) );
AOI22X1TS U4144 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .A1(n3322), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .B1(n5992), .Y(n3325) );
AOI32X1TS U4145 ( .A0(n3323), .A1(n5980), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B1(n5912), .Y(n3324) );
OAI32X1TS U4146 ( .A0(n3381), .A1(n3380), .A2(n3325), .B0(n3324), .B1(n3380),
.Y(n3328) );
OAI21XLTS U4147 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .A1(n5916), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .Y(n3326) );
OAI2BB2XLTS U4148 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .B1(
n3326), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .A1N(n5916),
.Y(n3327) );
OA22X1TS U4149 ( .A0(n5987), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]),
.B0(n5909), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .Y(n3377)
);
OA22X1TS U4150 ( .A0(n5915), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]),
.B0(n5994), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .Y(n3358)
);
OAI2BB1X1TS U4151 ( .A0N(n5902), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .Y(n3333) );
OAI22X1TS U4152 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .A1(n3333),
.B0(n5902), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .Y(n3344)
);
OAI2BB1X1TS U4153 ( .A0N(n5904), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .Y(n3334) );
OAI22X1TS U4154 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .A1(n3334),
.B0(n5904), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .Y(n3343)
);
NAND2BXLTS U4155 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .Y(n3337) );
AOI2BB2XLTS U4156 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .B1(
n5925), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .A1N(n3335),
.Y(n3336) );
OAI211XLTS U4157 ( .A0(n5983), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .B0(n3337), .C0(n3336), .Y(n3340) );
OAI21XLTS U4158 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .A1(n5983),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .Y(n3338) );
AOI2BB2XLTS U4159 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .B1(
n5983), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .A1N(n3338),
.Y(n3339) );
AOI222XLTS U4160 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .A1(n5961), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .B1(n5902), .C0(n3340), .C1(
n3339), .Y(n3342) );
AOI22X1TS U4161 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .A1(n5904),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .B1(n5945), .Y(n3341)
);
OAI32X1TS U4162 ( .A0(n3344), .A1(n3343), .A2(n3342), .B0(n3341), .B1(n3343),
.Y(n3361) );
NOR2XLTS U4163 ( .A(n5981), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]),
.Y(n3346) );
AOI21X1TS U4164 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .A1(n5930), .B0(n3346), .Y(n3351) );
OAI211XLTS U4165 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .A1(n5969), .B0(n3348), .C0(n3351), .Y(n3360) );
OAI21XLTS U4166 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .A1(n5986), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .Y(n3345) );
OAI2BB2XLTS U4167 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .B1(
n3345), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .A1N(n5986),
.Y(n3357) );
AOI22X1TS U4168 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .A1(n3347), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .B1(n5981), .Y(n3353) );
NAND2BXLTS U4169 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .Y(n3350) );
AOI21X1TS U4170 ( .A0(n3350), .A1(n3349), .B0(n3362), .Y(n3352) );
OAI2BB2XLTS U4171 ( .B0(n3353), .B1(n3362), .A0N(n3352), .A1N(n3351), .Y(
n3356) );
OAI21XLTS U4172 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .A1(n5994), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .Y(n3354) );
OAI2BB2XLTS U4173 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .B1(
n3354), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .A1N(n5994),
.Y(n3355) );
OAI31X1TS U4174 ( .A0(n3362), .A1(n3361), .A2(n3360), .B0(n3359), .Y(n3364)
);
NOR2XLTS U4175 ( .A(n5982), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]),
.Y(n3366) );
OAI21XLTS U4176 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .A1(n5967), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .Y(n3365) );
OAI2BB2XLTS U4177 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .B1(
n3365), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .A1N(n5967),
.Y(n3376) );
AOI22X1TS U4178 ( .A0(n3367), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B1(n5982), .Y(n3370) );
AOI32X1TS U4179 ( .A0(n5991), .A1(n3368), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B1(n5911), .Y(n3369) );
OAI32X1TS U4180 ( .A0(n3372), .A1(n3371), .A2(n3370), .B0(n3369), .B1(n3371),
.Y(n3375) );
OAI21XLTS U4181 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .A1(n5909), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .Y(n3373) );
OAI2BB2XLTS U4182 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .B1(
n3373), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .A1N(n5909),
.Y(n3374) );
NOR2BX1TS U4183 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .Y(n3379) );
OR4X2TS U4184 ( .A(n3381), .B(n3380), .C(n3379), .D(n3378), .Y(n3382) );
AOI32X1TS U4185 ( .A0(n3385), .A1(n3384), .A2(n3383), .B0(n3382), .B1(n3385),
.Y(n3454) );
NOR2XLTS U4186 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[56]), .B(n3386),
.Y(n3387) );
AOI22X1TS U4187 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .A1(n3387), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[57]), .B1(n5935), .Y(n3391) );
AOI32X1TS U4188 ( .A0(n3388), .A1(n5905), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[58]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[59]), .B1(n5949), .Y(n3389) );
OA21XLTS U4189 ( .A0(n3391), .A1(n3390), .B0(n3389), .Y(n3397) );
OAI211XLTS U4190 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]), .A1(
n5985), .B0(n3394), .C0(n3393), .Y(n3395) );
OAI2BB2XLTS U4191 ( .B0(n3398), .B1(n3397), .A0N(n3396), .A1N(n3395), .Y(
n3453) );
NOR2BX1TS U4192 ( .AN(n3399), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[46]),
.Y(n3413) );
NOR2XLTS U4193 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[44]), .B(n3400),
.Y(n3401) );
AOI22X1TS U4194 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[44]), .A1(n3401), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .B1(n5993), .Y(n3410) );
OAI21XLTS U4195 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .A1(n5966), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .Y(n3402) );
OAI2BB2XLTS U4196 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[40]), .B1(
n3402), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .A1N(n5966),
.Y(n3406) );
OAI21XLTS U4197 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .A1(n6010), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]), .Y(n3403) );
OAI2BB2XLTS U4198 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[42]), .B1(
n3403), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .A1N(n6010),
.Y(n3404) );
AOI32X1TS U4199 ( .A0(n3407), .A1(n3406), .A2(n3405), .B0(n3404), .B1(n3407),
.Y(n3408) );
NOR2BX1TS U4200 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[47]), .Y(n3411) );
OAI21XLTS U4201 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[37]), .A1(n5933), .B0(n3415), .Y(n3424) );
INVX2TS U4202 ( .A(n3416), .Y(n3422) );
OAI21XLTS U4203 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .A1(n5970), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .Y(n3417) );
OAI2BB2XLTS U4204 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[32]), .B1(
n3417), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .A1N(n5970),
.Y(n3421) );
OAI21XLTS U4205 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .A1(n5910), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]), .Y(n3418) );
OAI2BB2XLTS U4206 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[34]), .B1(
n3418), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .A1N(n5910),
.Y(n3419) );
AOI32X1TS U4207 ( .A0(n3422), .A1(n3421), .A2(n3420), .B0(n3419), .B1(n3422),
.Y(n3423) );
OAI2BB1X1TS U4208 ( .A0N(n3425), .A1N(n3424), .B0(n3423), .Y(n3430) );
NOR3XLTS U4209 ( .A(n6092), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[38]),
.C(n3426), .Y(n3429) );
NOR2BX1TS U4210 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[39]), .Y(n3428) );
OAI31X1TS U4211 ( .A0(n3430), .A1(n3429), .A2(n3428), .B0(n3427), .Y(n3448)
);
OAI21XLTS U4212 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .A1(n6003), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .Y(n3431) );
NOR2XLTS U4213 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[48]), .B(n3435),
.Y(n3436) );
AOI22X1TS U4214 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[48]), .A1(n3436), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]), .B1(n6009), .Y(n3439) );
AOI32X1TS U4215 ( .A0(n3437), .A1(n5908), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .B1(n5998), .Y(n3438) );
OAI32X1TS U4216 ( .A0(n3441), .A1(n3440), .A2(n3439), .B0(n3438), .B1(n3440),
.Y(n3445) );
OAI21XLTS U4217 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .A1(n6011), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .Y(n3442) );
OAI2BB2XLTS U4218 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[54]), .B1(
n3442), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .A1N(n6011),
.Y(n3444) );
OAI31X1TS U4219 ( .A0(n3446), .A1(n3445), .A2(n3444), .B0(n3443), .Y(n3447)
);
CLKBUFX2TS U4220 ( .A(n6039), .Y(n4118) );
CLKBUFX2TS U4221 ( .A(n4013), .Y(n4034) );
CLKBUFX2TS U4222 ( .A(n3668), .Y(n4032) );
CLKBUFX2TS U4223 ( .A(n6039), .Y(n5823) );
CLKBUFX2TS U4224 ( .A(n5823), .Y(n4048) );
CLKBUFX2TS U4225 ( .A(n4048), .Y(n4031) );
AOI22X1TS U4226 ( .A0(n4032), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[37]), .B1(n4031), .Y(n3456) );
CLKBUFX2TS U4227 ( .A(n4048), .Y(n4301) );
AOI22X1TS U4228 ( .A0(n4032), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[39]), .B1(n4301), .Y(n3457) );
CLKBUFX2TS U4229 ( .A(n4048), .Y(n4041) );
AOI22X1TS U4230 ( .A0(n4032), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]), .B1(n4041), .Y(n3458) );
CLKBUFX2TS U4231 ( .A(n4016), .Y(n4040) );
CLKBUFX2TS U4232 ( .A(n6039), .Y(n4051) );
AOI22X1TS U4233 ( .A0(n4057), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]), .B1(n4051), .Y(n3459) );
AOI22X1TS U4234 ( .A0(n4057), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]), .B1(n4051), .Y(n3460) );
AOI22X1TS U4235 ( .A0(n4057), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]), .B1(n4051), .Y(n3461) );
INVX2TS U4236 ( .A(n4038), .Y(n4121) );
INVX2TS U4237 ( .A(n4016), .Y(n4119) );
AOI22X1TS U4238 ( .A0(n4119), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[53]), .B1(n4118), .Y(n3462) );
INVX2TS U4239 ( .A(n4038), .Y(n3734) );
INVX2TS U4240 ( .A(n4016), .Y(n3890) );
AOI22X1TS U4241 ( .A0(n3890), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[46]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[46]), .B1(n4301), .Y(n3463) );
INVX2TS U4242 ( .A(n4016), .Y(n4042) );
AOI22X1TS U4243 ( .A0(n4042), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[43]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[43]), .B1(n4301), .Y(n3464) );
CLKBUFX2TS U4244 ( .A(n6039), .Y(n4026) );
AOI22X1TS U4245 ( .A0(n3890), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[47]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[47]), .B1(n4026), .Y(n3465) );
AOI22X1TS U4246 ( .A0(n3890), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[49]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[49]), .B1(n4026), .Y(n3466) );
AOI22X1TS U4247 ( .A0(n4042), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[28]), .B1(n4031), .Y(n3467) );
AOI22X1TS U4248 ( .A0(n3890), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[51]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[51]), .B1(n4026), .Y(n3468) );
AOI22X1TS U4249 ( .A0(n4042), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[40]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[40]), .B1(n4031), .Y(n3469) );
AOI22X1TS U4250 ( .A0(n3890), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[42]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[42]), .B1(n4301), .Y(n3470) );
AOI22X1TS U4251 ( .A0(n3890), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[34]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[34]), .B1(n4301), .Y(n3471) );
AOI22X1TS U4252 ( .A0(n4042), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[36]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[36]), .B1(n4301), .Y(n3472) );
AOI22X1TS U4253 ( .A0(n4042), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[32]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[32]), .B1(n4031), .Y(n3473) );
AOI22X1TS U4254 ( .A0(n4042), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[30]), .B1(n4031), .Y(n3474) );
CLKBUFX2TS U4255 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n5874) );
CLKBUFX2TS U4256 ( .A(n6094), .Y(n4347) );
INVX2TS U4257 ( .A(n4347), .Y(n5771) );
NOR2X1TS U4258 ( .A(n5874), .B(n5771), .Y(n4283) );
INVX2TS U4259 ( .A(n4283), .Y(n4296) );
CLKBUFX2TS U4260 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n4080) );
INVX2TS U4261 ( .A(n4080), .Y(n4320) );
CLKBUFX2TS U4262 ( .A(n4185), .Y(n4069) );
INVX2TS U4263 ( .A(n4069), .Y(n4082) );
AOI21X1TS U4264 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]),
.A1(n5900), .B0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(
n3512) );
NOR2X1TS U4265 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[53]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[52]), .Y(n3476) );
NOR2X1TS U4266 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[51]), .Y(n3475) );
NOR2X2TS U4267 ( .A(n3501), .B(n3506), .Y(n3553) );
NAND2X2TS U4268 ( .A(n3477), .B(n3553), .Y(n3537) );
NAND2X2TS U4269 ( .A(n4154), .B(n3203), .Y(n3502) );
NOR2X1TS U4270 ( .A(n3480), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n4157) );
NAND2X1TS U4271 ( .A(n5926), .B(n5900), .Y(n3481) );
NAND2X2TS U4272 ( .A(n4160), .B(n5932), .Y(n3544) );
AOI21X1TS U4273 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .A1(
n5901), .B0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n3484) );
AOI21X1TS U4274 ( .A0(n3205), .A1(n5939), .B0(n3537), .Y(n3482) );
AOI21X1TS U4275 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]),
.A1(n3509), .B0(n3482), .Y(n3483) );
OA21XLTS U4276 ( .A0(n4177), .A1(n3484), .B0(n3483), .Y(n4163) );
AOI21X1TS U4277 ( .A0(n5939), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[39]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[41]), .Y(n3487) );
OAI31X1TS U4278 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[42]),
.A1(n3487), .A2(n3537), .B0(n3486), .Y(n3488) );
AOI22X1TS U4279 ( .A0(n3493), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[27]), .B0(n3492), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[31]), .Y(n3524) );
AOI22X1TS U4280 ( .A0(n3494), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]), .B0(n3553), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]), .Y(n3497) );
NAND2X1TS U4281 ( .A(n3495), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .Y(n3496) );
NAND4X2TS U4282 ( .A(n4164), .B(n3524), .C(n3497), .D(n3496), .Y(n3498) );
OAI32X1TS U4283 ( .A0(n3498), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .A2(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B0(n4169), .B1(
n3498), .Y(n3499) );
OAI31X1TS U4284 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]),
.A1(n3500), .A2(n5924), .B0(n3499), .Y(n3563) );
OAI211XLTS U4285 ( .A0(n3507), .A1(n3506), .B0(n3541), .C0(n3505), .Y(n3508)
);
AOI211XLTS U4286 ( .A0(n3509), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(n3563), .C0(
n3508), .Y(n3510) );
INVX2TS U4287 ( .A(n4296), .Y(n5554) );
AOI22X1TS U4288 ( .A0(n4082), .A1(n5223), .B0(n4183), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n3513) );
INVX2TS U4289 ( .A(n4296), .Y(n5559) );
NAND2X1TS U4290 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .B(
n5891), .Y(n4174) );
NAND2X1TS U4291 ( .A(n5936), .B(n5901), .Y(n4173) );
NOR4X2TS U4292 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .C(n4173), .D(n4177),
.Y(n3751) );
NAND2X2TS U4293 ( .A(n3751), .B(n5941), .Y(n3557) );
INVX2TS U4294 ( .A(n3514), .Y(n3516) );
NOR2XLTS U4295 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n3517) );
AOI22X1TS U4296 ( .A0(n3554), .A1(n3522), .B0(n3521), .B1(n3520), .Y(n3523)
);
OAI211X1TS U4297 ( .A0(n4174), .A1(n3557), .B0(n3524), .C0(n3523), .Y(n3749)
);
NOR2XLTS U4298 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n3526) );
NOR2XLTS U4299 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n3527) );
AOI22X1TS U4300 ( .A0(n4166), .A1(n3530), .B0(n3529), .B1(n3528), .Y(n4176)
);
OAI21XLTS U4301 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[44]),
.A1(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]), .B0(n3531), .Y(
n3532) );
AOI211XLTS U4302 ( .A0(n3534), .A1(n3533), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[52]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[51]), .Y(n3535) );
NOR3XLTS U4303 ( .A(n3535), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[53]), .Y(n3539) );
NOR4XLTS U4304 ( .A(n3537), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[41]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[42]), .D(n3536), .Y(n3538) );
AOI211X1TS U4305 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]),
.A1(n5873), .B0(n5559), .C0(n3568), .Y(n3565) );
CLKBUFX2TS U4306 ( .A(n3634), .Y(n4295) );
INVX2TS U4307 ( .A(n4295), .Y(n4294) );
AOI32X1TS U4308 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(
n4181), .A2(n5947), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n4181), .Y(n3549) );
NOR2XLTS U4309 ( .A(n3546), .B(n5952), .Y(n3743) );
OAI211X1TS U4310 ( .A0(n3747), .A1(n5946), .B0(n3549), .C0(n3548), .Y(n4158)
);
AOI21X1TS U4311 ( .A0(n5956), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[49]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[51]), .Y(n3550) );
AOI31XLTS U4312 ( .A0(n3553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45]), .A2(n5957), .B0(
n3552), .Y(n3561) );
NOR2BX1TS U4313 ( .AN(n3554), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[36]), .Y(n3744) );
AOI21X1TS U4314 ( .A0(n5948), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n3555) );
NOR3XLTS U4315 ( .A(n4170), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .C(n3555), .Y(n3556) );
AOI21X1TS U4316 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[35]),
.A1(n3744), .B0(n3556), .Y(n3560) );
OR2X4TS U4317 ( .A(n3557), .B(n5891), .Y(n4175) );
OAI31X1TS U4318 ( .A0(n4158), .A1(n3563), .A2(n3562), .B0(n5874), .Y(n4374)
);
OAI211X1TS U4319 ( .A0(n5874), .A1(n5920), .B0(n4294), .C0(n4374), .Y(n4232)
);
CLKBUFX2TS U4320 ( .A(n3634), .Y(n4216) );
CLKBUFX2TS U4321 ( .A(n4185), .Y(n4071) );
OAI22X1TS U4322 ( .A0(n4071), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45]), .B0(n4080), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n3564) );
AOI21X1TS U4323 ( .A0(n4216), .A1(n6025), .B0(n3564), .Y(n4200) );
INVX2TS U4324 ( .A(n4200), .Y(n4229) );
INVX2TS U4325 ( .A(n3566), .Y(n3587) );
INVX2TS U4326 ( .A(n4290), .Y(n5555) );
INVX2TS U4327 ( .A(n4071), .Y(n5560) );
INVX2TS U4328 ( .A(n4080), .Y(n4073) );
AOI22X1TS U4329 ( .A0(n5560), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[46]), .B0(n4073), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n3567) );
AOI22X1TS U4330 ( .A0(n5559), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B0(n5555), .B1(n4224),
.Y(n3572) );
OR2X4TS U4331 ( .A(n4335), .B(n4234), .Y(n3609) );
INVX2TS U4332 ( .A(n3609), .Y(n5564) );
OAI22X1TS U4333 ( .A0(n4071), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]), .B0(n4080), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n3569) );
AOI21X1TS U4334 ( .A0(n4216), .A1(n6028), .B0(n3569), .Y(n4219) );
INVX2TS U4335 ( .A(n4273), .Y(n4338) );
AOI22X1TS U4336 ( .A0(n5560), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[44]), .B0(n4073), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n3570) );
AOI22X1TS U4337 ( .A0(n5564), .A1(n4219), .B0(n4338), .B1(n4226), .Y(n3571)
);
OAI211XLTS U4338 ( .A0(n4373), .A1(n4229), .B0(n3572), .C0(n3571), .Y(n2514)
);
AOI22X1TS U4339 ( .A0(n5560), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[42]), .B0(n4073), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n3574) );
CLKBUFX2TS U4340 ( .A(n3634), .Y(n4083) );
NAND2X1TS U4341 ( .A(n4083), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .Y(n3573) );
NAND2X1TS U4342 ( .A(n3574), .B(n3573), .Y(n4062) );
INVX2TS U4343 ( .A(n4062), .Y(n4223) );
INVX2TS U4344 ( .A(n4296), .Y(n4355) );
AOI22X1TS U4345 ( .A0(n4355), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .B0(n5555), .B1(n4219), .Y(n3578) );
AOI22X1TS U4346 ( .A0(n5560), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40]), .B0(n4073), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n3575) );
OAI22X1TS U4347 ( .A0(n4071), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[41]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n3576) );
AOI21X1TS U4348 ( .A0(n4216), .A1(n5900), .B0(n3576), .Y(n4220) );
AOI22X1TS U4349 ( .A0(n5564), .A1(n4349), .B0(n4338), .B1(n4220), .Y(n3577)
);
OAI211XLTS U4350 ( .A0(n4223), .A1(n4373), .B0(n3578), .C0(n3577), .Y(n2517)
);
INVX2TS U4351 ( .A(n4069), .Y(n4207) );
AOI22X1TS U4352 ( .A0(n4207), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]), .B0(n4073), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n3580) );
NAND2X1TS U4353 ( .A(n4083), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n3579) );
NAND2X1TS U4354 ( .A(n3580), .B(n3579), .Y(n4331) );
INVX2TS U4355 ( .A(n4331), .Y(n4241) );
INVX2TS U4356 ( .A(n4296), .Y(n4330) );
INVX2TS U4357 ( .A(n4290), .Y(n4357) );
INVX2TS U4358 ( .A(n4083), .Y(n3629) );
OAI22X1TS U4359 ( .A0(n3629), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n3581) );
AOI21X1TS U4360 ( .A0(n4082), .A1(n6037), .B0(n3581), .Y(n4250) );
AOI22X1TS U4361 ( .A0(n4330), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .B0(n4357), .B1(n4250), .Y(n3585) );
INVX2TS U4362 ( .A(n3609), .Y(n4359) );
INVX2TS U4363 ( .A(n4080), .Y(n4209) );
AOI22X1TS U4364 ( .A0(n4207), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]), .B0(n4209), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[24]), .Y(n3582) );
OAI2BB1X1TS U4365 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[26]),
.A1N(n4083), .B0(n3582), .Y(n4323) );
INVX2TS U4366 ( .A(n3210), .Y(n5562) );
AOI22X1TS U4367 ( .A0(n4207), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]), .B0(n4209), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[23]), .Y(n3583) );
AOI22X1TS U4368 ( .A0(n4359), .A1(n4323), .B0(n5562), .B1(n4328), .Y(n3584)
);
OAI211XLTS U4369 ( .A0(n4241), .A1(n4373), .B0(n3585), .C0(n3584), .Y(n2529)
);
OAI22X1TS U4370 ( .A0(n4071), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(n4080), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[29]), .Y(n3586) );
AO21XLTS U4371 ( .A0(n4216), .A1(n6037), .B0(n3586), .Y(n4249) );
INVX2TS U4372 ( .A(n3587), .Y(n4364) );
INVX2TS U4373 ( .A(n4069), .Y(n4215) );
OAI22X1TS U4374 ( .A0(n4211), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[28]), .Y(n3588) );
AOI21X1TS U4375 ( .A0(n4215), .A1(n5923), .B0(n3588), .Y(n4245) );
AOI22X1TS U4376 ( .A0(n4330), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .B0(n4364), .B1(n4245), .Y(n3592) );
INVX2TS U4377 ( .A(n3609), .Y(n4369) );
OAI22X1TS U4378 ( .A0(n3629), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .B0(n5874), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[31]), .Y(n3589) );
INVX2TS U4379 ( .A(n3210), .Y(n4367) );
AOI22X1TS U4380 ( .A0(n4215), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(n4209), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[30]), .Y(n3590) );
AOI22X1TS U4381 ( .A0(n4369), .A1(n4255), .B0(n4367), .B1(n4246), .Y(n3591)
);
OAI211XLTS U4382 ( .A0(n4373), .A1(n4249), .B0(n3592), .C0(n3591), .Y(n2536)
);
OAI22X1TS U4383 ( .A0(n4071), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[33]), .Y(n3594) );
NOR2XLTS U4384 ( .A(n3629), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[35]), .Y(n3593) );
INVX2TS U4385 ( .A(n4191), .Y(n4260) );
INVX2TS U4386 ( .A(n4296), .Y(n4365) );
AOI22X1TS U4387 ( .A0(n4215), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n4209), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[32]), .Y(n3595) );
AOI22X1TS U4388 ( .A0(n4365), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .B0(n4364), .B1(n4256), .Y(n3599) );
CLKBUFX2TS U4389 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n5221) );
OAI22X1TS U4390 ( .A0(n3629), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[37]), .B0(n5221), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[35]), .Y(n3596) );
AOI21X1TS U4391 ( .A0(n4082), .A1(n6033), .B0(n3596), .Y(n4192) );
AOI22X1TS U4392 ( .A0(n4215), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .B0(n4209), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[34]), .Y(n3597) );
OAI2BB1X1TS U4393 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[36]),
.A1N(n3634), .B0(n3597), .Y(n4257) );
AOI22X1TS U4394 ( .A0(n4369), .A1(n4192), .B0(n4367), .B1(n4257), .Y(n3598)
);
OAI211XLTS U4395 ( .A0(n4373), .A1(n4260), .B0(n3599), .C0(n3598), .Y(n2540)
);
OAI22X1TS U4396 ( .A0(n4071), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .B0(n4080), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n3601) );
NOR2XLTS U4397 ( .A(n3629), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n3600) );
INVX2TS U4398 ( .A(n4358), .Y(n4254) );
AOI22X1TS U4399 ( .A0(n4207), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[32]), .B0(n4073), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n3602) );
AOI22X1TS U4400 ( .A0(n4330), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .B0(n5562), .B1(n4251), .Y(n3605) );
AOI22X1TS U4401 ( .A0(n4207), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]), .B0(n4073), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n3603) );
AOI22X1TS U4402 ( .A0(n4359), .A1(n4250), .B0(n4357), .B1(n4354), .Y(n3604)
);
OAI211XLTS U4403 ( .A0(n4373), .A1(n4254), .B0(n3605), .C0(n3604), .Y(n2526)
);
AOI22X1TS U4404 ( .A0(n4216), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[48]), .B0(n5906), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[46]), .Y(n3607) );
NAND2X1TS U4405 ( .A(n5560), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n3606) );
CLKAND2X2TS U4406 ( .A(n3607), .B(n3606), .Y(n4267) );
INVX2TS U4407 ( .A(n3210), .Y(n4282) );
OAI22X1TS U4408 ( .A0(n3629), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[49]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[47]), .Y(n3608) );
AOI21X1TS U4409 ( .A0(n4082), .A1(n5901), .B0(n3608), .Y(n4264) );
AOI22X1TS U4410 ( .A0(n4283), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .B0(n4282), .B1(n4264), .Y(n3613) );
INVX2TS U4411 ( .A(n4214), .Y(n4286) );
AOI22X1TS U4412 ( .A0(n4207), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n5906), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[48]), .Y(n3610) );
OAI2BB1X1TS U4413 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]),
.A1N(n3634), .B0(n3610), .Y(n4268) );
INVX2TS U4414 ( .A(n3587), .Y(n4324) );
OAI22X1TS U4415 ( .A0(n3629), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]), .B0(n5221), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[45]), .Y(n3611) );
AOI21X1TS U4416 ( .A0(n4082), .A1(n6034), .B0(n3611), .Y(n4263) );
AOI22X1TS U4417 ( .A0(n4286), .A1(n4268), .B0(n4324), .B1(n4263), .Y(n3612)
);
OAI211XLTS U4418 ( .A0(n4267), .A1(n4373), .B0(n3613), .C0(n3612), .Y(n2553)
);
AOI22X1TS U4419 ( .A0(n4216), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[52]), .B0(n5906), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[50]), .Y(n3615) );
NAND2X1TS U4420 ( .A(n5560), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n3614) );
CLKAND2X2TS U4421 ( .A(n3615), .B(n3614), .Y(n4274) );
AOI22X1TS U4422 ( .A0(n5560), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n5906), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[49]), .Y(n3616) );
OAI2BB1X1TS U4423 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[51]),
.A1N(n4295), .B0(n3616), .Y(n4269) );
AOI22X1TS U4424 ( .A0(n4283), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[51]), .B0(n4324), .B1(n4269), .Y(n3619) );
OA22X1TS U4425 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(
n4069), .B0(n4294), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]), .Y(n5556) );
AOI22X1TS U4426 ( .A0(n4295), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[53]), .B0(n4320), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[51]), .Y(n3617) );
OAI21XLTS U4427 ( .A0(n5891), .A1(n4185), .B0(n3617), .Y(n4270) );
AOI22X1TS U4428 ( .A0(n4286), .A1(n5556), .B0(n4338), .B1(n4270), .Y(n3618)
);
OAI211XLTS U4429 ( .A0(n4274), .A1(n4373), .B0(n3619), .C0(n3618), .Y(n2557)
);
OAI22X1TS U4430 ( .A0(n4069), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B0(n5221), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[39]), .Y(n3621) );
INVX2TS U4431 ( .A(n4368), .Y(n4289) );
AOI22X1TS U4432 ( .A0(n4215), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .B0(n4073), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[38]), .Y(n3622) );
OAI2BB1X1TS U4433 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40]),
.A1N(n4083), .B0(n3622), .Y(n4366) );
AOI22X1TS U4434 ( .A0(n5554), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .B0(n4324), .B1(n4366), .Y(n3627) );
OAI22X1TS U4435 ( .A0(n4071), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .B0(n5221), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[41]), .Y(n3624) );
NOR2XLTS U4436 ( .A(n3629), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]), .Y(n3623) );
AOI22X1TS U4437 ( .A0(n4215), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n4209), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[40]), .Y(n3625) );
OAI2BB1X1TS U4438 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[42]),
.A1N(n3634), .B0(n3625), .Y(n4284) );
AOI22X1TS U4439 ( .A0(n4286), .A1(n4281), .B0(n4282), .B1(n4284), .Y(n3626)
);
OAI211XLTS U4440 ( .A0(n4373), .A1(n4289), .B0(n3627), .C0(n3626), .Y(n2546)
);
INVX2TS U4441 ( .A(n4281), .Y(n4280) );
AOI22X1TS U4442 ( .A0(n4216), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[44]), .B0(n4209), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[42]), .Y(n3628) );
OAI21XLTS U4443 ( .A0(n5932), .A1(n4185), .B0(n3628), .Y(n4285) );
AOI22X1TS U4444 ( .A0(n4365), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B0(n4282), .B1(n4285), .Y(n3632) );
OAI22X1TS U4445 ( .A0(n3629), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45]), .B0(n5221), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[43]), .Y(n3630) );
AOI21X1TS U4446 ( .A0(n4082), .A1(n6025), .B0(n3630), .Y(n4275) );
AOI22X1TS U4447 ( .A0(n4286), .A1(n4275), .B0(n4324), .B1(n4284), .Y(n3631)
);
OAI211XLTS U4448 ( .A0(n3195), .A1(n4280), .B0(n3632), .C0(n3631), .Y(n2548)
);
INVX2TS U4449 ( .A(n4275), .Y(n3637) );
AOI22X1TS U4450 ( .A0(n4365), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .B0(n4324), .B1(n4285), .Y(n3636) );
AOI22X1TS U4451 ( .A0(n4215), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .B0(n5906), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[44]), .Y(n3633) );
OAI2BB1X1TS U4452 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[46]),
.A1N(n3634), .B0(n3633), .Y(n4277) );
AOI22X1TS U4453 ( .A0(n4286), .A1(n4263), .B0(n4282), .B1(n4277), .Y(n3635)
);
OAI211XLTS U4454 ( .A0(n3195), .A1(n3637), .B0(n3636), .C0(n3635), .Y(n2550)
);
CLKBUFX2TS U4455 ( .A(n3668), .Y(n4302) );
AOI22X1TS U4456 ( .A0(n4302), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[59]), .B1(n4118), .Y(n3638) );
AOI22X1TS U4457 ( .A0(n4302), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[60]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[60]), .B1(n4118), .Y(n3639) );
NAND2X1TS U4458 ( .A(cont_iter_out[3]), .B(n3180), .Y(n4112) );
NOR3XLTS U4459 ( .A(n5899), .B(n5960), .C(n4112), .Y(n3642) );
NOR3XLTS U4460 ( .A(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n3650), .Y(n3641) );
OAI21XLTS U4461 ( .A0(n3642), .A1(n3644), .B0(n3899), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
NOR4XLTS U4462 ( .A(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(inst_CORDIC_FSM_v3_state_reg[1]),
.D(inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3720) );
INVX2TS U4463 ( .A(ready_cordic), .Y(n3901) );
INVX2TS U4464 ( .A(n3644), .Y(n5258) );
NAND2X1TS U4465 ( .A(n5258), .B(cont_iter_out[0]), .Y(n5259) );
INVX2TS U4466 ( .A(n4112), .Y(n5262) );
NAND2X1TS U4467 ( .A(n3176), .B(n5928), .Y(n5305) );
INVX2TS U4468 ( .A(n5277), .Y(n4103) );
CLKBUFX2TS U4469 ( .A(n5374), .Y(n5295) );
CLKBUFX2TS U4470 ( .A(n5374), .Y(n5741) );
INVX2TS U4471 ( .A(n5311), .Y(n5284) );
NOR2XLTS U4472 ( .A(n5928), .B(n5284), .Y(n5273) );
AOI22X1TS U4473 ( .A0(d_ff3_LUT_out[6]), .A1(n5295), .B0(n5273), .B1(n5960),
.Y(n3646) );
CLKBUFX2TS U4474 ( .A(n3668), .Y(n4028) );
AOI22X1TS U4475 ( .A0(n4028), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]), .B1(n4041), .Y(n3647) );
OAI21XLTS U4476 ( .A0(n5911), .A1(n4034), .B0(n3647), .Y(n2020) );
AOI22X1TS U4477 ( .A0(n4032), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]), .B1(n4031), .Y(n3648) );
OAI21XLTS U4478 ( .A0(n5975), .A1(n4034), .B0(n3648), .Y(n2114) );
AOI22X1TS U4479 ( .A0(n4032), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[41]), .B1(n4301), .Y(n3649) );
OAI21XLTS U4480 ( .A0(n5966), .A1(n4034), .B0(n3649), .Y(n2132) );
OR3X1TS U4481 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .C(n3650), .Y(n3898) );
NOR3X1TS U4482 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(n5950), .C(n3898),
.Y(n5435) );
CLKBUFX2TS U4483 ( .A(n5435), .Y(n5412) );
CLKBUFX2TS U4484 ( .A(n5412), .Y(n6246) );
INVX2TS U4485 ( .A(n4057), .Y(n4133) );
INVX2TS U4486 ( .A(n4021), .Y(n4131) );
CLKBUFX2TS U4487 ( .A(n6039), .Y(n4136) );
AOI22X1TS U4488 ( .A0(n4131), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]), .B1(n4136), .Y(n3651) );
OAI21XLTS U4489 ( .A0(n5915), .A1(n4133), .B0(n3651), .Y(n1850) );
AOI22X1TS U4490 ( .A0(n4131), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]), .B1(n4051), .Y(n3652) );
OAI21XLTS U4491 ( .A0(n5968), .A1(n4133), .B0(n3652), .Y(n1871) );
INVX2TS U4492 ( .A(n4021), .Y(n4123) );
AOI22X1TS U4493 ( .A0(n4123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]), .B1(n4051), .Y(n3653) );
OAI21XLTS U4494 ( .A0(n5964), .A1(n4133), .B0(n3653), .Y(n1878) );
INVX2TS U4495 ( .A(n4057), .Y(n4143) );
CLKBUFX2TS U4496 ( .A(n4013), .Y(n4304) );
INVX2TS U4497 ( .A(n4304), .Y(n4149) );
AOI22X1TS U4498 ( .A0(n4149), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[37]), .B1(n4136), .Y(n3654) );
OAI21XLTS U4499 ( .A0(n5965), .A1(n4143), .B0(n3654), .Y(n1818) );
CLKBUFX2TS U4500 ( .A(n6039), .Y(n4148) );
AOI22X1TS U4501 ( .A0(n4149), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[39]), .B1(n4148), .Y(n3655) );
OAI21XLTS U4502 ( .A0(n5976), .A1(n4143), .B0(n3655), .Y(n1802) );
OA22X1TS U4503 ( .A0(n4069), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[49]), .B0(n5874), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n3657) );
OAI21XLTS U4504 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(
n4211), .B0(n3657), .Y(n4342) );
OAI22X1TS U4505 ( .A0(n4069), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[51]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n3658) );
AOI21X1TS U4506 ( .A0(n4216), .A1(n6029), .B0(n3658), .Y(n5563) );
AOI22X1TS U4507 ( .A0(n5559), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]), .B0(n5555), .B1(n5563),
.Y(n3662) );
AOI22X1TS U4508 ( .A0(n4207), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[48]), .B0(n4320), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n3659) );
AOI22X1TS U4509 ( .A0(n5560), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]), .B0(n4320), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n3660) );
OAI2BB1X1TS U4510 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]),
.A1N(n4083), .B0(n3660), .Y(n4336) );
AOI22X1TS U4511 ( .A0(n5564), .A1(n4337), .B0(n4225), .B1(n4336), .Y(n3661)
);
OAI211XLTS U4512 ( .A0(n3210), .A1(n4342), .B0(n3662), .C0(n3661), .Y(n2509)
);
OA22X1TS U4513 ( .A0(n4069), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(n5874), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[37]), .Y(n3663) );
OAI21XLTS U4514 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[39]),
.A1(n4294), .B0(n3663), .Y(n4372) );
AOI22X1TS U4515 ( .A0(n4283), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .B0(n4367), .B1(n4368), .Y(n3665) );
AOI22X1TS U4516 ( .A0(n4369), .A1(n4284), .B0(n4329), .B1(n4366), .Y(n3664)
);
CLKBUFX2TS U4517 ( .A(n6041), .Y(n4639) );
CLKBUFX2TS U4518 ( .A(n5370), .Y(n5362) );
INVX2TS U4519 ( .A(n5362), .Y(n4110) );
INVX2TS U4520 ( .A(n5366), .Y(n5302) );
NAND2X1TS U4521 ( .A(n5302), .B(n5305), .Y(n5269) );
NAND2X1TS U4522 ( .A(cont_iter_out[1]), .B(n5302), .Y(n4298) );
AOI22X1TS U4523 ( .A0(n4038), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]), .B1(n6039), .Y(n3666) );
OAI21XLTS U4524 ( .A0(n5972), .A1(n4040), .B0(n3666), .Y(n1928) );
AOI22X1TS U4525 ( .A0(n4119), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56]), .B1(n4026), .Y(n3667) );
OAI21XLTS U4526 ( .A0(n5914), .A1(n4121), .B0(n3667), .Y(n2253) );
CLKBUFX2TS U4527 ( .A(n3668), .Y(n4014) );
AOI222XLTS U4528 ( .A0(n4119), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[52]), .B1(n5823), .C0(n4014),
.C1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .Y(n3669) );
INVX2TS U4529 ( .A(n3669), .Y(n2257) );
AOI222XLTS U4530 ( .A0(n4119), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[52]), .B1(n5823), .C0(n4014),
.C1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .Y(n3670) );
INVX2TS U4531 ( .A(n3670), .Y(n2191) );
AOI222XLTS U4532 ( .A0(n4119), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[54]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[54]), .B1(n5823), .C0(n4014),
.C1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .Y(n3671) );
INVX2TS U4533 ( .A(n3671), .Y(n2189) );
AOI222XLTS U4534 ( .A0(n4119), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[55]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[55]), .B1(n5823), .C0(n4014),
.C1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .Y(n3672) );
INVX2TS U4535 ( .A(n3672), .Y(n2188) );
AOI222XLTS U4536 ( .A0(n4119), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[53]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[53]), .B1(n4118), .C0(n4014),
.C1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .Y(n3673) );
INVX2TS U4537 ( .A(n3673), .Y(n2190) );
AOI22X1TS U4538 ( .A0(n3890), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[48]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[48]), .B1(n4026), .Y(n3674) );
OAI21XLTS U4539 ( .A0(n6081), .A1(n4121), .B0(n3674), .Y(n2168) );
AOI22X1TS U4540 ( .A0(n3890), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[44]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[44]), .B1(n4031), .Y(n3675) );
OAI21XLTS U4541 ( .A0(n6080), .A1(n4121), .B0(n3675), .Y(n2162) );
AOI22X1TS U4542 ( .A0(n4123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]), .B1(n4051), .Y(n3676) );
OAI21XLTS U4543 ( .A0(n5973), .A1(n4133), .B0(n3676), .Y(n1885) );
OA22X1TS U4544 ( .A0(n4069), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[39]), .B0(n5874), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n3677) );
OAI21XLTS U4545 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]),
.A1(n4211), .B0(n3677), .Y(n4353) );
AOI22X1TS U4546 ( .A0(n4355), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .B0(n4357), .B1(n4220), .Y(n3680) );
AOI22X1TS U4547 ( .A0(n4207), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[38]), .B0(n4073), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n3678) );
OAI2BB1X1TS U4548 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]),
.A1N(n4083), .B0(n3678), .Y(n4348) );
AOI22X1TS U4549 ( .A0(n4359), .A1(n4348), .B0(n4225), .B1(n4349), .Y(n3679)
);
OAI211XLTS U4550 ( .A0(n3210), .A1(n4353), .B0(n3680), .C0(n3679), .Y(n2519)
);
NAND2X1TS U4551 ( .A(n3901), .B(n3931), .Y(n5760) );
INVX2TS U4552 ( .A(n5760), .Y(n3753) );
CLKBUFX2TS U4553 ( .A(n3753), .Y(n3783) );
XNOR2X1TS U4554 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out), .Y(n3681) );
CLKBUFX2TS U4555 ( .A(n3761), .Y(n3771) );
CLKBUFX2TS U4556 ( .A(n3771), .Y(n3708) );
CLKBUFX2TS U4557 ( .A(n3796), .Y(n3785) );
CLKBUFX2TS U4558 ( .A(n3785), .Y(n3707) );
AOI222XLTS U4559 ( .A0(n3783), .A1(data_output[55]), .B0(n3708), .B1(
d_ff_Yn[55]), .C0(n3707), .C1(d_ff_Xn[55]), .Y(n3682) );
INVX2TS U4560 ( .A(n3682), .Y(n2285) );
CLKBUFX2TS U4561 ( .A(n3753), .Y(n3767) );
CLKBUFX2TS U4562 ( .A(n3771), .Y(n3713) );
CLKBUFX2TS U4563 ( .A(n3785), .Y(n3712) );
AOI222XLTS U4564 ( .A0(n3767), .A1(data_output[23]), .B0(n3713), .B1(
d_ff_Yn[23]), .C0(n3712), .C1(d_ff_Xn[23]), .Y(n3683) );
INVX2TS U4565 ( .A(n3683), .Y(n2317) );
AOI222XLTS U4566 ( .A0(n3783), .A1(data_output[54]), .B0(n3708), .B1(
d_ff_Yn[54]), .C0(n3707), .C1(d_ff_Xn[54]), .Y(n3684) );
INVX2TS U4567 ( .A(n3684), .Y(n2286) );
AOI222XLTS U4568 ( .A0(n3783), .A1(data_output[56]), .B0(n3708), .B1(
d_ff_Yn[56]), .C0(n3707), .C1(d_ff_Xn[56]), .Y(n3685) );
INVX2TS U4569 ( .A(n3685), .Y(n2284) );
CLKBUFX2TS U4570 ( .A(n3753), .Y(n3717) );
CLKBUFX2TS U4571 ( .A(n3771), .Y(n3716) );
CLKBUFX2TS U4572 ( .A(n3785), .Y(n3715) );
AOI222XLTS U4573 ( .A0(n3717), .A1(data_output[33]), .B0(n3716), .B1(
d_ff_Yn[33]), .C0(n3715), .C1(d_ff_Xn[33]), .Y(n3686) );
INVX2TS U4574 ( .A(n3686), .Y(n2307) );
AOI222XLTS U4575 ( .A0(n3717), .A1(data_output[29]), .B0(n3713), .B1(
d_ff_Yn[29]), .C0(n3712), .C1(d_ff_Xn[29]), .Y(n3687) );
INVX2TS U4576 ( .A(n3687), .Y(n2311) );
AOI222XLTS U4577 ( .A0(n3783), .A1(data_output[57]), .B0(n3708), .B1(
d_ff_Yn[57]), .C0(n3707), .C1(d_ff_Xn[57]), .Y(n3688) );
INVX2TS U4578 ( .A(n3688), .Y(n2283) );
AOI222XLTS U4579 ( .A0(n3767), .A1(data_output[22]), .B0(n3713), .B1(
d_ff_Yn[22]), .C0(n3712), .C1(d_ff_Xn[22]), .Y(n3689) );
INVX2TS U4580 ( .A(n3689), .Y(n2318) );
AOI222XLTS U4581 ( .A0(n3717), .A1(data_output[32]), .B0(n3716), .B1(
d_ff_Yn[32]), .C0(n3715), .C1(d_ff_Xn[32]), .Y(n3690) );
INVX2TS U4582 ( .A(n3690), .Y(n2308) );
AOI222XLTS U4583 ( .A0(n3717), .A1(data_output[28]), .B0(n3713), .B1(
d_ff_Yn[28]), .C0(n3712), .C1(d_ff_Xn[28]), .Y(n3691) );
INVX2TS U4584 ( .A(n3691), .Y(n2312) );
CLKBUFX2TS U4585 ( .A(n3753), .Y(n5761) );
AOI222XLTS U4586 ( .A0(n5761), .A1(data_output[58]), .B0(n3708), .B1(
d_ff_Yn[58]), .C0(n3707), .C1(d_ff_Xn[58]), .Y(n3692) );
INVX2TS U4587 ( .A(n3692), .Y(n2282) );
AOI222XLTS U4588 ( .A0(n3717), .A1(data_output[37]), .B0(n3716), .B1(
d_ff_Yn[37]), .C0(n3715), .C1(d_ff_Xn[37]), .Y(n3693) );
INVX2TS U4589 ( .A(n3693), .Y(n2303) );
AOI222XLTS U4590 ( .A0(n3767), .A1(data_output[25]), .B0(n3713), .B1(
d_ff_Yn[25]), .C0(n3712), .C1(d_ff_Xn[25]), .Y(n3694) );
INVX2TS U4591 ( .A(n3694), .Y(n2315) );
AOI222XLTS U4592 ( .A0(n3767), .A1(data_output[27]), .B0(n3713), .B1(
d_ff_Yn[27]), .C0(n3712), .C1(d_ff_Xn[27]), .Y(n3695) );
INVX2TS U4593 ( .A(n3695), .Y(n2313) );
AOI222XLTS U4594 ( .A0(n3717), .A1(data_output[30]), .B0(n3716), .B1(
d_ff_Yn[30]), .C0(n3715), .C1(d_ff_Xn[30]), .Y(n3696) );
INVX2TS U4595 ( .A(n3696), .Y(n2310) );
AOI222XLTS U4596 ( .A0(n3783), .A1(data_output[50]), .B0(n3708), .B1(
d_ff_Yn[50]), .C0(n3707), .C1(d_ff_Xn[50]), .Y(n3697) );
INVX2TS U4597 ( .A(n3697), .Y(n2290) );
AOI222XLTS U4598 ( .A0(n5761), .A1(data_output[59]), .B0(n3708), .B1(
d_ff_Yn[59]), .C0(n3707), .C1(d_ff_Xn[59]), .Y(n3698) );
INVX2TS U4599 ( .A(n3698), .Y(n2281) );
AOI222XLTS U4600 ( .A0(n3767), .A1(data_output[26]), .B0(n3713), .B1(
d_ff_Yn[26]), .C0(n3712), .C1(d_ff_Xn[26]), .Y(n3699) );
INVX2TS U4601 ( .A(n3699), .Y(n2314) );
CLKBUFX2TS U4602 ( .A(n3753), .Y(n3798) );
AOI222XLTS U4603 ( .A0(n3798), .A1(data_output[39]), .B0(n3716), .B1(
d_ff_Yn[39]), .C0(n3715), .C1(d_ff_Xn[39]), .Y(n3700) );
INVX2TS U4604 ( .A(n3700), .Y(n2301) );
AOI222XLTS U4605 ( .A0(n3767), .A1(data_output[20]), .B0(n3713), .B1(
d_ff_Yn[20]), .C0(n3712), .C1(d_ff_Xn[20]), .Y(n3701) );
INVX2TS U4606 ( .A(n3701), .Y(n2320) );
AOI222XLTS U4607 ( .A0(n3783), .A1(data_output[53]), .B0(n3708), .B1(
d_ff_Yn[53]), .C0(n3707), .C1(d_ff_Xn[53]), .Y(n3702) );
INVX2TS U4608 ( .A(n3702), .Y(n2287) );
AOI222XLTS U4609 ( .A0(n3717), .A1(data_output[36]), .B0(n3716), .B1(
d_ff_Yn[36]), .C0(n3715), .C1(d_ff_Xn[36]), .Y(n3703) );
INVX2TS U4610 ( .A(n3703), .Y(n2304) );
AOI222XLTS U4611 ( .A0(n3783), .A1(data_output[52]), .B0(n3708), .B1(
d_ff_Yn[52]), .C0(n3707), .C1(d_ff_Xn[52]), .Y(n3704) );
INVX2TS U4612 ( .A(n3704), .Y(n2288) );
AOI222XLTS U4613 ( .A0(n3717), .A1(data_output[34]), .B0(n3716), .B1(
d_ff_Yn[34]), .C0(n3715), .C1(d_ff_Xn[34]), .Y(n3705) );
INVX2TS U4614 ( .A(n3705), .Y(n2306) );
AOI222XLTS U4615 ( .A0(n3798), .A1(data_output[38]), .B0(n3716), .B1(
d_ff_Yn[38]), .C0(n3715), .C1(d_ff_Xn[38]), .Y(n3706) );
INVX2TS U4616 ( .A(n3706), .Y(n2302) );
AOI222XLTS U4617 ( .A0(n3783), .A1(data_output[51]), .B0(n3708), .B1(
d_ff_Yn[51]), .C0(n3707), .C1(d_ff_Xn[51]), .Y(n3709) );
INVX2TS U4618 ( .A(n3709), .Y(n2289) );
AOI222XLTS U4619 ( .A0(n3767), .A1(data_output[21]), .B0(n3713), .B1(
d_ff_Yn[21]), .C0(n3712), .C1(d_ff_Xn[21]), .Y(n3710) );
INVX2TS U4620 ( .A(n3710), .Y(n2319) );
AOI222XLTS U4621 ( .A0(n3717), .A1(data_output[35]), .B0(n3716), .B1(
d_ff_Yn[35]), .C0(n3715), .C1(d_ff_Xn[35]), .Y(n3711) );
INVX2TS U4622 ( .A(n3711), .Y(n2305) );
AOI222XLTS U4623 ( .A0(n3767), .A1(data_output[24]), .B0(n3713), .B1(
d_ff_Yn[24]), .C0(n3712), .C1(d_ff_Xn[24]), .Y(n3714) );
INVX2TS U4624 ( .A(n3714), .Y(n2316) );
AOI222XLTS U4625 ( .A0(n3717), .A1(data_output[31]), .B0(n3716), .B1(
d_ff_Yn[31]), .C0(n3715), .C1(d_ff_Xn[31]), .Y(n3718) );
INVX2TS U4626 ( .A(n3718), .Y(n2309) );
AOI22X1TS U4627 ( .A0(n4302), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[58]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[58]), .B1(n4118), .Y(n3719) );
OAI21XLTS U4628 ( .A0(n5989), .A1(n4016), .B0(n3719), .Y(n2251) );
NAND2X1TS U4629 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(
n5944), .Y(n5253) );
NAND2X1TS U4630 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
n5253), .Y(n4381) );
CLKBUFX2TS U4631 ( .A(n5585), .Y(n5745) );
CLKBUFX2TS U4632 ( .A(n3835), .Y(n5712) );
CLKBUFX2TS U4633 ( .A(n5712), .Y(n5493) );
CLKBUFX2TS U4634 ( .A(n5427), .Y(n5487) );
AOI22X1TS U4635 ( .A0(n5493), .A1(d_ff3_sh_y_out[34]), .B0(n5487), .B1(
d_ff3_sh_x_out[34]), .Y(n3722) );
NAND2X1TS U4636 ( .A(cont_var_out[1]), .B(cont_var_out[0]), .Y(n5250) );
CLKBUFX2TS U4637 ( .A(n5691), .Y(n5455) );
CLKBUFX2TS U4638 ( .A(n5455), .Y(n5461) );
NAND2X1TS U4639 ( .A(n5461), .B(d_ff3_LUT_out[34]), .Y(n3723) );
OAI211XLTS U4640 ( .A0(n5745), .A1(n6087), .B0(n3722), .C0(n3723), .Y(n2646)
);
CLKBUFX2TS U4641 ( .A(n5439), .Y(n5709) );
CLKBUFX2TS U4642 ( .A(n3835), .Y(n5718) );
CLKBUFX2TS U4643 ( .A(n5718), .Y(n5612) );
CLKBUFX2TS U4644 ( .A(n5427), .Y(n5507) );
AOI22X1TS U4645 ( .A0(n5612), .A1(d_ff3_sh_y_out[43]), .B0(n5507), .B1(
d_ff3_sh_x_out[43]), .Y(n3724) );
OAI211XLTS U4646 ( .A0(n5709), .A1(n6083), .B0(n3724), .C0(n3723), .Y(n2619)
);
CLKBUFX2TS U4647 ( .A(n5427), .Y(n5527) );
AOI22X1TS U4648 ( .A0(n5612), .A1(d_ff3_sh_y_out[47]), .B0(n5527), .B1(
d_ff3_sh_x_out[47]), .Y(n3725) );
CLKBUFX2TS U4649 ( .A(n5461), .Y(n5413) );
NAND2X1TS U4650 ( .A(n5413), .B(d_ff3_LUT_out[42]), .Y(n3726) );
OAI211XLTS U4651 ( .A0(n5709), .A1(n6091), .B0(n3725), .C0(n3726), .Y(n2607)
);
CLKBUFX2TS U4652 ( .A(n5718), .Y(n5500) );
AOI22X1TS U4653 ( .A0(n5500), .A1(d_ff3_sh_y_out[42]), .B0(n5507), .B1(
d_ff3_sh_x_out[42]), .Y(n3727) );
OAI211XLTS U4654 ( .A0(n5709), .A1(n6088), .B0(n3727), .C0(n3726), .Y(n2622)
);
AOI22X1TS U4655 ( .A0(n5500), .A1(d_ff3_sh_y_out[36]), .B0(n5487), .B1(
d_ff3_sh_x_out[36]), .Y(n3728) );
NAND2X1TS U4656 ( .A(n5413), .B(d_ff3_LUT_out[28]), .Y(n3910) );
OAI211XLTS U4657 ( .A0(n5745), .A1(n6017), .B0(n3728), .C0(n3910), .Y(n2640)
);
AOI22X1TS U4658 ( .A0(n5612), .A1(d_ff3_sh_y_out[46]), .B0(n5527), .B1(
d_ff3_sh_x_out[46]), .Y(n3729) );
NAND2X1TS U4659 ( .A(n5413), .B(d_ff3_LUT_out[44]), .Y(n4310) );
OAI211XLTS U4660 ( .A0(n5709), .A1(n6016), .B0(n3729), .C0(n4310), .Y(n2610)
);
AOI22X1TS U4661 ( .A0(n5500), .A1(d_ff3_sh_y_out[40]), .B0(n5507), .B1(
d_ff3_sh_x_out[40]), .Y(n3730) );
OAI211XLTS U4662 ( .A0(n5709), .A1(n6090), .B0(n3730), .C0(n3910), .Y(n2628)
);
CLKBUFX2TS U4663 ( .A(n6039), .Y(n4127) );
AOI22X1TS U4664 ( .A0(n4038), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]), .B1(n4127), .Y(n3731) );
OAI21XLTS U4665 ( .A0(n5912), .A1(n4040), .B0(n3731), .Y(n1938) );
AOI22X1TS U4666 ( .A0(n4038), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]), .B1(n4127), .Y(n3732) );
OAI21XLTS U4667 ( .A0(n5987), .A1(n4040), .B0(n3732), .Y(n1948) );
AOI22X1TS U4668 ( .A0(n4042), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[38]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[38]), .B1(n4041), .Y(n3733) );
OAI21XLTS U4669 ( .A0(n6092), .A1(n3734), .B0(n3733), .Y(n2129) );
INVX2TS U4670 ( .A(n4057), .Y(n4130) );
AOI22X1TS U4671 ( .A0(n4042), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]), .B1(n4041), .Y(n3735) );
OAI21XLTS U4672 ( .A0(n5911), .A1(n4130), .B0(n3735), .Y(n2018) );
AOI22X1TS U4673 ( .A0(n4131), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]), .B1(n4051), .Y(n3736) );
OAI21XLTS U4674 ( .A0(n5986), .A1(n4133), .B0(n3736), .Y(n1858) );
INVX2TS U4675 ( .A(n4057), .Y(n4055) );
AOI22X1TS U4676 ( .A0(n4123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]), .B1(n6039), .Y(n3737) );
OAI21XLTS U4677 ( .A0(n5977), .A1(n4055), .B0(n3737), .Y(n1899) );
AOI22X1TS U4678 ( .A0(n4131), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]), .B1(n4136), .Y(n3738) );
OAI21XLTS U4679 ( .A0(n5975), .A1(n4143), .B0(n3738), .Y(n1830) );
NAND2X1TS U4680 ( .A(n5941), .B(n5891), .Y(n3750) );
NAND2X1TS U4681 ( .A(n5898), .B(n6024), .Y(n3739) );
NOR2XLTS U4682 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .B(
n3209), .Y(n3740) );
NOR2XLTS U4683 ( .A(n3741), .B(n3740), .Y(n3742) );
AOI211XLTS U4684 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]),
.A1(n3744), .B0(n3743), .C0(n3742), .Y(n3745) );
OAI211XLTS U4685 ( .A0(n4157), .A1(n3747), .B0(n3746), .C0(n3745), .Y(n3748)
);
AOI211XLTS U4686 ( .A0(n3751), .A1(n3750), .B0(n3749), .C0(n3748), .Y(n4322)
);
AOI22X1TS U4687 ( .A0(n5554), .A1(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n4183), .Y(
n3752) );
CLKBUFX2TS U4688 ( .A(n3753), .Y(n3777) );
CLKBUFX2TS U4689 ( .A(n3796), .Y(n3766) );
AOI222XLTS U4690 ( .A0(n3777), .A1(data_output[11]), .B0(n3761), .B1(
d_ff_Yn[11]), .C0(n3766), .C1(d_ff_Xn[11]), .Y(n3754) );
INVX2TS U4691 ( .A(n3754), .Y(n2329) );
AOI222XLTS U4692 ( .A0(n3777), .A1(data_output[15]), .B0(n3761), .B1(
d_ff_Yn[15]), .C0(n3766), .C1(d_ff_Xn[15]), .Y(n3755) );
INVX2TS U4693 ( .A(n3755), .Y(n2325) );
AOI222XLTS U4694 ( .A0(n3777), .A1(data_output[14]), .B0(n3761), .B1(
d_ff_Yn[14]), .C0(n3766), .C1(d_ff_Xn[14]), .Y(n3756) );
INVX2TS U4695 ( .A(n3756), .Y(n2326) );
AOI222XLTS U4696 ( .A0(n3777), .A1(data_output[13]), .B0(n3761), .B1(
d_ff_Yn[13]), .C0(n3766), .C1(d_ff_Xn[13]), .Y(n3757) );
INVX2TS U4697 ( .A(n3757), .Y(n2327) );
AOI222XLTS U4698 ( .A0(n3777), .A1(data_output[12]), .B0(n3761), .B1(
d_ff_Yn[12]), .C0(n3766), .C1(d_ff_Xn[12]), .Y(n3758) );
INVX2TS U4699 ( .A(n3758), .Y(n2328) );
AOI222XLTS U4700 ( .A0(n3777), .A1(data_output[10]), .B0(n3761), .B1(
d_ff_Yn[10]), .C0(n3766), .C1(d_ff_Xn[10]), .Y(n3759) );
INVX2TS U4701 ( .A(n3759), .Y(n2330) );
AOI222XLTS U4702 ( .A0(n3777), .A1(data_output[16]), .B0(n3761), .B1(
d_ff_Yn[16]), .C0(n3766), .C1(d_ff_Xn[16]), .Y(n3760) );
INVX2TS U4703 ( .A(n3760), .Y(n2324) );
CLKBUFX2TS U4704 ( .A(n3796), .Y(n3787) );
AOI222XLTS U4705 ( .A0(n3789), .A1(data_output[2]), .B0(n3761), .B1(
d_ff_Yn[2]), .C0(n3787), .C1(d_ff_Xn[2]), .Y(n3762) );
INVX2TS U4706 ( .A(n3762), .Y(n2338) );
AOI222XLTS U4707 ( .A0(n3789), .A1(data_output[1]), .B0(n3771), .B1(
d_ff_Yn[1]), .C0(n3787), .C1(d_ff_Xn[1]), .Y(n3763) );
INVX2TS U4708 ( .A(n3763), .Y(n2339) );
AOI222XLTS U4709 ( .A0(n3777), .A1(data_output[17]), .B0(n3771), .B1(
d_ff_Yn[17]), .C0(n3766), .C1(d_ff_Xn[17]), .Y(n3764) );
INVX2TS U4710 ( .A(n3764), .Y(n2323) );
AOI222XLTS U4711 ( .A0(n3767), .A1(data_output[19]), .B0(n3771), .B1(
d_ff_Yn[19]), .C0(n3766), .C1(d_ff_Xn[19]), .Y(n3765) );
INVX2TS U4712 ( .A(n3765), .Y(n2321) );
AOI222XLTS U4713 ( .A0(n3767), .A1(data_output[18]), .B0(n3771), .B1(
d_ff_Yn[18]), .C0(n3766), .C1(d_ff_Xn[18]), .Y(n3768) );
INVX2TS U4714 ( .A(n3768), .Y(n2322) );
AOI222XLTS U4715 ( .A0(n3789), .A1(data_output[0]), .B0(n3771), .B1(
d_ff_Yn[0]), .C0(n3787), .C1(d_ff_Xn[0]), .Y(n3769) );
INVX2TS U4716 ( .A(n3769), .Y(n2340) );
CLKBUFX2TS U4717 ( .A(n3771), .Y(n3797) );
AOI222XLTS U4718 ( .A0(n3798), .A1(data_output[47]), .B0(n3797), .B1(
d_ff_Yn[47]), .C0(n3785), .C1(d_ff_Xn[47]), .Y(n3770) );
INVX2TS U4719 ( .A(n3770), .Y(n2293) );
CLKBUFX2TS U4720 ( .A(n3771), .Y(n3788) );
AOI222XLTS U4721 ( .A0(n5761), .A1(data_output[60]), .B0(n3788), .B1(
d_ff_Yn[60]), .C0(n3785), .C1(d_ff_Xn[60]), .Y(n3772) );
INVX2TS U4722 ( .A(n3772), .Y(n2280) );
AOI222XLTS U4723 ( .A0(n5761), .A1(data_output[62]), .B0(n3788), .B1(
d_ff_Yn[62]), .C0(n3785), .C1(d_ff_Xn[62]), .Y(n3773) );
INVX2TS U4724 ( .A(n3773), .Y(n2278) );
AOI222XLTS U4725 ( .A0(n3783), .A1(data_output[49]), .B0(n3797), .B1(
d_ff_Yn[49]), .C0(n3785), .C1(d_ff_Xn[49]), .Y(n3774) );
INVX2TS U4726 ( .A(n3774), .Y(n2291) );
AOI222XLTS U4727 ( .A0(n3789), .A1(data_output[3]), .B0(n3788), .B1(
d_ff_Yn[3]), .C0(n3787), .C1(d_ff_Xn[3]), .Y(n3775) );
INVX2TS U4728 ( .A(n3775), .Y(n2337) );
AOI222XLTS U4729 ( .A0(n3777), .A1(data_output[9]), .B0(n3788), .B1(
d_ff_Yn[9]), .C0(n3787), .C1(d_ff_Xn[9]), .Y(n3776) );
INVX2TS U4730 ( .A(n3776), .Y(n2331) );
AOI222XLTS U4731 ( .A0(n3777), .A1(data_output[8]), .B0(n3788), .B1(
d_ff_Yn[8]), .C0(n3787), .C1(d_ff_Xn[8]), .Y(n3778) );
INVX2TS U4732 ( .A(n3778), .Y(n2332) );
AOI222XLTS U4733 ( .A0(n3789), .A1(data_output[4]), .B0(n3788), .B1(
d_ff_Yn[4]), .C0(n3787), .C1(d_ff_Xn[4]), .Y(n3779) );
INVX2TS U4734 ( .A(n3779), .Y(n2336) );
AOI222XLTS U4735 ( .A0(n3789), .A1(data_output[6]), .B0(n3788), .B1(
d_ff_Yn[6]), .C0(n3787), .C1(d_ff_Xn[6]), .Y(n3780) );
INVX2TS U4736 ( .A(n3780), .Y(n2334) );
AOI222XLTS U4737 ( .A0(n5761), .A1(data_output[61]), .B0(n3788), .B1(
d_ff_Yn[61]), .C0(n3785), .C1(d_ff_Xn[61]), .Y(n3781) );
INVX2TS U4738 ( .A(n3781), .Y(n2279) );
AOI222XLTS U4739 ( .A0(n3789), .A1(data_output[5]), .B0(n3788), .B1(
d_ff_Yn[5]), .C0(n3787), .C1(d_ff_Xn[5]), .Y(n3782) );
INVX2TS U4740 ( .A(n3782), .Y(n2335) );
AOI222XLTS U4741 ( .A0(n3783), .A1(data_output[48]), .B0(n3797), .B1(
d_ff_Yn[48]), .C0(n3785), .C1(d_ff_Xn[48]), .Y(n3784) );
INVX2TS U4742 ( .A(n3784), .Y(n2292) );
AOI222XLTS U4743 ( .A0(n3798), .A1(data_output[46]), .B0(n3797), .B1(
d_ff_Yn[46]), .C0(n3785), .C1(d_ff_Xn[46]), .Y(n3786) );
INVX2TS U4744 ( .A(n3786), .Y(n2294) );
AOI222XLTS U4745 ( .A0(n3789), .A1(data_output[7]), .B0(n3788), .B1(
d_ff_Yn[7]), .C0(n3787), .C1(d_ff_Xn[7]), .Y(n3790) );
INVX2TS U4746 ( .A(n3790), .Y(n2333) );
AOI222XLTS U4747 ( .A0(n3798), .A1(data_output[44]), .B0(n3797), .B1(
d_ff_Yn[44]), .C0(n3796), .C1(d_ff_Xn[44]), .Y(n3791) );
INVX2TS U4748 ( .A(n3791), .Y(n2296) );
AOI222XLTS U4749 ( .A0(n3798), .A1(data_output[45]), .B0(n3797), .B1(
d_ff_Yn[45]), .C0(n3796), .C1(d_ff_Xn[45]), .Y(n3792) );
INVX2TS U4750 ( .A(n3792), .Y(n2295) );
AOI222XLTS U4751 ( .A0(n3798), .A1(data_output[42]), .B0(n3797), .B1(
d_ff_Yn[42]), .C0(n3796), .C1(d_ff_Xn[42]), .Y(n3793) );
INVX2TS U4752 ( .A(n3793), .Y(n2298) );
AOI222XLTS U4753 ( .A0(n3798), .A1(data_output[43]), .B0(n3797), .B1(
d_ff_Yn[43]), .C0(n3796), .C1(d_ff_Xn[43]), .Y(n3794) );
INVX2TS U4754 ( .A(n3794), .Y(n2297) );
AOI222XLTS U4755 ( .A0(n3798), .A1(data_output[41]), .B0(n3797), .B1(
d_ff_Yn[41]), .C0(n3796), .C1(d_ff_Xn[41]), .Y(n3795) );
INVX2TS U4756 ( .A(n3795), .Y(n2299) );
AOI222XLTS U4757 ( .A0(n3798), .A1(data_output[40]), .B0(n3797), .B1(
d_ff_Yn[40]), .C0(n3796), .C1(d_ff_Xn[40]), .Y(n3799) );
INVX2TS U4758 ( .A(n3799), .Y(n2300) );
CLKBUFX2TS U4759 ( .A(n5435), .Y(n5379) );
INVX2TS U4760 ( .A(n3905), .Y(n4096) );
INVX2TS U4761 ( .A(n5379), .Y(n5518) );
CLKBUFX2TS U4762 ( .A(n5380), .Y(n5382) );
INVX2TS U4763 ( .A(n5382), .Y(n3809) );
AOI222XLTS U4764 ( .A0(n3880), .A1(d_ff2_Z[0]), .B0(n3809), .B1(d_ff_Zn[0]),
.C0(n3843), .C1(d_ff1_Z[0]), .Y(n3800) );
INVX2TS U4765 ( .A(n3800), .Y(n2474) );
CLKBUFX2TS U4766 ( .A(n5412), .Y(n5376) );
INVX2TS U4767 ( .A(n5376), .Y(n5381) );
CLKBUFX2TS U4768 ( .A(n3843), .Y(n3874) );
AOI222XLTS U4769 ( .A0(n5381), .A1(d_ff2_Z[61]), .B0(n3874), .B1(d_ff1_Z[61]), .C0(d_ff_Zn[61]), .C1(n3809), .Y(n3801) );
INVX2TS U4770 ( .A(n3801), .Y(n2352) );
AOI222XLTS U4771 ( .A0(n5381), .A1(d_ff2_Z[58]), .B0(n3874), .B1(d_ff1_Z[58]), .C0(d_ff_Zn[58]), .C1(n3809), .Y(n3802) );
INVX2TS U4772 ( .A(n3802), .Y(n2358) );
INVX2TS U4773 ( .A(n6246), .Y(n3832) );
AOI222XLTS U4774 ( .A0(n3832), .A1(d_ff2_Z[57]), .B0(n3874), .B1(d_ff1_Z[57]), .C0(d_ff_Zn[57]), .C1(n3809), .Y(n3803) );
INVX2TS U4775 ( .A(n3803), .Y(n2360) );
AOI222XLTS U4776 ( .A0(n5381), .A1(d_ff2_Z[60]), .B0(n3874), .B1(d_ff1_Z[60]), .C0(d_ff_Zn[60]), .C1(n3809), .Y(n3804) );
INVX2TS U4777 ( .A(n3804), .Y(n2354) );
AOI222XLTS U4778 ( .A0(n5381), .A1(d_ff2_Z[63]), .B0(n3874), .B1(d_ff1_Z[63]), .C0(d_ff_Zn[63]), .C1(n3809), .Y(n3805) );
INVX2TS U4779 ( .A(n3805), .Y(n2349) );
CLKBUFX2TS U4780 ( .A(n3843), .Y(n3864) );
AOI222XLTS U4781 ( .A0(n5381), .A1(d_ff2_Z[49]), .B0(n3864), .B1(d_ff1_Z[49]), .C0(d_ff_Zn[49]), .C1(n3809), .Y(n3806) );
INVX2TS U4782 ( .A(n3806), .Y(n2376) );
AOI222XLTS U4783 ( .A0(n5381), .A1(d_ff2_Z[59]), .B0(n3874), .B1(d_ff1_Z[59]), .C0(d_ff_Zn[59]), .C1(n3809), .Y(n3807) );
INVX2TS U4784 ( .A(n3807), .Y(n2356) );
AOI222XLTS U4785 ( .A0(n3865), .A1(d_ff2_Z[56]), .B0(n3874), .B1(d_ff1_Z[56]), .C0(d_ff_Zn[56]), .C1(n3809), .Y(n3808) );
INVX2TS U4786 ( .A(n3808), .Y(n2362) );
AOI222XLTS U4787 ( .A0(n5381), .A1(d_ff2_Z[62]), .B0(n3874), .B1(d_ff1_Z[62]), .C0(d_ff_Zn[62]), .C1(n3809), .Y(n3810) );
INVX2TS U4788 ( .A(n3810), .Y(n2350) );
CLKBUFX2TS U4789 ( .A(n3843), .Y(n3869) );
AOI222XLTS U4790 ( .A0(n3832), .A1(d_ff2_Z[27]), .B0(n3869), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n3831), .Y(n3811) );
INVX2TS U4791 ( .A(n3811), .Y(n2420) );
AOI222XLTS U4792 ( .A0(n3832), .A1(d_ff2_Z[30]), .B0(n3869), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n3831), .Y(n3812) );
INVX2TS U4793 ( .A(n3812), .Y(n2414) );
CLKBUFX2TS U4794 ( .A(n3843), .Y(n3861) );
AOI222XLTS U4795 ( .A0(n3832), .A1(d_ff2_Z[37]), .B0(n3861), .B1(d_ff1_Z[37]), .C0(d_ff_Zn[37]), .C1(n3829), .Y(n3813) );
INVX2TS U4796 ( .A(n3813), .Y(n2400) );
AOI222XLTS U4797 ( .A0(n3832), .A1(d_ff2_Z[31]), .B0(n3869), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n3831), .Y(n3814) );
INVX2TS U4798 ( .A(n3814), .Y(n2412) );
AOI222XLTS U4799 ( .A0(n5518), .A1(d_ff2_Z[26]), .B0(n3869), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n3831), .Y(n3815) );
INVX2TS U4800 ( .A(n3815), .Y(n2422) );
AOI222XLTS U4801 ( .A0(n3865), .A1(d_ff2_Z[45]), .B0(n3864), .B1(d_ff1_Z[45]), .C0(d_ff_Zn[45]), .C1(n3829), .Y(n3816) );
INVX2TS U4802 ( .A(n3816), .Y(n2384) );
AOI222XLTS U4803 ( .A0(n3865), .A1(d_ff2_Z[41]), .B0(n3861), .B1(d_ff1_Z[41]), .C0(d_ff_Zn[41]), .C1(n3829), .Y(n3817) );
INVX2TS U4804 ( .A(n3817), .Y(n2392) );
AOI222XLTS U4805 ( .A0(n3865), .A1(d_ff2_Z[44]), .B0(n3864), .B1(d_ff1_Z[44]), .C0(d_ff_Zn[44]), .C1(n3829), .Y(n3818) );
INVX2TS U4806 ( .A(n3818), .Y(n2386) );
AOI222XLTS U4807 ( .A0(n3875), .A1(d_ff2_Z[36]), .B0(n3861), .B1(d_ff1_Z[36]), .C0(d_ff_Zn[36]), .C1(n3829), .Y(n3819) );
INVX2TS U4808 ( .A(n3819), .Y(n2402) );
AOI222XLTS U4809 ( .A0(n3875), .A1(d_ff2_Z[38]), .B0(n3861), .B1(d_ff1_Z[38]), .C0(d_ff_Zn[38]), .C1(n3829), .Y(n3820) );
INVX2TS U4810 ( .A(n3820), .Y(n2398) );
AOI222XLTS U4811 ( .A0(n3832), .A1(d_ff2_Z[32]), .B0(n3869), .B1(d_ff1_Z[32]), .C0(d_ff_Zn[32]), .C1(n3831), .Y(n3821) );
INVX2TS U4812 ( .A(n3821), .Y(n2410) );
AOI222XLTS U4813 ( .A0(n3832), .A1(d_ff2_Z[34]), .B0(n3861), .B1(d_ff1_Z[34]), .C0(d_ff_Zn[34]), .C1(n3831), .Y(n3822) );
INVX2TS U4814 ( .A(n3822), .Y(n2406) );
AOI222XLTS U4815 ( .A0(n3832), .A1(d_ff2_Z[42]), .B0(n3861), .B1(d_ff1_Z[42]), .C0(d_ff_Zn[42]), .C1(n3829), .Y(n3823) );
INVX2TS U4816 ( .A(n3823), .Y(n2390) );
AOI222XLTS U4817 ( .A0(n3865), .A1(d_ff2_Z[39]), .B0(n3861), .B1(d_ff1_Z[39]), .C0(d_ff_Zn[39]), .C1(n3829), .Y(n3824) );
INVX2TS U4818 ( .A(n3824), .Y(n2396) );
CLKBUFX2TS U4819 ( .A(n3843), .Y(n3885) );
AOI222XLTS U4820 ( .A0(n3865), .A1(d_ff2_Z[20]), .B0(n3885), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n3831), .Y(n3825) );
INVX2TS U4821 ( .A(n3825), .Y(n2434) );
AOI222XLTS U4822 ( .A0(n3865), .A1(d_ff2_Z[28]), .B0(n3869), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n3831), .Y(n3826) );
INVX2TS U4823 ( .A(n3826), .Y(n2418) );
AOI222XLTS U4824 ( .A0(n3865), .A1(d_ff2_Z[43]), .B0(n3861), .B1(d_ff1_Z[43]), .C0(d_ff_Zn[43]), .C1(n3829), .Y(n3827) );
INVX2TS U4825 ( .A(n3827), .Y(n2388) );
AOI222XLTS U4826 ( .A0(n3832), .A1(d_ff2_Z[29]), .B0(n3869), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n3831), .Y(n3828) );
INVX2TS U4827 ( .A(n3828), .Y(n2416) );
AOI222XLTS U4828 ( .A0(n3865), .A1(d_ff2_Z[40]), .B0(n3861), .B1(d_ff1_Z[40]), .C0(d_ff_Zn[40]), .C1(n3829), .Y(n3830) );
INVX2TS U4829 ( .A(n3830), .Y(n2394) );
AOI222XLTS U4830 ( .A0(n3832), .A1(d_ff2_Z[33]), .B0(n3869), .B1(d_ff1_Z[33]), .C0(d_ff_Zn[33]), .C1(n3831), .Y(n3833) );
INVX2TS U4831 ( .A(n3833), .Y(n2408) );
OAI21XLTS U4832 ( .A0(cont_iter_out[0]), .A1(n3180), .B0(n3176), .Y(n5309)
);
CLKBUFX2TS U4833 ( .A(n5374), .Y(n5361) );
NAND2X1TS U4834 ( .A(cont_iter_out[0]), .B(n5302), .Y(n4099) );
NOR3XLTS U4835 ( .A(cont_iter_out[1]), .B(n4103), .C(n4099), .Y(n4105) );
AOI21X1TS U4836 ( .A0(d_ff3_LUT_out[1]), .A1(n5361), .B0(n4105), .Y(n3834)
);
CLKBUFX2TS U4837 ( .A(n3835), .Y(n5737) );
CLKBUFX2TS U4838 ( .A(n5427), .Y(n5430) );
AOI222XLTS U4839 ( .A0(n5743), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[63]), .B0(n5737), .B1(
d_ff3_sh_y_out[63]), .C0(n5430), .C1(d_ff3_sh_x_out[63]), .Y(n3836) );
INVX2TS U4840 ( .A(n3836), .Y(n2342) );
AOI22X1TS U4841 ( .A0(n4302), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[56]), .B1(n4026), .Y(n3837) );
OAI21XLTS U4842 ( .A0(n5914), .A1(n4304), .B0(n3837), .Y(n2187) );
AOI22X1TS U4843 ( .A0(n4302), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[62]), .B1(n4118), .Y(n3838) );
OAI21XLTS U4844 ( .A0(n5995), .A1(n4304), .B0(n3838), .Y(n2247) );
AOI22X1TS U4845 ( .A0(n4032), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]), .B1(n4031), .Y(n3839) );
OAI21XLTS U4846 ( .A0(n5994), .A1(n4034), .B0(n3839), .Y(n2111) );
CLKBUFX2TS U4847 ( .A(n3843), .Y(n3879) );
INVX2TS U4848 ( .A(n5378), .Y(n5750) );
AOI222XLTS U4849 ( .A0(n5518), .A1(d_ff2_Z[4]), .B0(n3879), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n5750), .Y(n3840) );
INVX2TS U4850 ( .A(n3840), .Y(n2466) );
AOI222XLTS U4851 ( .A0(n3880), .A1(d_ff2_Z[3]), .B0(n3843), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n5750), .Y(n3841) );
INVX2TS U4852 ( .A(n3841), .Y(n2468) );
AOI222XLTS U4853 ( .A0(n3880), .A1(d_ff2_Z[1]), .B0(n3843), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n5750), .Y(n3842) );
INVX2TS U4854 ( .A(n3842), .Y(n2472) );
AOI222XLTS U4855 ( .A0(n3880), .A1(d_ff2_Z[2]), .B0(n3843), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n5750), .Y(n3844) );
INVX2TS U4856 ( .A(n3844), .Y(n2470) );
INVX2TS U4857 ( .A(n5378), .Y(n3884) );
AOI222XLTS U4858 ( .A0(n5518), .A1(d_ff2_Z[23]), .B0(n3885), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n3884), .Y(n3845) );
INVX2TS U4859 ( .A(n3845), .Y(n2428) );
INVX2TS U4860 ( .A(n5378), .Y(n3873) );
AOI222XLTS U4861 ( .A0(n3875), .A1(d_ff2_Z[48]), .B0(n3864), .B1(d_ff1_Z[48]), .C0(d_ff_Zn[48]), .C1(n3873), .Y(n3846) );
INVX2TS U4862 ( .A(n3846), .Y(n2378) );
INVX2TS U4863 ( .A(n5378), .Y(n3882) );
AOI222XLTS U4864 ( .A0(n3886), .A1(d_ff2_Z[11]), .B0(n3879), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n3882), .Y(n3847) );
INVX2TS U4865 ( .A(n3847), .Y(n2452) );
AOI222XLTS U4866 ( .A0(n3875), .A1(d_ff2_Z[50]), .B0(n3864), .B1(d_ff1_Z[50]), .C0(d_ff_Zn[50]), .C1(n3873), .Y(n3848) );
INVX2TS U4867 ( .A(n3848), .Y(n2374) );
AOI222XLTS U4868 ( .A0(n3886), .A1(d_ff2_Z[24]), .B0(n3869), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n3884), .Y(n3849) );
INVX2TS U4869 ( .A(n3849), .Y(n2426) );
AOI222XLTS U4870 ( .A0(n3886), .A1(d_ff2_Z[9]), .B0(n3879), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n3882), .Y(n3850) );
INVX2TS U4871 ( .A(n3850), .Y(n2456) );
AOI222XLTS U4872 ( .A0(n3880), .A1(d_ff2_Z[47]), .B0(n3864), .B1(d_ff1_Z[47]), .C0(d_ff_Zn[47]), .C1(n3873), .Y(n3851) );
INVX2TS U4873 ( .A(n3851), .Y(n2380) );
AOI222XLTS U4874 ( .A0(n3875), .A1(d_ff2_Z[52]), .B0(n3864), .B1(d_ff1_Z[52]), .C0(d_ff_Zn[52]), .C1(n3873), .Y(n3852) );
INVX2TS U4875 ( .A(n3852), .Y(n2370) );
AOI222XLTS U4876 ( .A0(n3880), .A1(d_ff2_Z[21]), .B0(n3885), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n3884), .Y(n3853) );
INVX2TS U4877 ( .A(n3853), .Y(n2432) );
AOI222XLTS U4878 ( .A0(n3886), .A1(d_ff2_Z[8]), .B0(n3879), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n3882), .Y(n3854) );
INVX2TS U4879 ( .A(n3854), .Y(n2458) );
AOI222XLTS U4880 ( .A0(n5518), .A1(d_ff2_Z[22]), .B0(n3885), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n3884), .Y(n3855) );
INVX2TS U4881 ( .A(n3855), .Y(n2430) );
AOI222XLTS U4882 ( .A0(n3875), .A1(d_ff2_Z[51]), .B0(n3864), .B1(d_ff1_Z[51]), .C0(d_ff_Zn[51]), .C1(n3873), .Y(n3856) );
INVX2TS U4883 ( .A(n3856), .Y(n2372) );
AOI222XLTS U4884 ( .A0(n3875), .A1(d_ff2_Z[5]), .B0(n3879), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n3884), .Y(n3857) );
INVX2TS U4885 ( .A(n3857), .Y(n2464) );
AOI222XLTS U4886 ( .A0(n3875), .A1(d_ff2_Z[53]), .B0(n3864), .B1(d_ff1_Z[53]), .C0(d_ff_Zn[53]), .C1(n3873), .Y(n3858) );
INVX2TS U4887 ( .A(n3858), .Y(n2368) );
AOI222XLTS U4888 ( .A0(n3880), .A1(d_ff2_Z[12]), .B0(n3879), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n3882), .Y(n3859) );
INVX2TS U4889 ( .A(n3859), .Y(n2450) );
AOI222XLTS U4890 ( .A0(n5518), .A1(d_ff2_Z[19]), .B0(n3885), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n3884), .Y(n3860) );
INVX2TS U4891 ( .A(n3860), .Y(n2436) );
AOI222XLTS U4892 ( .A0(n5381), .A1(d_ff2_Z[35]), .B0(n3861), .B1(d_ff1_Z[35]), .C0(d_ff_Zn[35]), .C1(n3873), .Y(n3862) );
INVX2TS U4893 ( .A(n3862), .Y(n2404) );
AOI222XLTS U4894 ( .A0(n3880), .A1(d_ff2_Z[13]), .B0(n3879), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n3882), .Y(n3863) );
INVX2TS U4895 ( .A(n3863), .Y(n2448) );
AOI222XLTS U4896 ( .A0(n3865), .A1(d_ff2_Z[46]), .B0(n3864), .B1(d_ff1_Z[46]), .C0(d_ff_Zn[46]), .C1(n3873), .Y(n3866) );
INVX2TS U4897 ( .A(n3866), .Y(n2382) );
AOI222XLTS U4898 ( .A0(n3886), .A1(d_ff2_Z[6]), .B0(n3879), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n3882), .Y(n3867) );
INVX2TS U4899 ( .A(n3867), .Y(n2462) );
AOI222XLTS U4900 ( .A0(n3886), .A1(d_ff2_Z[14]), .B0(n3885), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n3882), .Y(n3868) );
INVX2TS U4901 ( .A(n3868), .Y(n2446) );
AOI222XLTS U4902 ( .A0(n3886), .A1(d_ff2_Z[25]), .B0(n3869), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n3884), .Y(n3870) );
INVX2TS U4903 ( .A(n3870), .Y(n2424) );
AOI222XLTS U4904 ( .A0(n3886), .A1(d_ff2_Z[16]), .B0(n3885), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n3884), .Y(n3871) );
INVX2TS U4905 ( .A(n3871), .Y(n2442) );
AOI222XLTS U4906 ( .A0(n3875), .A1(d_ff2_Z[54]), .B0(n3874), .B1(d_ff1_Z[54]), .C0(d_ff_Zn[54]), .C1(n3873), .Y(n3872) );
INVX2TS U4907 ( .A(n3872), .Y(n2366) );
AOI222XLTS U4908 ( .A0(n3875), .A1(d_ff2_Z[55]), .B0(n3874), .B1(d_ff1_Z[55]), .C0(d_ff_Zn[55]), .C1(n3873), .Y(n3876) );
INVX2TS U4909 ( .A(n3876), .Y(n2364) );
AOI222XLTS U4910 ( .A0(n3880), .A1(d_ff2_Z[17]), .B0(n3885), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n3884), .Y(n3877) );
INVX2TS U4911 ( .A(n3877), .Y(n2440) );
AOI222XLTS U4912 ( .A0(n3886), .A1(d_ff2_Z[10]), .B0(n3879), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n3882), .Y(n3878) );
INVX2TS U4913 ( .A(n3878), .Y(n2454) );
AOI222XLTS U4914 ( .A0(n3880), .A1(d_ff2_Z[7]), .B0(n3879), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n3882), .Y(n3881) );
INVX2TS U4915 ( .A(n3881), .Y(n2460) );
AOI222XLTS U4916 ( .A0(n5518), .A1(d_ff2_Z[15]), .B0(n3885), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n3882), .Y(n3883) );
INVX2TS U4917 ( .A(n3883), .Y(n2444) );
AOI222XLTS U4918 ( .A0(n3886), .A1(d_ff2_Z[18]), .B0(n3885), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n3884), .Y(n3887) );
INVX2TS U4919 ( .A(n3887), .Y(n2438) );
AOI22X1TS U4920 ( .A0(n3890), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[57]), .B1(n4026), .Y(n3888) );
OAI21XLTS U4921 ( .A0(n5962), .A1(n4121), .B0(n3888), .Y(n2186) );
AOI22X1TS U4922 ( .A0(n4042), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]), .B1(n4041), .Y(n3889) );
OAI21XLTS U4923 ( .A0(n5963), .A1(n4130), .B0(n3889), .Y(n2004) );
AOI22X1TS U4924 ( .A0(n3890), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[55]), .B1(n4118), .Y(n3891) );
OAI21XLTS U4925 ( .A0(n6011), .A1(n4121), .B0(n3891), .Y(n2254) );
INVX2TS U4926 ( .A(n4021), .Y(n4128) );
CLKBUFX2TS U4927 ( .A(n6039), .Y(n4122) );
AOI22X1TS U4928 ( .A0(n4128), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]), .B1(n4122), .Y(n3892) );
OAI21XLTS U4929 ( .A0(n5978), .A1(n4130), .B0(n3892), .Y(n1983) );
AOI22X1TS U4930 ( .A0(n4128), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]), .B1(n4122), .Y(n3893) );
OAI21XLTS U4931 ( .A0(n5979), .A1(n4130), .B0(n3893), .Y(n1997) );
AOI22X1TS U4932 ( .A0(n4128), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]), .B1(n4122), .Y(n3894) );
OAI21XLTS U4933 ( .A0(n5913), .A1(n4130), .B0(n3894), .Y(n1990) );
AOI22X1TS U4934 ( .A0(n4128), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .B1(n4048), .Y(n3895) );
OAI21XLTS U4935 ( .A0(n5972), .A1(n4055), .B0(n3895), .Y(n1926) );
AOI22X1TS U4936 ( .A0(n4128), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]), .B1(n4127), .Y(n3896) );
OAI21XLTS U4937 ( .A0(n5967), .A1(n4130), .B0(n3896), .Y(n1963) );
AOI22X1TS U4938 ( .A0(n4149), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[36]), .B1(n4148), .Y(n3897) );
OAI21XLTS U4939 ( .A0(n6001), .A1(n4143), .B0(n3897), .Y(n1798) );
NAND2X1TS U4940 ( .A(n3899), .B(n5248), .Y(n5330) );
CLKBUFX2TS U4941 ( .A(n5330), .Y(n5328) );
NOR4XLTS U4942 ( .A(n5258), .B(n5302), .C(n5379), .D(n5328), .Y(n3900) );
AOI32X1TS U4943 ( .A0(n3902), .A1(n3901), .A2(n3900), .B0(ready_cordic),
.B1(ack_cordic), .Y(n3903) );
AOI21X1TS U4944 ( .A0(d_ff3_LUT_out[13]), .A1(n5361), .B0(n5306), .Y(n3904)
);
CLKBUFX2TS U4945 ( .A(n5374), .Y(n5406) );
NAND2X1TS U4946 ( .A(n5302), .B(n3905), .Y(n4107) );
NAND2X1TS U4947 ( .A(n3180), .B(n3184), .Y(n4101) );
AOI21X1TS U4948 ( .A0(cont_iter_out[1]), .A1(n3176), .B0(n5361), .Y(n5294)
);
NAND2X1TS U4949 ( .A(n4101), .B(n5294), .Y(n5281) );
NAND2X1TS U4950 ( .A(n4107), .B(n5281), .Y(n4111) );
AOI211XLTS U4951 ( .A0(d_ff3_LUT_out[8]), .A1(n5406), .B0(n5272), .C0(n4111),
.Y(n3906) );
INVX2TS U4952 ( .A(n3906), .Y(n3119) );
AOI22X1TS U4953 ( .A0(n5500), .A1(d_ff3_sh_y_out[38]), .B0(n5507), .B1(
d_ff3_sh_x_out[38]), .Y(n3907) );
NAND2X1TS U4954 ( .A(n5455), .B(d_ff3_LUT_out[32]), .Y(n4299) );
OAI211XLTS U4955 ( .A0(n5709), .A1(n6092), .B0(n3907), .C0(n4299), .Y(n2634)
);
AOI22X1TS U4956 ( .A0(n4032), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]), .B1(n4051), .Y(n3908) );
OAI21XLTS U4957 ( .A0(n5986), .A1(n4021), .B0(n3908), .Y(n1860) );
AOI22X1TS U4958 ( .A0(n5500), .A1(d_ff3_sh_y_out[30]), .B0(n5487), .B1(
d_ff3_sh_x_out[30]), .Y(n3909) );
NAND2X1TS U4959 ( .A(n5413), .B(d_ff3_LUT_out[4]), .Y(n4308) );
OAI211XLTS U4960 ( .A0(n5439), .A1(n6089), .B0(n3909), .C0(n4308), .Y(n2658)
);
AOI22X1TS U4961 ( .A0(n5493), .A1(d_ff3_sh_y_out[28]), .B0(n5487), .B1(
d_ff3_sh_x_out[28]), .Y(n3911) );
OAI211XLTS U4962 ( .A0(n5439), .A1(n6082), .B0(n3911), .C0(n3910), .Y(n2664)
);
AOI22X1TS U4963 ( .A0(n5612), .A1(d_ff3_sh_y_out[44]), .B0(n5507), .B1(
d_ff3_sh_x_out[44]), .Y(n3912) );
OAI211XLTS U4964 ( .A0(n5709), .A1(n6080), .B0(n3912), .C0(n4310), .Y(n2616)
);
CLKBUFX2TS U4965 ( .A(n5718), .Y(n5588) );
AOI22X1TS U4966 ( .A0(n5588), .A1(d_ff3_sh_y_out[58]), .B0(n5527), .B1(
d_ff3_sh_x_out[58]), .Y(n3913) );
NAND2X1TS U4967 ( .A(n5413), .B(d_ff3_LUT_out[48]), .Y(n4314) );
OAI211XLTS U4968 ( .A0(n5745), .A1(n5989), .B0(n3913), .C0(n4314), .Y(n2570)
);
CLKBUFX2TS U4969 ( .A(n5427), .Y(n5650) );
AOI22X1TS U4970 ( .A0(n5588), .A1(d_ff3_sh_y_out[59]), .B0(n5650), .B1(
d_ff3_sh_x_out[59]), .Y(n3914) );
OAI211XLTS U4971 ( .A0(n5745), .A1(n5990), .B0(n3914), .C0(n4314), .Y(n2568)
);
AOI22X1TS U4972 ( .A0(n5588), .A1(d_ff3_sh_y_out[60]), .B0(n5650), .B1(
d_ff3_sh_x_out[60]), .Y(n3915) );
OAI211XLTS U4973 ( .A0(n5745), .A1(n5988), .B0(n3915), .C0(n4314), .Y(n2566)
);
AOI22X1TS U4974 ( .A0(n5612), .A1(d_ff3_sh_y_out[48]), .B0(n5527), .B1(
d_ff3_sh_x_out[48]), .Y(n3916) );
OAI211XLTS U4975 ( .A0(n5709), .A1(n6081), .B0(n3916), .C0(n4314), .Y(n2604)
);
AOI22X1TS U4976 ( .A0(n4128), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]), .B1(n4127), .Y(n3917) );
OAI21XLTS U4977 ( .A0(n5987), .A1(n4055), .B0(n3917), .Y(n1946) );
AOI22X1TS U4978 ( .A0(n4123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .B1(n4048), .Y(n3918) );
OAI21XLTS U4979 ( .A0(n5912), .A1(n4055), .B0(n3918), .Y(n1915) );
AOI22X1TS U4980 ( .A0(n4123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]), .B1(n4048), .Y(n3919) );
OAI21XLTS U4981 ( .A0(n5981), .A1(n4055), .B0(n3919), .Y(n1907) );
AOI22X1TS U4982 ( .A0(n4123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]), .B1(n4048), .Y(n3920) );
OAI21XLTS U4983 ( .A0(n5969), .A1(n4055), .B0(n3920), .Y(n1903) );
AOI22X1TS U4984 ( .A0(n4149), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[41]), .B1(n4148), .Y(n3921) );
OAI21XLTS U4985 ( .A0(n5966), .A1(n4143), .B0(n3921), .Y(n1806) );
CLKBUFX2TS U4986 ( .A(n5246), .Y(n6321) );
CLKBUFX2TS U4987 ( .A(n6321), .Y(n6323) );
CLKBUFX2TS U4988 ( .A(n6323), .Y(n6317) );
CLKBUFX2TS U4989 ( .A(n6317), .Y(n6262) );
NOR2XLTS U4990 ( .A(n5258), .B(rst), .Y(n4380) );
CLKBUFX2TS U4991 ( .A(n4380), .Y(n3926) );
CLKBUFX2TS U4992 ( .A(n3926), .Y(n6245) );
CLKBUFX2TS U4993 ( .A(n6245), .Y(n6180) );
CLKBUFX2TS U4994 ( .A(n6245), .Y(n6181) );
CLKBUFX2TS U4995 ( .A(n6317), .Y(n6258) );
CLKBUFX2TS U4996 ( .A(n6317), .Y(n6322) );
CLKBUFX2TS U4997 ( .A(n6322), .Y(n6314) );
CLKBUFX2TS U4998 ( .A(n6314), .Y(n6318) );
CLKBUFX2TS U4999 ( .A(n6318), .Y(n6256) );
CLKBUFX2TS U5000 ( .A(n6245), .Y(n6182) );
CLKBUFX2TS U5001 ( .A(n6322), .Y(n6316) );
CLKBUFX2TS U5002 ( .A(n6316), .Y(n6271) );
CLKBUFX2TS U5003 ( .A(n6245), .Y(n6176) );
CLKBUFX2TS U5004 ( .A(n6316), .Y(n6270) );
CLKBUFX2TS U5005 ( .A(n6314), .Y(n6269) );
CLKBUFX2TS U5006 ( .A(n6321), .Y(n6268) );
CLKBUFX2TS U5007 ( .A(n6245), .Y(n6177) );
CLKBUFX2TS U5008 ( .A(n6318), .Y(n6267) );
CLKBUFX2TS U5009 ( .A(n4380), .Y(n3922) );
CLKBUFX2TS U5010 ( .A(n3922), .Y(n6189) );
CLKBUFX2TS U5011 ( .A(n4380), .Y(n3925) );
CLKBUFX2TS U5012 ( .A(n3925), .Y(n6218) );
CLKBUFX2TS U5013 ( .A(n3922), .Y(n6190) );
CLKBUFX2TS U5014 ( .A(n3922), .Y(n6192) );
CLKBUFX2TS U5015 ( .A(n3922), .Y(n6193) );
CLKBUFX2TS U5016 ( .A(n3922), .Y(n6194) );
CLKBUFX2TS U5017 ( .A(n3925), .Y(n6222) );
CLKBUFX2TS U5018 ( .A(n3922), .Y(n6195) );
CLKBUFX2TS U5019 ( .A(n4380), .Y(n3927) );
CLKBUFX2TS U5020 ( .A(n3927), .Y(n6196) );
CLKBUFX2TS U5021 ( .A(n6245), .Y(n6185) );
CLKBUFX2TS U5022 ( .A(n4380), .Y(n3929) );
CLKBUFX2TS U5023 ( .A(n3929), .Y(n6215) );
CLKBUFX2TS U5024 ( .A(n3922), .Y(n6186) );
CLKBUFX2TS U5025 ( .A(n3922), .Y(n6187) );
CLKBUFX2TS U5026 ( .A(n3925), .Y(n6217) );
CLKBUFX2TS U5027 ( .A(n3922), .Y(n6188) );
CLKBUFX2TS U5028 ( .A(n5246), .Y(n3923) );
CLKBUFX2TS U5029 ( .A(n3923), .Y(n6299) );
CLKBUFX2TS U5030 ( .A(n3923), .Y(n6298) );
CLKBUFX2TS U5031 ( .A(n4380), .Y(n3924) );
CLKBUFX2TS U5032 ( .A(n3924), .Y(n6167) );
CLKBUFX2TS U5033 ( .A(n3924), .Y(n6168) );
CLKBUFX2TS U5034 ( .A(n5246), .Y(n6320) );
CLKBUFX2TS U5035 ( .A(n6320), .Y(n6319) );
CLKBUFX2TS U5036 ( .A(n6319), .Y(n6324) );
CLKBUFX2TS U5037 ( .A(n6324), .Y(n6311) );
CLKBUFX2TS U5038 ( .A(n6320), .Y(n6310) );
CLKBUFX2TS U5039 ( .A(n6324), .Y(n6308) );
CLKBUFX2TS U5040 ( .A(n6324), .Y(n6307) );
CLKBUFX2TS U5041 ( .A(n6324), .Y(n6306) );
CLKBUFX2TS U5042 ( .A(n6324), .Y(n6305) );
CLKBUFX2TS U5043 ( .A(n3923), .Y(n6304) );
CLKBUFX2TS U5044 ( .A(n3923), .Y(n6302) );
CLKBUFX2TS U5045 ( .A(n3923), .Y(n6301) );
CLKBUFX2TS U5046 ( .A(n6321), .Y(n6281) );
CLKBUFX2TS U5047 ( .A(n6322), .Y(n6315) );
CLKBUFX2TS U5048 ( .A(n6315), .Y(n6280) );
CLKBUFX2TS U5049 ( .A(n6321), .Y(n6279) );
CLKBUFX2TS U5050 ( .A(n3924), .Y(n6173) );
CLKBUFX2TS U5051 ( .A(n6314), .Y(n6278) );
CLKBUFX2TS U5052 ( .A(n6314), .Y(n6277) );
CLKBUFX2TS U5053 ( .A(n6314), .Y(n6276) );
CLKBUFX2TS U5054 ( .A(n3924), .Y(n6174) );
CLKBUFX2TS U5055 ( .A(n6315), .Y(n6275) );
CLKBUFX2TS U5056 ( .A(n6315), .Y(n6274) );
CLKBUFX2TS U5057 ( .A(n3924), .Y(n6175) );
CLKBUFX2TS U5058 ( .A(n6315), .Y(n6273) );
CLKBUFX2TS U5059 ( .A(n6316), .Y(n6272) );
CLKBUFX2TS U5060 ( .A(n6316), .Y(n6289) );
CLKBUFX2TS U5061 ( .A(n3924), .Y(n6169) );
CLKBUFX2TS U5062 ( .A(n6315), .Y(n6288) );
CLKBUFX2TS U5063 ( .A(n6314), .Y(n6287) );
CLKBUFX2TS U5064 ( .A(n3924), .Y(n6170) );
CLKBUFX2TS U5065 ( .A(n6321), .Y(n6286) );
CLKBUFX2TS U5066 ( .A(n6321), .Y(n6285) );
CLKBUFX2TS U5067 ( .A(n6318), .Y(n6284) );
CLKBUFX2TS U5068 ( .A(n3924), .Y(n6171) );
CLKBUFX2TS U5069 ( .A(n6315), .Y(n6283) );
CLKBUFX2TS U5070 ( .A(n4380), .Y(n3928) );
CLKBUFX2TS U5071 ( .A(n3928), .Y(n6233) );
CLKBUFX2TS U5072 ( .A(n3927), .Y(n6201) );
CLKBUFX2TS U5073 ( .A(n3929), .Y(n6207) );
CLKBUFX2TS U5074 ( .A(n3928), .Y(n6229) );
CLKBUFX2TS U5075 ( .A(n3928), .Y(n6234) );
CLKBUFX2TS U5076 ( .A(n3927), .Y(n6200) );
CLKBUFX2TS U5077 ( .A(n3928), .Y(n6230) );
CLKBUFX2TS U5078 ( .A(n3929), .Y(n6211) );
CLKBUFX2TS U5079 ( .A(n3927), .Y(n6199) );
CLKBUFX2TS U5080 ( .A(n3929), .Y(n6213) );
CLKBUFX2TS U5081 ( .A(n3927), .Y(n6204) );
CLKBUFX2TS U5082 ( .A(n3927), .Y(n6205) );
CLKBUFX2TS U5083 ( .A(n3927), .Y(n6203) );
CLKBUFX2TS U5084 ( .A(n3926), .Y(n6244) );
CLKBUFX2TS U5085 ( .A(n3928), .Y(n6231) );
CLKBUFX2TS U5086 ( .A(n3925), .Y(n6219) );
CLKBUFX2TS U5087 ( .A(n3926), .Y(n6242) );
CLKBUFX2TS U5088 ( .A(n3928), .Y(n6235) );
CLKBUFX2TS U5089 ( .A(n3926), .Y(n6238) );
CLKBUFX2TS U5090 ( .A(n3929), .Y(n6212) );
CLKBUFX2TS U5091 ( .A(n3928), .Y(n6232) );
CLKBUFX2TS U5092 ( .A(n3926), .Y(n6243) );
CLKBUFX2TS U5093 ( .A(n3927), .Y(n6202) );
CLKBUFX2TS U5094 ( .A(n3929), .Y(n6206) );
CLKBUFX2TS U5095 ( .A(n3924), .Y(n6172) );
CLKBUFX2TS U5096 ( .A(n3929), .Y(n6208) );
CLKBUFX2TS U5097 ( .A(n3922), .Y(n6191) );
CLKBUFX2TS U5098 ( .A(n3929), .Y(n6214) );
CLKBUFX2TS U5099 ( .A(n3923), .Y(n6297) );
CLKBUFX2TS U5100 ( .A(n3923), .Y(n6296) );
CLKBUFX2TS U5101 ( .A(n6318), .Y(n6295) );
CLKBUFX2TS U5102 ( .A(n6322), .Y(n6294) );
CLKBUFX2TS U5103 ( .A(n6323), .Y(n6293) );
CLKBUFX2TS U5104 ( .A(n6314), .Y(n6292) );
CLKBUFX2TS U5105 ( .A(n6322), .Y(n6291) );
CLKBUFX2TS U5106 ( .A(n3926), .Y(n6236) );
CLKBUFX2TS U5107 ( .A(n6320), .Y(n6249) );
CLKBUFX2TS U5108 ( .A(n6323), .Y(n6290) );
CLKBUFX2TS U5109 ( .A(n6315), .Y(n6266) );
CLKBUFX2TS U5110 ( .A(n6316), .Y(n6265) );
CLKBUFX2TS U5111 ( .A(n6318), .Y(n6263) );
CLKBUFX2TS U5112 ( .A(n6323), .Y(n6261) );
CLKBUFX2TS U5113 ( .A(n6316), .Y(n6260) );
CLKBUFX2TS U5114 ( .A(n6317), .Y(n6259) );
CLKBUFX2TS U5115 ( .A(n6317), .Y(n6257) );
CLKBUFX2TS U5116 ( .A(n6318), .Y(n6255) );
CLKBUFX2TS U5117 ( .A(n6318), .Y(n6254) );
CLKBUFX2TS U5118 ( .A(n6319), .Y(n6253) );
CLKBUFX2TS U5119 ( .A(n3925), .Y(n6224) );
CLKBUFX2TS U5120 ( .A(n6319), .Y(n6252) );
CLKBUFX2TS U5121 ( .A(n3924), .Y(n6166) );
CLKBUFX2TS U5122 ( .A(n3925), .Y(n6220) );
CLKBUFX2TS U5123 ( .A(n3928), .Y(n6228) );
CLKBUFX2TS U5124 ( .A(n3926), .Y(n6241) );
CLKBUFX2TS U5125 ( .A(n6245), .Y(n6179) );
CLKBUFX2TS U5126 ( .A(n6245), .Y(n6178) );
CLKBUFX2TS U5127 ( .A(n3925), .Y(n6216) );
CLKBUFX2TS U5128 ( .A(n3925), .Y(n6221) );
CLKBUFX2TS U5129 ( .A(n3926), .Y(n6239) );
CLKBUFX2TS U5130 ( .A(n6316), .Y(n6282) );
CLKBUFX2TS U5131 ( .A(n3925), .Y(n6225) );
CLKBUFX2TS U5132 ( .A(n3925), .Y(n6223) );
CLKBUFX2TS U5133 ( .A(n3926), .Y(n6240) );
CLKBUFX2TS U5134 ( .A(n6319), .Y(n6248) );
CLKBUFX2TS U5135 ( .A(n3929), .Y(n6209) );
CLKBUFX2TS U5136 ( .A(n6324), .Y(n6313) );
CLKBUFX2TS U5137 ( .A(n3927), .Y(n6197) );
CLKBUFX2TS U5138 ( .A(n3926), .Y(n6237) );
CLKBUFX2TS U5139 ( .A(n3928), .Y(n6227) );
CLKBUFX2TS U5140 ( .A(n3927), .Y(n6198) );
CLKBUFX2TS U5141 ( .A(n3928), .Y(n6226) );
CLKBUFX2TS U5142 ( .A(n3929), .Y(n6210) );
XOR2XLTS U5143 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[63]), .B(
inst_FPU_PIPELINED_FPADDSUB_intAS), .Y(n5820) );
INVX2TS U5144 ( .A(n5820), .Y(n3930) );
CLKBUFX2TS U5145 ( .A(n5823), .Y(n5255) );
AOI221XLTS U5146 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[63]), .A1(
n5820), .B0(n6022), .B1(n3930), .C0(n5255), .Y(n4005) );
AO21XLTS U5147 ( .A0(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP), .A1(n5823),
.B0(n4005), .Y(n2086) );
CLKBUFX2TS U5148 ( .A(n6035), .Y(n5885) );
INVX2TS U5149 ( .A(n5885), .Y(n5775) );
CLKBUFX2TS U5150 ( .A(n5838), .Y(n5774) );
AO22XLTS U5151 ( .A0(n5775), .A1(intadd_22_SUM_2_), .B0(n5774), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n2273) );
AOI32X1TS U5152 ( .A0(n3931), .A1(n5260), .A2(n3180), .B0(cont_iter_out[3]),
.B1(n3931), .Y(n3932) );
INVX2TS U5153 ( .A(n3932), .Y(n3161) );
AOI22X1TS U5154 ( .A0(n5983), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]),
.B0(n5995), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .Y(n3933)
);
OAI221XLTS U5155 ( .A0(n5983), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .B0(n5995), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .C0(n3933), .Y(
n3934) );
AOI221XLTS U5156 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .A1(n6012), .B0(n5919), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .C0(n3934), .Y(
n3948) );
OAI22X1TS U5157 ( .A0(n5908), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .B0(n5966), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .Y(n3935) );
AOI221XLTS U5158 ( .A0(n5908), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .B1(n5966), .C0(n3935),
.Y(n3947) );
OAI22X1TS U5159 ( .A0(n5998), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .B0(n5999), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .Y(n3936) );
AOI221XLTS U5160 ( .A0(n5998), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .B1(n5999), .C0(n3936),
.Y(n3946) );
AOI22X1TS U5161 ( .A0(n5974), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B0(n5989), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[58]), .Y(n3937) );
OAI221XLTS U5162 ( .A0(n5974), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B0(n5989), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[58]), .C0(n3937), .Y(n3944) );
AOI22X1TS U5163 ( .A0(n5971), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .B0(n5916), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .Y(n3938) );
OAI221XLTS U5164 ( .A0(n5971), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .B0(n5916), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .C0(n3938), .Y(n3943) );
AOI22X1TS U5165 ( .A0(n5918), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]), .B0(n6007), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .Y(n3939) );
OAI221XLTS U5166 ( .A0(n5918), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]), .B0(n6007), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .C0(n3939), .Y(n3942) );
AOI22X1TS U5167 ( .A0(n5980), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B0(n5992), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .Y(n3940) );
OAI221XLTS U5168 ( .A0(n5980), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B0(n5992), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .C0(n3940), .Y(n3941) );
NOR4XLTS U5169 ( .A(n3944), .B(n3943), .C(n3942), .D(n3941), .Y(n3945) );
NAND4XLTS U5170 ( .A(n3948), .B(n3947), .C(n3946), .D(n3945), .Y(n4004) );
OAI22X1TS U5171 ( .A0(n5909), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B0(n5961), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .Y(n3949) );
AOI221XLTS U5172 ( .A0(n5909), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .B1(n5961), .C0(n3949),
.Y(n3956) );
OAI22X1TS U5173 ( .A0(n5967), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B0(n5970), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .Y(n3950) );
AOI221XLTS U5174 ( .A0(n5967), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .B1(n5970), .C0(n3950),
.Y(n3955) );
OAI22X1TS U5175 ( .A0(n5964), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]),
.B0(n6003), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .Y(n3951)
);
AOI221XLTS U5176 ( .A0(n5964), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .B1(n6003), .C0(n3951), .Y(
n3954) );
OAI22X1TS U5177 ( .A0(n5910), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .B0(n5968), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .Y(n3952) );
AOI221XLTS U5178 ( .A0(n5910), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .B1(n5968), .C0(n3952),
.Y(n3953) );
NAND4XLTS U5179 ( .A(n3956), .B(n3955), .C(n3954), .D(n3953), .Y(n4003) );
OAI22X1TS U5180 ( .A0(n5965), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .B0(n6001), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .Y(n3957) );
AOI221XLTS U5181 ( .A0(n5965), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .B1(n6001), .C0(n3957),
.Y(n3964) );
OAI22X1TS U5182 ( .A0(n5997), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[44]), .B0(n5969), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .Y(n3958) );
AOI221XLTS U5183 ( .A0(n5997), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[44]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .B1(n5969), .C0(n3958),
.Y(n3963) );
OAI22X1TS U5184 ( .A0(n5963), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .B0(n6000), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .Y(n3959) );
AOI221XLTS U5185 ( .A0(n5963), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .B1(n6000), .C0(n3959),
.Y(n3962) );
OAI22X1TS U5186 ( .A0(n5917), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .B0(n5996), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[48]), .Y(n3960) );
AOI221XLTS U5187 ( .A0(n5917), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[48]), .B1(n5996), .C0(n3960),
.Y(n3961) );
NAND4XLTS U5188 ( .A(n3964), .B(n3963), .C(n3962), .D(n3961), .Y(n4002) );
AOI22X1TS U5189 ( .A0(n6002), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[38]), .B0(n5914), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .Y(n3965) );
OAI221XLTS U5190 ( .A0(n6002), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[38]), .B0(n5914), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .C0(n3965), .Y(n3972) );
AOI22X1TS U5191 ( .A0(n5976), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .B0(n5915), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .Y(n3966) );
OAI221XLTS U5192 ( .A0(n5976), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .B0(n5915), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .C0(n3966), .Y(n3971) );
AOI22X1TS U5193 ( .A0(n5982), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B0(n5988), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[60]), .Y(n3967) );
OAI221XLTS U5194 ( .A0(n5982), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B0(n5988), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[60]), .C0(n3967), .Y(n3970) );
AOI22X1TS U5195 ( .A0(n5985), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]), .B0(n5979), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .Y(n3968) );
OAI221XLTS U5196 ( .A0(n5985), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]), .B0(n5979), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .C0(n3968), .Y(n3969) );
NOR4XLTS U5197 ( .A(n3972), .B(n3971), .C(n3970), .D(n3969), .Y(n4000) );
AOI22X1TS U5198 ( .A0(n5912), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B0(n5994), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .Y(n3973) );
OAI221XLTS U5199 ( .A0(n5912), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B0(n5994), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .C0(n3973), .Y(n3980) );
AOI22X1TS U5200 ( .A0(n6004), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .B0(n5962), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .Y(n3974) );
OAI221XLTS U5201 ( .A0(n6004), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .B0(n5962), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .C0(n3974), .Y(n3979) );
AOI22X1TS U5202 ( .A0(n6005), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]), .B0(n6006), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .Y(n3975) );
OAI221XLTS U5203 ( .A0(n6005), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]), .B0(n6006), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .C0(n3975), .Y(n3978) );
AOI22X1TS U5204 ( .A0(n6010), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .B0(n5990), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .Y(n3976) );
OAI221XLTS U5205 ( .A0(n6010), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .B0(n5990), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .C0(n3976), .Y(n3977) );
NOR4XLTS U5206 ( .A(n3980), .B(n3979), .C(n3978), .D(n3977), .Y(n3999) );
AOI22X1TS U5207 ( .A0(n5973), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]),
.B0(n5913), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .Y(n3981)
);
OAI221XLTS U5208 ( .A0(n5973), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .B0(n5913), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .C0(n3981), .Y(
n3988) );
AOI22X1TS U5209 ( .A0(n5911), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B0(n5991), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .Y(n3982) );
OAI221XLTS U5210 ( .A0(n5911), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B0(n5991), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .C0(n3982), .Y(n3987) );
AOI22X1TS U5211 ( .A0(n6014), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .B0(n5987), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .Y(n3983) );
OAI221XLTS U5212 ( .A0(n6014), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .B0(n5987), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .C0(n3983), .Y(n3986) );
AOI22X1TS U5213 ( .A0(n5981), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .B0(n5978), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .Y(n3984) );
OAI221XLTS U5214 ( .A0(n5981), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .B0(n5978), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .C0(n3984), .Y(n3985) );
NOR4XLTS U5215 ( .A(n3988), .B(n3987), .C(n3986), .D(n3985), .Y(n3998) );
AOI22X1TS U5216 ( .A0(n6009), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]), .B0(n5977), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .Y(n3989) );
OAI221XLTS U5217 ( .A0(n6009), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]), .B0(n5977), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .C0(n3989), .Y(n3996) );
AOI22X1TS U5218 ( .A0(n5975), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B0(n6008), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .Y(n3990) );
OAI221XLTS U5219 ( .A0(n5975), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B0(n6008), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .C0(n3990), .Y(n3995) );
AOI22X1TS U5220 ( .A0(n6011), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .B0(n5986), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .Y(n3991) );
OAI221XLTS U5221 ( .A0(n6011), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .B0(n5986), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .C0(n3991), .Y(n3994) );
AOI22X1TS U5222 ( .A0(n5972), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .B0(n5993), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .Y(n3992) );
OAI221XLTS U5223 ( .A0(n5972), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .B0(n5993), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .C0(n3992), .Y(n3993) );
NOR4XLTS U5224 ( .A(n3996), .B(n3995), .C(n3994), .D(n3993), .Y(n3997) );
NAND4XLTS U5225 ( .A(n4000), .B(n3999), .C(n3998), .D(n3997), .Y(n4001) );
NOR4XLTS U5226 ( .A(n4004), .B(n4003), .C(n4002), .D(n4001), .Y(n5818) );
AO22XLTS U5227 ( .A0(n4005), .A1(n5818), .B0(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP), .B1(n5823), .Y(n1867) );
CLKBUFX2TS U5228 ( .A(n5374), .Y(n5751) );
AO22XLTS U5229 ( .A0(n5752), .A1(intadd_24_SUM_2_), .B0(n5751), .B1(
d_ff3_sh_x_out[55]), .Y(n2763) );
AO22XLTS U5230 ( .A0(n5752), .A1(intadd_24_SUM_0_), .B0(n5751), .B1(
d_ff3_sh_x_out[53]), .Y(n2765) );
CLKBUFX2TS U5231 ( .A(n5374), .Y(n5475) );
INVX2TS U5232 ( .A(n5475), .Y(n5390) );
AO22XLTS U5233 ( .A0(n5390), .A1(intadd_24_SUM_1_), .B0(n5751), .B1(
d_ff3_sh_x_out[54]), .Y(n2764) );
CLKBUFX2TS U5234 ( .A(n5374), .Y(n5373) );
INVX2TS U5235 ( .A(n5373), .Y(n5541) );
AO22XLTS U5236 ( .A0(n5541), .A1(intadd_23_SUM_2_), .B0(n5751), .B1(
d_ff3_sh_y_out[55]), .Y(n2577) );
CLKBUFX2TS U5237 ( .A(n5295), .Y(n5520) );
AO22XLTS U5238 ( .A0(n5742), .A1(intadd_23_SUM_0_), .B0(n5520), .B1(
d_ff3_sh_y_out[53]), .Y(n2581) );
AO22XLTS U5239 ( .A0(n5742), .A1(intadd_23_SUM_1_), .B0(n5520), .B1(
d_ff3_sh_y_out[54]), .Y(n2579) );
CLKBUFX2TS U5240 ( .A(n5412), .Y(n5365) );
OA22X1TS U5241 ( .A0(n5365), .A1(d_ff2_X[32]), .B0(d_ff_Xn[32]), .B1(n5382),
.Y(n2817) );
OA22X1TS U5242 ( .A0(n5365), .A1(d_ff2_X[26]), .B0(d_ff_Xn[26]), .B1(n5382),
.Y(n2829) );
OA22X1TS U5243 ( .A0(n5365), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n5382),
.Y(n2825) );
OA22X1TS U5244 ( .A0(n5365), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n5382),
.Y(n2823) );
OA22X1TS U5245 ( .A0(n5365), .A1(d_ff2_X[31]), .B0(d_ff_Xn[31]), .B1(n5382),
.Y(n2819) );
OA22X1TS U5246 ( .A0(n5365), .A1(d_ff2_X[34]), .B0(d_ff_Xn[34]), .B1(n5382),
.Y(n2813) );
OA22X1TS U5247 ( .A0(n5365), .A1(d_ff2_X[35]), .B0(d_ff_Xn[35]), .B1(n5382),
.Y(n2811) );
AOI22X1TS U5248 ( .A0(n4028), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]), .B1(n4122), .Y(n4007) );
OAI21XLTS U5249 ( .A0(n5913), .A1(n4013), .B0(n4007), .Y(n1992) );
AOI22X1TS U5250 ( .A0(n4028), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]), .B1(n4122), .Y(n4008) );
OAI21XLTS U5251 ( .A0(n5977), .A1(n4013), .B0(n4008), .Y(n1978) );
AOI22X1TS U5252 ( .A0(n4028), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]), .B1(n4122), .Y(n4009) );
OAI21XLTS U5253 ( .A0(n5978), .A1(n4013), .B0(n4009), .Y(n1985) );
AOI22X1TS U5254 ( .A0(n4028), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]), .B1(n4041), .Y(n4010) );
OAI21XLTS U5255 ( .A0(n5979), .A1(n4013), .B0(n4010), .Y(n1999) );
AOI22X1TS U5256 ( .A0(n4028), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]), .B1(n4041), .Y(n4011) );
OAI21XLTS U5257 ( .A0(n5963), .A1(n4013), .B0(n4011), .Y(n2006) );
AOI22X1TS U5258 ( .A0(n4028), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]), .B1(n4122), .Y(n4012) );
OAI21XLTS U5259 ( .A0(n5974), .A1(n4013), .B0(n4012), .Y(n1975) );
AOI22X1TS U5260 ( .A0(n4014), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[57]), .B1(n4118), .Y(n4015) );
OAI21XLTS U5261 ( .A0(n5962), .A1(n4016), .B0(n4015), .Y(n2252) );
AOI22X1TS U5262 ( .A0(n4038), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]), .B1(n4127), .Y(n4017) );
OAI21XLTS U5263 ( .A0(n5967), .A1(n4021), .B0(n4017), .Y(n1965) );
AOI22X1TS U5264 ( .A0(n4028), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]), .B1(n4041), .Y(n4018) );
OAI21XLTS U5265 ( .A0(n5991), .A1(n4021), .B0(n4018), .Y(n2013) );
AOI22X1TS U5266 ( .A0(n4038), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]), .B1(n4127), .Y(n4019) );
OAI21XLTS U5267 ( .A0(n5981), .A1(n4021), .B0(n4019), .Y(n1951) );
AOI22X1TS U5268 ( .A0(n4028), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]), .B1(n4122), .Y(n4020) );
OAI21XLTS U5269 ( .A0(n5969), .A1(n4021), .B0(n4020), .Y(n1968) );
AOI22X1TS U5270 ( .A0(n4302), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[45]), .B1(n4301), .Y(n4022) );
OAI21XLTS U5271 ( .A0(n5993), .A1(n4304), .B0(n4022), .Y(n2153) );
AOI22X1TS U5272 ( .A0(n4302), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[61]), .B1(n4026), .Y(n4023) );
OAI21XLTS U5273 ( .A0(n5985), .A1(n4304), .B0(n4023), .Y(n2248) );
AOI22X1TS U5274 ( .A0(n4302), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[50]), .B1(n4026), .Y(n4024) );
OAI21XLTS U5275 ( .A0(n5908), .A1(n4304), .B0(n4024), .Y(n2177) );
AOI22X1TS U5276 ( .A0(n4032), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[35]), .B1(n4301), .Y(n4025) );
OAI21XLTS U5277 ( .A0(n5910), .A1(n4304), .B0(n4025), .Y(n2147) );
AOI22X1TS U5278 ( .A0(n4302), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[33]), .B1(n4026), .Y(n4027) );
OAI21XLTS U5279 ( .A0(n5970), .A1(n4304), .B0(n4027), .Y(n2165) );
AOI22X1TS U5280 ( .A0(n4028), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[29]), .B1(n4041), .Y(n4029) );
OAI21XLTS U5281 ( .A0(n5971), .A1(n4034), .B0(n4029), .Y(n2096) );
AOI22X1TS U5282 ( .A0(n4032), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]), .B1(n4031), .Y(n4030) );
OAI21XLTS U5283 ( .A0(n5982), .A1(n4034), .B0(n4030), .Y(n2105) );
AOI22X1TS U5284 ( .A0(n4032), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[31]), .B1(n4031), .Y(n4033) );
OAI21XLTS U5285 ( .A0(n5916), .A1(n4034), .B0(n4033), .Y(n2117) );
AOI22X1TS U5286 ( .A0(n4038), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]), .B1(n4048), .Y(n4035) );
OAI21XLTS U5287 ( .A0(n5992), .A1(n4040), .B0(n4035), .Y(n1921) );
AOI22X1TS U5288 ( .A0(n4038), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]), .B1(n4127), .Y(n4036) );
OAI21XLTS U5289 ( .A0(n5980), .A1(n4040), .B0(n4036), .Y(n1941) );
AOI22X1TS U5290 ( .A0(n4057), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]), .B1(n4051), .Y(n4037) );
OAI21XLTS U5291 ( .A0(n5961), .A1(n4040), .B0(n4037), .Y(n1892) );
AOI22X1TS U5292 ( .A0(n4038), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .B1(n4127), .Y(n4039) );
OAI21XLTS U5293 ( .A0(n5909), .A1(n4040), .B0(n4039), .Y(n1935) );
AOI22X1TS U5294 ( .A0(n4042), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]), .B1(n4041), .Y(n4043) );
OAI21XLTS U5295 ( .A0(n5991), .A1(n4130), .B0(n4043), .Y(n2011) );
AOI22X1TS U5296 ( .A0(n4128), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]), .B1(n4122), .Y(n4044) );
OAI21XLTS U5297 ( .A0(n5974), .A1(n4130), .B0(n4044), .Y(n1973) );
AOI22X1TS U5298 ( .A0(n4131), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]), .B1(n4136), .Y(n4045) );
OAI21XLTS U5299 ( .A0(n5971), .A1(n4133), .B0(n4045), .Y(n1854) );
AOI22X1TS U5300 ( .A0(n4123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .B1(n4048), .Y(n4046) );
OAI21XLTS U5301 ( .A0(n5992), .A1(n4055), .B0(n4046), .Y(n1919) );
AOI22X1TS U5302 ( .A0(n4131), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]), .B1(n4136), .Y(n4047) );
OAI21XLTS U5303 ( .A0(n5982), .A1(n4133), .B0(n4047), .Y(n1842) );
AOI22X1TS U5304 ( .A0(n4123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .B1(n4048), .Y(n4049) );
OAI21XLTS U5305 ( .A0(n5980), .A1(n4055), .B0(n4049), .Y(n1911) );
AOI22X1TS U5306 ( .A0(n4131), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]), .B1(n4136), .Y(n4050) );
OAI21XLTS U5307 ( .A0(n5994), .A1(n4133), .B0(n4050), .Y(n1834) );
AOI22X1TS U5308 ( .A0(n4123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]), .B1(n4051), .Y(n4052) );
OAI21XLTS U5309 ( .A0(n5961), .A1(n4055), .B0(n4052), .Y(n1894) );
AOI22X1TS U5310 ( .A0(n4131), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[31]), .B1(n4136), .Y(n4053) );
OAI21XLTS U5311 ( .A0(n5916), .A1(n4143), .B0(n4053), .Y(n1826) );
AOI22X1TS U5312 ( .A0(n4128), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .B1(n5823), .Y(n4054) );
OAI21XLTS U5313 ( .A0(n5909), .A1(n4055), .B0(n4054), .Y(n1933) );
INVX2TS U5314 ( .A(n4057), .Y(n4151) );
INVX2TS U5315 ( .A(n4304), .Y(n4146) );
AOI22X1TS U5316 ( .A0(n4146), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[45]), .B1(n4148), .Y(n4056) );
OAI21XLTS U5317 ( .A0(n5993), .A1(n4151), .B0(n4056), .Y(n1778) );
AOI22X1TS U5318 ( .A0(n4146), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[50]), .B1(n5255), .Y(n4058) );
OAI21XLTS U5319 ( .A0(n5908), .A1(n4135), .B0(n4058), .Y(n1746) );
AOI22X1TS U5320 ( .A0(n4149), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[35]), .B1(n4148), .Y(n4059) );
OAI21XLTS U5321 ( .A0(n5910), .A1(n4151), .B0(n4059), .Y(n1786) );
AOI22X1TS U5322 ( .A0(n4146), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[33]), .B1(n5255), .Y(n4060) );
OAI21XLTS U5323 ( .A0(n5970), .A1(n4151), .B0(n4060), .Y(n1762) );
AOI22X1TS U5324 ( .A0(n4146), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]), .B1(n5255), .Y(n4061) );
OAI21XLTS U5325 ( .A0(n5983), .A1(n4151), .B0(n4061), .Y(n1770) );
AOI22X1TS U5326 ( .A0(n4355), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .B0(n5562), .B1(n4349), .Y(n4064) );
AOI22X1TS U5327 ( .A0(n4276), .A1(n4220), .B0(n4357), .B1(n4062), .Y(n4063)
);
AOI22X1TS U5328 ( .A0(n4365), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .B0(n4364), .B1(n4257), .Y(n4068) );
AOI22X1TS U5329 ( .A0(n4215), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .B0(n4209), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[36]), .Y(n4066) );
NAND2X1TS U5330 ( .A(n4083), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[38]), .Y(n4065) );
NAND2X1TS U5331 ( .A(n4066), .B(n4065), .Y(n4363) );
AOI22X1TS U5332 ( .A0(n4276), .A1(n4192), .B0(n4367), .B1(n4363), .Y(n4067)
);
CLKBUFX2TS U5333 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n5222) );
OA22X1TS U5334 ( .A0(n4069), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[35]), .B0(n5222), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n4070) );
OAI21XLTS U5335 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]),
.A1(n4211), .B0(n4070), .Y(n4362) );
AOI22X1TS U5336 ( .A0(n4355), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .B0(n4357), .B1(n4348), .Y(n4076) );
OAI22X1TS U5337 ( .A0(n4071), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[37]), .B0(n4080), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n4072) );
AOI21X1TS U5338 ( .A0(n4216), .A1(n6033), .B0(n4072), .Y(n4350) );
AOI22X1TS U5339 ( .A0(n4207), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[36]), .B0(n4073), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n4074) );
OAI2BB1X1TS U5340 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]),
.A1N(n4083), .B0(n4074), .Y(n4356) );
AOI22X1TS U5341 ( .A0(n4276), .A1(n4350), .B0(n5562), .B1(n4356), .Y(n4075)
);
AOI22X1TS U5342 ( .A0(n5559), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]), .B0(n4338), .B1(n4336),
.Y(n4079) );
AOI22X1TS U5343 ( .A0(n5560), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[52]), .B0(n4320), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n4077) );
AOI22X1TS U5344 ( .A0(n4276), .A1(n5563), .B0(n4364), .B1(n5561), .Y(n4078)
);
AOI21X1TS U5345 ( .A0(n4082), .A1(n5934), .B0(n4081), .Y(n4085) );
NAND2X1TS U5346 ( .A(n6034), .B(n4083), .Y(n4084) );
AOI22X1TS U5347 ( .A0(n5559), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .B0(n4338), .B1(n4339),
.Y(n4087) );
AOI22X1TS U5348 ( .A0(n5564), .A1(n4224), .B0(n4225), .B1(n4337), .Y(n4086)
);
AOI22X1TS U5349 ( .A0(n4355), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .B0(n5562), .B1(n4350), .Y(n4089) );
AOI22X1TS U5350 ( .A0(n4359), .A1(n4356), .B0(n4225), .B1(n4348), .Y(n4088)
);
AOI22X1TS U5351 ( .A0(n4355), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .B0(n5562), .B1(n4358), .Y(n4091) );
AOI22X1TS U5352 ( .A0(n4359), .A1(n4251), .B0(n4225), .B1(n4354), .Y(n4090)
);
AOI22X1TS U5353 ( .A0(n4365), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .B0(n4364), .B1(n4192), .Y(n4093) );
AOI22X1TS U5354 ( .A0(n4369), .A1(n4366), .B0(n4329), .B1(n4363), .Y(n4092)
);
AOI22X1TS U5355 ( .A0(n4355), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .B0(n4357), .B1(n4350), .Y(n4095) );
AOI22X1TS U5356 ( .A0(n4359), .A1(n4354), .B0(n4225), .B1(n4356), .Y(n4094)
);
AOI21X1TS U5357 ( .A0(cont_iter_out[1]), .A1(cont_iter_out[0]), .B0(n5361),
.Y(n4306) );
NAND2X1TS U5358 ( .A(n4306), .B(n4096), .Y(n5263) );
INVX2TS U5359 ( .A(n4099), .Y(n5264) );
NAND2X1TS U5360 ( .A(n5264), .B(n5899), .Y(n4097) );
NOR2XLTS U5361 ( .A(n3180), .B(n3176), .Y(n5274) );
NOR2XLTS U5362 ( .A(cont_iter_out[3]), .B(n5960), .Y(n4098) );
AOI211XLTS U5363 ( .A0(n5274), .A1(n5960), .B0(cont_iter_out[1]), .C0(n4098),
.Y(n5316) );
NAND2X1TS U5364 ( .A(n5302), .B(n5316), .Y(n4109) );
NAND2X1TS U5365 ( .A(n5302), .B(n4101), .Y(n5285) );
INVX2TS U5366 ( .A(n5285), .Y(n5268) );
NAND2X1TS U5367 ( .A(cont_iter_out[1]), .B(n5268), .Y(n5312) );
CLKAND2X2TS U5368 ( .A(n5269), .B(n4099), .Y(n5266) );
AOI22X1TS U5369 ( .A0(n3180), .A1(n5311), .B0(n4113), .B1(n5277), .Y(n5271)
);
NOR2X1TS U5370 ( .A(n5899), .B(n4099), .Y(n5289) );
INVX2TS U5371 ( .A(n5274), .Y(n5283) );
AOI22X1TS U5372 ( .A0(n5289), .A1(n5283), .B0(d_ff3_LUT_out[23]), .B1(n5406),
.Y(n4100) );
NAND2X1TS U5373 ( .A(n5289), .B(n5277), .Y(n4102) );
NAND2X1TS U5374 ( .A(n4306), .B(n3176), .Y(n5278) );
AOI22X1TS U5375 ( .A0(n3196), .A1(n5306), .B0(n4113), .B1(n4103), .Y(n5301)
);
INVX2TS U5376 ( .A(n4107), .Y(n4115) );
AOI22X1TS U5377 ( .A0(d_ff3_LUT_out[11]), .A1(n5295), .B0(n4115), .B1(n4112),
.Y(n4104) );
INVX2TS U5378 ( .A(n4298), .Y(n5265) );
AOI21X1TS U5379 ( .A0(d_ff3_LUT_out[33]), .A1(n5361), .B0(n4105), .Y(n4106)
);
NAND2X1TS U5380 ( .A(n5960), .B(n3184), .Y(n5310) );
AOI21X1TS U5381 ( .A0(n5311), .A1(n5310), .B0(n5307), .Y(n5287) );
INVX2TS U5382 ( .A(n4113), .Y(n5288) );
AOI21X1TS U5383 ( .A0(n5302), .A1(cont_iter_out[3]), .B0(n5307), .Y(n5280)
);
AOI21X1TS U5384 ( .A0(n5289), .A1(n3180), .B0(n4111), .Y(n5276) );
AOI22X1TS U5385 ( .A0(d_ff3_LUT_out[7]), .A1(n5295), .B0(n4113), .B1(n4112),
.Y(n4114) );
AOI22X1TS U5386 ( .A0(n4115), .A1(n5283), .B0(d_ff3_LUT_out[3]), .B1(n5361),
.Y(n4117) );
INVX2TS U5387 ( .A(n5272), .Y(n4116) );
AOI22X1TS U5388 ( .A0(n4119), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[54]), .B1(n4118), .Y(n4120) );
AOI22X1TS U5389 ( .A0(n4123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[51]), .B1(n4122), .Y(n4124) );
AOI22X1TS U5390 ( .A0(n4128), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]), .B1(n4127), .Y(n4125) );
AOI22X1TS U5391 ( .A0(n4131), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]), .B1(n4136), .Y(n4126) );
AOI22X1TS U5392 ( .A0(n4128), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]), .B1(n4127), .Y(n4129) );
AOI22X1TS U5393 ( .A0(n4131), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[32]), .B1(n4136), .Y(n4132) );
AOI22X1TS U5394 ( .A0(n4146), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[47]), .B1(n5255), .Y(n4134) );
AOI22X1TS U5395 ( .A0(n4149), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]), .B1(n4136), .Y(n4137) );
AOI22X1TS U5396 ( .A0(n4146), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[49]), .B1(n5255), .Y(n4138) );
AOI22X1TS U5397 ( .A0(n4149), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[43]), .B1(n4148), .Y(n4139) );
AOI22X1TS U5398 ( .A0(n4149), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[38]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[38]), .B1(n4148), .Y(n4140) );
AOI22X1TS U5399 ( .A0(n4146), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[34]), .B1(n5255), .Y(n4141) );
AOI22X1TS U5400 ( .A0(n4149), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[40]), .B1(n4148), .Y(n4142) );
AOI22X1TS U5401 ( .A0(n4146), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[48]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[48]), .B1(n5255), .Y(n4144) );
AOI22X1TS U5402 ( .A0(n4146), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[44]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[44]), .B1(n5255), .Y(n4145) );
AOI22X1TS U5403 ( .A0(n4146), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[46]), .B1(n4148), .Y(n4147) );
AOI22X1TS U5404 ( .A0(n4149), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[42]), .B1(n4148), .Y(n4150) );
AOI22X1TS U5405 ( .A0(n4154), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]), .B0(n4153), .B1(
n4152), .Y(n4162) );
AOI31XLTS U5406 ( .A0(n4157), .A1(n5923), .A2(n5898), .B0(n4156), .Y(n4159)
);
AOI211XLTS U5407 ( .A0(n4160), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B0(n4159), .C0(
n4158), .Y(n4161) );
AOI21X1TS U5408 ( .A0(n4166), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .B0(n4165), .Y(n4317) );
AOI22X1TS U5409 ( .A0(n5554), .A1(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .B0(n4183), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n4167) );
NOR2BX1TS U5410 ( .AN(n4168), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n4172) );
NOR3BXLTS U5411 ( .AN(n4174), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .C(n4173), .Y(n4178)
);
OAI211XLTS U5412 ( .A0(n4178), .A1(n4177), .B0(n4176), .C0(n4175), .Y(n4179)
);
NAND2X1TS U5413 ( .A(n4320), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[5]), .Y(n4182) );
AOI22X1TS U5414 ( .A0(n5554), .A1(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[5]), .B0(n4183), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[5]), .Y(n4184) );
AOI22X1TS U5415 ( .A0(n4283), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .B0(n4324), .B1(n4275), .Y(n4188) );
AOI22X1TS U5416 ( .A0(n4203), .A1(n4277), .B0(n4282), .B1(n4263), .Y(n4187)
);
AOI22X1TS U5417 ( .A0(n4283), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .B0(n4367), .B1(n4269), .Y(n4190) );
AOI22X1TS U5418 ( .A0(n4203), .A1(n4268), .B0(n4324), .B1(n4264), .Y(n4189)
);
INVX2TS U5419 ( .A(n4363), .Y(n4195) );
AOI22X1TS U5420 ( .A0(n4365), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .B0(n4364), .B1(n4191), .Y(n4194) );
AOI22X1TS U5421 ( .A0(n4203), .A1(n4257), .B0(n4367), .B1(n4192), .Y(n4193)
);
AOI22X1TS U5422 ( .A0(n4365), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .B0(n4364), .B1(n4246), .Y(n4197) );
AOI22X1TS U5423 ( .A0(n4203), .A1(n4255), .B0(n4367), .B1(n4256), .Y(n4196)
);
AOI22X1TS U5424 ( .A0(n5556), .A1(n4338), .B0(n5554), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[52]), .Y(n4199) );
NAND2X1TS U5425 ( .A(n4276), .B(n4270), .Y(n4198) );
AOI22X1TS U5426 ( .A0(n5559), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .B0(n5555), .B1(n4200),
.Y(n4202) );
AOI22X1TS U5427 ( .A0(n4203), .A1(n4226), .B0(n4338), .B1(n4219), .Y(n4201)
);
AOI22X1TS U5428 ( .A0(n5559), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .B0(n5555), .B1(n4337),
.Y(n4205) );
AOI22X1TS U5429 ( .A0(n4203), .A1(n4339), .B0(n4338), .B1(n4224), .Y(n4204)
);
AOI22X1TS U5430 ( .A0(n5556), .A1(n4225), .B0(n5555), .B1(n4270), .Y(n4206)
);
AOI22X1TS U5431 ( .A0(n4207), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[26]), .B0(n4209), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[26]), .Y(n4208) );
AOI22X1TS U5432 ( .A0(n4330), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .B0(n4357), .B1(n4235), .Y(n4213) );
AOI22X1TS U5433 ( .A0(n4215), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n4209), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[27]), .Y(n4210) );
AOI22X1TS U5434 ( .A0(n4225), .A1(n4244), .B0(n4367), .B1(n4245), .Y(n4212)
);
AOI22X1TS U5435 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .A1(
n4216), .B0(n4215), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[53]), .Y(n5567) );
AOI22X1TS U5436 ( .A0(n4330), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]), .B0(n4338), .B1(n5563),
.Y(n4218) );
AOI22X1TS U5437 ( .A0(n5564), .A1(n4336), .B0(n4276), .B1(n5561), .Y(n4217)
);
AOI22X1TS U5438 ( .A0(n4355), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .B0(n5555), .B1(n4226), .Y(n4222) );
AOI22X1TS U5439 ( .A0(n5564), .A1(n4220), .B0(n4225), .B1(n4219), .Y(n4221)
);
AOI22X1TS U5440 ( .A0(n5559), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .B0(n5555), .B1(n4339),
.Y(n4228) );
AOI22X1TS U5441 ( .A0(n5564), .A1(n4226), .B0(n4225), .B1(n4224), .Y(n4227)
);
MX2X1TS U5442 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[27]), .S0(n5221), .Y(
n4233) );
AOI22X1TS U5443 ( .A0(n4234), .A1(n4233), .B0(n4235), .B1(n4232), .Y(n4327)
);
AOI22X1TS U5444 ( .A0(n4369), .A1(n4245), .B0(n5554), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .Y(n4231) );
NAND2X1TS U5445 ( .A(n4282), .B(n4244), .Y(n4230) );
AOI22X1TS U5446 ( .A0(n4234), .A1(n4323), .B0(n4233), .B1(n4232), .Y(n4334)
);
AOI22X1TS U5447 ( .A0(n4369), .A1(n4244), .B0(n5554), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .Y(n4237) );
NAND2X1TS U5448 ( .A(n4282), .B(n4235), .Y(n4236) );
AOI22X1TS U5449 ( .A0(n4330), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .B0(n4357), .B1(n4251), .Y(n4240) );
AOI22X1TS U5450 ( .A0(n4359), .A1(n4328), .B0(n4329), .B1(n4250), .Y(n4239)
);
AOI22X1TS U5451 ( .A0(n4365), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .B0(n4367), .B1(n4255), .Y(n4243) );
AOI22X1TS U5452 ( .A0(n4369), .A1(n4256), .B0(n4329), .B1(n4246), .Y(n4242)
);
AOI22X1TS U5453 ( .A0(n4330), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .B0(n4364), .B1(n4244), .Y(n4248) );
AOI22X1TS U5454 ( .A0(n4369), .A1(n4246), .B0(n4329), .B1(n4245), .Y(n4247)
);
AOI22X1TS U5455 ( .A0(n4330), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .B0(n5562), .B1(n4250), .Y(n4253) );
AOI22X1TS U5456 ( .A0(n4359), .A1(n4331), .B0(n4329), .B1(n4251), .Y(n4252)
);
AOI22X1TS U5457 ( .A0(n4365), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .B0(n4364), .B1(n4255), .Y(n4259) );
AOI22X1TS U5458 ( .A0(n4369), .A1(n4257), .B0(n4329), .B1(n4256), .Y(n4258)
);
AOI22X1TS U5459 ( .A0(n4283), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .B0(n4282), .B1(n4268), .Y(n4262) );
AOI22X1TS U5460 ( .A0(n4286), .A1(n4269), .B0(n4276), .B1(n4264), .Y(n4261)
);
AOI22X1TS U5461 ( .A0(n4283), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .B0(n4324), .B1(n4277), .Y(n4266) );
AOI22X1TS U5462 ( .A0(n4286), .A1(n4264), .B0(n4276), .B1(n4263), .Y(n4265)
);
AOI22X1TS U5463 ( .A0(n5554), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .B0(n4324), .B1(n4268), .Y(n4272) );
AOI22X1TS U5464 ( .A0(n4286), .A1(n4270), .B0(n4276), .B1(n4269), .Y(n4271)
);
AOI22X1TS U5465 ( .A0(n4283), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .B0(n4282), .B1(n4275), .Y(n4279) );
AOI22X1TS U5466 ( .A0(n4286), .A1(n4277), .B0(n4276), .B1(n4285), .Y(n4278)
);
AOI22X1TS U5467 ( .A0(n4283), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .B0(n4282), .B1(n4281), .Y(n4288) );
AOI22X1TS U5468 ( .A0(n4286), .A1(n4285), .B0(n4329), .B1(n4284), .Y(n4287)
);
CLKBUFX2TS U5469 ( .A(n6094), .Y(n5890) );
INVX2TS U5470 ( .A(n5890), .Y(busy) );
NOR3XLTS U5471 ( .A(n5258), .B(n5249), .C(ready_add_subt), .Y(n5261) );
OAI21XLTS U5472 ( .A0(n5261), .A1(n5892), .B0(cont_var_out[1]), .Y(n4291) );
NOR3XLTS U5473 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .C(
n5944), .Y(n5254) );
AOI31XLTS U5474 ( .A0(n4292), .A1(n5253), .A2(n6093), .B0(n5254), .Y(n4293)
);
OAI21XLTS U5475 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
n4381), .B0(n4293), .Y(n3172) );
OAI21XLTS U5476 ( .A0(n5221), .A1(n3183), .B0(n4294), .Y(n2081) );
OAI21XLTS U5477 ( .A0(n4296), .A1(n5907), .B0(n5557), .Y(n3043) );
AOI22X1TS U5478 ( .A0(n3180), .A1(n4306), .B0(d_ff3_LUT_out[14]), .B1(n5406),
.Y(n4297) );
OAI21XLTS U5479 ( .A0(n3184), .A1(n4298), .B0(n4297), .Y(n3125) );
AOI22X1TS U5480 ( .A0(n5493), .A1(d_ff3_sh_y_out[32]), .B0(n5487), .B1(
d_ff3_sh_x_out[32]), .Y(n4300) );
OAI211XLTS U5481 ( .A0(n5585), .A1(n6086), .B0(n4300), .C0(n4299), .Y(n2652)
);
AOI22X1TS U5482 ( .A0(n4302), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]), .B1(n4301), .Y(n4303) );
OAI21XLTS U5483 ( .A0(n5983), .A1(n4304), .B0(n4303), .Y(n2159) );
CLKBUFX2TS U5484 ( .A(n5427), .Y(n5677) );
CLKBUFX2TS U5485 ( .A(n5677), .Y(n5672) );
CLKBUFX2TS U5486 ( .A(n5737), .Y(n5663) );
AOI22X1TS U5487 ( .A0(d_ff3_sh_x_out[62]), .A1(n5672), .B0(n5663), .B1(
d_ff3_sh_y_out[62]), .Y(n4305) );
OAI21XLTS U5488 ( .A0(n5585), .A1(n5995), .B0(n4305), .Y(n2562) );
INVX2TS U5489 ( .A(n5289), .Y(n5313) );
AOI22X1TS U5490 ( .A0(d_ff3_LUT_out[54]), .A1(n5295), .B0(n4306), .B1(n5928),
.Y(n4307) );
OAI21XLTS U5491 ( .A0(n5928), .A1(n5313), .B0(n4307), .Y(n3156) );
AOI22X1TS U5492 ( .A0(n5493), .A1(d_ff3_sh_y_out[4]), .B0(n5430), .B1(
d_ff3_sh_x_out[4]), .Y(n4309) );
OAI211XLTS U5493 ( .A0(n5439), .A1(n5961), .B0(n4309), .C0(n4308), .Y(n2736)
);
AOI22X1TS U5494 ( .A0(n5612), .A1(d_ff3_sh_y_out[49]), .B0(n5527), .B1(
d_ff3_sh_x_out[49]), .Y(n4311) );
OAI211XLTS U5495 ( .A0(n5585), .A1(n6084), .B0(n4311), .C0(n4310), .Y(n2601)
);
AOI22X1TS U5496 ( .A0(n5588), .A1(d_ff3_sh_y_out[57]), .B0(n5527), .B1(
d_ff3_sh_x_out[57]), .Y(n4312) );
OAI211XLTS U5497 ( .A0(n5585), .A1(n5962), .B0(n4312), .C0(n4314), .Y(n2572)
);
AOI22X1TS U5498 ( .A0(n5612), .A1(d_ff3_sh_y_out[51]), .B0(n5527), .B1(
d_ff3_sh_x_out[51]), .Y(n4313) );
OAI211XLTS U5499 ( .A0(n5585), .A1(n6085), .B0(n4313), .C0(n4314), .Y(n2595)
);
AOI22X1TS U5500 ( .A0(n5588), .A1(d_ff3_sh_y_out[61]), .B0(n5650), .B1(
d_ff3_sh_x_out[61]), .Y(n4315) );
OAI211XLTS U5501 ( .A0(n5745), .A1(n5985), .B0(n4315), .C0(n4314), .Y(n2564)
);
NAND2X1TS U5502 ( .A(n4320), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n4316) );
OAI21XLTS U5503 ( .A0(n4317), .A1(n5906), .B0(n4316), .Y(n2025) );
NAND2X1TS U5504 ( .A(n4320), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]), .Y(n4318) );
OAI21XLTS U5505 ( .A0(n4319), .A1(n5906), .B0(n4318), .Y(n2182) );
NAND2X1TS U5506 ( .A(n4320), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n4321) );
OAI21XLTS U5507 ( .A0(n4322), .A1(n5906), .B0(n4321), .Y(n2026) );
AOI22X1TS U5508 ( .A0(n4330), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .B0(n4329), .B1(n4323), .Y(n4326) );
NAND2X1TS U5509 ( .A(n4324), .B(n4328), .Y(n4325) );
OAI211XLTS U5510 ( .A0(n4335), .A1(n4327), .B0(n4326), .C0(n4325), .Y(n2531)
);
AOI22X1TS U5511 ( .A0(n4330), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B0(n4329), .B1(n4328), .Y(n4333) );
OAI211XLTS U5512 ( .A0(n4335), .A1(n4334), .B0(n4333), .C0(n4332), .Y(n2530)
);
AOI22X1TS U5513 ( .A0(n5559), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .B0(n5555), .B1(n4336),
.Y(n4341) );
AOI22X1TS U5514 ( .A0(n5564), .A1(n4339), .B0(n4338), .B1(n4337), .Y(n4340)
);
OAI211XLTS U5515 ( .A0(n3195), .A1(n4342), .B0(n4341), .C0(n4340), .Y(n2510)
);
CLKBUFX2TS U5516 ( .A(n6094), .Y(n5770) );
AO22XLTS U5517 ( .A0(n4343), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]), .B1(n5770), .Y(n6044)
);
AO22XLTS U5518 ( .A0(n4343), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]), .B1(n5770), .Y(n6045)
);
AO22XLTS U5519 ( .A0(n4343), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]), .B1(n5770), .Y(n6046)
);
AO22XLTS U5520 ( .A0(n4343), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]), .B1(n5770), .Y(n6047)
);
AO22XLTS U5521 ( .A0(n4343), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]), .B1(n5770), .Y(n6048)
);
AO22XLTS U5522 ( .A0(n4343), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]), .B1(n5770), .Y(n6049)
);
CLKBUFX2TS U5523 ( .A(n6094), .Y(n4344) );
AO22XLTS U5524 ( .A0(n4343), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]), .B1(n4344), .Y(n6050)
);
AO22XLTS U5525 ( .A0(n4343), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]), .B1(n4344), .Y(n6051)
);
AO22XLTS U5526 ( .A0(n4343), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]), .B1(n5770), .Y(n6052)
);
AO22XLTS U5527 ( .A0(n4343), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7]), .B1(n4344), .Y(n6053)
);
AO22XLTS U5528 ( .A0(n4345), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[35]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[35]), .B1(n4347), .Y(n6054)
);
AO22XLTS U5529 ( .A0(n5894), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]), .B1(n4347), .Y(n6055)
);
AO22XLTS U5530 ( .A0(n4345), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]), .B1(n4344), .Y(n6056)
);
AO22XLTS U5531 ( .A0(n4345), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]), .B1(n4344), .Y(n6057)
);
CLKBUFX2TS U5532 ( .A(n6094), .Y(n4346) );
AO22XLTS U5533 ( .A0(n4345), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]), .B1(n4346), .Y(n6058)
);
AO22XLTS U5534 ( .A0(n4345), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]), .B1(n4344), .Y(n6059)
);
AO22XLTS U5535 ( .A0(n4345), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]), .B1(n4344), .Y(n6060)
);
AO22XLTS U5536 ( .A0(n4345), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]), .B1(n4344), .Y(n6061)
);
AO22XLTS U5537 ( .A0(n5894), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]), .B1(n4346), .Y(n6062)
);
AO22XLTS U5538 ( .A0(n5894), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]), .B1(n4347), .Y(n6063)
);
AO22XLTS U5539 ( .A0(n5894), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]), .B1(n4346), .Y(n6064)
);
AO22XLTS U5540 ( .A0(n5894), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]), .B1(n4346), .Y(n6065)
);
AO22XLTS U5541 ( .A0(n5894), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]), .B1(n4346), .Y(n6066)
);
AO22XLTS U5542 ( .A0(n5894), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]), .B1(n4346), .Y(n6067)
);
AO22XLTS U5543 ( .A0(n5894), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]), .B1(n4346), .Y(n6068)
);
AO22XLTS U5544 ( .A0(n5894), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]), .B1(n4346), .Y(n6069)
);
AO22XLTS U5545 ( .A0(n4345), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]), .B1(n4344), .Y(n6070)
);
AO22XLTS U5546 ( .A0(n4345), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]), .B1(n4344), .Y(n6071)
);
AO22XLTS U5547 ( .A0(n4345), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]), .B1(n4346), .Y(n6072)
);
AO22XLTS U5548 ( .A0(n5894), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]), .B1(n4346), .Y(n6073)
);
AO22XLTS U5549 ( .A0(n5771), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[33]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[33]), .B1(n5890), .Y(n6074)
);
AO22XLTS U5550 ( .A0(n5771), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[34]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[34]), .B1(n4347), .Y(n6075)
);
AO22XLTS U5551 ( .A0(n5771), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[31]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[31]), .B1(n6094), .Y(n6076)
);
AO22XLTS U5552 ( .A0(n5771), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]), .B1(n6094), .Y(n6077)
);
AO22XLTS U5553 ( .A0(n5771), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[32]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[32]), .B1(n4347), .Y(n6078)
);
AO22XLTS U5554 ( .A0(n5771), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]), .B1(n6094), .Y(n6079)
);
AOI22X1TS U5555 ( .A0(n4355), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .B0(n5562), .B1(n4348), .Y(n4352) );
AOI22X1TS U5556 ( .A0(n4359), .A1(n4350), .B0(n4357), .B1(n4349), .Y(n4351)
);
AOI22X1TS U5557 ( .A0(n4355), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .B0(n5562), .B1(n4354), .Y(n4361) );
AOI22X1TS U5558 ( .A0(n4359), .A1(n4358), .B0(n4357), .B1(n4356), .Y(n4360)
);
AOI22X1TS U5559 ( .A0(n4365), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .B0(n4364), .B1(n4363), .Y(n4371) );
AOI22X1TS U5560 ( .A0(n4369), .A1(n4368), .B0(n4367), .B1(n4366), .Y(n4370)
);
OAI2BB1X1TS U5561 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]),
.A1N(n5873), .B0(n4374), .Y(n2023) );
NOR2BX1TS U5562 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[5]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4375) );
NOR2BX1TS U5563 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4376) );
NOR2BX1TS U5564 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4377) );
NOR2BX1TS U5565 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4378) );
NOR2BX1TS U5566 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4379) );
CLKBUFX2TS U5567 ( .A(n4380), .Y(n6183) );
CLKBUFX2TS U5568 ( .A(n4380), .Y(n6184) );
NOR2X1TS U5569 ( .A(n6032), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n5777) );
CLKBUFX2TS U5570 ( .A(n5777), .Y(n4680) );
MX2X1TS U5571 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[51]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[51]), .S0(n4680), .Y(n1739)
);
CLKBUFX2TS U5572 ( .A(n5777), .Y(n5776) );
CLKBUFX2TS U5573 ( .A(n5776), .Y(n5871) );
MX2X1TS U5574 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[50]), .S0(n5871), .Y(n1743)
);
MX2X1TS U5575 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[49]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[49]), .S0(n5871), .Y(n1751)
);
MX2X1TS U5576 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[48]), .S0(n5871), .Y(n1755)
);
MX2X1TS U5577 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[47]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[47]), .S0(n5871), .Y(n1747)
);
MX2X1TS U5578 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[46]), .S0(n5871), .Y(n1779)
);
MX2X1TS U5579 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[45]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[45]), .S0(n5871), .Y(n1775)
);
CLKBUFX2TS U5580 ( .A(n4680), .Y(n4382) );
MX2X1TS U5581 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[44]), .S0(n4382), .Y(n1763)
);
MX2X1TS U5582 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[43]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[43]), .S0(n5871), .Y(n1791)
);
MX2X1TS U5583 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[42]), .S0(n5871), .Y(n1787)
);
MX2X1TS U5584 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[41]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[41]), .S0(n4382), .Y(n1803)
);
MX2X1TS U5585 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[40]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[40]), .S0(n4382), .Y(n1811)
);
MX2X1TS U5586 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[39]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[39]), .S0(n4382), .Y(n1799)
);
MX2X1TS U5587 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[38]), .S0(n4382), .Y(n1807)
);
MX2X1TS U5588 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[37]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[37]), .S0(n4382), .Y(n1815)
);
MX2X1TS U5589 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[36]), .S0(n4382), .Y(n1795)
);
CLKBUFX2TS U5590 ( .A(n4680), .Y(n4384) );
MX2X1TS U5591 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[35]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[35]), .S0(n4384), .Y(n1783)
);
MX2X1TS U5592 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[34]), .S0(n4382), .Y(n1771)
);
MX2X1TS U5593 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[33]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[33]), .S0(n4382), .Y(n1759)
);
MX2X1TS U5594 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[32]), .S0(n4382), .Y(n1843)
);
CLKBUFX2TS U5595 ( .A(n4680), .Y(n4383) );
MX2X1TS U5596 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[31]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[31]), .S0(n4383), .Y(n1823)
);
MX2X1TS U5597 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]), .S0(n4383), .Y(n1835)
);
MX2X1TS U5598 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]), .S0(n4383), .Y(n1851)
);
MX2X1TS U5599 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]), .S0(n4383), .Y(n1819)
);
MX2X1TS U5600 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]), .S0(n4383), .Y(n1912)
);
MX2X1TS U5601 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]), .S0(n4383), .Y(n1908)
);
MX2X1TS U5602 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]), .S0(n4383), .Y(n1916)
);
MX2X1TS U5603 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]), .S0(n4383), .Y(n1923)
);
MX2X1TS U5604 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]), .S0(n4383), .Y(n1930)
);
MX2X1TS U5605 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]), .S0(n4383), .Y(n1943)
);
MX2X1TS U5606 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]), .S0(n4384), .Y(n1960)
);
MX2X1TS U5607 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]), .S0(n4384), .Y(n1970)
);
MX2X1TS U5608 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]), .S0(n4384), .Y(n2015)
);
MX2X1TS U5609 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]), .S0(n4384), .Y(n2008)
);
MX2X1TS U5610 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]), .S0(n4384), .Y(n1839)
);
MX2X1TS U5611 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]), .S0(n4384), .Y(n2001)
);
MX2X1TS U5612 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]), .S0(n4384), .Y(n1831)
);
MX2X1TS U5613 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]), .S0(n4384), .Y(n1847)
);
MX2X1TS U5614 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]), .S0(n4384), .Y(n1855)
);
CLKBUFX2TS U5615 ( .A(n5777), .Y(n5869) );
MX2X1TS U5616 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]), .S0(n5869), .Y(n1827)
);
MX2X1TS U5617 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]), .S0(n5869), .Y(n1904)
);
MX2X1TS U5618 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]), .S0(n5869), .Y(n1994)
);
MX2X1TS U5619 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]), .S0(n5869), .Y(n1953)
);
MX2X1TS U5620 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]), .S0(n5869), .Y(n1900)
);
CLKBUFX2TS U5621 ( .A(n5869), .Y(n4662) );
MX2X1TS U5622 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7]), .S0(n4662), .Y(n1987)
);
MX2X1TS U5623 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]), .S0(n4662), .Y(n1980)
);
MX2X1TS U5624 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]), .S0(n5777), .Y(n1896)
);
MX2X1TS U5625 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]), .S0(n5869), .Y(n1889)
);
MX2X1TS U5626 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]), .S0(n4662), .Y(n1767)
);
CLKBUFX2TS U5627 ( .A(n5777), .Y(n4510) );
MX2X1TS U5628 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]), .S0(n4510), .Y(n1882)
);
MX2X1TS U5629 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]), .S0(n4510), .Y(n1875)
);
MX2X1TS U5630 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]), .S0(n4510), .Y(n1868)
);
NAND2X1TS U5631 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]),
.B(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4467) );
NAND2X1TS U5632 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(n5940), .Y(n4476) );
AOI22X1TS U5633 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .A1(
n3187), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B1(n3199),
.Y(n4394) );
OR2X1TS U5634 ( .A(n5940), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4458) );
OR2X1TS U5635 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4477) );
AOI22X1TS U5636 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .A1(
n3190), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]), .B1(n3185),
.Y(n4393) );
INVX2TS U5637 ( .A(n4467), .Y(n4479) );
CLKBUFX2TS U5638 ( .A(n4479), .Y(n4514) );
INVX2TS U5639 ( .A(n4458), .Y(n4511) );
AOI22X1TS U5640 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .A1(
n4514), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .B1(n4511), .Y(n4386) );
INVX2TS U5641 ( .A(n4476), .Y(n4398) );
CLKBUFX2TS U5642 ( .A(n4398), .Y(n4512) );
INVX2TS U5643 ( .A(n4477), .Y(n4502) );
AOI22X1TS U5644 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .A1(
n4512), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .B1(n4502), .Y(n4385) );
NAND2X1TS U5645 ( .A(n4386), .B(n4385), .Y(n4572) );
NAND2X1TS U5646 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]),
.B(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[5]), .Y(n4438) );
INVX2TS U5647 ( .A(n4458), .Y(n4491) );
INVX2TS U5648 ( .A(n4477), .Y(n4490) );
NAND2X1TS U5649 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .Y(n4457) );
OAI2BB1X1TS U5650 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]),
.A1N(n4490), .B0(n4457), .Y(n4387) );
AOI21X1TS U5651 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[52]), .A1(
n4491), .B0(n4387), .Y(n4574) );
AOI2BB2XLTS U5652 ( .B0(n3182), .B1(n4572), .A0N(n4438), .A1N(n4574), .Y(
n4392) );
OR2X1TS U5653 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[5]), .B(
n6013), .Y(n4570) );
INVX2TS U5654 ( .A(n4570), .Y(n4390) );
AOI22X1TS U5655 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .A1(
n4514), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .B1(n4511), .Y(n4389) );
AOI22X1TS U5656 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .A1(
n4512), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .B1(n4502), .Y(n4388) );
NAND2X1TS U5657 ( .A(n4389), .B(n4388), .Y(n4532) );
NAND2X1TS U5658 ( .A(n4390), .B(n4532), .Y(n4391) );
NOR2XLTS U5659 ( .A(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .B(n4490),
.Y(n4415) );
INVX2TS U5660 ( .A(n4534), .Y(n4579) );
NAND2X1TS U5661 ( .A(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .B(n4545),
.Y(n4530) );
CLKBUFX2TS U5662 ( .A(n6041), .Y(n4531) );
AOI22X1TS U5663 ( .A0(n5895), .A1(n4678), .B0(n4677), .B1(n4531), .Y(n4395)
);
INVX2TS U5664 ( .A(n4531), .Y(n4676) );
AOI22X1TS U5665 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .A1(
n3190), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]), .B1(n3185),
.Y(n4405) );
AOI22X1TS U5666 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .A1(
n3188), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .B1(n3199),
.Y(n4404) );
CLKBUFX2TS U5667 ( .A(n4398), .Y(n4504) );
AOI22X1TS U5668 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .A1(
n4514), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .B1(n4504), .Y(n4397) );
INVX2TS U5669 ( .A(n4458), .Y(n4503) );
INVX2TS U5670 ( .A(n4477), .Y(n4513) );
AOI22X1TS U5671 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .A1(
n4503), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .B1(n4513), .Y(n4396) );
NAND2X1TS U5672 ( .A(n4397), .B(n4396), .Y(n4564) );
INVX2TS U5673 ( .A(n4570), .Y(n4563) );
INVX2TS U5674 ( .A(n4477), .Y(n4521) );
AOI22X1TS U5675 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .A1(
n4479), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .B1(n4521), .Y(n4400) );
CLKBUFX2TS U5676 ( .A(n4398), .Y(n4524) );
AOI22X1TS U5677 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .A1(
n4524), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .B1(n4511), .Y(n4399) );
NAND2X1TS U5678 ( .A(n4400), .B(n4399), .Y(n4539) );
AOI22X1TS U5679 ( .A0(n4568), .A1(n4564), .B0(n4563), .B1(n4539), .Y(n4403)
);
INVX2TS U5680 ( .A(n4438), .Y(n4445) );
INVX2TS U5681 ( .A(n4458), .Y(n4523) );
AOI22X1TS U5682 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .A1(
n4513), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[53]), .B1(n4523), .Y(n4401) );
NAND2X1TS U5683 ( .A(n4401), .B(n4457), .Y(n4562) );
NAND2X1TS U5684 ( .A(n4445), .B(n4562), .Y(n4402) );
AOI22X1TS U5685 ( .A0(n4513), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[53]), .B0(
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .B1(n4477), .Y(n4537) );
AOI22X1TS U5686 ( .A0(n4676), .A1(n4674), .B0(n4673), .B1(n4639), .Y(n5779)
);
AOI22X1TS U5687 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .A1(
n3198), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]), .B1(n3185),
.Y(n4414) );
AOI22X1TS U5688 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .A1(
n3188), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .B1(n3189),
.Y(n4413) );
AOI22X1TS U5689 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .A1(
n4513), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[54]), .B1(n4491), .Y(n4406) );
NAND2X1TS U5690 ( .A(n4406), .B(n4457), .Y(n4556) );
AOI22X1TS U5691 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .A1(
n4524), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .B1(n4490), .Y(n4408) );
AOI22X1TS U5692 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .A1(
n4479), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .B1(n4523), .Y(n4407) );
NAND2X1TS U5693 ( .A(n4408), .B(n4407), .Y(n4546) );
AOI22X1TS U5694 ( .A0(n4445), .A1(n4556), .B0(n4563), .B1(n4546), .Y(n4412)
);
AOI22X1TS U5695 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .A1(
n4503), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .B1(n4490), .Y(n4410) );
CLKBUFX2TS U5696 ( .A(n4479), .Y(n4522) );
AOI22X1TS U5697 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .A1(
n4522), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B1(n4504), .Y(n4409) );
NAND2X1TS U5698 ( .A(n4410), .B(n4409), .Y(n4555) );
NAND2X1TS U5699 ( .A(n3182), .B(n4555), .Y(n4411) );
AOI22X1TS U5700 ( .A0(n4513), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[52]), .B0(
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .B1(n4477), .Y(n4542) );
AOI22X1TS U5701 ( .A0(n4676), .A1(n4672), .B0(n4671), .B1(n4639), .Y(n5780)
);
INVX2TS U5702 ( .A(n4531), .Y(n4536) );
AOI22X1TS U5703 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .A1(
n3188), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .B1(n3189),
.Y(n4423) );
AOI21X1TS U5704 ( .A0(n4513), .A1(n6021), .B0(n4415), .Y(n4549) );
AOI22X1TS U5705 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .A1(
n3198), .B0(n4445), .B1(n4549), .Y(n4422) );
AOI22X1TS U5706 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .A1(
n4479), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .B1(n4521), .Y(n4417) );
AOI22X1TS U5707 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .A1(
n4524), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .B1(n4523), .Y(n4416) );
NAND2X1TS U5708 ( .A(n4417), .B(n4416), .Y(n4552) );
INVX2TS U5709 ( .A(n4570), .Y(n4543) );
AOI22X1TS U5710 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .A1(
n4503), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .B1(n4521), .Y(n4419) );
AOI22X1TS U5711 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .A1(
n4522), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .B1(n4504), .Y(n4418) );
NAND2X1TS U5712 ( .A(n4419), .B(n4418), .Y(n4551) );
AOI22X1TS U5713 ( .A0(n3182), .A1(n4552), .B0(n4543), .B1(n4551), .Y(n4421)
);
NAND2X1TS U5714 ( .A(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]), .B(
n3186), .Y(n4420) );
INVX2TS U5715 ( .A(n4549), .Y(n4554) );
AOI22X1TS U5716 ( .A0(n4536), .A1(n4670), .B0(n4669), .B1(n4639), .Y(n5783)
);
AOI22X1TS U5717 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .A1(
n4522), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .B1(n4523), .Y(n4424) );
OAI2BB1X1TS U5718 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]),
.A1N(n4490), .B0(n4424), .Y(n4425) );
AOI21X1TS U5719 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .A1(
n4504), .B0(n4425), .Y(n4561) );
INVX2TS U5720 ( .A(n3182), .Y(n4580) );
AOI22X1TS U5721 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .A1(
n4522), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B1(n4523), .Y(n4427) );
AOI22X1TS U5722 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .A1(
n4524), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .B1(n4521), .Y(n4426) );
NAND2X1TS U5723 ( .A(n4427), .B(n4426), .Y(n4558) );
AOI22X1TS U5724 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .A1(
n3188), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .B1(n3198), .Y(n4429) );
AOI22X1TS U5725 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .A1(
n3190), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .B1(n3186),
.Y(n4428) );
AOI21X1TS U5726 ( .A0(n4543), .A1(n4558), .B0(n4430), .Y(n4431) );
INVX2TS U5727 ( .A(n4556), .Y(n4548) );
AOI22X1TS U5728 ( .A0(n4536), .A1(n4668), .B0(n4667), .B1(n4531), .Y(n5784)
);
AOI22X1TS U5729 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .A1(
n4503), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .B1(n4521), .Y(n4432) );
AOI21X1TS U5730 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .A1(
n4479), .B0(n4433), .Y(n4571) );
AOI22X1TS U5731 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .A1(
n4524), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .B1(n4523), .Y(n4435) );
AOI22X1TS U5732 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .A1(
n4522), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .B1(n4521), .Y(n4434) );
NAND2X1TS U5733 ( .A(n4435), .B(n4434), .Y(n4566) );
AOI22X1TS U5734 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .A1(
n3187), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .B1(n3189),
.Y(n4437) );
AOI22X1TS U5735 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .A1(
n3199), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .B1(n3185),
.Y(n4436) );
AOI21X1TS U5736 ( .A0(n4543), .A1(n4566), .B0(n4439), .Y(n4440) );
INVX2TS U5737 ( .A(n4562), .Y(n4541) );
AOI22X1TS U5738 ( .A0(n4676), .A1(n4666), .B0(n4665), .B1(n4639), .Y(n5781)
);
AOI22X1TS U5739 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .A1(
n3190), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .B1(n3186),
.Y(n4449) );
AOI22X1TS U5740 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .A1(
n3187), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .B1(n3199), .Y(n4448) );
AOI22X1TS U5741 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .A1(
n4522), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B1(n4523), .Y(n4442) );
AOI22X1TS U5742 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .A1(
n4524), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .B1(n4502), .Y(n4441) );
NAND2X1TS U5743 ( .A(n4442), .B(n4441), .Y(n4576) );
AOI22X1TS U5744 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .A1(
n4511), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .B1(n4502), .Y(n4444) );
AOI22X1TS U5745 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .A1(
n4514), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .B1(n4504), .Y(n4443) );
NAND2X1TS U5746 ( .A(n4444), .B(n4443), .Y(n4575) );
AOI22X1TS U5747 ( .A0(n3182), .A1(n4576), .B0(n4563), .B1(n4575), .Y(n4447)
);
NAND2X1TS U5748 ( .A(n4445), .B(n4534), .Y(n4446) );
AOI22X1TS U5749 ( .A0(n4536), .A1(n4664), .B0(n4663), .B1(n6041), .Y(n5792)
);
AOI22X1TS U5750 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .A1(
n3187), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .B1(n3199), .Y(n4456) );
AOI22X1TS U5751 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .A1(
n3189), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .B1(n3185),
.Y(n4455) );
AOI22X1TS U5752 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[51]), .A1(
n4522), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .B1(n4504), .Y(n4451) );
AOI22X1TS U5753 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .A1(
n4503), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .B1(n4521), .Y(n4450) );
NAND2X1TS U5754 ( .A(n4451), .B(n4450), .Y(n4585) );
AOI22X1TS U5755 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .A1(
n4522), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .B1(n4523), .Y(n4453) );
AOI22X1TS U5756 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .A1(
n4524), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .B1(n4502), .Y(n4452) );
NAND2X1TS U5757 ( .A(n4453), .B(n4452), .Y(n4584) );
AOI22X1TS U5758 ( .A0(n3182), .A1(n4585), .B0(n4563), .B1(n4584), .Y(n4454)
);
NOR2X1TS U5759 ( .A(n5893), .B(n5907), .Y(n4599) );
NAND2X1TS U5760 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]),
.B(n4599), .Y(n4577) );
AOI21X1TS U5761 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .A1(
n4490), .B0(n4459), .Y(n4583) );
AOI22X1TS U5762 ( .A0(n4536), .A1(n4661), .B0(n4660), .B1(n4531), .Y(n5791)
);
AOI22X1TS U5763 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .A1(
n3187), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .B1(n3198), .Y(n4466) );
AOI22X1TS U5764 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .A1(
n3190), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B1(n3186),
.Y(n4465) );
AOI22X1TS U5765 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .A1(
n4503), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .B1(n4521), .Y(n4461) );
AOI22X1TS U5766 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .A1(
n4524), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[52]), .B1(n4479), .Y(n4460) );
NAND2X1TS U5767 ( .A(n4461), .B(n4460), .Y(n4591) );
AOI22X1TS U5768 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .A1(
n4522), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .B1(n4523), .Y(n4463) );
AOI22X1TS U5769 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .A1(
n4524), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B1(n4521), .Y(n4462) );
NAND2X1TS U5770 ( .A(n4463), .B(n4462), .Y(n4590) );
AOI22X1TS U5771 ( .A0(n4568), .A1(n4591), .B0(n4563), .B1(n4590), .Y(n4464)
);
NOR2XLTS U5772 ( .A(n5907), .B(n4467), .Y(n4492) );
AO22XLTS U5773 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .A1(
n4490), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[54]), .B1(n4504), .Y(n4468) );
AOI22X1TS U5774 ( .A0(n4536), .A1(n4657), .B0(n4656), .B1(n6041), .Y(n5786)
);
AOI22X1TS U5775 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .A1(
n3198), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .B1(n3190), .Y(n4475) );
AOI22X1TS U5776 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .A1(
n3188), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .B1(n3185),
.Y(n4474) );
AOI22X1TS U5777 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .A1(
n4512), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .B1(n4511), .Y(n4470) );
AOI22X1TS U5778 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .A1(
n4513), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[53]), .B1(n4479), .Y(n4469) );
NAND2X1TS U5779 ( .A(n4470), .B(n4469), .Y(n4597) );
AOI22X1TS U5780 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .A1(
n4514), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .B1(n4511), .Y(n4472) );
AOI22X1TS U5781 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .A1(
n4512), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .B1(n4502), .Y(n4471) );
NAND2X1TS U5782 ( .A(n4472), .B(n4471), .Y(n4596) );
AOI22X1TS U5783 ( .A0(n3182), .A1(n4597), .B0(n4563), .B1(n4596), .Y(n4473)
);
OAI22X1TS U5784 ( .A0(n5921), .A1(n4477), .B0(n6020), .B1(n4476), .Y(n4478)
);
AOI22X1TS U5785 ( .A0(n4536), .A1(n4655), .B0(n4654), .B1(n6041), .Y(n5795)
);
AOI22X1TS U5786 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .A1(
n3189), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .B1(n3186), .Y(n4486) );
AOI22X1TS U5787 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .A1(
n3188), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .B1(n3199), .Y(n4485) );
AOI22X1TS U5788 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .A1(
n4512), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[54]), .B1(n4479), .Y(n4481) );
AOI22X1TS U5789 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .A1(
n4503), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B1(n4502), .Y(n4480) );
NAND2X1TS U5790 ( .A(n4481), .B(n4480), .Y(n4606) );
AOI22X1TS U5791 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .A1(
n4514), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .B1(n4502), .Y(n4483) );
AOI22X1TS U5792 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .A1(
n4512), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .B1(n4511), .Y(n4482) );
NAND2X1TS U5793 ( .A(n4483), .B(n4482), .Y(n4604) );
AOI22X1TS U5794 ( .A0(n4568), .A1(n4606), .B0(n4563), .B1(n4604), .Y(n4484)
);
AO22XLTS U5795 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .A1(
n4491), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[52]), .B1(n4504), .Y(n4487) );
AOI22X1TS U5796 ( .A0(n4536), .A1(n4653), .B0(n4652), .B1(n4531), .Y(n5794)
);
AOI22X1TS U5797 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .A1(
n3189), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .B1(n3185), .Y(n4496) );
AOI22X1TS U5798 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .A1(
n3187), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .B1(n3198), .Y(n4495) );
AOI22X1TS U5799 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .A1(
n4514), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .B1(n4513), .Y(n4489) );
AOI22X1TS U5800 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .A1(
n4512), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .B1(n4511), .Y(n4488) );
NAND2X1TS U5801 ( .A(n4489), .B(n4488), .Y(n4616) );
AO22XLTS U5802 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .A1(
n4491), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .B1(n4490), .Y(n4493) );
AOI2BB2XLTS U5803 ( .B0(n4543), .B1(n4616), .A0N(n4580), .A1N(n4613), .Y(
n4494) );
AOI22X1TS U5804 ( .A0(n4536), .A1(n4651), .B0(n4650), .B1(n6041), .Y(n5798)
);
AOI22X1TS U5805 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .A1(
n3199), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .B1(n3189), .Y(n4501) );
AOI22X1TS U5806 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .A1(
n3187), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .B1(n3185), .Y(n4500) );
AOI22X1TS U5807 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .A1(
n4512), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .B1(n4502), .Y(n4498) );
AOI22X1TS U5808 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .A1(
n4514), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .B1(n4511), .Y(n4497) );
NAND2X1TS U5809 ( .A(n4498), .B(n4497), .Y(n4600) );
AOI2BB2XLTS U5810 ( .B0(n4543), .B1(n4600), .A0N(n4603), .A1N(n4580), .Y(
n4499) );
INVX2TS U5811 ( .A(n4545), .Y(n4601) );
OAI2BB1X1TS U5812 ( .A0N(n4606), .A1N(n4601), .B0(n3191), .Y(n4648) );
AOI22X1TS U5813 ( .A0(n5895), .A1(n4649), .B0(n4648), .B1(n4639), .Y(n5800)
);
AOI22X1TS U5814 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .A1(
n3198), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .B1(n3186), .Y(n4509) );
AOI22X1TS U5815 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .A1(
n3188), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .B1(n3190), .Y(n4508) );
AOI22X1TS U5816 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .A1(
n4503), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .B1(n4502), .Y(n4506) );
AOI22X1TS U5817 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .A1(
n4514), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .B1(n4504), .Y(n4505) );
NAND2X1TS U5818 ( .A(n4506), .B(n4505), .Y(n4593) );
AOI2BB2XLTS U5819 ( .B0(n4543), .B1(n4593), .A0N(n4595), .A1N(n4580), .Y(
n4507) );
OAI2BB1X1TS U5820 ( .A0N(n4597), .A1N(n4601), .B0(n4530), .Y(n4646) );
AOI22X1TS U5821 ( .A0(n4536), .A1(n4647), .B0(n4646), .B1(n6041), .Y(n5797)
);
AOI22X1TS U5822 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .A1(
n3187), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .B1(n3190), .Y(n4519) );
AOI22X1TS U5823 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .A1(
n3199), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .B1(n3186), .Y(n4518) );
AOI22X1TS U5824 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .A1(
n4512), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .B1(n4511), .Y(n4516) );
AOI22X1TS U5825 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .A1(
n4514), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .B1(n4513), .Y(n4515) );
NAND2X1TS U5826 ( .A(n4516), .B(n4515), .Y(n4587) );
OAI2BB1X1TS U5827 ( .A0N(n4591), .A1N(n4601), .B0(n3191), .Y(n4644) );
AOI22X1TS U5828 ( .A0(n5895), .A1(n4645), .B0(n4644), .B1(n4639), .Y(n5799)
);
AOI22X1TS U5829 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .A1(
n3188), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .B1(n3198), .Y(n4529) );
AOI22X1TS U5830 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .A1(
n3189), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .B1(n3186), .Y(n4528) );
AOI22X1TS U5831 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .A1(
n4522), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .B1(n4521), .Y(n4526) );
AOI22X1TS U5832 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .A1(
n4524), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .B1(n4523), .Y(n4525) );
NAND2X1TS U5833 ( .A(n4526), .B(n4525), .Y(n4581) );
AOI2BB2XLTS U5834 ( .B0(n4543), .B1(n4581), .A0N(n4583), .A1N(n4580), .Y(
n4527) );
OAI2BB1X1TS U5835 ( .A0N(n4585), .A1N(n4601), .B0(n4530), .Y(n4642) );
AOI22X1TS U5836 ( .A0(n5895), .A1(n4643), .B0(n4642), .B1(n4531), .Y(n5803)
);
CLKBUFX2TS U5837 ( .A(n4601), .Y(n4615) );
AOI22X1TS U5838 ( .A0(n4563), .A1(n4572), .B0(n4615), .B1(n4532), .Y(n4533)
);
CLKBUFX2TS U5839 ( .A(n4570), .Y(n4612) );
INVX2TS U5840 ( .A(n4612), .Y(n4607) );
AOI22X1TS U5841 ( .A0(n4607), .A1(n4534), .B0(n4615), .B1(n4576), .Y(n4535)
);
INVX2TS U5842 ( .A(n4599), .Y(n4611) );
NAND2X1TS U5843 ( .A(n4535), .B(n4611), .Y(n4640) );
AOI22X1TS U5844 ( .A0(n4536), .A1(n4641), .B0(n4640), .B1(n6041), .Y(n5796)
);
INVX2TS U5845 ( .A(n4537), .Y(n4567) );
AOI21X1TS U5846 ( .A0(n4567), .A1(n4543), .B0(n4599), .Y(n4538) );
AOI22X1TS U5847 ( .A0(n4615), .A1(n4539), .B0(n4563), .B1(n4564), .Y(n4540)
);
INVX2TS U5848 ( .A(n4639), .Y(n4609) );
INVX2TS U5849 ( .A(n5869), .Y(n4610) );
INVX2TS U5850 ( .A(n4542), .Y(n4559) );
AOI21X1TS U5851 ( .A0(n4559), .A1(n4543), .B0(n4599), .Y(n4544) );
AOI22X1TS U5852 ( .A0(n4607), .A1(n4555), .B0(n4615), .B1(n4546), .Y(n4547)
);
AOI22X1TS U5853 ( .A0(n4607), .A1(n4549), .B0(n4615), .B1(n4552), .Y(n4550)
);
NAND2X1TS U5854 ( .A(n4550), .B(n4611), .Y(n4631) );
CLKBUFX2TS U5855 ( .A(n4601), .Y(n4605) );
AOI22X1TS U5856 ( .A0(n4607), .A1(n4552), .B0(n4605), .B1(n4551), .Y(n4553)
);
AOI22X1TS U5857 ( .A0(n4607), .A1(n4556), .B0(n4605), .B1(n4555), .Y(n4557)
);
NAND2X1TS U5858 ( .A(n4557), .B(n4611), .Y(n4629) );
AOI22X1TS U5859 ( .A0(n3182), .A1(n4559), .B0(n4605), .B1(n4558), .Y(n4560)
);
AOI22X1TS U5860 ( .A0(n4615), .A1(n4564), .B0(n4563), .B1(n4562), .Y(n4565)
);
NAND2X1TS U5861 ( .A(n4565), .B(n4611), .Y(n4627) );
AOI22X1TS U5862 ( .A0(n4568), .A1(n4567), .B0(n4615), .B1(n4566), .Y(n4569)
);
AOI21X1TS U5863 ( .A0(n4605), .A1(n4572), .B0(n4599), .Y(n4573) );
AOI22X1TS U5864 ( .A0(n4607), .A1(n4576), .B0(n4615), .B1(n4575), .Y(n4578)
);
AOI21X1TS U5865 ( .A0(n4605), .A1(n4581), .B0(n4599), .Y(n4582) );
AOI22X1TS U5866 ( .A0(n4607), .A1(n4585), .B0(n4605), .B1(n4584), .Y(n4586)
);
NAND2X1TS U5867 ( .A(n4586), .B(n4611), .Y(n4624) );
AOI21X1TS U5868 ( .A0(n4605), .A1(n4587), .B0(n4599), .Y(n4588) );
AOI22X1TS U5869 ( .A0(n4607), .A1(n4591), .B0(n4615), .B1(n4590), .Y(n4592)
);
NAND2X1TS U5870 ( .A(n4592), .B(n4611), .Y(n4622) );
AOI21X1TS U5871 ( .A0(n4605), .A1(n4593), .B0(n4599), .Y(n4594) );
AOI22X1TS U5872 ( .A0(n4607), .A1(n4597), .B0(n4605), .B1(n4596), .Y(n4598)
);
NAND2X1TS U5873 ( .A(n4598), .B(n4611), .Y(n4620) );
AOI21X1TS U5874 ( .A0(n4601), .A1(n4600), .B0(n4599), .Y(n4602) );
AOI22X1TS U5875 ( .A0(n4607), .A1(n4606), .B0(n4605), .B1(n4604), .Y(n4608)
);
NAND2X1TS U5876 ( .A(n4608), .B(n4611), .Y(n4618) );
AOI21X1TS U5877 ( .A0(n4616), .A1(n4615), .B0(n4614), .Y(n5857) );
INVX2TS U5878 ( .A(n4662), .Y(n4635) );
INVX2TS U5879 ( .A(n4639), .Y(n4636) );
INVX2TS U5880 ( .A(n4662), .Y(n4658) );
INVX2TS U5881 ( .A(n4639), .Y(n4659) );
INVX2TS U5882 ( .A(n4662), .Y(n5772) );
MX2X1TS U5883 ( .A(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .B(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2), .S0(n4680), .Y(n2083) );
INVX2TS U5884 ( .A(n4682), .Y(n4685) );
INVX2TS U5885 ( .A(n4683), .Y(n4684) );
OAI21XLTS U5886 ( .A0(n5160), .A1(n4685), .B0(n4684), .Y(n5138) );
INVX2TS U5887 ( .A(n4686), .Y(n4689) );
INVX2TS U5888 ( .A(n4687), .Y(n4688) );
AOI21X1TS U5889 ( .A0(n5138), .A1(n4689), .B0(n4688), .Y(n4692) );
INVX2TS U5890 ( .A(n4690), .Y(n4710) );
NAND2X1TS U5891 ( .A(n4710), .B(n4708), .Y(n4698) );
INVX2TS U5892 ( .A(n4698), .Y(n4691) );
XOR2XLTS U5893 ( .A(n4692), .B(n4691), .Y(n4701) );
INVX2TS U5894 ( .A(n4694), .Y(n4697) );
INVX2TS U5895 ( .A(n4695), .Y(n4696) );
XNOR2X1TS U5896 ( .A(n4711), .B(n4698), .Y(n4699) );
AOI22X1TS U5897 ( .A0(n4699), .A1(n4864), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n5872), .Y(
n4700) );
OAI2BB1X1TS U5898 ( .A0N(n5215), .A1N(n4701), .B0(n4700), .Y(n2068) );
INVX2TS U5899 ( .A(n4721), .Y(n5068) );
INVX2TS U5900 ( .A(n4704), .Y(n4706) );
NAND2X1TS U5901 ( .A(n4706), .B(n4705), .Y(n4712) );
INVX2TS U5902 ( .A(n4712), .Y(n4707) );
XOR2XLTS U5903 ( .A(n5068), .B(n4707), .Y(n4716) );
CLKBUFX2TS U5904 ( .A(n5036), .Y(n5205) );
INVX2TS U5905 ( .A(n4708), .Y(n4709) );
AOI21X1TS U5906 ( .A0(n4711), .A1(n4710), .B0(n4709), .Y(n4713) );
AOI22X1TS U5907 ( .A0(n5205), .A1(n4714), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n5872), .Y(
n4715) );
OAI2BB1X1TS U5908 ( .A0N(n5219), .A1N(n4716), .B0(n4715), .Y(n2067) );
INVX2TS U5909 ( .A(n4717), .Y(n4720) );
INVX2TS U5910 ( .A(n4718), .Y(n4719) );
AOI21X1TS U5911 ( .A0(n4721), .A1(n4720), .B0(n4719), .Y(n4724) );
INVX2TS U5912 ( .A(n4722), .Y(n5090) );
NAND2X1TS U5913 ( .A(n5090), .B(n5088), .Y(n4727) );
INVX2TS U5914 ( .A(n4727), .Y(n4723) );
XOR2XLTS U5915 ( .A(n4724), .B(n4723), .Y(n4730) );
INVX2TS U5916 ( .A(n5091), .Y(n4735) );
AOI22X1TS U5917 ( .A0(n5205), .A1(n4728), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .B1(n5872), .Y(
n4729) );
OAI2BB1X1TS U5918 ( .A0N(n5219), .A1N(n4730), .B0(n4729), .Y(n2066) );
INVX2TS U5919 ( .A(n4732), .Y(n4733) );
INVX2TS U5920 ( .A(n4736), .Y(n5074) );
INVX2TS U5921 ( .A(n5073), .Y(n4737) );
AOI21X1TS U5922 ( .A0(n5078), .A1(n5074), .B0(n4737), .Y(n4741) );
INVX2TS U5923 ( .A(n4738), .Y(n4740) );
NAND2X1TS U5924 ( .A(n4740), .B(n4739), .Y(n4743) );
XOR2XLTS U5925 ( .A(n4741), .B(n4743), .Y(n4747) );
CLKINVX1TS U5926 ( .A(n4742), .Y(n5054) );
INVX2TS U5927 ( .A(n4743), .Y(n4744) );
XNOR2X1TS U5928 ( .A(n5054), .B(n4744), .Y(n4745) );
AOI22X1TS U5929 ( .A0(n4745), .A1(n5215), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .B1(n5872), .Y(
n4746) );
OAI2BB1X1TS U5930 ( .A0N(n5036), .A1N(n4747), .B0(n4746), .Y(n2063) );
CLKBUFX2TS U5931 ( .A(n5219), .Y(n4868) );
INVX2TS U5932 ( .A(n4748), .Y(n4751) );
INVX2TS U5933 ( .A(n4749), .Y(n4750) );
AOI21X1TS U5934 ( .A0(n5054), .A1(n4751), .B0(n4750), .Y(n4782) );
INVX2TS U5935 ( .A(n4782), .Y(n4766) );
INVX2TS U5936 ( .A(n4752), .Y(n4754) );
NAND2X1TS U5937 ( .A(n4754), .B(n4753), .Y(n4759) );
INVX2TS U5938 ( .A(n4759), .Y(n4755) );
XNOR2X1TS U5939 ( .A(n4766), .B(n4755), .Y(n4763) );
AOI21X1TS U5940 ( .A0(n5060), .A1(n4758), .B0(n4757), .Y(n4815) );
XNOR2X1TS U5941 ( .A(n4760), .B(n4759), .Y(n4761) );
AOI22X1TS U5942 ( .A0(n4761), .A1(n4864), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n5872), .Y(
n4762) );
OAI2BB1X1TS U5943 ( .A0N(n4868), .A1N(n4763), .B0(n4762), .Y(n2059) );
AOI21X1TS U5944 ( .A0(n4766), .A1(n4765), .B0(n4764), .Y(n5039) );
INVX2TS U5945 ( .A(n4767), .Y(n4769) );
NAND2X1TS U5946 ( .A(n4769), .B(n4768), .Y(n4775) );
INVX2TS U5947 ( .A(n4775), .Y(n4770) );
XOR2XLTS U5948 ( .A(n5039), .B(n4770), .Y(n4779) );
AOI21X1TS U5949 ( .A0(n5060), .A1(n4774), .B0(n4773), .Y(n4788) );
XNOR2X1TS U5950 ( .A(n4776), .B(n4775), .Y(n4777) );
AOI22X1TS U5951 ( .A0(n4777), .A1(n4864), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B1(n5872), .Y(
n4778) );
OAI2BB1X1TS U5952 ( .A0N(n5219), .A1N(n4779), .B0(n4778), .Y(n2057) );
OAI21XLTS U5953 ( .A0(n4782), .A1(n4781), .B0(n4780), .Y(n4787) );
INVX2TS U5954 ( .A(n4783), .Y(n4785) );
NAND2X1TS U5955 ( .A(n4785), .B(n4784), .Y(n4789) );
INVX2TS U5956 ( .A(n4789), .Y(n4786) );
XNOR2X1TS U5957 ( .A(n4787), .B(n4786), .Y(n4792) );
INVX2TS U5958 ( .A(n4788), .Y(n5025) );
XNOR2X1TS U5959 ( .A(n5025), .B(n4789), .Y(n4790) );
CLKBUFX2TS U5960 ( .A(n5036), .Y(n4918) );
AOI22X1TS U5961 ( .A0(n4790), .A1(n4918), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B1(n4856), .Y(
n4791) );
OAI2BB1X1TS U5962 ( .A0N(n4868), .A1N(n4792), .B0(n4791), .Y(n2058) );
AOI21X1TS U5963 ( .A0(n5054), .A1(n4794), .B0(n4793), .Y(n4808) );
INVX2TS U5964 ( .A(n4795), .Y(n4797) );
NAND2X1TS U5965 ( .A(n4797), .B(n4796), .Y(n4801) );
INVX2TS U5966 ( .A(n4801), .Y(n4798) );
XOR2XLTS U5967 ( .A(n4808), .B(n4798), .Y(n4805) );
INVX2TS U5968 ( .A(n4799), .Y(n5056) );
INVX2TS U5969 ( .A(n5055), .Y(n4800) );
AOI21X1TS U5970 ( .A0(n5060), .A1(n5056), .B0(n4800), .Y(n4802) );
AOI22X1TS U5971 ( .A0(n5205), .A1(n4803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n4856), .Y(
n4804) );
OAI2BB1X1TS U5972 ( .A0N(n4868), .A1N(n4805), .B0(n4804), .Y(n2061) );
INVX2TS U5973 ( .A(n4809), .Y(n4811) );
NAND2X1TS U5974 ( .A(n4811), .B(n4810), .Y(n4814) );
INVX2TS U5975 ( .A(n4814), .Y(n4812) );
XNOR2X1TS U5976 ( .A(n4813), .B(n4812), .Y(n4818) );
AOI22X1TS U5977 ( .A0(n5205), .A1(n4816), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B1(n4856), .Y(
n4817) );
OAI2BB1X1TS U5978 ( .A0N(n4868), .A1N(n4818), .B0(n4817), .Y(n2060) );
AOI22X1TS U5979 ( .A0(n4821), .A1(n4864), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45]), .B1(n4856), .Y(
n4822) );
OAI2BB1X1TS U5980 ( .A0N(n4868), .A1N(n4823), .B0(n4822), .Y(n2035) );
AFHCONX2TS U5981 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]), .B(n6140),
.CI(n4824), .CON(n4876), .S(n4829) );
AOI22X1TS U5982 ( .A0(n4827), .A1(n4864), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[46]), .B1(n4856), .Y(
n4828) );
OAI2BB1X1TS U5983 ( .A0N(n4868), .A1N(n4829), .B0(n4828), .Y(n2034) );
AFHCONX2TS U5984 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]), .B(n6141),
.CI(n4830), .CON(n4819), .S(n4835) );
AOI22X1TS U5985 ( .A0(n4833), .A1(n4864), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[44]), .B1(n4856), .Y(
n4834) );
OAI2BB1X1TS U5986 ( .A0N(n4868), .A1N(n4835), .B0(n4834), .Y(n2036) );
AFHCINX2TS U5987 ( .CIN(n4837), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[49]),
.A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[51]), .S(n4838), .CO(
n4848) );
AOI22X1TS U5988 ( .A0(n4838), .A1(n4864), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[51]), .B1(n4856), .Y(
n4839) );
OAI2BB1X1TS U5989 ( .A0N(n4868), .A1N(n4840), .B0(n4839), .Y(n2029) );
XNOR2X1TS U5990 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[51]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[53]), .Y(n4841) );
XNOR2X1TS U5991 ( .A(n4842), .B(n4841), .Y(n4846) );
AFHCINX2TS U5992 ( .CIN(n4843), .B(n6124), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[51]), .S(n4844), .CO(n3307) );
CLKBUFX2TS U5993 ( .A(n5773), .Y(n4911) );
AOI22X1TS U5994 ( .A0(n4844), .A1(n5215), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[53]), .B1(n4911), .Y(
n4845) );
OAI2BB1X1TS U5995 ( .A0N(n5036), .A1N(n4846), .B0(n4845), .Y(n2027) );
AOI22X1TS U5996 ( .A0(n4851), .A1(n5215), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[52]), .B1(n4856), .Y(
n4852) );
OAI2BB1X1TS U5997 ( .A0N(n5036), .A1N(n4853), .B0(n4852), .Y(n2028) );
AOI22X1TS U5998 ( .A0(n4857), .A1(n4864), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[49]), .B1(n4856), .Y(
n4858) );
OAI2BB1X1TS U5999 ( .A0N(n4868), .A1N(n4859), .B0(n4858), .Y(n2031) );
AOI22X1TS U6000 ( .A0(n4865), .A1(n4864), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[48]), .B1(n4911), .Y(
n4866) );
OAI2BB1X1TS U6001 ( .A0N(n4868), .A1N(n4867), .B0(n4866), .Y(n2032) );
CLKBUFX2TS U6002 ( .A(n5219), .Y(n4927) );
XNOR2X1TS U6003 ( .A(n6138), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]),
.Y(n4869) );
AOI22X1TS U6004 ( .A0(n4873), .A1(n4918), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]), .B1(n4911), .Y(
n4874) );
OAI2BB1X1TS U6005 ( .A0N(n4927), .A1N(n4875), .B0(n4874), .Y(n2030) );
AOI22X1TS U6006 ( .A0(n4878), .A1(n4918), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]), .B1(n4911), .Y(
n4879) );
OAI2BB1X1TS U6007 ( .A0N(n4927), .A1N(n4880), .B0(n4879), .Y(n2033) );
AOI22X1TS U6008 ( .A0(n4883), .A1(n4918), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]), .B1(n4911), .Y(
n4884) );
OAI2BB1X1TS U6009 ( .A0N(n4927), .A1N(n4885), .B0(n4884), .Y(n2037) );
AOI22X1TS U6010 ( .A0(n4888), .A1(n4918), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[39]), .B1(n4911), .Y(
n4889) );
OAI2BB1X1TS U6011 ( .A0N(n4927), .A1N(n4890), .B0(n4889), .Y(n2041) );
XOR2XLTS U6012 ( .A(n6143), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]), .Y(
n4891) );
AFHCONX2TS U6013 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[40]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]), .CI(n4893), .CON(n4904), .S(
n4894) );
AOI22X1TS U6014 ( .A0(n4894), .A1(n4918), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40]), .B1(n4911), .Y(
n4895) );
OAI2BB1X1TS U6015 ( .A0N(n4927), .A1N(n4896), .B0(n4895), .Y(n2040) );
AFHCONX2TS U6016 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[40]), .B(n6142),
.CI(n4897), .CON(n4881), .S(n4901) );
AFHCONX2TS U6017 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[42]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[40]), .CI(n4898), .CON(n4882), .S(
n4899) );
AOI22X1TS U6018 ( .A0(n4899), .A1(n4918), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[42]), .B1(n4911), .Y(
n4900) );
OAI2BB1X1TS U6019 ( .A0N(n4927), .A1N(n4901), .B0(n4900), .Y(n2038) );
AFHCINX2TS U6020 ( .CIN(n4902), .B(n6150), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[39]), .S(n4907), .CO(n4897) );
XNOR2X1TS U6021 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[41]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[39]), .Y(n4903) );
AOI22X1TS U6022 ( .A0(n4905), .A1(n4918), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[41]), .B1(n4911), .Y(
n4906) );
OAI2BB1X1TS U6023 ( .A0N(n4927), .A1N(n4907), .B0(n4906), .Y(n2039) );
XNOR2X1TS U6024 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[37]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[35]), .Y(n4909) );
AOI22X1TS U6025 ( .A0(n4912), .A1(n4918), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[37]), .B1(n4911), .Y(
n4913) );
OAI2BB1X1TS U6026 ( .A0N(n4927), .A1N(n4914), .B0(n4913), .Y(n2043) );
XOR2XLTS U6027 ( .A(n6144), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]), .Y(
n4915) );
AFHCONX2TS U6028 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[38]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]), .CI(n4917), .CON(n4887), .S(
n4919) );
AOI22X1TS U6029 ( .A0(n4919), .A1(n4918), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[38]), .B1(n6042), .Y(
n4920) );
OAI2BB1X1TS U6030 ( .A0N(n4927), .A1N(n4921), .B0(n4920), .Y(n2042) );
AFHCINX2TS U6031 ( .CIN(n4923), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[33]),
.A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[35]), .S(n4924), .CO(
n4930) );
CLKBUFX2TS U6032 ( .A(n5036), .Y(n5217) );
AOI22X1TS U6033 ( .A0(n4924), .A1(n5217), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[35]), .B1(n6042), .Y(
n4925) );
OAI2BB1X1TS U6034 ( .A0N(n4927), .A1N(n4926), .B0(n4925), .Y(n2045) );
CLKBUFX2TS U6035 ( .A(n5219), .Y(n5082) );
AFHCONX2TS U6036 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]), .B(n6152),
.CI(n4928), .CON(n4908), .S(n4933) );
AOI22X1TS U6037 ( .A0(n4931), .A1(n5217), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[36]), .B1(n6042), .Y(
n4932) );
OAI2BB1X1TS U6038 ( .A0N(n5082), .A1N(n4933), .B0(n4932), .Y(n2044) );
XOR2XLTS U6039 ( .A(n6153), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]), .Y(
n4934) );
AOI22X1TS U6040 ( .A0(n4938), .A1(n5217), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]), .B1(n6042), .Y(
n4939) );
OAI2BB1X1TS U6041 ( .A0N(n5082), .A1N(n4940), .B0(n4939), .Y(n2046) );
AOI22X1TS U6042 ( .A0(n4943), .A1(n5217), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .B1(n6042), .Y(
n4944) );
OAI2BB1X1TS U6043 ( .A0N(n5082), .A1N(n4945), .B0(n4944), .Y(n2047) );
AFHCONX2TS U6044 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .B(n6154),
.CI(n4946), .CON(n4941), .S(n4950) );
AFHCONX2TS U6045 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[32]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .CI(n4947), .CON(n4942), .S(
n4948) );
AOI22X1TS U6046 ( .A0(n4948), .A1(n5217), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[32]), .B1(n6042), .Y(
n4949) );
OAI2BB1X1TS U6047 ( .A0N(n5082), .A1N(n4950), .B0(n4949), .Y(n2048) );
AFHCINX2TS U6048 ( .CIN(n4951), .B(n6159), .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .S(n4955), .CO(n4946) );
AOI22X1TS U6049 ( .A0(n4953), .A1(n5217), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[31]), .B1(n6042), .Y(
n4954) );
OAI2BB1X1TS U6050 ( .A0N(n5082), .A1N(n4955), .B0(n4954), .Y(n2049) );
AFHCONX2TS U6051 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .B(n6155),
.CI(n4956), .CON(n4951), .S(n4961) );
XOR2XLTS U6052 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[30]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .Y(n4957) );
AOI22X1TS U6053 ( .A0(n4959), .A1(n5217), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]), .B1(n6042), .Y(
n4960) );
OAI2BB1X1TS U6054 ( .A0N(n5082), .A1N(n4961), .B0(n4960), .Y(n2050) );
AOI21X1TS U6055 ( .A0(n5054), .A1(n4963), .B0(n4962), .Y(n5012) );
INVX2TS U6056 ( .A(n5012), .Y(n5032) );
INVX2TS U6057 ( .A(n4965), .Y(n4966) );
AOI21X1TS U6058 ( .A0(n5032), .A1(n4967), .B0(n4966), .Y(n4972) );
NAND2X1TS U6059 ( .A(n4970), .B(n4969), .Y(n4979) );
INVX2TS U6060 ( .A(n4979), .Y(n4971) );
XOR2XLTS U6061 ( .A(n4972), .B(n4971), .Y(n4983) );
CLKBUFX2TS U6062 ( .A(n5036), .Y(n5211) );
AOI21X1TS U6063 ( .A0(n5060), .A1(n4974), .B0(n4973), .Y(n5004) );
INVX2TS U6064 ( .A(n5004), .Y(n5019) );
AOI21X1TS U6065 ( .A0(n5019), .A1(n4978), .B0(n4977), .Y(n4980) );
AOI22X1TS U6066 ( .A0(n5211), .A1(n4981), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]), .B1(n5773), .Y(
n4982) );
OAI2BB1X1TS U6067 ( .A0N(n5082), .A1N(n4983), .B0(n4982), .Y(n2051) );
AOI21X1TS U6068 ( .A0(n5032), .A1(n4985), .B0(n4984), .Y(n5003) );
NAND2X1TS U6069 ( .A(n4989), .B(n4988), .Y(n4994) );
INVX2TS U6070 ( .A(n4994), .Y(n4990) );
XNOR2X1TS U6071 ( .A(n4991), .B(n4990), .Y(n4998) );
AOI21X1TS U6072 ( .A0(n5019), .A1(n4993), .B0(n4992), .Y(n4995) );
AOI22X1TS U6073 ( .A0(n5211), .A1(n4996), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]), .B1(n5773), .Y(
n4997) );
OAI2BB1X1TS U6074 ( .A0N(n5082), .A1N(n4998), .B0(n4997), .Y(n2052) );
NAND2X1TS U6075 ( .A(n5001), .B(n5000), .Y(n5005) );
INVX2TS U6076 ( .A(n5005), .Y(n5002) );
XOR2XLTS U6077 ( .A(n5003), .B(n5002), .Y(n5009) );
XNOR2X1TS U6078 ( .A(n5006), .B(n5005), .Y(n5007) );
CLKBUFX2TS U6079 ( .A(n5773), .Y(n5130) );
AOI22X1TS U6080 ( .A0(n5007), .A1(n5217), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[27]), .B1(n5130), .Y(
n5008) );
OAI2BB1X1TS U6081 ( .A0N(n5082), .A1N(n5009), .B0(n5008), .Y(n2053) );
CLKBUFX2TS U6082 ( .A(n5219), .Y(n5183) );
OAI21XLTS U6083 ( .A0(n5012), .A1(n5011), .B0(n5010), .Y(n5017) );
INVX2TS U6084 ( .A(n5013), .Y(n5015) );
NAND2X1TS U6085 ( .A(n5015), .B(n5014), .Y(n5018) );
INVX2TS U6086 ( .A(n5018), .Y(n5016) );
XNOR2X1TS U6087 ( .A(n5017), .B(n5016), .Y(n5022) );
XNOR2X1TS U6088 ( .A(n5019), .B(n5018), .Y(n5020) );
AOI22X1TS U6089 ( .A0(n5020), .A1(n5211), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[26]), .B1(n5130), .Y(
n5021) );
OAI2BB1X1TS U6090 ( .A0N(n5183), .A1N(n5022), .B0(n5021), .Y(n2054) );
AOI21X1TS U6091 ( .A0(n5025), .A1(n5024), .B0(n5023), .Y(n5046) );
INVX2TS U6092 ( .A(n5026), .Y(n5028) );
NAND2X1TS U6093 ( .A(n5028), .B(n5027), .Y(n5030) );
XNOR2X1TS U6094 ( .A(n5029), .B(n5030), .Y(n5035) );
INVX2TS U6095 ( .A(n5030), .Y(n5031) );
XNOR2X1TS U6096 ( .A(n5032), .B(n5031), .Y(n5033) );
AOI22X1TS U6097 ( .A0(n5033), .A1(n5215), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n5130), .Y(
n5034) );
OAI2BB1X1TS U6098 ( .A0N(n5036), .A1N(n5035), .B0(n5034), .Y(n2055) );
INVX2TS U6099 ( .A(n5040), .Y(n5042) );
NAND2X1TS U6100 ( .A(n5042), .B(n5041), .Y(n5045) );
INVX2TS U6101 ( .A(n5045), .Y(n5043) );
XNOR2X1TS U6102 ( .A(n5044), .B(n5043), .Y(n5049) );
AOI22X1TS U6103 ( .A0(n5205), .A1(n5047), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .B1(n5130), .Y(
n5048) );
OAI2BB1X1TS U6104 ( .A0N(n5183), .A1N(n5049), .B0(n5048), .Y(n2056) );
INVX2TS U6105 ( .A(n5050), .Y(n5053) );
INVX2TS U6106 ( .A(n5051), .Y(n5052) );
AOI21X1TS U6107 ( .A0(n5054), .A1(n5053), .B0(n5052), .Y(n5058) );
NAND2X1TS U6108 ( .A(n5056), .B(n5055), .Y(n5059) );
INVX2TS U6109 ( .A(n5059), .Y(n5057) );
XOR2XLTS U6110 ( .A(n5058), .B(n5057), .Y(n5063) );
XNOR2X1TS U6111 ( .A(n5060), .B(n5059), .Y(n5061) );
AOI22X1TS U6112 ( .A0(n5061), .A1(n5211), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .B1(n5130), .Y(
n5062) );
OAI2BB1X1TS U6113 ( .A0N(n5183), .A1N(n5063), .B0(n5062), .Y(n2062) );
INVX2TS U6114 ( .A(n5064), .Y(n5067) );
INVX2TS U6115 ( .A(n5065), .Y(n5066) );
INVX2TS U6116 ( .A(n5069), .Y(n5072) );
INVX2TS U6117 ( .A(n5070), .Y(n5071) );
AOI21X1TS U6118 ( .A0(n5087), .A1(n5072), .B0(n5071), .Y(n5076) );
NAND2X1TS U6119 ( .A(n5074), .B(n5073), .Y(n5077) );
INVX2TS U6120 ( .A(n5077), .Y(n5075) );
XOR2XLTS U6121 ( .A(n5076), .B(n5075), .Y(n5081) );
XNOR2X1TS U6122 ( .A(n5078), .B(n5077), .Y(n5079) );
AOI22X1TS U6123 ( .A0(n5079), .A1(n5211), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .B1(n5130), .Y(
n5080) );
OAI2BB1X1TS U6124 ( .A0N(n5082), .A1N(n5081), .B0(n5080), .Y(n2064) );
INVX2TS U6125 ( .A(n5083), .Y(n5085) );
NAND2X1TS U6126 ( .A(n5085), .B(n5084), .Y(n5092) );
INVX2TS U6127 ( .A(n5092), .Y(n5086) );
XNOR2X1TS U6128 ( .A(n5087), .B(n5086), .Y(n5096) );
INVX2TS U6129 ( .A(n5088), .Y(n5089) );
AOI21X1TS U6130 ( .A0(n5091), .A1(n5090), .B0(n5089), .Y(n5093) );
AOI22X1TS U6131 ( .A0(n5211), .A1(n5094), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B1(n5130), .Y(
n5095) );
OAI2BB1X1TS U6132 ( .A0N(n5183), .A1N(n5096), .B0(n5095), .Y(n2065) );
INVX2TS U6133 ( .A(n5097), .Y(n5202) );
OAI21XLTS U6134 ( .A0(n5202), .A1(n5099), .B0(n5098), .Y(n5102) );
INVX2TS U6135 ( .A(n5114), .Y(n5100) );
NAND2X1TS U6136 ( .A(n5100), .B(n5113), .Y(n5104) );
INVX2TS U6137 ( .A(n5104), .Y(n5101) );
XNOR2X1TS U6138 ( .A(n5102), .B(n5101), .Y(n5107) );
INVX2TS U6139 ( .A(n5103), .Y(n5115) );
XOR2XLTS U6140 ( .A(n5115), .B(n5104), .Y(n5105) );
AOI22X1TS U6141 ( .A0(n5205), .A1(n5105), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .B1(n5130), .Y(n5106) );
OAI2BB1X1TS U6142 ( .A0N(n5183), .A1N(n5107), .B0(n5106), .Y(n2076) );
INVX2TS U6143 ( .A(n5108), .Y(n5170) );
INVX2TS U6144 ( .A(n5109), .Y(n5111) );
NAND2X1TS U6145 ( .A(n5111), .B(n5110), .Y(n5116) );
INVX2TS U6146 ( .A(n5116), .Y(n5112) );
XNOR2X1TS U6147 ( .A(n5170), .B(n5112), .Y(n5120) );
XNOR2X1TS U6148 ( .A(n5117), .B(n5116), .Y(n5118) );
AOI22X1TS U6149 ( .A0(n5118), .A1(n5217), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .B1(n5130), .Y(n5119) );
OAI2BB1X1TS U6150 ( .A0N(n5183), .A1N(n5120), .B0(n5119), .Y(n2075) );
INVX2TS U6151 ( .A(n5121), .Y(n5124) );
INVX2TS U6152 ( .A(n5122), .Y(n5123) );
AOI21X1TS U6153 ( .A0(n5170), .A1(n5124), .B0(n5123), .Y(n5127) );
INVX2TS U6154 ( .A(n5125), .Y(n5191) );
NAND2X1TS U6155 ( .A(n5191), .B(n5189), .Y(n5129) );
INVX2TS U6156 ( .A(n5129), .Y(n5126) );
XOR2XLTS U6157 ( .A(n5127), .B(n5126), .Y(n5133) );
XNOR2X1TS U6158 ( .A(n5192), .B(n5129), .Y(n5131) );
AOI22X1TS U6159 ( .A0(n5131), .A1(n5211), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n5130), .Y(n5132) );
OAI2BB1X1TS U6160 ( .A0N(n5183), .A1N(n5133), .B0(n5132), .Y(n2074) );
INVX2TS U6161 ( .A(n5134), .Y(n5136) );
NAND2X1TS U6162 ( .A(n5136), .B(n5135), .Y(n5139) );
INVX2TS U6163 ( .A(n5139), .Y(n5137) );
XNOR2X1TS U6164 ( .A(n5138), .B(n5137), .Y(n5143) );
OAI21XLTS U6165 ( .A0(n5152), .A1(n5146), .B0(n5147), .Y(n5140) );
XNOR2X1TS U6166 ( .A(n5140), .B(n5139), .Y(n5141) );
AOI22X1TS U6167 ( .A0(n5141), .A1(n5211), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n5216), .Y(
n5142) );
OAI2BB1X1TS U6168 ( .A0N(n5183), .A1N(n5143), .B0(n5142), .Y(n2069) );
INVX2TS U6169 ( .A(n5146), .Y(n5148) );
NAND2X1TS U6170 ( .A(n5148), .B(n5147), .Y(n5151) );
INVX2TS U6171 ( .A(n5151), .Y(n5149) );
XNOR2X1TS U6172 ( .A(n5150), .B(n5149), .Y(n5155) );
XOR2XLTS U6173 ( .A(n5152), .B(n5151), .Y(n5153) );
AOI22X1TS U6174 ( .A0(n5205), .A1(n5153), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n5216), .Y(
n5154) );
OAI2BB1X1TS U6175 ( .A0N(n5183), .A1N(n5155), .B0(n5154), .Y(n2070) );
INVX2TS U6176 ( .A(n5156), .Y(n5158) );
NAND2X1TS U6177 ( .A(n5158), .B(n5157), .Y(n5163) );
INVX2TS U6178 ( .A(n5163), .Y(n5159) );
XOR2XLTS U6179 ( .A(n5160), .B(n5159), .Y(n5167) );
AOI21X1TS U6180 ( .A0(n5192), .A1(n5162), .B0(n5161), .Y(n5179) );
XNOR2X1TS U6181 ( .A(n5164), .B(n5163), .Y(n5165) );
AOI22X1TS U6182 ( .A0(n5165), .A1(n5211), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n5216), .Y(n5166) );
OAI2BB1X1TS U6183 ( .A0N(n5215), .A1N(n5167), .B0(n5166), .Y(n2071) );
AOI21X1TS U6184 ( .A0(n5170), .A1(n5169), .B0(n5168), .Y(n5188) );
OAI21XLTS U6185 ( .A0(n5188), .A1(n5172), .B0(n5171), .Y(n5177) );
INVX2TS U6186 ( .A(n5173), .Y(n5175) );
NAND2X1TS U6187 ( .A(n5175), .B(n5174), .Y(n5178) );
INVX2TS U6188 ( .A(n5178), .Y(n5176) );
XNOR2X1TS U6189 ( .A(n5177), .B(n5176), .Y(n5182) );
XOR2XLTS U6190 ( .A(n5179), .B(n5178), .Y(n5180) );
AOI22X1TS U6191 ( .A0(n5205), .A1(n5180), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n5216), .Y(n5181) );
OAI2BB1X1TS U6192 ( .A0N(n5183), .A1N(n5182), .B0(n5181), .Y(n2072) );
INVX2TS U6193 ( .A(n5184), .Y(n5186) );
NAND2X1TS U6194 ( .A(n5186), .B(n5185), .Y(n5193) );
INVX2TS U6195 ( .A(n5193), .Y(n5187) );
XOR2XLTS U6196 ( .A(n5188), .B(n5187), .Y(n5197) );
INVX2TS U6197 ( .A(n5189), .Y(n5190) );
AOI21X1TS U6198 ( .A0(n5192), .A1(n5191), .B0(n5190), .Y(n5194) );
XOR2XLTS U6199 ( .A(n5194), .B(n5193), .Y(n5195) );
AOI22X1TS U6200 ( .A0(n5205), .A1(n5195), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(n5216), .Y(n5196) );
OAI2BB1X1TS U6201 ( .A0N(n5215), .A1N(n5197), .B0(n5196), .Y(n2073) );
INVX2TS U6202 ( .A(n5198), .Y(n5200) );
NAND2X1TS U6203 ( .A(n5200), .B(n5199), .Y(n5203) );
INVX2TS U6204 ( .A(n5203), .Y(n5201) );
XOR2XLTS U6205 ( .A(n5202), .B(n5201), .Y(n5207) );
XOR2XLTS U6206 ( .A(n5203), .B(n5208), .Y(n5204) );
AOI22X1TS U6207 ( .A0(n5205), .A1(n5204), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B1(n5216), .Y(n5206) );
OAI2BB1X1TS U6208 ( .A0N(n5215), .A1N(n5207), .B0(n5206), .Y(n2077) );
OR2X1TS U6209 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n5209) );
CLKAND2X2TS U6210 ( .A(n5209), .B(n5208), .Y(n5212) );
XOR2XLTS U6211 ( .A(n5212), .B(n5210), .Y(n5214) );
AOI22X1TS U6212 ( .A0(n5212), .A1(n5211), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n5216), .Y(n5213) );
OAI2BB1X1TS U6213 ( .A0N(n5215), .A1N(n5214), .B0(n5213), .Y(n2078) );
XNOR2X1TS U6214 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .B(
n6165), .Y(n5220) );
AOI22X1TS U6215 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .A1(
n5217), .B0(n5216), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n5218) );
OAI2BB1X1TS U6216 ( .A0N(n5220), .A1N(n5219), .B0(n5218), .Y(n2079) );
MX2X1TS U6217 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[0]), .S0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n2080) );
MX2X1TS U6218 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[10]), .S0(n5221), .Y(n2192)
);
MX2X1TS U6219 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[9]), .S0(n5222), .Y(n2197)
);
MX2X1TS U6220 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[8]), .S0(n5221), .Y(n2202)
);
MX2X1TS U6221 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n5222), .Y(n2207)
);
MX2X1TS U6222 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n5222), .Y(n2212)
);
MX2X1TS U6223 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]), .S0(n5222), .Y(n2217)
);
MX2X1TS U6224 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n5221), .Y(n2222)
);
MX2X1TS U6225 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]), .S0(n5222), .Y(n2227)
);
MX2X1TS U6226 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n5222), .Y(n2232)
);
MX2X1TS U6227 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n5222), .Y(n2237)
);
MX2X1TS U6228 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n5222), .Y(n2242)
);
INVX2TS U6229 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(
n5243) );
CLKBUFX2TS U6230 ( .A(n5846), .Y(n5875) );
INVX2TS U6231 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
n5239) );
INVX2TS U6232 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
n5240) );
INVX2TS U6233 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(
n5230) );
INVX2TS U6234 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(
n5242) );
INVX2TS U6235 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(
n5232) );
AOI22X1TS U6236 ( .A0(n5241), .A1(n5239), .B0(n5875), .B1(n6160), .Y(n2268)
);
NAND2X1TS U6237 ( .A(n5828), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n5778) );
OA22X1TS U6238 ( .A0(n5778), .A1(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(
result_add_subt[53]), .Y(n2267) );
AOI22X1TS U6239 ( .A0(n5241), .A1(n5240), .B0(n5875), .B1(n6161), .Y(n2266)
);
OA22X1TS U6240 ( .A0(n5778), .A1(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(
result_add_subt[55]), .Y(n2265) );
OA22X1TS U6241 ( .A0(n5778), .A1(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(
result_add_subt[56]), .Y(n2264) );
OA22X1TS U6242 ( .A0(n5778), .A1(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(
result_add_subt[57]), .Y(n2263) );
CLKBUFX2TS U6243 ( .A(n5241), .Y(n5245) );
AOI22X1TS U6244 ( .A0(n5245), .A1(n5242), .B0(n5875), .B1(n6162), .Y(n2262)
);
AOI22X1TS U6245 ( .A0(n5245), .A1(n5243), .B0(n5875), .B1(n6163), .Y(n2261)
);
OA22X1TS U6246 ( .A0(n5778), .A1(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[8]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(
result_add_subt[60]), .Y(n2260) );
AOI22X1TS U6247 ( .A0(n5245), .A1(n5244), .B0(n5875), .B1(n6164), .Y(n2259)
);
CLKBUFX2TS U6248 ( .A(n5246), .Y(n6250) );
CLKBUFX2TS U6249 ( .A(n5246), .Y(n6251) );
CLKBUFX2TS U6250 ( .A(n5246), .Y(n6264) );
CLKBUFX2TS U6251 ( .A(n5246), .Y(n6300) );
CLKBUFX2TS U6252 ( .A(n5246), .Y(n6303) );
CLKBUFX2TS U6253 ( .A(n5246), .Y(n6309) );
CLKBUFX2TS U6254 ( .A(n5246), .Y(n6312) );
NOR2BX1TS U6255 ( .AN(n5247), .B(n5256), .Y(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
NOR2BX1TS U6256 ( .AN(beg_fsm_cordic), .B(n5248), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
INVX2TS U6257 ( .A(n5295), .Y(n5547) );
AO21XLTS U6258 ( .A0(n5249), .A1(n5250), .B0(n5547), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
CLKBUFX2TS U6259 ( .A(n5336), .Y(n5576) );
OAI2BB2XLTS U6260 ( .B0(n5251), .B1(n5250), .A0N(n5252), .A1N(n5576), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U6261 ( .AN(n5252), .B(n5576), .Y(inst_CORDIC_FSM_v3_state_next[6]) );
NAND2BXLTS U6262 ( .AN(n5254), .B(n5253), .Y(n3173) );
AO21XLTS U6263 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .A1(
n5256), .B0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .Y(
n3171) );
INVX2TS U6264 ( .A(n5256), .Y(n5257) );
CLKBUFX2TS U6265 ( .A(n6035), .Y(n5886) );
AOI22X1TS U6266 ( .A0(n5257), .A1(n5255), .B0(n5886), .B1(n5256), .Y(n3170)
);
AOI22X1TS U6267 ( .A0(n5257), .A1(n5886), .B0(n5770), .B1(n5256), .Y(n3169)
);
AO22XLTS U6268 ( .A0(n5257), .A1(busy), .B0(n5256), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n3168) );
AOI22X1TS U6269 ( .A0(n5257), .A1(n5872), .B0(n5873), .B1(n5256), .Y(n3166)
);
AOI22X1TS U6270 ( .A0(n5257), .A1(n5906), .B0(n5875), .B1(n5256), .Y(n3165)
);
OA21XLTS U6271 ( .A0(n5258), .A1(n3196), .B0(n5259), .Y(n3164) );
AOI21X1TS U6272 ( .A0(n5899), .A1(n5259), .B0(n5260), .Y(n3163) );
AOI2BB2XLTS U6273 ( .B0(n5260), .B1(cont_iter_out[2]), .A0N(cont_iter_out[2]), .A1N(n5260), .Y(n3162) );
XNOR2X1TS U6274 ( .A(cont_var_out[0]), .B(n5261), .Y(n3160) );
AOI31XLTS U6275 ( .A0(cont_iter_out[1]), .A1(cont_iter_out[0]), .A2(n5262),
.B0(n5406), .Y(n5270) );
AO21XLTS U6276 ( .A0(d_ff3_LUT_out[56]), .A1(n5362), .B0(n5270), .Y(n3158)
);
OA21XLTS U6277 ( .A0(n5547), .A1(d_ff3_LUT_out[53]), .B0(n5263), .Y(n3155)
);
AO21XLTS U6278 ( .A0(d_ff3_LUT_out[52]), .A1(n5370), .B0(n5264), .Y(n3154)
);
AOI22X1TS U6279 ( .A0(n6126), .A1(n5295), .B0(n5269), .B1(n5265), .Y(n3151)
);
OAI2BB1X1TS U6280 ( .A0N(d_ff3_LUT_out[42]), .A1N(n5369), .B0(n5266), .Y(
n3149) );
OA22X1TS U6281 ( .A0(n5742), .A1(d_ff3_LUT_out[39]), .B0(n5267), .B1(n5278),
.Y(n3147) );
AO21XLTS U6282 ( .A0(d_ff3_LUT_out[37]), .A1(n5362), .B0(n5268), .Y(n3146)
);
AOI22X1TS U6283 ( .A0(n6127), .A1(n5295), .B0(n5271), .B1(n5270), .Y(n3140)
);
NAND2X1TS U6284 ( .A(n5272), .B(n5899), .Y(n5290) );
OA22X1TS U6285 ( .A0(n5742), .A1(d_ff3_LUT_out[28]), .B0(cont_iter_out[3]),
.B1(n5290), .Y(n3139) );
AOI22X1TS U6286 ( .A0(n3196), .A1(n5273), .B0(d_ff3_LUT_out[27]), .B1(n5406),
.Y(n5275) );
AOI32X1TS U6287 ( .A0(n5288), .A1(n5275), .A2(n5312), .B0(n5274), .B1(n5275),
.Y(n3138) );
OAI2BB1X1TS U6288 ( .A0N(d_ff3_LUT_out[26]), .A1N(n5369), .B0(n5276), .Y(
n3137) );
AOI22X1TS U6289 ( .A0(n5289), .A1(n5277), .B0(d_ff3_LUT_out[25]), .B1(n5406),
.Y(n5279) );
AOI32X1TS U6290 ( .A0(n5288), .A1(n5279), .A2(n5278), .B0(n5928), .B1(n5279),
.Y(n3136) );
OAI2BB1X1TS U6291 ( .A0N(d_ff3_LUT_out[22]), .A1N(n5369), .B0(n5281), .Y(
n3133) );
AOI2BB2XLTS U6292 ( .B0(n5309), .B1(n5294), .A0N(n5742), .A1N(
d_ff3_LUT_out[21]), .Y(n3132) );
OAI2BB1X1TS U6293 ( .A0N(d_ff3_LUT_out[20]), .A1N(n5369), .B0(n5280), .Y(
n3131) );
OAI21XLTS U6294 ( .A0(d_ff3_LUT_out[19]), .A1(n5302), .B0(n5281), .Y(n5282)
);
NAND2X1TS U6295 ( .A(n5282), .B(n5291), .Y(n3130) );
NOR3XLTS U6296 ( .A(cont_iter_out[0]), .B(n5284), .C(n5283), .Y(n5298) );
CLKBUFX2TS U6297 ( .A(n5370), .Y(n5363) );
INVX2TS U6298 ( .A(n5363), .Y(n5549) );
OAI211XLTS U6299 ( .A0(n5549), .A1(d_ff3_LUT_out[17]), .B0(n5285), .C0(n5284), .Y(n5286) );
OAI2BB1X1TS U6300 ( .A0N(d_ff3_LUT_out[16]), .A1N(n5369), .B0(n5287), .Y(
n3127) );
NAND2X1TS U6301 ( .A(n5928), .B(n5310), .Y(n5303) );
AOI22X1TS U6302 ( .A0(d_ff3_LUT_out[10]), .A1(n5295), .B0(n5294), .B1(n5303),
.Y(n5297) );
NAND2X1TS U6303 ( .A(n5297), .B(n5296), .Y(n3121) );
AOI21X1TS U6304 ( .A0(d_ff3_LUT_out[9]), .A1(n5361), .B0(n5298), .Y(n5300)
);
OAI21XLTS U6305 ( .A0(n5899), .A1(n5303), .B0(n5302), .Y(n5315) );
OAI2BB1X1TS U6306 ( .A0N(n5306), .A1N(n5305), .B0(n5304), .Y(n3116) );
AOI21X1TS U6307 ( .A0(d_ff3_LUT_out[4]), .A1(n5361), .B0(n5307), .Y(n5308)
);
OAI2BB1X1TS U6308 ( .A0N(n5309), .A1N(n5547), .B0(n5308), .Y(n3115) );
AOI22X1TS U6309 ( .A0(n5311), .A1(n5310), .B0(d_ff3_LUT_out[2]), .B1(n5406),
.Y(n5314) );
OAI2BB2XLTS U6310 ( .B0(n5316), .B1(n5315), .A0N(d_ff3_LUT_out[0]), .A1N(
n5741), .Y(n3111) );
CLKBUFX2TS U6311 ( .A(n5330), .Y(n5329) );
INVX2TS U6312 ( .A(n5329), .Y(n5317) );
AO22XLTS U6313 ( .A0(n5317), .A1(d_ff1_operation_out), .B0(n5328), .B1(
operation), .Y(n3110) );
AO22XLTS U6314 ( .A0(n5317), .A1(d_ff1_shift_region_flag_out[0]), .B0(n5328),
.B1(shift_region_flag[0]), .Y(n3109) );
AO22XLTS U6315 ( .A0(n5317), .A1(d_ff1_shift_region_flag_out[1]), .B0(n5328),
.B1(shift_region_flag[1]), .Y(n3108) );
AO22XLTS U6316 ( .A0(n5317), .A1(d_ff1_Z[62]), .B0(n5328), .B1(data_in[62]),
.Y(n3107) );
AO22XLTS U6317 ( .A0(n5317), .A1(d_ff1_Z[61]), .B0(n5328), .B1(data_in[61]),
.Y(n3106) );
AO22XLTS U6318 ( .A0(n5317), .A1(d_ff1_Z[60]), .B0(n5328), .B1(data_in[60]),
.Y(n3105) );
AO22XLTS U6319 ( .A0(n5317), .A1(d_ff1_Z[59]), .B0(n5328), .B1(data_in[59]),
.Y(n3104) );
AO22XLTS U6320 ( .A0(n5317), .A1(d_ff1_Z[58]), .B0(n5328), .B1(data_in[58]),
.Y(n3103) );
CLKBUFX2TS U6321 ( .A(n5330), .Y(n5325) );
AO22XLTS U6322 ( .A0(n5317), .A1(d_ff1_Z[57]), .B0(n5325), .B1(data_in[57]),
.Y(n3102) );
AO22XLTS U6323 ( .A0(n5317), .A1(d_ff1_Z[56]), .B0(n5325), .B1(data_in[56]),
.Y(n3101) );
CLKBUFX2TS U6324 ( .A(n5330), .Y(n5326) );
INVX2TS U6325 ( .A(n5326), .Y(n5318) );
AO22XLTS U6326 ( .A0(n5318), .A1(d_ff1_Z[55]), .B0(n5325), .B1(data_in[55]),
.Y(n3100) );
AO22XLTS U6327 ( .A0(n5318), .A1(d_ff1_Z[54]), .B0(n5325), .B1(data_in[54]),
.Y(n3099) );
AO22XLTS U6328 ( .A0(n5318), .A1(d_ff1_Z[53]), .B0(n5325), .B1(data_in[53]),
.Y(n3098) );
AO22XLTS U6329 ( .A0(n5318), .A1(d_ff1_Z[52]), .B0(n5325), .B1(data_in[52]),
.Y(n3097) );
AO22XLTS U6330 ( .A0(n5318), .A1(d_ff1_Z[51]), .B0(n5325), .B1(data_in[51]),
.Y(n3096) );
AO22XLTS U6331 ( .A0(n5318), .A1(d_ff1_Z[50]), .B0(n5325), .B1(data_in[50]),
.Y(n3095) );
AO22XLTS U6332 ( .A0(n5318), .A1(d_ff1_Z[49]), .B0(n5325), .B1(data_in[49]),
.Y(n3094) );
CLKBUFX2TS U6333 ( .A(n5330), .Y(n5322) );
AO22XLTS U6334 ( .A0(n5318), .A1(d_ff1_Z[48]), .B0(n5322), .B1(data_in[48]),
.Y(n3093) );
AO22XLTS U6335 ( .A0(n5318), .A1(d_ff1_Z[47]), .B0(n5322), .B1(data_in[47]),
.Y(n3092) );
AO22XLTS U6336 ( .A0(n5318), .A1(d_ff1_Z[46]), .B0(n5322), .B1(data_in[46]),
.Y(n3091) );
CLKBUFX2TS U6337 ( .A(n5330), .Y(n5323) );
INVX2TS U6338 ( .A(n5323), .Y(n5319) );
AO22XLTS U6339 ( .A0(n5319), .A1(d_ff1_Z[45]), .B0(n5322), .B1(data_in[45]),
.Y(n3090) );
AO22XLTS U6340 ( .A0(n5319), .A1(d_ff1_Z[44]), .B0(n5322), .B1(data_in[44]),
.Y(n3089) );
AO22XLTS U6341 ( .A0(n5319), .A1(d_ff1_Z[43]), .B0(n5322), .B1(data_in[43]),
.Y(n3088) );
AO22XLTS U6342 ( .A0(n5319), .A1(d_ff1_Z[42]), .B0(n5322), .B1(data_in[42]),
.Y(n3087) );
AO22XLTS U6343 ( .A0(n5319), .A1(d_ff1_Z[41]), .B0(n5322), .B1(data_in[41]),
.Y(n3086) );
AO22XLTS U6344 ( .A0(n5319), .A1(d_ff1_Z[40]), .B0(n5322), .B1(data_in[40]),
.Y(n3085) );
CLKBUFX2TS U6345 ( .A(n5330), .Y(n5320) );
AO22XLTS U6346 ( .A0(n5319), .A1(d_ff1_Z[39]), .B0(n5320), .B1(data_in[39]),
.Y(n3084) );
AO22XLTS U6347 ( .A0(n5319), .A1(d_ff1_Z[38]), .B0(n5320), .B1(data_in[38]),
.Y(n3083) );
AO22XLTS U6348 ( .A0(n5319), .A1(d_ff1_Z[37]), .B0(n5320), .B1(data_in[37]),
.Y(n3082) );
AO22XLTS U6349 ( .A0(n5319), .A1(d_ff1_Z[36]), .B0(n5320), .B1(data_in[36]),
.Y(n3081) );
INVX2TS U6350 ( .A(n5320), .Y(n5321) );
AO22XLTS U6351 ( .A0(n5321), .A1(d_ff1_Z[35]), .B0(n5320), .B1(data_in[35]),
.Y(n3080) );
AO22XLTS U6352 ( .A0(n5321), .A1(d_ff1_Z[34]), .B0(n5320), .B1(data_in[34]),
.Y(n3079) );
AO22XLTS U6353 ( .A0(n5321), .A1(d_ff1_Z[33]), .B0(n5320), .B1(data_in[33]),
.Y(n3078) );
AO22XLTS U6354 ( .A0(n5321), .A1(d_ff1_Z[32]), .B0(n5320), .B1(data_in[32]),
.Y(n3077) );
AO22XLTS U6355 ( .A0(n5321), .A1(d_ff1_Z[31]), .B0(n5320), .B1(data_in[31]),
.Y(n3076) );
AO22XLTS U6356 ( .A0(n5321), .A1(d_ff1_Z[30]), .B0(n5323), .B1(data_in[30]),
.Y(n3075) );
AO22XLTS U6357 ( .A0(n5321), .A1(d_ff1_Z[29]), .B0(n5323), .B1(data_in[29]),
.Y(n3074) );
AO22XLTS U6358 ( .A0(n5321), .A1(d_ff1_Z[28]), .B0(n5323), .B1(data_in[28]),
.Y(n3073) );
AO22XLTS U6359 ( .A0(n5321), .A1(d_ff1_Z[27]), .B0(n5323), .B1(data_in[27]),
.Y(n3072) );
AO22XLTS U6360 ( .A0(n5321), .A1(d_ff1_Z[26]), .B0(n5323), .B1(data_in[26]),
.Y(n3071) );
INVX2TS U6361 ( .A(n5322), .Y(n5324) );
AO22XLTS U6362 ( .A0(n5324), .A1(d_ff1_Z[25]), .B0(n5323), .B1(data_in[25]),
.Y(n3070) );
AO22XLTS U6363 ( .A0(n5324), .A1(d_ff1_Z[24]), .B0(n5323), .B1(data_in[24]),
.Y(n3069) );
AO22XLTS U6364 ( .A0(n5324), .A1(d_ff1_Z[23]), .B0(n5323), .B1(data_in[23]),
.Y(n3068) );
AO22XLTS U6365 ( .A0(n5324), .A1(d_ff1_Z[22]), .B0(n5323), .B1(data_in[22]),
.Y(n3067) );
AO22XLTS U6366 ( .A0(n5324), .A1(d_ff1_Z[21]), .B0(n5326), .B1(data_in[21]),
.Y(n3066) );
AO22XLTS U6367 ( .A0(n5324), .A1(d_ff1_Z[20]), .B0(n5326), .B1(data_in[20]),
.Y(n3065) );
AO22XLTS U6368 ( .A0(n5324), .A1(d_ff1_Z[19]), .B0(n5326), .B1(data_in[19]),
.Y(n3064) );
AO22XLTS U6369 ( .A0(n5324), .A1(d_ff1_Z[18]), .B0(n5326), .B1(data_in[18]),
.Y(n3063) );
AO22XLTS U6370 ( .A0(n5324), .A1(d_ff1_Z[17]), .B0(n5326), .B1(data_in[17]),
.Y(n3062) );
AO22XLTS U6371 ( .A0(n5324), .A1(d_ff1_Z[16]), .B0(n5326), .B1(data_in[16]),
.Y(n3061) );
INVX2TS U6372 ( .A(n5325), .Y(n5327) );
AO22XLTS U6373 ( .A0(n5327), .A1(d_ff1_Z[15]), .B0(n5326), .B1(data_in[15]),
.Y(n3060) );
AO22XLTS U6374 ( .A0(n5327), .A1(d_ff1_Z[14]), .B0(n5326), .B1(data_in[14]),
.Y(n3059) );
AO22XLTS U6375 ( .A0(n5327), .A1(d_ff1_Z[13]), .B0(n5326), .B1(data_in[13]),
.Y(n3058) );
AO22XLTS U6376 ( .A0(n5327), .A1(d_ff1_Z[12]), .B0(n5329), .B1(data_in[12]),
.Y(n3057) );
AO22XLTS U6377 ( .A0(n5327), .A1(d_ff1_Z[11]), .B0(n5329), .B1(data_in[11]),
.Y(n3056) );
AO22XLTS U6378 ( .A0(n5327), .A1(d_ff1_Z[10]), .B0(n5329), .B1(data_in[10]),
.Y(n3055) );
AO22XLTS U6379 ( .A0(n5327), .A1(d_ff1_Z[9]), .B0(n5329), .B1(data_in[9]),
.Y(n3054) );
AO22XLTS U6380 ( .A0(n5327), .A1(d_ff1_Z[8]), .B0(n5329), .B1(data_in[8]),
.Y(n3053) );
AO22XLTS U6381 ( .A0(n5327), .A1(d_ff1_Z[7]), .B0(n5329), .B1(data_in[7]),
.Y(n3052) );
AO22XLTS U6382 ( .A0(n5327), .A1(d_ff1_Z[6]), .B0(n5329), .B1(data_in[6]),
.Y(n3051) );
INVX2TS U6383 ( .A(n5328), .Y(n5332) );
AO22XLTS U6384 ( .A0(n5332), .A1(d_ff1_Z[5]), .B0(n5329), .B1(data_in[5]),
.Y(n3050) );
AO22XLTS U6385 ( .A0(n5332), .A1(d_ff1_Z[4]), .B0(n5329), .B1(data_in[4]),
.Y(n3049) );
CLKBUFX2TS U6386 ( .A(n5330), .Y(n5331) );
AO22XLTS U6387 ( .A0(n5332), .A1(d_ff1_Z[3]), .B0(n5331), .B1(data_in[3]),
.Y(n3048) );
AO22XLTS U6388 ( .A0(n5332), .A1(d_ff1_Z[2]), .B0(n5331), .B1(data_in[2]),
.Y(n3047) );
AO22XLTS U6389 ( .A0(n5332), .A1(d_ff1_Z[1]), .B0(n5331), .B1(data_in[1]),
.Y(n3046) );
AO22XLTS U6390 ( .A0(n5332), .A1(d_ff1_Z[0]), .B0(n5331), .B1(data_in[0]),
.Y(n3045) );
AO22XLTS U6391 ( .A0(n5332), .A1(d_ff1_Z[63]), .B0(n5331), .B1(data_in[63]),
.Y(n3044) );
CLKBUFX2TS U6392 ( .A(n5336), .Y(n5355) );
INVX2TS U6393 ( .A(n5355), .Y(n5333) );
AO22XLTS U6394 ( .A0(n5333), .A1(result_add_subt[0]), .B0(n5576), .B1(
d_ff_Zn[0]), .Y(n3037) );
CLKBUFX2TS U6395 ( .A(n5577), .Y(n5746) );
INVX2TS U6396 ( .A(n5746), .Y(n5334) );
CLKBUFX2TS U6397 ( .A(n5746), .Y(n5573) );
AO22XLTS U6398 ( .A0(n5334), .A1(result_add_subt[0]), .B0(n5573), .B1(
d_ff_Yn[0]), .Y(n3036) );
CLKBUFX2TS U6399 ( .A(n5748), .Y(n5753) );
INVX2TS U6400 ( .A(n5753), .Y(n5335) );
CLKBUFX2TS U6401 ( .A(n5748), .Y(n5575) );
AO22XLTS U6402 ( .A0(n5335), .A1(result_add_subt[0]), .B0(n5575), .B1(
d_ff_Xn[0]), .Y(n3035) );
AO22XLTS U6403 ( .A0(n5333), .A1(result_add_subt[1]), .B0(n5355), .B1(
d_ff_Zn[1]), .Y(n3034) );
AO22XLTS U6404 ( .A0(n5334), .A1(result_add_subt[1]), .B0(n5573), .B1(
d_ff_Yn[1]), .Y(n3033) );
AO22XLTS U6405 ( .A0(n5335), .A1(result_add_subt[1]), .B0(n5575), .B1(
d_ff_Xn[1]), .Y(n3032) );
AO22XLTS U6406 ( .A0(n5333), .A1(result_add_subt[2]), .B0(n5355), .B1(
d_ff_Zn[2]), .Y(n3031) );
AO22XLTS U6407 ( .A0(n5334), .A1(result_add_subt[2]), .B0(n5573), .B1(
d_ff_Yn[2]), .Y(n3030) );
AO22XLTS U6408 ( .A0(n5335), .A1(result_add_subt[2]), .B0(n5575), .B1(
d_ff_Xn[2]), .Y(n3029) );
AO22XLTS U6409 ( .A0(n5333), .A1(result_add_subt[3]), .B0(n5336), .B1(
d_ff_Zn[3]), .Y(n3028) );
AO22XLTS U6410 ( .A0(n5334), .A1(result_add_subt[3]), .B0(n5573), .B1(
d_ff_Yn[3]), .Y(n3027) );
AO22XLTS U6411 ( .A0(n5335), .A1(result_add_subt[3]), .B0(n5575), .B1(
d_ff_Xn[3]), .Y(n3026) );
AO22XLTS U6412 ( .A0(n5333), .A1(result_add_subt[4]), .B0(n5336), .B1(
d_ff_Zn[4]), .Y(n3025) );
AO22XLTS U6413 ( .A0(n5334), .A1(result_add_subt[4]), .B0(n5573), .B1(
d_ff_Yn[4]), .Y(n3024) );
AO22XLTS U6414 ( .A0(n5335), .A1(result_add_subt[4]), .B0(n5575), .B1(
d_ff_Xn[4]), .Y(n3023) );
AO22XLTS U6415 ( .A0(n5333), .A1(result_add_subt[5]), .B0(n5336), .B1(
d_ff_Zn[5]), .Y(n3022) );
AO22XLTS U6416 ( .A0(n5334), .A1(result_add_subt[5]), .B0(n5573), .B1(
d_ff_Yn[5]), .Y(n3021) );
AO22XLTS U6417 ( .A0(n5335), .A1(result_add_subt[5]), .B0(n5575), .B1(
d_ff_Xn[5]), .Y(n3020) );
AO22XLTS U6418 ( .A0(n5333), .A1(result_add_subt[6]), .B0(n5336), .B1(
d_ff_Zn[6]), .Y(n3019) );
AO22XLTS U6419 ( .A0(n5334), .A1(result_add_subt[6]), .B0(n5573), .B1(
d_ff_Yn[6]), .Y(n3018) );
AO22XLTS U6420 ( .A0(n5335), .A1(result_add_subt[6]), .B0(n5575), .B1(
d_ff_Xn[6]), .Y(n3017) );
AO22XLTS U6421 ( .A0(n5333), .A1(result_add_subt[7]), .B0(n5336), .B1(
d_ff_Zn[7]), .Y(n3016) );
AO22XLTS U6422 ( .A0(n5334), .A1(result_add_subt[7]), .B0(n5573), .B1(
d_ff_Yn[7]), .Y(n3015) );
AO22XLTS U6423 ( .A0(n5335), .A1(result_add_subt[7]), .B0(n5575), .B1(
d_ff_Xn[7]), .Y(n3014) );
AO22XLTS U6424 ( .A0(n5333), .A1(result_add_subt[8]), .B0(n5336), .B1(
d_ff_Zn[8]), .Y(n3013) );
AO22XLTS U6425 ( .A0(n5334), .A1(result_add_subt[8]), .B0(n5573), .B1(
d_ff_Yn[8]), .Y(n3012) );
AO22XLTS U6426 ( .A0(n5335), .A1(result_add_subt[8]), .B0(n5575), .B1(
d_ff_Xn[8]), .Y(n3011) );
AO22XLTS U6427 ( .A0(n5333), .A1(result_add_subt[9]), .B0(n5336), .B1(
d_ff_Zn[9]), .Y(n3010) );
CLKBUFX2TS U6428 ( .A(n5746), .Y(n5359) );
AO22XLTS U6429 ( .A0(n5334), .A1(result_add_subt[9]), .B0(n5359), .B1(
d_ff_Yn[9]), .Y(n3009) );
CLKBUFX2TS U6430 ( .A(n5753), .Y(n5360) );
AO22XLTS U6431 ( .A0(n5335), .A1(result_add_subt[9]), .B0(n5360), .B1(
d_ff_Xn[9]), .Y(n3008) );
CLKBUFX2TS U6432 ( .A(n5355), .Y(n5340) );
INVX2TS U6433 ( .A(n5340), .Y(n5337) );
AO22XLTS U6434 ( .A0(n5337), .A1(result_add_subt[10]), .B0(n5336), .B1(
d_ff_Zn[10]), .Y(n3007) );
CLKBUFX2TS U6435 ( .A(n5746), .Y(n5568) );
INVX2TS U6436 ( .A(n5568), .Y(n5338) );
AO22XLTS U6437 ( .A0(n5338), .A1(result_add_subt[10]), .B0(n5359), .B1(
d_ff_Yn[10]), .Y(n3006) );
CLKBUFX2TS U6438 ( .A(n5753), .Y(n5569) );
INVX2TS U6439 ( .A(n5569), .Y(n5339) );
AO22XLTS U6440 ( .A0(n5339), .A1(result_add_subt[10]), .B0(n5360), .B1(
d_ff_Xn[10]), .Y(n3005) );
AO22XLTS U6441 ( .A0(n5337), .A1(result_add_subt[11]), .B0(n5355), .B1(
d_ff_Zn[11]), .Y(n3004) );
AO22XLTS U6442 ( .A0(n5338), .A1(result_add_subt[11]), .B0(n5359), .B1(
d_ff_Yn[11]), .Y(n3003) );
AO22XLTS U6443 ( .A0(n5339), .A1(result_add_subt[11]), .B0(n5360), .B1(
d_ff_Xn[11]), .Y(n3002) );
AO22XLTS U6444 ( .A0(n5337), .A1(result_add_subt[12]), .B0(n5355), .B1(
d_ff_Zn[12]), .Y(n3001) );
AO22XLTS U6445 ( .A0(n5338), .A1(result_add_subt[12]), .B0(n5359), .B1(
d_ff_Yn[12]), .Y(n3000) );
AO22XLTS U6446 ( .A0(n5339), .A1(result_add_subt[12]), .B0(n5360), .B1(
d_ff_Xn[12]), .Y(n2999) );
AO22XLTS U6447 ( .A0(n5337), .A1(result_add_subt[13]), .B0(n5340), .B1(
d_ff_Zn[13]), .Y(n2998) );
AO22XLTS U6448 ( .A0(n5338), .A1(result_add_subt[13]), .B0(n5359), .B1(
d_ff_Yn[13]), .Y(n2997) );
AO22XLTS U6449 ( .A0(n5339), .A1(result_add_subt[13]), .B0(n5360), .B1(
d_ff_Xn[13]), .Y(n2996) );
AO22XLTS U6450 ( .A0(n5337), .A1(result_add_subt[14]), .B0(n5340), .B1(
d_ff_Zn[14]), .Y(n2995) );
AO22XLTS U6451 ( .A0(n5338), .A1(result_add_subt[14]), .B0(n5359), .B1(
d_ff_Yn[14]), .Y(n2994) );
AO22XLTS U6452 ( .A0(n5339), .A1(result_add_subt[14]), .B0(n5360), .B1(
d_ff_Xn[14]), .Y(n2993) );
AO22XLTS U6453 ( .A0(n5337), .A1(result_add_subt[15]), .B0(n5340), .B1(
d_ff_Zn[15]), .Y(n2992) );
AO22XLTS U6454 ( .A0(n5338), .A1(result_add_subt[15]), .B0(n5359), .B1(
d_ff_Yn[15]), .Y(n2991) );
AO22XLTS U6455 ( .A0(n5339), .A1(result_add_subt[15]), .B0(n5360), .B1(
d_ff_Xn[15]), .Y(n2990) );
AO22XLTS U6456 ( .A0(n5337), .A1(result_add_subt[16]), .B0(n5340), .B1(
d_ff_Zn[16]), .Y(n2989) );
AO22XLTS U6457 ( .A0(n5338), .A1(result_add_subt[16]), .B0(n5359), .B1(
d_ff_Yn[16]), .Y(n2988) );
AO22XLTS U6458 ( .A0(n5339), .A1(result_add_subt[16]), .B0(n5360), .B1(
d_ff_Xn[16]), .Y(n2987) );
AO22XLTS U6459 ( .A0(n5337), .A1(result_add_subt[17]), .B0(n5340), .B1(
d_ff_Zn[17]), .Y(n2986) );
AO22XLTS U6460 ( .A0(n5338), .A1(result_add_subt[17]), .B0(n5359), .B1(
d_ff_Yn[17]), .Y(n2985) );
AO22XLTS U6461 ( .A0(n5339), .A1(result_add_subt[17]), .B0(n5360), .B1(
d_ff_Xn[17]), .Y(n2984) );
AO22XLTS U6462 ( .A0(n5337), .A1(result_add_subt[18]), .B0(n5340), .B1(
d_ff_Zn[18]), .Y(n2983) );
CLKBUFX2TS U6463 ( .A(n5577), .Y(n5350) );
AO22XLTS U6464 ( .A0(n5338), .A1(result_add_subt[18]), .B0(n5350), .B1(
d_ff_Yn[18]), .Y(n2982) );
CLKBUFX2TS U6465 ( .A(n5753), .Y(n5351) );
AO22XLTS U6466 ( .A0(n5339), .A1(result_add_subt[18]), .B0(n5351), .B1(
d_ff_Xn[18]), .Y(n2981) );
AO22XLTS U6467 ( .A0(n5337), .A1(result_add_subt[19]), .B0(n5340), .B1(
d_ff_Zn[19]), .Y(n2980) );
AO22XLTS U6468 ( .A0(n5338), .A1(result_add_subt[19]), .B0(n5350), .B1(
d_ff_Yn[19]), .Y(n2979) );
AO22XLTS U6469 ( .A0(n5339), .A1(result_add_subt[19]), .B0(n5351), .B1(
d_ff_Xn[19]), .Y(n2978) );
CLKBUFX2TS U6470 ( .A(n5355), .Y(n5344) );
INVX2TS U6471 ( .A(n5344), .Y(n5341) );
AO22XLTS U6472 ( .A0(n5341), .A1(result_add_subt[20]), .B0(n5340), .B1(
d_ff_Zn[20]), .Y(n2977) );
CLKBUFX2TS U6473 ( .A(n5746), .Y(n5352) );
INVX2TS U6474 ( .A(n5352), .Y(n5342) );
AO22XLTS U6475 ( .A0(n5342), .A1(result_add_subt[20]), .B0(n5350), .B1(
d_ff_Yn[20]), .Y(n2976) );
CLKBUFX2TS U6476 ( .A(n5753), .Y(n5353) );
INVX2TS U6477 ( .A(n5353), .Y(n5343) );
AO22XLTS U6478 ( .A0(n5343), .A1(result_add_subt[20]), .B0(n5351), .B1(
d_ff_Xn[20]), .Y(n2975) );
AO22XLTS U6479 ( .A0(n5341), .A1(result_add_subt[21]), .B0(n5340), .B1(
d_ff_Zn[21]), .Y(n2974) );
AO22XLTS U6480 ( .A0(n5342), .A1(result_add_subt[21]), .B0(n5350), .B1(
d_ff_Yn[21]), .Y(n2973) );
AO22XLTS U6481 ( .A0(n5343), .A1(result_add_subt[21]), .B0(n5351), .B1(
d_ff_Xn[21]), .Y(n2972) );
AO22XLTS U6482 ( .A0(n5341), .A1(result_add_subt[22]), .B0(n5344), .B1(
d_ff_Zn[22]), .Y(n2971) );
AO22XLTS U6483 ( .A0(n5342), .A1(result_add_subt[22]), .B0(n5350), .B1(
d_ff_Yn[22]), .Y(n2970) );
AO22XLTS U6484 ( .A0(n5343), .A1(result_add_subt[22]), .B0(n5351), .B1(
d_ff_Xn[22]), .Y(n2969) );
AO22XLTS U6485 ( .A0(n5341), .A1(result_add_subt[23]), .B0(n5344), .B1(
d_ff_Zn[23]), .Y(n2968) );
AO22XLTS U6486 ( .A0(n5342), .A1(result_add_subt[23]), .B0(n5350), .B1(
d_ff_Yn[23]), .Y(n2967) );
AO22XLTS U6487 ( .A0(n5343), .A1(result_add_subt[23]), .B0(n5351), .B1(
d_ff_Xn[23]), .Y(n2966) );
AO22XLTS U6488 ( .A0(n5341), .A1(result_add_subt[24]), .B0(n5344), .B1(
d_ff_Zn[24]), .Y(n2965) );
AO22XLTS U6489 ( .A0(n5342), .A1(result_add_subt[24]), .B0(n5350), .B1(
d_ff_Yn[24]), .Y(n2964) );
AO22XLTS U6490 ( .A0(n5343), .A1(result_add_subt[24]), .B0(n5351), .B1(
d_ff_Xn[24]), .Y(n2963) );
AO22XLTS U6491 ( .A0(n5341), .A1(result_add_subt[25]), .B0(n5344), .B1(
d_ff_Zn[25]), .Y(n2962) );
AO22XLTS U6492 ( .A0(n5342), .A1(result_add_subt[25]), .B0(n5350), .B1(
d_ff_Yn[25]), .Y(n2961) );
AO22XLTS U6493 ( .A0(n5343), .A1(result_add_subt[25]), .B0(n5351), .B1(
d_ff_Xn[25]), .Y(n2960) );
AO22XLTS U6494 ( .A0(n5341), .A1(result_add_subt[26]), .B0(n5344), .B1(
d_ff_Zn[26]), .Y(n2959) );
AO22XLTS U6495 ( .A0(n5342), .A1(result_add_subt[26]), .B0(n5350), .B1(
d_ff_Yn[26]), .Y(n2958) );
AO22XLTS U6496 ( .A0(n5343), .A1(result_add_subt[26]), .B0(n5351), .B1(
d_ff_Xn[26]), .Y(n2957) );
AO22XLTS U6497 ( .A0(n5341), .A1(result_add_subt[27]), .B0(n5344), .B1(
d_ff_Zn[27]), .Y(n2956) );
CLKBUFX2TS U6498 ( .A(n5746), .Y(n5345) );
AO22XLTS U6499 ( .A0(n5342), .A1(result_add_subt[27]), .B0(n5345), .B1(
d_ff_Yn[27]), .Y(n2955) );
CLKBUFX2TS U6500 ( .A(n5753), .Y(n5346) );
AO22XLTS U6501 ( .A0(n5343), .A1(result_add_subt[27]), .B0(n5346), .B1(
d_ff_Xn[27]), .Y(n2954) );
AO22XLTS U6502 ( .A0(n5341), .A1(result_add_subt[28]), .B0(n5344), .B1(
d_ff_Zn[28]), .Y(n2953) );
AO22XLTS U6503 ( .A0(n5342), .A1(result_add_subt[28]), .B0(n5345), .B1(
d_ff_Yn[28]), .Y(n2952) );
AO22XLTS U6504 ( .A0(n5343), .A1(result_add_subt[28]), .B0(n5346), .B1(
d_ff_Xn[28]), .Y(n2951) );
AO22XLTS U6505 ( .A0(n5341), .A1(result_add_subt[29]), .B0(n5344), .B1(
d_ff_Zn[29]), .Y(n2950) );
AO22XLTS U6506 ( .A0(n5342), .A1(result_add_subt[29]), .B0(n5345), .B1(
d_ff_Yn[29]), .Y(n2949) );
AO22XLTS U6507 ( .A0(n5343), .A1(result_add_subt[29]), .B0(n5346), .B1(
d_ff_Xn[29]), .Y(n2948) );
CLKBUFX2TS U6508 ( .A(n5355), .Y(n5578) );
INVX2TS U6509 ( .A(n5578), .Y(n5347) );
AO22XLTS U6510 ( .A0(n5347), .A1(result_add_subt[30]), .B0(n5344), .B1(
d_ff_Zn[30]), .Y(n2947) );
INVX2TS U6511 ( .A(n5345), .Y(n5348) );
AO22XLTS U6512 ( .A0(n5348), .A1(result_add_subt[30]), .B0(n5345), .B1(
d_ff_Yn[30]), .Y(n2946) );
INVX2TS U6513 ( .A(n5346), .Y(n5349) );
AO22XLTS U6514 ( .A0(n5349), .A1(result_add_subt[30]), .B0(n5346), .B1(
d_ff_Xn[30]), .Y(n2945) );
AO22XLTS U6515 ( .A0(n5347), .A1(result_add_subt[31]), .B0(n5578), .B1(
d_ff_Zn[31]), .Y(n2944) );
AO22XLTS U6516 ( .A0(n5348), .A1(result_add_subt[31]), .B0(n5345), .B1(
d_ff_Yn[31]), .Y(n2943) );
AO22XLTS U6517 ( .A0(n5349), .A1(result_add_subt[31]), .B0(n5346), .B1(
d_ff_Xn[31]), .Y(n2942) );
AO22XLTS U6518 ( .A0(n5347), .A1(result_add_subt[32]), .B0(n5578), .B1(
d_ff_Zn[32]), .Y(n2941) );
AO22XLTS U6519 ( .A0(n5348), .A1(result_add_subt[32]), .B0(n5345), .B1(
d_ff_Yn[32]), .Y(n2940) );
AO22XLTS U6520 ( .A0(n5349), .A1(result_add_subt[32]), .B0(n5346), .B1(
d_ff_Xn[32]), .Y(n2939) );
AO22XLTS U6521 ( .A0(n5347), .A1(result_add_subt[33]), .B0(n5578), .B1(
d_ff_Zn[33]), .Y(n2938) );
AO22XLTS U6522 ( .A0(n5348), .A1(result_add_subt[33]), .B0(n5345), .B1(
d_ff_Yn[33]), .Y(n2937) );
AO22XLTS U6523 ( .A0(n5349), .A1(result_add_subt[33]), .B0(n5346), .B1(
d_ff_Xn[33]), .Y(n2936) );
AO22XLTS U6524 ( .A0(n5347), .A1(result_add_subt[34]), .B0(n5578), .B1(
d_ff_Zn[34]), .Y(n2935) );
AO22XLTS U6525 ( .A0(n5348), .A1(result_add_subt[34]), .B0(n5345), .B1(
d_ff_Yn[34]), .Y(n2934) );
AO22XLTS U6526 ( .A0(n5349), .A1(result_add_subt[34]), .B0(n5346), .B1(
d_ff_Xn[34]), .Y(n2933) );
AO22XLTS U6527 ( .A0(n5347), .A1(result_add_subt[35]), .B0(n5578), .B1(
d_ff_Zn[35]), .Y(n2932) );
AO22XLTS U6528 ( .A0(n5348), .A1(result_add_subt[35]), .B0(n5345), .B1(
d_ff_Yn[35]), .Y(n2931) );
AO22XLTS U6529 ( .A0(n5349), .A1(result_add_subt[35]), .B0(n5346), .B1(
d_ff_Xn[35]), .Y(n2930) );
AO22XLTS U6530 ( .A0(n5347), .A1(result_add_subt[36]), .B0(n5578), .B1(
d_ff_Zn[36]), .Y(n2929) );
AO22XLTS U6531 ( .A0(n5348), .A1(result_add_subt[36]), .B0(n5352), .B1(
d_ff_Yn[36]), .Y(n2928) );
AO22XLTS U6532 ( .A0(n5349), .A1(result_add_subt[36]), .B0(n5353), .B1(
d_ff_Xn[36]), .Y(n2927) );
AO22XLTS U6533 ( .A0(n5347), .A1(result_add_subt[37]), .B0(n5578), .B1(
d_ff_Zn[37]), .Y(n2926) );
AO22XLTS U6534 ( .A0(n5348), .A1(result_add_subt[37]), .B0(n5352), .B1(
d_ff_Yn[37]), .Y(n2925) );
AO22XLTS U6535 ( .A0(n5349), .A1(result_add_subt[37]), .B0(n5353), .B1(
d_ff_Xn[37]), .Y(n2924) );
AO22XLTS U6536 ( .A0(n5347), .A1(result_add_subt[38]), .B0(n5578), .B1(
d_ff_Zn[38]), .Y(n2923) );
AO22XLTS U6537 ( .A0(n5348), .A1(result_add_subt[38]), .B0(n5352), .B1(
d_ff_Yn[38]), .Y(n2922) );
AO22XLTS U6538 ( .A0(n5349), .A1(result_add_subt[38]), .B0(n5353), .B1(
d_ff_Xn[38]), .Y(n2921) );
CLKBUFX2TS U6539 ( .A(n5355), .Y(n5354) );
AO22XLTS U6540 ( .A0(n5347), .A1(result_add_subt[39]), .B0(n5354), .B1(
d_ff_Zn[39]), .Y(n2920) );
AO22XLTS U6541 ( .A0(n5348), .A1(result_add_subt[39]), .B0(n5352), .B1(
d_ff_Yn[39]), .Y(n2919) );
AO22XLTS U6542 ( .A0(n5349), .A1(result_add_subt[39]), .B0(n5353), .B1(
d_ff_Xn[39]), .Y(n2918) );
INVX2TS U6543 ( .A(n5354), .Y(n5356) );
AO22XLTS U6544 ( .A0(n5356), .A1(result_add_subt[40]), .B0(n5354), .B1(
d_ff_Zn[40]), .Y(n2917) );
INVX2TS U6545 ( .A(n5350), .Y(n5357) );
AO22XLTS U6546 ( .A0(n5357), .A1(result_add_subt[40]), .B0(n5352), .B1(
d_ff_Yn[40]), .Y(n2916) );
INVX2TS U6547 ( .A(n5351), .Y(n5358) );
AO22XLTS U6548 ( .A0(n5358), .A1(result_add_subt[40]), .B0(n5353), .B1(
d_ff_Xn[40]), .Y(n2915) );
AO22XLTS U6549 ( .A0(n5356), .A1(result_add_subt[41]), .B0(n5354), .B1(
d_ff_Zn[41]), .Y(n2914) );
AO22XLTS U6550 ( .A0(n5357), .A1(result_add_subt[41]), .B0(n5352), .B1(
d_ff_Yn[41]), .Y(n2913) );
AO22XLTS U6551 ( .A0(n5358), .A1(result_add_subt[41]), .B0(n5353), .B1(
d_ff_Xn[41]), .Y(n2912) );
AO22XLTS U6552 ( .A0(n5356), .A1(result_add_subt[42]), .B0(n5354), .B1(
d_ff_Zn[42]), .Y(n2911) );
AO22XLTS U6553 ( .A0(n5357), .A1(result_add_subt[42]), .B0(n5352), .B1(
d_ff_Yn[42]), .Y(n2910) );
AO22XLTS U6554 ( .A0(n5358), .A1(result_add_subt[42]), .B0(n5353), .B1(
d_ff_Xn[42]), .Y(n2909) );
AO22XLTS U6555 ( .A0(n5356), .A1(result_add_subt[43]), .B0(n5354), .B1(
d_ff_Zn[43]), .Y(n2908) );
AO22XLTS U6556 ( .A0(n5357), .A1(result_add_subt[43]), .B0(n5352), .B1(
d_ff_Yn[43]), .Y(n2907) );
AO22XLTS U6557 ( .A0(n5358), .A1(result_add_subt[43]), .B0(n5353), .B1(
d_ff_Xn[43]), .Y(n2906) );
AO22XLTS U6558 ( .A0(n5356), .A1(result_add_subt[44]), .B0(n5354), .B1(
d_ff_Zn[44]), .Y(n2905) );
AO22XLTS U6559 ( .A0(n5357), .A1(result_add_subt[44]), .B0(n5352), .B1(
d_ff_Yn[44]), .Y(n2904) );
AO22XLTS U6560 ( .A0(n5358), .A1(result_add_subt[44]), .B0(n5353), .B1(
d_ff_Xn[44]), .Y(n2903) );
AO22XLTS U6561 ( .A0(n5356), .A1(result_add_subt[45]), .B0(n5354), .B1(
d_ff_Zn[45]), .Y(n2902) );
AO22XLTS U6562 ( .A0(n5357), .A1(result_add_subt[45]), .B0(n5568), .B1(
d_ff_Yn[45]), .Y(n2901) );
AO22XLTS U6563 ( .A0(n5358), .A1(result_add_subt[45]), .B0(n5569), .B1(
d_ff_Xn[45]), .Y(n2900) );
AO22XLTS U6564 ( .A0(n5356), .A1(result_add_subt[46]), .B0(n5354), .B1(
d_ff_Zn[46]), .Y(n2899) );
AO22XLTS U6565 ( .A0(n5357), .A1(result_add_subt[46]), .B0(n5568), .B1(
d_ff_Yn[46]), .Y(n2898) );
AO22XLTS U6566 ( .A0(n5358), .A1(result_add_subt[46]), .B0(n5569), .B1(
d_ff_Xn[46]), .Y(n2897) );
AO22XLTS U6567 ( .A0(n5356), .A1(result_add_subt[47]), .B0(n5354), .B1(
d_ff_Zn[47]), .Y(n2896) );
AO22XLTS U6568 ( .A0(n5357), .A1(result_add_subt[47]), .B0(n5568), .B1(
d_ff_Yn[47]), .Y(n2895) );
AO22XLTS U6569 ( .A0(n5358), .A1(result_add_subt[47]), .B0(n5569), .B1(
d_ff_Xn[47]), .Y(n2894) );
CLKBUFX2TS U6570 ( .A(n5355), .Y(n5570) );
AO22XLTS U6571 ( .A0(n5356), .A1(result_add_subt[48]), .B0(n5570), .B1(
d_ff_Zn[48]), .Y(n2893) );
AO22XLTS U6572 ( .A0(n5357), .A1(result_add_subt[48]), .B0(n5568), .B1(
d_ff_Yn[48]), .Y(n2892) );
AO22XLTS U6573 ( .A0(n5358), .A1(result_add_subt[48]), .B0(n5569), .B1(
d_ff_Xn[48]), .Y(n2891) );
AO22XLTS U6574 ( .A0(n5356), .A1(result_add_subt[49]), .B0(n5570), .B1(
d_ff_Zn[49]), .Y(n2890) );
AO22XLTS U6575 ( .A0(n5357), .A1(result_add_subt[49]), .B0(n5568), .B1(
d_ff_Yn[49]), .Y(n2889) );
AO22XLTS U6576 ( .A0(n5358), .A1(result_add_subt[49]), .B0(n5569), .B1(
d_ff_Xn[49]), .Y(n2888) );
INVX2TS U6577 ( .A(n5570), .Y(n5571) );
AO22XLTS U6578 ( .A0(n5571), .A1(result_add_subt[50]), .B0(n5570), .B1(
d_ff_Zn[50]), .Y(n2887) );
INVX2TS U6579 ( .A(n5359), .Y(n5572) );
AO22XLTS U6580 ( .A0(n5572), .A1(result_add_subt[50]), .B0(n5568), .B1(
d_ff_Yn[50]), .Y(n2886) );
INVX2TS U6581 ( .A(n5360), .Y(n5574) );
AO22XLTS U6582 ( .A0(n5574), .A1(result_add_subt[50]), .B0(n5569), .B1(
d_ff_Xn[50]), .Y(n2885) );
AO22XLTS U6583 ( .A0(n5571), .A1(result_add_subt[51]), .B0(n5570), .B1(
d_ff_Zn[51]), .Y(n2884) );
AO22XLTS U6584 ( .A0(n5572), .A1(result_add_subt[51]), .B0(n5568), .B1(
d_ff_Yn[51]), .Y(n2883) );
AO22XLTS U6585 ( .A0(n5574), .A1(result_add_subt[51]), .B0(n5569), .B1(
d_ff_Xn[51]), .Y(n2882) );
CLKBUFX2TS U6586 ( .A(n5423), .Y(n5411) );
OA22X1TS U6587 ( .A0(n5435), .A1(d_ff2_X[0]), .B0(d_ff_Xn[0]), .B1(n5411),
.Y(n2881) );
INVX2TS U6588 ( .A(n5406), .Y(n5537) );
AO22XLTS U6589 ( .A0(n5537), .A1(d_ff2_X[0]), .B0(n5362), .B1(
d_ff3_sh_x_out[0]), .Y(n2880) );
INVX2TS U6590 ( .A(n5378), .Y(n5516) );
AO22XLTS U6591 ( .A0(d_ff_Xn[1]), .A1(n5516), .B0(d_ff2_X[1]), .B1(n5519),
.Y(n2879) );
AO22XLTS U6592 ( .A0(n5537), .A1(d_ff2_X[1]), .B0(n5362), .B1(
d_ff3_sh_x_out[1]), .Y(n2878) );
AO22XLTS U6593 ( .A0(d_ff_Xn[2]), .A1(n5750), .B0(d_ff2_X[2]), .B1(n5372),
.Y(n2877) );
INVX2TS U6594 ( .A(n5361), .Y(n5364) );
AO22XLTS U6595 ( .A0(n5364), .A1(d_ff2_X[2]), .B0(n5362), .B1(
d_ff3_sh_x_out[2]), .Y(n2876) );
OA22X1TS U6596 ( .A0(n6246), .A1(d_ff2_X[3]), .B0(d_ff_Xn[3]), .B1(n5380),
.Y(n2875) );
AO22XLTS U6597 ( .A0(n5364), .A1(d_ff2_X[3]), .B0(n5362), .B1(
d_ff3_sh_x_out[3]), .Y(n2874) );
INVX2TS U6598 ( .A(n5411), .Y(n5377) );
AO22XLTS U6599 ( .A0(d_ff_Xn[4]), .A1(n5377), .B0(d_ff2_X[4]), .B1(n5466),
.Y(n2873) );
AO22XLTS U6600 ( .A0(n5537), .A1(d_ff2_X[4]), .B0(n5362), .B1(
d_ff3_sh_x_out[4]), .Y(n2872) );
INVX2TS U6601 ( .A(n5411), .Y(n5517) );
AO22XLTS U6602 ( .A0(d_ff_Xn[5]), .A1(n5517), .B0(d_ff2_X[5]), .B1(n5466),
.Y(n2871) );
AO22XLTS U6603 ( .A0(n5537), .A1(d_ff2_X[5]), .B0(n5362), .B1(
d_ff3_sh_x_out[5]), .Y(n2870) );
OA22X1TS U6604 ( .A0(n6246), .A1(d_ff2_X[6]), .B0(d_ff_Xn[6]), .B1(n5380),
.Y(n2869) );
AO22XLTS U6605 ( .A0(n5537), .A1(d_ff2_X[6]), .B0(n5362), .B1(
d_ff3_sh_x_out[6]), .Y(n2868) );
OA22X1TS U6606 ( .A0(n6246), .A1(d_ff2_X[7]), .B0(d_ff_Xn[7]), .B1(n5380),
.Y(n2867) );
AO22XLTS U6607 ( .A0(n5364), .A1(d_ff2_X[7]), .B0(n5363), .B1(
d_ff3_sh_x_out[7]), .Y(n2866) );
OA22X1TS U6608 ( .A0(n6246), .A1(d_ff2_X[8]), .B0(d_ff_Xn[8]), .B1(n5380),
.Y(n2865) );
AO22XLTS U6609 ( .A0(n5364), .A1(d_ff2_X[8]), .B0(n5363), .B1(
d_ff3_sh_x_out[8]), .Y(n2864) );
OA22X1TS U6610 ( .A0(n6246), .A1(d_ff2_X[9]), .B0(d_ff_Xn[9]), .B1(n5380),
.Y(n2863) );
AO22XLTS U6611 ( .A0(n5364), .A1(d_ff2_X[9]), .B0(n5363), .B1(
d_ff3_sh_x_out[9]), .Y(n2862) );
AO22XLTS U6612 ( .A0(d_ff_Xn[10]), .A1(n5517), .B0(d_ff2_X[10]), .B1(n5466),
.Y(n2861) );
AO22XLTS U6613 ( .A0(n5364), .A1(d_ff2_X[10]), .B0(n5363), .B1(
d_ff3_sh_x_out[10]), .Y(n2860) );
OA22X1TS U6614 ( .A0(n6246), .A1(d_ff2_X[11]), .B0(d_ff_Xn[11]), .B1(n5423),
.Y(n2859) );
INVX2TS U6615 ( .A(n5741), .Y(n5368) );
AO22XLTS U6616 ( .A0(n5368), .A1(d_ff2_X[11]), .B0(n5363), .B1(
d_ff3_sh_x_out[11]), .Y(n2858) );
INVX2TS U6617 ( .A(n5411), .Y(n5367) );
AO22XLTS U6618 ( .A0(d_ff_Xn[12]), .A1(n5367), .B0(d_ff2_X[12]), .B1(n5466),
.Y(n2857) );
AO22XLTS U6619 ( .A0(n5364), .A1(d_ff2_X[12]), .B0(n5363), .B1(
d_ff3_sh_x_out[12]), .Y(n2856) );
OA22X1TS U6620 ( .A0(n5365), .A1(d_ff2_X[13]), .B0(d_ff_Xn[13]), .B1(n5423),
.Y(n2855) );
AO22XLTS U6621 ( .A0(n5364), .A1(d_ff2_X[13]), .B0(n5363), .B1(
d_ff3_sh_x_out[13]), .Y(n2854) );
OA22X1TS U6622 ( .A0(n6246), .A1(d_ff2_X[14]), .B0(d_ff_Xn[14]), .B1(n5423),
.Y(n2853) );
AO22XLTS U6623 ( .A0(n5364), .A1(d_ff2_X[14]), .B0(n5363), .B1(
d_ff3_sh_x_out[14]), .Y(n2852) );
AO22XLTS U6624 ( .A0(d_ff_Xn[15]), .A1(n5367), .B0(d_ff2_X[15]), .B1(n5466),
.Y(n2851) );
AO22XLTS U6625 ( .A0(n5368), .A1(d_ff2_X[15]), .B0(n5363), .B1(
d_ff3_sh_x_out[15]), .Y(n2850) );
AO22XLTS U6626 ( .A0(d_ff_Xn[16]), .A1(n5367), .B0(d_ff2_X[16]), .B1(n5466),
.Y(n2849) );
AO22XLTS U6627 ( .A0(n5364), .A1(d_ff2_X[16]), .B0(n5366), .B1(
d_ff3_sh_x_out[16]), .Y(n2848) );
AO22XLTS U6628 ( .A0(d_ff_Xn[17]), .A1(n5367), .B0(d_ff2_X[17]), .B1(n5466),
.Y(n2847) );
AO22XLTS U6629 ( .A0(n5368), .A1(d_ff2_X[17]), .B0(n5366), .B1(
d_ff3_sh_x_out[17]), .Y(n2846) );
AO22XLTS U6630 ( .A0(d_ff_Xn[18]), .A1(n5367), .B0(d_ff2_X[18]), .B1(n5466),
.Y(n2845) );
AO22XLTS U6631 ( .A0(n5368), .A1(d_ff2_X[18]), .B0(n5366), .B1(
d_ff3_sh_x_out[18]), .Y(n2844) );
OA22X1TS U6632 ( .A0(n5365), .A1(d_ff2_X[19]), .B0(d_ff_Xn[19]), .B1(n5423),
.Y(n2843) );
AO22XLTS U6633 ( .A0(n5368), .A1(d_ff2_X[19]), .B0(n5366), .B1(
d_ff3_sh_x_out[19]), .Y(n2842) );
AO22XLTS U6634 ( .A0(d_ff_Xn[20]), .A1(n5367), .B0(d_ff2_X[20]), .B1(n5405),
.Y(n2841) );
AO22XLTS U6635 ( .A0(n5368), .A1(d_ff2_X[20]), .B0(n5366), .B1(
d_ff3_sh_x_out[20]), .Y(n2840) );
AO22XLTS U6636 ( .A0(d_ff_Xn[21]), .A1(n5367), .B0(d_ff2_X[21]), .B1(n5372),
.Y(n2839) );
AO22XLTS U6637 ( .A0(n5368), .A1(d_ff2_X[21]), .B0(n5366), .B1(
d_ff3_sh_x_out[21]), .Y(n2838) );
AO22XLTS U6638 ( .A0(d_ff_Xn[22]), .A1(n5367), .B0(d_ff2_X[22]), .B1(n5372),
.Y(n2837) );
AO22XLTS U6639 ( .A0(n5368), .A1(d_ff2_X[22]), .B0(n5366), .B1(
d_ff3_sh_x_out[22]), .Y(n2836) );
AO22XLTS U6640 ( .A0(d_ff_Xn[23]), .A1(n5367), .B0(d_ff2_X[23]), .B1(n5372),
.Y(n2835) );
CLKBUFX2TS U6641 ( .A(n5374), .Y(n5426) );
INVX2TS U6642 ( .A(n5426), .Y(n5371) );
AO22XLTS U6643 ( .A0(n5371), .A1(d_ff2_X[23]), .B0(n5366), .B1(
d_ff3_sh_x_out[23]), .Y(n2834) );
OA22X1TS U6644 ( .A0(n5365), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n5423),
.Y(n2833) );
AO22XLTS U6645 ( .A0(n5368), .A1(d_ff2_X[24]), .B0(n5366), .B1(
d_ff3_sh_x_out[24]), .Y(n2832) );
AO22XLTS U6646 ( .A0(d_ff_Xn[25]), .A1(n5367), .B0(d_ff2_X[25]), .B1(n5372),
.Y(n2831) );
AO22XLTS U6647 ( .A0(n5371), .A1(d_ff2_X[25]), .B0(n5369), .B1(
d_ff3_sh_x_out[25]), .Y(n2830) );
AO22XLTS U6648 ( .A0(n5368), .A1(d_ff2_X[26]), .B0(n5369), .B1(
d_ff3_sh_x_out[26]), .Y(n2828) );
AO22XLTS U6649 ( .A0(d_ff_Xn[27]), .A1(n5377), .B0(d_ff2_X[27]), .B1(n5372),
.Y(n2827) );
AO22XLTS U6650 ( .A0(n5371), .A1(d_ff2_X[27]), .B0(n5369), .B1(
d_ff3_sh_x_out[27]), .Y(n2826) );
AO22XLTS U6651 ( .A0(n5371), .A1(d_ff2_X[28]), .B0(n5369), .B1(
d_ff3_sh_x_out[28]), .Y(n2824) );
CLKBUFX2TS U6652 ( .A(n5374), .Y(n5452) );
INVX2TS U6653 ( .A(n5452), .Y(n5375) );
AO22XLTS U6654 ( .A0(n5375), .A1(d_ff2_X[29]), .B0(n5370), .B1(
d_ff3_sh_x_out[29]), .Y(n2822) );
AO22XLTS U6655 ( .A0(d_ff_Xn[30]), .A1(n5377), .B0(d_ff2_X[30]), .B1(n5372),
.Y(n2821) );
AO22XLTS U6656 ( .A0(n5371), .A1(d_ff2_X[30]), .B0(n5370), .B1(
d_ff3_sh_x_out[30]), .Y(n2820) );
AO22XLTS U6657 ( .A0(n5371), .A1(d_ff2_X[31]), .B0(n5370), .B1(
d_ff3_sh_x_out[31]), .Y(n2818) );
AO22XLTS U6658 ( .A0(n5371), .A1(d_ff2_X[32]), .B0(n5370), .B1(
d_ff3_sh_x_out[32]), .Y(n2816) );
AO22XLTS U6659 ( .A0(d_ff_Xn[33]), .A1(n5420), .B0(d_ff2_X[33]), .B1(n5372),
.Y(n2815) );
AO22XLTS U6660 ( .A0(n5371), .A1(d_ff2_X[33]), .B0(n5370), .B1(
d_ff3_sh_x_out[33]), .Y(n2814) );
AO22XLTS U6661 ( .A0(n5371), .A1(d_ff2_X[34]), .B0(n5373), .B1(
d_ff3_sh_x_out[34]), .Y(n2812) );
AO22XLTS U6662 ( .A0(n5375), .A1(d_ff2_X[35]), .B0(n5373), .B1(
d_ff3_sh_x_out[35]), .Y(n2810) );
OA22X1TS U6663 ( .A0(n5376), .A1(d_ff2_X[36]), .B0(d_ff_Xn[36]), .B1(n5382),
.Y(n2809) );
AO22XLTS U6664 ( .A0(n5371), .A1(d_ff2_X[36]), .B0(n5373), .B1(
d_ff3_sh_x_out[36]), .Y(n2808) );
AO22XLTS U6665 ( .A0(d_ff_Xn[37]), .A1(n5377), .B0(d_ff2_X[37]), .B1(n5372),
.Y(n2807) );
AO22XLTS U6666 ( .A0(n5375), .A1(d_ff2_X[37]), .B0(n5373), .B1(
d_ff3_sh_x_out[37]), .Y(n2806) );
AO22XLTS U6667 ( .A0(d_ff_Xn[38]), .A1(n5377), .B0(d_ff2_X[38]), .B1(n5372),
.Y(n2805) );
AO22XLTS U6668 ( .A0(n5375), .A1(d_ff2_X[38]), .B0(n5373), .B1(
d_ff3_sh_x_out[38]), .Y(n2804) );
OA22X1TS U6669 ( .A0(n5376), .A1(d_ff2_X[39]), .B0(d_ff_Xn[39]), .B1(n5491),
.Y(n2803) );
AO22XLTS U6670 ( .A0(n5375), .A1(d_ff2_X[39]), .B0(n5373), .B1(
d_ff3_sh_x_out[39]), .Y(n2802) );
AO22XLTS U6671 ( .A0(d_ff_Xn[40]), .A1(n5377), .B0(d_ff2_X[40]), .B1(n5513),
.Y(n2801) );
AO22XLTS U6672 ( .A0(n5375), .A1(d_ff2_X[40]), .B0(n5373), .B1(
d_ff3_sh_x_out[40]), .Y(n2800) );
OA22X1TS U6673 ( .A0(n5376), .A1(d_ff2_X[41]), .B0(d_ff_Xn[41]), .B1(n5491),
.Y(n2799) );
AO22XLTS U6674 ( .A0(n5390), .A1(d_ff2_X[41]), .B0(n5373), .B1(
d_ff3_sh_x_out[41]), .Y(n2798) );
OA22X1TS U6675 ( .A0(n5376), .A1(d_ff2_X[42]), .B0(d_ff_Xn[42]), .B1(n5378),
.Y(n2797) );
AO22XLTS U6676 ( .A0(n5375), .A1(d_ff2_X[42]), .B0(n5373), .B1(
d_ff3_sh_x_out[42]), .Y(n2796) );
OA22X1TS U6677 ( .A0(n5376), .A1(d_ff2_X[43]), .B0(d_ff_Xn[43]), .B1(n5378),
.Y(n2795) );
CLKBUFX2TS U6678 ( .A(n5374), .Y(n5483) );
AO22XLTS U6679 ( .A0(n5375), .A1(d_ff2_X[43]), .B0(n5483), .B1(
d_ff3_sh_x_out[43]), .Y(n2794) );
AO22XLTS U6680 ( .A0(d_ff_Xn[44]), .A1(n5377), .B0(d_ff2_X[44]), .B1(n5515),
.Y(n2793) );
AO22XLTS U6681 ( .A0(n5375), .A1(d_ff2_X[44]), .B0(n5483), .B1(
d_ff3_sh_x_out[44]), .Y(n2792) );
OA22X1TS U6682 ( .A0(n5376), .A1(d_ff2_X[45]), .B0(d_ff_Xn[45]), .B1(n5378),
.Y(n2791) );
AO22XLTS U6683 ( .A0(n5390), .A1(d_ff2_X[45]), .B0(n5483), .B1(
d_ff3_sh_x_out[45]), .Y(n2790) );
OA22X1TS U6684 ( .A0(n5376), .A1(d_ff2_X[46]), .B0(d_ff_Xn[46]), .B1(n5378),
.Y(n2789) );
AO22XLTS U6685 ( .A0(n5375), .A1(d_ff2_X[46]), .B0(n5483), .B1(
d_ff3_sh_x_out[46]), .Y(n2788) );
AO22XLTS U6686 ( .A0(d_ff_Xn[47]), .A1(n5377), .B0(d_ff2_X[47]), .B1(n5405),
.Y(n2787) );
AO22XLTS U6687 ( .A0(n5390), .A1(d_ff2_X[47]), .B0(n5483), .B1(
d_ff3_sh_x_out[47]), .Y(n2786) );
OA22X1TS U6688 ( .A0(n5376), .A1(d_ff2_X[48]), .B0(d_ff_Xn[48]), .B1(n5491),
.Y(n2785) );
AO22XLTS U6689 ( .A0(n5390), .A1(d_ff2_X[48]), .B0(n5483), .B1(
d_ff3_sh_x_out[48]), .Y(n2784) );
OA22X1TS U6690 ( .A0(n5376), .A1(d_ff2_X[49]), .B0(d_ff_Xn[49]), .B1(n5491),
.Y(n2783) );
AO22XLTS U6691 ( .A0(n5390), .A1(d_ff2_X[49]), .B0(n5483), .B1(
d_ff3_sh_x_out[49]), .Y(n2782) );
AO22XLTS U6692 ( .A0(d_ff_Xn[50]), .A1(n5377), .B0(d_ff2_X[50]), .B1(n5405),
.Y(n2781) );
AO22XLTS U6693 ( .A0(n5390), .A1(d_ff2_X[50]), .B0(n5483), .B1(
d_ff3_sh_x_out[50]), .Y(n2780) );
AO22XLTS U6694 ( .A0(d_ff_Xn[51]), .A1(n5377), .B0(d_ff2_X[51]), .B1(n5405),
.Y(n2779) );
AO22XLTS U6695 ( .A0(n5390), .A1(d_ff2_X[51]), .B0(n5483), .B1(
d_ff3_sh_x_out[51]), .Y(n2778) );
AO22XLTS U6696 ( .A0(d_ff2_X[52]), .A1(n5518), .B0(d_ff_Xn[52]), .B1(n5517),
.Y(n2777) );
OA22X1TS U6697 ( .A0(n5435), .A1(d_ff2_X[53]), .B0(d_ff_Xn[53]), .B1(n5491),
.Y(n2776) );
OA22X1TS U6698 ( .A0(n5435), .A1(d_ff2_X[54]), .B0(d_ff_Xn[54]), .B1(n5378),
.Y(n2775) );
OA22X1TS U6699 ( .A0(n5379), .A1(d_ff2_X[55]), .B0(d_ff_Xn[55]), .B1(n5380),
.Y(n2774) );
OA22X1TS U6700 ( .A0(n5379), .A1(d_ff2_X[56]), .B0(d_ff_Xn[56]), .B1(n5423),
.Y(n2773) );
OA22X1TS U6701 ( .A0(n5412), .A1(d_ff2_X[57]), .B0(d_ff_Xn[57]), .B1(n5411),
.Y(n2772) );
OA22X1TS U6702 ( .A0(n5412), .A1(d_ff2_X[59]), .B0(d_ff_Xn[59]), .B1(n5411),
.Y(n2770) );
OA22X1TS U6703 ( .A0(n5435), .A1(d_ff2_X[61]), .B0(d_ff_Xn[61]), .B1(n5382),
.Y(n2768) );
AO22XLTS U6704 ( .A0(d_ff_Xn[62]), .A1(n5420), .B0(d_ff2_X[62]), .B1(n5405),
.Y(n2767) );
OAI21XLTS U6705 ( .A0(n3196), .A1(n5938), .B0(intadd_24_CI), .Y(n5383) );
AO22XLTS U6706 ( .A0(n5390), .A1(n5383), .B0(n5751), .B1(d_ff3_sh_x_out[52]),
.Y(n2766) );
NOR2XLTS U6707 ( .A(d_ff2_X[56]), .B(intadd_24_n1), .Y(n5385) );
AOI21X1TS U6708 ( .A0(intadd_24_n1), .A1(d_ff2_X[56]), .B0(n5385), .Y(n5384)
);
AOI2BB2XLTS U6709 ( .B0(n5549), .B1(n5384), .A0N(d_ff3_sh_x_out[56]), .A1N(
n5537), .Y(n2762) );
INVX2TS U6710 ( .A(n5385), .Y(n5386) );
NOR3XLTS U6711 ( .A(d_ff2_X[57]), .B(d_ff2_X[56]), .C(intadd_24_n1), .Y(
n5388) );
AOI21X1TS U6712 ( .A0(d_ff2_X[57]), .A1(n5386), .B0(n5388), .Y(n5387) );
AOI2BB2XLTS U6713 ( .B0(n5549), .B1(n5387), .A0N(d_ff3_sh_x_out[57]), .A1N(
n5537), .Y(n2761) );
NAND2X1TS U6714 ( .A(n5388), .B(n6018), .Y(n5391) );
AO22XLTS U6715 ( .A0(n5390), .A1(n5389), .B0(n5475), .B1(d_ff3_sh_x_out[58]),
.Y(n2760) );
AOI21X1TS U6716 ( .A0(d_ff2_X[59]), .A1(n5391), .B0(n5393), .Y(n5392) );
NAND2X1TS U6717 ( .A(n5393), .B(n6019), .Y(n5395) );
AO22XLTS U6718 ( .A0(n5752), .A1(n5394), .B0(n5741), .B1(d_ff3_sh_x_out[60]),
.Y(n2758) );
AOI21X1TS U6719 ( .A0(d_ff2_X[61]), .A1(n5395), .B0(n5397), .Y(n5396) );
AO22XLTS U6720 ( .A0(n5750), .A1(d_ff_Xn[63]), .B0(d_ff2_X[63]), .B1(n5405),
.Y(n2755) );
AO22XLTS U6721 ( .A0(n5752), .A1(d_ff2_X[63]), .B0(n5741), .B1(
d_ff3_sh_x_out[63]), .Y(n2754) );
CLKBUFX2TS U6722 ( .A(n5677), .Y(n5736) );
AOI22X1TS U6723 ( .A0(n5736), .A1(d_ff2_Y[63]), .B0(d_ff2_Z[63]), .B1(n5413),
.Y(n5400) );
AOI22X1TS U6724 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[63]), .A1(n5743), .B0(n5737), .B1(d_ff2_X[63]), .Y(n5399) );
NAND2X1TS U6725 ( .A(n5400), .B(n5399), .Y(n2753) );
AO22XLTS U6726 ( .A0(n5571), .A1(result_add_subt[63]), .B0(n5570), .B1(
d_ff_Zn[63]), .Y(n2752) );
AO22XLTS U6727 ( .A0(n5572), .A1(result_add_subt[63]), .B0(n5568), .B1(
d_ff_Yn[63]), .Y(n2751) );
AO22XLTS U6728 ( .A0(d_ff_Yn[0]), .A1(n5420), .B0(d_ff2_Y[0]), .B1(n5405),
.Y(n2750) );
AO22XLTS U6729 ( .A0(n5752), .A1(d_ff2_Y[0]), .B0(n5426), .B1(
d_ff3_sh_y_out[0]), .Y(n2749) );
CLKBUFX2TS U6730 ( .A(n5712), .Y(n5731) );
AOI22X1TS U6731 ( .A0(n5731), .A1(d_ff3_sh_y_out[0]), .B0(n5413), .B1(
d_ff3_LUT_out[0]), .Y(n5402) );
AOI22X1TS U6732 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .A1(n5743),
.B0(n5672), .B1(d_ff3_sh_x_out[0]), .Y(n5401) );
NAND2X1TS U6733 ( .A(n5402), .B(n5401), .Y(n2748) );
AO22XLTS U6734 ( .A0(d_ff_Yn[1]), .A1(n5420), .B0(d_ff2_Y[1]), .B1(n5405),
.Y(n2747) );
AO22XLTS U6735 ( .A0(n5752), .A1(d_ff2_Y[1]), .B0(n5426), .B1(
d_ff3_sh_y_out[1]), .Y(n2746) );
CLKBUFX2TS U6736 ( .A(n5712), .Y(n5477) );
AOI22X1TS U6737 ( .A0(n5477), .A1(d_ff3_sh_y_out[1]), .B0(n5413), .B1(
d_ff3_LUT_out[1]), .Y(n5404) );
AOI22X1TS U6738 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .A1(n5743),
.B0(n5430), .B1(d_ff3_sh_x_out[1]), .Y(n5403) );
NAND2X1TS U6739 ( .A(n5404), .B(n5403), .Y(n2745) );
AO22XLTS U6740 ( .A0(d_ff_Yn[2]), .A1(n5420), .B0(d_ff2_Y[2]), .B1(n5405),
.Y(n2744) );
CLKBUFX2TS U6741 ( .A(n5406), .Y(n5506) );
INVX2TS U6742 ( .A(n5506), .Y(n5436) );
AO22XLTS U6743 ( .A0(n5436), .A1(d_ff2_Y[2]), .B0(n5741), .B1(
d_ff3_sh_y_out[2]), .Y(n2743) );
AOI22X1TS U6744 ( .A0(n5477), .A1(d_ff3_sh_y_out[2]), .B0(n5413), .B1(
d_ff3_LUT_out[2]), .Y(n5408) );
AOI22X1TS U6745 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .A1(n5743),
.B0(n5430), .B1(d_ff3_sh_x_out[2]), .Y(n5407) );
NAND2X1TS U6746 ( .A(n5408), .B(n5407), .Y(n2742) );
AO22XLTS U6747 ( .A0(d_ff_Yn[3]), .A1(n5420), .B0(d_ff2_Y[3]), .B1(n5460),
.Y(n2741) );
AO22XLTS U6748 ( .A0(n5436), .A1(d_ff2_Y[3]), .B0(n5741), .B1(
d_ff3_sh_y_out[3]), .Y(n2740) );
AOI22X1TS U6749 ( .A0(n5736), .A1(d_ff3_sh_x_out[3]), .B0(n5455), .B1(
d_ff3_LUT_out[3]), .Y(n5410) );
CLKBUFX2TS U6750 ( .A(n5737), .Y(n5700) );
AOI22X1TS U6751 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .A1(n5442),
.B0(n5700), .B1(d_ff3_sh_y_out[3]), .Y(n5409) );
NAND2X1TS U6752 ( .A(n5410), .B(n5409), .Y(n2739) );
AO22XLTS U6753 ( .A0(d_ff_Yn[4]), .A1(n5420), .B0(d_ff2_Y[4]), .B1(n5460),
.Y(n2738) );
AO22XLTS U6754 ( .A0(n5752), .A1(d_ff2_Y[4]), .B0(n5426), .B1(
d_ff3_sh_y_out[4]), .Y(n2737) );
INVX2TS U6755 ( .A(n5411), .Y(n5480) );
AO22XLTS U6756 ( .A0(d_ff_Yn[5]), .A1(n5480), .B0(d_ff2_Y[5]), .B1(n5749),
.Y(n2735) );
AO22XLTS U6757 ( .A0(n5436), .A1(d_ff2_Y[5]), .B0(n5426), .B1(
d_ff3_sh_y_out[5]), .Y(n2734) );
AOI22X1TS U6758 ( .A0(n5477), .A1(d_ff3_sh_y_out[5]), .B0(n5413), .B1(
d_ff3_LUT_out[5]), .Y(n5415) );
AOI22X1TS U6759 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .A1(n5442),
.B0(n5430), .B1(d_ff3_sh_x_out[5]), .Y(n5414) );
NAND2X1TS U6760 ( .A(n5415), .B(n5414), .Y(n2733) );
AO22XLTS U6761 ( .A0(d_ff_Yn[6]), .A1(n5420), .B0(d_ff2_Y[6]), .B1(n5749),
.Y(n2732) );
AO22XLTS U6762 ( .A0(n5436), .A1(d_ff2_Y[6]), .B0(n5426), .B1(
d_ff3_sh_y_out[6]), .Y(n2731) );
AOI22X1TS U6763 ( .A0(n5736), .A1(d_ff3_sh_x_out[6]), .B0(n5455), .B1(
d_ff3_LUT_out[6]), .Y(n5417) );
AOI22X1TS U6764 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .A1(n5442),
.B0(n5700), .B1(d_ff3_sh_y_out[6]), .Y(n5416) );
NAND2X1TS U6765 ( .A(n5417), .B(n5416), .Y(n2730) );
AO22XLTS U6766 ( .A0(d_ff_Yn[7]), .A1(n5420), .B0(d_ff2_Y[7]), .B1(n5513),
.Y(n2729) );
AO22XLTS U6767 ( .A0(n5436), .A1(d_ff2_Y[7]), .B0(n5426), .B1(
d_ff3_sh_y_out[7]), .Y(n2728) );
AOI22X1TS U6768 ( .A0(n5477), .A1(d_ff3_sh_y_out[7]), .B0(n5430), .B1(
d_ff3_sh_x_out[7]), .Y(n5419) );
CLKBUFX2TS U6769 ( .A(n5461), .Y(n5732) );
AOI22X1TS U6770 ( .A0(d_ff3_LUT_out[7]), .A1(n5732), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .B1(n5743), .Y(n5418) );
NAND2X1TS U6771 ( .A(n5419), .B(n5418), .Y(n2727) );
AO22XLTS U6772 ( .A0(d_ff_Yn[8]), .A1(n5420), .B0(d_ff2_Y[8]), .B1(n5749),
.Y(n2726) );
AO22XLTS U6773 ( .A0(n5436), .A1(d_ff2_Y[8]), .B0(n5426), .B1(
d_ff3_sh_y_out[8]), .Y(n2725) );
AOI22X1TS U6774 ( .A0(n5736), .A1(d_ff3_sh_x_out[8]), .B0(n5461), .B1(
d_ff3_LUT_out[8]), .Y(n5422) );
AOI22X1TS U6775 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .A1(n5442),
.B0(n5700), .B1(d_ff3_sh_y_out[8]), .Y(n5421) );
NAND2X1TS U6776 ( .A(n5422), .B(n5421), .Y(n2724) );
AO22XLTS U6777 ( .A0(d_ff_Yn[9]), .A1(n5449), .B0(d_ff2_Y[9]), .B1(n5749),
.Y(n2723) );
AO22XLTS U6778 ( .A0(n5436), .A1(d_ff2_Y[9]), .B0(n5426), .B1(
d_ff3_sh_y_out[9]), .Y(n2722) );
AOI22X1TS U6779 ( .A0(n5477), .A1(d_ff3_sh_y_out[9]), .B0(n5455), .B1(
d_ff3_LUT_out[9]), .Y(n5425) );
AOI22X1TS U6780 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .A1(n5442),
.B0(n5430), .B1(d_ff3_sh_x_out[9]), .Y(n5424) );
NAND2X1TS U6781 ( .A(n5425), .B(n5424), .Y(n2721) );
AO22XLTS U6782 ( .A0(d_ff_Yn[10]), .A1(n5449), .B0(d_ff2_Y[10]), .B1(n5749),
.Y(n2720) );
AO22XLTS U6783 ( .A0(n5436), .A1(d_ff2_Y[10]), .B0(n5426), .B1(
d_ff3_sh_y_out[10]), .Y(n2719) );
CLKBUFX2TS U6784 ( .A(n5427), .Y(n5467) );
AOI22X1TS U6785 ( .A0(n5493), .A1(d_ff3_sh_y_out[10]), .B0(n5467), .B1(
d_ff3_sh_x_out[10]), .Y(n5429) );
CLKBUFX2TS U6786 ( .A(n5461), .Y(n5488) );
AOI22X1TS U6787 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .A1(n5442), .B0(n5488), .B1(d_ff3_LUT_out[10]), .Y(n5428) );
NAND2X1TS U6788 ( .A(n5429), .B(n5428), .Y(n2718) );
AO22XLTS U6789 ( .A0(d_ff_Yn[11]), .A1(n5449), .B0(d_ff2_Y[11]), .B1(n5749),
.Y(n2717) );
AO22XLTS U6790 ( .A0(n5436), .A1(d_ff2_Y[11]), .B0(n5452), .B1(
d_ff3_sh_y_out[11]), .Y(n2716) );
AOI22X1TS U6791 ( .A0(d_ff3_LUT_out[11]), .A1(n5732), .B0(n5700), .B1(
d_ff3_sh_y_out[11]), .Y(n5432) );
AOI22X1TS U6792 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .A1(n5442), .B0(n5430), .B1(d_ff3_sh_x_out[11]), .Y(n5431) );
NAND2X1TS U6793 ( .A(n5432), .B(n5431), .Y(n2715) );
AO22XLTS U6794 ( .A0(d_ff_Yn[12]), .A1(n5449), .B0(d_ff2_Y[12]), .B1(n5749),
.Y(n2714) );
INVX2TS U6795 ( .A(n5520), .Y(n5476) );
AO22XLTS U6796 ( .A0(n5476), .A1(d_ff2_Y[12]), .B0(n5452), .B1(
d_ff3_sh_y_out[12]), .Y(n2713) );
AOI22X1TS U6797 ( .A0(n5736), .A1(d_ff3_sh_x_out[12]), .B0(n5455), .B1(
d_ff3_LUT_out[12]), .Y(n5434) );
AOI22X1TS U6798 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .A1(n5442), .B0(n5737), .B1(d_ff3_sh_y_out[12]), .Y(n5433) );
NAND2X1TS U6799 ( .A(n5434), .B(n5433), .Y(n2712) );
AO22XLTS U6800 ( .A0(d_ff_Yn[13]), .A1(n5449), .B0(d_ff2_Y[13]), .B1(n5486),
.Y(n2711) );
AO22XLTS U6801 ( .A0(n5436), .A1(d_ff2_Y[13]), .B0(n5452), .B1(
d_ff3_sh_y_out[13]), .Y(n2710) );
AOI22X1TS U6802 ( .A0(n5477), .A1(d_ff3_sh_y_out[13]), .B0(n5467), .B1(
d_ff3_sh_x_out[13]), .Y(n5438) );
AOI22X1TS U6803 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .A1(n5442), .B0(n5488), .B1(d_ff3_LUT_out[13]), .Y(n5437) );
NAND2X1TS U6804 ( .A(n5438), .B(n5437), .Y(n2709) );
AO22XLTS U6805 ( .A0(d_ff_Yn[14]), .A1(n5449), .B0(d_ff2_Y[14]), .B1(n5486),
.Y(n2708) );
AO22XLTS U6806 ( .A0(n5476), .A1(d_ff2_Y[14]), .B0(n5452), .B1(
d_ff3_sh_y_out[14]), .Y(n2707) );
AOI22X1TS U6807 ( .A0(n5477), .A1(d_ff3_sh_y_out[14]), .B0(n5455), .B1(
d_ff3_LUT_out[14]), .Y(n5441) );
AOI22X1TS U6808 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .A1(n5468), .B0(n5467), .B1(d_ff3_sh_x_out[14]), .Y(n5440) );
NAND2X1TS U6809 ( .A(n5441), .B(n5440), .Y(n2706) );
AO22XLTS U6810 ( .A0(d_ff_Yn[15]), .A1(n5449), .B0(d_ff2_Y[15]), .B1(n5460),
.Y(n2705) );
AO22XLTS U6811 ( .A0(n5476), .A1(d_ff2_Y[15]), .B0(n5452), .B1(
d_ff3_sh_y_out[15]), .Y(n2704) );
AOI22X1TS U6812 ( .A0(d_ff3_LUT_out[15]), .A1(n5732), .B0(n5700), .B1(
d_ff3_sh_y_out[15]), .Y(n5444) );
AOI22X1TS U6813 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .A1(n5442), .B0(n5467), .B1(d_ff3_sh_x_out[15]), .Y(n5443) );
NAND2X1TS U6814 ( .A(n5444), .B(n5443), .Y(n2703) );
AO22XLTS U6815 ( .A0(d_ff_Yn[16]), .A1(n5449), .B0(d_ff2_Y[16]), .B1(n5460),
.Y(n2702) );
AO22XLTS U6816 ( .A0(n5476), .A1(d_ff2_Y[16]), .B0(n5452), .B1(
d_ff3_sh_y_out[16]), .Y(n2701) );
AOI22X1TS U6817 ( .A0(n5500), .A1(d_ff3_sh_y_out[16]), .B0(n5467), .B1(
d_ff3_sh_x_out[16]), .Y(n5446) );
AOI22X1TS U6818 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .A1(n5468), .B0(n5461), .B1(d_ff3_LUT_out[16]), .Y(n5445) );
NAND2X1TS U6819 ( .A(n5446), .B(n5445), .Y(n2700) );
AO22XLTS U6820 ( .A0(d_ff_Yn[17]), .A1(n5449), .B0(d_ff2_Y[17]), .B1(n5460),
.Y(n2699) );
AO22XLTS U6821 ( .A0(n5476), .A1(d_ff2_Y[17]), .B0(n5452), .B1(
d_ff3_sh_y_out[17]), .Y(n2698) );
CLKBUFX2TS U6822 ( .A(n5677), .Y(n5708) );
AOI22X1TS U6823 ( .A0(n5708), .A1(d_ff3_sh_x_out[17]), .B0(n5455), .B1(
d_ff3_LUT_out[17]), .Y(n5448) );
AOI22X1TS U6824 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .A1(n5468), .B0(n5663), .B1(d_ff3_sh_y_out[17]), .Y(n5447) );
NAND2X1TS U6825 ( .A(n5448), .B(n5447), .Y(n2697) );
AO22XLTS U6826 ( .A0(d_ff_Yn[18]), .A1(n5449), .B0(d_ff2_Y[18]), .B1(n5460),
.Y(n2696) );
AO22XLTS U6827 ( .A0(n5476), .A1(d_ff2_Y[18]), .B0(n5452), .B1(
d_ff3_sh_y_out[18]), .Y(n2695) );
AOI22X1TS U6828 ( .A0(n5493), .A1(d_ff3_sh_y_out[18]), .B0(n5488), .B1(
d_ff3_LUT_out[18]), .Y(n5451) );
AOI22X1TS U6829 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .A1(n5468), .B0(n5467), .B1(d_ff3_sh_x_out[18]), .Y(n5450) );
NAND2X1TS U6830 ( .A(n5451), .B(n5450), .Y(n2694) );
AO22XLTS U6831 ( .A0(d_ff_Yn[19]), .A1(n5480), .B0(d_ff2_Y[19]), .B1(n5460),
.Y(n2693) );
AO22XLTS U6832 ( .A0(n5476), .A1(d_ff2_Y[19]), .B0(n5452), .B1(
d_ff3_sh_y_out[19]), .Y(n2692) );
AOI22X1TS U6833 ( .A0(n5493), .A1(d_ff3_sh_y_out[19]), .B0(n5455), .B1(
d_ff3_LUT_out[19]), .Y(n5454) );
AOI22X1TS U6834 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .A1(n5468), .B0(n5467), .B1(d_ff3_sh_x_out[19]), .Y(n5453) );
NAND2X1TS U6835 ( .A(n5454), .B(n5453), .Y(n2691) );
AO22XLTS U6836 ( .A0(d_ff_Yn[20]), .A1(n5499), .B0(d_ff2_Y[20]), .B1(n5460),
.Y(n2690) );
INVX2TS U6837 ( .A(n5751), .Y(n5492) );
AO22XLTS U6838 ( .A0(n5492), .A1(d_ff2_Y[20]), .B0(n5475), .B1(
d_ff3_sh_y_out[20]), .Y(n2689) );
AOI22X1TS U6839 ( .A0(n5477), .A1(d_ff3_sh_y_out[20]), .B0(n5467), .B1(
d_ff3_sh_x_out[20]), .Y(n5457) );
AOI22X1TS U6840 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .A1(n5468), .B0(n5455), .B1(d_ff3_LUT_out[20]), .Y(n5456) );
NAND2X1TS U6841 ( .A(n5457), .B(n5456), .Y(n2688) );
AO22XLTS U6842 ( .A0(d_ff_Yn[21]), .A1(n5480), .B0(d_ff2_Y[21]), .B1(n5460),
.Y(n2687) );
AO22XLTS U6843 ( .A0(n5492), .A1(d_ff2_Y[21]), .B0(n5475), .B1(
d_ff3_sh_y_out[21]), .Y(n2686) );
AOI22X1TS U6844 ( .A0(n5500), .A1(d_ff3_sh_y_out[21]), .B0(n5467), .B1(
d_ff3_sh_x_out[21]), .Y(n5459) );
AOI22X1TS U6845 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .A1(n5468), .B0(n5488), .B1(d_ff3_LUT_out[21]), .Y(n5458) );
NAND2X1TS U6846 ( .A(n5459), .B(n5458), .Y(n2685) );
AO22XLTS U6847 ( .A0(d_ff_Yn[22]), .A1(n5480), .B0(d_ff2_Y[22]), .B1(n5460),
.Y(n2684) );
AO22XLTS U6848 ( .A0(n5476), .A1(d_ff2_Y[22]), .B0(n5475), .B1(
d_ff3_sh_y_out[22]), .Y(n2683) );
CLKBUFX2TS U6849 ( .A(n5461), .Y(n5524) );
AOI22X1TS U6850 ( .A0(n5708), .A1(d_ff3_sh_x_out[22]), .B0(n5524), .B1(
d_ff3_LUT_out[22]), .Y(n5463) );
AOI22X1TS U6851 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .A1(n5468), .B0(n5731), .B1(d_ff3_sh_y_out[22]), .Y(n5462) );
NAND2X1TS U6852 ( .A(n5463), .B(n5462), .Y(n2682) );
AO22XLTS U6853 ( .A0(d_ff_Yn[23]), .A1(n5480), .B0(d_ff2_Y[23]), .B1(n5466),
.Y(n2681) );
AO22XLTS U6854 ( .A0(n5492), .A1(d_ff2_Y[23]), .B0(n5475), .B1(
d_ff3_sh_y_out[23]), .Y(n2680) );
AOI22X1TS U6855 ( .A0(n5477), .A1(d_ff3_sh_y_out[23]), .B0(n5488), .B1(
d_ff3_LUT_out[23]), .Y(n5465) );
AOI22X1TS U6856 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .A1(n5468), .B0(n5487), .B1(d_ff3_sh_x_out[23]), .Y(n5464) );
NAND2X1TS U6857 ( .A(n5465), .B(n5464), .Y(n2679) );
AO22XLTS U6858 ( .A0(d_ff_Yn[24]), .A1(n5480), .B0(d_ff2_Y[24]), .B1(n5466),
.Y(n2678) );
AO22XLTS U6859 ( .A0(n5492), .A1(d_ff2_Y[24]), .B0(n5475), .B1(
d_ff3_sh_y_out[24]), .Y(n2677) );
AOI22X1TS U6860 ( .A0(n5493), .A1(d_ff3_sh_y_out[24]), .B0(n5467), .B1(
d_ff3_sh_x_out[24]), .Y(n5470) );
AOI22X1TS U6861 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .A1(n5468), .B0(n5488), .B1(d_ff3_LUT_out[24]), .Y(n5469) );
NAND2X1TS U6862 ( .A(n5470), .B(n5469), .Y(n2676) );
AO22XLTS U6863 ( .A0(d_ff_Yn[25]), .A1(n5480), .B0(d_ff2_Y[25]), .B1(n5486),
.Y(n2675) );
AO22XLTS U6864 ( .A0(n5476), .A1(d_ff2_Y[25]), .B0(n5475), .B1(
d_ff3_sh_y_out[25]), .Y(n2674) );
AOI22X1TS U6865 ( .A0(n5708), .A1(d_ff3_sh_x_out[25]), .B0(n5488), .B1(
d_ff3_LUT_out[25]), .Y(n5472) );
AOI22X1TS U6866 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .A1(n5503), .B0(n5731), .B1(d_ff3_sh_y_out[25]), .Y(n5471) );
NAND2X1TS U6867 ( .A(n5472), .B(n5471), .Y(n2673) );
AO22XLTS U6868 ( .A0(d_ff_Yn[26]), .A1(n5480), .B0(d_ff2_Y[26]), .B1(n5486),
.Y(n2672) );
AO22XLTS U6869 ( .A0(n5492), .A1(d_ff2_Y[26]), .B0(n5475), .B1(
d_ff3_sh_y_out[26]), .Y(n2671) );
AOI22X1TS U6870 ( .A0(d_ff3_LUT_out[26]), .A1(n5732), .B0(n5487), .B1(
d_ff3_sh_x_out[26]), .Y(n5474) );
AOI22X1TS U6871 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .A1(n5503), .B0(n5700), .B1(d_ff3_sh_y_out[26]), .Y(n5473) );
NAND2X1TS U6872 ( .A(n5474), .B(n5473), .Y(n2670) );
AO22XLTS U6873 ( .A0(d_ff_Yn[27]), .A1(n5480), .B0(d_ff2_Y[27]), .B1(n5486),
.Y(n2669) );
AO22XLTS U6874 ( .A0(n5476), .A1(d_ff2_Y[27]), .B0(n5475), .B1(
d_ff3_sh_y_out[27]), .Y(n2668) );
AOI22X1TS U6875 ( .A0(n5477), .A1(d_ff3_sh_y_out[27]), .B0(n5487), .B1(
d_ff3_sh_x_out[27]), .Y(n5479) );
AOI22X1TS U6876 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .A1(n5503), .B0(n5524), .B1(d_ff3_LUT_out[27]), .Y(n5478) );
NAND2X1TS U6877 ( .A(n5479), .B(n5478), .Y(n2667) );
AO22XLTS U6878 ( .A0(d_ff_Yn[28]), .A1(n5480), .B0(d_ff2_Y[28]), .B1(n5486),
.Y(n2666) );
AO22XLTS U6879 ( .A0(n5492), .A1(d_ff2_Y[28]), .B0(n5496), .B1(
d_ff3_sh_y_out[28]), .Y(n2665) );
AO22XLTS U6880 ( .A0(d_ff_Yn[29]), .A1(n5499), .B0(d_ff2_Y[29]), .B1(n5486),
.Y(n2663) );
AO22XLTS U6881 ( .A0(n5492), .A1(d_ff2_Y[29]), .B0(n5496), .B1(
d_ff3_sh_y_out[29]), .Y(n2662) );
AOI22X1TS U6882 ( .A0(n5708), .A1(d_ff3_sh_x_out[29]), .B0(n5488), .B1(
d_ff3_LUT_out[29]), .Y(n5482) );
AOI22X1TS U6883 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .A1(n5503), .B0(n5700), .B1(d_ff3_sh_y_out[29]), .Y(n5481) );
NAND2X1TS U6884 ( .A(n5482), .B(n5481), .Y(n2661) );
AO22XLTS U6885 ( .A0(d_ff_Yn[30]), .A1(n5499), .B0(d_ff2_Y[30]), .B1(n5486),
.Y(n2660) );
INVX2TS U6886 ( .A(n5483), .Y(n5514) );
AO22XLTS U6887 ( .A0(n5514), .A1(d_ff2_Y[30]), .B0(n5496), .B1(
d_ff3_sh_y_out[30]), .Y(n2659) );
AO22XLTS U6888 ( .A0(d_ff_Yn[31]), .A1(n5499), .B0(d_ff2_Y[31]), .B1(n5486),
.Y(n2657) );
AO22XLTS U6889 ( .A0(n5492), .A1(d_ff2_Y[31]), .B0(n5496), .B1(
d_ff3_sh_y_out[31]), .Y(n2656) );
AOI22X1TS U6890 ( .A0(n5493), .A1(d_ff3_sh_y_out[31]), .B0(n5487), .B1(
d_ff3_sh_x_out[31]), .Y(n5485) );
AOI22X1TS U6891 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .A1(n5503), .B0(n5488), .B1(d_ff3_LUT_out[31]), .Y(n5484) );
NAND2X1TS U6892 ( .A(n5485), .B(n5484), .Y(n2655) );
AO22XLTS U6893 ( .A0(d_ff_Yn[32]), .A1(n5499), .B0(d_ff2_Y[32]), .B1(n5486),
.Y(n2654) );
AO22XLTS U6894 ( .A0(n5514), .A1(d_ff2_Y[32]), .B0(n5496), .B1(
d_ff3_sh_y_out[32]), .Y(n2653) );
AO22XLTS U6895 ( .A0(d_ff_Yn[33]), .A1(n5499), .B0(d_ff2_Y[33]), .B1(n5513),
.Y(n2651) );
AO22XLTS U6896 ( .A0(n5514), .A1(d_ff2_Y[33]), .B0(n5496), .B1(
d_ff3_sh_y_out[33]), .Y(n2650) );
AOI22X1TS U6897 ( .A0(n5500), .A1(d_ff3_sh_y_out[33]), .B0(n5487), .B1(
d_ff3_sh_x_out[33]), .Y(n5490) );
AOI22X1TS U6898 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .A1(n5503), .B0(n5488), .B1(d_ff3_LUT_out[33]), .Y(n5489) );
NAND2X1TS U6899 ( .A(n5490), .B(n5489), .Y(n2649) );
AO22XLTS U6900 ( .A0(d_ff_Yn[34]), .A1(n5499), .B0(d_ff2_Y[34]), .B1(n5513),
.Y(n2648) );
AO22XLTS U6901 ( .A0(n5492), .A1(d_ff2_Y[34]), .B0(n5496), .B1(
d_ff3_sh_y_out[34]), .Y(n2647) );
AO22XLTS U6902 ( .A0(d_ff_Yn[35]), .A1(n5510), .B0(d_ff2_Y[35]), .B1(n5515),
.Y(n2645) );
AO22XLTS U6903 ( .A0(n5492), .A1(d_ff2_Y[35]), .B0(n5496), .B1(
d_ff3_sh_y_out[35]), .Y(n2644) );
AOI22X1TS U6904 ( .A0(n5493), .A1(d_ff3_sh_y_out[35]), .B0(n5507), .B1(
d_ff3_sh_x_out[35]), .Y(n5495) );
AOI22X1TS U6905 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .A1(n5503), .B0(n5524), .B1(d_ff3_LUT_out[35]), .Y(n5494) );
NAND2X1TS U6906 ( .A(n5495), .B(n5494), .Y(n2643) );
AO22XLTS U6907 ( .A0(d_ff_Yn[36]), .A1(n5499), .B0(d_ff2_Y[36]), .B1(n5515),
.Y(n2642) );
AO22XLTS U6908 ( .A0(n5514), .A1(d_ff2_Y[36]), .B0(n5496), .B1(
d_ff3_sh_y_out[36]), .Y(n2641) );
AO22XLTS U6909 ( .A0(d_ff_Yn[37]), .A1(n5499), .B0(d_ff2_Y[37]), .B1(n5515),
.Y(n2639) );
AO22XLTS U6910 ( .A0(n5752), .A1(d_ff2_Y[37]), .B0(n5506), .B1(
d_ff3_sh_y_out[37]), .Y(n2638) );
AOI22X1TS U6911 ( .A0(n5500), .A1(d_ff3_sh_y_out[37]), .B0(n5507), .B1(
d_ff3_sh_x_out[37]), .Y(n5498) );
AOI22X1TS U6912 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .A1(n5503), .B0(n5524), .B1(d_ff3_LUT_out[37]), .Y(n5497) );
NAND2X1TS U6913 ( .A(n5498), .B(n5497), .Y(n2637) );
AO22XLTS U6914 ( .A0(d_ff_Yn[38]), .A1(n5499), .B0(d_ff2_Y[38]), .B1(n5515),
.Y(n2636) );
AO22XLTS U6915 ( .A0(n5514), .A1(d_ff2_Y[38]), .B0(n5506), .B1(
d_ff3_sh_y_out[38]), .Y(n2635) );
AO22XLTS U6916 ( .A0(d_ff_Yn[39]), .A1(n5510), .B0(d_ff2_Y[39]), .B1(n5515),
.Y(n2633) );
AO22XLTS U6917 ( .A0(n5514), .A1(d_ff2_Y[39]), .B0(n5506), .B1(
d_ff3_sh_y_out[39]), .Y(n2632) );
AOI22X1TS U6918 ( .A0(n5500), .A1(d_ff3_sh_y_out[39]), .B0(n5507), .B1(
d_ff3_sh_x_out[39]), .Y(n5502) );
AOI22X1TS U6919 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .A1(n5503), .B0(n5524), .B1(d_ff3_LUT_out[39]), .Y(n5501) );
NAND2X1TS U6920 ( .A(n5502), .B(n5501), .Y(n2631) );
AO22XLTS U6921 ( .A0(d_ff_Yn[40]), .A1(n5510), .B0(d_ff2_Y[40]), .B1(n5515),
.Y(n2630) );
AO22XLTS U6922 ( .A0(n5514), .A1(d_ff2_Y[40]), .B0(n5506), .B1(
d_ff3_sh_y_out[40]), .Y(n2629) );
AO22XLTS U6923 ( .A0(d_ff_Yn[41]), .A1(n5510), .B0(d_ff2_Y[41]), .B1(n5515),
.Y(n2627) );
AO22XLTS U6924 ( .A0(n5541), .A1(d_ff2_Y[41]), .B0(n5506), .B1(
d_ff3_sh_y_out[41]), .Y(n2626) );
AOI22X1TS U6925 ( .A0(n5612), .A1(d_ff3_sh_y_out[41]), .B0(n5507), .B1(
d_ff3_sh_x_out[41]), .Y(n5505) );
AOI22X1TS U6926 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .A1(n5503), .B0(n5524), .B1(d_ff3_LUT_out[41]), .Y(n5504) );
NAND2X1TS U6927 ( .A(n5505), .B(n5504), .Y(n2625) );
AO22XLTS U6928 ( .A0(d_ff_Yn[42]), .A1(n5510), .B0(d_ff2_Y[42]), .B1(n5515),
.Y(n2624) );
AO22XLTS U6929 ( .A0(n5541), .A1(d_ff2_Y[42]), .B0(n5506), .B1(
d_ff3_sh_y_out[42]), .Y(n2623) );
AO22XLTS U6930 ( .A0(d_ff_Yn[43]), .A1(n5510), .B0(d_ff2_Y[43]), .B1(n5519),
.Y(n2621) );
AO22XLTS U6931 ( .A0(n5514), .A1(d_ff2_Y[43]), .B0(n5506), .B1(
d_ff3_sh_y_out[43]), .Y(n2620) );
AO22XLTS U6932 ( .A0(d_ff_Yn[44]), .A1(n5510), .B0(d_ff2_Y[44]), .B1(n5519),
.Y(n2618) );
AO22XLTS U6933 ( .A0(n5541), .A1(d_ff2_Y[44]), .B0(n5506), .B1(
d_ff3_sh_y_out[44]), .Y(n2617) );
AO22XLTS U6934 ( .A0(d_ff_Yn[45]), .A1(n5510), .B0(d_ff2_Y[45]), .B1(n5519),
.Y(n2615) );
AO22XLTS U6935 ( .A0(n5541), .A1(d_ff2_Y[45]), .B0(n5506), .B1(
d_ff3_sh_y_out[45]), .Y(n2614) );
AOI22X1TS U6936 ( .A0(n5612), .A1(d_ff3_sh_y_out[45]), .B0(n5507), .B1(
d_ff3_sh_x_out[45]), .Y(n5509) );
AOI22X1TS U6937 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .A1(n5582), .B0(n5524), .B1(d_ff3_LUT_out[45]), .Y(n5508) );
NAND2X1TS U6938 ( .A(n5509), .B(n5508), .Y(n2613) );
AO22XLTS U6939 ( .A0(d_ff_Yn[46]), .A1(n5510), .B0(d_ff2_Y[46]), .B1(n5513),
.Y(n2612) );
AO22XLTS U6940 ( .A0(n5514), .A1(d_ff2_Y[46]), .B0(n5520), .B1(
d_ff3_sh_y_out[46]), .Y(n2611) );
AO22XLTS U6941 ( .A0(d_ff_Yn[47]), .A1(n5510), .B0(d_ff2_Y[47]), .B1(n5513),
.Y(n2609) );
AO22XLTS U6942 ( .A0(n5541), .A1(d_ff2_Y[47]), .B0(n5520), .B1(
d_ff3_sh_y_out[47]), .Y(n2608) );
AO22XLTS U6943 ( .A0(d_ff_Yn[48]), .A1(n5516), .B0(d_ff2_Y[48]), .B1(n5513),
.Y(n2606) );
AO22XLTS U6944 ( .A0(n5541), .A1(d_ff2_Y[48]), .B0(n5520), .B1(
d_ff3_sh_y_out[48]), .Y(n2605) );
AO22XLTS U6945 ( .A0(d_ff_Yn[49]), .A1(n5516), .B0(d_ff2_Y[49]), .B1(n5513),
.Y(n2603) );
AO22XLTS U6946 ( .A0(n5541), .A1(d_ff2_Y[49]), .B0(n5520), .B1(
d_ff3_sh_y_out[49]), .Y(n2602) );
AO22XLTS U6947 ( .A0(d_ff_Yn[50]), .A1(n5516), .B0(d_ff2_Y[50]), .B1(n5513),
.Y(n2600) );
AO22XLTS U6948 ( .A0(n5742), .A1(d_ff2_Y[50]), .B0(n5520), .B1(
d_ff3_sh_y_out[50]), .Y(n2599) );
AOI22X1TS U6949 ( .A0(n5672), .A1(d_ff3_sh_x_out[50]), .B0(n5524), .B1(
d_ff3_LUT_out[50]), .Y(n5512) );
AOI22X1TS U6950 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .A1(n5582), .B0(n5731), .B1(d_ff3_sh_y_out[50]), .Y(n5511) );
NAND2X1TS U6951 ( .A(n5512), .B(n5511), .Y(n2598) );
AO22XLTS U6952 ( .A0(d_ff_Yn[51]), .A1(n5516), .B0(d_ff2_Y[51]), .B1(n5513),
.Y(n2597) );
AO22XLTS U6953 ( .A0(n5514), .A1(d_ff2_Y[51]), .B0(n5520), .B1(
d_ff3_sh_y_out[51]), .Y(n2596) );
AO22XLTS U6954 ( .A0(d_ff2_Y[52]), .A1(n5515), .B0(d_ff_Yn[52]), .B1(n5517),
.Y(n2594) );
AO22XLTS U6955 ( .A0(d_ff_Yn[53]), .A1(n5516), .B0(d_ff2_Y[53]), .B1(n5749),
.Y(n2593) );
AO22XLTS U6956 ( .A0(d_ff_Yn[54]), .A1(n5516), .B0(d_ff2_Y[54]), .B1(n5749),
.Y(n2592) );
AO22XLTS U6957 ( .A0(d_ff_Yn[55]), .A1(n5516), .B0(d_ff2_Y[55]), .B1(n5519),
.Y(n2591) );
AO22XLTS U6958 ( .A0(d_ff_Yn[56]), .A1(n5516), .B0(d_ff2_Y[56]), .B1(n5519),
.Y(n2590) );
AO22XLTS U6959 ( .A0(d_ff_Yn[57]), .A1(n5516), .B0(d_ff2_Y[57]), .B1(n5519),
.Y(n2589) );
AO22XLTS U6960 ( .A0(d_ff2_Y[58]), .A1(n5518), .B0(d_ff_Yn[58]), .B1(n5517),
.Y(n2588) );
AO22XLTS U6961 ( .A0(d_ff_Yn[59]), .A1(n5750), .B0(d_ff2_Y[59]), .B1(n5519),
.Y(n2587) );
AO22XLTS U6962 ( .A0(d_ff2_Y[60]), .A1(n5518), .B0(d_ff_Yn[60]), .B1(n5517),
.Y(n2586) );
AO22XLTS U6963 ( .A0(d_ff_Yn[61]), .A1(n5750), .B0(d_ff2_Y[61]), .B1(n5519),
.Y(n2585) );
AO22XLTS U6964 ( .A0(d_ff_Yn[62]), .A1(n5750), .B0(d_ff2_Y[62]), .B1(n5519),
.Y(n2584) );
OAI21XLTS U6965 ( .A0(n3196), .A1(n5937), .B0(intadd_23_CI), .Y(n5521) );
AO22XLTS U6966 ( .A0(n5541), .A1(n5521), .B0(n5520), .B1(d_ff3_sh_y_out[52]),
.Y(n2583) );
AOI22X1TS U6967 ( .A0(n5588), .A1(d_ff3_sh_y_out[52]), .B0(n5524), .B1(
d_ff3_LUT_out[52]), .Y(n5523) );
AOI22X1TS U6968 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .A1(n5582), .B0(n5527), .B1(d_ff3_sh_x_out[52]), .Y(n5522) );
NAND2X1TS U6969 ( .A(n5523), .B(n5522), .Y(n2582) );
AOI22X1TS U6970 ( .A0(n5588), .A1(d_ff3_sh_y_out[53]), .B0(n5527), .B1(
d_ff3_sh_x_out[53]), .Y(n5526) );
AOI22X1TS U6971 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .A1(n5582), .B0(n5524), .B1(d_ff3_LUT_out[53]), .Y(n5525) );
NAND2X1TS U6972 ( .A(n5526), .B(n5525), .Y(n2580) );
AOI22X1TS U6973 ( .A0(n5588), .A1(d_ff3_sh_y_out[54]), .B0(n5527), .B1(
d_ff3_sh_x_out[54]), .Y(n5529) );
CLKBUFX2TS U6974 ( .A(n5691), .Y(n5593) );
AOI22X1TS U6975 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .A1(n5582), .B0(n5593), .B1(d_ff3_LUT_out[54]), .Y(n5528) );
NAND2X1TS U6976 ( .A(n5529), .B(n5528), .Y(n2578) );
AOI22X1TS U6977 ( .A0(n5736), .A1(d_ff3_sh_x_out[55]), .B0(n5593), .B1(
d_ff3_LUT_out[55]), .Y(n5531) );
AOI22X1TS U6978 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .A1(n5582), .B0(n5731), .B1(d_ff3_sh_y_out[55]), .Y(n5530) );
NAND2X1TS U6979 ( .A(n5531), .B(n5530), .Y(n2576) );
NOR2XLTS U6980 ( .A(d_ff2_Y[56]), .B(intadd_23_n1), .Y(n5535) );
AOI21X1TS U6981 ( .A0(intadd_23_n1), .A1(d_ff2_Y[56]), .B0(n5535), .Y(n5532)
);
AOI2BB2XLTS U6982 ( .B0(n5549), .B1(n5532), .A0N(d_ff3_sh_y_out[56]), .A1N(
n5547), .Y(n2575) );
AOI22X1TS U6983 ( .A0(n5672), .A1(d_ff3_sh_x_out[56]), .B0(n5593), .B1(
d_ff3_LUT_out[56]), .Y(n5534) );
AOI22X1TS U6984 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .A1(n5582), .B0(n5663), .B1(d_ff3_sh_y_out[56]), .Y(n5533) );
NAND2X1TS U6985 ( .A(n5534), .B(n5533), .Y(n2574) );
INVX2TS U6986 ( .A(n5535), .Y(n5536) );
NOR3XLTS U6987 ( .A(d_ff2_Y[57]), .B(d_ff2_Y[56]), .C(intadd_23_n1), .Y(
n5539) );
AOI21X1TS U6988 ( .A0(d_ff2_Y[57]), .A1(n5536), .B0(n5539), .Y(n5538) );
AOI2BB2XLTS U6989 ( .B0(n5549), .B1(n5538), .A0N(d_ff3_sh_y_out[57]), .A1N(
n5537), .Y(n2573) );
NAND2X1TS U6990 ( .A(n5539), .B(n6026), .Y(n5542) );
AO22XLTS U6991 ( .A0(n5541), .A1(n5540), .B0(n5751), .B1(d_ff3_sh_y_out[58]),
.Y(n2571) );
AOI21X1TS U6992 ( .A0(d_ff2_Y[59]), .A1(n5542), .B0(n5544), .Y(n5543) );
NAND2X1TS U6993 ( .A(n5544), .B(n6027), .Y(n5546) );
AO22XLTS U6994 ( .A0(n5742), .A1(n5545), .B0(n5751), .B1(d_ff3_sh_y_out[60]),
.Y(n2567) );
AOI21X1TS U6995 ( .A0(d_ff2_Y[61]), .A1(n5546), .B0(n5550), .Y(n5548) );
AOI22X1TS U6996 ( .A0(d_ff2_X[62]), .A1(n5731), .B0(n5650), .B1(d_ff2_Y[62]),
.Y(n5553) );
AOI22X1TS U6997 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .A1(n5582), .B0(n5593), .B1(d_ff2_Z[62]), .Y(n5552) );
NAND2X1TS U6998 ( .A(n5553), .B(n5552), .Y(n2561) );
AOI22X1TS U6999 ( .A0(n5556), .A1(n5555), .B0(n5554), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[54]), .Y(n5558) );
NAND2X1TS U7000 ( .A(n5558), .B(n5557), .Y(n2560) );
AOI22X1TS U7001 ( .A0(n5560), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]), .B0(n5559), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]), .Y(n5566) );
AOI22X1TS U7002 ( .A0(n5564), .A1(n5563), .B0(n5562), .B1(n5561), .Y(n5565)
);
AO22XLTS U7003 ( .A0(n5571), .A1(result_add_subt[52]), .B0(n5570), .B1(
d_ff_Zn[52]), .Y(n2505) );
AO22XLTS U7004 ( .A0(n5572), .A1(result_add_subt[52]), .B0(n5568), .B1(
d_ff_Yn[52]), .Y(n2504) );
AO22XLTS U7005 ( .A0(n5574), .A1(result_add_subt[52]), .B0(n5569), .B1(
d_ff_Xn[52]), .Y(n2503) );
AO22XLTS U7006 ( .A0(n5571), .A1(result_add_subt[53]), .B0(n5570), .B1(
d_ff_Zn[53]), .Y(n2502) );
AO22XLTS U7007 ( .A0(n5572), .A1(result_add_subt[53]), .B0(n5577), .B1(
d_ff_Yn[53]), .Y(n2501) );
AO22XLTS U7008 ( .A0(n5574), .A1(result_add_subt[53]), .B0(n5569), .B1(
d_ff_Xn[53]), .Y(n2500) );
AO22XLTS U7009 ( .A0(n5571), .A1(result_add_subt[54]), .B0(n5570), .B1(
d_ff_Zn[54]), .Y(n2499) );
AO22XLTS U7010 ( .A0(n5572), .A1(result_add_subt[54]), .B0(n5746), .B1(
d_ff_Yn[54]), .Y(n2498) );
AO22XLTS U7011 ( .A0(n5574), .A1(result_add_subt[54]), .B0(n5753), .B1(
d_ff_Xn[54]), .Y(n2497) );
AO22XLTS U7012 ( .A0(n5571), .A1(result_add_subt[55]), .B0(n5570), .B1(
d_ff_Zn[55]), .Y(n2496) );
AO22XLTS U7013 ( .A0(n5572), .A1(result_add_subt[55]), .B0(n5577), .B1(
d_ff_Yn[55]), .Y(n2495) );
AO22XLTS U7014 ( .A0(n5574), .A1(result_add_subt[55]), .B0(n5748), .B1(
d_ff_Xn[55]), .Y(n2494) );
AO22XLTS U7015 ( .A0(n5571), .A1(result_add_subt[56]), .B0(n5576), .B1(
d_ff_Zn[56]), .Y(n2493) );
AO22XLTS U7016 ( .A0(n5572), .A1(result_add_subt[56]), .B0(n5577), .B1(
d_ff_Yn[56]), .Y(n2492) );
AO22XLTS U7017 ( .A0(n5574), .A1(result_add_subt[56]), .B0(n5748), .B1(
d_ff_Xn[56]), .Y(n2491) );
AO22XLTS U7018 ( .A0(n5571), .A1(result_add_subt[57]), .B0(n5576), .B1(
d_ff_Zn[57]), .Y(n2490) );
AO22XLTS U7019 ( .A0(n5572), .A1(result_add_subt[57]), .B0(n5577), .B1(
d_ff_Yn[57]), .Y(n2489) );
AO22XLTS U7020 ( .A0(n5574), .A1(result_add_subt[57]), .B0(n5748), .B1(
d_ff_Xn[57]), .Y(n2488) );
AO22XLTS U7021 ( .A0(n5571), .A1(result_add_subt[58]), .B0(n5576), .B1(
d_ff_Zn[58]), .Y(n2487) );
AO22XLTS U7022 ( .A0(n5572), .A1(result_add_subt[58]), .B0(n5577), .B1(
d_ff_Yn[58]), .Y(n2486) );
AO22XLTS U7023 ( .A0(n5574), .A1(result_add_subt[58]), .B0(n5748), .B1(
d_ff_Xn[58]), .Y(n2485) );
INVX2TS U7024 ( .A(n5576), .Y(n5579) );
AO22XLTS U7025 ( .A0(n5579), .A1(result_add_subt[59]), .B0(n5576), .B1(
d_ff_Zn[59]), .Y(n2484) );
INVX2TS U7026 ( .A(n5573), .Y(n5747) );
AO22XLTS U7027 ( .A0(n5747), .A1(result_add_subt[59]), .B0(n5577), .B1(
d_ff_Yn[59]), .Y(n2483) );
AO22XLTS U7028 ( .A0(n5574), .A1(result_add_subt[59]), .B0(n5748), .B1(
d_ff_Xn[59]), .Y(n2482) );
AO22XLTS U7029 ( .A0(n5579), .A1(result_add_subt[60]), .B0(n5576), .B1(
d_ff_Zn[60]), .Y(n2481) );
AO22XLTS U7030 ( .A0(n5747), .A1(result_add_subt[60]), .B0(n5577), .B1(
d_ff_Yn[60]), .Y(n2480) );
INVX2TS U7031 ( .A(n5575), .Y(n5754) );
AO22XLTS U7032 ( .A0(n5754), .A1(result_add_subt[60]), .B0(n5748), .B1(
d_ff_Xn[60]), .Y(n2479) );
AO22XLTS U7033 ( .A0(n5579), .A1(result_add_subt[61]), .B0(n5576), .B1(
d_ff_Zn[61]), .Y(n2478) );
AO22XLTS U7034 ( .A0(n5747), .A1(result_add_subt[61]), .B0(n5577), .B1(
d_ff_Yn[61]), .Y(n2477) );
AO22XLTS U7035 ( .A0(n5754), .A1(result_add_subt[61]), .B0(n5748), .B1(
d_ff_Xn[61]), .Y(n2476) );
AO22XLTS U7036 ( .A0(n5579), .A1(result_add_subt[62]), .B0(n5578), .B1(
d_ff_Zn[62]), .Y(n2475) );
AOI22X1TS U7037 ( .A0(n5672), .A1(d_ff2_Y[0]), .B0(n5593), .B1(d_ff2_Z[0]),
.Y(n5581) );
AOI22X1TS U7038 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .A1(n5582),
.B0(n5663), .B1(d_ff2_X[0]), .Y(n5580) );
NAND2X1TS U7039 ( .A(n5581), .B(n5580), .Y(n2473) );
AOI22X1TS U7040 ( .A0(n5672), .A1(d_ff2_Y[1]), .B0(n5593), .B1(d_ff2_Z[1]),
.Y(n5584) );
AOI22X1TS U7041 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n5582),
.B0(n5731), .B1(d_ff2_X[1]), .Y(n5583) );
NAND2X1TS U7042 ( .A(n5584), .B(n5583), .Y(n2471) );
AOI22X1TS U7043 ( .A0(n5588), .A1(d_ff2_X[2]), .B0(n5650), .B1(d_ff2_Y[2]),
.Y(n5587) );
AOI22X1TS U7044 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .A1(n5669),
.B0(n5593), .B1(d_ff2_Z[2]), .Y(n5586) );
NAND2X1TS U7045 ( .A(n5587), .B(n5586), .Y(n2469) );
AOI22X1TS U7046 ( .A0(n5588), .A1(d_ff2_X[3]), .B0(n5650), .B1(d_ff2_Y[3]),
.Y(n5590) );
AOI22X1TS U7047 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .A1(n5669),
.B0(n5593), .B1(d_ff2_Z[3]), .Y(n5589) );
NAND2X1TS U7048 ( .A(n5590), .B(n5589), .Y(n2467) );
AOI22X1TS U7049 ( .A0(n5672), .A1(d_ff2_Y[4]), .B0(n5593), .B1(d_ff2_Z[4]),
.Y(n5592) );
AOI22X1TS U7050 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .A1(n5669),
.B0(n5663), .B1(d_ff2_X[4]), .Y(n5591) );
NAND2X1TS U7051 ( .A(n5592), .B(n5591), .Y(n2465) );
CLKBUFX2TS U7052 ( .A(n5712), .Y(n5617) );
AOI22X1TS U7053 ( .A0(n5617), .A1(d_ff2_X[5]), .B0(n5593), .B1(d_ff2_Z[5]),
.Y(n5595) );
AOI22X1TS U7054 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .A1(n5669),
.B0(n5650), .B1(d_ff2_Y[5]), .Y(n5594) );
NAND2X1TS U7055 ( .A(n5595), .B(n5594), .Y(n2463) );
AOI22X1TS U7056 ( .A0(n5617), .A1(d_ff2_X[6]), .B0(n5650), .B1(d_ff2_Y[6]),
.Y(n5597) );
CLKBUFX2TS U7057 ( .A(n5691), .Y(n5735) );
AOI22X1TS U7058 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .A1(n5669),
.B0(n5735), .B1(d_ff2_Z[6]), .Y(n5596) );
NAND2X1TS U7059 ( .A(n5597), .B(n5596), .Y(n2461) );
AOI22X1TS U7060 ( .A0(n5617), .A1(d_ff2_X[7]), .B0(n5735), .B1(d_ff2_Z[7]),
.Y(n5599) );
AOI22X1TS U7061 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .A1(n5669),
.B0(n5650), .B1(d_ff2_Y[7]), .Y(n5598) );
NAND2X1TS U7062 ( .A(n5599), .B(n5598), .Y(n2459) );
CLKBUFX2TS U7063 ( .A(n5677), .Y(n5645) );
AOI22X1TS U7064 ( .A0(n5617), .A1(d_ff2_X[8]), .B0(n5645), .B1(d_ff2_Y[8]),
.Y(n5601) );
AOI22X1TS U7065 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .A1(n5669),
.B0(n5735), .B1(d_ff2_Z[8]), .Y(n5600) );
NAND2X1TS U7066 ( .A(n5601), .B(n5600), .Y(n2457) );
AOI22X1TS U7067 ( .A0(n5617), .A1(d_ff2_X[9]), .B0(n5735), .B1(d_ff2_Z[9]),
.Y(n5603) );
AOI22X1TS U7068 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .A1(n5669),
.B0(n5645), .B1(d_ff2_Y[9]), .Y(n5602) );
NAND2X1TS U7069 ( .A(n5603), .B(n5602), .Y(n2455) );
AOI22X1TS U7070 ( .A0(n5708), .A1(d_ff2_Y[10]), .B0(n5735), .B1(d_ff2_Z[10]),
.Y(n5605) );
AOI22X1TS U7071 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .A1(n5669), .B0(n5663), .B1(d_ff2_X[10]), .Y(n5604) );
NAND2X1TS U7072 ( .A(n5605), .B(n5604), .Y(n2453) );
AOI22X1TS U7073 ( .A0(n5617), .A1(d_ff2_X[11]), .B0(n5645), .B1(d_ff2_Y[11]),
.Y(n5607) );
INVX2TS U7074 ( .A(n5745), .Y(n5626) );
AOI22X1TS U7075 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .A1(n5626), .B0(n5735), .B1(d_ff2_Z[11]), .Y(n5606) );
NAND2X1TS U7076 ( .A(n5607), .B(n5606), .Y(n2451) );
AOI22X1TS U7077 ( .A0(n5617), .A1(d_ff2_X[12]), .B0(n5735), .B1(d_ff2_Z[12]),
.Y(n5609) );
AOI22X1TS U7078 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .A1(n5626), .B0(n5645), .B1(d_ff2_Y[12]), .Y(n5608) );
NAND2X1TS U7079 ( .A(n5609), .B(n5608), .Y(n2449) );
AOI22X1TS U7080 ( .A0(n5617), .A1(d_ff2_X[13]), .B0(n5645), .B1(d_ff2_Y[13]),
.Y(n5611) );
AOI22X1TS U7081 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1(n5626), .B0(n5735), .B1(d_ff2_Z[13]), .Y(n5610) );
NAND2X1TS U7082 ( .A(n5611), .B(n5610), .Y(n2447) );
AOI22X1TS U7083 ( .A0(n5612), .A1(d_ff2_X[14]), .B0(n5735), .B1(d_ff2_Z[14]),
.Y(n5614) );
AOI22X1TS U7084 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .A1(n5626), .B0(n5645), .B1(d_ff2_Y[14]), .Y(n5613) );
NAND2X1TS U7085 ( .A(n5614), .B(n5613), .Y(n2445) );
AOI22X1TS U7086 ( .A0(n5617), .A1(d_ff2_X[15]), .B0(n5645), .B1(d_ff2_Y[15]),
.Y(n5616) );
CLKBUFX2TS U7087 ( .A(n5691), .Y(n5635) );
AOI22X1TS U7088 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1(n5626), .B0(n5635), .B1(d_ff2_Z[15]), .Y(n5615) );
NAND2X1TS U7089 ( .A(n5616), .B(n5615), .Y(n2443) );
CLKBUFX2TS U7090 ( .A(n5677), .Y(n5668) );
AOI22X1TS U7091 ( .A0(n5617), .A1(d_ff2_X[16]), .B0(n5668), .B1(d_ff2_Y[16]),
.Y(n5619) );
AOI22X1TS U7092 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .A1(n5626), .B0(n5635), .B1(d_ff2_Z[16]), .Y(n5618) );
NAND2X1TS U7093 ( .A(n5619), .B(n5618), .Y(n2441) );
CLKBUFX2TS U7094 ( .A(n5718), .Y(n5642) );
AOI22X1TS U7095 ( .A0(n5642), .A1(d_ff2_X[17]), .B0(n5645), .B1(d_ff2_Y[17]),
.Y(n5621) );
AOI22X1TS U7096 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .A1(n5626), .B0(n5635), .B1(d_ff2_Z[17]), .Y(n5620) );
NAND2X1TS U7097 ( .A(n5621), .B(n5620), .Y(n2439) );
AOI22X1TS U7098 ( .A0(n5642), .A1(d_ff2_X[18]), .B0(n5668), .B1(d_ff2_Y[18]),
.Y(n5623) );
AOI22X1TS U7099 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .A1(n5626), .B0(n5635), .B1(d_ff2_Z[18]), .Y(n5622) );
NAND2X1TS U7100 ( .A(n5623), .B(n5622), .Y(n2437) );
AOI22X1TS U7101 ( .A0(n5642), .A1(d_ff2_X[19]), .B0(n5645), .B1(d_ff2_Y[19]),
.Y(n5625) );
AOI22X1TS U7102 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .A1(n5626), .B0(n5635), .B1(d_ff2_Z[19]), .Y(n5624) );
NAND2X1TS U7103 ( .A(n5625), .B(n5624), .Y(n2435) );
AOI22X1TS U7104 ( .A0(n5642), .A1(d_ff2_X[20]), .B0(n5668), .B1(d_ff2_Y[20]),
.Y(n5628) );
AOI22X1TS U7105 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .A1(n5626), .B0(n5635), .B1(d_ff2_Z[20]), .Y(n5627) );
NAND2X1TS U7106 ( .A(n5628), .B(n5627), .Y(n2433) );
AOI22X1TS U7107 ( .A0(n5642), .A1(d_ff2_X[21]), .B0(n5668), .B1(d_ff2_Y[21]),
.Y(n5630) );
INVX2TS U7108 ( .A(n5745), .Y(n5651) );
AOI22X1TS U7109 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1(n5651), .B0(n5635), .B1(d_ff2_Z[21]), .Y(n5629) );
NAND2X1TS U7110 ( .A(n5630), .B(n5629), .Y(n2431) );
AOI22X1TS U7111 ( .A0(n5642), .A1(d_ff2_X[22]), .B0(n5635), .B1(d_ff2_Z[22]),
.Y(n5632) );
AOI22X1TS U7112 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .A1(n5651), .B0(n5668), .B1(d_ff2_Y[22]), .Y(n5631) );
NAND2X1TS U7113 ( .A(n5632), .B(n5631), .Y(n2429) );
AOI22X1TS U7114 ( .A0(n5642), .A1(d_ff2_X[23]), .B0(n5668), .B1(d_ff2_Y[23]),
.Y(n5634) );
AOI22X1TS U7115 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1(n5651), .B0(n5635), .B1(d_ff2_Z[23]), .Y(n5633) );
NAND2X1TS U7116 ( .A(n5634), .B(n5633), .Y(n2427) );
AOI22X1TS U7117 ( .A0(n5736), .A1(d_ff2_Y[24]), .B0(n5635), .B1(d_ff2_Z[24]),
.Y(n5637) );
AOI22X1TS U7118 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .A1(n5651), .B0(n5663), .B1(d_ff2_X[24]), .Y(n5636) );
NAND2X1TS U7119 ( .A(n5637), .B(n5636), .Y(n2425) );
AOI22X1TS U7120 ( .A0(n5642), .A1(d_ff2_X[25]), .B0(n5668), .B1(d_ff2_Y[25]),
.Y(n5639) );
CLKBUFX2TS U7121 ( .A(n5691), .Y(n5660) );
AOI22X1TS U7122 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .A1(n5651), .B0(n5660), .B1(d_ff2_Z[25]), .Y(n5638) );
NAND2X1TS U7123 ( .A(n5639), .B(n5638), .Y(n2423) );
AOI22X1TS U7124 ( .A0(n5642), .A1(d_ff2_X[26]), .B0(n5668), .B1(d_ff2_Y[26]),
.Y(n5641) );
AOI22X1TS U7125 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .A1(n5651), .B0(n5660), .B1(d_ff2_Z[26]), .Y(n5640) );
NAND2X1TS U7126 ( .A(n5641), .B(n5640), .Y(n2421) );
AOI22X1TS U7127 ( .A0(n5642), .A1(d_ff2_X[27]), .B0(n5660), .B1(d_ff2_Z[27]),
.Y(n5644) );
CLKBUFX2TS U7128 ( .A(n5677), .Y(n5713) );
AOI22X1TS U7129 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .A1(n5651), .B0(n5713), .B1(d_ff2_Y[27]), .Y(n5643) );
NAND2X1TS U7130 ( .A(n5644), .B(n5643), .Y(n2419) );
CLKBUFX2TS U7131 ( .A(n5712), .Y(n5683) );
AOI22X1TS U7132 ( .A0(n5683), .A1(d_ff2_X[28]), .B0(n5645), .B1(d_ff2_Y[28]),
.Y(n5647) );
AOI22X1TS U7133 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .A1(n5651), .B0(n5660), .B1(d_ff2_Z[28]), .Y(n5646) );
NAND2X1TS U7134 ( .A(n5647), .B(n5646), .Y(n2417) );
AOI22X1TS U7135 ( .A0(n5672), .A1(d_ff2_Y[29]), .B0(n5660), .B1(d_ff2_Z[29]),
.Y(n5649) );
AOI22X1TS U7136 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .A1(n5651), .B0(n5663), .B1(d_ff2_X[29]), .Y(n5648) );
NAND2X1TS U7137 ( .A(n5649), .B(n5648), .Y(n2415) );
AOI22X1TS U7138 ( .A0(n5683), .A1(d_ff2_X[30]), .B0(n5650), .B1(d_ff2_Y[30]),
.Y(n5653) );
AOI22X1TS U7139 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .A1(n5651), .B0(n5660), .B1(d_ff2_Z[30]), .Y(n5652) );
NAND2X1TS U7140 ( .A(n5653), .B(n5652), .Y(n2413) );
AOI22X1TS U7141 ( .A0(n5683), .A1(d_ff2_X[31]), .B0(n5668), .B1(d_ff2_Y[31]),
.Y(n5655) );
INVX2TS U7142 ( .A(n5745), .Y(n5680) );
AOI22X1TS U7143 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .A1(n5680), .B0(n5660), .B1(d_ff2_Z[31]), .Y(n5654) );
NAND2X1TS U7144 ( .A(n5655), .B(n5654), .Y(n2411) );
AOI22X1TS U7145 ( .A0(n5683), .A1(d_ff2_X[32]), .B0(n5713), .B1(d_ff2_Y[32]),
.Y(n5657) );
AOI22X1TS U7146 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[32]), .A1(n5680), .B0(n5660), .B1(d_ff2_Z[32]), .Y(n5656) );
NAND2X1TS U7147 ( .A(n5657), .B(n5656), .Y(n2409) );
AOI22X1TS U7148 ( .A0(n5708), .A1(d_ff2_Y[33]), .B0(n5660), .B1(d_ff2_Z[33]),
.Y(n5659) );
AOI22X1TS U7149 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[33]), .A1(n5680), .B0(n5663), .B1(d_ff2_X[33]), .Y(n5658) );
NAND2X1TS U7150 ( .A(n5659), .B(n5658), .Y(n2407) );
AOI22X1TS U7151 ( .A0(n5683), .A1(d_ff2_X[34]), .B0(n5713), .B1(d_ff2_Y[34]),
.Y(n5662) );
AOI22X1TS U7152 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[34]), .A1(n5680), .B0(n5660), .B1(d_ff2_Z[34]), .Y(n5661) );
NAND2X1TS U7153 ( .A(n5662), .B(n5661), .Y(n2405) );
CLKBUFX2TS U7154 ( .A(n5691), .Y(n5688) );
AOI22X1TS U7155 ( .A0(n5708), .A1(d_ff2_Y[35]), .B0(n5688), .B1(d_ff2_Z[35]),
.Y(n5665) );
AOI22X1TS U7156 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[35]), .A1(n5680), .B0(n5663), .B1(d_ff2_X[35]), .Y(n5664) );
NAND2X1TS U7157 ( .A(n5665), .B(n5664), .Y(n2403) );
AOI22X1TS U7158 ( .A0(n5672), .A1(d_ff2_Y[36]), .B0(n5688), .B1(d_ff2_Z[36]),
.Y(n5667) );
AOI22X1TS U7159 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[36]), .A1(n5680), .B0(n5700), .B1(d_ff2_X[36]), .Y(n5666) );
NAND2X1TS U7160 ( .A(n5667), .B(n5666), .Y(n2401) );
AOI22X1TS U7161 ( .A0(n5683), .A1(d_ff2_X[37]), .B0(n5688), .B1(d_ff2_Z[37]),
.Y(n5671) );
AOI22X1TS U7162 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[37]), .A1(n5669), .B0(n5668), .B1(d_ff2_Y[37]), .Y(n5670) );
NAND2X1TS U7163 ( .A(n5671), .B(n5670), .Y(n2399) );
AOI22X1TS U7164 ( .A0(n5672), .A1(d_ff2_Y[38]), .B0(n5688), .B1(d_ff2_Z[38]),
.Y(n5674) );
AOI22X1TS U7165 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[38]), .A1(n5680), .B0(n5700), .B1(d_ff2_X[38]), .Y(n5673) );
NAND2X1TS U7166 ( .A(n5674), .B(n5673), .Y(n2397) );
AOI22X1TS U7167 ( .A0(n5683), .A1(d_ff2_X[39]), .B0(n5713), .B1(d_ff2_Y[39]),
.Y(n5676) );
AOI22X1TS U7168 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[39]), .A1(n5680), .B0(n5688), .B1(d_ff2_Z[39]), .Y(n5675) );
NAND2X1TS U7169 ( .A(n5676), .B(n5675), .Y(n2395) );
AOI22X1TS U7170 ( .A0(n5683), .A1(d_ff2_X[40]), .B0(n5688), .B1(d_ff2_Z[40]),
.Y(n5679) );
CLKBUFX2TS U7171 ( .A(n5677), .Y(n5730) );
AOI22X1TS U7172 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[40]), .A1(n5680), .B0(n5730), .B1(d_ff2_Y[40]), .Y(n5678) );
NAND2X1TS U7173 ( .A(n5679), .B(n5678), .Y(n2393) );
AOI22X1TS U7174 ( .A0(n5683), .A1(d_ff2_X[41]), .B0(n5730), .B1(d_ff2_Y[41]),
.Y(n5682) );
AOI22X1TS U7175 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[41]), .A1(n5680), .B0(n5688), .B1(d_ff2_Z[41]), .Y(n5681) );
NAND2X1TS U7176 ( .A(n5682), .B(n5681), .Y(n2391) );
AOI22X1TS U7177 ( .A0(n5683), .A1(d_ff2_X[42]), .B0(n5688), .B1(d_ff2_Z[42]),
.Y(n5685) );
INVX2TS U7178 ( .A(n5709), .Y(n5705) );
AOI22X1TS U7179 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[42]), .A1(n5705), .B0(n5713), .B1(d_ff2_Y[42]), .Y(n5684) );
NAND2X1TS U7180 ( .A(n5685), .B(n5684), .Y(n2389) );
AOI22X1TS U7181 ( .A0(n5718), .A1(d_ff2_X[43]), .B0(n5730), .B1(d_ff2_Y[43]),
.Y(n5687) );
AOI22X1TS U7182 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[43]), .A1(n5705), .B0(n5688), .B1(d_ff2_Z[43]), .Y(n5686) );
NAND2X1TS U7183 ( .A(n5687), .B(n5686), .Y(n2387) );
AOI22X1TS U7184 ( .A0(n5708), .A1(d_ff2_Y[44]), .B0(n5688), .B1(d_ff2_Z[44]),
.Y(n5690) );
AOI22X1TS U7185 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[44]), .A1(n5705), .B0(n5737), .B1(d_ff2_X[44]), .Y(n5689) );
NAND2X1TS U7186 ( .A(n5690), .B(n5689), .Y(n2385) );
AOI22X1TS U7187 ( .A0(n5712), .A1(d_ff2_X[45]), .B0(n5713), .B1(d_ff2_Y[45]),
.Y(n5693) );
CLKBUFX2TS U7188 ( .A(n5691), .Y(n5727) );
AOI22X1TS U7189 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[45]), .A1(n5705), .B0(n5727), .B1(d_ff2_Z[45]), .Y(n5692) );
NAND2X1TS U7190 ( .A(n5693), .B(n5692), .Y(n2383) );
AOI22X1TS U7191 ( .A0(n5718), .A1(d_ff2_X[46]), .B0(n5713), .B1(d_ff2_Y[46]),
.Y(n5695) );
AOI22X1TS U7192 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[46]), .A1(n5705), .B0(n5727), .B1(d_ff2_Z[46]), .Y(n5694) );
NAND2X1TS U7193 ( .A(n5695), .B(n5694), .Y(n2381) );
AOI22X1TS U7194 ( .A0(n5718), .A1(d_ff2_X[47]), .B0(n5727), .B1(d_ff2_Z[47]),
.Y(n5697) );
AOI22X1TS U7195 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[47]), .A1(n5705), .B0(n5730), .B1(d_ff2_Y[47]), .Y(n5696) );
NAND2X1TS U7196 ( .A(n5697), .B(n5696), .Y(n2379) );
AOI22X1TS U7197 ( .A0(n5712), .A1(d_ff2_X[48]), .B0(n5713), .B1(d_ff2_Y[48]),
.Y(n5699) );
AOI22X1TS U7198 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[48]), .A1(n5705), .B0(n5727), .B1(d_ff2_Z[48]), .Y(n5698) );
NAND2X1TS U7199 ( .A(n5699), .B(n5698), .Y(n2377) );
AOI22X1TS U7200 ( .A0(n5708), .A1(d_ff2_Y[49]), .B0(n5727), .B1(d_ff2_Z[49]),
.Y(n5702) );
AOI22X1TS U7201 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[49]), .A1(n5705), .B0(n5700), .B1(d_ff2_X[49]), .Y(n5701) );
NAND2X1TS U7202 ( .A(n5702), .B(n5701), .Y(n2375) );
AOI22X1TS U7203 ( .A0(n5712), .A1(d_ff2_X[50]), .B0(n5727), .B1(d_ff2_Z[50]),
.Y(n5704) );
AOI22X1TS U7204 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[50]), .A1(n5705), .B0(n5730), .B1(d_ff2_Y[50]), .Y(n5703) );
NAND2X1TS U7205 ( .A(n5704), .B(n5703), .Y(n2373) );
AOI22X1TS U7206 ( .A0(n5718), .A1(d_ff2_X[51]), .B0(n5727), .B1(d_ff2_Z[51]),
.Y(n5707) );
AOI22X1TS U7207 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[51]), .A1(n5705), .B0(n5713), .B1(d_ff2_Y[51]), .Y(n5706) );
NAND2X1TS U7208 ( .A(n5707), .B(n5706), .Y(n2371) );
AOI22X1TS U7209 ( .A0(n5708), .A1(d_ff2_Y[52]), .B0(n5727), .B1(d_ff2_Z[52]),
.Y(n5711) );
INVX2TS U7210 ( .A(n5709), .Y(n5738) );
AOI22X1TS U7211 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .A1(n5738), .B0(n5737), .B1(d_ff2_X[52]), .Y(n5710) );
NAND2X1TS U7212 ( .A(n5711), .B(n5710), .Y(n2369) );
AOI22X1TS U7213 ( .A0(n5712), .A1(d_ff2_X[53]), .B0(n5732), .B1(d_ff2_Z[53]),
.Y(n5715) );
AOI22X1TS U7214 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[53]), .A1(n5738), .B0(n5713), .B1(d_ff2_Y[53]), .Y(n5714) );
NAND2X1TS U7215 ( .A(n5715), .B(n5714), .Y(n2367) );
AOI22X1TS U7216 ( .A0(n5718), .A1(d_ff2_X[54]), .B0(n5730), .B1(d_ff2_Y[54]),
.Y(n5717) );
AOI22X1TS U7217 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[54]), .A1(n5738), .B0(n5727), .B1(d_ff2_Z[54]), .Y(n5716) );
NAND2X1TS U7218 ( .A(n5717), .B(n5716), .Y(n2365) );
AOI22X1TS U7219 ( .A0(n5718), .A1(d_ff2_X[55]), .B0(n5732), .B1(d_ff2_Z[55]),
.Y(n5720) );
AOI22X1TS U7220 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[55]), .A1(n5738), .B0(n5730), .B1(d_ff2_Y[55]), .Y(n5719) );
NAND2X1TS U7221 ( .A(n5720), .B(n5719), .Y(n2363) );
AOI22X1TS U7222 ( .A0(n5736), .A1(d_ff2_Y[56]), .B0(n5732), .B1(d_ff2_Z[56]),
.Y(n5722) );
AOI22X1TS U7223 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[56]), .A1(n5738), .B0(d_ff2_X[56]), .B1(n5737), .Y(n5721) );
NAND2X1TS U7224 ( .A(n5722), .B(n5721), .Y(n2361) );
AOI22X1TS U7225 ( .A0(n5736), .A1(d_ff2_Y[57]), .B0(n5732), .B1(d_ff2_Z[57]),
.Y(n5724) );
AOI22X1TS U7226 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .A1(n5738), .B0(d_ff2_X[57]), .B1(n5737), .Y(n5723) );
NAND2X1TS U7227 ( .A(n5724), .B(n5723), .Y(n2359) );
AOI22X1TS U7228 ( .A0(d_ff2_X[58]), .A1(n5731), .B0(n5732), .B1(d_ff2_Z[58]),
.Y(n5726) );
AOI22X1TS U7229 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[58]), .A1(n5738), .B0(n5730), .B1(d_ff2_Y[58]), .Y(n5725) );
NAND2X1TS U7230 ( .A(n5726), .B(n5725), .Y(n2357) );
AOI22X1TS U7231 ( .A0(d_ff2_X[59]), .A1(n5731), .B0(n5727), .B1(d_ff2_Z[59]),
.Y(n5729) );
AOI22X1TS U7232 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .A1(n5738), .B0(n5730), .B1(d_ff2_Y[59]), .Y(n5728) );
NAND2X1TS U7233 ( .A(n5729), .B(n5728), .Y(n2355) );
AOI22X1TS U7234 ( .A0(d_ff2_X[60]), .A1(n5731), .B0(n5730), .B1(d_ff2_Y[60]),
.Y(n5734) );
AOI22X1TS U7235 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[60]), .A1(n5738), .B0(n5732), .B1(d_ff2_Z[60]), .Y(n5733) );
NAND2X1TS U7236 ( .A(n5734), .B(n5733), .Y(n2353) );
AOI22X1TS U7237 ( .A0(n5736), .A1(d_ff2_Y[61]), .B0(n5735), .B1(d_ff2_Z[61]),
.Y(n5740) );
AOI22X1TS U7238 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]), .A1(n5738), .B0(d_ff2_X[61]), .B1(n5737), .Y(n5739) );
NAND2X1TS U7239 ( .A(n5740), .B(n5739), .Y(n2351) );
AO22XLTS U7240 ( .A0(n5742), .A1(d_ff2_Z[63]), .B0(n5741), .B1(
d_ff3_sign_out), .Y(n2348) );
AOI2BB2XLTS U7241 ( .B0(cont_var_out[0]), .B1(d_ff3_sign_out), .A0N(
d_ff3_sign_out), .A1N(cont_var_out[0]), .Y(n5744) );
AO22XLTS U7242 ( .A0(n5745), .A1(n5744), .B0(n5743), .B1(
inst_FPU_PIPELINED_FPADDSUB_intAS), .Y(n2347) );
AO22XLTS U7243 ( .A0(n5747), .A1(result_add_subt[62]), .B0(n5746), .B1(
d_ff_Yn[62]), .Y(n2346) );
AO22XLTS U7244 ( .A0(n5754), .A1(result_add_subt[62]), .B0(n5748), .B1(
d_ff_Xn[62]), .Y(n2345) );
AO22XLTS U7245 ( .A0(n5750), .A1(d_ff_Yn[63]), .B0(d_ff2_Y[63]), .B1(n5749),
.Y(n2344) );
AO22XLTS U7246 ( .A0(n5752), .A1(d_ff2_Y[63]), .B0(n5751), .B1(
d_ff3_sh_y_out[63]), .Y(n2343) );
AO22XLTS U7247 ( .A0(n5754), .A1(result_add_subt[63]), .B0(n5753), .B1(
d_ff_Xn[63]), .Y(n2341) );
AOI22X1TS U7248 ( .A0(n5756), .A1(d_ff_Xn[63]), .B0(d_ff_Yn[63]), .B1(n5755),
.Y(n5758) );
OAI33XLTS U7249 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n5922), .B0(n5896), .B1(n6040), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n5757) );
XNOR2X1TS U7250 ( .A(n5758), .B(n5757), .Y(n5759) );
AO22XLTS U7251 ( .A0(n5761), .A1(data_output[63]), .B0(n5760), .B1(n5759),
.Y(n2276) );
NAND2X1TS U7252 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[52]), .B(n5955), .Y(intadd_22_CI) );
CLKBUFX2TS U7253 ( .A(n5838), .Y(n5782) );
INVX2TS U7254 ( .A(n5782), .Y(n5887) );
NAND2X1TS U7255 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56]), .B(
intadd_22_n1), .Y(n5762) );
AOI21X1TS U7256 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[56]), .A1(
n5763), .B0(n5766), .Y(n5764) );
AO22XLTS U7257 ( .A0(n5887), .A1(n5764), .B0(n5886), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n2274) );
AO22XLTS U7258 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
intadd_22_SUM_1_), .B0(n5774), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n2272) );
AO22XLTS U7259 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
intadd_22_SUM_0_), .B0(n5774), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n2271) );
OA21XLTS U7260 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[52]), .A1(
n5955), .B0(intadd_22_CI), .Y(n5765) );
AOI22X1TS U7261 ( .A0(n5887), .A1(n5765), .B0(n5920), .B1(n5886), .Y(n2270)
);
AOI21X1TS U7262 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56]), .A1(
intadd_22_n1), .B0(n5766), .Y(n5767) );
AO22XLTS U7263 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
n5769), .B0(n5774), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[5]), .Y(n2269) );
AO22XLTS U7264 ( .A0(n5775), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[52]), .B0(n5774), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[52]), .Y(n2246) );
AO22XLTS U7265 ( .A0(n5771), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[52]), .B0(n5770), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[52]), .Y(n2245) );
AO22XLTS U7266 ( .A0(n5777), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[52]), .B0(n5772), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[52]), .Y(n2244) );
AO22XLTS U7267 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[52]), .B0(n6042), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n2243) );
AO22XLTS U7268 ( .A0(n5775), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[53]), .B0(n5774), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[53]), .Y(n2241) );
AO22XLTS U7269 ( .A0(n5771), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[53]), .B0(n5770), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[53]), .Y(n2240) );
AO22XLTS U7270 ( .A0(n5776), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[53]), .B0(n5772), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[53]), .Y(n2239) );
CLKBUFX2TS U7271 ( .A(n5773), .Y(n5827) );
AO22XLTS U7272 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[53]), .B0(n5827), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n2238) );
AO22XLTS U7273 ( .A0(n5775), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[54]), .B0(n5774), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[54]), .Y(n2236) );
CLKBUFX2TS U7274 ( .A(n6094), .Y(n5824) );
AO22XLTS U7275 ( .A0(n5825), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[54]), .B0(n5824), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[54]), .Y(n2235) );
INVX2TS U7276 ( .A(n5869), .Y(n5826) );
AO22XLTS U7277 ( .A0(n5776), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[54]), .B0(n5826), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[54]), .Y(n2234) );
AO22XLTS U7278 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[54]), .B0(n5827), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n2233) );
AO22XLTS U7279 ( .A0(n5775), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[55]), .B0(n5774), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[55]), .Y(n2231) );
AO22XLTS U7280 ( .A0(n5825), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[55]), .B0(n5824), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[55]), .Y(n2230) );
AO22XLTS U7281 ( .A0(n5776), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[55]), .B0(n5826), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[55]), .Y(n2229) );
AO22XLTS U7282 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[55]), .B0(n5827), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n2228) );
AO22XLTS U7283 ( .A0(n5775), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56]), .B0(n5774), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[56]), .Y(n2226) );
AO22XLTS U7284 ( .A0(n5825), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[56]), .B0(n5824), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[56]), .Y(n2225) );
AO22XLTS U7285 ( .A0(n5776), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[56]), .B0(n5826), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[56]), .Y(n2224) );
AO22XLTS U7286 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[56]), .B0(n5827), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n2223) );
AO22XLTS U7287 ( .A0(n5775), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[57]), .B0(n5782), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[57]), .Y(n2221) );
AO22XLTS U7288 ( .A0(n5825), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[57]), .B0(n5824), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[57]), .Y(n2220) );
AO22XLTS U7289 ( .A0(n5776), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[57]), .B0(n5826), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[57]), .Y(n2219) );
AO22XLTS U7290 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[57]), .B0(n5827), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n2218) );
CLKBUFX2TS U7291 ( .A(n6035), .Y(n5881) );
INVX2TS U7292 ( .A(n5881), .Y(n5789) );
AO22XLTS U7293 ( .A0(n5789), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[58]), .B0(n5782), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[58]), .Y(n2216) );
AO22XLTS U7294 ( .A0(n5825), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[58]), .B0(n5824), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[58]), .Y(n2215) );
AO22XLTS U7295 ( .A0(n5776), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[58]), .B0(n5826), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[58]), .Y(n2214) );
AO22XLTS U7296 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[58]), .B0(n5827), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n2213) );
AO22XLTS U7297 ( .A0(n5775), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[59]), .B0(n5782), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[59]), .Y(n2211) );
AO22XLTS U7298 ( .A0(n5825), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[59]), .B0(n5824), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[59]), .Y(n2210) );
AO22XLTS U7299 ( .A0(n5776), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[59]), .B0(n5826), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[59]), .Y(n2209) );
AO22XLTS U7300 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[59]), .B0(n6042), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n2208) );
AO22XLTS U7301 ( .A0(n5775), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[60]), .B0(n5782), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[60]), .Y(n2206) );
AO22XLTS U7302 ( .A0(n5825), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[60]), .B0(n5824), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[60]), .Y(n2205) );
AO22XLTS U7303 ( .A0(n5776), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[60]), .B0(n5826), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[60]), .Y(n2204) );
AO22XLTS U7304 ( .A0(n3194), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[60]),
.B0(n5827), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[8]), .Y(
n2203) );
AO22XLTS U7305 ( .A0(n5775), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[61]), .B0(n5782), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[61]), .Y(n2201) );
AO22XLTS U7306 ( .A0(n5825), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[61]), .B0(n5824), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[61]), .Y(n2200) );
AO22XLTS U7307 ( .A0(n5776), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[61]), .B0(n5826), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[61]), .Y(n2199) );
AO22XLTS U7308 ( .A0(n3194), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[61]),
.B0(n5827), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[9]), .Y(
n2198) );
AO22XLTS U7309 ( .A0(n5789), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[62]), .B0(n5782), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[62]), .Y(n2196) );
AO22XLTS U7310 ( .A0(n5825), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[62]), .B0(n5824), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[62]), .Y(n2195) );
AO22XLTS U7311 ( .A0(n5777), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[62]), .B0(n5826), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[62]), .Y(n2194) );
AO22XLTS U7312 ( .A0(n3194), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[62]),
.B0(n5827), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[10]), .Y(
n2193) );
OA21XLTS U7313 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(
underflow_flag), .B0(n5778), .Y(n2185) );
OAI2BB2XLTS U7314 ( .B0(n5790), .B1(n5779), .A0N(n5875), .A1N(
result_add_subt[51]), .Y(n2181) );
AO22XLTS U7315 ( .A0(n5789), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[51]), .B0(n5782), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[51]), .Y(n2179) );
OAI2BB2XLTS U7316 ( .B0(n5780), .B1(n5790), .A0N(n6043), .A1N(
result_add_subt[50]), .Y(n2178) );
AO22XLTS U7317 ( .A0(n5789), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[50]), .B0(n5782), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[50]), .Y(n2176) );
OAI2BB2XLTS U7318 ( .B0(n5781), .B1(n5790), .A0N(n5846), .A1N(
result_add_subt[47]), .Y(n2175) );
AO22XLTS U7319 ( .A0(n5789), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[47]), .B0(n5782), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[47]), .Y(n2173) );
OAI2BB2XLTS U7320 ( .B0(n5783), .B1(n5790), .A0N(n5846), .A1N(
result_add_subt[49]), .Y(n2172) );
CLKBUFX2TS U7321 ( .A(n5838), .Y(n5880) );
AO22XLTS U7322 ( .A0(n5789), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[49]), .B0(n5880), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[49]), .Y(n2170) );
OAI2BB2XLTS U7323 ( .B0(n5784), .B1(n5790), .A0N(n6043), .A1N(
result_add_subt[48]), .Y(n2169) );
AO22XLTS U7324 ( .A0(n5789), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[48]), .B0(n5880), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[48]), .Y(n2167) );
OAI2BB2XLTS U7325 ( .B0(n5785), .B1(n5790), .A0N(n6043), .A1N(
result_add_subt[33]), .Y(n2166) );
CLKBUFX2TS U7326 ( .A(n6035), .Y(n5878) );
INVX2TS U7327 ( .A(n5878), .Y(n5801) );
AO22XLTS U7328 ( .A0(n5801), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[33]), .B0(n5880), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[33]), .Y(n2164) );
OAI2BB2XLTS U7329 ( .B0(n5786), .B1(n5790), .A0N(n6043), .A1N(
result_add_subt[44]), .Y(n2163) );
AO22XLTS U7330 ( .A0(n5789), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[44]), .B0(n5880), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[44]), .Y(n2161) );
CLKBUFX2TS U7331 ( .A(n5846), .Y(n5804) );
OAI2BB2XLTS U7332 ( .B0(n5787), .B1(n5790), .A0N(n5804), .A1N(
result_add_subt[3]), .Y(n2160) );
AO22XLTS U7333 ( .A0(n5789), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]), .B0(n5880), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n2158)
);
OAI2BB2XLTS U7334 ( .B0(n5788), .B1(n5790), .A0N(n6043), .A1N(
result_add_subt[34]), .Y(n2157) );
AO22XLTS U7335 ( .A0(n5789), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[34]), .B0(n5880), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[34]), .Y(n2155) );
OAI2BB2XLTS U7336 ( .B0(n5791), .B1(n5790), .A0N(n6043), .A1N(
result_add_subt[45]), .Y(n2154) );
AO22XLTS U7337 ( .A0(n5801), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[45]), .B0(n5880), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[45]), .Y(n2152) );
OAI2BB2XLTS U7338 ( .B0(n5792), .B1(n5802), .A0N(n6043), .A1N(
result_add_subt[46]), .Y(n2151) );
AO22XLTS U7339 ( .A0(n5801), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[46]), .B0(n5880), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[46]), .Y(n2149) );
OAI2BB2XLTS U7340 ( .B0(n5793), .B1(n5802), .A0N(n5804), .A1N(
result_add_subt[35]), .Y(n2148) );
AO22XLTS U7341 ( .A0(n5801), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[35]), .B0(n5880), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[35]), .Y(n2146) );
OAI2BB2XLTS U7342 ( .B0(n5794), .B1(n5802), .A0N(n5804), .A1N(
result_add_subt[42]), .Y(n2145) );
CLKBUFX2TS U7343 ( .A(n5838), .Y(n5877) );
AO22XLTS U7344 ( .A0(n5801), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[42]), .B0(n5877), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[42]), .Y(n2143) );
CLKBUFX2TS U7345 ( .A(n5846), .Y(n5815) );
OAI2BB2XLTS U7346 ( .B0(n5795), .B1(n5802), .A0N(n5815), .A1N(
result_add_subt[43]), .Y(n2142) );
AO22XLTS U7347 ( .A0(n5801), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[43]), .B0(n5877), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[43]), .Y(n2140) );
OAI2BB2XLTS U7348 ( .B0(n5796), .B1(n5802), .A0N(n5804), .A1N(
result_add_subt[36]), .Y(n2139) );
AO22XLTS U7349 ( .A0(n5801), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[36]), .B0(n5877), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[36]), .Y(n2137) );
OAI2BB2XLTS U7350 ( .B0(n5797), .B1(n5802), .A0N(n5804), .A1N(
result_add_subt[39]), .Y(n2136) );
CLKBUFX2TS U7351 ( .A(n6035), .Y(n5868) );
INVX2TS U7352 ( .A(n5868), .Y(n5814) );
AO22XLTS U7353 ( .A0(n5814), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[39]), .B0(n5877), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[39]), .Y(n2134) );
OAI2BB2XLTS U7354 ( .B0(n5798), .B1(n5802), .A0N(n5804), .A1N(
result_add_subt[41]), .Y(n2133) );
AO22XLTS U7355 ( .A0(n5801), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[41]), .B0(n5877), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[41]), .Y(n2131) );
OAI2BB2XLTS U7356 ( .B0(n5799), .B1(n5802), .A0N(n5804), .A1N(
result_add_subt[38]), .Y(n2130) );
AO22XLTS U7357 ( .A0(n5801), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[38]), .B0(n5877), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[38]), .Y(n2128) );
OAI2BB2XLTS U7358 ( .B0(n5800), .B1(n5802), .A0N(n5804), .A1N(
result_add_subt[40]), .Y(n2127) );
AO22XLTS U7359 ( .A0(n5801), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[40]), .B0(n5877), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[40]), .Y(n2125) );
OAI2BB2XLTS U7360 ( .B0(n5803), .B1(n5802), .A0N(n5804), .A1N(
result_add_subt[37]), .Y(n2124) );
AO22XLTS U7361 ( .A0(n5814), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[37]), .B0(n5877), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[37]), .Y(n2122) );
OAI2BB2XLTS U7362 ( .B0(n5805), .B1(n5816), .A0N(n5804), .A1N(
result_add_subt[28]), .Y(n2121) );
AO22XLTS U7363 ( .A0(n5886), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[28]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[28]), .Y(n2119) );
OAI2BB2XLTS U7364 ( .B0(n5806), .B1(n5816), .A0N(n5815), .A1N(
result_add_subt[31]), .Y(n2118) );
AO22XLTS U7365 ( .A0(n5814), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[31]), .B0(n5877), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[31]), .Y(n2116) );
OAI2BB2XLTS U7366 ( .B0(n5807), .B1(n5816), .A0N(n5815), .A1N(
result_add_subt[12]), .Y(n2115) );
CLKBUFX2TS U7367 ( .A(n5838), .Y(n5861) );
AO22XLTS U7368 ( .A0(n5814), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]), .B0(n5861), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n2113) );
OAI2BB2XLTS U7369 ( .B0(n5808), .B1(n5816), .A0N(n5815), .A1N(
result_add_subt[15]), .Y(n2112) );
AO22XLTS U7370 ( .A0(n5814), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]), .B0(n5861), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n2110) );
OAI2BB2XLTS U7371 ( .B0(n5809), .B1(n5816), .A0N(n5815), .A1N(
result_add_subt[30]), .Y(n2109) );
AO22XLTS U7372 ( .A0(n5814), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[30]), .B0(n5861), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[30]), .Y(n2107) );
OAI2BB2XLTS U7373 ( .B0(n5810), .B1(n5816), .A0N(n5815), .A1N(
result_add_subt[17]), .Y(n2106) );
AO22XLTS U7374 ( .A0(n5814), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]), .B0(n5861), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n2104) );
OAI2BB2XLTS U7375 ( .B0(n5811), .B1(n5816), .A0N(n5815), .A1N(
result_add_subt[32]), .Y(n2103) );
AO22XLTS U7376 ( .A0(n5814), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[32]), .B0(n5861), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[32]), .Y(n2101) );
OAI2BB2XLTS U7377 ( .B0(n5812), .B1(n5816), .A0N(n5815), .A1N(
result_add_subt[14]), .Y(n2100) );
AO22XLTS U7378 ( .A0(n5814), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]), .B0(n5861), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n2098) );
OAI2BB2XLTS U7379 ( .B0(n5813), .B1(n5816), .A0N(n5815), .A1N(
result_add_subt[29]), .Y(n2097) );
AO22XLTS U7380 ( .A0(n5814), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[29]), .B0(n5861), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[29]), .Y(n2095) );
OAI2BB2XLTS U7381 ( .B0(n5817), .B1(n5816), .A0N(n5815), .A1N(
result_add_subt[13]), .Y(n2094) );
OAI21XLTS U7382 ( .A0(n5821), .A1(n5818), .B0(n6022), .Y(n5819) );
OAI211XLTS U7383 ( .A0(n5821), .A1(n5820), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .C0(n5819), .Y(n5822) );
OAI2BB1X1TS U7384 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP), .A1N(
n5823), .B0(n5822), .Y(n2093) );
CLKBUFX2TS U7385 ( .A(n6035), .Y(n5858) );
INVX2TS U7386 ( .A(n5858), .Y(n5836) );
AO22XLTS U7387 ( .A0(n5836), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP),
.B0(n5861), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1), .Y(n2092)
);
AO22XLTS U7388 ( .A0(n5825), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1),
.B0(n5824), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2), .Y(n2091)
);
AO22XLTS U7389 ( .A0(n5871), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2),
.B0(n5826), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG), .Y(n2090)
);
AO22XLTS U7390 ( .A0(n3194), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG),
.B0(n5827), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM), .Y(n2089)
);
AO22XLTS U7391 ( .A0(n5874), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM),
.B0(n5873), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(
n2088) );
OAI21XLTS U7392 ( .A0(n5830), .A1(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n5829), .Y(n5831)
);
OAI2BB1X1TS U7393 ( .A0N(n6043), .A1N(result_add_subt[63]), .B0(n5831), .Y(
n2087) );
AO22XLTS U7394 ( .A0(n5836), .A1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP),
.B0(n5861), .B1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1), .Y(n2085)
);
CLKBUFX2TS U7395 ( .A(n6094), .Y(n5882) );
AO22XLTS U7396 ( .A0(n5883), .A1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1),
.B0(n5882), .B1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2), .Y(n2084)
);
CLKBUFX2TS U7397 ( .A(n5846), .Y(n5843) );
OAI2BB2XLTS U7398 ( .B0(n5832), .B1(n5844), .A0N(n5843), .A1N(
result_add_subt[19]), .Y(n2021) );
CLKBUFX2TS U7399 ( .A(n5838), .Y(n5856) );
AO22XLTS U7400 ( .A0(n5836), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]), .B0(n5856), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n2019) );
AO22XLTS U7401 ( .A0(n5836), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]), .B0(n5856), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n2017) );
OAI2BB2XLTS U7402 ( .B0(n5833), .B1(n5844), .A0N(n5843), .A1N(
result_add_subt[18]), .Y(n2014) );
AO22XLTS U7403 ( .A0(n5836), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]), .B0(n5856), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n2012) );
AO22XLTS U7404 ( .A0(n5836), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]), .B0(n5856), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n2010) );
OAI2BB2XLTS U7405 ( .B0(n5834), .B1(n5844), .A0N(n5843), .A1N(
result_add_subt[16]), .Y(n2007) );
AO22XLTS U7406 ( .A0(n5836), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]), .B0(n5856), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n2005) );
AO22XLTS U7407 ( .A0(n5836), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]), .B0(n5856), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n2003) );
OAI2BB2XLTS U7408 ( .B0(n5835), .B1(n5844), .A0N(n5843), .A1N(
result_add_subt[10]), .Y(n2000) );
AO22XLTS U7409 ( .A0(n5836), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]), .B0(n5856), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1998) );
AO22XLTS U7410 ( .A0(n5836), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]), .B0(n5856), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1996) );
OAI2BB2XLTS U7411 ( .B0(n5837), .B1(n5844), .A0N(n5843), .A1N(
result_add_subt[7]), .Y(n1993) );
CLKBUFX2TS U7412 ( .A(n5838), .Y(n5853) );
INVX2TS U7413 ( .A(n5853), .Y(n5889) );
AO22XLTS U7414 ( .A0(n5889), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]), .B0(n5856), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1991)
);
CLKBUFX2TS U7415 ( .A(n5838), .Y(n5888) );
AO22XLTS U7416 ( .A0(n5889), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]), .B0(n5888), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1989) );
OAI2BB2XLTS U7417 ( .B0(n5839), .B1(n5844), .A0N(n5843), .A1N(
result_add_subt[6]), .Y(n1986) );
AO22XLTS U7418 ( .A0(n5889), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]), .B0(n5888), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1984)
);
AO22XLTS U7419 ( .A0(n5889), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]), .B0(n5888), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1982) );
OAI2BB2XLTS U7420 ( .B0(n5840), .B1(n5844), .A0N(n5843), .A1N(
result_add_subt[5]), .Y(n1979) );
AO22XLTS U7421 ( .A0(n5889), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]), .B0(n5888), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1977)
);
OAI2BB2XLTS U7422 ( .B0(n5841), .B1(n5844), .A0N(n5843), .A1N(
result_add_subt[20]), .Y(n1976) );
AO22XLTS U7423 ( .A0(n5889), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]), .B0(n5888), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1974) );
AO22XLTS U7424 ( .A0(n5889), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]), .B0(n5888), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1972) );
OAI2BB2XLTS U7425 ( .B0(n5842), .B1(n5844), .A0N(n5843), .A1N(
result_add_subt[8]), .Y(n1969) );
AO22XLTS U7426 ( .A0(n5889), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]), .B0(n5888), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1967)
);
OAI2BB2XLTS U7427 ( .B0(n5845), .B1(n5844), .A0N(n5843), .A1N(
result_add_subt[21]), .Y(n1966) );
AO22XLTS U7428 ( .A0(n5889), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]), .B0(n5888), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1964) );
INVX2TS U7429 ( .A(n5888), .Y(n5854) );
AO22XLTS U7430 ( .A0(n5854), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]), .B0(n5853), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1962) );
CLKBUFX2TS U7431 ( .A(n5846), .Y(n5862) );
OAI2BB2XLTS U7432 ( .B0(n5847), .B1(n5863), .A0N(n5862), .A1N(
result_add_subt[9]), .Y(n1959) );
AO22XLTS U7433 ( .A0(n5854), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]), .B0(n5853), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n1957)
);
AO22XLTS U7434 ( .A0(n5854), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]), .B0(n5853), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1955) );
OAI2BB2XLTS U7435 ( .B0(n5848), .B1(n5863), .A0N(n5862), .A1N(
result_add_subt[11]), .Y(n1952) );
AO22XLTS U7436 ( .A0(n5854), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]), .B0(n5853), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1950) );
OAI2BB2XLTS U7437 ( .B0(n5849), .B1(n5863), .A0N(n5862), .A1N(
result_add_subt[22]), .Y(n1949) );
AO22XLTS U7438 ( .A0(n5854), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]), .B0(n5853), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1947) );
AO22XLTS U7439 ( .A0(n5854), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]), .B0(n5853), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1945) );
OAI2BB2XLTS U7440 ( .B0(n5850), .B1(n5863), .A0N(n5862), .A1N(
result_add_subt[26]), .Y(n1942) );
AO22XLTS U7441 ( .A0(n5854), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]), .B0(n5853), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[26]), .Y(n1940) );
OAI2BB2XLTS U7442 ( .B0(n5851), .B1(n5863), .A0N(n5862), .A1N(
result_add_subt[27]), .Y(n1939) );
AO22XLTS U7443 ( .A0(n5854), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]), .B0(n5853), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[27]), .Y(n1937) );
OAI2BB2XLTS U7444 ( .B0(n5852), .B1(n5863), .A0N(n5862), .A1N(
result_add_subt[23]), .Y(n1936) );
AO22XLTS U7445 ( .A0(n5854), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .B0(n5853), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[23]), .Y(n1934) );
AO22XLTS U7446 ( .A0(n5854), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .B0(n5858), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1932) );
OAI2BB2XLTS U7447 ( .B0(n5855), .B1(n5863), .A0N(n5862), .A1N(
result_add_subt[24]), .Y(n1929) );
INVX2TS U7448 ( .A(n5856), .Y(n5860) );
AO22XLTS U7449 ( .A0(n5860), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]), .B0(n5858), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[24]), .Y(n1927) );
AO22XLTS U7450 ( .A0(n5860), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .B0(n5858), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1925) );
OAI2BB2XLTS U7451 ( .B0(n5857), .B1(n5863), .A0N(n5862), .A1N(
result_add_subt[25]), .Y(n1922) );
AO22XLTS U7452 ( .A0(n5860), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]), .B0(n5858), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[25]), .Y(n1920) );
AO22XLTS U7453 ( .A0(n5860), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .B0(n5858), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1918) );
AO22XLTS U7454 ( .A0(n5860), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .B0(n5858), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1914) );
AO22XLTS U7455 ( .A0(n5860), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .B0(n5858), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1910) );
AO22XLTS U7456 ( .A0(n5860), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]), .B0(n5858), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1906) );
AO22XLTS U7457 ( .A0(n5860), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]), .B0(n5858), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1902) );
AO22XLTS U7458 ( .A0(n5860), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]), .B0(n5868), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1898) );
OAI2BB2XLTS U7459 ( .B0(n5859), .B1(n5863), .A0N(n5862), .A1N(
result_add_subt[4]), .Y(n1895) );
AO22XLTS U7460 ( .A0(n5860), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]), .B0(n5868), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1893)
);
INVX2TS U7461 ( .A(n5861), .Y(n5876) );
AO22XLTS U7462 ( .A0(n5876), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]), .B0(n5868), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1891) );
OAI2BB2XLTS U7463 ( .B0(n5864), .B1(n5863), .A0N(n5862), .A1N(
result_add_subt[2]), .Y(n1888) );
AO22XLTS U7464 ( .A0(n5876), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]), .B0(n5868), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1886)
);
AO22XLTS U7465 ( .A0(n5876), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]), .B0(n5868), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1884) );
OAI2BB2XLTS U7466 ( .B0(n5865), .B1(n5866), .A0N(n6043), .A1N(
result_add_subt[1]), .Y(n1881) );
AO22XLTS U7467 ( .A0(n5876), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]), .B0(n5868), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n1879)
);
AO22XLTS U7468 ( .A0(n5876), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]), .B0(n5868), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1877) );
OAI2BB2XLTS U7469 ( .B0(n5867), .B1(n5866), .A0N(n6043), .A1N(
result_add_subt[0]), .Y(n1874) );
AO22XLTS U7470 ( .A0(n5876), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]), .B0(n5868), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1872)
);
AO22XLTS U7471 ( .A0(n5876), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]), .B0(n5868), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1870) );
AO22XLTS U7472 ( .A0(n5876), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP),
.B0(n5878), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1), .Y(n1866)
);
AO22XLTS U7473 ( .A0(n5883), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1),
.B0(n5882), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2), .Y(n1865)
);
AO22XLTS U7474 ( .A0(n5871), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2),
.B0(n5870), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG), .Y(n1864)
);
AO22XLTS U7475 ( .A0(n3194), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG),
.B0(n5872), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM), .Y(n1863)
);
AO22XLTS U7476 ( .A0(n5874), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM),
.B0(n5873), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2), .Y(
n1862) );
AO22XLTS U7477 ( .A0(n3193), .A1(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2), .B0(n5875), .B1(
zero_flag), .Y(n1861) );
AO22XLTS U7478 ( .A0(n5876), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]), .B0(n5878), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1859) );
AO22XLTS U7479 ( .A0(n5876), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]), .B0(n5878), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1857) );
INVX2TS U7480 ( .A(n5877), .Y(n5879) );
AO22XLTS U7481 ( .A0(n5879), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]), .B0(n5878), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1853) );
AO22XLTS U7482 ( .A0(n5879), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]), .B0(n5878), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1849) );
AO22XLTS U7483 ( .A0(n5879), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[32]), .B0(n5878), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[32]), .Y(n1845) );
AO22XLTS U7484 ( .A0(n5879), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]), .B0(n5878), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1841) );
AO22XLTS U7485 ( .A0(n5879), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]), .B0(n5878), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1837) );
AO22XLTS U7486 ( .A0(n5879), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]), .B0(n5878), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1833) );
AO22XLTS U7487 ( .A0(n5879), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]), .B0(n5881), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1829) );
AO22XLTS U7488 ( .A0(n5879), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[31]), .B0(n5881), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[31]), .Y(n1825) );
AO22XLTS U7489 ( .A0(n5879), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]), .B0(n5881), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1821) );
AO22XLTS U7490 ( .A0(n5879), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[37]), .B0(n5881), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[37]), .Y(n1817) );
AO22XLTS U7491 ( .A0(n5883), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[37]), .B0(n5882), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[37]), .Y(n1816) );
INVX2TS U7492 ( .A(n5880), .Y(n5884) );
AO22XLTS U7493 ( .A0(n5884), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[40]), .B0(n5881), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[40]), .Y(n1813) );
AO22XLTS U7494 ( .A0(n5883), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[40]), .B0(n5882), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[40]), .Y(n1812) );
AO22XLTS U7495 ( .A0(n5884), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[38]), .B0(n5881), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[38]), .Y(n1809) );
AO22XLTS U7496 ( .A0(n5883), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[38]), .B0(n5882), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[38]), .Y(n1808) );
AO22XLTS U7497 ( .A0(n5884), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[41]), .B0(n5881), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[41]), .Y(n1805) );
AO22XLTS U7498 ( .A0(n5883), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[41]), .B0(n5882), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[41]), .Y(n1804) );
AO22XLTS U7499 ( .A0(n5884), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[39]), .B0(n5881), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[39]), .Y(n1801) );
AO22XLTS U7500 ( .A0(n5883), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[39]), .B0(n5882), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[39]), .Y(n1800) );
AO22XLTS U7501 ( .A0(n5884), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[36]), .B0(n5881), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[36]), .Y(n1797) );
AO22XLTS U7502 ( .A0(n5883), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[36]), .B0(n5882), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[36]), .Y(n1796) );
AO22XLTS U7503 ( .A0(n5884), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[43]), .B0(n5885), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[43]), .Y(n1793) );
AO22XLTS U7504 ( .A0(n5883), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[43]), .B0(n5882), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[43]), .Y(n1792) );
AO22XLTS U7505 ( .A0(n5884), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[42]), .B0(n5885), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[42]), .Y(n1789) );
AO22XLTS U7506 ( .A0(n5883), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[42]), .B0(n5882), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[42]), .Y(n1788) );
AO22XLTS U7507 ( .A0(n5884), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[35]), .B0(n5885), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[35]), .Y(n1785) );
AO22XLTS U7508 ( .A0(n5884), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[46]), .B0(n5885), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[46]), .Y(n1781) );
AO22XLTS U7509 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[46]), .B0(n5890), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[46]), .Y(n1780) );
AO22XLTS U7510 ( .A0(n5884), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[45]), .B0(n5885), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[45]), .Y(n1777) );
AO22XLTS U7511 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[45]), .B0(n5890), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[45]), .Y(n1776) );
AO22XLTS U7512 ( .A0(n5887), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[34]), .B0(n5885), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[34]), .Y(n1773) );
AO22XLTS U7513 ( .A0(n5887), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]), .B0(n5885), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1769) );
AO22XLTS U7514 ( .A0(n5887), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[44]), .B0(n5885), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[44]), .Y(n1765) );
AO22XLTS U7515 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[44]), .B0(n5890), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[44]), .Y(n1764) );
AO22XLTS U7516 ( .A0(n5887), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[33]), .B0(n5885), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[33]), .Y(n1761) );
AO22XLTS U7517 ( .A0(n5887), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[48]), .B0(n5886), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[48]), .Y(n1757) );
AO22XLTS U7518 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[48]), .B0(n5890), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[48]), .Y(n1756) );
AO22XLTS U7519 ( .A0(n5887), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[49]), .B0(n5886), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[49]), .Y(n1753) );
AO22XLTS U7520 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[49]), .B0(n5890), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[49]), .Y(n1752) );
AO22XLTS U7521 ( .A0(n5887), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[47]), .B0(n5886), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[47]), .Y(n1749) );
AO22XLTS U7522 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[47]), .B0(n5890), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[47]), .Y(n1748) );
AO22XLTS U7523 ( .A0(n5887), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[50]), .B0(n5886), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[50]), .Y(n1745) );
AO22XLTS U7524 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[50]), .B0(n5890), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[50]), .Y(n1744) );
AO22XLTS U7525 ( .A0(n5889), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[51]), .B0(n5888), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[51]), .Y(n1741) );
AO22XLTS U7526 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[51]), .B0(n5890), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[51]), .Y(n1740) );
initial $sdf_annotate("CORDIC_Arch3_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2a (
VPWR,
VGND,
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_1_V
`define SKY130_FD_SC_HD__FILL_1_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fill_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fill_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_dmac_response_manager #(
parameter DMA_DATA_WIDTH_SRC = 64,
parameter DMA_DATA_WIDTH_DEST = 64,
parameter DMA_LENGTH_WIDTH = 24,
parameter BYTES_PER_BURST_WIDTH = 7,
parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8),
parameter ASYNC_CLK_DEST_REQ = 1
)(
// Interface to destination side
input dest_clk,
input dest_resetn,
input dest_response_valid,
output dest_response_ready,
input [1:0] dest_response_resp,
input dest_response_partial,
input dest_response_resp_eot,
input [BYTES_PER_BURST_WIDTH-1:0] dest_response_data_burst_length,
// Interface to processor
input req_clk,
input req_resetn,
output response_eot,
output reg [BYTES_PER_BURST_WIDTH-1:0] measured_burst_length = 'h0,
output response_partial,
output reg response_valid = 1'b0,
input response_ready,
// Interface to requester side
input completion_req_valid,
input completion_req_last,
input [1:0] completion_transfer_id
);
localparam STATE_IDLE = 3'h0;
localparam STATE_ACC = 3'h1;
localparam STATE_WRITE_RESPR = 3'h2;
localparam STATE_ZERO_COMPL = 3'h3;
localparam STATE_WRITE_ZRCMPL = 3'h4;
reg [2:0] state = STATE_IDLE;
reg [2:0] nx_state;
localparam DEST_SRC_RATIO = DMA_DATA_WIDTH_DEST/DMA_DATA_WIDTH_SRC;
localparam DEST_SRC_RATIO_WIDTH = DEST_SRC_RATIO > 64 ? 7 :
DEST_SRC_RATIO > 32 ? 6 :
DEST_SRC_RATIO > 16 ? 5 :
DEST_SRC_RATIO > 8 ? 4 :
DEST_SRC_RATIO > 4 ? 3 :
DEST_SRC_RATIO > 2 ? 2 :
DEST_SRC_RATIO > 1 ? 1 : 0;
localparam BYTES_PER_BEAT_WIDTH = DEST_SRC_RATIO_WIDTH + BYTES_PER_BEAT_WIDTH_SRC;
localparam BURST_LEN_WIDTH = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH;
wire do_acc_st;
wire do_compl;
reg req_eot = 1'b0;
reg req_response_partial = 1'b0;
reg [BYTES_PER_BURST_WIDTH-1:0] req_response_dest_data_burst_length = 'h0;
wire response_dest_valid;
reg response_dest_ready = 1'b1;
wire [1:0] response_dest_resp;
wire response_dest_resp_eot;
wire [BYTES_PER_BURST_WIDTH-1:0] response_dest_data_burst_length;
wire [BURST_LEN_WIDTH-1:0] burst_lenght;
reg [BURST_LEN_WIDTH-1:0] burst_pointer_end;
reg [1:0] to_complete_count = 'h0;
reg [1:0] transfer_id = 'h0;
reg completion_req_last_found = 1'b0;
util_axis_fifo #(
.DATA_WIDTH(BYTES_PER_BURST_WIDTH+1+1),
.ADDRESS_WIDTH(0),
.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
) i_dest_response_fifo (
.s_axis_aclk(dest_clk),
.s_axis_aresetn(dest_resetn),
.s_axis_valid(dest_response_valid),
.s_axis_ready(dest_response_ready),
.s_axis_empty(),
.s_axis_data({dest_response_data_burst_length,
dest_response_partial,
dest_response_resp_eot}),
.s_axis_room(),
.m_axis_aclk(req_clk),
.m_axis_aresetn(req_resetn),
.m_axis_valid(response_dest_valid),
.m_axis_ready(response_dest_ready),
.m_axis_data({response_dest_data_burst_length,
response_dest_partial,
response_dest_resp_eot}),
.m_axis_level()
);
always @(posedge req_clk)
begin
if (response_dest_valid & response_dest_ready) begin
req_eot <= response_dest_resp_eot;
req_response_partial <= response_dest_partial;
req_response_dest_data_burst_length <= response_dest_data_burst_length;
end
end
always @(posedge req_clk)
begin
if (req_resetn == 1'b0) begin
response_dest_ready <= 1'b1;
end else begin
response_dest_ready <= (nx_state == STATE_IDLE);
end
end
assign response_eot = (state == STATE_WRITE_RESPR) ? req_eot : 1'b1;
assign response_partial = (state == STATE_WRITE_RESPR) ? req_response_partial : 1'b0;
always @(posedge req_clk)
begin
if (req_resetn == 1'b0) begin
response_valid <= 1'b0;
end else begin
if (nx_state == STATE_WRITE_RESPR || nx_state == STATE_WRITE_ZRCMPL) begin
response_valid <= 1'b1;
end else if (response_ready == 1'b1) begin
response_valid <= 1'b0;
end
end
end
// transform the free running pointer from burst memory into burst length
assign burst_lenght = req_response_dest_data_burst_length[BYTES_PER_BURST_WIDTH-1 -: BURST_LEN_WIDTH] -
burst_pointer_end - 1'b1;
always @(posedge req_clk)
begin
if (req_resetn == 1'b0) begin
burst_pointer_end <= {BURST_LEN_WIDTH{1'b1}};
end else if (state == STATE_ACC) begin
burst_pointer_end <= req_response_dest_data_burst_length[BYTES_PER_BURST_WIDTH-1 -: BURST_LEN_WIDTH];
end
end
always @(posedge req_clk)
begin
if (state == STATE_ZERO_COMPL) begin
measured_burst_length <= {BYTES_PER_BURST_WIDTH{1'b1}};
end else if (state == STATE_ACC) begin
measured_burst_length[BYTES_PER_BURST_WIDTH-1 -: BURST_LEN_WIDTH] <= burst_lenght;
measured_burst_length[BYTES_PER_BEAT_WIDTH-1 : 0] <=
req_response_dest_data_burst_length[BYTES_PER_BEAT_WIDTH-1: 0];
end
end
always @(*) begin
nx_state = state;
case (state)
STATE_IDLE: begin
if (response_dest_valid == 1'b1) begin
nx_state = STATE_ACC;
end else if (|to_complete_count) begin
if (transfer_id == completion_transfer_id)
nx_state = STATE_ZERO_COMPL;
end
end
STATE_ACC: begin
nx_state = STATE_WRITE_RESPR;
end
STATE_WRITE_RESPR: begin
if (response_ready == 1'b1) begin
nx_state = STATE_IDLE;
end
end
STATE_ZERO_COMPL: begin
if (|to_complete_count) begin
nx_state = STATE_WRITE_ZRCMPL;
end else begin
if (completion_req_last_found == 1'b1) begin
nx_state = STATE_IDLE;
end
end
end
STATE_WRITE_ZRCMPL:begin
if (response_ready == 1'b1) begin
nx_state = STATE_ZERO_COMPL;
end
end
default: begin
nx_state = STATE_IDLE;
end
endcase
end
always @(posedge req_clk) begin
if (req_resetn == 1'b0) begin
state <= STATE_IDLE;
end else begin
state <= nx_state;
end
end
assign do_compl = (state == STATE_WRITE_ZRCMPL) && response_ready;
// Once the last completion request from request generator is received
// we can wait for completions from the destination side
always @(posedge req_clk) begin
if (req_resetn == 1'b0) begin
completion_req_last_found <= 1'b0;
end else if (completion_req_valid) begin
completion_req_last_found <= completion_req_last;
end else if (state ==STATE_ZERO_COMPL && ~(|to_complete_count)) begin
completion_req_last_found <= 1'b0;
end
end
// Track transfers so we can tell when did the destination completed all its
// transfers
always @(posedge req_clk) begin
if (req_resetn == 1'b0) begin
transfer_id <= 'h0;
end else if ((state == STATE_ACC && req_eot) || do_compl) begin
transfer_id <= transfer_id + 1;
end
end
// Count how many transfers we need to complete
always @(posedge req_clk) begin
if (req_resetn == 1'b0) begin
to_complete_count <= 'h0;
end else if (completion_req_valid & ~do_compl) begin
to_complete_count <= to_complete_count + 1;
end else if (~completion_req_valid & do_compl) begin
to_complete_count <= to_complete_count - 1;
end
end
endmodule
|
// ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0.v
// This file was auto-generated from alt_mem_if_ddr3_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using SOPC Builder version 11.0sp1 208 at 2011.09.28.12:47:44
`timescale 1 ps / 1 ps
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0 (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_clk, // afi_clk.clk
output wire afi_half_clk, // afi_half_clk.clk
output wire afi_reset_n, // afi_reset.reset_n
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire [1:0] mem_dm, // .mem_dm
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [15:0] mem_dq, // .mem_dq
inout wire [1:0] mem_dqs, // .mem_dqs
inout wire [1:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire avl_ready, // avl.waitrequest_n
input wire avl_burstbegin, // .beginbursttransfer
input wire [23:0] avl_addr, // .address
output wire avl_rdata_valid, // .readdatavalid
output wire [63:0] avl_rdata, // .readdata
input wire [63:0] avl_wdata, // .writedata
input wire [7:0] avl_be, // .byteenable
input wire avl_read_req, // .read
input wire avl_write_req, // .write
input wire [2:0] avl_size, // .burstcount
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire oct_rdn, // oct.rdn
input wire oct_rup, // .rup
output wire local_powerdn_ack, // local_powerdown.local_powerdn_ack
input wire local_powerdn_req // .local_powerdn_req
);
wire [25:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire c0_afi_afi_cal_req; // c0:afi_cal_req -> p0:afi_cal_req
wire [5:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire [1:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire [1:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [1:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [5:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [63:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [1:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [1:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [1:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [5:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire [63:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [3:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [3:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [7:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_c0 c0 (
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.local_powerdn_ack (local_powerdn_ack), // local_powerdown.local_powerdn_ack
.local_powerdn_req (local_powerdn_req), // .local_powerdn_req
.avl_ready (avl_ready), // avl.waitrequest_n
.avl_burstbegin (avl_burstbegin), // .beginbursttransfer
.avl_addr (avl_addr), // .address
.avl_rdata_valid (avl_rdata_valid), // .readdatavalid
.avl_rdata (avl_rdata), // .readdata
.avl_wdata (avl_wdata), // .writedata
.avl_be (avl_be), // .byteenable
.avl_read_req (avl_read_req), // .read
.avl_write_req (avl_write_req), // .write
.avl_size (avl_size) // .burstcount
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.oct_rdn (oct_rdn), // oct.rdn
.oct_rup (oct_rup), // .rup
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.dll_delayctrl (), // (terminated)
.seriesterminationcontrol (), // (terminated)
.parallelterminationcontrol () // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_OV2_SYMBOL_V
`define SKY130_FD_SC_LP__SDFRTP_OV2_SYMBOL_V
/**
* sdfrtp_ov2: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtp_ov2 (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_OV2_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_V |
module cov_mhu
import bsg_cache_non_blocking_pkg::*;
(
input clk_i
, input reset_i
, input mhu_state_e mhu_state_r
, input data_mem_pkt_yumi_i
, input is_secondary
, input miss_fifo_v_i
, input tl_block_loading_i
);
covergroup cg_dequeue_mode @ (negedge clk_i iff mhu_state_r == DEQUEUE_MODE);
coverpoint data_mem_pkt_yumi_i;
coverpoint is_secondary;
coverpoint miss_fifo_v_i;
coverpoint tl_block_loading_i;
cross data_mem_pkt_yumi_i, is_secondary, miss_fifo_v_i, tl_block_loading_i {
ignore_bins non_secondary =
binsof(data_mem_pkt_yumi_i) intersect {1'b1} &&
binsof(is_secondary) intersect {1'b0};
ignore_bins tl_block_load =
binsof(tl_block_loading_i) intersect {1'b1} &&
binsof(data_mem_pkt_yumi_i) intersect {1'b1};
ignore_bins miss_fifo_not_v =
binsof(miss_fifo_v_i) intersect {1'b0} &&
(binsof(data_mem_pkt_yumi_i) intersect {1'b1} || binsof(is_secondary) intersect {1'b0});
}
endgroup
covergroup cg_scan_mode @ (negedge clk_i iff mhu_state_r == SCAN_MODE);
coverpoint miss_fifo_v_i;
coverpoint is_secondary;
coverpoint data_mem_pkt_yumi_i;
coverpoint tl_block_loading_i;
cross data_mem_pkt_yumi_i, is_secondary, miss_fifo_v_i, tl_block_loading_i {
ignore_bins miss_fifo_not_v =
binsof(miss_fifo_v_i) intersect {1'b0} &&
(binsof(data_mem_pkt_yumi_i) intersect {1'b1} || binsof(is_secondary) intersect {1'b0});
ignore_bins non_secondary =
binsof(data_mem_pkt_yumi_i) intersect {1'b1} &&
binsof(is_secondary) intersect {1'b0};
ignore_bins tl_block_load =
binsof(tl_block_loading_i) intersect {1'b1} &&
binsof(data_mem_pkt_yumi_i) intersect {1'b1};
}
endgroup
initial begin
cg_dequeue_mode dq = new;
cg_scan_mode sc = new;
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
//TODO: check with more then 1 hold/priority at a time
module rrp_arbiter #(
parameter WIDTH = 4
) (
input wire RST,
input wire CLK,
input wire [WIDTH-1:0] WRITE_REQ, // round robin
input wire [WIDTH-1:0] HOLD_REQ, // lower channels have higher priority, has to be high until read was granted
input wire [WIDTH*32-1:0] DATA_IN,
output wire[WIDTH-1:0] READ_GRANT,
input wire READY_OUT,
output wire WRITE_OUT,
output wire [31:0] DATA_OUT
);
//`include "../includes/log2func.v"
//localparam SEL_SIZE = log2(WIDTH);
integer m;
reg [WIDTH-1:0] prev_select; // one hot
reg [WIDTH-1:0] select; // one hot
reg hold;
wire WRITE_REQ_OR, HOLD_REQ_OR;
assign WRITE_REQ_OR = |WRITE_REQ;
assign HOLD_REQ_OR = |HOLD_REQ;
assign WRITE_OUT = |(WRITE_REQ & select & READ_GRANT);
//assign WRITE_OUT = HOLD_REQ_OR ? WRITE_REQ[0] : WRITE_REQ_OR;
always @(*) begin
select = prev_select;
if(HOLD_REQ_OR && !hold) begin
m = 0;
select = 1; // always start from lowest channel
while(!(HOLD_REQ & select) && (m < WIDTH)) begin
m = m + 1;
select = 1 << m;
end
end
else if(WRITE_REQ_OR && !hold) begin
m = 0;
select = prev_select << 1; // start from last channel + 1
if(select == 0) // 0 is not valid
select = 1;
while(!(WRITE_REQ & select) && (m < WIDTH)) begin
m = m + 1;
select = select << 1;
if(select == 0) // 0 is not valid
select = 1;
end
end
end
always @(posedge CLK) begin
if(RST)
prev_select <= (1 << (WIDTH - 1));
else if (WRITE_REQ_OR & !hold)
prev_select <= select;
end
always @(posedge CLK) begin
if(RST)
hold <= 0;
else if(READY_OUT)
hold <= 0;
else if (WRITE_OUT)
hold <= 1;
end
//wire [31:0] DATA_A [WIDTH-1:0];
wire [WIDTH-1:0] DATA_A [31:0]; // this will simplify the loop below
// generation of DATA_A
genvar i, j;
generate
for (i = 0; i < 32; i = i + 1) begin: gen
for (j = 0; j < WIDTH; j = j + 1) begin: gen2
assign DATA_A[i][j] = DATA_IN[j*32+i];
end
end
endgenerate
// selecting bits for DATA_OUT
generate
for (i = 0; i < 32; i = i + 1) begin: gen3
assign DATA_OUT[i] = |(DATA_A[i] & select);
end
endgenerate
//assign DATA_OUT = DATA_A[select];
assign READ_GRANT = select & {WIDTH{READY_OUT}} & WRITE_REQ;
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: crc_accu
*/
module crc_accu #(parameter FPW=4)(
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----Input
//----------------------------------
input wire [FPW-1:0] tail,
input wire [(FPW*32)-1:0] d_in,
//----------------------------------
//----Output
//----------------------------------
output reg [31:0] crc_out
);
integer i_f;
reg [31:0] crc_temp [FPW:0];
wire [31:0] in [FPW-1:0];
genvar f;
generate
for(f=0;f<FPW;f=f+1) begin
assign in[f] = d_in[(f*32)+32-1:(f*32)];
end
endgenerate
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
`ifdef RESET_ALL
if (!res_n) begin
crc_out <= 32'h0;
end else
`endif
begin
crc_out <= 32'h0;
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
if(tail[i_f]) begin
crc_out <= crc_temp[i_f+1];
end
end
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if (!res_n)
crc_temp[0] <= 32'h0;
else
crc_temp[0] <= |tail ? 32'h0 : crc_temp[FPW];
end
always @(*)
begin
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
crc_temp[i_f+1][31] = in[i_f][31] ^ crc_temp[i_f][3]^crc_temp[i_f][5]^crc_temp[i_f][6]^crc_temp[i_f][8]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][14]^crc_temp[i_f][15]^crc_temp[i_f][17]^crc_temp[i_f][18]^crc_temp[i_f][19]^crc_temp[i_f][21]^crc_temp[i_f][26]^crc_temp[i_f][29];
crc_temp[i_f+1][30] = in[i_f][30] ^ crc_temp[i_f][2]^crc_temp[i_f][4]^crc_temp[i_f][5]^crc_temp[i_f][7]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][16]^crc_temp[i_f][17]^crc_temp[i_f][18]^crc_temp[i_f][20]^crc_temp[i_f][25]^crc_temp[i_f][28];
crc_temp[i_f+1][29] = in[i_f][29] ^ crc_temp[i_f][1]^crc_temp[i_f][4]^crc_temp[i_f][5]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][16]^crc_temp[i_f][18]^crc_temp[i_f][21]^crc_temp[i_f][24]^crc_temp[i_f][26]^crc_temp[i_f][27]^crc_temp[i_f][29];
crc_temp[i_f+1][28] = in[i_f][28] ^ crc_temp[i_f][0]^crc_temp[i_f][4]^crc_temp[i_f][5]^crc_temp[i_f][6]^crc_temp[i_f][9]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][18]^crc_temp[i_f][19]^crc_temp[i_f][20]^crc_temp[i_f][21]^crc_temp[i_f][23]^crc_temp[i_f][25]^crc_temp[i_f][28]^crc_temp[i_f][29]^crc_temp[i_f][31];
crc_temp[i_f+1][27] = in[i_f][27] ^ crc_temp[i_f][4]^crc_temp[i_f][6]^crc_temp[i_f][10]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][15]^crc_temp[i_f][20]^crc_temp[i_f][21]^crc_temp[i_f][22]^crc_temp[i_f][24]^crc_temp[i_f][26]^crc_temp[i_f][27]^crc_temp[i_f][28]^crc_temp[i_f][29]^crc_temp[i_f][30]^crc_temp[i_f][31];
crc_temp[i_f+1][26] = in[i_f][26] ^ crc_temp[i_f][3]^crc_temp[i_f][5]^crc_temp[i_f][9]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][19]^crc_temp[i_f][20]^crc_temp[i_f][21]^crc_temp[i_f][23]^crc_temp[i_f][25]^crc_temp[i_f][26]^crc_temp[i_f][27]^crc_temp[i_f][28]^crc_temp[i_f][29]^crc_temp[i_f][30]^crc_temp[i_f][31];
crc_temp[i_f+1][25] = in[i_f][25] ^ crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][4]^crc_temp[i_f][5]^crc_temp[i_f][6]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][15]^crc_temp[i_f][17]^crc_temp[i_f][20]^crc_temp[i_f][21]^crc_temp[i_f][22]^crc_temp[i_f][24]^crc_temp[i_f][25]^crc_temp[i_f][27]^crc_temp[i_f][28]^crc_temp[i_f][30]^crc_temp[i_f][31];
crc_temp[i_f+1][24] = in[i_f][24] ^ crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][4]^crc_temp[i_f][5]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][16]^crc_temp[i_f][19]^crc_temp[i_f][20]^crc_temp[i_f][21]^crc_temp[i_f][23]^crc_temp[i_f][24]^crc_temp[i_f][26]^crc_temp[i_f][27]^crc_temp[i_f][29]^crc_temp[i_f][30];
crc_temp[i_f+1][23] = in[i_f][23] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][4]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][15]^crc_temp[i_f][18]^crc_temp[i_f][19]^crc_temp[i_f][20]^crc_temp[i_f][22]^crc_temp[i_f][23]^crc_temp[i_f][25]^crc_temp[i_f][26]^crc_temp[i_f][28]^crc_temp[i_f][29];
crc_temp[i_f+1][22] = in[i_f][22] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][14]^crc_temp[i_f][17]^crc_temp[i_f][18]^crc_temp[i_f][19]^crc_temp[i_f][21]^crc_temp[i_f][22]^crc_temp[i_f][24]^crc_temp[i_f][25]^crc_temp[i_f][27]^crc_temp[i_f][28];
crc_temp[i_f+1][21] = in[i_f][21] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][8]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][13]^crc_temp[i_f][16]^crc_temp[i_f][17]^crc_temp[i_f][18]^crc_temp[i_f][20]^crc_temp[i_f][21]^crc_temp[i_f][23]^crc_temp[i_f][24]^crc_temp[i_f][26]^crc_temp[i_f][27];
crc_temp[i_f+1][20] = in[i_f][20] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][7]^crc_temp[i_f][8]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][12]^crc_temp[i_f][15]^crc_temp[i_f][16]^crc_temp[i_f][17]^crc_temp[i_f][19]^crc_temp[i_f][20]^crc_temp[i_f][22]^crc_temp[i_f][23]^crc_temp[i_f][25]^crc_temp[i_f][26]^crc_temp[i_f][31];
crc_temp[i_f+1][19] = in[i_f][19] ^ crc_temp[i_f][0]^crc_temp[i_f][3]^crc_temp[i_f][5]^crc_temp[i_f][7]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][16]^crc_temp[i_f][17]^crc_temp[i_f][22]^crc_temp[i_f][24]^crc_temp[i_f][25]^crc_temp[i_f][26]^crc_temp[i_f][29]^crc_temp[i_f][30];
crc_temp[i_f+1][18] = in[i_f][18] ^ crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][4]^crc_temp[i_f][5]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][14]^crc_temp[i_f][16]^crc_temp[i_f][17]^crc_temp[i_f][18]^crc_temp[i_f][19]^crc_temp[i_f][23]^crc_temp[i_f][24]^crc_temp[i_f][25]^crc_temp[i_f][26]^crc_temp[i_f][28];
crc_temp[i_f+1][17] = in[i_f][17] ^ crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][4]^crc_temp[i_f][8]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][13]^crc_temp[i_f][15]^crc_temp[i_f][16]^crc_temp[i_f][17]^crc_temp[i_f][18]^crc_temp[i_f][22]^crc_temp[i_f][23]^crc_temp[i_f][24]^crc_temp[i_f][25]^crc_temp[i_f][27]^crc_temp[i_f][31];
crc_temp[i_f+1][16] = in[i_f][16] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][5]^crc_temp[i_f][6]^crc_temp[i_f][7]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][16]^crc_temp[i_f][18]^crc_temp[i_f][19]^crc_temp[i_f][22]^crc_temp[i_f][23]^crc_temp[i_f][24]^crc_temp[i_f][29]^crc_temp[i_f][30]^crc_temp[i_f][31];
crc_temp[i_f+1][15] = in[i_f][15] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][3]^crc_temp[i_f][4]^crc_temp[i_f][9]^crc_temp[i_f][14]^crc_temp[i_f][19]^crc_temp[i_f][22]^crc_temp[i_f][23]^crc_temp[i_f][26]^crc_temp[i_f][28]^crc_temp[i_f][30]^crc_temp[i_f][31];
crc_temp[i_f+1][14] = in[i_f][14] ^ crc_temp[i_f][0]^crc_temp[i_f][2]^crc_temp[i_f][5]^crc_temp[i_f][6]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][15]^crc_temp[i_f][17]^crc_temp[i_f][19]^crc_temp[i_f][22]^crc_temp[i_f][25]^crc_temp[i_f][26]^crc_temp[i_f][27]^crc_temp[i_f][30]^crc_temp[i_f][31];
crc_temp[i_f+1][13] = in[i_f][13] ^ crc_temp[i_f][1]^crc_temp[i_f][4]^crc_temp[i_f][5]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][16]^crc_temp[i_f][18]^crc_temp[i_f][21]^crc_temp[i_f][24]^crc_temp[i_f][25]^crc_temp[i_f][26]^crc_temp[i_f][29]^crc_temp[i_f][30];
crc_temp[i_f+1][12] = in[i_f][12] ^ crc_temp[i_f][0]^crc_temp[i_f][3]^crc_temp[i_f][4]^crc_temp[i_f][8]^crc_temp[i_f][9]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][15]^crc_temp[i_f][17]^crc_temp[i_f][20]^crc_temp[i_f][23]^crc_temp[i_f][24]^crc_temp[i_f][25]^crc_temp[i_f][28]^crc_temp[i_f][29]^crc_temp[i_f][31];
crc_temp[i_f+1][11] = in[i_f][11] ^ crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][7]^crc_temp[i_f][8]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][14]^crc_temp[i_f][16]^crc_temp[i_f][19]^crc_temp[i_f][22]^crc_temp[i_f][23]^crc_temp[i_f][24]^crc_temp[i_f][27]^crc_temp[i_f][28]^crc_temp[i_f][30];
crc_temp[i_f+1][10] = in[i_f][10] ^ crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][5]^crc_temp[i_f][7]^crc_temp[i_f][8]^crc_temp[i_f][9]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][17]^crc_temp[i_f][19]^crc_temp[i_f][22]^crc_temp[i_f][23]^crc_temp[i_f][27];
crc_temp[i_f+1][ 9] = in[i_f][ 9] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][4]^crc_temp[i_f][5]^crc_temp[i_f][7]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][15]^crc_temp[i_f][16]^crc_temp[i_f][17]^crc_temp[i_f][19]^crc_temp[i_f][22]^crc_temp[i_f][29]^crc_temp[i_f][31];
crc_temp[i_f+1][ 8] = in[i_f][ 8] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][4]^crc_temp[i_f][6]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][15]^crc_temp[i_f][16]^crc_temp[i_f][18]^crc_temp[i_f][21]^crc_temp[i_f][28]^crc_temp[i_f][30];
crc_temp[i_f+1][ 7] = in[i_f][ 7] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][5]^crc_temp[i_f][8]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][14]^crc_temp[i_f][15]^crc_temp[i_f][17]^crc_temp[i_f][20]^crc_temp[i_f][27]^crc_temp[i_f][29]^crc_temp[i_f][31];
crc_temp[i_f+1][ 6] = in[i_f][ 6] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][4]^crc_temp[i_f][5]^crc_temp[i_f][6]^crc_temp[i_f][7]^crc_temp[i_f][9]^crc_temp[i_f][12]^crc_temp[i_f][13]^crc_temp[i_f][15]^crc_temp[i_f][16]^crc_temp[i_f][17]^crc_temp[i_f][18]^crc_temp[i_f][21]^crc_temp[i_f][28]^crc_temp[i_f][29]^crc_temp[i_f][30]^crc_temp[i_f][31];
crc_temp[i_f+1][ 5] = in[i_f][ 5] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][4]^crc_temp[i_f][10]^crc_temp[i_f][12]^crc_temp[i_f][16]^crc_temp[i_f][18]^crc_temp[i_f][19]^crc_temp[i_f][20]^crc_temp[i_f][21]^crc_temp[i_f][26]^crc_temp[i_f][27]^crc_temp[i_f][28]^crc_temp[i_f][30];
crc_temp[i_f+1][ 4] = in[i_f][ 4] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][3]^crc_temp[i_f][9]^crc_temp[i_f][11]^crc_temp[i_f][15]^crc_temp[i_f][17]^crc_temp[i_f][18]^crc_temp[i_f][19]^crc_temp[i_f][20]^crc_temp[i_f][25]^crc_temp[i_f][26]^crc_temp[i_f][27]^crc_temp[i_f][29]^crc_temp[i_f][31];
crc_temp[i_f+1][ 3] = in[i_f][ 3] ^ crc_temp[i_f][0]^crc_temp[i_f][2]^crc_temp[i_f][3]^crc_temp[i_f][5]^crc_temp[i_f][6]^crc_temp[i_f][11]^crc_temp[i_f][15]^crc_temp[i_f][16]^crc_temp[i_f][21]^crc_temp[i_f][24]^crc_temp[i_f][25]^crc_temp[i_f][28]^crc_temp[i_f][29]^crc_temp[i_f][30]^crc_temp[i_f][31];
crc_temp[i_f+1][ 2] = in[i_f][ 2] ^ crc_temp[i_f][1]^crc_temp[i_f][2]^crc_temp[i_f][4]^crc_temp[i_f][5]^crc_temp[i_f][10]^crc_temp[i_f][14]^crc_temp[i_f][15]^crc_temp[i_f][20]^crc_temp[i_f][23]^crc_temp[i_f][24]^crc_temp[i_f][27]^crc_temp[i_f][28]^crc_temp[i_f][29]^crc_temp[i_f][30]^crc_temp[i_f][31];
crc_temp[i_f+1][ 1] = in[i_f][ 1] ^ crc_temp[i_f][0]^crc_temp[i_f][1]^crc_temp[i_f][4]^crc_temp[i_f][5]^crc_temp[i_f][6]^crc_temp[i_f][8]^crc_temp[i_f][9]^crc_temp[i_f][10]^crc_temp[i_f][11]^crc_temp[i_f][13]^crc_temp[i_f][15]^crc_temp[i_f][17]^crc_temp[i_f][18]^crc_temp[i_f][21]^crc_temp[i_f][22]^crc_temp[i_f][23]^crc_temp[i_f][27]^crc_temp[i_f][28]^crc_temp[i_f][30]^crc_temp[i_f][31];
crc_temp[i_f+1][ 0] = in[i_f][ 0] ^ crc_temp[i_f][0]^crc_temp[i_f][4]^crc_temp[i_f][6]^crc_temp[i_f][7]^crc_temp[i_f][9]^crc_temp[i_f][11]^crc_temp[i_f][12]^crc_temp[i_f][15]^crc_temp[i_f][16]^crc_temp[i_f][18]^crc_temp[i_f][19]^crc_temp[i_f][20]^crc_temp[i_f][22]^crc_temp[i_f][27]^crc_temp[i_f][30];
end
end
endmodule
|
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module rptr_empty
#(
parameter ADDRSIZE = 4
)(
input wire rclk,
input wire rrst_n,
input wire rinc,
input wire [ADDRSIZE :0] rq2_wptr,
output reg rempty,
output reg arempty,
output wire [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr
);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext, rgraynextm1;
wire arempty_val, rempty_val;
//-------------------
// GRAYSTYLE2 pointer
//-------------------
always @(posedge rclk or negedge rrst_n) begin
if (!rrst_n)
{rbin, rptr} <= 0;
else
{rbin, rptr} <= {rbinnext, rgraynext};
end
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext >> 1) ^ rbinnext;
assign rgraynextm1 = ((rbinnext + 1'b1) >> 1) ^ (rbinnext + 1'b1);
//---------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//---------------------------------------------------------------
assign rempty_val = (rgraynext == rq2_wptr);
assign arempty_val = (rgraynextm1 == rq2_wptr);
always @ (posedge rclk or negedge rrst_n) begin
if (!rrst_n) begin
arempty <= 1'b0;
rempty <= 1'b1;
end
else begin
arempty <= arempty_val;
rempty <= rempty_val;
end
end
endmodule
`resetall
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_set_addr_map O 1 const
// slave_awready O 1 reg
// slave_wready O 1 reg
// slave_bvalid O 1 reg
// slave_bid O 4 reg
// slave_bresp O 2 reg
// slave_arready O 1 reg
// slave_rvalid O 1 reg
// slave_rid O 4 reg
// slave_rdata O 64 reg
// slave_rresp O 2 reg
// slave_rlast O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_addr_map_addr_base I 64 reg
// set_addr_map_addr_lim I 64 reg
// slave_awvalid I 1
// slave_awid I 4 reg
// slave_awaddr I 64 reg
// slave_awlen I 8 reg
// slave_awsize I 3 reg
// slave_awburst I 2 reg
// slave_awlock I 1 reg
// slave_awcache I 4 reg
// slave_awprot I 3 reg
// slave_awqos I 4 reg
// slave_awregion I 4 reg
// slave_wvalid I 1
// slave_wdata I 64 reg
// slave_wstrb I 8 reg
// slave_wlast I 1 reg
// slave_bready I 1
// slave_arvalid I 1
// slave_arid I 4 reg
// slave_araddr I 64 reg
// slave_arlen I 8 reg
// slave_arsize I 3 reg
// slave_arburst I 2 reg
// slave_arlock I 1 reg
// slave_arcache I 4 reg
// slave_arprot I 3 reg
// slave_arqos I 4 reg
// slave_arregion I 4 reg
// slave_rready I 1
// EN_set_addr_map I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkBoot_ROM(CLK,
RST_N,
set_addr_map_addr_base,
set_addr_map_addr_lim,
EN_set_addr_map,
RDY_set_addr_map,
slave_awvalid,
slave_awid,
slave_awaddr,
slave_awlen,
slave_awsize,
slave_awburst,
slave_awlock,
slave_awcache,
slave_awprot,
slave_awqos,
slave_awregion,
slave_awready,
slave_wvalid,
slave_wdata,
slave_wstrb,
slave_wlast,
slave_wready,
slave_bvalid,
slave_bid,
slave_bresp,
slave_bready,
slave_arvalid,
slave_arid,
slave_araddr,
slave_arlen,
slave_arsize,
slave_arburst,
slave_arlock,
slave_arcache,
slave_arprot,
slave_arqos,
slave_arregion,
slave_arready,
slave_rvalid,
slave_rid,
slave_rdata,
slave_rresp,
slave_rlast,
slave_rready);
input CLK;
input RST_N;
// action method set_addr_map
input [63 : 0] set_addr_map_addr_base;
input [63 : 0] set_addr_map_addr_lim;
input EN_set_addr_map;
output RDY_set_addr_map;
// action method slave_m_awvalid
input slave_awvalid;
input [3 : 0] slave_awid;
input [63 : 0] slave_awaddr;
input [7 : 0] slave_awlen;
input [2 : 0] slave_awsize;
input [1 : 0] slave_awburst;
input slave_awlock;
input [3 : 0] slave_awcache;
input [2 : 0] slave_awprot;
input [3 : 0] slave_awqos;
input [3 : 0] slave_awregion;
// value method slave_m_awready
output slave_awready;
// action method slave_m_wvalid
input slave_wvalid;
input [63 : 0] slave_wdata;
input [7 : 0] slave_wstrb;
input slave_wlast;
// value method slave_m_wready
output slave_wready;
// value method slave_m_bvalid
output slave_bvalid;
// value method slave_m_bid
output [3 : 0] slave_bid;
// value method slave_m_bresp
output [1 : 0] slave_bresp;
// value method slave_m_buser
// action method slave_m_bready
input slave_bready;
// action method slave_m_arvalid
input slave_arvalid;
input [3 : 0] slave_arid;
input [63 : 0] slave_araddr;
input [7 : 0] slave_arlen;
input [2 : 0] slave_arsize;
input [1 : 0] slave_arburst;
input slave_arlock;
input [3 : 0] slave_arcache;
input [2 : 0] slave_arprot;
input [3 : 0] slave_arqos;
input [3 : 0] slave_arregion;
// value method slave_m_arready
output slave_arready;
// value method slave_m_rvalid
output slave_rvalid;
// value method slave_m_rid
output [3 : 0] slave_rid;
// value method slave_m_rdata
output [63 : 0] slave_rdata;
// value method slave_m_rresp
output [1 : 0] slave_rresp;
// value method slave_m_rlast
output slave_rlast;
// value method slave_m_ruser
// action method slave_m_rready
input slave_rready;
// signals for module outputs
wire [63 : 0] slave_rdata;
wire [3 : 0] slave_bid, slave_rid;
wire [1 : 0] slave_bresp, slave_rresp;
wire RDY_set_addr_map,
slave_arready,
slave_awready,
slave_bvalid,
slave_rlast,
slave_rvalid,
slave_wready;
// register rg_addr_base
reg [63 : 0] rg_addr_base;
wire [63 : 0] rg_addr_base$D_IN;
wire rg_addr_base$EN;
// register rg_addr_lim
reg [63 : 0] rg_addr_lim;
wire [63 : 0] rg_addr_lim$D_IN;
wire rg_addr_lim$EN;
// register rg_module_ready
reg rg_module_ready;
wire rg_module_ready$D_IN, rg_module_ready$EN;
// ports of submodule slave_xactor_f_rd_addr
wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT;
wire slave_xactor_f_rd_addr$CLR,
slave_xactor_f_rd_addr$DEQ,
slave_xactor_f_rd_addr$EMPTY_N,
slave_xactor_f_rd_addr$ENQ,
slave_xactor_f_rd_addr$FULL_N;
// ports of submodule slave_xactor_f_rd_data
wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT;
wire slave_xactor_f_rd_data$CLR,
slave_xactor_f_rd_data$DEQ,
slave_xactor_f_rd_data$EMPTY_N,
slave_xactor_f_rd_data$ENQ,
slave_xactor_f_rd_data$FULL_N;
// ports of submodule slave_xactor_f_wr_addr
wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT;
wire slave_xactor_f_wr_addr$CLR,
slave_xactor_f_wr_addr$DEQ,
slave_xactor_f_wr_addr$EMPTY_N,
slave_xactor_f_wr_addr$ENQ,
slave_xactor_f_wr_addr$FULL_N;
// ports of submodule slave_xactor_f_wr_data
wire [72 : 0] slave_xactor_f_wr_data$D_IN;
wire slave_xactor_f_wr_data$CLR,
slave_xactor_f_wr_data$DEQ,
slave_xactor_f_wr_data$EMPTY_N,
slave_xactor_f_wr_data$ENQ,
slave_xactor_f_wr_data$FULL_N;
// ports of submodule slave_xactor_f_wr_resp
wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT;
wire slave_xactor_f_wr_resp$CLR,
slave_xactor_f_wr_resp$DEQ,
slave_xactor_f_wr_resp$EMPTY_N,
slave_xactor_f_wr_resp$ENQ,
slave_xactor_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_rl_process_rd_req,
CAN_FIRE_RL_rl_process_wr_req,
CAN_FIRE_set_addr_map,
CAN_FIRE_slave_m_arvalid,
CAN_FIRE_slave_m_awvalid,
CAN_FIRE_slave_m_bready,
CAN_FIRE_slave_m_rready,
CAN_FIRE_slave_m_wvalid,
WILL_FIRE_RL_rl_process_rd_req,
WILL_FIRE_RL_rl_process_wr_req,
WILL_FIRE_set_addr_map,
WILL_FIRE_slave_m_arvalid,
WILL_FIRE_slave_m_awvalid,
WILL_FIRE_slave_m_bready,
WILL_FIRE_slave_m_rready,
WILL_FIRE_slave_m_wvalid;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h899;
reg [31 : 0] v__h6528;
reg [31 : 0] v__h6817;
reg [31 : 0] v__h6927;
reg [31 : 0] v__h893;
reg [31 : 0] v__h6522;
reg [31 : 0] v__h6811;
reg [31 : 0] v__h6921;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] data64__h1055;
reg [31 : 0] CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2,
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3;
reg CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4,
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5;
wire [63 : 0] rdata__h1011,
slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1;
wire [1 : 0] rdr_rresp__h1044;
wire NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33,
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248;
// action method set_addr_map
assign RDY_set_addr_map = 1'd1 ;
assign CAN_FIRE_set_addr_map = 1'd1 ;
assign WILL_FIRE_set_addr_map = EN_set_addr_map ;
// action method slave_m_awvalid
assign CAN_FIRE_slave_m_awvalid = 1'd1 ;
assign WILL_FIRE_slave_m_awvalid = 1'd1 ;
// value method slave_m_awready
assign slave_awready = slave_xactor_f_wr_addr$FULL_N ;
// action method slave_m_wvalid
assign CAN_FIRE_slave_m_wvalid = 1'd1 ;
assign WILL_FIRE_slave_m_wvalid = 1'd1 ;
// value method slave_m_wready
assign slave_wready = slave_xactor_f_wr_data$FULL_N ;
// value method slave_m_bvalid
assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ;
// value method slave_m_bid
assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ;
// value method slave_m_bresp
assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ;
// action method slave_m_bready
assign CAN_FIRE_slave_m_bready = 1'd1 ;
assign WILL_FIRE_slave_m_bready = 1'd1 ;
// action method slave_m_arvalid
assign CAN_FIRE_slave_m_arvalid = 1'd1 ;
assign WILL_FIRE_slave_m_arvalid = 1'd1 ;
// value method slave_m_arready
assign slave_arready = slave_xactor_f_rd_addr$FULL_N ;
// value method slave_m_rvalid
assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ;
// value method slave_m_rid
assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ;
// value method slave_m_rdata
assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ;
// value method slave_m_rresp
assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ;
// value method slave_m_rlast
assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ;
// action method slave_m_rready
assign CAN_FIRE_slave_m_rready = 1'd1 ;
assign WILL_FIRE_slave_m_rready = 1'd1 ;
// submodule slave_xactor_f_rd_addr
FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_addr$D_IN),
.ENQ(slave_xactor_f_rd_addr$ENQ),
.DEQ(slave_xactor_f_rd_addr$DEQ),
.CLR(slave_xactor_f_rd_addr$CLR),
.D_OUT(slave_xactor_f_rd_addr$D_OUT),
.FULL_N(slave_xactor_f_rd_addr$FULL_N),
.EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N));
// submodule slave_xactor_f_rd_data
FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_data$D_IN),
.ENQ(slave_xactor_f_rd_data$ENQ),
.DEQ(slave_xactor_f_rd_data$DEQ),
.CLR(slave_xactor_f_rd_data$CLR),
.D_OUT(slave_xactor_f_rd_data$D_OUT),
.FULL_N(slave_xactor_f_rd_data$FULL_N),
.EMPTY_N(slave_xactor_f_rd_data$EMPTY_N));
// submodule slave_xactor_f_wr_addr
FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_addr$D_IN),
.ENQ(slave_xactor_f_wr_addr$ENQ),
.DEQ(slave_xactor_f_wr_addr$DEQ),
.CLR(slave_xactor_f_wr_addr$CLR),
.D_OUT(slave_xactor_f_wr_addr$D_OUT),
.FULL_N(slave_xactor_f_wr_addr$FULL_N),
.EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N));
// submodule slave_xactor_f_wr_data
FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_data$D_IN),
.ENQ(slave_xactor_f_wr_data$ENQ),
.DEQ(slave_xactor_f_wr_data$DEQ),
.CLR(slave_xactor_f_wr_data$CLR),
.D_OUT(),
.FULL_N(slave_xactor_f_wr_data$FULL_N),
.EMPTY_N(slave_xactor_f_wr_data$EMPTY_N));
// submodule slave_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_resp$D_IN),
.ENQ(slave_xactor_f_wr_resp$ENQ),
.DEQ(slave_xactor_f_wr_resp$DEQ),
.CLR(slave_xactor_f_wr_resp$CLR),
.D_OUT(slave_xactor_f_wr_resp$D_OUT),
.FULL_N(slave_xactor_f_wr_resp$FULL_N),
.EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N));
// rule RL_rl_process_rd_req
assign CAN_FIRE_RL_rl_process_rd_req =
slave_xactor_f_rd_addr$EMPTY_N &&
slave_xactor_f_rd_data$FULL_N &&
rg_module_ready ;
assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ;
// rule RL_rl_process_wr_req
assign CAN_FIRE_RL_rl_process_wr_req =
slave_xactor_f_wr_addr$EMPTY_N &&
slave_xactor_f_wr_data$EMPTY_N &&
slave_xactor_f_wr_resp$FULL_N &&
rg_module_ready ;
assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ;
// register rg_addr_base
assign rg_addr_base$D_IN = set_addr_map_addr_base ;
assign rg_addr_base$EN = EN_set_addr_map ;
// register rg_addr_lim
assign rg_addr_lim$D_IN = set_addr_map_addr_lim ;
assign rg_addr_lim$EN = EN_set_addr_map ;
// register rg_module_ready
assign rg_module_ready$D_IN = 1'd1 ;
assign rg_module_ready$EN = EN_set_addr_map ;
// submodule slave_xactor_f_rd_addr
assign slave_xactor_f_rd_addr$D_IN =
{ slave_arid,
slave_araddr,
slave_arlen,
slave_arsize,
slave_arburst,
slave_arlock,
slave_arcache,
slave_arprot,
slave_arqos,
slave_arregion } ;
assign slave_xactor_f_rd_addr$ENQ =
slave_arvalid && slave_xactor_f_rd_addr$FULL_N ;
assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ;
assign slave_xactor_f_rd_addr$CLR = 1'b0 ;
// submodule slave_xactor_f_rd_data
assign slave_xactor_f_rd_data$D_IN =
{ slave_xactor_f_rd_addr$D_OUT[96:93],
rdata__h1011,
rdr_rresp__h1044,
1'd1 } ;
assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ;
assign slave_xactor_f_rd_data$DEQ =
slave_rready && slave_xactor_f_rd_data$EMPTY_N ;
assign slave_xactor_f_rd_data$CLR = 1'b0 ;
// submodule slave_xactor_f_wr_addr
assign slave_xactor_f_wr_addr$D_IN =
{ slave_awid,
slave_awaddr,
slave_awlen,
slave_awsize,
slave_awburst,
slave_awlock,
slave_awcache,
slave_awprot,
slave_awqos,
slave_awregion } ;
assign slave_xactor_f_wr_addr$ENQ =
slave_awvalid && slave_xactor_f_wr_addr$FULL_N ;
assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_addr$CLR = 1'b0 ;
// submodule slave_xactor_f_wr_data
assign slave_xactor_f_wr_data$D_IN =
{ slave_wdata, slave_wstrb, slave_wlast } ;
assign slave_xactor_f_wr_data$ENQ =
slave_wvalid && slave_xactor_f_wr_data$FULL_N ;
assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_data$CLR = 1'b0 ;
// submodule slave_xactor_f_wr_resp
assign slave_xactor_f_wr_resp$D_IN =
{ slave_xactor_f_wr_addr$D_OUT[96:93],
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248 ?
2'b10 :
2'b0 } ;
assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_resp$DEQ =
slave_bready && slave_xactor_f_wr_resp$EMPTY_N ;
assign slave_xactor_f_wr_resp$CLR = 1'b0 ;
// remaining internal signals
assign NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33 =
slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 &&
CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 ||
rg_addr_base > slave_xactor_f_rd_addr$D_OUT[92:29] ||
slave_xactor_f_rd_addr$D_OUT[92:29] >= rg_addr_lim ;
assign NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248 =
slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 &&
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 ||
rg_addr_base > slave_xactor_f_wr_addr$D_OUT[92:29] ||
slave_xactor_f_wr_addr$D_OUT[92:29] >= rg_addr_lim ;
assign rdata__h1011 =
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33 ?
64'd0 :
data64__h1055 ;
assign rdr_rresp__h1044 =
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33 ?
2'b10 :
2'b0 ;
assign slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1 =
slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ;
always@(slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1)
begin
case (slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1[63:3])
61'd2,
61'd3,
61'd7,
61'd9,
61'd10,
61'd11,
61'd25,
61'd29,
61'd39,
61'd53,
61'd56,
61'd75,
61'd91,
61'd142,
61'd143,
61'd144,
61'd145,
61'd146,
61'd147,
61'd148,
61'd149,
61'd150,
61'd151,
61'd152,
61'd153,
61'd154,
61'd155,
61'd156,
61'd157,
61'd158,
61'd159,
61'd160,
61'd161,
61'd162,
61'd163,
61'd164,
61'd165,
61'd166,
61'd167,
61'd168,
61'd169,
61'd170,
61'd171,
61'd172,
61'd173,
61'd174,
61'd175,
61'd176,
61'd177,
61'd178,
61'd179,
61'd180,
61'd181,
61'd182,
61'd183,
61'd184,
61'd185,
61'd186,
61'd187,
61'd188,
61'd189,
61'd190,
61'd191,
61'd192,
61'd193,
61'd194,
61'd195,
61'd196,
61'd197,
61'd198,
61'd199,
61'd200,
61'd201,
61'd202,
61'd203,
61'd204,
61'd205,
61'd206,
61'd207,
61'd208,
61'd209,
61'd210,
61'd211,
61'd212,
61'd213,
61'd214,
61'd215,
61'd216,
61'd217,
61'd218,
61'd219,
61'd220,
61'd221,
61'd222,
61'd223,
61'd224,
61'd225,
61'd226,
61'd227,
61'd228,
61'd229,
61'd230,
61'd231,
61'd232,
61'd233,
61'd234,
61'd235,
61'd236,
61'd237,
61'd238,
61'd239,
61'd240,
61'd241,
61'd242,
61'd243,
61'd244,
61'd245,
61'd246,
61'd247,
61'd248,
61'd249,
61'd250,
61'd251,
61'd252,
61'd253,
61'd254,
61'd255,
61'd256,
61'd257,
61'd258,
61'd259,
61'd260,
61'd261,
61'd262,
61'd263,
61'd264,
61'd265,
61'd266,
61'd267,
61'd268,
61'd269,
61'd270,
61'd271,
61'd272,
61'd273,
61'd274,
61'd275,
61'd276,
61'd277,
61'd278,
61'd279,
61'd280,
61'd281,
61'd282,
61'd283,
61'd284,
61'd285,
61'd286,
61'd287,
61'd288,
61'd289,
61'd290,
61'd291,
61'd292,
61'd293,
61'd294,
61'd295,
61'd296,
61'd297,
61'd298,
61'd299,
61'd300,
61'd301,
61'd302,
61'd303,
61'd304,
61'd305,
61'd306,
61'd307,
61'd308,
61'd309,
61'd310,
61'd311,
61'd312,
61'd313,
61'd314,
61'd315,
61'd316,
61'd317,
61'd318,
61'd319,
61'd320,
61'd321,
61'd322,
61'd323,
61'd324,
61'd325,
61'd326,
61'd327,
61'd328,
61'd329,
61'd330,
61'd331,
61'd332,
61'd333,
61'd334,
61'd335,
61'd336,
61'd337,
61'd338,
61'd339,
61'd340,
61'd341,
61'd342,
61'd343,
61'd344,
61'd345,
61'd346,
61'd347,
61'd348,
61'd349,
61'd350,
61'd351,
61'd352,
61'd353,
61'd354,
61'd355,
61'd356,
61'd357,
61'd358,
61'd359,
61'd360,
61'd361,
61'd362,
61'd363,
61'd364,
61'd365,
61'd366,
61'd367,
61'd368,
61'd369,
61'd370,
61'd371,
61'd372,
61'd373,
61'd374,
61'd375,
61'd376,
61'd377,
61'd378,
61'd379,
61'd380,
61'd381,
61'd382,
61'd383,
61'd384,
61'd385,
61'd386,
61'd387,
61'd388,
61'd389,
61'd390,
61'd391,
61'd392,
61'd393,
61'd394,
61'd395,
61'd396,
61'd397,
61'd398,
61'd399,
61'd400,
61'd401,
61'd402,
61'd403,
61'd404,
61'd405,
61'd406,
61'd407,
61'd408,
61'd409,
61'd410,
61'd411,
61'd412,
61'd413,
61'd414,
61'd415,
61'd416,
61'd417,
61'd418,
61'd419,
61'd420,
61'd421,
61'd422,
61'd423,
61'd424,
61'd425,
61'd426,
61'd427,
61'd428,
61'd429,
61'd430,
61'd431,
61'd432,
61'd433,
61'd434,
61'd435,
61'd436,
61'd437,
61'd438,
61'd439,
61'd440,
61'd441,
61'd442,
61'd443,
61'd444,
61'd445,
61'd446,
61'd447,
61'd448,
61'd449,
61'd450,
61'd451,
61'd452,
61'd453,
61'd454,
61'd455,
61'd456,
61'd457,
61'd458,
61'd459,
61'd460,
61'd461,
61'd462,
61'd463,
61'd464,
61'd465,
61'd466,
61'd467,
61'd468,
61'd469,
61'd470,
61'd471,
61'd472,
61'd473,
61'd474,
61'd475,
61'd476,
61'd477,
61'd478,
61'd479,
61'd480,
61'd481,
61'd482,
61'd483,
61'd484,
61'd485,
61'd486,
61'd487,
61'd488,
61'd489,
61'd490,
61'd491,
61'd492,
61'd493,
61'd494,
61'd495,
61'd496,
61'd497,
61'd498,
61'd499,
61'd500,
61'd501,
61'd502,
61'd503,
61'd504,
61'd505,
61'd506,
61'd507,
61'd508,
61'd509,
61'd510,
61'd511:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 = 32'h0;
61'd4:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h54040000;
61'd5:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h88030000;
61'd6:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h11000000;
61'd8:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h50030000;
61'd12,
61'd14,
61'd26,
61'd28,
61'd30,
61'd54,
61'd61,
61'd109,
61'd111:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h04000000;
61'd13, 61'd15, 61'd63, 61'd99, 61'd115:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h02000000;
61'd16:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h16000000;
61'd17:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h62626375;
61'd18:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h656B6970;
61'd19:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h65642D65;
61'd20,
61'd33,
61'd35,
61'd37,
61'd42,
61'd45,
61'd48,
61'd57,
61'd69,
61'd74,
61'd76,
61'd78,
61'd84,
61'd88,
61'd95,
61'd102,
61'd105,
61'd110:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h03000000;
61'd21:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h26000000;
61'd22, 61'd80:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h732C7261;
61'd23, 61'd81:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h7261622D;
61'd24,
61'd27,
61'd50,
61'd55,
61'd62,
61'd64,
61'd73,
61'd93,
61'd94,
61'd114:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h01000000;
61'd31, 61'd112:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h80969800;
61'd32:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h40757063;
61'd34:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h3F000000;
61'd36, 61'd70, 61'd96, 61'd106:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h4B000000;
61'd38:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h4F000000;
61'd40:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h06000000;
61'd41:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h63736972;
61'd43:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h56000000;
61'd44:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h75616D69;
61'd46:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h60000000;
61'd47:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h76732C76;
61'd49:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h69000000;
61'd51:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h70757272;
61'd52:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6F72746E;
61'd58, 61'd79, 61'd89, 61'd103:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h1B000000;
61'd59:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h70632C76;
61'd60:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00006374;
61'd65:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h38407972;
61'd66:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00303030;
61'd67:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h07000000;
61'd68:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6F6D656D;
61'd71:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000080;
61'd72:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000010;
61'd77:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h0F000000;
61'd82:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h69730063;
61'd83:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h7375622D;
61'd85:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'hA7000000;
61'd86:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6E696C63;
61'd87, 61'd101:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h30303030;
61'd90:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6C632C76;
61'd92:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h10000000;
61'd97:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000002;
61'd98:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000C00;
61'd100:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h74726175;
61'd104:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h61303535;
61'd107:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h000000C0;
61'd108:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h40000000;
61'd113:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h08000000;
61'd116:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h09000000;
61'd117:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h73736572;
61'd118:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h2300736C;
61'd119:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6C65632D;
61'd120:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h61706D6F;
61'd121:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6F6D0065;
61'd122:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h656D6974;
61'd123:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6572662D;
61'd124:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h64007963;
61'd125:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h79745F65;
61'd126:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h73006765;
61'd127:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h69720073;
61'd128:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00617369;
61'd129:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h65707974;
61'd130:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h662D6B63;
61'd131:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h79636E65;
61'd132, 61'd134:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h72726574;
61'd133:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6C6C6563;
61'd135:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h746E6F63;
61'd136:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h70007265;
61'd137:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h7200656C;
61'd138:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6E690073;
61'd139:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h73747075;
61'd140:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h65646E65;
61'd141:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h68732D67;
default: CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'hAAAAAAAA;
endcase
end
always@(slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1)
begin
case (slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1[63:3])
61'd2:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00028067;
61'd3:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h80000000;
61'd4:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hEDFE0DD0;
61'd5:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h38000000;
61'd6:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h28000000;
61'd7, 61'd70, 61'd96, 61'd106:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h10000000;
61'd8:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hCC000000;
61'd9,
61'd10,
61'd13,
61'd27,
61'd37,
61'd71,
61'd72,
61'd84,
61'd85,
61'd97,
61'd98,
61'd105,
61'd107,
61'd108,
61'd143,
61'd144,
61'd145,
61'd146,
61'd147,
61'd148,
61'd149,
61'd150,
61'd151,
61'd152,
61'd153,
61'd154,
61'd155,
61'd156,
61'd157,
61'd158,
61'd159,
61'd160,
61'd161,
61'd162,
61'd163,
61'd164,
61'd165,
61'd166,
61'd167,
61'd168,
61'd169,
61'd170,
61'd171,
61'd172,
61'd173,
61'd174,
61'd175,
61'd176,
61'd177,
61'd178,
61'd179,
61'd180,
61'd181,
61'd182,
61'd183,
61'd184,
61'd185,
61'd186,
61'd187,
61'd188,
61'd189,
61'd190,
61'd191,
61'd192,
61'd193,
61'd194,
61'd195,
61'd196,
61'd197,
61'd198,
61'd199,
61'd200,
61'd201,
61'd202,
61'd203,
61'd204,
61'd205,
61'd206,
61'd207,
61'd208,
61'd209,
61'd210,
61'd211,
61'd212,
61'd213,
61'd214,
61'd215,
61'd216,
61'd217,
61'd218,
61'd219,
61'd220,
61'd221,
61'd222,
61'd223,
61'd224,
61'd225,
61'd226,
61'd227,
61'd228,
61'd229,
61'd230,
61'd231,
61'd232,
61'd233,
61'd234,
61'd235,
61'd236,
61'd237,
61'd238,
61'd239,
61'd240,
61'd241,
61'd242,
61'd243,
61'd244,
61'd245,
61'd246,
61'd247,
61'd248,
61'd249,
61'd250,
61'd251,
61'd252,
61'd253,
61'd254,
61'd255,
61'd256,
61'd257,
61'd258,
61'd259,
61'd260,
61'd261,
61'd262,
61'd263,
61'd264,
61'd265,
61'd266,
61'd267,
61'd268,
61'd269,
61'd270,
61'd271,
61'd272,
61'd273,
61'd274,
61'd275,
61'd276,
61'd277,
61'd278,
61'd279,
61'd280,
61'd281,
61'd282,
61'd283,
61'd284,
61'd285,
61'd286,
61'd287,
61'd288,
61'd289,
61'd290,
61'd291,
61'd292,
61'd293,
61'd294,
61'd295,
61'd296,
61'd297,
61'd298,
61'd299,
61'd300,
61'd301,
61'd302,
61'd303,
61'd304,
61'd305,
61'd306,
61'd307,
61'd308,
61'd309,
61'd310,
61'd311,
61'd312,
61'd313,
61'd314,
61'd315,
61'd316,
61'd317,
61'd318,
61'd319,
61'd320,
61'd321,
61'd322,
61'd323,
61'd324,
61'd325,
61'd326,
61'd327,
61'd328,
61'd329,
61'd330,
61'd331,
61'd332,
61'd333,
61'd334,
61'd335,
61'd336,
61'd337,
61'd338,
61'd339,
61'd340,
61'd341,
61'd342,
61'd343,
61'd344,
61'd345,
61'd346,
61'd347,
61'd348,
61'd349,
61'd350,
61'd351,
61'd352,
61'd353,
61'd354,
61'd355,
61'd356,
61'd357,
61'd358,
61'd359,
61'd360,
61'd361,
61'd362,
61'd363,
61'd364,
61'd365,
61'd366,
61'd367,
61'd368,
61'd369,
61'd370,
61'd371,
61'd372,
61'd373,
61'd374,
61'd375,
61'd376,
61'd377,
61'd378,
61'd379,
61'd380,
61'd381,
61'd382,
61'd383,
61'd384,
61'd385,
61'd386,
61'd387,
61'd388,
61'd389,
61'd390,
61'd391,
61'd392,
61'd393,
61'd394,
61'd395,
61'd396,
61'd397,
61'd398,
61'd399,
61'd400,
61'd401,
61'd402,
61'd403,
61'd404,
61'd405,
61'd406,
61'd407,
61'd408,
61'd409,
61'd410,
61'd411,
61'd412,
61'd413,
61'd414,
61'd415,
61'd416,
61'd417,
61'd418,
61'd419,
61'd420,
61'd421,
61'd422,
61'd423,
61'd424,
61'd425,
61'd426,
61'd427,
61'd428,
61'd429,
61'd430,
61'd431,
61'd432,
61'd433,
61'd434,
61'd435,
61'd436,
61'd437,
61'd438,
61'd439,
61'd440,
61'd441,
61'd442,
61'd443,
61'd444,
61'd445,
61'd446,
61'd447,
61'd448,
61'd449,
61'd450,
61'd451,
61'd452,
61'd453,
61'd454,
61'd455,
61'd456,
61'd457,
61'd458,
61'd459,
61'd460,
61'd461,
61'd462,
61'd463,
61'd464,
61'd465,
61'd466,
61'd467,
61'd468,
61'd469,
61'd470,
61'd471,
61'd472,
61'd473,
61'd474,
61'd475,
61'd476,
61'd477,
61'd478,
61'd479,
61'd480,
61'd481,
61'd482,
61'd483,
61'd484,
61'd485,
61'd486,
61'd487,
61'd488,
61'd489,
61'd490,
61'd491,
61'd492,
61'd493,
61'd494,
61'd495,
61'd496,
61'd497,
61'd498,
61'd499,
61'd500,
61'd501,
61'd502,
61'd503,
61'd504,
61'd505,
61'd506,
61'd507,
61'd508,
61'd509,
61'd510,
61'd511:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 = 32'h0;
61'd11, 61'd32, 61'd86, 61'd100:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h01000000;
61'd12,
61'd14,
61'd16,
61'd26,
61'd28,
61'd30,
61'd40,
61'd54,
61'd56,
61'd61,
61'd67,
61'd92,
61'd94,
61'd109,
61'd111,
61'd113:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h03000000;
61'd15, 61'd29, 61'd58:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0F000000;
61'd17, 61'd41:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h1B000000;
61'd18:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h732C7261;
61'd19:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h7261622D;
61'd20, 61'd42:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000076;
61'd21:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h12000000;
61'd22, 61'd80:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h62626375;
61'd23, 61'd81:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h656B6970;
61'd24:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000065;
61'd25:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h73757063;
61'd31:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2C000000;
61'd33, 61'd88, 61'd102:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000030;
61'd34, 61'd36, 61'd49, 61'd75, 61'd77:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h04000000;
61'd35:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00757063;
61'd38:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h05000000;
61'd39:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h79616B6F;
61'd43:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0A000000;
61'd44:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h34367672;
61'd45:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000073;
61'd46, 61'd115:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0B000000;
61'd47, 61'd59, 61'd90:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h63736972;
61'd48:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00003933;
61'd50:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h80969800;
61'd51:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65746E69;
61'd52:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F632D74;
61'd53:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h72656C6C;
61'd55:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h79000000;
61'd57:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h8A000000;
61'd60:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E692D75;
61'd62:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h9F000000;
61'd63, 61'd64, 61'd73, 61'd76, 61'd78, 61'd99, 61'd116:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h02000000;
61'd65:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F6D656D;
61'd66:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30303030;
61'd68:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h3F000000;
61'd69:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00007972;
61'd74:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00636F73;
61'd79:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h21000000;
61'd82:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F732D65;
61'd83:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h656C706D;
61'd87:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30324074;
61'd89:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0D000000;
61'd91:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30746E69;
61'd93, 61'd114:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hAE000000;
61'd95:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h07000000;
61'd101:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30306340;
61'd103:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h09000000;
61'd104:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h3631736E;
61'd110:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hC2000000;
61'd112:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h69000000;
61'd117:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h64646123;
61'd118:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6C65632D;
61'd119:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h657A6973;
61'd120:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6300736C;
61'd121:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6C626974;
61'd122:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h006C6564;
61'd123:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65736162;
61'd124:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E657571;
61'd125:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h63697665;
61'd126:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h72006570;
61'd127:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h75746174;
61'd128:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2C766373;
61'd129:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2D756D6D;
61'd130:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F6C6300;
61'd131:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h75716572;
61'd132:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E692300;
61'd133, 61'd135:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2D747075;
61'd134:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E690073;
61'd136:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6C6C6F72;
61'd137:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h646E6168;
61'd138:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65676E61;
61'd139:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h72726574;
61'd140:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h7478652D;
61'd141:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65720064;
61'd142:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00746669;
default: CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hAAAAAAAA;
endcase
end
always@(slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1 or
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 or
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3)
begin
case (slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1[63:3])
61'd0: data64__h1055 = 64'h0202859300000297;
61'd1: data64__h1055 = 64'h0182B283F1402573;
default: data64__h1055 =
{ CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2,
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 };
endcase
end
always@(slave_xactor_f_rd_addr$D_OUT)
begin
case (slave_xactor_f_rd_addr$D_OUT[20:18])
3'b001:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 =
slave_xactor_f_rd_addr$D_OUT[29];
3'b010:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 =
slave_xactor_f_rd_addr$D_OUT[30:29] != 2'b0;
default: CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 =
slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011 ||
slave_xactor_f_rd_addr$D_OUT[31:29] != 3'b0;
endcase
end
always@(slave_xactor_f_wr_addr$D_OUT)
begin
case (slave_xactor_f_wr_addr$D_OUT[20:18])
3'b001:
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 =
slave_xactor_f_wr_addr$D_OUT[29];
3'b010:
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 =
slave_xactor_f_wr_addr$D_OUT[30:29] != 2'b0;
default: CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 =
slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011 ||
slave_xactor_f_wr_addr$D_OUT[31:29] != 3'b0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_module_ready <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (rg_module_ready$EN)
rg_module_ready <= `BSV_ASSIGNMENT_DELAY rg_module_ready$D_IN;
end
if (rg_addr_base$EN)
rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN;
if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_addr_base = 64'hAAAAAAAAAAAAAAAA;
rg_addr_lim = 64'hAAAAAAAAAAAAAAAA;
rg_module_ready = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
begin
v__h899 = $stime;
#0;
end
v__h893 = v__h899 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$display("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized or misaligned addr",
v__h893);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
begin
v__h6528 = $stime;
#0;
end
v__h6522 = v__h6528 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized or misaligned addr",
v__h6522);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0)
begin
v__h6817 = $stime;
#0;
end
v__h6811 = v__h6817 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0)
$display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned",
v__h6811,
set_addr_map_addr_base);
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0)
begin
v__h6927 = $stime;
#0;
end
v__h6921 = v__h6927 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0)
$display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned",
v__h6921,
set_addr_map_addr_lim);
end
// synopsys translate_on
endmodule // mkBoot_ROM
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "distributed" *) module CvtColor_1_sectorocq_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 2;
parameter AWIDTH = 3;
parameter MEM_SIZE = 6;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./CvtColor_1_sectorocq_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module CvtColor_1_sectorocq(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd6;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
CvtColor_1_sectorocq_rom CvtColor_1_sectorocq_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:48:31 MST 2014
// Date : Mon Feb 16 11:07:32 2015
// Host : austin_workstation_1 running 64-bit Fedora release 20 (Heisenbug)
// Command : write_verilog -force -mode synth_stub
// /home/luis/FIRMWARE/git/vhdl/ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_0_stub.v
// Design : axi_traffic_gen_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1157-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_traffic_gen_v2_0_top,Vivado 2014.4" *)
module axi_traffic_gen_0(s_axi_aclk, s_axi_aresetn, m_axi_lite_ch1_awaddr, m_axi_lite_ch1_awprot, m_axi_lite_ch1_awvalid, m_axi_lite_ch1_awready, m_axi_lite_ch1_wdata, m_axi_lite_ch1_wstrb, m_axi_lite_ch1_wvalid, m_axi_lite_ch1_wready, m_axi_lite_ch1_bresp, m_axi_lite_ch1_bvalid, m_axi_lite_ch1_bready, done, status)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,m_axi_lite_ch1_awaddr[31:0],m_axi_lite_ch1_awprot[2:0],m_axi_lite_ch1_awvalid,m_axi_lite_ch1_awready,m_axi_lite_ch1_wdata[31:0],m_axi_lite_ch1_wstrb[3:0],m_axi_lite_ch1_wvalid,m_axi_lite_ch1_wready,m_axi_lite_ch1_bresp[1:0],m_axi_lite_ch1_bvalid,m_axi_lite_ch1_bready,done,status[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
output [31:0]m_axi_lite_ch1_awaddr;
output [2:0]m_axi_lite_ch1_awprot;
output m_axi_lite_ch1_awvalid;
input m_axi_lite_ch1_awready;
output [31:0]m_axi_lite_ch1_wdata;
output [3:0]m_axi_lite_ch1_wstrb;
output m_axi_lite_ch1_wvalid;
input m_axi_lite_ch1_wready;
input [1:0]m_axi_lite_ch1_bresp;
input m_axi_lite_ch1_bvalid;
output m_axi_lite_ch1_bready;
output done;
output [31:0]status;
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Reset_Delay.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Reset_Delay
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Reset_Delay
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Reset_Delay
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
In,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [31:0] In; // sfix32_En26
output signed [31:0] Out; // sfix32_En26
wire signed [31:0] Constant1_out1; // sfix32_En26
wire signed [31:0] Reset_Switch1_out1; // sfix32_En26
reg signed [31:0] In_Delay_out1; // sfix32_En26
wire signed [31:0] Constant_out1; // sfix32_En26
wire signed [31:0] Reset_Switch_out1; // sfix32_En26
// <S13>/Constant1
assign Constant1_out1 = 32'sb00000000000000000000000000000000;
// <S13>/Reset_Switch1
assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In :
Constant1_out1);
// <S13>/In_Delay
always @(posedge CLK_IN)
begin : In_Delay_process
if (reset == 1'b1) begin
In_Delay_out1 <= 32'sb00000000000000000000000000000000;
end
else if (enb_1_2000_0) begin
In_Delay_out1 <= Reset_Switch1_out1;
end
end
// <S13>/Constant
assign Constant_out1 = 32'sb00000000000000000000000000000000;
// <S13>/Reset_Switch
assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 :
Constant_out1);
assign Out = Reset_Switch_out1;
endmodule // velocityControlHdl_Reset_Delay
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BO_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A21BO_PP_SYMBOL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21bo (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BO_PP_SYMBOL_V
|
// Copyright (c) 2011, Richard Castle
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the organization nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
module fibonacci_lfsr(
input clk,
input rst_n,
output [4:0] data
);
wire feedback = data[4] ^ data[1] ;
always @(posedge clk or negedge rst_n)
if (~rst_n)
data <= 4'hf;
else
data <= {data[2:0], feedback} ;
endmodule
|
`timescale 1ns/1ps
module tb_cocotb #(
parameter DATA_WIDTH = 32, //This is the output bus
parameter ADDR_WIDTH = 32,
parameter INTERRUPT_WIDTH = 32
)(
//Virtual Host Interface Signals
input clk,
input rst,
input [31:0] test_id,
input CMD_EN,
output CMD_ERROR,
output CMD_ACK,
output [31:0] CMD_STATUS,
output CMD_INTERRUPT,
input [ADDR_WIDTH - 1:0] CMD_ADR,
input CMD_WR_RD, //1 = WRITE, 0 = READ
input [3:0] CMD_BYTE_EN,
input [31:0] CMD_WR_DATA,
output [31:0] CMD_RD_DATA,
//***************** AXI Bus ************************************************
//bus write addr path
output [3:0] AXIS_AWID, //Write ID
output [ADDR_WIDTH - 1:0] AXIS_AWADDR, //Write Addr Path Address
output [7:0] AXIS_AWLEN, //Write Addr Path Burst Length
output [2:0] AXIS_AWSIZE, //Write Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output [1:0] AXIS_AWBURST, //Write Addr Path Burst Type
// 0 = Fixed
// 1 = Incrementing
// 2 = wrap
output [1:0] AXIS_AWLOCK, //Write Addr Path Lock (atomic) information
// 0 = Normal
// 1 = Exclusive
// 2 = Locked
output [3:0] AXIS_AWCACHE, //Write Addr Path Cache Type
output [2:0] AXIS_AWPROT, //Write Addr Path Protection Type
output AXIS_AWVALID, //Write Addr Path Address Valid
input AXIS_AWREADY, //Write Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus write data
output [3:0] AXIS_WID, //Write ID
output [DATA_WIDTH - 1: 0] AXIS_WDATA, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
output [(DATA_WIDTH >> 3) - 1:0] AXIS_WSTRB, //Write Strobe (a 1 in the write is associated with the byte to write)
output AXIS_WLAST, //Write Last transfer in a write burst
output AXIS_WVALID, //Data through this bus is valid
input AXIS_WREADY, //Slave is ready for data
//Write Response Channel
input [3:0] AXIS_BID, //Response ID (this must match awid)
input [1:0] AXIS_BRESP, //Write Response
// 0 = OKAY
// 1 = EXOKAY
// 2 = SLVERR
// 3 = DECERR
input AXIS_BVALID, //Write Response is:
// 1 = Available
// 0 = Not Available
output AXIS_BREADY, //WBM Ready
//bus read addr path
output [3:0] AXIS_ARID, //Read ID
output [ADDR_WIDTH - 1:0] AXIS_ARADDR, //Read Addr Path Address
output [7:0] AXIS_ARLEN, //Read Addr Path Burst Length
output [2:0] AXIS_ARSIZE, //Read Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output [1:0] AXIS_ARBURST, //Read Addr Path Burst Type
output [1:0] AXIS_ARLOCK, //Read Addr Path Lock (atomic) information
output [3:0] AXIS_ARCACHE, //Read Addr Path Cache Type
output [2:0] AXIS_ARPROT, //Read Addr Path Protection Type
output AXIS_ARVALID, //Read Addr Path Address Valid
input AXIS_ARREADY, //Read Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus read data
input [3:0] AXIS_RID, //Write ID
input [DATA_WIDTH - 1: 0] AXIS_RDATA, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
input [1:0] AXIS_RRESP,
input [(DATA_WIDTH >> 3) - 1:0] AXIS_RSTRB, //Write Strobe (a 1 in the write is associated with the byte to write)
input AXIS_RLAST, //Write Last transfer in a write burst
input AXIS_RVALID, //Data through this bus is valid
output AXIS_RREADY, //WBM is ready for data
// 1 = WBM Ready
// 0 = Slave Ready
input [INTERRUPT_WIDTH - 1:0] i_interrupts
);
//Local Parameters
localparam INVERT_AXI_RESET = 0;
localparam DEFAULT_TIMEOUT = 32'd100000000; //1 Second at 100MHz
//Registers/Wires
reg r_rst;
wire [INTERRUPT_WIDTH - 1:0] w_interrupts;
assign AXIS_AWLEN = 0;
assign AXIS_AWBURST = 1;
assign AXIS_AWPROT = 0;
assign AXIS_ARBURST = 1;
assign AXIS_ARPROT = 0;
//Submodules
axi_lite_master #(
.INVERT_AXI_RESET (INVERT_AXI_RESET ),
.ADDR_WIDTH (ADDR_WIDTH ),
.INTERRUPT_WIDTH (INTERRUPT_WIDTH ),
.DEFAULT_TIMEOUT (DEFAULT_TIMEOUT )
) am (
.clk (clk ),
.rst (r_rst ),
//************* User Facing Side *******************************************
.i_cmd_en (CMD_EN ),
.o_cmd_error (CMD_ERROR ),
.o_cmd_ack (CMD_ACK ),
.o_cmd_status (CMD_STATUS ),
.i_cmd_addr (CMD_ADR ),
.i_cmd_wr_rd (CMD_WR_RD ),
.i_cmd_byte_en (CMD_BYTE_EN ),
.i_cmd_data (CMD_WR_DATA ),
.o_cmd_data (CMD_RD_DATA ),
.o_cmd_interrupt (CMD_INTERRUPT ),
//***************** AXI Bus ************************************************
//bus write addr path
.o_awid (AXIS_AWID ),
.o_awaddr (AXIS_AWADDR ),
.o_awsize (AXIS_AWSIZE ),
.o_awvalid (AXIS_AWVALID ),
.i_awready (AXIS_AWREADY ),
//bus write data
.o_wid (AXIS_WID ),
.o_wdata (AXIS_WDATA ),
.o_wstrobe (AXIS_WSTRB ),
.o_wlast (AXIS_WLAST ),
.o_wvalid (AXIS_WVALID ),
.i_wready (AXIS_WREADY ),
//Write Response Channel
.i_bid (AXIS_BID ),
.i_bresp (AXIS_BRESP ),
.i_bvalid (AXIS_BVALID ),
.o_bready (AXIS_BREADY ),
//bus read addr path
.o_arid (AXIS_ARID ),
.o_araddr (AXIS_ARADDR ),
.o_arlen (AXIS_ARLEN ),
.o_arsize (AXIS_ARSIZE ),
.o_arvalid (AXIS_ARVALID ),
.i_arready (AXIS_ARREADY ),
//bus read data
.i_rid (AXIS_RID ),
.i_rdata (AXIS_RDATA ),
.i_rresp (AXIS_RRESP ),
.i_rstrobe (AXIS_RSTRB ),
.i_rlast (AXIS_RLAST ),
.i_rvalid (AXIS_RVALID ),
.o_rready (AXIS_RREADY ),
//nterrupts
.i_interrupts (i_interrupts )
);
//There is a timing thing in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Mon Oct 31 02:56:32 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire n6077, NaN_reg, ready_add_subt, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_d_ff3_sign_out, FPSENCOS_d_ff1_operation_out,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_exp_operation_A_S, FPMULT_FSM_add_overflow_flag,
FPMULT_zero_flag, FPADDSUB_OP_FLAG_SFG, FPADDSUB_SIGN_FLAG_SFG,
FPADDSUB_SIGN_FLAG_NRM, FPADDSUB_SIGN_FLAG_SHT1SHT2,
FPADDSUB_ADD_OVRFLW_NRM2, FPADDSUB_OP_FLAG_SHT2,
FPADDSUB_SIGN_FLAG_SHT2, FPADDSUB_bit_shift_SHT2,
FPADDSUB_left_right_SHT2, FPADDSUB_ADD_OVRFLW_NRM,
FPADDSUB_OP_FLAG_SHT1, FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP,
FPADDSUB_SIGN_FLAG_EXP, FPADDSUB_intAS, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N23,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N22,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N21,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N20,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N19,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N18,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N17,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N16,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N15,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N14,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N13,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N12,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N11,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N10,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N9,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N8,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N7,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N6,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N5,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N4,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N3,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N2,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N1,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N0,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N25,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N24,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N23,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N22,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N21,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N20,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N19,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N18,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N17,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N16,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N15,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N14,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N13,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N12,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N11,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N10,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N9,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N8,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N7,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N6,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N5,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N4,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N3,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N2,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N1,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N0,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N23,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N22,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N21,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N20,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N19,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N18,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N17,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N16,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N15,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N14,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N13,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N12,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N11,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N10,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N9,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N8,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N7,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N6,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N5,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N4,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N3,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N2,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N1, n1180, n1181, n1182,
n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192,
n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202,
n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212,
n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1236, n1237, n1238, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1288, n1289, n1290, n1291, n1292, n1293, n1295, n1296, n1297,
n1298, n1299, n1300, n1302, n1303, n1304, n1305, n1306, n1307, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1481, n1483,
n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493,
n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503,
n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513,
n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523,
n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533,
n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543,
n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553,
n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563,
n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573,
n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583,
n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593,
n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603,
n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613,
n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1624,
n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634,
n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644,
n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654,
n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664,
n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674,
n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684,
n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694,
n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704,
n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714,
n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724,
n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734,
n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744,
n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754,
n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764,
n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774,
n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784,
n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794,
n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804,
n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814,
n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824,
n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834,
n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844,
n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854,
n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864,
n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874,
n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884,
n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894,
n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904,
n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914,
n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924,
n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934,
n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944,
n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954,
n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964,
n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974,
n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984,
n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994,
n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004,
n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034,
n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044,
n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054,
n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064,
n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074,
n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084,
n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094,
n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2191, DP_OP_26J16_124_9022_n18,
DP_OP_26J16_124_9022_n17, DP_OP_26J16_124_9022_n16,
DP_OP_26J16_124_9022_n15, DP_OP_26J16_124_9022_n14,
DP_OP_26J16_124_9022_n8, DP_OP_26J16_124_9022_n7,
DP_OP_26J16_124_9022_n6, DP_OP_26J16_124_9022_n5,
DP_OP_26J16_124_9022_n4, DP_OP_26J16_124_9022_n3,
DP_OP_26J16_124_9022_n2, DP_OP_26J16_124_9022_n1,
DP_OP_234J16_127_8543_n22, DP_OP_234J16_127_8543_n21,
DP_OP_234J16_127_8543_n20, DP_OP_234J16_127_8543_n19,
DP_OP_234J16_127_8543_n18, DP_OP_234J16_127_8543_n17,
DP_OP_234J16_127_8543_n16, DP_OP_234J16_127_8543_n15,
DP_OP_234J16_127_8543_n9, DP_OP_234J16_127_8543_n8,
DP_OP_234J16_127_8543_n7, DP_OP_234J16_127_8543_n6,
DP_OP_234J16_127_8543_n5, DP_OP_234J16_127_8543_n4,
DP_OP_234J16_127_8543_n3, DP_OP_234J16_127_8543_n2,
DP_OP_234J16_127_8543_n1, intadd_21_CI, intadd_21_SUM_2_,
intadd_21_SUM_1_, intadd_21_SUM_0_, intadd_21_n3, intadd_21_n2,
intadd_21_n1, intadd_22_CI, intadd_22_SUM_2_, intadd_22_SUM_1_,
intadd_22_SUM_0_, intadd_22_n3, intadd_22_n2, intadd_22_n1,
DP_OP_453J16_122_8745_n227, DP_OP_454J16_123_2743_n727,
DP_OP_454J16_123_2743_n474, DP_OP_454J16_123_2743_n473,
DP_OP_454J16_123_2743_n472, DP_OP_454J16_123_2743_n471,
DP_OP_454J16_123_2743_n470, DP_OP_454J16_123_2743_n469,
DP_OP_454J16_123_2743_n468, DP_OP_454J16_123_2743_n467,
DP_OP_454J16_123_2743_n461, DP_OP_454J16_123_2743_n460,
DP_OP_454J16_123_2743_n459, DP_OP_454J16_123_2743_n458,
DP_OP_454J16_123_2743_n457, DP_OP_454J16_123_2743_n456,
DP_OP_454J16_123_2743_n455, DP_OP_454J16_123_2743_n454,
DP_OP_454J16_123_2743_n453, DP_OP_454J16_123_2743_n452,
DP_OP_454J16_123_2743_n448, DP_OP_454J16_123_2743_n447,
DP_OP_454J16_123_2743_n445, DP_OP_454J16_123_2743_n444,
DP_OP_454J16_123_2743_n443, DP_OP_454J16_123_2743_n442,
DP_OP_454J16_123_2743_n441, DP_OP_454J16_123_2743_n440,
DP_OP_454J16_123_2743_n439, DP_OP_454J16_123_2743_n438,
DP_OP_454J16_123_2743_n437, DP_OP_454J16_123_2743_n436,
DP_OP_454J16_123_2743_n435, DP_OP_454J16_123_2743_n431,
DP_OP_454J16_123_2743_n430, DP_OP_454J16_123_2743_n429,
DP_OP_454J16_123_2743_n428, DP_OP_454J16_123_2743_n427,
DP_OP_454J16_123_2743_n426, DP_OP_454J16_123_2743_n425,
DP_OP_454J16_123_2743_n424, DP_OP_454J16_123_2743_n423,
DP_OP_454J16_123_2743_n418, DP_OP_454J16_123_2743_n417,
DP_OP_454J16_123_2743_n415, DP_OP_454J16_123_2743_n414,
DP_OP_454J16_123_2743_n413, DP_OP_454J16_123_2743_n412,
DP_OP_454J16_123_2743_n411, DP_OP_454J16_123_2743_n410,
DP_OP_454J16_123_2743_n409, DP_OP_454J16_123_2743_n408,
DP_OP_454J16_123_2743_n407, DP_OP_454J16_123_2743_n406,
DP_OP_454J16_123_2743_n401, DP_OP_454J16_123_2743_n400,
DP_OP_454J16_123_2743_n399, DP_OP_454J16_123_2743_n398,
DP_OP_454J16_123_2743_n397, DP_OP_454J16_123_2743_n396,
DP_OP_454J16_123_2743_n395, DP_OP_454J16_123_2743_n394,
DP_OP_454J16_123_2743_n388, DP_OP_454J16_123_2743_n387,
DP_OP_454J16_123_2743_n385, DP_OP_454J16_123_2743_n384,
DP_OP_454J16_123_2743_n369, DP_OP_454J16_123_2743_n366,
DP_OP_454J16_123_2743_n365, DP_OP_454J16_123_2743_n364,
DP_OP_454J16_123_2743_n363, DP_OP_454J16_123_2743_n362,
DP_OP_454J16_123_2743_n361, DP_OP_454J16_123_2743_n360,
DP_OP_454J16_123_2743_n359, DP_OP_454J16_123_2743_n358,
DP_OP_454J16_123_2743_n356, DP_OP_454J16_123_2743_n355,
DP_OP_454J16_123_2743_n354, DP_OP_454J16_123_2743_n352,
DP_OP_454J16_123_2743_n351, DP_OP_454J16_123_2743_n350,
DP_OP_454J16_123_2743_n349, DP_OP_454J16_123_2743_n348,
DP_OP_454J16_123_2743_n347, DP_OP_454J16_123_2743_n346,
DP_OP_454J16_123_2743_n345, DP_OP_454J16_123_2743_n344,
DP_OP_454J16_123_2743_n343, DP_OP_454J16_123_2743_n342,
DP_OP_454J16_123_2743_n341, DP_OP_454J16_123_2743_n340,
DP_OP_454J16_123_2743_n339, DP_OP_454J16_123_2743_n338,
DP_OP_454J16_123_2743_n337, DP_OP_454J16_123_2743_n336,
DP_OP_454J16_123_2743_n335, DP_OP_454J16_123_2743_n334,
DP_OP_454J16_123_2743_n333, DP_OP_454J16_123_2743_n332,
DP_OP_454J16_123_2743_n330, DP_OP_454J16_123_2743_n329,
DP_OP_454J16_123_2743_n328, DP_OP_454J16_123_2743_n327,
DP_OP_454J16_123_2743_n326, DP_OP_454J16_123_2743_n325,
DP_OP_454J16_123_2743_n324, DP_OP_454J16_123_2743_n323,
DP_OP_454J16_123_2743_n322, DP_OP_454J16_123_2743_n321,
DP_OP_454J16_123_2743_n320, DP_OP_454J16_123_2743_n319,
DP_OP_454J16_123_2743_n318, DP_OP_454J16_123_2743_n317,
DP_OP_454J16_123_2743_n315, DP_OP_454J16_123_2743_n313,
DP_OP_454J16_123_2743_n312, DP_OP_454J16_123_2743_n311,
DP_OP_454J16_123_2743_n310, DP_OP_454J16_123_2743_n309,
DP_OP_454J16_123_2743_n308, DP_OP_454J16_123_2743_n305,
DP_OP_454J16_123_2743_n304, DP_OP_454J16_123_2743_n303,
DP_OP_454J16_123_2743_n302, DP_OP_454J16_123_2743_n301,
DP_OP_454J16_123_2743_n300, DP_OP_454J16_123_2743_n299,
DP_OP_454J16_123_2743_n298, DP_OP_454J16_123_2743_n297,
DP_OP_454J16_123_2743_n296, DP_OP_454J16_123_2743_n295,
DP_OP_454J16_123_2743_n294, DP_OP_454J16_123_2743_n293,
DP_OP_454J16_123_2743_n292, DP_OP_454J16_123_2743_n291,
DP_OP_454J16_123_2743_n290, DP_OP_454J16_123_2743_n289,
DP_OP_454J16_123_2743_n288, DP_OP_454J16_123_2743_n287,
DP_OP_454J16_123_2743_n286, DP_OP_454J16_123_2743_n285,
DP_OP_454J16_123_2743_n284, DP_OP_454J16_123_2743_n283,
DP_OP_454J16_123_2743_n282, DP_OP_454J16_123_2743_n281,
DP_OP_454J16_123_2743_n280, DP_OP_454J16_123_2743_n279,
DP_OP_454J16_123_2743_n278, DP_OP_454J16_123_2743_n277,
DP_OP_454J16_123_2743_n274, DP_OP_454J16_123_2743_n273,
DP_OP_454J16_123_2743_n272, DP_OP_454J16_123_2743_n271,
DP_OP_454J16_123_2743_n270, DP_OP_454J16_123_2743_n269,
DP_OP_454J16_123_2743_n268, DP_OP_454J16_123_2743_n267,
DP_OP_454J16_123_2743_n266, DP_OP_454J16_123_2743_n265,
DP_OP_454J16_123_2743_n264, DP_OP_454J16_123_2743_n263,
DP_OP_454J16_123_2743_n262, DP_OP_454J16_123_2743_n261,
DP_OP_454J16_123_2743_n260, DP_OP_454J16_123_2743_n259,
DP_OP_454J16_123_2743_n258, DP_OP_454J16_123_2743_n257,
mult_x_219_n355, mult_x_219_n351, mult_x_219_n350, mult_x_219_n343,
mult_x_219_n342, mult_x_219_n340, mult_x_219_n339, mult_x_219_n338,
mult_x_219_n337, mult_x_219_n336, mult_x_219_n335, mult_x_219_n334,
mult_x_219_n331, mult_x_219_n330, mult_x_219_n329, mult_x_219_n327,
mult_x_219_n326, mult_x_219_n325, mult_x_219_n323, mult_x_219_n322,
mult_x_219_n321, mult_x_219_n320, mult_x_219_n319, mult_x_219_n318,
mult_x_219_n317, mult_x_219_n315, mult_x_219_n314, mult_x_219_n313,
mult_x_219_n312, mult_x_219_n311, mult_x_219_n310, mult_x_219_n309,
mult_x_219_n308, mult_x_219_n306, mult_x_219_n303, mult_x_219_n302,
mult_x_219_n301, mult_x_219_n300, mult_x_219_n299, mult_x_219_n298,
mult_x_219_n297, mult_x_219_n296, mult_x_219_n295, mult_x_219_n294,
mult_x_219_n293, mult_x_219_n292, mult_x_219_n291, mult_x_219_n285,
mult_x_219_n284, mult_x_219_n281, mult_x_219_n280, mult_x_219_n265,
mult_x_219_n262, mult_x_219_n261, mult_x_219_n260, mult_x_219_n259,
mult_x_219_n258, mult_x_219_n257, mult_x_219_n256, mult_x_219_n255,
mult_x_219_n254, mult_x_219_n253, mult_x_219_n252, mult_x_219_n251,
mult_x_219_n250, mult_x_219_n249, mult_x_219_n248, mult_x_219_n247,
mult_x_219_n246, mult_x_219_n245, mult_x_219_n244, mult_x_219_n243,
mult_x_219_n242, mult_x_219_n241, mult_x_219_n240, mult_x_219_n239,
mult_x_219_n238, mult_x_219_n237, mult_x_219_n236, mult_x_219_n235,
mult_x_219_n234, mult_x_219_n233, mult_x_219_n232, mult_x_219_n231,
mult_x_219_n230, mult_x_219_n229, mult_x_219_n228, mult_x_219_n227,
mult_x_219_n226, mult_x_219_n225, mult_x_219_n224, mult_x_219_n223,
mult_x_219_n222, mult_x_219_n221, mult_x_219_n219, mult_x_219_n218,
mult_x_219_n217, mult_x_219_n216, mult_x_219_n215, mult_x_219_n214,
mult_x_219_n213, mult_x_219_n212, mult_x_219_n209, mult_x_219_n208,
mult_x_219_n207, mult_x_219_n206, mult_x_219_n205, mult_x_219_n204,
mult_x_219_n203, mult_x_219_n202, mult_x_219_n201, mult_x_219_n200,
mult_x_219_n199, mult_x_219_n198, mult_x_219_n197, mult_x_219_n196,
mult_x_219_n195, mult_x_219_n194, mult_x_219_n191, mult_x_219_n190,
mult_x_219_n189, mult_x_219_n188, mult_x_219_n187, mult_x_219_n186,
mult_x_219_n185, mult_x_219_n184, mult_x_219_n183, mult_x_219_n182,
mult_x_219_n181, mult_x_219_n180, mult_x_219_n177, mult_x_219_n176,
mult_x_219_n175, mult_x_219_n174, mult_x_219_n173, mult_x_219_n172,
mult_x_219_n171, mult_x_219_n170, mult_x_219_n169, mult_x_219_n168,
mult_x_219_n165, mult_x_219_n164, mult_x_219_n163, mult_x_219_n162,
mult_x_219_n161, mult_x_219_n160, mult_x_254_n363, mult_x_254_n361,
mult_x_254_n359, mult_x_254_n357, mult_x_254_n351, mult_x_254_n350,
mult_x_254_n348, mult_x_254_n347, mult_x_254_n346, mult_x_254_n345,
mult_x_254_n344, mult_x_254_n343, mult_x_254_n342, mult_x_254_n339,
mult_x_254_n338, mult_x_254_n337, mult_x_254_n335, mult_x_254_n334,
mult_x_254_n331, mult_x_254_n330, mult_x_254_n329, mult_x_254_n328,
mult_x_254_n327, mult_x_254_n326, mult_x_254_n323, mult_x_254_n322,
mult_x_254_n321, mult_x_254_n320, mult_x_254_n317, mult_x_254_n316,
mult_x_254_n314, mult_x_254_n311, mult_x_254_n307, mult_x_254_n306,
mult_x_254_n305, mult_x_254_n304, mult_x_254_n301, mult_x_254_n300,
mult_x_254_n299, mult_x_254_n298, mult_x_254_n297, mult_x_254_n296,
mult_x_254_n295, mult_x_254_n294, mult_x_254_n293, mult_x_254_n292,
mult_x_254_n291, mult_x_254_n290, mult_x_254_n289, mult_x_254_n288,
mult_x_254_n282, mult_x_254_n280, mult_x_254_n273, mult_x_254_n267,
mult_x_254_n264, mult_x_254_n263, mult_x_254_n262, mult_x_254_n261,
mult_x_254_n260, mult_x_254_n259, mult_x_254_n258, mult_x_254_n257,
mult_x_254_n256, mult_x_254_n255, mult_x_254_n254, mult_x_254_n253,
mult_x_254_n252, mult_x_254_n251, mult_x_254_n250, mult_x_254_n249,
mult_x_254_n248, mult_x_254_n247, mult_x_254_n246, mult_x_254_n245,
mult_x_254_n244, mult_x_254_n243, mult_x_254_n242, mult_x_254_n241,
mult_x_254_n240, mult_x_254_n239, mult_x_254_n238, mult_x_254_n237,
mult_x_254_n236, mult_x_254_n235, mult_x_254_n234, mult_x_254_n233,
mult_x_254_n232, mult_x_254_n231, mult_x_254_n230, mult_x_254_n229,
mult_x_254_n228, mult_x_254_n227, mult_x_254_n226, mult_x_254_n225,
mult_x_254_n224, mult_x_254_n223, mult_x_254_n221, mult_x_254_n220,
mult_x_254_n219, mult_x_254_n218, mult_x_254_n217, mult_x_254_n216,
mult_x_254_n215, mult_x_254_n214, mult_x_254_n211, mult_x_254_n210,
mult_x_254_n209, mult_x_254_n208, mult_x_254_n207, mult_x_254_n206,
mult_x_254_n205, mult_x_254_n204, mult_x_254_n203, mult_x_254_n202,
mult_x_254_n201, mult_x_254_n200, mult_x_254_n199, mult_x_254_n198,
mult_x_254_n197, mult_x_254_n196, mult_x_254_n195, mult_x_254_n194,
mult_x_254_n193, mult_x_254_n192, mult_x_254_n191, mult_x_254_n190,
mult_x_254_n189, mult_x_254_n188, mult_x_254_n187, mult_x_254_n186,
mult_x_254_n185, mult_x_254_n184, mult_x_254_n183, mult_x_254_n182,
mult_x_254_n179, mult_x_254_n178, mult_x_254_n177, mult_x_254_n176,
mult_x_254_n175, mult_x_254_n174, mult_x_254_n173, mult_x_254_n172,
mult_x_254_n171, mult_x_254_n170, mult_x_254_n169, mult_x_254_n168,
mult_x_254_n167, mult_x_254_n166, mult_x_254_n165, mult_x_254_n164,
mult_x_254_n163, mult_x_254_n162, n2194, n2195, n2196, n2197, n2198,
n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208,
n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218,
n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228,
n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238,
n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248,
n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258,
n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268,
n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278,
n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288,
n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298,
n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308,
n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318,
n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328,
n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338,
n2339, n2340, n2341, n2342, n2343, n2345, n2346, n2347, n2348, n2349,
n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359,
n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369,
n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379,
n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389,
n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399,
n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409,
n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419,
n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429,
n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439,
n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449,
n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459,
n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469,
n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479,
n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489,
n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499,
n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509,
n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519,
n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529,
n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539,
n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549,
n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559,
n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569,
n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579,
n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589,
n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599,
n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609,
n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619,
n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629,
n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639,
n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649,
n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659,
n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669,
n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679,
n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689,
n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699,
n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709,
n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719,
n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729,
n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739,
n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749,
n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759,
n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769,
n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779,
n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789,
n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859,
n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869,
n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879,
n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889,
n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949,
n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959,
n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969,
n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979,
n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989,
n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999,
n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009,
n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019,
n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029,
n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039,
n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049,
n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059,
n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069,
n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079,
n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089,
n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099,
n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109,
n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119,
n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129,
n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139,
n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149,
n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159,
n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169,
n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179,
n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189,
n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199,
n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209,
n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219,
n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229,
n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239,
n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249,
n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259,
n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269,
n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279,
n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289,
n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299,
n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309,
n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319,
n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329,
n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339,
n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349,
n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359,
n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369,
n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379,
n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389,
n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399,
n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409,
n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419,
n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429,
n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439,
n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449,
n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459,
n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469,
n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479,
n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489,
n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499,
n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509,
n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3518, n3519, n3520,
n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530,
n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540,
n3541, n3542, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551,
n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561,
n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571,
n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581,
n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591,
n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601,
n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611,
n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621,
n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631,
n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641,
n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651,
n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661,
n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671,
n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681,
n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691,
n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701,
n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711,
n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721,
n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731,
n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741,
n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751,
n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761,
n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771,
n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781,
n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791,
n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801,
n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811,
n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821,
n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831,
n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841,
n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851,
n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861,
n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871,
n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881,
n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891,
n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901,
n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911,
n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921,
n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931,
n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941,
n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951,
n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961,
n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971,
n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981,
n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991,
n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001,
n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011,
n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021,
n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031,
n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041,
n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051,
n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061,
n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071,
n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081,
n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091,
n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101,
n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111,
n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121,
n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131,
n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141,
n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151,
n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161,
n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171,
n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181,
n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191,
n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201,
n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211,
n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221,
n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231,
n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241,
n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251,
n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261,
n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271,
n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281,
n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291,
n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301,
n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311,
n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321,
n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331,
n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341,
n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351,
n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361,
n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371,
n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381,
n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391,
n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401,
n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411,
n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421,
n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431,
n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441,
n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451,
n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461,
n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471,
n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481,
n4482, n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491,
n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501,
n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511,
n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521,
n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531,
n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541,
n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551,
n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561,
n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571,
n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581,
n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591,
n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601,
n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611,
n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621,
n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631,
n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641,
n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651,
n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661,
n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671,
n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681,
n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691,
n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701,
n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711,
n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721,
n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731,
n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741,
n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751,
n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761,
n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771,
n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781,
n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791,
n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801,
n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811,
n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821,
n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831,
n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841,
n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851,
n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861,
n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871,
n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881,
n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891,
n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901,
n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911,
n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921,
n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931,
n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941,
n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951,
n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961,
n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971,
n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981,
n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991,
n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001,
n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011,
n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021,
n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031,
n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041,
n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051,
n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061,
n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071,
n5072, n5073, n5074, n5075, n5076, n5077, n5079, n5080, n5081, n5082,
n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092,
n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102,
n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112,
n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122,
n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132,
n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142,
n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152,
n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162,
n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172,
n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182,
n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192,
n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202,
n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212,
n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222,
n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232,
n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242,
n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252,
n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262,
n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272,
n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282,
n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292,
n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302,
n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312,
n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322,
n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332,
n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342,
n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352,
n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362,
n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372,
n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382,
n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392,
n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402,
n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412,
n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422,
n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432,
n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442,
n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452,
n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462,
n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472,
n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482,
n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492,
n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502,
n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512,
n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522,
n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532,
n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542,
n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552,
n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562,
n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572,
n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582,
n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592,
n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602,
n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612,
n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622,
n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632,
n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642,
n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652,
n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662,
n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672,
n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682,
n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692,
n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702,
n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712,
n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722,
n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732,
n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742,
n5743, n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752,
n5753, n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762,
n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772,
n5773, n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782,
n5783, n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792,
n5793, n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802,
n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812,
n5813, n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823,
n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833,
n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843,
n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853,
n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863,
n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873,
n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883,
n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893,
n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903,
n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913,
n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923,
n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933,
n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943,
n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953,
n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963,
n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973,
n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983,
n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993,
n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003,
n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013,
n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023,
n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033,
n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043,
n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053,
n6054, n6055, n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063,
n6064, n6065, n6066, n6067, n6068, n6069, n6071, n6072, n6073, n6074,
n6075, n6076;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:23] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:3] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [30:1] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:0] FPMULT_P_Sgf;
wire [25:1] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [25:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [11:1] FPMULT_Sgf_operation_Result;
wire [25:0] FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle;
wire [23:12] FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right;
wire [23:0] FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n6039), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n6039), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n6038), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n6036), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n6036), .Q(
dataB[31]) );
DFFRXLTS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2139), .CK(clk), .RN(n6035),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n5827) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2145), .CK(clk), .RN(
n6005), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]), .QN(n5902) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2144), .CK(clk), .RN(
n5998), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n2535) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2143), .CK(clk), .RN(
n6007), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n2218) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n6034),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2130), .CK(clk), .RN(n6034), .Q(
FPSENCOS_d_ff3_LUT_out[3]), .QN(n5948) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2127), .CK(clk), .RN(n6034), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2125), .CK(clk), .RN(n6033), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2124), .CK(clk), .RN(n6033), .Q(
FPSENCOS_d_ff3_LUT_out[9]), .QN(n5947) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2122), .CK(clk), .RN(n6033), .Q(
FPSENCOS_d_ff3_LUT_out[12]), .QN(n5950) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2121), .CK(clk), .RN(n6033), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2120), .CK(clk), .RN(n6033), .Q(
FPSENCOS_d_ff3_LUT_out[15]), .QN(n5949) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2119), .CK(clk), .RN(n6033), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2118), .CK(clk), .RN(n6033), .Q(
FPSENCOS_d_ff3_LUT_out[21]), .QN(n5951) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2113), .CK(clk), .RN(n6032), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1852), .CK(clk), .RN(n6032),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1851), .CK(clk), .RN(n6032),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1850), .CK(clk), .RN(n6032),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1849), .CK(clk), .RN(n6032),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1848), .CK(clk), .RN(n6032),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1847), .CK(clk), .RN(n6031),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1846), .CK(clk), .RN(n6031),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1951), .CK(clk), .RN(n6031),
.Q(FPSENCOS_d_ff3_sh_x_out[23]), .QN(n5946) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1950), .CK(clk), .RN(n6031),
.QN(n2452) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1949), .CK(clk), .RN(n6031),
.QN(n2468) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1948), .CK(clk), .RN(n6031),
.QN(n2487) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1947), .CK(clk), .RN(n6031),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1946), .CK(clk), .RN(n6031),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1945), .CK(clk), .RN(n6031),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1944), .CK(clk), .RN(n6031),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2112), .CK(clk), .RN(n6036), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2111), .CK(clk), .RN(n6051), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2110), .CK(clk), .RN(n6051), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2109), .CK(clk), .RN(n6051), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2108), .CK(clk), .RN(n6051), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2107), .CK(clk), .RN(n6051), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2106), .CK(clk), .RN(n6051), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2105), .CK(clk), .RN(n6051), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2104), .CK(clk), .RN(n6051), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2103), .CK(clk), .RN(n6050), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2102), .CK(clk), .RN(n6050), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2101), .CK(clk), .RN(n6050), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2100), .CK(clk), .RN(n6050), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2099), .CK(clk), .RN(n6050), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2098), .CK(clk), .RN(n6050), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2097), .CK(clk), .RN(n6050), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2096), .CK(clk), .RN(n6050), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2095), .CK(clk), .RN(n6050), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2094), .CK(clk), .RN(n6050), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2093), .CK(clk), .RN(n6049), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2092), .CK(clk), .RN(n6049), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2091), .CK(clk), .RN(n6049), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2090), .CK(clk), .RN(n6049), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2089), .CK(clk), .RN(n6049), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2088), .CK(clk), .RN(n6049), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2087), .CK(clk), .RN(n6049), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2086), .CK(clk), .RN(n6049), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2085), .CK(clk), .RN(n6049), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2084), .CK(clk), .RN(n6049), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2083), .CK(clk), .RN(n6048), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2082), .CK(clk), .RN(n6048), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2081), .CK(clk), .RN(n6048), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n6048), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n6047), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1860), .CK(clk), .RN(
n6047), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n5942) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n6047), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1859), .CK(clk), .RN(
n6046), .Q(FPSENCOS_d_ff2_Y[25]), .QN(n5943) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n6046), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1858), .CK(clk), .RN(
n6046), .Q(FPSENCOS_d_ff2_Y[26]), .QN(n5944) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n6045), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n6044), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1736), .CK(clk), .RN(
n6044), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1856), .CK(clk), .RN(
n6044), .Q(FPSENCOS_d_ff2_Y[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1698), .CK(clk), .RN(n6044),
.Q(cordic_result[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n6044), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1765), .CK(clk), .RN(n6043), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1854), .CK(clk), .RN(
n6043), .Q(FPSENCOS_d_ff2_Y[30]), .QN(n5910) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n6042), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1742), .CK(clk), .RN(
n6042), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1863), .CK(clk), .RN(
n6042), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1862), .CK(clk), .RN(n6042),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1960), .CK(clk), .RN(n6042),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n6042), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1749), .CK(clk), .RN(
n6041), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1877), .CK(clk), .RN(
n6041), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1876), .CK(clk), .RN(n6041),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1974), .CK(clk), .RN(n6041),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n6041), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1746), .CK(clk), .RN(
n6041), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1871), .CK(clk), .RN(
n6040), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1870), .CK(clk), .RN(n6040),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1968), .CK(clk), .RN(n6040),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n6040), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1743), .CK(clk), .RN(
n6040), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1865), .CK(clk), .RN(
n6040), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1864), .CK(clk), .RN(n6040),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1962), .CK(clk), .RN(n6020),
.QN(n2458) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n6019), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1745), .CK(clk), .RN(
n6019), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1869), .CK(clk), .RN(
n6019), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1868), .CK(clk), .RN(n6019),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1966), .CK(clk), .RN(n6019),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n6019), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1744), .CK(clk), .RN(
n6019), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1866), .CK(clk), .RN(n4008),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1964), .CK(clk), .RN(n6052),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n4005), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1747), .CK(clk), .RN(
n4007), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1872), .CK(clk), .RN(n6017),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1970), .CK(clk), .RN(n6017),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n6017), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1760), .CK(clk), .RN(
n6017), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1899), .CK(clk), .RN(
n6017), .Q(FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1898), .CK(clk), .RN(n6017),
.Q(FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1996), .CK(clk), .RN(n6016),
.QN(n2490) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n6016), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1758), .CK(clk), .RN(
n6016), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1895), .CK(clk), .RN(
n6016), .Q(FPSENCOS_d_ff2_Y[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1894), .CK(clk), .RN(n6016),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1992), .CK(clk), .RN(n6016),
.QN(n2273) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n6018), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1751), .CK(clk), .RN(
n4004), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1881), .CK(clk), .RN(
n6052), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1880), .CK(clk), .RN(n4008),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1978), .CK(clk), .RN(n6015),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n4008), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1748), .CK(clk), .RN(
n6014), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1875), .CK(clk), .RN(
n6018), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1874), .CK(clk), .RN(n4005),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1972), .CK(clk), .RN(n6052),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n4008), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1756), .CK(clk), .RN(
n4007), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1891), .CK(clk), .RN(
n6013), .Q(FPSENCOS_d_ff2_Y[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1890), .CK(clk), .RN(n6013),
.Q(FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1988), .CK(clk), .RN(n6013),
.QN(n2477) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n6013), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1753), .CK(clk), .RN(
n6013), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1885), .CK(clk), .RN(
n6013), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1884), .CK(clk), .RN(n6013),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1982), .CK(clk), .RN(n6012),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n6012), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1750), .CK(clk), .RN(
n6012), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1878), .CK(clk), .RN(n6012),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1976), .CK(clk), .RN(n6011),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n6011), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1754), .CK(clk), .RN(
n6011), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1886), .CK(clk), .RN(n6011),
.Q(FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1984), .CK(clk), .RN(n6011),
.QN(n2456) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n6011), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1752), .CK(clk), .RN(
n6010), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1883), .CK(clk), .RN(
n6010), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1882), .CK(clk), .RN(n6010),
.Q(FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1980), .CK(clk), .RN(n6010),
.QN(n2457) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1909), .CK(clk), .RN(n6010), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1908), .CK(clk), .RN(n6009), .Q(
FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1844), .CK(clk), .RN(n6009),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1727), .CK(clk), .RN(n6009), .Q(
FPSENCOS_d_ff_Xn[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1942), .CK(clk), .RN(n6009),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n6009), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1761), .CK(clk), .RN(
n6009), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1901), .CK(clk), .RN(
n6009), .Q(FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1900), .CK(clk), .RN(n6008),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n1998), .CK(clk), .RN(n6008),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1723), .CK(clk), .RN(n6008),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n6008), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1762), .CK(clk), .RN(
n6008), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1903), .CK(clk), .RN(
n6020), .Q(FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1902), .CK(clk), .RN(n6030),
.Q(FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2000), .CK(clk), .RN(n6030),
.QN(n2467) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1724), .CK(clk), .RN(n6030),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n6030), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1757), .CK(clk), .RN(
n6030), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1892), .CK(clk), .RN(n6029),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1990), .CK(clk), .RN(n6029),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1719), .CK(clk), .RN(n6029),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n6029), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1764), .CK(clk), .RN(
n6029), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1906), .CK(clk), .RN(n6029),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2004), .CK(clk), .RN(n6028),
.QN(n2474) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1726), .CK(clk), .RN(n6028),
.Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n6028), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1763), .CK(clk), .RN(
n6028), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1905), .CK(clk), .RN(
n6028), .Q(FPSENCOS_d_ff2_Y[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1904), .CK(clk), .RN(n6028),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2002), .CK(clk), .RN(n6027),
.QN(n2486) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1725), .CK(clk), .RN(n6027),
.Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n6027), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1755), .CK(clk), .RN(
n6027), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1889), .CK(clk), .RN(
n6027), .Q(FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1888), .CK(clk), .RN(n6027),
.Q(FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1986), .CK(clk), .RN(n6026),
.QN(n2488) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1717), .CK(clk), .RN(n6026),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n6026), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1759), .CK(clk), .RN(
n6026), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1897), .CK(clk), .RN(
n6026), .Q(FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1896), .CK(clk), .RN(n6026),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1994), .CK(clk), .RN(n6026),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1721), .CK(clk), .RN(n6025),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1714), .CK(clk), .RN(n6025),
.Q(cordic_result[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1715), .CK(clk), .RN(n6025),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1718), .CK(clk), .RN(n6025),
.Q(cordic_result[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1710), .CK(clk), .RN(n6025),
.Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1713), .CK(clk), .RN(n6025),
.Q(cordic_result[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1720), .CK(clk), .RN(n6025),
.Q(cordic_result[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1722), .CK(clk), .RN(n6024),
.Q(cordic_result[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1707), .CK(clk), .RN(n6024),
.Q(cordic_result[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1705), .CK(clk), .RN(n6024),
.Q(cordic_result[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1708), .CK(clk), .RN(n6024),
.Q(cordic_result[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1711), .CK(clk), .RN(n6024),
.Q(cordic_result[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1704), .CK(clk), .RN(n6024),
.Q(cordic_result[22]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1624), .CK(clk),
.RN(n4010), .Q(FPMULT_Op_MY[31]) );
DFFRXLTS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1691), .CK(clk), .RN(n6021),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n2217) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1679), .CK(clk),
.RN(n6067), .Q(FPMULT_Op_MX[21]), .QN(n2242) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1678), .CK(clk),
.RN(n6067), .Q(FPMULT_Op_MX[20]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1676), .CK(clk),
.RN(n6067), .Q(FPMULT_Op_MX[18]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n1672), .CK(clk),
.RN(n6067), .Q(FPMULT_Op_MX[14]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n1671), .CK(clk),
.RN(n6067), .Q(FPMULT_Op_MX[13]), .QN(n2525) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n1670), .CK(clk),
.RN(n6067), .Q(FPMULT_Op_MX[12]), .QN(n2520) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1669), .CK(clk),
.RN(n6066), .Q(FPMULT_Op_MX[11]), .QN(n2455) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1664), .CK(clk),
.RN(n6066), .Q(n2213), .QN(n2499) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1662), .CK(clk),
.RN(n6066), .Q(n2209), .QN(n2501) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n1661), .CK(clk),
.RN(n6066), .Q(FPMULT_Op_MX[3]), .QN(n2500) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n1660), .CK(clk),
.RN(n6066), .Q(FPMULT_Op_MX[2]), .QN(n2517) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1657), .CK(clk),
.RN(n6065), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1596), .CK(clk),
.RN(n6063), .Q(FPMULT_FSM_add_overflow_flag), .QN(n5904) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1643), .CK(clk),
.RN(n6061), .Q(n2207), .QN(n2238) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1642), .CK(clk),
.RN(n6061), .Q(n2206), .QN(n2524) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1640), .CK(clk),
.RN(n6061), .Q(FPMULT_Op_MY[14]), .QN(n2420) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1633), .CK(clk),
.RN(n6060), .Q(FPMULT_Op_MY[7]), .QN(n2247) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1632), .CK(clk),
.RN(n6060), .Q(FPMULT_Op_MY[6]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1631), .CK(clk),
.RN(n6060), .Q(FPMULT_Op_MY[5]), .QN(n2243) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1630), .CK(clk),
.RN(n6060), .Q(FPMULT_Op_MY[4]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1629), .CK(clk),
.RN(n6060), .Q(FPMULT_Op_MY[3]), .QN(n2483) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1625), .CK(
clk), .RN(n6060), .Q(FPMULT_zero_flag), .QN(n5952) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_23_ ( .D(n1552),
.CK(clk), .RN(n6021), .Q(FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_22_ ( .D(n1551),
.CK(clk), .RN(n6023), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_14_ ( .D(n1543),
.CK(clk), .RN(n6023), .Q(FPMULT_P_Sgf[14]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_12_ ( .D(n1541),
.CK(clk), .RN(n6023), .Q(FPMULT_P_Sgf[12]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_10_ ( .D(n1539),
.CK(clk), .RN(n6023), .Q(FPMULT_P_Sgf[10]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_9_ ( .D(n1538),
.CK(clk), .RN(n6023), .Q(FPMULT_P_Sgf[9]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_2_ ( .D(n1531),
.CK(clk), .RN(n6023), .Q(FPMULT_P_Sgf[2]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_0_ ( .D(n1529),
.CK(clk), .RN(n6023), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1621), .CK(
clk), .RN(n6058), .Q(FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1576), .CK(clk), .RN(n6056), .Q(mult_result[31]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1584), .CK(clk), .RN(n6056), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1583), .CK(clk), .RN(n6055), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1582), .CK(clk), .RN(n6055), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1581), .CK(clk), .RN(n6055), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1580), .CK(clk), .RN(n6055), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1579), .CK(clk), .RN(n6055), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1578), .CK(clk), .RN(n6055), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1577), .CK(clk), .RN(n6055), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1504), .CK(clk), .RN(n6055), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1503), .CK(clk), .RN(n6055), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1502), .CK(clk), .RN(n6055), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1501), .CK(clk), .RN(n6054), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1500), .CK(clk), .RN(n6054), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1499), .CK(clk), .RN(n6054), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1498), .CK(clk), .RN(n6054), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1497), .CK(clk), .RN(n6054), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1496), .CK(clk), .RN(n6054), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1495), .CK(clk), .RN(n6054), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1494), .CK(clk), .RN(n6054), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1493), .CK(clk), .RN(n6054), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1492), .CK(clk), .RN(n6054), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1491), .CK(clk), .RN(n6053), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1490), .CK(clk), .RN(n6053), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1489), .CK(clk), .RN(n6053), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1488), .CK(clk), .RN(n6053), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1487), .CK(clk), .RN(n6053), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1486), .CK(clk), .RN(n6053), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1485), .CK(clk), .RN(n6053), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1484), .CK(clk), .RN(n6053), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1483), .CK(clk), .RN(n6053), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1481), .CK(clk), .RN(n6053), .Q(mult_result[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1478), .CK(clk), .RN(
n5977), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1477), .CK(clk), .RN(
n5977), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1476), .CK(clk), .RN(
n5977), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1475), .CK(clk), .RN(
n5977), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1474), .CK(clk), .RN(
n5977), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1472), .CK(clk), .RN(
n5996), .Q(result_add_subt[24]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1470), .CK(clk), .RN(
n5996), .Q(result_add_subt[26]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1469), .CK(clk), .RN(
n5997), .Q(result_add_subt[27]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1468), .CK(clk), .RN(
n5997), .Q(result_add_subt[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1460), .CK(clk), .RN(n4011),
.Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1459), .CK(clk), .RN(n5978),
.Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1458), .CK(clk), .RN(n4012),
.Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n5982),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1456), .CK(clk), .RN(n4006),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1455), .CK(clk), .RN(n4009),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1454), .CK(clk), .RN(
n6005), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n5983),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1451), .CK(clk), .RN(n5978),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1450), .CK(clk), .RN(n5979),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1449), .CK(clk), .RN(
n6006), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n5980),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(clk), .RN(n4011),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1445), .CK(clk), .RN(n5982),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1444), .CK(clk), .RN(
n6006), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n5983),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(clk), .RN(n4012),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1440), .CK(clk), .RN(n4006),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1439), .CK(clk), .RN(
n6006), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n4009),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1436), .CK(clk), .RN(n5983),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1435), .CK(clk), .RN(n5978),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1434), .CK(clk), .RN(
n6006), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n5979),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1431), .CK(clk), .RN(n5982),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1430), .CK(clk), .RN(n2411),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1429), .CK(clk), .RN(
n6006), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n4006),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1426), .CK(clk), .RN(n4012),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1425), .CK(clk), .RN(n4009),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1424), .CK(clk), .RN(
n6007), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n5983),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1421), .CK(clk), .RN(n5978),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1420), .CK(clk), .RN(n5979),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1419), .CK(clk), .RN(
n6007), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1412), .CK(clk), .RN(n5981), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1411), .CK(clk), .RN(n5997), .Q(overflow_flag_addsubt) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1410), .CK(clk), .RN(
n5996), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1409), .CK(clk), .RN(
n5997), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1407), .CK(clk), .RN(n5981),
.Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1406), .CK(clk), .RN(
n5993), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1404), .CK(clk), .RN(n5981),
.Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1403), .CK(clk), .RN(
n5993), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1401), .CK(clk), .RN(n5981),
.Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1400), .CK(clk), .RN(
n5993), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1398), .CK(clk), .RN(n5980),
.Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1397), .CK(clk), .RN(
n5993), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1395), .CK(clk), .RN(n4011),
.Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1394), .CK(clk), .RN(
n5993), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1392), .CK(clk), .RN(n5982),
.Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1391), .CK(clk), .RN(
n5993), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1389), .CK(clk), .RN(n4012),
.Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1388), .CK(clk), .RN(
n5993), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1386), .CK(clk), .RN(n5982),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1385), .CK(clk), .RN(
n5993), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1383), .CK(clk), .RN(n4006),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1382), .CK(clk), .RN(
n5993), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1380), .CK(clk), .RN(n5983),
.Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1379), .CK(clk), .RN(
n5978), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1377), .CK(clk), .RN(n5979),
.Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1376), .CK(clk), .RN(
n5980), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1374), .CK(clk), .RN(n4011),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1373), .CK(clk), .RN(
n5984), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1371), .CK(clk), .RN(n5984),
.Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1370), .CK(clk), .RN(
n5984), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1368), .CK(clk), .RN(n5984),
.Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1367), .CK(clk), .RN(
n5984), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1365), .CK(clk), .RN(n5984),
.Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1364), .CK(clk), .RN(
n5984), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n5985),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n5985), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1360), .CK(clk), .RN(n5985), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1359), .CK(clk), .RN(n5985),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1358), .CK(clk), .RN(n5985),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(
n5992), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1356), .CK(clk), .RN(
n5985), .Q(result_add_subt[31]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n5985),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n5985), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1353), .CK(clk), .RN(n5985), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1351), .CK(clk), .RN(n5998),
.Q(FPADDSUB_ADD_OVRFLW_NRM), .QN(n5861) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1349), .CK(clk), .RN(
n5995), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1340), .CK(clk), .RN(
n5994), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n5842) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1335), .CK(clk), .RN(
n5995), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n5839) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1334), .CK(clk), .RN(
n5996), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n5941) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1331), .CK(clk), .RN(
n5995), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n5857) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1330), .CK(clk), .RN(
n6005), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1328), .CK(clk), .RN(n5986),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(
n5992), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n5986),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n5986),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n5961), .CK(clk), .RN(n6001),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1322), .CK(clk), .RN(
n5997), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1318), .CK(clk), .RN(
n5997), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1317), .CK(clk), .RN(
n5995), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1316), .CK(clk), .RN(
n5996), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1315), .CK(clk), .RN(
n5996), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1312), .CK(clk), .RN(n5986),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(
n5992), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n5986),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n5986),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n5960), .CK(clk), .RN(n6001),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1305), .CK(clk), .RN(n5986),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(
n5987), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n5987),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n5987),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n5959), .CK(clk), .RN(n6002),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1298), .CK(clk), .RN(n5987),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(
n5992), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n5987),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n5987),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n5958), .CK(clk), .RN(n6001),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1291), .CK(clk), .RN(n5987),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(
n5992), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n5987),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n5988),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n5957), .CK(clk), .RN(n6001),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1284), .CK(clk), .RN(n5988),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(
n5988), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n5988),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n5988),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1280), .CK(clk), .RN(n6002),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1277), .CK(clk), .RN(n5988),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(
n5993), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n5988),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n5988),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n5956), .CK(clk), .RN(n6002),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1271), .CK(clk), .RN(n5989),
.Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(
n5989), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n5989),
.Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n5989),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1267), .CK(clk), .RN(n6003),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n5989),
.Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n5989),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1263), .CK(clk), .RN(n6003),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n5989),
.Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n5989),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1259), .CK(clk), .RN(n6003),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n5989),
.Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n5989),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1255), .CK(clk), .RN(n6003),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n5990),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n5990),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1251), .CK(clk), .RN(n6002),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n5990),
.Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n5990),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1247), .CK(clk), .RN(n6004),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n5990),
.Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n5990),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1243), .CK(clk), .RN(n6003),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n5990),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n5990),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n5955), .CK(clk), .RN(n6002),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n5990),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n5990),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n5954), .CK(clk), .RN(n6001),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n5991),
.Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n5991),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1231), .CK(clk), .RN(n6004),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n5991),
.Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n5991),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1227), .CK(clk), .RN(n6005),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n5991),
.Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n5991),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1223), .CK(clk), .RN(n6004),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n5991),
.Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n5991),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1219), .CK(clk), .RN(n6005),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n5991),
.Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n5991),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1215), .CK(clk), .RN(n6004),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n5992),
.Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n5992),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1211), .CK(clk), .RN(n6004),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n5992),
.Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n5992),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1207), .CK(clk), .RN(n6005),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1180), .CK(clk), .RN(
n6000), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n5940) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_19_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_20_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_21_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_22_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_23_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_24_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N24), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_25_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N25), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]) );
DFFHQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_2_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[2]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_19_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_21_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[21]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_22_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[22]) );
CMPR32X2TS DP_OP_234J16_127_8543_U9 ( .A(DP_OP_234J16_127_8543_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J16_127_8543_n9), .CO(
DP_OP_234J16_127_8543_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J16_127_8543_U8 ( .A(DP_OP_234J16_127_8543_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J16_127_8543_n8), .CO(
DP_OP_234J16_127_8543_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J16_127_8543_U7 ( .A(DP_OP_234J16_127_8543_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J16_127_8543_n7), .CO(
DP_OP_234J16_127_8543_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J16_127_8543_U6 ( .A(DP_OP_234J16_127_8543_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J16_127_8543_n6), .CO(
DP_OP_234J16_127_8543_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J16_127_8543_U5 ( .A(DP_OP_234J16_127_8543_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J16_127_8543_n5), .CO(
DP_OP_234J16_127_8543_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J16_127_8543_U4 ( .A(DP_OP_234J16_127_8543_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J16_127_8543_n4), .CO(
DP_OP_234J16_127_8543_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J16_127_8543_U3 ( .A(DP_OP_234J16_127_8543_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J16_127_8543_n3), .CO(
DP_OP_234J16_127_8543_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS intadd_21_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n5844), .C(
intadd_21_CI), .CO(intadd_21_n3), .S(intadd_21_SUM_0_) );
CMPR32X2TS intadd_21_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n2301), .C(
intadd_21_n3), .CO(intadd_21_n2), .S(intadd_21_SUM_1_) );
CMPR32X2TS intadd_21_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n5821), .C(
intadd_21_n2), .CO(intadd_21_n1), .S(intadd_21_SUM_2_) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1512), .CK(
clk), .RN(n6057), .Q(FPMULT_Sgf_normalized_result[7]), .QN(n5939) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1515), .CK(
clk), .RN(n6057), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n5938) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1954), .CK(clk), .RN(
n6044), .Q(FPSENCOS_d_ff2_X[28]), .QN(n5907) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1511), .CK(
clk), .RN(n6056), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n5899) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1509), .CK(
clk), .RN(n6056), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n5898) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1465), .CK(clk), .RN(n5977),
.Q(FPADDSUB_DMP_EXP_EWSW[23]), .QN(n5869) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1812), .CK(clk), .RN(n5975), .Q(FPADDSUB_Data_array_SWR[25]), .QN(n5868) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1810), .CK(clk), .RN(n5975), .Q(FPADDSUB_Data_array_SWR[23]), .QN(n5867) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1809), .CK(clk), .RN(n5975), .Q(FPADDSUB_Data_array_SWR[22]), .QN(n5866) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1927), .CK(clk), .RN(
n5973), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n5863) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1926), .CK(clk), .RN(
n5969), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n5853) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1929), .CK(clk), .RN(
n5974), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n5852) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1921), .CK(clk), .RN(
n5971), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n5851) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1510), .CK(
clk), .RN(n6056), .Q(FPMULT_Sgf_normalized_result[5]), .QN(n5849) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1514), .CK(
clk), .RN(n6057), .Q(FPMULT_Sgf_normalized_result[9]), .QN(n5847) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1508), .CK(
clk), .RN(n6056), .Q(FPMULT_Sgf_normalized_result[3]), .QN(n5845) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1689), .CK(clk), .RN(n6068), .Q(
FPMULT_FSM_selector_A), .QN(n5900) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2140), .CK(clk), .RN(n6035),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n5844) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1693), .CK(clk), .RN(n6024),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n5841) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1338), .CK(clk), .RN(
n5995), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n5837) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1595), .CK(clk), .RN(
n6059), .Q(FPMULT_exp_oper_result[8]), .QN(n5834) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2080), .CK(clk), .RN(n6048),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n5832) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1808), .CK(clk), .RN(n5969), .Q(FPADDSUB_Data_array_SWR[21]), .QN(n5830) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1513), .CK(
clk), .RN(n6057), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n5825) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1622), .CK(clk), .RN(n6059), .Q(
FPMULT_FSM_selector_B[1]), .QN(n5822) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1690), .CK(clk), .RN(n6030),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n5819) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n6036), .Q(NaN_flag)
);
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1586), .CK(clk), .RN(
n6056), .Q(underflow_flag_mult), .QN(n5937) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2138), .CK(clk), .RN(n6035),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n5821) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_23_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[23]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n6035), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .QN(n5824) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1692), .CK(clk), .RN(n6021),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n5858) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n6035), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .QN(n5850) );
CMPR32X2TS DP_OP_234J16_127_8543_U2 ( .A(n2419), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_234J16_127_8543_n2), .CO(DP_OP_234J16_127_8543_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
CMPR42X2TS DP_OP_454J16_123_2743_U309 ( .A(DP_OP_454J16_123_2743_n456), .B(
DP_OP_454J16_123_2743_n469), .C(DP_OP_454J16_123_2743_n345), .D(
DP_OP_454J16_123_2743_n341), .ICI(DP_OP_454J16_123_2743_n338), .S(
DP_OP_454J16_123_2743_n335), .ICO(DP_OP_454J16_123_2743_n333), .CO(
DP_OP_454J16_123_2743_n334) );
CMPR42X1TS DP_OP_454J16_123_2743_U307 ( .A(DP_OP_454J16_123_2743_n339), .B(
DP_OP_454J16_123_2743_n332), .C(DP_OP_454J16_123_2743_n442), .D(
DP_OP_454J16_123_2743_n429), .ICI(DP_OP_454J16_123_2743_n455), .S(
DP_OP_454J16_123_2743_n330), .ICO(DP_OP_454J16_123_2743_n328), .CO(
DP_OP_454J16_123_2743_n329) );
CMPR42X2TS DP_OP_454J16_123_2743_U303 ( .A(DP_OP_454J16_123_2743_n441), .B(
DP_OP_454J16_123_2743_n454), .C(DP_OP_454J16_123_2743_n329), .D(
DP_OP_454J16_123_2743_n325), .ICI(DP_OP_454J16_123_2743_n322), .S(
DP_OP_454J16_123_2743_n319), .ICO(DP_OP_454J16_123_2743_n317), .CO(
DP_OP_454J16_123_2743_n318) );
CMPR42X2TS DP_OP_454J16_123_2743_U300 ( .A(DP_OP_454J16_123_2743_n315), .B(
DP_OP_454J16_123_2743_n427), .C(DP_OP_454J16_123_2743_n414), .D(
DP_OP_454J16_123_2743_n323), .ICI(DP_OP_454J16_123_2743_n320), .S(
DP_OP_454J16_123_2743_n313), .ICO(DP_OP_454J16_123_2743_n311), .CO(
DP_OP_454J16_123_2743_n312) );
CMPR42X2TS DP_OP_454J16_123_2743_U299 ( .A(DP_OP_454J16_123_2743_n453), .B(
DP_OP_454J16_123_2743_n440), .C(DP_OP_454J16_123_2743_n321), .D(
DP_OP_454J16_123_2743_n313), .ICI(DP_OP_454J16_123_2743_n317), .S(
DP_OP_454J16_123_2743_n310), .ICO(DP_OP_454J16_123_2743_n308), .CO(
DP_OP_454J16_123_2743_n309) );
CMPR42X2TS DP_OP_454J16_123_2743_U295 ( .A(DP_OP_454J16_123_2743_n426), .B(
DP_OP_454J16_123_2743_n439), .C(DP_OP_454J16_123_2743_n312), .D(
DP_OP_454J16_123_2743_n303), .ICI(DP_OP_454J16_123_2743_n308), .S(
DP_OP_454J16_123_2743_n300), .ICO(DP_OP_454J16_123_2743_n298), .CO(
DP_OP_454J16_123_2743_n299) );
CMPR42X1TS DP_OP_454J16_123_2743_U290 ( .A(DP_OP_454J16_123_2743_n388), .B(
DP_OP_454J16_123_2743_n290), .C(DP_OP_454J16_123_2743_n437), .D(
DP_OP_454J16_123_2743_n399), .ICI(DP_OP_454J16_123_2743_n294), .S(
DP_OP_454J16_123_2743_n288), .ICO(DP_OP_454J16_123_2743_n286), .CO(
DP_OP_454J16_123_2743_n287) );
CMPR42X2TS DP_OP_454J16_123_2743_U289 ( .A(DP_OP_454J16_123_2743_n411), .B(
DP_OP_454J16_123_2743_n424), .C(DP_OP_454J16_123_2743_n295), .D(
DP_OP_454J16_123_2743_n288), .ICI(DP_OP_454J16_123_2743_n291), .S(
DP_OP_454J16_123_2743_n285), .ICO(DP_OP_454J16_123_2743_n283), .CO(
DP_OP_454J16_123_2743_n284) );
CMPR42X2TS DP_OP_454J16_123_2743_U284 ( .A(DP_OP_454J16_123_2743_n397), .B(
DP_OP_454J16_123_2743_n409), .C(DP_OP_454J16_123_2743_n274), .D(
DP_OP_454J16_123_2743_n281), .ICI(DP_OP_454J16_123_2743_n277), .S(
DP_OP_454J16_123_2743_n272), .ICO(DP_OP_454J16_123_2743_n270), .CO(
DP_OP_454J16_123_2743_n271) );
CMPR42X2TS DP_OP_454J16_123_2743_U282 ( .A(DP_OP_454J16_123_2743_n408), .B(
DP_OP_454J16_123_2743_n269), .C(DP_OP_454J16_123_2743_n396), .D(
DP_OP_454J16_123_2743_n273), .ICI(DP_OP_454J16_123_2743_n270), .S(
DP_OP_454J16_123_2743_n267), .ICO(DP_OP_454J16_123_2743_n265), .CO(
DP_OP_454J16_123_2743_n266) );
CMPR42X2TS mult_x_219_U220 ( .A(mult_x_219_n319), .B(mult_x_219_n355), .C(
mult_x_219_n343), .D(mult_x_219_n331), .ICI(mult_x_219_n265), .S(
mult_x_219_n262), .ICO(mult_x_219_n260), .CO(mult_x_219_n261) );
CMPR42X2TS mult_x_219_U218 ( .A(mult_x_219_n342), .B(mult_x_219_n318), .C(
mult_x_219_n330), .D(mult_x_219_n259), .ICI(mult_x_219_n260), .S(
mult_x_219_n257), .ICO(mult_x_219_n255), .CO(mult_x_219_n256) );
CMPR42X2TS mult_x_219_U213 ( .A(mult_x_219_n340), .B(mult_x_219_n249), .C(
mult_x_219_n253), .D(mult_x_219_n247), .ICI(mult_x_219_n250), .S(
mult_x_219_n245), .ICO(mult_x_219_n243), .CO(mult_x_219_n244) );
CMPR42X2TS mult_x_219_U211 ( .A(mult_x_219_n315), .B(mult_x_219_n303), .C(
mult_x_219_n246), .D(mult_x_219_n243), .ICI(mult_x_219_n242), .S(
mult_x_219_n239), .ICO(mult_x_219_n237), .CO(mult_x_219_n238) );
CMPR42X1TS mult_x_219_U208 ( .A(mult_x_219_n326), .B(mult_x_219_n314), .C(
mult_x_219_n237), .D(mult_x_219_n241), .ICI(mult_x_219_n234), .S(
mult_x_219_n231), .ICO(mult_x_219_n229), .CO(mult_x_219_n230) );
CMPR42X2TS mult_x_219_U206 ( .A(mult_x_219_n313), .B(mult_x_219_n337), .C(
mult_x_219_n301), .D(mult_x_219_n235), .ICI(mult_x_219_n232), .S(
mult_x_219_n226), .ICO(mult_x_219_n224), .CO(mult_x_219_n225) );
CMPR42X1TS mult_x_219_U198 ( .A(mult_x_219_n311), .B(mult_x_219_n335), .C(
mult_x_219_n323), .D(mult_x_219_n209), .ICI(mult_x_219_n215), .S(
mult_x_219_n207), .ICO(mult_x_219_n205), .CO(mult_x_219_n206) );
CMPR42X2TS mult_x_219_U195 ( .A(mult_x_219_n310), .B(mult_x_219_n322), .C(
mult_x_219_n208), .D(mult_x_219_n201), .ICI(mult_x_219_n205), .S(
mult_x_219_n199), .ICO(mult_x_219_n197), .CO(mult_x_219_n198) );
CMPR42X1TS mult_x_219_U194 ( .A(mult_x_219_n298), .B(mult_x_219_n334), .C(
mult_x_219_n206), .D(mult_x_219_n199), .ICI(mult_x_219_n202), .S(
mult_x_219_n196), .ICO(mult_x_219_n194), .CO(mult_x_219_n195) );
CMPR42X2TS mult_x_219_U191 ( .A(mult_x_219_n200), .B(mult_x_219_n197), .C(
mult_x_219_n191), .D(mult_x_219_n198), .ICI(mult_x_219_n194), .S(
mult_x_219_n188), .ICO(mult_x_219_n186), .CO(mult_x_219_n187) );
CMPR42X1TS mult_x_219_U189 ( .A(mult_x_219_n320), .B(mult_x_219_n189), .C(
mult_x_219_n190), .D(mult_x_219_n185), .ICI(mult_x_219_n186), .S(
mult_x_219_n182), .ICO(mult_x_219_n180), .CO(mult_x_219_n181) );
CMPR42X2TS mult_x_254_U218 ( .A(mult_x_254_n337), .B(mult_x_254_n361), .C(
mult_x_254_n260), .D(mult_x_254_n257), .ICI(mult_x_254_n256), .S(
mult_x_254_n254), .ICO(mult_x_254_n252), .CO(mult_x_254_n253) );
CMPR42X2TS mult_x_254_U215 ( .A(mult_x_254_n348), .B(mult_x_254_n251), .C(
mult_x_254_n255), .D(mult_x_254_n249), .ICI(mult_x_254_n252), .S(
mult_x_254_n247), .ICO(mult_x_254_n245), .CO(mult_x_254_n246) );
CMPR42X1TS mult_x_254_U214 ( .A(mult_x_254_n299), .B(mult_x_254_n323), .C(
mult_x_254_n347), .D(mult_x_254_n311), .ICI(mult_x_254_n248), .S(
mult_x_254_n244), .ICO(mult_x_254_n242), .CO(mult_x_254_n243) );
CMPR42X1TS mult_x_254_U210 ( .A(mult_x_254_n346), .B(mult_x_254_n238), .C(
mult_x_254_n242), .D(mult_x_254_n243), .ICI(mult_x_254_n236), .S(
mult_x_254_n233), .ICO(mult_x_254_n231), .CO(mult_x_254_n232) );
CMPR42X1TS mult_x_254_U208 ( .A(mult_x_254_n321), .B(mult_x_254_n345), .C(
mult_x_254_n297), .D(mult_x_254_n357), .ICI(mult_x_254_n230), .S(
mult_x_254_n228), .ICO(mult_x_254_n226), .CO(mult_x_254_n227) );
CMPR42X1TS mult_x_254_U204 ( .A(mult_x_254_n320), .B(mult_x_254_n344), .C(
mult_x_254_n296), .D(n2249), .ICI(mult_x_254_n221), .S(mult_x_254_n219), .ICO(mult_x_254_n217), .CO(mult_x_254_n218) );
CMPR42X1TS mult_x_254_U200 ( .A(mult_x_254_n307), .B(mult_x_254_n343), .C(
mult_x_254_n331), .D(mult_x_254_n295), .ICI(mult_x_254_n220), .S(
mult_x_254_n209), .ICO(mult_x_254_n207), .CO(mult_x_254_n208) );
CMPR42X2TS mult_x_254_U199 ( .A(mult_x_254_n211), .B(mult_x_254_n217), .C(
mult_x_254_n218), .D(mult_x_254_n209), .ICI(mult_x_254_n214), .S(
mult_x_254_n206), .ICO(mult_x_254_n204), .CO(mult_x_254_n205) );
CMPR42X2TS mult_x_254_U196 ( .A(mult_x_254_n210), .B(mult_x_254_n203), .C(
mult_x_254_n208), .D(mult_x_254_n201), .ICI(mult_x_254_n204), .S(
mult_x_254_n198), .ICO(mult_x_254_n196), .CO(mult_x_254_n197) );
CMPR42X1TS mult_x_254_U194 ( .A(mult_x_254_n195), .B(mult_x_254_n329), .C(
mult_x_254_n317), .D(mult_x_254_n305), .ICI(mult_x_254_n202), .S(
mult_x_254_n193), .ICO(mult_x_254_n191), .CO(mult_x_254_n192) );
CMPR42X2TS mult_x_254_U193 ( .A(mult_x_254_n293), .B(mult_x_254_n199), .C(
mult_x_254_n200), .D(mult_x_254_n193), .ICI(mult_x_254_n196), .S(
mult_x_254_n190), .ICO(mult_x_254_n188), .CO(mult_x_254_n189) );
CMPR42X1TS mult_x_254_U192 ( .A(mult_x_254_n194), .B(mult_x_254_n282), .C(
mult_x_254_n316), .D(mult_x_254_n304), .ICI(mult_x_254_n328), .S(
mult_x_254_n187), .ICO(mult_x_254_n185), .CO(mult_x_254_n186) );
CMPR42X1TS mult_x_254_U191 ( .A(mult_x_254_n292), .B(mult_x_254_n191), .C(
mult_x_254_n187), .D(mult_x_254_n192), .ICI(mult_x_254_n188), .S(
mult_x_254_n184), .ICO(mult_x_254_n182), .CO(mult_x_254_n183) );
CMPR42X2TS DP_OP_454J16_123_2743_U296 ( .A(DP_OP_454J16_123_2743_n452), .B(
DP_OP_454J16_123_2743_n401), .C(DP_OP_454J16_123_2743_n413), .D(
DP_OP_454J16_123_2743_n305), .ICI(DP_OP_454J16_123_2743_n311), .S(
DP_OP_454J16_123_2743_n303), .ICO(DP_OP_454J16_123_2743_n301), .CO(
DP_OP_454J16_123_2743_n302) );
CMPR42X2TS DP_OP_454J16_123_2743_U317 ( .A(DP_OP_454J16_123_2743_n362), .B(
DP_OP_454J16_123_2743_n358), .C(DP_OP_454J16_123_2743_n472), .D(
DP_OP_454J16_123_2743_n459), .ICI(DP_OP_454J16_123_2743_n359), .S(
DP_OP_454J16_123_2743_n356), .ICO(DP_OP_454J16_123_2743_n354), .CO(
DP_OP_454J16_123_2743_n355) );
CMPR42X2TS mult_x_219_U197 ( .A(mult_x_219_n299), .B(mult_x_219_n218), .C(
mult_x_219_n216), .D(mult_x_219_n207), .ICI(mult_x_219_n212), .S(
mult_x_219_n204), .ICO(mult_x_219_n202), .CO(mult_x_219_n203) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1832), .CK(clk), .RN(
n5973), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n5817) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1842), .CK(clk), .RN(
n5976), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n5816) );
CMPR42X2TS DP_OP_454J16_123_2743_U292 ( .A(DP_OP_454J16_123_2743_n438), .B(
DP_OP_454J16_123_2743_n425), .C(DP_OP_454J16_123_2743_n302), .D(
DP_OP_454J16_123_2743_n296), .ICI(DP_OP_454J16_123_2743_n298), .S(
DP_OP_454J16_123_2743_n293), .ICO(DP_OP_454J16_123_2743_n291), .CO(
DP_OP_454J16_123_2743_n292) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1829), .CK(clk), .RN(
n5973), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n2475) );
CMPR42X2TS mult_x_219_U192 ( .A(n2524), .B(mult_x_219_n285), .C(
mult_x_219_n321), .D(mult_x_219_n297), .ICI(mult_x_219_n309), .S(
mult_x_219_n191), .ICO(mult_x_219_n189), .CO(mult_x_219_n190) );
CMPR42X2TS DP_OP_454J16_123_2743_U312 ( .A(DP_OP_454J16_123_2743_n444), .B(
DP_OP_454J16_123_2743_n350), .C(DP_OP_454J16_123_2743_n470), .D(
DP_OP_454J16_123_2743_n346), .ICI(DP_OP_454J16_123_2743_n347), .S(
DP_OP_454J16_123_2743_n343), .ICO(DP_OP_454J16_123_2743_n341), .CO(
DP_OP_454J16_123_2743_n342) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1286), .CK(clk), .RN(n6001),
.Q(FPADDSUB_DMP_SFG[1]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1293), .CK(clk), .RN(n6001),
.Q(FPADDSUB_DMP_SFG[0]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1279), .CK(clk), .RN(n6002),
.Q(FPADDSUB_DMP_SFG[9]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1250), .CK(clk), .RN(n6002),
.Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1300), .CK(clk), .RN(n6002),
.Q(FPADDSUB_DMP_SFG[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1238), .CK(clk), .RN(n6002),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1272), .CK(clk), .RN(n6002),
.Q(FPADDSUB_DMP_SFG[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1234), .CK(clk), .RN(n6001),
.Q(FPADDSUB_DMP_SFG[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1323), .CK(clk), .RN(n6001),
.Q(FPADDSUB_DMP_SFG[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1307), .CK(clk), .RN(n6001),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1648), .CK(clk),
.RN(n6062), .Q(FPMULT_Op_MY[22]), .QN(n2515) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1644), .CK(clk),
.RN(n6061), .Q(FPMULT_Op_MY[18]), .QN(n2512) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1637), .CK(clk),
.RN(n6061), .Q(FPMULT_Op_MY[11]), .QN(DP_OP_454J16_123_2743_n727) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1635), .CK(clk),
.RN(n6061), .Q(FPMULT_Op_MY[9]), .QN(n2508) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1634), .CK(clk),
.RN(n6060), .Q(FPMULT_Op_MY[8]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1339), .CK(clk), .RN(
n5995), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRXLTS R_12 ( .D(n5963), .CK(clk), .RN(n6037), .Q(n6072) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n5981), .QN(n5874) );
DFFX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_23_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .QN(
DP_OP_453J16_122_8745_n227) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n1658), .CK(clk),
.RN(n6065), .Q(FPMULT_Op_MX[0]), .QN(n2510) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1626), .CK(clk),
.RN(n6060), .Q(FPMULT_Op_MY[0]), .QN(n2230) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_16_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_20_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n1659), .CK(clk),
.RN(n6065), .Q(FPMULT_Op_MX[1]), .QN(n2509) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2148), .CK(clk), .RN(
n5967), .Q(FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n5818) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2136), .CK(clk), .RN(n6034),
.Q(FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1838), .CK(clk), .RN(
n5976), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1837), .CK(clk), .RN(
n5971), .Q(FPADDSUB_intDY_EWSW[6]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1827), .CK(clk), .RN(
n5972), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1833), .CK(clk), .RN(
n5973), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1841), .CK(clk), .RN(
n5975), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1816), .CK(clk), .RN(
n5968), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2147), .CK(clk), .RN(
n5967), .Q(FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n2272) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1843), .CK(clk), .RN(
n5975), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1824), .CK(clk), .RN(
n5970), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n2465) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1830), .CK(clk), .RN(
n5972), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n2494) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1822), .CK(clk), .RN(
n5970), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n2461) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1831), .CK(clk), .RN(
n5973), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n2459) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1918), .CK(clk), .RN(
n5967), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n5855) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1505), .CK(
clk), .RN(n6056), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1342), .CK(clk), .RN(
n5994), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n5967),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n2250) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1804), .CK(clk), .RN(n5976), .Q(FPADDSUB_Data_array_SWR[17]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1803), .CK(clk), .RN(n5971), .Q(FPADDSUB_Data_array_SWR[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1262), .CK(clk), .RN(n6003),
.Q(FPADDSUB_DMP_SFG[10]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1805), .CK(clk), .RN(n5976), .Q(FPADDSUB_Data_array_SWR[18]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1806), .CK(clk), .RN(n5971), .Q(FPADDSUB_Data_array_SWR[19]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1800), .CK(clk), .RN(n5973), .Q(FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1799), .CK(clk), .RN(n5972), .Q(FPADDSUB_Data_array_SWR[12]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1820), .CK(clk), .RN(
n5968), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n2469) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1825), .CK(clk), .RN(
n5970), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n2480) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1210), .CK(clk), .RN(n6004),
.Q(FPADDSUB_DMP_SFG[15]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1222), .CK(clk), .RN(n6004),
.Q(FPADDSUB_DMP_SFG[19]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1254), .CK(clk), .RN(n6003),
.Q(FPADDSUB_DMP_SFG[11]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1347), .CK(clk), .RN(
n5994), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1218), .CK(clk), .RN(n6005),
.Q(FPADDSUB_DMP_SFG[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1230), .CK(clk), .RN(n6004),
.Q(FPADDSUB_DMP_SFG[17]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1242), .CK(clk), .RN(n6003),
.Q(FPADDSUB_DMP_SFG[13]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1214), .CK(clk), .RN(n6004),
.Q(FPADDSUB_DMP_SFG[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1246), .CK(clk), .RN(n6004),
.Q(FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1258), .CK(clk), .RN(n6003),
.Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1507), .CK(
clk), .RN(n6056), .Q(FPMULT_Sgf_normalized_result[2]) );
DFFRX2TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1955), .CK(clk), .RN(
n6045), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1226), .CK(clk), .RN(n6005),
.Q(FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1266), .CK(clk), .RN(n6003),
.Q(FPADDSUB_DMP_SFG[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1206), .CK(clk), .RN(n6005),
.Q(FPADDSUB_DMP_SFG[22]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1471), .CK(clk), .RN(
n5996), .Q(result_add_subt[25]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n6035), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1933), .CK(clk), .RN(
n5972), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n2259) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1923), .CK(clk), .RN(
n5970), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n2223) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1930), .CK(clk), .RN(
n5973), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n2264) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1916), .CK(clk), .RN(
n5967), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n2224) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1346), .CK(clk), .RN(
n5994), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n2216) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1934), .CK(clk), .RN(
n5975), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n5865) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1343), .CK(clk), .RN(
n5994), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n5840) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1932), .CK(clk), .RN(
n5976), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n2265) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1818), .CK(clk), .RN(
n5968), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n5906) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1953), .CK(clk), .RN(
n6043), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(
n5974), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n6036), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1959), .CK(clk), .RN(
n6048), .Q(FPSENCOS_d_ff2_X[23]) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1585), .CK(clk), .RN(
n6058), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1466), .CK(clk), .RN(
n5997), .Q(result_add_subt[30]), .QN(n5913) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1467), .CK(clk), .RN(
n5997), .Q(result_add_subt[29]), .QN(n5911) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1473), .CK(clk), .RN(
n5996), .Q(result_add_subt[23]), .QN(n5912) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1345), .CK(clk), .RN(
n5994), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n5848) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1516), .CK(
clk), .RN(n6057), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1518), .CK(
clk), .RN(n6057), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1520), .CK(
clk), .RN(n6057), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1522), .CK(
clk), .RN(n6058), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1524), .CK(
clk), .RN(n6058), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1526), .CK(
clk), .RN(n6058), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1418), .CK(clk), .RN(
n6007), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1428), .CK(clk), .RN(
n6006), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1448), .CK(clk), .RN(
n6006), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1517), .CK(
clk), .RN(n6057), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1519), .CK(
clk), .RN(n6057), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1521), .CK(
clk), .RN(n6057), .Q(FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1523), .CK(
clk), .RN(n6058), .Q(FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1525), .CK(
clk), .RN(n6058), .Q(FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1527), .CK(
clk), .RN(n6058), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1348), .CK(clk), .RN(
n5994), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n2251) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1956), .CK(clk), .RN(
n6045), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1957), .CK(clk), .RN(
n6046), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1958), .CK(clk), .RN(
n6047), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1935), .CK(clk), .RN(
n5971), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n2511) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1687), .CK(clk),
.RN(n6068), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1941), .CK(clk), .RN(
n5975), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n2266) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1794), .CK(clk), .RN(n5972),
.Q(FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1793), .CK(clk), .RN(n5971),
.Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1417), .CK(clk), .RN(n4009),
.Q(FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1911), .CK(clk), .RN(
n5968), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n5829) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_47_ ( .D(n1694),
.CK(clk), .RN(n6021), .Q(FPMULT_P_Sgf[47]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1912), .CK(clk), .RN(
n5968), .Q(FPADDSUB_intDX_EWSW[29]), .QN(n5864) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1618), .CK(clk), .RN(
n6063), .Q(FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1616), .CK(clk), .RN(
n6063), .Q(FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1615), .CK(clk), .RN(
n6063), .Q(FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1614), .CK(clk), .RN(
n6064), .Q(FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1613), .CK(clk), .RN(
n6064), .Q(FPMULT_Add_result[7]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n6008),
.Q(operation_reg[0]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1685), .CK(clk),
.RN(n6068), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1352), .CK(clk), .RN(n5998),
.Q(FPADDSUB_OP_FLAG_SFG) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1656), .CK(clk),
.RN(n6063), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1682), .CK(clk),
.RN(n6068), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1952), .CK(clk), .RN(
n6043), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1196), .CK(clk), .RN(
n5999), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n5925) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1200), .CK(clk), .RN(
n5998), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n5927) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1653), .CK(clk),
.RN(n6062), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1733), .CK(clk), .RN(
n6010), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1587), .CK(clk), .RN(
n6058), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1589), .CK(clk), .RN(
n6059), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1591), .CK(clk), .RN(
n6059), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1592), .CK(clk), .RN(
n6059), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1594), .CK(clk), .RN(
n6059), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1649), .CK(clk),
.RN(n6062), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n5977),
.Q(FPADDSUB_DMP_EXP_EWSW[26]), .QN(n5835) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1464), .CK(clk), .RN(n5977),
.Q(FPADDSUB_DMP_EXP_EWSW[24]), .QN(n5833) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1769), .CK(clk), .RN(n6044), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2057), .CK(clk), .RN(n6026), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2069), .CK(clk), .RN(n6028), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2051), .CK(clk), .RN(n6029), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2066), .CK(clk), .RN(n6030), .Q(
FPSENCOS_d_ff_Xn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2063), .CK(clk), .RN(n6008), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2036), .CK(clk), .RN(n6010), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2042), .CK(clk), .RN(n6011), .Q(
FPSENCOS_d_ff_Xn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2030), .CK(clk), .RN(n6012), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2024), .CK(clk), .RN(n6020), .Q(
FPSENCOS_d_ff_Xn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2033), .CK(clk), .RN(n4004), .Q(
FPSENCOS_d_ff_Xn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2054), .CK(clk), .RN(n6016), .Q(
FPSENCOS_d_ff_Xn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2021), .CK(clk), .RN(n6017), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2012), .CK(clk), .RN(n4005), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2015), .CK(clk), .RN(n6019), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2045), .CK(clk), .RN(n6027), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2072), .CK(clk), .RN(n6028), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2039), .CK(clk), .RN(n6012), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2048), .CK(clk), .RN(n6013), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2060), .CK(clk), .RN(n6017), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2009), .CK(clk), .RN(n6037), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2018), .CK(clk), .RN(n6040), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2027), .CK(clk), .RN(n6041), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2006), .CK(clk), .RN(n6042), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1887), .CK(clk), .RN(
n6011), .QN(n2482) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1879), .CK(clk), .RN(
n6012), .QN(n2481) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1873), .CK(clk), .RN(
n6018), .QN(n2476) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1867), .CK(clk), .RN(
n6014), .QN(n2470) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2058), .CK(clk), .RN(n6026), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2046), .CK(clk), .RN(n6027), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2070), .CK(clk), .RN(n6028), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2073), .CK(clk), .RN(n6029), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2052), .CK(clk), .RN(n6030), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2067), .CK(clk), .RN(n6008), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2064), .CK(clk), .RN(n6009), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2037), .CK(clk), .RN(n6010), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2040), .CK(clk), .RN(n6013), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2049), .CK(clk), .RN(n4008), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2025), .CK(clk), .RN(n6052), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2034), .CK(clk), .RN(n4007), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2055), .CK(clk), .RN(n6016), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2061), .CK(clk), .RN(n6017), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2016), .CK(clk), .RN(n6019), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2010), .CK(clk), .RN(n6040), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2019), .CK(clk), .RN(n6041), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2028), .CK(clk), .RN(n6041), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2007), .CK(clk), .RN(n6042), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1770), .CK(clk), .RN(n6044), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1773), .CK(clk), .RN(n6045), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1776), .CK(clk), .RN(n6046), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1782), .CK(clk), .RN(n6047), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1197), .CK(clk), .RN(
n5999), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n5915) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1201), .CK(clk), .RN(
n5998), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n5917) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1198), .CK(clk), .RN(
n5999), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n5926) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1438), .CK(clk), .RN(
n6006), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1423), .CK(clk), .RN(
n6007), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1433), .CK(clk), .RN(
n6006), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1443), .CK(clk), .RN(
n6006), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1453), .CK(clk), .RN(
n6005), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1861), .CK(clk), .RN(
n6048), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n2252) );
DFFSX1TS R_3 ( .D(n5966), .CK(clk), .SN(n6038), .Q(n6074) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1936), .CK(clk), .RN(
n5976), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n2513) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1913), .CK(clk), .RN(
n5968), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n2505) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1728), .CK(clk), .RN(
n5974), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_1_ ( .D(n1530),
.CK(clk), .RN(n6022), .Q(FPMULT_P_Sgf[1]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_13_ ( .D(n1542),
.CK(clk), .RN(n6021), .Q(FPMULT_P_Sgf[13]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_20_ ( .D(n1549),
.CK(clk), .RN(n6022), .Q(FPMULT_P_Sgf[20]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1706), .CK(clk), .RN(n6024),
.Q(cordic_result[20]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1709), .CK(clk), .RN(n6024),
.Q(cordic_result[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1712), .CK(clk), .RN(n6025),
.Q(cordic_result[14]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1716), .CK(clk), .RN(n6025),
.Q(cordic_result[10]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1696), .CK(clk), .RN(n6042),
.Q(cordic_result[30]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1697), .CK(clk), .RN(n6043),
.Q(cordic_result[29]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1699), .CK(clk), .RN(n6045),
.Q(cordic_result[27]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1700), .CK(clk), .RN(n6045),
.Q(cordic_result[26]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1701), .CK(clk), .RN(n6046),
.Q(cordic_result[25]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1702), .CK(clk), .RN(n6047),
.Q(cordic_result[24]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1703), .CK(clk), .RN(n6047),
.Q(cordic_result[23]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1695), .CK(clk), .RN(n6025),
.Q(cordic_result[31]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n6036), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n6038), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n6038), .Q(
dataA[29]) );
DFFRX1TS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n6037), .Q(
dataB[25]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1790), .CK(clk), .RN(n5970),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1789), .CK(clk), .RN(n5970),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1788), .CK(clk), .RN(n5969),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2115), .CK(clk), .RN(n6032), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2116), .CK(clk), .RN(n6032), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2123), .CK(clk), .RN(n6033), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2129), .CK(clk), .RN(n6034), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2132), .CK(clk), .RN(n6034), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2117), .CK(clk), .RN(n6033), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2128), .CK(clk), .RN(n6034), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1415), .CK(clk), .RN(n5981),
.Q(FPADDSUB_DmP_EXP_EWSW[25]), .QN(n5836) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1787), .CK(clk), .RN(n5992),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2114), .CK(clk), .RN(n6032), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2131), .CK(clk), .RN(n6034), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2126), .CK(clk), .RN(n6033), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRX1TS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n6036), .Q(
dataB[27]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1620), .CK(clk), .RN(
n6063), .Q(FPMULT_Add_result[0]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n1638), .CK(clk),
.RN(n6061), .Q(FPMULT_Op_MY[12]), .QN(n2443) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1839), .CK(clk), .RN(
n5971), .Q(FPADDSUB_intDY_EWSW[4]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1834), .CK(clk), .RN(
n5976), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1815), .CK(clk), .RN(
n5969), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1821), .CK(clk), .RN(
n5969), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n2491) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1823), .CK(clk), .RN(
n5970), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n2472) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1828), .CK(clk), .RN(
n5969), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n2478) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1826), .CK(clk), .RN(
n5971), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n2485) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1835), .CK(clk), .RN(
n5972), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n2479) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1840), .CK(clk), .RN(
n5974), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n2464) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1819), .CK(clk), .RN(
n5968), .Q(FPADDSUB_intDY_EWSW[24]), .QN(n5897) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1817), .CK(clk), .RN(
n5968), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n5905) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1917), .CK(clk), .RN(
n5967), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n2226) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1938), .CK(clk), .RN(
n5974), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n2466) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1914), .CK(clk), .RN(
n5968), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n2262) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1919), .CK(clk), .RN(
n5969), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n2225) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1922), .CK(clk), .RN(
n5970), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n2260) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1814), .CK(clk), .RN(
n5969), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n2489) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1928), .CK(clk), .RN(
n5972), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n2492) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1940), .CK(clk), .RN(
n5976), .Q(FPADDSUB_intDX_EWSW[1]), .QN(n2263) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1939), .CK(clk), .RN(
n5975), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n2261) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1463), .CK(clk), .RN(n5977),
.Q(FPADDSUB_DMP_EXP_EWSW[25]), .QN(n2460) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1506), .CK(
clk), .RN(n6056), .Q(FPMULT_Sgf_normalized_result[1]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2077), .CK(clk), .RN(
n5974), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n5854) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1811), .CK(clk), .RN(n5975), .Q(FPADDSUB_Data_array_SWR[24]), .QN(n5870) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1925), .CK(clk), .RN(
n5972), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n2507) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1931), .CK(clk), .RN(
n5973), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n2484) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(clk), .RN(n5967), .Q(ready_add_subt), .QN(n5823) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1688), .CK(clk),
.RN(n6068), .Q(FPMULT_Op_MX[30]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1937), .CK(clk), .RN(
n5971), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n2514) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1686), .CK(clk),
.RN(n6068), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n6069), .CK(clk),
.RN(n6035), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2191), .CK(
clk), .RN(n5967), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n5826) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2149), .CK(
clk), .RN(n5967), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n5871) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1684), .CK(clk),
.RN(n6068), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1681), .CK(clk),
.RN(n6068), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1193), .CK(clk), .RN(
n5999), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n5924) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1192), .CK(clk), .RN(
n5999), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n5923) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1186), .CK(clk), .RN(
n6000), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n5920) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1194), .CK(clk), .RN(
n5999), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n5936) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2003), .CK(clk), .RN(
n6027), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1190), .CK(clk), .RN(
n5999), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n5922) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1772), .CK(clk), .RN(n6045), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1943), .CK(clk), .RN(
n6009), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1781), .CK(clk), .RN(n6047), .Q(
FPSENCOS_d_ff_Xn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1775), .CK(clk), .RN(n6046), .Q(
FPSENCOS_d_ff_Xn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2031), .CK(clk), .RN(n6012), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2043), .CK(clk), .RN(n6011), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2013), .CK(clk), .RN(n6052), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2022), .CK(clk), .RN(n6014), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n5981), .QN(n5875) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n4012), .QN(n5883) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n2411), .QN(n5882) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n4006), .QN(n5885) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n5982), .QN(n5884) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n5984), .QN(n5887) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n5984), .QN(n5886) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1363), .CK(clk), .RN(
n5985), .QN(n5889) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n5984), .QN(n5888) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n5988), .QN(n5895) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n5987), .QN(n5894) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1857), .CK(clk), .RN(
n6045), .Q(FPSENCOS_d_ff2_Y[27]), .QN(n5909) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1416), .CK(clk), .RN(n5983),
.Q(FPADDSUB_DmP_EXP_EWSW[24]), .QN(n2268) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2079), .CK(clk), .RN(
n5974), .Q(FPADDSUB_bit_shift_SHT2), .QN(n2267) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1735), .CK(clk), .RN(
n6044), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1734), .CK(clk), .RN(
n6043), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1738), .CK(clk), .RN(
n6046), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1737), .CK(clk), .RN(
n6045), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1740), .CK(clk), .RN(
n6047), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1739), .CK(clk), .RN(
n6047), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_8_ ( .D(n1537),
.CK(clk), .RN(n6023), .Q(FPMULT_P_Sgf[8]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1741), .CK(clk), .RN(
n6048), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1204), .CK(clk), .RN(
n5998), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n5838) );
DFFRX1TS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1853), .CK(clk), .RN(n6032),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_6_ ( .D(n1535),
.CK(clk), .RN(n6023), .Q(FPMULT_P_Sgf[6]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2142), .CK(clk), .RN(
n6007), .Q(FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n5953) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n6039), .Q(
dataA[23]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2133), .CK(clk), .RN(n6034), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1683), .CK(clk),
.RN(n6068), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1619), .CK(clk), .RN(
n6063), .Q(FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1617), .CK(clk), .RN(
n6063), .Q(FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1612), .CK(clk), .RN(
n6064), .Q(FPMULT_Add_result[8]) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n6039), .Q(
dataA[27]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1611), .CK(clk), .RN(
n6064), .Q(FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1610), .CK(clk),
.RN(n6064), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1609), .CK(clk),
.RN(n6064), .Q(FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1608), .CK(clk),
.RN(n6064), .Q(FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1607), .CK(clk),
.RN(n6064), .Q(FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1606), .CK(clk),
.RN(n6064), .Q(FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1605), .CK(clk),
.RN(n6064), .Q(FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1604), .CK(clk),
.RN(n6065), .Q(FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1603), .CK(clk),
.RN(n6065), .Q(FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1602), .CK(clk),
.RN(n6065), .Q(FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1601), .CK(clk),
.RN(n6065), .Q(FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1600), .CK(clk),
.RN(n6065), .Q(FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1599), .CK(clk),
.RN(n6065), .Q(FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1598), .CK(clk),
.RN(n6065), .Q(FPMULT_Add_result[22]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1597), .CK(clk),
.RN(n6063), .Q(FPMULT_Add_result[23]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n6035), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1414), .CK(clk), .RN(n5981),
.Q(FPADDSUB_DmP_EXP_EWSW[26]), .QN(n2463) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1182), .CK(clk), .RN(
n6000), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n5918) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1184), .CK(clk), .RN(
n6000), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n5919) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1188), .CK(clk), .RN(
n6000), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n5921) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1195), .CK(clk), .RN(
n5999), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n5914) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1199), .CK(clk), .RN(
n5998), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n5916) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1202), .CK(clk), .RN(
n5998), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n5928) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1651), .CK(clk),
.RN(n6062), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1655), .CK(clk),
.RN(n6063), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1588), .CK(clk), .RN(
n6059), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1590), .CK(clk), .RN(
n6059), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1593), .CK(clk), .RN(
n6059), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1652), .CK(clk),
.RN(n6062), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1461), .CK(clk), .RN(n5980),
.Q(FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1650), .CK(clk),
.RN(n6062), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1654), .CK(clk),
.RN(n6062), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n6038),
.Q(operation_reg[1]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2001), .CK(clk), .RN(
n6030), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1981), .CK(clk), .RN(
n6010), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1985), .CK(clk), .RN(
n6011), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1993), .CK(clk), .RN(
n6016), .Q(FPSENCOS_d_ff2_X[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1987), .CK(clk), .RN(
n6027), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2005), .CK(clk), .RN(
n6028), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1989), .CK(clk), .RN(
n6013), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1997), .CK(clk), .RN(
n6016), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1963), .CK(clk), .RN(
n6045), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1845), .CK(clk), .RN(
n6009), .QN(n2462) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1995), .CK(clk), .RN(
n6026), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1991), .CK(clk), .RN(
n6029), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n1999), .CK(clk), .RN(
n6008), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1977), .CK(clk), .RN(
n6012), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1973), .CK(clk), .RN(
n4004), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1979), .CK(clk), .RN(
n6020), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1971), .CK(clk), .RN(
n6017), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1967), .CK(clk), .RN(
n6019), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1965), .CK(clk), .RN(
n6015), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1961), .CK(clk), .RN(
n6042), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1975), .CK(clk), .RN(
n6041), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1969), .CK(clk), .RN(
n6040), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1983), .CK(clk), .RN(
n6012), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1191), .CK(clk), .RN(
n5999), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n5935) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1189), .CK(clk), .RN(
n6000), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n5934) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1187), .CK(clk), .RN(
n6000), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n5933) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1185), .CK(clk), .RN(
n6000), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n5932) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1183), .CK(clk), .RN(
n6000), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n5931) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1181), .CK(clk), .RN(
n6000), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n5930) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1778), .CK(clk), .RN(n6046), .Q(
FPSENCOS_d_ff_Xn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1766), .CK(clk), .RN(n6043), .Q(
FPSENCOS_d_ff_Xn[29]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1893), .CK(clk), .RN(
n6030), .QN(n2471) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1907), .CK(clk), .RN(
n6029), .QN(n2473) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_45_ ( .D(n1574),
.CK(clk), .RN(n4007), .Q(FPMULT_P_Sgf[45]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1784), .CK(clk), .RN(n6048), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1729), .CK(clk), .RN(n6043), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_44_ ( .D(n1573),
.CK(clk), .RN(n4005), .Q(FPMULT_P_Sgf[44]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_43_ ( .D(n1572),
.CK(clk), .RN(n6018), .Q(FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_42_ ( .D(n1571),
.CK(clk), .RN(n6014), .Q(FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_41_ ( .D(n1570),
.CK(clk), .RN(n6039), .Q(FPMULT_P_Sgf[41]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_40_ ( .D(n1569),
.CK(clk), .RN(n6015), .Q(FPMULT_P_Sgf[40]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_39_ ( .D(n1568),
.CK(clk), .RN(n4005), .Q(FPMULT_P_Sgf[39]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_38_ ( .D(n1567),
.CK(clk), .RN(n6015), .Q(FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_37_ ( .D(n1566),
.CK(clk), .RN(n4008), .Q(FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_36_ ( .D(n1565),
.CK(clk), .RN(n6052), .Q(FPMULT_P_Sgf[36]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_35_ ( .D(n1564),
.CK(clk), .RN(n6020), .Q(FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_34_ ( .D(n1563),
.CK(clk), .RN(n4007), .Q(FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_33_ ( .D(n1562),
.CK(clk), .RN(n4004), .Q(FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_32_ ( .D(n1561),
.CK(clk), .RN(n4005), .Q(FPMULT_P_Sgf[32]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_31_ ( .D(n1560),
.CK(clk), .RN(n6018), .Q(FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_30_ ( .D(n1559),
.CK(clk), .RN(n6014), .Q(FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_29_ ( .D(n1558),
.CK(clk), .RN(n6052), .Q(FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_28_ ( .D(n1557),
.CK(clk), .RN(n6015), .Q(FPMULT_P_Sgf[28]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_27_ ( .D(n1556),
.CK(clk), .RN(n6021), .Q(FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_26_ ( .D(n1555),
.CK(clk), .RN(n6021), .Q(FPMULT_P_Sgf[26]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_25_ ( .D(n1554),
.CK(clk), .RN(n6021), .Q(FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_24_ ( .D(n1553),
.CK(clk), .RN(n6021), .Q(FPMULT_P_Sgf[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1785), .CK(clk), .RN(n6048), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1779), .CK(clk), .RN(n6046), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1767), .CK(clk), .RN(n6044), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1730), .CK(clk), .RN(n6043), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1732), .CK(clk), .RN(n6010), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n5988), .QN(n5896) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n5986), .QN(n5892) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n5986), .QN(n5890) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n5978), .QN(n5881) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n5987), .QN(n5893) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n5986), .QN(n5891) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n5979), .QN(n5880) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n4011), .QN(n5879) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n5980), .QN(n5878) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n4009), .QN(n5877) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n5981), .QN(n5876) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1855), .CK(clk), .RN(
n6043), .Q(FPSENCOS_d_ff2_Y[29]), .QN(n5908) );
DFFRX4TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2137), .CK(clk), .RN(n6035),
.Q(FPSENCOS_cont_var_out[0]), .QN(n5856) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_19_ ( .D(n1548),
.CK(clk), .RN(n6022), .Q(FPMULT_P_Sgf[19]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_15_ ( .D(n1544),
.CK(clk), .RN(n6022), .Q(FPMULT_P_Sgf[15]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_3_ ( .D(n1532),
.CK(clk), .RN(n6022), .Q(FPMULT_P_Sgf[3]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_18_ ( .D(n1547),
.CK(clk), .RN(n6022), .Q(FPMULT_P_Sgf[18]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_17_ ( .D(n1546),
.CK(clk), .RN(n6021), .Q(FPMULT_P_Sgf[17]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_5_ ( .D(n1534),
.CK(clk), .RN(n6022), .Q(FPMULT_P_Sgf[5]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n6036), .Q(
dataB[28]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_21_ ( .D(n1550),
.CK(clk), .RN(n6022), .Q(FPMULT_P_Sgf[21]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_16_ ( .D(n1545),
.CK(clk), .RN(n6022), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_4_ ( .D(n1533),
.CK(clk), .RN(n6022), .Q(FPMULT_P_Sgf[4]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1731), .CK(clk), .RN(
n5974), .Q(FPADDSUB_intAS) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_7_ ( .D(n1536),
.CK(clk), .RN(n6023), .Q(FPMULT_P_Sgf[7]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1413), .CK(clk), .RN(n5981),
.Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n6037), .Q(
dataB[23]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_11_ ( .D(n1540),
.CK(clk), .RN(n6024), .Q(FPMULT_P_Sgf[11]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n6039), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n6038), .Q(
dataA[28]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n6036), .Q(
dataB[26]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n6037), .Q(
dataB[24]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1924), .CK(clk), .RN(
n5971), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n2270) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1920), .CK(clk), .RN(
n5970), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n2269) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1813), .CK(clk), .RN(
n5969), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n2256) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2075), .CK(clk), .RN(
n5974), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2254) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n1639), .CK(clk),
.RN(n6061), .Q(FPMULT_Op_MY[13]), .QN(n2248) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1677), .CK(clk),
.RN(n6067), .Q(FPMULT_Op_MX[19]), .QN(n2245) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1666), .CK(clk),
.RN(n6066), .Q(FPMULT_Op_MX[8]), .QN(n2496) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n1641), .CK(clk),
.RN(n6061), .Q(FPMULT_Op_MY[15]), .QN(n2195) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1645), .CK(clk),
.RN(n6062), .Q(n2205), .QN(n2233) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1205), .CK(clk), .RN(
n5998), .QN(n5945) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2146), .CK(clk), .RN(
n5967), .Q(n6077), .QN(n5962) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1915), .CK(clk), .RN(
n5968), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n2227) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1667), .CK(clk),
.RN(n6066), .Q(FPMULT_Op_MX[9]), .QN(n2502) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1675), .CK(clk),
.RN(n6067), .Q(FPMULT_Op_MX[17]), .QN(n2246) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2141), .CK(clk), .RN(n6036),
.Q(FPSENCOS_cont_iter_out[0]), .QN(n2208) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1668), .CK(clk),
.RN(n6066), .Q(n2214), .QN(n2519) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1663), .CK(clk),
.RN(n6066), .Q(n2212), .QN(n2516) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n6051), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .QN(n5846) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1333), .CK(clk), .RN(
n5996), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n5860) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1332), .CK(clk), .RN(
n5996), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_0_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N0), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_1_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[1]) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_2_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[2]) );
DFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_14_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[14]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_18_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[18]) );
DFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_2_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_14_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_15_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_17_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_18_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_3_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[3]) );
DFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_4_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[4]) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_6_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[6]) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_8_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[8]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_16_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_17_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_18_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]) );
DFFSX1TS R_11 ( .D(n5964), .CK(clk), .SN(n4005), .Q(n6073) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_20_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[20]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_22_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[22]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_21_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[21]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_19_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[19]) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1528), .CK(clk), .RN(n6058), .Q(
FPMULT_FSM_selector_C), .QN(n5873) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n6035), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n5859) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_15_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1314), .CK(clk), .RN(
n5997), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1203), .CK(clk), .RN(
n5998), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n5929) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1341), .CK(clk), .RN(
n5994), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n6076) );
DFFSX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n6071), .CK(clk), .SN(n6059), .Q(n5843),
.QN(FPMULT_FSM_selector_B[0]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1344), .CK(clk), .RN(
n5994), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n5820) );
DFFSX1TS R_4 ( .D(n5965), .CK(clk), .SN(n6018), .Q(n6075) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1836), .CK(clk), .RN(
n5975), .Q(FPADDSUB_intDY_EWSW[7]), .QN(n5828) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1801), .CK(clk), .RN(n5972), .Q(FPADDSUB_Data_array_SWR[14]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1802), .CK(clk), .RN(n5972), .Q(FPADDSUB_Data_array_SWR[15]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1807), .CK(clk), .RN(n5970), .Q(FPADDSUB_Data_array_SWR[20]), .QN(n5831) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1796), .CK(clk), .RN(n5973),
.Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1798), .CK(clk), .RN(n5973), .Q(FPADDSUB_Data_array_SWR[11]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1797), .CK(clk), .RN(n5976), .Q(FPADDSUB_Data_array_SWR[10]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1795), .CK(clk), .RN(n5976),
.Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1791), .CK(clk), .RN(n5977),
.Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1792), .CK(clk), .RN(n5969),
.Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1680), .CK(clk),
.RN(n6068), .Q(FPMULT_Op_MX[22]), .QN(n2229) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n1673), .CK(clk),
.RN(n6067), .Q(FPMULT_Op_MX[15]), .QN(n2237) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1665), .CK(clk),
.RN(n6066), .Q(FPMULT_Op_MX[7]), .QN(n2498) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1646), .CK(clk),
.RN(n6062), .Q(FPMULT_Op_MY[20]), .QN(n2528) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1674), .CK(clk),
.RN(n6067), .Q(FPMULT_Op_MX[16]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_8_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1628), .CK(clk),
.RN(n6060), .Q(FPMULT_Op_MY[2]) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1350), .CK(clk), .RN(
n5997), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n2211) );
MDFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_0_ ( .D0(
n2510), .D1(1'b1), .S0(n2230), .CK(clk), .Q(n5815) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1647), .CK(clk),
.RN(n6062), .Q(FPMULT_Op_MY[21]), .QN(n2194) );
DFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_1_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[1]) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n6034),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n5872) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_10_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_13_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_5_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[5]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_7_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_7_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[7]) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_9_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[9]) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_11_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[11]) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_13_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[13]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_12_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_11_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_4_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[4]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_9_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_5_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[5]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_10_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[10]) );
DFFHQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_3_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_0_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N0), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_10_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_12_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[12]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_6_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[6]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_14_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[14]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_15_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[15]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_4_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_6_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_7_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_9_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_5_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_11_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_12_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_13_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_1_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_3_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_8_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_17_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[17]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_16_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[16]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1321), .CK(clk), .RN(
n5995), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1319), .CK(clk), .RN(
n5995), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n5862) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1320), .CK(clk), .RN(
n5995), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1336), .CK(clk), .RN(
n5995), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]), .QN(n5903) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1636), .CK(clk),
.RN(n6061), .Q(FPMULT_Op_MY[10]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1627), .CK(clk),
.RN(n6060), .Q(FPMULT_Op_MY[1]), .QN(n2249) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1337), .CK(clk), .RN(
n5994), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n5901) );
CMPR32X2TS DP_OP_26J16_124_9022_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n2276), .C(DP_OP_26J16_124_9022_n18), .CO(DP_OP_26J16_124_9022_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J16_124_9022_U8 ( .A(DP_OP_26J16_124_9022_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J16_124_9022_n8), .CO(
DP_OP_26J16_124_9022_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J16_124_9022_U7 ( .A(DP_OP_26J16_124_9022_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J16_124_9022_n7), .CO(
DP_OP_26J16_124_9022_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR42X1TS mult_x_254_U220 ( .A(mult_x_254_n350), .B(mult_x_254_n326), .C(
mult_x_254_n338), .D(mult_x_254_n261), .ICI(mult_x_254_n262), .S(
mult_x_254_n259), .ICO(mult_x_254_n257), .CO(mult_x_254_n258) );
CMPR42X1TS mult_x_219_U216 ( .A(mult_x_219_n329), .B(mult_x_219_n317), .C(
mult_x_219_n258), .D(mult_x_219_n255), .ICI(mult_x_219_n254), .S(
mult_x_219_n252), .ICO(mult_x_219_n250), .CO(mult_x_219_n251) );
CMPR32X2TS DP_OP_26J16_124_9022_U6 ( .A(DP_OP_26J16_124_9022_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J16_124_9022_n6), .CO(
DP_OP_26J16_124_9022_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2076), .CK(clk), .RN(
n5974), .Q(FPADDSUB_shift_value_SHT2_EWR[3]) );
CMPR32X2TS DP_OP_234J16_127_8543_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n2418),
.C(DP_OP_234J16_127_8543_n22), .CO(DP_OP_234J16_127_8543_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_26J16_124_9022_U5 ( .A(DP_OP_26J16_124_9022_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J16_124_9022_n5), .CO(
DP_OP_26J16_124_9022_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR42X1TS mult_x_254_U188 ( .A(mult_x_254_n291), .B(mult_x_254_n185), .C(
mult_x_254_n179), .D(mult_x_254_n186), .ICI(mult_x_254_n182), .S(
mult_x_254_n177), .ICO(mult_x_254_n175), .CO(mult_x_254_n176) );
CMPR32X2TS DP_OP_26J16_124_9022_U4 ( .A(n2211), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J16_124_9022_n4), .CO(
DP_OP_26J16_124_9022_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J16_124_9022_U3 ( .A(n2211), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J16_124_9022_n3), .CO(
DP_OP_26J16_124_9022_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J16_124_9022_U2 ( .A(n2211), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J16_124_9022_n2), .CO(
DP_OP_26J16_124_9022_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS intadd_22_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n5844), .C(
intadd_22_CI), .CO(intadd_22_n3), .S(intadd_22_SUM_0_) );
CMPR32X2TS intadd_22_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n2301), .C(
intadd_22_n3), .CO(intadd_22_n2), .S(intadd_22_SUM_1_) );
CMPR32X2TS intadd_22_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n5821), .C(
intadd_22_n2), .CO(intadd_22_n1), .S(intadd_22_SUM_2_) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_46_ ( .D(n1575),
.CK(clk), .RN(n4004), .Q(FPMULT_P_Sgf[46]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2078), .CK(clk), .RN(
n5999), .Q(FPADDSUB_left_right_SHT2), .QN(n2222) );
INVX4TS U2217 ( .A(n5800), .Y(n2405) );
AOI222X1TS U2218 ( .A0(n4240), .A1(cordic_result[12]), .B0(n4302), .B1(
FPSENCOS_d_ff_Yn[12]), .C0(n4239), .C1(FPSENCOS_d_ff_Xn[12]), .Y(n4303) );
AOI222X1TS U2219 ( .A0(n5527), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n5556), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n4261), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n4274) );
AOI222X1TS U2220 ( .A0(n4311), .A1(cordic_result[22]), .B0(n4310), .B1(
FPSENCOS_d_ff_Yn[22]), .C0(n4309), .C1(FPSENCOS_d_ff_Xn[22]), .Y(n4307) );
AOI222X1TS U2221 ( .A0(n4311), .A1(cordic_result[28]), .B0(n4310), .B1(
FPSENCOS_d_ff_Yn[28]), .C0(n4309), .C1(FPSENCOS_d_ff_Xn[28]), .Y(n4295) );
AOI222X1TS U2222 ( .A0(n4255), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n4267), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n4257), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n4249)
);
AOI222X1TS U2223 ( .A0(n4255), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4267), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n4257), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n4256)
);
AOI222X1TS U2224 ( .A0(n4255), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n4267), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n4257), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n4250)
);
AOI222X1TS U2225 ( .A0(n4255), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n2406), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n4231) );
AOI222X1TS U2226 ( .A0(n4255), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n2406), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n4232) );
AOI222X1TS U2227 ( .A0(n4315), .A1(cordic_result[11]), .B0(n4314), .B1(
FPSENCOS_d_ff_Yn[11]), .C0(n4276), .C1(FPSENCOS_d_ff_Xn[11]), .Y(n4293) );
AOI222X1TS U2228 ( .A0(n5537), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n2406), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n4257), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n4258)
);
AOI222X1TS U2229 ( .A0(n5537), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n2406), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n4257), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n4254)
);
AOI222X1TS U2230 ( .A0(n4255), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n2406), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n4257), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n4251)
);
AOI222X1TS U2231 ( .A0(n4255), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n2406), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n4257), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n4252)
);
AOI222X1TS U2232 ( .A0(n4255), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n2406), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n4257), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n4253)
);
AOI222X1TS U2233 ( .A0(n4297), .A1(cordic_result[21]), .B0(n4302), .B1(
FPSENCOS_d_ff_Yn[21]), .C0(n4309), .C1(FPSENCOS_d_ff_Xn[21]), .Y(n4278) );
AOI222X1TS U2234 ( .A0(n4297), .A1(cordic_result[15]), .B0(n4302), .B1(
FPSENCOS_d_ff_Yn[15]), .C0(n4276), .C1(FPSENCOS_d_ff_Xn[15]), .Y(n4283) );
AOI222X1TS U2235 ( .A0(n4297), .A1(cordic_result[18]), .B0(n4302), .B1(
FPSENCOS_d_ff_Yn[18]), .C0(n4276), .C1(FPSENCOS_d_ff_Xn[18]), .Y(n4287) );
AOI222X1TS U2236 ( .A0(n4297), .A1(cordic_result[19]), .B0(n4302), .B1(
FPSENCOS_d_ff_Yn[19]), .C0(n4276), .C1(FPSENCOS_d_ff_Xn[19]), .Y(n4279) );
AOI222X1TS U2237 ( .A0(n4297), .A1(cordic_result[13]), .B0(n4302), .B1(
FPSENCOS_d_ff_Yn[13]), .C0(n4276), .C1(FPSENCOS_d_ff_Xn[13]), .Y(n4288) );
AOI222X1TS U2238 ( .A0(n4297), .A1(cordic_result[16]), .B0(n4302), .B1(
FPSENCOS_d_ff_Yn[16]), .C0(n4276), .C1(FPSENCOS_d_ff_Xn[16]), .Y(n4281) );
AOI222X1TS U2239 ( .A0(n5537), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n5570), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n4257), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n4248)
);
AOI222X1TS U2240 ( .A0(n5537), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n4257), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n5570), .Y(n4247)
);
AOI222X1TS U2241 ( .A0(n4272), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n4271), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n4224) );
AOI222X1TS U2242 ( .A0(n4272), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n4271), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n4246), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n4217) );
AOI222X1TS U2243 ( .A0(n4272), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n4271), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n4261), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n4270) );
AOI222X1TS U2244 ( .A0(n4272), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n4271), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n4246), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n4218) );
AOI222X1TS U2245 ( .A0(n4272), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n4271), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n4246), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n4273) );
AOI222X1TS U2246 ( .A0(n4272), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n4271), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n4220) );
AOI222X1TS U2247 ( .A0(n4272), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n4271), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n4222) );
AOI222X1TS U2248 ( .A0(n4272), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n4271), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n4221) );
AOI222X1TS U2249 ( .A0(n4272), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n4271), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n4219) );
AOI222X1TS U2250 ( .A0(n4255), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n4271), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n4223) );
AOI222X1TS U2251 ( .A0(n5527), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n5523), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n4261), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n4262) );
INVX2TS U2252 ( .A(n4275), .Y(n4313) );
CLKINVX6TS U2253 ( .A(n2240), .Y(n2295) );
INVX3TS U2254 ( .A(n2240), .Y(n2401) );
CLKBUFX2TS U2255 ( .A(n5569), .Y(n5552) );
INVX2TS U2256 ( .A(n2918), .Y(n2943) );
INVX2TS U2257 ( .A(n3145), .Y(n3170) );
NOR2X1TS U2258 ( .A(n3599), .B(n3603), .Y(n2905) );
BUFX3TS U2259 ( .A(n5513), .Y(n5511) );
CLKBUFX2TS U2260 ( .A(n4530), .Y(n4510) );
BUFX3TS U2261 ( .A(n4530), .Y(n4523) );
CLKBUFX2TS U2262 ( .A(n5692), .Y(n5698) );
OAI21X1TS U2263 ( .A0(n4813), .A1(n4809), .B0(n4810), .Y(n4802) );
OAI21X1TS U2264 ( .A0(n2632), .A1(n2696), .B0(n2699), .Y(n2633) );
BUFX3TS U2265 ( .A(n4108), .Y(n4322) );
NAND2X1TS U2266 ( .A(n3589), .B(n2232), .Y(n3599) );
INVX2TS U2267 ( .A(n2944), .Y(n2967) );
NOR2X1TS U2268 ( .A(n3588), .B(n3575), .Y(n3577) );
INVX2TS U2269 ( .A(n5667), .Y(n5516) );
INVX2TS U2270 ( .A(n5658), .Y(n5515) );
AOI21X2TS U2271 ( .A0(n4837), .A1(n4800), .B0(n4799), .Y(n4813) );
NOR2X4TS U2272 ( .A(n5477), .B(n5784), .Y(n4530) );
NOR2X1TS U2273 ( .A(n2920), .B(n2921), .Y(n2855) );
BUFX3TS U2274 ( .A(n4240), .Y(n4315) );
CLKINVX6TS U2275 ( .A(n2407), .Y(n5556) );
BUFX3TS U2276 ( .A(n5507), .Y(n5513) );
BUFX3TS U2277 ( .A(n5579), .Y(n5525) );
INVX2TS U2278 ( .A(n5700), .Y(n5702) );
NOR2X6TS U2279 ( .A(n5640), .B(n4688), .Y(n4494) );
NAND2X2TS U2280 ( .A(n2804), .B(n2803), .Y(n5784) );
NAND2X2TS U2281 ( .A(DP_OP_454J16_123_2743_n279), .B(
DP_OP_454J16_123_2743_n284), .Y(n3640) );
NOR2X2TS U2282 ( .A(DP_OP_454J16_123_2743_n279), .B(
DP_OP_454J16_123_2743_n284), .Y(n3332) );
AO21XLTS U2283 ( .A0(n2788), .A1(n2787), .B0(n2786), .Y(n2804) );
BUFX3TS U2284 ( .A(n4240), .Y(n4311) );
BUFX3TS U2285 ( .A(n4321), .Y(n4444) );
CLKBUFX2TS U2286 ( .A(n5693), .Y(n5700) );
INVX2TS U2287 ( .A(n2305), .Y(n5715) );
AOI21X2TS U2288 ( .A0(n3154), .A1(n3158), .B0(n2683), .Y(n3146) );
NAND2X1TS U2289 ( .A(DP_OP_454J16_123_2743_n285), .B(
DP_OP_454J16_123_2743_n292), .Y(n2698) );
NOR2X4TS U2290 ( .A(DP_OP_454J16_123_2743_n300), .B(
DP_OP_454J16_123_2743_n309), .Y(n2875) );
NAND2X2TS U2291 ( .A(DP_OP_454J16_123_2743_n293), .B(
DP_OP_454J16_123_2743_n299), .Y(n2699) );
NOR2X2TS U2292 ( .A(DP_OP_454J16_123_2743_n327), .B(
DP_OP_454J16_123_2743_n334), .Y(n3521) );
CLKBUFX2TS U2293 ( .A(n5953), .Y(n5725) );
NOR2X1TS U2294 ( .A(n3196), .B(n3289), .Y(n2678) );
NOR2X1TS U2295 ( .A(n2969), .B(n3070), .Y(n2848) );
NOR2X1TS U2296 ( .A(n3179), .B(n3174), .Y(n2680) );
BUFX3TS U2297 ( .A(n5526), .Y(n5579) );
NOR2X2TS U2298 ( .A(n2939), .B(n2934), .Y(n2926) );
NAND2X1TS U2299 ( .A(mult_x_254_n233), .B(mult_x_254_n240), .Y(n3071) );
NOR2X2TS U2300 ( .A(mult_x_254_n206), .B(mult_x_254_n215), .Y(n2959) );
NOR2X2TS U2301 ( .A(mult_x_219_n182), .B(mult_x_219_n187), .Y(n3166) );
NOR2X1TS U2302 ( .A(n5482), .B(n4091), .Y(n4237) );
INVX2TS U2303 ( .A(n3664), .Y(n5526) );
INVX2TS U2304 ( .A(n5788), .Y(n2304) );
NAND3BX1TS U2305 ( .AN(n3663), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]),
.C(n3662), .Y(n3664) );
NOR2X1TS U2306 ( .A(n4695), .B(n5904), .Y(n4727) );
OAI21X2TS U2307 ( .A0(n3223), .A1(n3220), .B0(n3221), .Y(n3209) );
AOI211X1TS U2308 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n4148), .B0(n4488), .C0(n4127), .Y(n4478) );
OR2X2TS U2309 ( .A(DP_OP_454J16_123_2743_n365), .B(
DP_OP_454J16_123_2743_n361), .Y(n2526) );
BUFX6TS U2310 ( .A(n5569), .Y(n5586) );
AOI21X2TS U2311 ( .A0(n5259), .A1(n5255), .B0(n3692), .Y(n5229) );
INVX2TS U2312 ( .A(n2300), .Y(n4600) );
NAND4X1TS U2313 ( .A(n5844), .B(n2208), .C(n5821), .D(n2301), .Y(n4216) );
CMPR32X2TS U2314 ( .A(n3554), .B(n3553), .C(n3552), .CO(
DP_OP_454J16_123_2743_n268), .S(DP_OP_454J16_123_2743_n269) );
NAND2X1TS U2315 ( .A(n5826), .B(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.Y(n5465) );
BUFX6TS U2316 ( .A(n3699), .Y(n5569) );
INVX2TS U2317 ( .A(operation[1]), .Y(n5454) );
INVX2TS U2318 ( .A(operation[2]), .Y(n5463) );
XNOR2X1TS U2319 ( .A(n3559), .B(n2343), .Y(n3443) );
CMPR32X2TS U2320 ( .A(FPMULT_Op_MY[14]), .B(n2248), .C(n3242), .CO(
mult_x_219_n208), .S(mult_x_219_n209) );
CMPR42X1TS U2321 ( .A(DP_OP_454J16_123_2743_n436), .B(
DP_OP_454J16_123_2743_n289), .C(DP_OP_454J16_123_2743_n387), .D(
DP_OP_454J16_123_2743_n398), .ICI(DP_OP_454J16_123_2743_n423), .S(
DP_OP_454J16_123_2743_n282), .ICO(DP_OP_454J16_123_2743_n280), .CO(
DP_OP_454J16_123_2743_n281) );
NOR3X1TS U2322 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n5850),
.C(n4189), .Y(n3699) );
NOR2BX1TS U2323 ( .AN(n3661), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n4188) );
CMPR42X1TS U2324 ( .A(mult_x_254_n327), .B(mult_x_254_n339), .C(
mult_x_254_n351), .D(mult_x_254_n363), .ICI(mult_x_254_n267), .S(
mult_x_254_n264), .ICO(mult_x_254_n262), .CO(mult_x_254_n263) );
INVX4TS U2325 ( .A(n2236), .Y(n2318) );
ADDHXLTS U2326 ( .A(n3135), .B(n3134), .CO(mult_x_254_n260), .S(
mult_x_254_n261) );
ADDHXLTS U2327 ( .A(n3317), .B(n3316), .CO(mult_x_219_n258), .S(
mult_x_219_n259) );
NOR2X1TS U2328 ( .A(n2348), .B(n2501), .Y(mult_x_254_n194) );
NOR2X1TS U2329 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(n3663),
.Y(n3661) );
BUFX3TS U2330 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n5017) );
NOR2X1TS U2331 ( .A(n2571), .B(n2570), .Y(n3376) );
NAND2BX1TS U2332 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n3698),
.Y(n4189) );
NAND2X1TS U2333 ( .A(n4951), .B(n3918), .Y(n4898) );
OAI22X1TS U2334 ( .A0(n3433), .A1(n2422), .B0(n3551), .B1(n2314), .Y(n3552)
);
INVX2TS U2335 ( .A(n5502), .Y(n2301) );
INVX2TS U2336 ( .A(n3315), .Y(n2426) );
INVX2TS U2337 ( .A(n5827), .Y(n5502) );
INVX4TS U2338 ( .A(n2390), .Y(n2391) );
INVX4TS U2339 ( .A(n2390), .Y(n2392) );
CLKINVX6TS U2340 ( .A(n2341), .Y(n2342) );
NAND2X1TS U2341 ( .A(n3921), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .Y(n4916) );
NAND2X1TS U2342 ( .A(n3913), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .Y(n4990) );
NOR2X1TS U2343 ( .A(n3905), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]), .Y(n5380) );
AOI21X1TS U2344 ( .A0(n3441), .A1(n3430), .B0(n3419), .Y(n3424) );
BUFX3TS U2345 ( .A(n2550), .Y(n2200) );
CLKAND2X2TS U2346 ( .A(n2808), .B(n2366), .Y(n3104) );
CLKINVX6TS U2347 ( .A(n2197), .Y(n2340) );
NAND2X1TS U2348 ( .A(FPMULT_Op_MY[1]), .B(n2230), .Y(n3059) );
INVX2TS U2349 ( .A(n2508), .Y(n2328) );
OR2X2TS U2350 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n2534) );
INVX3TS U2351 ( .A(n2333), .Y(n2334) );
INVX4TS U2352 ( .A(n2336), .Y(n2337) );
INVX2TS U2353 ( .A(n3627), .Y(n2445) );
OAI21X2TS U2354 ( .A0(n2888), .A1(n2887), .B0(n2886), .Y(n2889) );
INVX2TS U2355 ( .A(n2650), .Y(n2356) );
CLKAND2X2TS U2356 ( .A(n3396), .B(n3395), .Y(n3549) );
AND2X2TS U2357 ( .A(n2559), .B(n2550), .Y(n3518) );
NAND2X1TS U2358 ( .A(n2885), .B(n3402), .Y(n2886) );
NAND2X1TS U2359 ( .A(n2606), .B(n2883), .Y(n2586) );
NAND2X1TS U2360 ( .A(n2566), .B(n2580), .Y(n2567) );
INVX4TS U2361 ( .A(n3487), .Y(n2333) );
CLKXOR2X4TS U2362 ( .A(n2576), .B(n2575), .Y(n2577) );
INVX2TS U2363 ( .A(n2241), .Y(n2324) );
XOR2X1TS U2364 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[2]), .Y(n2234) );
CLKXOR2X2TS U2365 ( .A(n2292), .B(FPMULT_Op_MX[22]), .Y(n2722) );
BUFX4TS U2366 ( .A(n3395), .Y(n3548) );
CLKXOR2X2TS U2367 ( .A(n2549), .B(n2548), .Y(n2550) );
INVX4TS U2368 ( .A(n2525), .Y(n2312) );
NAND2X1TS U2369 ( .A(n2574), .B(n2573), .Y(n2575) );
NAND2X1TS U2370 ( .A(n3392), .B(n3391), .Y(n3393) );
NOR2X1TS U2371 ( .A(n2579), .B(n2582), .Y(n2584) );
INVX2TS U2372 ( .A(n2519), .Y(n2292) );
NOR2X1TS U2373 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[3]), .Y(n2572) );
NAND2X1TS U2374 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[3]), .Y(n2580) );
NAND2X2TS U2375 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n2581) );
NOR2X2TS U2376 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[3]), .Y(n2582) );
NOR2X1TS U2377 ( .A(n3867), .B(n3869), .Y(n3711) );
NOR2X2TS U2378 ( .A(n3721), .B(n3720), .Y(n3840) );
OAI21X2TS U2379 ( .A0(n2884), .A1(n2883), .B0(n2882), .Y(n3402) );
NOR2XLTS U2380 ( .A(n2650), .B(n2594), .Y(n2595) );
AND3X4TS U2381 ( .A(n3771), .B(n3770), .C(n3769), .Y(n3803) );
OR2X1TS U2382 ( .A(n3943), .B(n3942), .Y(n3947) );
INVX2TS U2383 ( .A(n2599), .Y(n2336) );
INVX2TS U2384 ( .A(n3327), .Y(n2428) );
NAND2X1TS U2385 ( .A(n3707), .B(n3706), .Y(n3866) );
NOR2XLTS U2386 ( .A(n2348), .B(n2500), .Y(n3084) );
NOR2XLTS U2387 ( .A(n2348), .B(n2517), .Y(n3089) );
INVX2TS U2388 ( .A(n3835), .Y(n3865) );
OR2X1TS U2389 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n5036), .Y(n3674)
);
BUFX3TS U2390 ( .A(n3629), .Y(n2327) );
NOR2XLTS U2391 ( .A(n2525), .B(n2520), .Y(n3245) );
NOR2XLTS U2392 ( .A(n4369), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n4370) );
CLKXOR2X2TS U2393 ( .A(n3956), .B(n3953), .Y(n3982) );
OAI22X1TS U2394 ( .A0(n3451), .A1(n2441), .B0(n2389), .B1(n2202), .Y(
DP_OP_454J16_123_2743_n263) );
CMPR42X1TS U2395 ( .A(DP_OP_454J16_123_2743_n445), .B(
DP_OP_454J16_123_2743_n458), .C(DP_OP_454J16_123_2743_n351), .D(
DP_OP_454J16_123_2743_n471), .ICI(DP_OP_454J16_123_2743_n354), .S(
DP_OP_454J16_123_2743_n349), .ICO(DP_OP_454J16_123_2743_n347), .CO(
DP_OP_454J16_123_2743_n348) );
NOR2X1TS U2396 ( .A(n5382), .B(n5380), .Y(n5402) );
NAND2X2TS U2397 ( .A(n4785), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .Y(n3993) );
CLKINVX3TS U2398 ( .A(n4608), .Y(n4612) );
NOR3X1TS U2399 ( .A(FPSENCOS_cont_var_out[1]), .B(n5856), .C(n4317), .Y(
n4108) );
INVX2TS U2400 ( .A(n4018), .Y(n4046) );
NAND2X2TS U2401 ( .A(n5476), .B(n4121), .Y(n4321) );
OAI21XLTS U2402 ( .A0(n5337), .A1(n5336), .B0(n5335), .Y(n5339) );
NOR2X1TS U2403 ( .A(mult_x_219_n214), .B(mult_x_219_n222), .Y(n3184) );
OAI21X2TS U2404 ( .A0(n5248), .A1(n5242), .B0(n5243), .Y(n5219) );
NOR2XLTS U2405 ( .A(n5920), .B(FPADDSUB_DMP_SFG[17]), .Y(n5179) );
OR2X1TS U2406 ( .A(mult_x_254_n241), .B(mult_x_254_n246), .Y(n2977) );
AOI21X2TS U2407 ( .A0(n2196), .A1(n3358), .B0(n2618), .Y(n2619) );
AOI21X2TS U2408 ( .A0(n5163), .A1(n5162), .B0(n5161), .Y(n5175) );
OAI21XLTS U2409 ( .A0(n5390), .A1(n5389), .B0(n5388), .Y(n5395) );
OAI21XLTS U2410 ( .A0(n4820), .A1(n4833), .B0(n4834), .Y(n4825) );
BUFX3TS U2411 ( .A(n4109), .Y(n4387) );
NOR3XLTS U2412 ( .A(dataB[25]), .B(dataB[31]), .C(n5440), .Y(n5437) );
NOR2BX1TS U2413 ( .AN(n3659), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]),
.Y(n3698) );
OAI21X1TS U2414 ( .A0(n2919), .A1(n2921), .B0(n2922), .Y(n2854) );
NAND2X1TS U2415 ( .A(DP_OP_454J16_123_2743_n261), .B(
DP_OP_454J16_123_2743_n259), .Y(n3564) );
NAND2X1TS U2416 ( .A(DP_OP_454J16_123_2743_n278), .B(
DP_OP_454J16_123_2743_n272), .Y(n3645) );
INVX2TS U2417 ( .A(n5017), .Y(n2299) );
OAI21XLTS U2418 ( .A0(n5409), .A1(n5408), .B0(n5407), .Y(n5414) );
AOI21X2TS U2419 ( .A0(n2967), .A1(n2946), .B0(n2945), .Y(n2956) );
OAI21XLTS U2420 ( .A0(n3183), .A1(n3179), .B0(n3180), .Y(n3178) );
NAND3X1TS U2421 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n4188),
.C(n5824), .Y(n5457) );
CLKINVX3TS U2422 ( .A(n2195), .Y(n2289) );
INVX2TS U2423 ( .A(n4107), .Y(n4317) );
NAND2X2TS U2424 ( .A(n4216), .B(n5586), .Y(n4215) );
CLKINVX3TS U2425 ( .A(n5661), .Y(n4448) );
INVX2TS U2426 ( .A(n4494), .Y(n2306) );
OAI21XLTS U2427 ( .A0(n5485), .A1(n5856), .B0(FPSENCOS_cont_var_out[1]), .Y(
n4701) );
INVX2TS U2428 ( .A(n2217), .Y(n2283) );
CLKINVX3TS U2429 ( .A(n5661), .Y(n4354) );
BUFX3TS U2430 ( .A(n4215), .Y(n5584) );
CLKINVX3TS U2431 ( .A(n4531), .Y(n5723) );
INVX2TS U2432 ( .A(n4510), .Y(n2806) );
CLKINVX3TS U2433 ( .A(n5737), .Y(n5740) );
INVX2TS U2434 ( .A(n4190), .Y(n5507) );
OAI211XLTS U2435 ( .A0(n4638), .A1(n2307), .B0(n4637), .C0(n4636), .Y(n1807)
);
OAI21XLTS U2436 ( .A0(n4172), .A1(n4608), .B0(n4170), .Y(n2075) );
OAI21XLTS U2437 ( .A0(n4317), .A1(n4260), .B0(n4259), .Y(n1731) );
OAI21XLTS U2438 ( .A0(n2262), .A1(n5723), .B0(n4551), .Y(n1461) );
OAI21XLTS U2439 ( .A0(n5497), .A1(n5498), .B0(n4227), .Y(n2133) );
OAI211XLTS U2440 ( .A0(n4448), .A1(n5543), .B0(n4441), .C0(n4440), .Y(n1939)
);
OAI21XLTS U2441 ( .A0(n4137), .A1(n5503), .B0(n4120), .Y(n2117) );
OAI211XLTS U2442 ( .A0(n4448), .A1(n5546), .B0(n4424), .C0(n4423), .Y(n1936)
);
OAI211XLTS U2443 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5912), .B0(n4384), .C0(n4377), .Y(n1473) );
OAI211XLTS U2444 ( .A0(n4354), .A1(n5558), .B0(n4346), .C0(n4345), .Y(n1926)
);
OAI21XLTS U2445 ( .A0(n2269), .A1(n5723), .B0(n4507), .Y(n1221) );
OAI21XLTS U2446 ( .A0(n2737), .A1(n4526), .B0(n4520), .Y(n1237) );
OAI21XLTS U2447 ( .A0(n2264), .A1(n4526), .B0(n4514), .Y(n1257) );
OAI21XLTS U2448 ( .A0(n5852), .A1(n2806), .B0(n2805), .Y(n1271) );
OAI21XLTS U2449 ( .A0(n2263), .A1(n4538), .B0(n4499), .Y(n1291) );
OAI21XLTS U2450 ( .A0(n2261), .A1(n4538), .B0(n4503), .Y(n1312) );
OAI21XLTS U2451 ( .A0(n5740), .A1(n5666), .B0(n4456), .Y(n1356) );
OAI21XLTS U2452 ( .A0(n2264), .A1(n4544), .B0(n4527), .Y(n1371) );
OAI21XLTS U2453 ( .A0(n2223), .A1(n5722), .B0(n4463), .Y(n1401) );
OAI21XLTS U2454 ( .A0(n5864), .A1(n4546), .B0(n4534), .Y(n1459) );
OR2X2TS U2455 ( .A(DP_OP_454J16_123_2743_n356), .B(
DP_OP_454J16_123_2743_n360), .Y(n2196) );
CLKXOR2X2TS U2456 ( .A(n2398), .B(FPMULT_Op_MX[22]), .Y(n2197) );
INVX2TS U2457 ( .A(n2577), .Y(n2394) );
INVX2TS U2458 ( .A(n3548), .Y(n2386) );
XOR2X1TS U2459 ( .A(n3394), .B(n3393), .Y(n3395) );
INVX2TS U2460 ( .A(n2403), .Y(n2296) );
CLKINVX6TS U2461 ( .A(n2239), .Y(n2403) );
AND2X2TS U2462 ( .A(n5727), .B(n5726), .Y(n5800) );
CLKMX2X2TS U2463 ( .A(FPMULT_P_Sgf[44]), .B(n4000), .S0(n4826), .Y(n1573) );
CLKMX2X2TS U2464 ( .A(FPMULT_P_Sgf[38]), .B(n4803), .S0(n4826), .Y(n1567) );
CLKMX2X2TS U2465 ( .A(FPMULT_P_Sgf[37]), .B(n4814), .S0(n4826), .Y(n1566) );
XOR2X1TS U2466 ( .A(n2637), .B(n2636), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N17) );
XOR2X1TS U2467 ( .A(n2630), .B(n2629), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N16) );
CLKINVX6TS U2468 ( .A(n2296), .Y(n2297) );
CLKMX2X2TS U2469 ( .A(FPMULT_P_Sgf[33]), .B(n4864), .S0(n4962), .Y(n1562) );
CLKMX2X2TS U2470 ( .A(FPMULT_P_Sgf[26]), .B(n4963), .S0(n4962), .Y(n1555) );
XOR2X1TS U2471 ( .A(n3170), .B(n3169), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N17) );
OAI21X1TS U2472 ( .A0(n3170), .A1(n3147), .B0(n3146), .Y(n3152) );
INVX2TS U2473 ( .A(n3588), .Y(n3592) );
AOI211X1TS U2474 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n4489), .B0(n4488), .C0(n4487), .Y(n4491) );
OAI21X1TS U2475 ( .A0(n4993), .A1(n4989), .B0(n4990), .Y(n4983) );
INVX2TS U2476 ( .A(n3350), .Y(n3345) );
NOR2X4TS U2477 ( .A(DP_OP_454J16_123_2743_n319), .B(
DP_OP_454J16_123_2743_n326), .Y(n3339) );
OAI21X1TS U2478 ( .A0(n4455), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n5727),
.Y(n4456) );
OAI211X1TS U2479 ( .A0(n4374), .A1(n5953), .B0(n4384), .C0(n4373), .Y(n1469)
);
CLKMX2X2TS U2480 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_exp_oper_result[8]), .S0(n4070), .Y(n1595) );
AOI2BB1X1TS U2481 ( .A0N(n5802), .A1N(overflow_flag_addsubt), .B0(n5727),
.Y(n1411) );
OAI211X1TS U2482 ( .A0(n4381), .A1(n5953), .B0(n4384), .C0(n4380), .Y(n1470)
);
CLKMX2X2TS U2483 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_exp_oper_result[7]), .S0(n4070), .Y(n1587) );
INVX4TS U2484 ( .A(n5724), .Y(n4384) );
INVX4TS U2485 ( .A(n5115), .Y(n5727) );
AO21X1TS U2486 ( .A0(underflow_flag_addsubt), .A1(n5725), .B0(n5724), .Y(
n1412) );
OR2X2TS U2487 ( .A(n3571), .B(n3570), .Y(n3615) );
XOR2X1TS U2488 ( .A(n3380), .B(n3379), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N3) );
AOI2BB2X1TS U2489 ( .B0(FPADDSUB_Shift_reg_FLAGS_7_6), .B1(n5786), .A0N(
FPADDSUB_SIGN_FLAG_EXP), .A1N(FPADDSUB_Shift_reg_FLAGS_7_6), .Y(n1362)
);
OR2X2TS U2490 ( .A(DP_OP_454J16_123_2743_n366), .B(n2616), .Y(n2493) );
BUFX6TS U2491 ( .A(n5556), .Y(n4267) );
XOR2X1TS U2492 ( .A(n3009), .B(n3008), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N4) );
XOR2X1TS U2493 ( .A(n3014), .B(n3013), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N3) );
BUFX4TS U2494 ( .A(n2527), .Y(n4531) );
NOR2X4TS U2495 ( .A(n4317), .B(n5459), .Y(n4318) );
OR2X2TS U2496 ( .A(mult_x_254_n163), .B(n2858), .Y(n2910) );
OR2X2TS U2497 ( .A(mult_x_219_n161), .B(n2686), .Y(n3137) );
AOI2BB2X1TS U2498 ( .B0(n5572), .B1(n5534), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n5583), .Y(n1945) );
AO22X1TS U2499 ( .A0(n5656), .A1(n5575), .B0(n5581), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1848) );
OR2X2TS U2500 ( .A(mult_x_219_n239), .B(mult_x_219_n244), .Y(n2523) );
OR2X2TS U2501 ( .A(mult_x_219_n245), .B(mult_x_219_n251), .Y(n2522) );
OR2X2TS U2502 ( .A(mult_x_254_n247), .B(mult_x_254_n253), .Y(n2503) );
OAI211X1TS U2503 ( .A0(n5579), .A1(n5948), .B0(n4154), .C0(n4153), .Y(n2130)
);
AO22X1TS U2504 ( .A0(n5511), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n5512), .B1(
Data_1[26]), .Y(n2086) );
AO22X1TS U2505 ( .A0(n5511), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n5512), .B1(
Data_1[28]), .Y(n2084) );
NOR2X6TS U2506 ( .A(n4486), .B(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n4476) );
AO22X1TS U2507 ( .A0(n5513), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n5512), .B1(
Data_1[29]), .Y(n2083) );
AO22X1TS U2508 ( .A0(n5513), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n5512), .B1(
Data_1[30]), .Y(n2082) );
AO22X1TS U2509 ( .A0(n5513), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n5512), .B1(
Data_1[31]), .Y(n2081) );
AO22X1TS U2510 ( .A0(n5583), .A1(n5532), .B0(n5538), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1946) );
CLKINVX6TS U2511 ( .A(n5584), .Y(n2406) );
OAI21XLTS U2512 ( .A0(n5695), .A1(underflow_flag_mult), .B0(n5694), .Y(n5696) );
OAI21X1TS U2513 ( .A0(n5531), .A1(n5907), .B0(n5533), .Y(n5532) );
NAND2BX1TS U2514 ( .AN(n3621), .B(n2343), .Y(n3526) );
INVX4TS U2515 ( .A(n4148), .Y(n4486) );
NAND2BX1TS U2516 ( .AN(n3621), .B(n2351), .Y(n3513) );
OAI21X1TS U2517 ( .A0(n2283), .A1(n5007), .B0(n4160), .Y(n1690) );
AND2X4TS U2518 ( .A(n2902), .B(n2388), .Y(n3624) );
NOR2X6TS U2519 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n4128), .Y(n4148) );
INVX4TS U2520 ( .A(n5586), .Y(n5527) );
OAI21X1TS U2521 ( .A0(n5350), .A1(n5349), .B0(n5348), .Y(n5352) );
OAI21X1TS U2522 ( .A0(n5337), .A1(n5292), .B0(n5301), .Y(n5294) );
NAND2X2TS U2523 ( .A(n4140), .B(n5839), .Y(n4128) );
INVX2TS U2524 ( .A(n2721), .Y(n2390) );
INVX4TS U2525 ( .A(n5716), .Y(n5082) );
INVX4TS U2526 ( .A(n5639), .Y(n4673) );
INVX4TS U2527 ( .A(n5639), .Y(n4679) );
INVX2TS U2528 ( .A(n5291), .Y(n5337) );
NOR3X1TS U2529 ( .A(n4469), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .C(n5839),
.Y(n4470) );
INVX4TS U2530 ( .A(n5579), .Y(n5501) );
OAI21X1TS U2531 ( .A0(n5639), .A1(n2204), .B0(n4608), .Y(n2078) );
AO21X1TS U2532 ( .A0(n5469), .A1(begin_operation), .B0(n4010), .Y(n4159) );
INVX2TS U2533 ( .A(n3886), .Y(n3838) );
INVX2TS U2534 ( .A(n3847), .Y(n3849) );
INVX4TS U2535 ( .A(n4782), .Y(n4977) );
INVX4TS U2536 ( .A(n4782), .Y(n5001) );
INVX2TS U2537 ( .A(n3888), .Y(n3890) );
INVX4TS U2538 ( .A(n2887), .Y(n3408) );
INVX4TS U2539 ( .A(n4686), .Y(n4648) );
INVX2TS U2540 ( .A(n3896), .Y(n3898) );
AND2X4TS U2541 ( .A(n5009), .B(n4713), .Y(n4715) );
INVX1TS U2542 ( .A(n4725), .Y(n4726) );
OR2X2TS U2543 ( .A(n3806), .B(n3805), .Y(n3931) );
OR2X2TS U2544 ( .A(n3959), .B(n3958), .Y(n3963) );
OR2X2TS U2545 ( .A(n3973), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]), .Y(n3977) );
OR2X2TS U2546 ( .A(n3794), .B(n3793), .Y(n2531) );
NAND2XLTS U2547 ( .A(n2299), .B(FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n4580) );
OR2X2TS U2548 ( .A(n3774), .B(n3773), .Y(n3797) );
INVX4TS U2549 ( .A(n5737), .Y(n5796) );
INVX2TS U2550 ( .A(n4163), .Y(n4145) );
INVX4TS U2551 ( .A(n5725), .Y(n5802) );
NOR2X1TS U2552 ( .A(n2751), .B(FPADDSUB_intDY_EWSW[10]), .Y(n2752) );
NOR2X1TS U2553 ( .A(n2789), .B(FPADDSUB_intDY_EWSW[24]), .Y(n2790) );
NAND2XLTS U2554 ( .A(n5725), .B(result_add_subt[27]), .Y(n4373) );
OAI21X1TS U2555 ( .A0(n5343), .A1(n5348), .B0(n5344), .Y(n3682) );
NAND2X1TS U2556 ( .A(n5465), .B(n5464), .Y(n2191) );
INVX4TS U2557 ( .A(n5107), .Y(n5788) );
NAND2XLTS U2558 ( .A(n5725), .B(result_add_subt[28]), .Y(n4383) );
XOR2X1TS U2559 ( .A(n2276), .B(n2534), .Y(DP_OP_26J16_124_9022_n18) );
INVX2TS U2560 ( .A(n4485), .Y(n4492) );
NAND2XLTS U2561 ( .A(n5725), .B(result_add_subt[24]), .Y(n4375) );
OAI21X1TS U2562 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n2461), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n2772) );
NOR2X1TS U2563 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .Y(n3697) );
AND2X4TS U2564 ( .A(n5454), .B(n5463), .Y(n4104) );
NOR2X4TS U2565 ( .A(operation[1]), .B(n5463), .Y(n4157) );
MX2X2TS U2566 ( .A(FPMULT_P_Sgf[47]), .B(n5006), .S0(n5427), .Y(n1694) );
MX2X2TS U2567 ( .A(FPMULT_P_Sgf[46]), .B(n3997), .S0(n5426), .Y(n1575) );
NAND2X4TS U2568 ( .A(n5003), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[22]), .Y(n5005) );
XNOR2X2TS U2569 ( .A(n5003), .B(n3995), .Y(n3997) );
NOR2X6TS U2570 ( .A(n4733), .B(n4732), .Y(n5003) );
NAND2X6TS U2571 ( .A(n4759), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[18]), .Y(n4751) );
OAI211X1TS U2572 ( .A0(n4647), .A1(n2306), .B0(n4646), .C0(n4645), .Y(n1793)
);
OAI211X1TS U2573 ( .A0(n4647), .A1(n2315), .B0(n4565), .C0(n4564), .Y(n1794)
);
OAI211X1TS U2574 ( .A0(n4579), .A1(n2315), .B0(n4578), .C0(n4577), .Y(n1790)
);
OAI211X1TS U2575 ( .A0(n4638), .A1(n2316), .B0(n4595), .C0(n4594), .Y(n1808)
);
OAI211X1TS U2576 ( .A0(n4685), .A1(n2240), .B0(n4684), .C0(n4683), .Y(n1787)
);
NAND2X4TS U2577 ( .A(n4776), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[16]), .Y(n4766) );
OAI211X1TS U2578 ( .A0(n4685), .A1(n2316), .B0(n4585), .C0(n4584), .Y(n1789)
);
OAI211X1TS U2579 ( .A0(n4685), .A1(n2306), .B0(n4651), .C0(n4650), .Y(n1788)
);
OAI211X1TS U2580 ( .A0(n4678), .A1(n2307), .B0(n4677), .C0(n4676), .Y(n1797)
);
OAI211X1TS U2581 ( .A0(n4656), .A1(n2306), .B0(n4655), .C0(n4654), .Y(n1803)
);
XOR2X2TS U2582 ( .A(n3648), .B(n3647), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N19) );
XNOR2X2TS U2583 ( .A(n4802), .B(n4801), .Y(n4803) );
OAI211X1TS U2584 ( .A0(n4642), .A1(n2316), .B0(n4572), .C0(n4571), .Y(n1792)
);
OAI211X1TS U2585 ( .A0(n4671), .A1(n2316), .B0(n4622), .C0(n4621), .Y(n1802)
);
OAI211X1TS U2586 ( .A0(n4660), .A1(n2306), .B0(n4659), .C0(n4658), .Y(n1799)
);
OAI211X1TS U2587 ( .A0(n4665), .A1(n2307), .B0(n4664), .C0(n4663), .Y(n1795)
);
OAI211X1TS U2588 ( .A0(n4678), .A1(n2316), .B0(n4603), .C0(n4602), .Y(n1798)
);
OAI211X1TS U2589 ( .A0(n4642), .A1(n2307), .B0(n4641), .C0(n4640), .Y(n1791)
);
OAI211X1TS U2590 ( .A0(n4665), .A1(n2316), .B0(n4599), .C0(n4598), .Y(n1796)
);
OAI211X1TS U2591 ( .A0(n4660), .A1(n2315), .B0(n4624), .C0(n4623), .Y(n1800)
);
XOR2X1TS U2592 ( .A(n2879), .B(n2878), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N15) );
AOI21X2TS U2593 ( .A0(n3337), .A1(n3335), .B0(n2874), .Y(n2879) );
XNOR2X1TS U2594 ( .A(n3343), .B(n3342), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N13) );
AOI21X2TS U2595 ( .A0(n3337), .A1(n2634), .B0(n2633), .Y(n2637) );
XOR2X1TS U2596 ( .A(n3525), .B(n3524), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N12) );
XOR2X1TS U2597 ( .A(n3349), .B(n3348), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N11) );
INVX2TS U2598 ( .A(n4625), .Y(n2286) );
NOR2X2TS U2599 ( .A(n4810), .B(n4801), .Y(n3989) );
INVX6TS U2600 ( .A(n4784), .Y(n4887) );
NAND2X2TS U2601 ( .A(n3987), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .Y(n4822) );
AO22X1TS U2602 ( .A0(n3696), .A1(n4049), .B0(FPADDSUB_ADD_OVRFLW_NRM), .B1(
n2304), .Y(n1351) );
AOI22X2TS U2603 ( .A0(n5192), .A1(n4049), .B0(FPADDSUB_Raw_mant_NRM_SWR[25]),
.B1(n2304), .Y(n5193) );
OAI21X1TS U2604 ( .A0(n4172), .A1(n5480), .B0(n4171), .Y(n1330) );
XOR2X1TS U2605 ( .A(n3183), .B(n3182), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N15) );
XOR2X1TS U2606 ( .A(n3144), .B(n3143), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N21) );
INVX4TS U2607 ( .A(n5800), .Y(n2198) );
INVX2TS U2608 ( .A(n4846), .Y(n4848) );
OAI21X1TS U2609 ( .A0(n4136), .A1(n4608), .B0(n4134), .Y(n2077) );
XOR2X1TS U2610 ( .A(n3361), .B(n3360), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N8) );
OAI21X1TS U2611 ( .A0(n4151), .A1(n5480), .B0(n4150), .Y(n1322) );
OAI21X1TS U2612 ( .A0(n4151), .A1(n4608), .B0(n4149), .Y(n2076) );
XOR2X1TS U2613 ( .A(n3190), .B(n3189), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N14) );
OAI21X1TS U2614 ( .A0(n4616), .A1(n4136), .B0(n4135), .Y(n1318) );
NOR2X4TS U2615 ( .A(n3332), .B(n3644), .Y(n3589) );
XOR2X1TS U2616 ( .A(n2956), .B(n2955), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N15) );
XOR2X1TS U2617 ( .A(n2917), .B(n2916), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N21) );
XOR2X1TS U2618 ( .A(n2943), .B(n2942), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N17) );
NAND2X1TS U2619 ( .A(n3646), .B(n3645), .Y(n3647) );
INVX2TS U2620 ( .A(n4873), .Y(n4875) );
OAI21X1TS U2621 ( .A0(n3293), .A1(n3289), .B0(n3290), .Y(n3200) );
XOR2X1TS U2622 ( .A(n3293), .B(n3292), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N11) );
XOR2X1TS U2623 ( .A(n3205), .B(n3204), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N10) );
XNOR2X2TS U2624 ( .A(n3964), .B(n3960), .Y(n3983) );
NAND3X1TS U2625 ( .A(n5617), .B(n5616), .C(n5615), .Y(n1825) );
NAND3X1TS U2626 ( .A(n5600), .B(n5599), .C(n5598), .Y(n1832) );
OAI21X1TS U2627 ( .A0(n3074), .A1(n3070), .B0(n3071), .Y(n2973) );
NAND3X1TS U2628 ( .A(n5611), .B(n5610), .C(n5609), .Y(n1827) );
OAI211X1TS U2629 ( .A0(n4408), .A1(n5946), .B0(n4395), .C0(n4394), .Y(n1820)
);
NOR2X4TS U2630 ( .A(DP_OP_454J16_123_2743_n278), .B(
DP_OP_454J16_123_2743_n272), .Y(n3644) );
NAND3X1TS U2631 ( .A(n5592), .B(n5591), .C(n5603), .Y(n1838) );
NAND3X1TS U2632 ( .A(n5631), .B(n5630), .C(n5636), .Y(n1816) );
NAND3X1TS U2633 ( .A(n5619), .B(n5618), .C(n5625), .Y(n1824) );
OAI211X1TS U2634 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5911), .B0(n4384), .C0(n4382), .Y(n1467) );
NAND3X1TS U2635 ( .A(n5602), .B(n5601), .C(n5615), .Y(n1830) );
OAI211X1TS U2636 ( .A0(n4408), .A1(n2458), .B0(n4391), .C0(n4390), .Y(n1822)
);
OAI211X1TS U2637 ( .A0(n4376), .A1(n5737), .B0(n4384), .C0(n4375), .Y(n1472)
);
OAI211X1TS U2638 ( .A0(n4448), .A1(n2473), .B0(n4447), .C0(n4446), .Y(n1941)
);
OAI211X1TS U2639 ( .A0(n4448), .A1(n5544), .B0(n4426), .C0(n4425), .Y(n1938)
);
OAI211X1TS U2640 ( .A0(n4448), .A1(n2471), .B0(n4428), .C0(n4427), .Y(n1934)
);
OAI211X1TS U2641 ( .A0(n4451), .A1(n5737), .B0(n4384), .C0(n4383), .Y(n1468)
);
OAI211X1TS U2642 ( .A0(n4408), .A1(n2457), .B0(n4386), .C0(n4385), .Y(n1831)
);
OAI211X1TS U2643 ( .A0(n4448), .A1(n5545), .B0(n4430), .C0(n4429), .Y(n1937)
);
NAND3X1TS U2644 ( .A(n5605), .B(n5604), .C(n5603), .Y(n1829) );
OAI211X1TS U2645 ( .A0(n4448), .A1(n5541), .B0(n4443), .C0(n4442), .Y(n1940)
);
OAI211X1TS U2646 ( .A0(n4448), .A1(n5547), .B0(n4439), .C0(n4438), .Y(n1935)
);
NAND3X1TS U2647 ( .A(n5595), .B(n5594), .C(n5598), .Y(n1836) );
OAI211X1TS U2648 ( .A0(n4408), .A1(n2487), .B0(n4401), .C0(n4400), .Y(n1817)
);
OAI211X1TS U2649 ( .A0(n4408), .A1(n2452), .B0(n4403), .C0(n4402), .Y(n1819)
);
OAI21X1TS U2650 ( .A0(n4905), .A1(n4916), .B0(n4906), .Y(n3923) );
NAND3X1TS U2651 ( .A(n5590), .B(n5589), .C(n5609), .Y(n1840) );
OAI211X1TS U2652 ( .A0(n4408), .A1(n2468), .B0(n4407), .C0(n4406), .Y(n1818)
);
NAND3X1TS U2653 ( .A(n5614), .B(n5613), .C(n5620), .Y(n1826) );
NAND3X1TS U2654 ( .A(n5607), .B(n5606), .C(n5620), .Y(n1828) );
OAI211X1TS U2655 ( .A0(n4448), .A1(n5551), .B0(n4435), .C0(n4434), .Y(n1932)
);
NAND3X1TS U2656 ( .A(n5622), .B(n5621), .C(n5620), .Y(n1823) );
XOR2X1TS U2657 ( .A(n2979), .B(n2978), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N10) );
NAND3X1TS U2658 ( .A(n5627), .B(n5626), .C(n5625), .Y(n1821) );
OAI211X1TS U2659 ( .A0(n4422), .A1(n2488), .B0(n4389), .C0(n4388), .Y(n1834)
);
OAI211X1TS U2660 ( .A0(n4422), .A1(n2490), .B0(n4412), .C0(n4411), .Y(n1839)
);
OAI211X1TS U2661 ( .A0(n4448), .A1(n5549), .B0(n4432), .C0(n4431), .Y(n1933)
);
XOR2X1TS U2662 ( .A(n3372), .B(n3371), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N5) );
OAI211X1TS U2663 ( .A0(n4379), .A1(n5737), .B0(n4384), .C0(n4378), .Y(n1471)
);
XOR2X1TS U2664 ( .A(n3074), .B(n3073), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N11) );
INVX3TS U2665 ( .A(n4131), .Y(n4169) );
NAND3BX1TS U2666 ( .AN(FPMULT_Exp_module_Data_S[7]), .B(n5112), .C(n5111),
.Y(n5113) );
OAI211X1TS U2667 ( .A0(n4354), .A1(n2476), .B0(n4330), .C0(n4329), .Y(n1924)
);
OAI211X1TS U2668 ( .A0(n4354), .A1(n5553), .B0(n4320), .C0(n4319), .Y(n1930)
);
OAI211X1TS U2669 ( .A0(n4354), .A1(n5563), .B0(n4326), .C0(n4325), .Y(n1923)
);
OAI211X1TS U2670 ( .A0(n4354), .A1(n2481), .B0(n4348), .C0(n4347), .Y(n1927)
);
XOR2X1TS U2671 ( .A(n3219), .B(n3218), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N7) );
INVX1TS U2672 ( .A(n3154), .Y(n3155) );
NAND3X1TS U2673 ( .A(n5633), .B(n5632), .C(n5636), .Y(n1815) );
NAND2X2TS U2674 ( .A(DP_OP_454J16_123_2743_n361), .B(
DP_OP_454J16_123_2743_n365), .Y(n3362) );
AOI211X1TS U2675 ( .A0(n5848), .A1(n4126), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C0(n4131), .Y(n4127) );
OAI211X1TS U2676 ( .A0(n4367), .A1(n5568), .B0(n4324), .C0(n4323), .Y(n1919)
);
OAI211X1TS U2677 ( .A0(n4354), .A1(n5565), .B0(n4328), .C0(n4327), .Y(n1922)
);
OAI211X1TS U2678 ( .A0(n4354), .A1(n2482), .B0(n4338), .C0(n4337), .Y(n1931)
);
NAND3X1TS U2679 ( .A(n5638), .B(n5637), .C(n5636), .Y(n1814) );
OAI211X1TS U2680 ( .A0(n4354), .A1(n5557), .B0(n4332), .C0(n4331), .Y(n1928)
);
OAI211X1TS U2681 ( .A0(n4367), .A1(n2470), .B0(n4350), .C0(n4349), .Y(n1921)
);
OAI211X1TS U2682 ( .A0(n4354), .A1(n5555), .B0(n4353), .C0(n4352), .Y(n1929)
);
OAI211X1TS U2683 ( .A0(n4354), .A1(n5560), .B0(n4334), .C0(n4333), .Y(n1925)
);
CMPR42X2TS U2684 ( .A(DP_OP_454J16_123_2743_n336), .B(
DP_OP_454J16_123_2743_n468), .C(DP_OP_454J16_123_2743_n337), .D(
DP_OP_454J16_123_2743_n333), .ICI(DP_OP_454J16_123_2743_n330), .S(
DP_OP_454J16_123_2743_n327), .ICO(DP_OP_454J16_123_2743_n325), .CO(
DP_OP_454J16_123_2743_n326) );
OAI21X1TS U2685 ( .A0(n2225), .A1(n5722), .B0(n4462), .Y(n1407) );
AOI222X1TS U2686 ( .A0(n4272), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n5523), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n4261), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n4265) );
AO22X1TS U2687 ( .A0(FPSENCOS_d_ff2_X[21]), .A1(n5537), .B0(
FPSENCOS_d_ff_Xn[21]), .B1(n5542), .Y(n1963) );
AO22X1TS U2688 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n5537), .B0(
FPSENCOS_d_ff_Xn[30]), .B1(n5542), .Y(n1952) );
AOI222X1TS U2689 ( .A0(n5527), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n4267), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n4261), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n4268) );
AOI222X1TS U2690 ( .A0(n5527), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n5523), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n4246), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n4269) );
AO22X1TS U2691 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n5524), .B0(
FPSENCOS_d_ff_Xn[4]), .B1(n5523), .Y(n1997) );
INVX2TS U2692 ( .A(n5410), .Y(n5412) );
OAI21X1TS U2693 ( .A0(n4245), .A1(n4275), .B0(n4244), .Y(n1695) );
INVX2TS U2694 ( .A(n2926), .Y(n2929) );
AOI222X1TS U2695 ( .A0(n5527), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n4267), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n4261), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n4235) );
AOI222X1TS U2696 ( .A0(n4255), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4267), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n4261), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n4234) );
AO22X1TS U2697 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n5537), .B0(
FPSENCOS_d_ff_Xn[22]), .B1(n5542), .Y(n1961) );
OAI21X1TS U2698 ( .A0(n2797), .A1(n4546), .B0(n4545), .Y(n1460) );
OAI21X1TS U2699 ( .A0(n5853), .A1(n5722), .B0(n4498), .Y(n1404) );
OAI21X1TS U2700 ( .A0(n2223), .A1(n5723), .B0(n4508), .Y(n1217) );
AO22X1TS U2701 ( .A0(FPSENCOS_d_ff2_X[15]), .A1(n5524), .B0(
FPSENCOS_d_ff_Xn[15]), .B1(n5542), .Y(n1975) );
AO22X1TS U2702 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n5537), .B0(
FPSENCOS_d_ff_Xn[23]), .B1(n5542), .Y(n1959) );
OAI21X1TS U2703 ( .A0(n5853), .A1(n5723), .B0(n4506), .Y(n1213) );
AO22X1TS U2704 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n5537), .B0(
FPSENCOS_d_ff_Xn[18]), .B1(n5542), .Y(n1969) );
AO22X1TS U2705 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n5524), .B0(
FPSENCOS_d_ff_Xn[11]), .B1(n5542), .Y(n1983) );
OAI21X1TS U2706 ( .A0(n2492), .A1(n4544), .B0(n4535), .Y(n1380) );
OAI21X1TS U2707 ( .A0(n2262), .A1(n5722), .B0(n4461), .Y(n1413) );
OAI21X1TS U2708 ( .A0(n2766), .A1(n4544), .B0(n4539), .Y(n1377) );
OAI21X1TS U2709 ( .A0(n2492), .A1(n4526), .B0(n4515), .Y(n1245) );
OAI21X1TS U2710 ( .A0(n5863), .A1(n4538), .B0(n2807), .Y(n1368) );
OAI21X1TS U2711 ( .A0(n2265), .A1(n4538), .B0(n4502), .Y(n1284) );
XOR2X1TS U2712 ( .A(n2993), .B(n2992), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N7) );
OAI21X1TS U2713 ( .A0(n2265), .A1(n4556), .B0(n4552), .Y(n1282) );
OAI21X1TS U2714 ( .A0(n2766), .A1(n4526), .B0(n4518), .Y(n1249) );
OAI21X1TS U2715 ( .A0(n2734), .A1(n4538), .B0(n4504), .Y(n1277) );
OAI21X1TS U2716 ( .A0(n2738), .A1(n4544), .B0(n4540), .Y(n1383) );
ADDFHX2TS U2717 ( .A(n3547), .B(n3546), .CI(n3545), .CO(
DP_OP_454J16_123_2743_n350), .S(DP_OP_454J16_123_2743_n351) );
OAI21X1TS U2718 ( .A0(n2745), .A1(n4556), .B0(n4517), .Y(n1265) );
OAI21X1TS U2719 ( .A0(n2734), .A1(n4556), .B0(n4524), .Y(n1275) );
OAI21X1TS U2720 ( .A0(n2993), .A1(n2989), .B0(n2990), .Y(n2988) );
OAI21X1TS U2721 ( .A0(n5863), .A1(n4556), .B0(n4511), .Y(n1261) );
AO22X1TS U2722 ( .A0(FPSENCOS_d_ff2_X[9]), .A1(n5524), .B0(
FPSENCOS_d_ff_Xn[9]), .B1(n5523), .Y(n1987) );
OAI21X1TS U2723 ( .A0(n2259), .A1(n4544), .B0(n4529), .Y(n1374) );
OAI21X1TS U2724 ( .A0(n2259), .A1(n4526), .B0(n4522), .Y(n1253) );
OAI21X1TS U2725 ( .A0(n5852), .A1(n4556), .B0(n4509), .Y(n1269) );
AO22X1TS U2726 ( .A0(FPSENCOS_d_ff2_X[8]), .A1(n5524), .B0(
FPSENCOS_d_ff_Xn[8]), .B1(n5523), .Y(n1989) );
AO22X1TS U2727 ( .A0(FPSENCOS_d_ff2_X[0]), .A1(n5524), .B0(
FPSENCOS_d_ff_Xn[0]), .B1(n5523), .Y(n2005) );
AOI222X1TS U2728 ( .A0(n5527), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n5556), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n4261), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n4266) );
AOI222X1TS U2729 ( .A0(n5527), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n5556), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n4261), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n4264) );
AOI222X1TS U2730 ( .A0(n5527), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n5556), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n4261), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n4263) );
XOR2X1TS U2731 ( .A(n3224), .B(n3223), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N6) );
INVX2TS U2732 ( .A(n4106), .Y(n4422) );
XNOR2X2TS U2733 ( .A(DP_OP_26J16_124_9022_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n4453) );
XOR2X1TS U2734 ( .A(n2998), .B(n2997), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N6) );
INVX2TS U2735 ( .A(n4106), .Y(n4367) );
OAI21X1TS U2736 ( .A0(n3009), .A1(n3005), .B0(n3006), .Y(n3004) );
OR2X2TS U2737 ( .A(mult_x_219_n174), .B(mult_x_219_n170), .Y(n3158) );
AO22X1TS U2738 ( .A0(n5583), .A1(n5582), .B0(n5581), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1846) );
AO22X1TS U2739 ( .A0(n5507), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n5508), .B1(
Data_1[10]), .Y(n2102) );
AO22X1TS U2740 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n5701), .B0(
mult_result[15]), .B1(n5703), .Y(n1489) );
AO22X1TS U2741 ( .A0(n5507), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n5506), .B1(
Data_1[5]), .Y(n2107) );
AO22X1TS U2742 ( .A0(n5511), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n5506), .B1(
Data_1[2]), .Y(n2110) );
AO22X1TS U2743 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n5701), .B0(
mult_result[14]), .B1(n5703), .Y(n1490) );
AO22X1TS U2744 ( .A0(n5507), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n5508), .B1(
Data_1[12]), .Y(n2100) );
INVX4TS U2745 ( .A(n2406), .Y(n2407) );
AO22X1TS U2746 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n5704), .B0(
mult_result[16]), .B1(n5703), .Y(n1488) );
AO22X1TS U2747 ( .A0(n5509), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n5510), .B1(
Data_1[16]), .Y(n2096) );
AO22X1TS U2748 ( .A0(n5511), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n5510), .B1(
Data_1[15]), .Y(n2097) );
AO22X1TS U2749 ( .A0(n5513), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n5506), .B1(
Data_1[1]), .Y(n2111) );
NAND3X1TS U2750 ( .A(n4476), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n5842),
.Y(n4477) );
AO22X1TS U2751 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n5704), .B0(
mult_result[17]), .B1(n5702), .Y(n1487) );
AO22X1TS U2752 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n5704), .B0(
mult_result[18]), .B1(n5702), .Y(n1486) );
AO22X1TS U2753 ( .A0(n5583), .A1(n5536), .B0(n5538), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1944) );
AO22X1TS U2754 ( .A0(n5507), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n5508), .B1(
Data_1[11]), .Y(n2101) );
AO22X1TS U2755 ( .A0(n5507), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n5506), .B1(
Data_1[4]), .Y(n2108) );
AO22X1TS U2756 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n5704), .B0(
mult_result[19]), .B1(n5702), .Y(n1485) );
AO22X1TS U2757 ( .A0(n5511), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n5508), .B1(
Data_1[14]), .Y(n2098) );
AO22X1TS U2758 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n5704), .B0(
mult_result[22]), .B1(n5703), .Y(n1481) );
AO22X1TS U2759 ( .A0(n5507), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n5508), .B1(
Data_1[9]), .Y(n2103) );
AO22X1TS U2760 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n5704), .B0(
mult_result[20]), .B1(n5702), .Y(n1484) );
AO22X1TS U2761 ( .A0(n5511), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n5506), .B1(
Data_1[0]), .Y(n2112) );
AO22X1TS U2762 ( .A0(n5513), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n5506), .B1(
Data_1[3]), .Y(n2109) );
AO22X1TS U2763 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n5704), .B0(
mult_result[21]), .B1(n5702), .Y(n1483) );
AO22X1TS U2764 ( .A0(n5507), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n5508), .B1(
Data_1[13]), .Y(n2099) );
OAI21X1TS U2765 ( .A0(n5505), .A1(n4226), .B0(n4225), .Y(n2131) );
AO22X1TS U2766 ( .A0(n5513), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n5510), .B1(
Data_1[27]), .Y(n2085) );
NAND3X1TS U2767 ( .A(n5453), .B(n5452), .C(n5461), .Y(n5455) );
AO22X1TS U2768 ( .A0(n5704), .A1(FPMULT_Sgf_normalized_result[2]), .B0(
mult_result[2]), .B1(n5702), .Y(n1502) );
AO22X1TS U2769 ( .A0(n5704), .A1(FPMULT_Sgf_normalized_result[1]), .B0(
mult_result[1]), .B1(n5702), .Y(n1503) );
AO22X1TS U2770 ( .A0(n5704), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
mult_result[0]), .B1(n5702), .Y(n1504) );
AO22X1TS U2771 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n5697), .B0(
mult_result[3]), .B1(n5699), .Y(n1501) );
AO22X1TS U2772 ( .A0(n5513), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n5508), .B1(
Data_1[7]), .Y(n2105) );
AO22X1TS U2773 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n5697), .B0(
mult_result[4]), .B1(n5699), .Y(n1500) );
AO22X1TS U2774 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n5697), .B0(
mult_result[5]), .B1(n5699), .Y(n1499) );
AO22X1TS U2775 ( .A0(n5509), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n5508), .B1(
Data_1[24]), .Y(n2088) );
AO22X1TS U2776 ( .A0(n5509), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n5510), .B1(
Data_1[23]), .Y(n2089) );
AO22X1TS U2777 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n5701), .B0(
mult_result[6]), .B1(n5699), .Y(n1498) );
AO22X1TS U2778 ( .A0(n5511), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n5508), .B1(
Data_1[6]), .Y(n2106) );
AO22X1TS U2779 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n5701), .B0(
mult_result[7]), .B1(n5699), .Y(n1497) );
AO22X1TS U2780 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n5701), .B0(
mult_result[8]), .B1(n5703), .Y(n1496) );
AO22X1TS U2781 ( .A0(n5509), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n5510), .B1(
Data_1[22]), .Y(n2090) );
AO22X1TS U2782 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n5701), .B0(
mult_result[9]), .B1(n5703), .Y(n1495) );
AO22X1TS U2783 ( .A0(n5509), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n5510), .B1(
Data_1[21]), .Y(n2091) );
AO22X1TS U2784 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n5701), .B0(
mult_result[10]), .B1(n5703), .Y(n1494) );
AO22X1TS U2785 ( .A0(n5507), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n5508), .B1(
Data_1[8]), .Y(n2104) );
AO22X1TS U2786 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n5701), .B0(
mult_result[13]), .B1(n5703), .Y(n1491) );
AO22X1TS U2787 ( .A0(n5509), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n5510), .B1(
Data_1[17]), .Y(n2095) );
OR2X2TS U2788 ( .A(mult_x_254_n176), .B(mult_x_254_n172), .Y(n2931) );
AO22X1TS U2789 ( .A0(n5509), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n5510), .B1(
Data_1[18]), .Y(n2094) );
AO22X1TS U2790 ( .A0(n5509), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n5510), .B1(
Data_1[19]), .Y(n2093) );
AO22X1TS U2791 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n5701), .B0(
mult_result[12]), .B1(n5703), .Y(n1492) );
AO22X1TS U2792 ( .A0(n5509), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n5510), .B1(
Data_1[20]), .Y(n2092) );
AO22X1TS U2793 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n5701), .B0(
mult_result[11]), .B1(n5703), .Y(n1493) );
AO22X1TS U2794 ( .A0(n5509), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n5512), .B1(
Data_1[25]), .Y(n2087) );
NAND2X2TS U2795 ( .A(mult_x_254_n259), .B(mult_x_254_n263), .Y(n2990) );
AND3X2TS U2796 ( .A(FPSENCOS_cont_var_out[1]), .B(n4107), .C(n5856), .Y(
n4106) );
BUFX3TS U2797 ( .A(n4233), .Y(n4261) );
OAI21X1TS U2798 ( .A0(n2284), .A1(n5496), .B0(n4139), .Y(n2116) );
NAND2BX1TS U2799 ( .AN(n5492), .B(n5491), .Y(n2123) );
OAI21X1TS U2800 ( .A0(n5502), .A1(n5498), .B0(n4152), .Y(n2129) );
NOR2X1TS U2801 ( .A(n2208), .B(n5498), .Y(n5500) );
NAND4BX1TS U2802 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n4368), .C(n4381),
.D(n4379), .Y(n4369) );
OAI21X1TS U2803 ( .A0(n4123), .A1(n4122), .B0(n5464), .Y(n2149) );
OAI211X1TS U2804 ( .A0(n5952), .A1(n5015), .B0(n4865), .C0(n4174), .Y(n1693)
);
OAI21X1TS U2805 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n5505), .B0(n4156),
.Y(n2114) );
OAI31XLTS U2806 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(
FPMULT_FS_Module_state_reg[2]), .A2(n4700), .B0(n4699), .Y(n1691) );
NOR2X4TS U2807 ( .A(n5353), .B(FPADDSUB_OP_FLAG_SFG), .Y(n4049) );
INVX4TS U2808 ( .A(n2336), .Y(n2338) );
INVX4TS U2809 ( .A(n2386), .Y(n2199) );
OAI21X1TS U2810 ( .A0(n5452), .A1(intadd_21_CI), .B0(n4117), .Y(n1853) );
NOR2X4TS U2811 ( .A(n5426), .B(n5112), .Y(n4070) );
INVX3TS U2812 ( .A(n5586), .Y(n4272) );
OAI21X1TS U2813 ( .A0(n5452), .A1(intadd_22_CI), .B0(n4118), .Y(n1951) );
NOR2X1TS U2814 ( .A(n4472), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n4473) );
INVX3TS U2815 ( .A(n5569), .Y(n4255) );
OR2X2TS U2816 ( .A(n5873), .B(n4736), .Y(n4737) );
OR2X2TS U2817 ( .A(FPMULT_FSM_selector_C), .B(n4736), .Y(n2253) );
OAI21X1TS U2818 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n4977), .B0(
n4114), .Y(n1620) );
CLKBUFX3TS U2819 ( .A(n4011), .Y(n2411) );
NAND3X1TS U2820 ( .A(FPSENCOS_cont_iter_out[1]), .B(n2285), .C(n5495), .Y(
n4091) );
INVX3TS U2821 ( .A(n2244), .Y(n2389) );
NOR2X1TS U2822 ( .A(n5101), .B(n5054), .Y(n4001) );
OAI21X1TS U2823 ( .A0(n3665), .A1(n5460), .B0(n5452), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
NOR2X1TS U2824 ( .A(n5102), .B(n5101), .Y(n5104) );
CLKBUFX3TS U2825 ( .A(n3673), .Y(n2303) );
AND2X2TS U2826 ( .A(n2305), .B(FPADDSUB_OP_FLAG_SFG), .Y(n5253) );
OR2X2TS U2827 ( .A(n4738), .B(FPMULT_FSM_selector_C), .Y(n4997) );
INVX2TS U2828 ( .A(n4715), .Y(n5014) );
INVX2TS U2829 ( .A(n4715), .Y(n4717) );
INVX2TS U2830 ( .A(n4715), .Y(n4714) );
INVX2TS U2831 ( .A(n5020), .Y(n5057) );
NOR2X4TS U2832 ( .A(n4738), .B(n5873), .Y(n4744) );
NOR2X1TS U2833 ( .A(n5050), .B(n5055), .Y(n5021) );
INVX3TS U2834 ( .A(n2712), .Y(n2314) );
INVX4TS U2835 ( .A(n2215), .Y(n2201) );
NOR2X1TS U2836 ( .A(n5098), .B(n5101), .Y(n5099) );
NOR2X1TS U2837 ( .A(n5086), .B(n5055), .Y(n5047) );
AOI211X1TS U2838 ( .A0(n2764), .A1(n2763), .B0(n2762), .C0(n2761), .Y(n2770)
);
NOR2X1TS U2839 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n4368) );
NAND2XLTS U2840 ( .A(FPSENCOS_cont_iter_out[0]), .B(n4137), .Y(n4138) );
NOR2X1TS U2841 ( .A(n5101), .B(n5050), .Y(n4098) );
INVX2TS U2842 ( .A(n4715), .Y(n5691) );
NOR2X1TS U2843 ( .A(n5095), .B(n5055), .Y(n5038) );
NOR2X1TS U2844 ( .A(n5102), .B(n5055), .Y(n5026) );
NOR2X1TS U2845 ( .A(n5092), .B(n5055), .Y(n5041) );
NOR2X1TS U2846 ( .A(n5089), .B(n5055), .Y(n5044) );
NOR2X1TS U2847 ( .A(n5079), .B(n5055), .Y(n5056) );
NOR2X1TS U2848 ( .A(n5083), .B(n5055), .Y(n5051) );
NOR2X1TS U2849 ( .A(n5098), .B(n5055), .Y(n5031) );
OAI21XLTS U2850 ( .A0(n4214), .A1(n5886), .B0(n4211), .Y(op_result[11]) );
OAI21XLTS U2851 ( .A0(n4209), .A1(n5892), .B0(n4208), .Y(op_result[7]) );
OAI21XLTS U2852 ( .A0(n4209), .A1(n5882), .B0(n4206), .Y(op_result[6]) );
OAI21XLTS U2853 ( .A0(n4214), .A1(n5889), .B0(n4204), .Y(op_result[12]) );
OAI21XLTS U2854 ( .A0(n4209), .A1(n5896), .B0(n4201), .Y(op_result[5]) );
OAI21XLTS U2855 ( .A0(n4209), .A1(n5881), .B0(n4205), .Y(op_result[4]) );
OAI21XLTS U2856 ( .A0(n4209), .A1(n5890), .B0(n4207), .Y(op_result[3]) );
OAI21XLTS U2857 ( .A0(n4209), .A1(n5891), .B0(n4193), .Y(op_result[2]) );
OAI21XLTS U2858 ( .A0(n4209), .A1(n5894), .B0(n4194), .Y(op_result[1]) );
OAI21XLTS U2859 ( .A0(n4209), .A1(n5893), .B0(n4192), .Y(op_result[0]) );
OAI21XLTS U2860 ( .A0(n4214), .A1(n5883), .B0(n4183), .Y(op_result[13]) );
OAI21XLTS U2861 ( .A0(n4214), .A1(n5887), .B0(n4179), .Y(op_result[14]) );
OAI21XLTS U2862 ( .A0(n4200), .A1(n5878), .B0(n4177), .Y(op_result[19]) );
OAI21XLTS U2863 ( .A0(n4200), .A1(n5877), .B0(n4184), .Y(op_result[21]) );
OAI21XLTS U2864 ( .A0(n4200), .A1(n5874), .B0(n4185), .Y(op_result[22]) );
OAI21XLTS U2865 ( .A0(n4200), .A1(n5879), .B0(n4187), .Y(op_result[20]) );
INVX3TS U2866 ( .A(n5526), .Y(n5452) );
AND2X2TS U2867 ( .A(n4173), .B(n2283), .Y(n4735) );
NOR2X1TS U2868 ( .A(n5079), .B(n5101), .Y(n5080) );
OR2X4TS U2869 ( .A(n2300), .B(n5714), .Y(n5639) );
AND2X2TS U2870 ( .A(n5117), .B(n5116), .Y(n5693) );
INVX2TS U2871 ( .A(n3842), .Y(n3844) );
NOR2X1TS U2872 ( .A(n5092), .B(n5101), .Y(n5093) );
NOR2X1TS U2873 ( .A(n5086), .B(n5101), .Y(n5087) );
NOR2X1TS U2874 ( .A(n5095), .B(n5101), .Y(n5096) );
INVX4TS U2875 ( .A(n3533), .Y(n2202) );
NAND2X6TS U2876 ( .A(n3038), .B(n2360), .Y(n3130) );
INVX4TS U2877 ( .A(n2376), .Y(n2203) );
NOR2X1TS U2878 ( .A(n5083), .B(n5101), .Y(n5084) );
NAND2BX1TS U2879 ( .AN(n3621), .B(n2324), .Y(n2553) );
NOR2X1TS U2880 ( .A(n5461), .B(n5650), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
NOR2X1TS U2881 ( .A(n5089), .B(n5101), .Y(n5090) );
INVX1TS U2882 ( .A(n3814), .Y(n3816) );
NAND3X1TS U2883 ( .A(n3654), .B(n3653), .C(n3652), .Y(n3656) );
INVX1TS U2884 ( .A(n5482), .Y(n5483) );
NAND2BX1TS U2885 ( .AN(FPSENCOS_d_ff2_X[23]), .B(n2285), .Y(intadd_22_CI) );
XNOR2X1TS U2886 ( .A(n3390), .B(n3389), .Y(n3394) );
NOR2X1TS U2887 ( .A(n2348), .B(n2498), .Y(n3126) );
NOR2X4TS U2888 ( .A(n3723), .B(n3722), .Y(n3842) );
INVX1TS U2889 ( .A(n4695), .Y(n4698) );
OAI211X1TS U2890 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n2479), .B0(n2753), .C0(
n2756), .Y(n2746) );
XNOR2X1TS U2891 ( .A(n2594), .B(n2572), .Y(n2576) );
NOR2X1TS U2892 ( .A(n4948), .B(FPMULT_Sgf_normalized_result[2]), .Y(n4949)
);
XNOR2X2TS U2893 ( .A(n2894), .B(n2892), .Y(n2893) );
INVX1TS U2894 ( .A(n5644), .Y(n5514) );
NOR2X1TS U2895 ( .A(n4468), .B(FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n4474) );
NAND2X4TS U2896 ( .A(n4130), .B(n4129), .Y(n4471) );
AND2X2TS U2897 ( .A(n5009), .B(n5117), .Y(n4782) );
NOR2X4TS U2898 ( .A(n5902), .B(n5802), .Y(n5018) );
NAND2X2TS U2899 ( .A(n4713), .B(n3697), .Y(n4113) );
INVX1TS U2900 ( .A(n5007), .Y(n4115) );
INVX3TS U2901 ( .A(n2255), .Y(n2294) );
INVX4TS U2902 ( .A(n5105), .Y(n2204) );
OR2X2TS U2903 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n4094), .Y(n3671)
);
OAI211X2TS U2904 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n2459), .B0(n2764),
.C0(n2744), .Y(n2758) );
NOR2X1TS U2905 ( .A(n4720), .B(n4893), .Y(n4721) );
NAND3X1TS U2906 ( .A(n5905), .B(n2791), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n2793) );
NOR2X1TS U2907 ( .A(n4720), .B(n5849), .Y(n4722) );
AOI211X1TS U2908 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n2797), .B0(n2799),
.C0(n2796), .Y(n2801) );
INVX3TS U2909 ( .A(n2247), .Y(n2375) );
OAI211X2TS U2910 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n2472), .B0(n2784),
.C0(n2765), .Y(n2778) );
NAND2XLTS U2911 ( .A(n4586), .B(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n4589) );
INVX1TS U2912 ( .A(n5459), .Y(n3665) );
INVX3TS U2913 ( .A(n4569), .Y(n4680) );
NAND3X1TS U2914 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(n3657),
.C(n3659), .Y(n4236) );
NAND3X1TS U2915 ( .A(n5434), .B(n5433), .C(n5432), .Y(n5963) );
AND3X2TS U2916 ( .A(FPSENCOS_cont_var_out[1]), .B(ready_add_subt), .C(n5856),
.Y(n5654) );
OAI21X1TS U2917 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n2469), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n2780) );
OR2X2TS U2918 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n2255) );
NAND3X1TS U2919 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2250),
.C(n5871), .Y(n5464) );
NOR2X1TS U2920 ( .A(n5834), .B(n5900), .Y(FPMULT_S_Oper_A_exp[8]) );
NAND2BX1TS U2921 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n2792) );
INVX1TS U2922 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n5486) );
NAND2BX1TS U2923 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n2785) );
NAND2BX1TS U2924 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n2791) );
NAND2BX1TS U2925 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n2775) );
CLKBUFX3TS U2926 ( .A(n2230), .Y(n2326) );
NAND2BX1TS U2927 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n2765) );
NOR2X1TS U2928 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .Y(n3658) );
OAI21X1TS U2929 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n2478), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n2760) );
INVX3TS U2930 ( .A(n2483), .Y(n2331) );
AOI32X1TS U2931 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n2216), .A2(n2251),
.B0(FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n2216), .Y(n4126) );
INVX6TS U2932 ( .A(n2243), .Y(n2396) );
NAND2BX1TS U2933 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n2744) );
NAND2BX1TS U2934 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n2753) );
INVX1TS U2935 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n5107) );
OR2X2TS U2936 ( .A(n2218), .B(FPADDSUB_ADD_OVRFLW_NRM), .Y(n4569) );
NOR2X4TS U2937 ( .A(n5454), .B(operation[2]), .Y(n4176) );
NAND3X1TS U2938 ( .A(n3668), .B(n3667), .C(n3666), .Y(n3669) );
OAI21X2TS U2939 ( .A0(n4873), .A1(n4884), .B0(n4874), .Y(n4844) );
OAI21X4TS U2940 ( .A0(n3896), .A1(n3893), .B0(n3897), .Y(n3809) );
OAI21X1TS U2941 ( .A0(n5819), .A1(n5010), .B0(FPMULT_FS_Module_state_reg[3]),
.Y(n4174) );
NOR2X1TS U2942 ( .A(n5929), .B(FPADDSUB_DMP_SFG[0]), .Y(n4014) );
CMPR42X2TS U2943 ( .A(DP_OP_454J16_123_2743_n417), .B(
DP_OP_454J16_123_2743_n340), .C(DP_OP_454J16_123_2743_n344), .D(
DP_OP_454J16_123_2743_n430), .ICI(DP_OP_454J16_123_2743_n443), .S(
DP_OP_454J16_123_2743_n338), .ICO(DP_OP_454J16_123_2743_n336), .CO(
DP_OP_454J16_123_2743_n337) );
AOI21X4TS U2944 ( .A0(n3593), .A1(n3592), .B0(n3591), .Y(n3611) );
INVX4TS U2945 ( .A(n4523), .Y(n5722) );
AOI21X4TS U2946 ( .A0(n2843), .A1(n2983), .B0(n2842), .Y(n2974) );
OAI21X4TS U2947 ( .A0(n5379), .A1(n3912), .B0(n3911), .Y(n4896) );
ADDFX2TS U2948 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]), .B(
n3740), .CI(n3739), .CO(n3760), .S(n3759) );
ADDFHX2TS U2949 ( .A(n3620), .B(n3619), .CI(n3618), .CO(n3545), .S(
DP_OP_454J16_123_2743_n358) );
XOR2X1TS U2950 ( .A(n2963), .B(n2962), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N14) );
AOI21X4TS U2951 ( .A0(n2703), .A1(n2702), .B0(n2701), .Y(n2704) );
INVX4TS U2952 ( .A(n2244), .Y(n2388) );
OAI21X4TS U2953 ( .A0(n4821), .A1(n4834), .B0(n4822), .Y(n4799) );
OAI21X2TS U2954 ( .A0(n3888), .A1(n3885), .B0(n3889), .Y(n3728) );
OAI21X1TS U2955 ( .A0(n3170), .A1(n3166), .B0(n3167), .Y(n3165) );
CMPR42X2TS U2956 ( .A(DP_OP_454J16_123_2743_n264), .B(
DP_OP_454J16_123_2743_n385), .C(DP_OP_454J16_123_2743_n268), .D(
DP_OP_454J16_123_2743_n395), .ICI(DP_OP_454J16_123_2743_n265), .S(
DP_OP_454J16_123_2743_n262), .ICO(DP_OP_454J16_123_2743_n260), .CO(
DP_OP_454J16_123_2743_n261) );
NOR3X4TS U2957 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(
n4129) );
NOR2BX4TS U2958 ( .AN(n4161), .B(FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n4475) );
AO22X2TS U2959 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[1]), .A1(n4600), .B0(
n4596), .B1(n5108), .Y(n4560) );
OAI211X1TS U2960 ( .A0(n4671), .A1(n2307), .B0(n4670), .C0(n4669), .Y(n1801)
);
XNOR2X2TS U2961 ( .A(n3488), .B(n2342), .Y(n3449) );
XNOR2X2TS U2962 ( .A(n3477), .B(n2342), .Y(n3631) );
OAI21X2TS U2963 ( .A0(n5368), .A1(n3878), .B0(n3877), .Y(n5364) );
AOI21X2TS U2964 ( .A0(n3337), .A1(n2697), .B0(n2702), .Y(n2630) );
NAND2X2TS U2965 ( .A(n2946), .B(n2850), .Y(n2852) );
CLKINVX6TS U2966 ( .A(n3386), .Y(n2358) );
CMPR42X2TS U2967 ( .A(DP_OP_454J16_123_2743_n410), .B(
DP_OP_454J16_123_2743_n286), .C(DP_OP_454J16_123_2743_n282), .D(
DP_OP_454J16_123_2743_n287), .ICI(DP_OP_454J16_123_2743_n283), .S(
DP_OP_454J16_123_2743_n279), .ICO(DP_OP_454J16_123_2743_n277), .CO(
DP_OP_454J16_123_2743_n278) );
XOR2X4TS U2968 ( .A(n2709), .B(n2708), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N20) );
CLKXOR2X2TS U2969 ( .A(n2277), .B(FPMULT_Op_MX[16]), .Y(n2594) );
OAI21X2TS U2970 ( .A0(n3895), .A1(n3811), .B0(n3810), .Y(n3904) );
OAI21X2TS U2971 ( .A0(n4979), .A1(n4990), .B0(n4980), .Y(n4952) );
AOI21X4TS U2972 ( .A0(n5200), .A1(n5196), .B0(n3695), .Y(n5191) );
OAI21X4TS U2973 ( .A0(n5210), .A1(n5204), .B0(n5205), .Y(n5200) );
OAI21X4TS U2974 ( .A0(n5146), .A1(n5141), .B0(n5142), .Y(n5157) );
XOR2X4TS U2975 ( .A(n2908), .B(n2907), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N22) );
XNOR2X2TS U2976 ( .A(n3488), .B(n3533), .Y(n3626) );
OAI21X1TS U2977 ( .A0(n5410), .A1(n5407), .B0(n5411), .Y(n3909) );
OAI21X1TS U2978 ( .A0(n2956), .A1(n2952), .B0(n2953), .Y(n2951) );
INVX4TS U2979 ( .A(n4275), .Y(n4309) );
NOR2X4TS U2980 ( .A(n5475), .B(n4237), .Y(n4240) );
NOR2X2TS U2981 ( .A(n4955), .B(n4957), .Y(n3918) );
NOR2X1TS U2982 ( .A(n3915), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(n4955) );
OAI21X4TS U2983 ( .A0(n3821), .A1(n3782), .B0(n3781), .Y(n3834) );
OAI2BB1X2TS U2984 ( .A0N(n5252), .A1N(n5194), .B0(n5193), .Y(n1410) );
OAI21X4TS U2985 ( .A0(n5276), .A1(n5138), .B0(n5137), .Y(n5266) );
AOI21X4TS U2986 ( .A0(n5282), .A1(n5136), .B0(n5135), .Y(n5276) );
OAI21X1TS U2987 ( .A0(n5324), .A1(n4014), .B0(n4013), .Y(n4029) );
NOR2X8TS U2988 ( .A(n4751), .B(n4750), .Y(n3999) );
XOR2X4TS U2989 ( .A(n3607), .B(n3606), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N21) );
OAI21X4TS U2990 ( .A0(n3371), .A1(n3368), .B0(n3369), .Y(n3366) );
NAND2X2TS U2991 ( .A(n2612), .B(n2611), .Y(n3369) );
ADDHX1TS U2992 ( .A(n3639), .B(n3638), .CO(DP_OP_454J16_123_2743_n369), .S(
n2614) );
XOR2X4TS U2993 ( .A(n3587), .B(n3586), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N25) );
OAI21X2TS U2994 ( .A0(n2700), .A1(n2699), .B0(n2698), .Y(n2701) );
OAI21X1TS U2995 ( .A0(n3525), .A1(n3521), .B0(n3522), .Y(n3343) );
AOI21X2TS U2996 ( .A0(n3865), .A1(n3837), .B0(n3836), .Y(n3887) );
OAI21X2TS U2997 ( .A0(n4863), .A1(n4859), .B0(n4860), .Y(n4850) );
AOI21X1TS U2998 ( .A0(n4887), .A1(n4845), .B0(n4844), .Y(n4863) );
XNOR2X2TS U2999 ( .A(n3892), .B(n3891), .Y(n3905) );
XNOR2X2TS U3000 ( .A(n3622), .B(n2342), .Y(n3630) );
XOR2X4TS U3001 ( .A(n3598), .B(n3597), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N23) );
XNOR2X2TS U3002 ( .A(n3527), .B(n2342), .Y(n3623) );
OAI21X1TS U3003 ( .A0(n2943), .A1(n2939), .B0(n2940), .Y(n2938) );
NAND2X2TS U3004 ( .A(n2926), .B(n2931), .Y(n2920) );
AOI21X4TS U3005 ( .A0(n3978), .A1(n3977), .B0(n3976), .Y(n3979) );
OAI21X4TS U3006 ( .A0(n3972), .A1(n3971), .B0(n3970), .Y(n3978) );
AOI21X4TS U3007 ( .A0(n3964), .A1(n3963), .B0(n3962), .Y(n3972) );
OAI21X2TS U3008 ( .A0(n3186), .A1(n3191), .B0(n3187), .Y(n3172) );
OAI21X1TS U3009 ( .A0(n3170), .A1(n3156), .B0(n3155), .Y(n3160) );
XOR2X4TS U3010 ( .A(n2870), .B(n2869), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N23) );
AOI21X4TS U3011 ( .A0(n2927), .A1(n2931), .B0(n2853), .Y(n2919) );
OAI21X4TS U3012 ( .A0(n2940), .A1(n2934), .B0(n2935), .Y(n2927) );
AOI21X2TS U3013 ( .A0(n4018), .A1(n3681), .B0(n3680), .Y(n4035) );
OAI21X4TS U3014 ( .A0(n5169), .A1(n5164), .B0(n5165), .Y(n5259) );
OAI21X1TS U3015 ( .A0(n4040), .A1(n4044), .B0(n4041), .Y(n3680) );
MX2X1TS U3016 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
BUFX3TS U3017 ( .A(n4106), .Y(n5635) );
MX2X1TS U3018 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U3019 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
OAI21X2TS U3020 ( .A0(n3826), .A1(n3822), .B0(n3827), .Y(n3780) );
XOR2X1TS U3021 ( .A(FPMULT_Op_MY[6]), .B(n2396), .Y(n2235) );
AND2X4TS U3022 ( .A(n2644), .B(n2354), .Y(n3298) );
INVX2TS U3023 ( .A(n3298), .Y(n2424) );
AOI21X1TS U3024 ( .A0(n4722), .A1(n4892), .B0(n4721), .Y(n4855) );
AOI21X2TS U3025 ( .A0(n5291), .A1(n3689), .B0(n3688), .Y(n5278) );
BUFX3TS U3026 ( .A(n3059), .Y(n3133) );
AO21XLTS U3027 ( .A0(n2425), .A1(n2356), .B0(n2246), .Y(mult_x_219_n320) );
AOI21X2TS U3028 ( .A0(n5157), .A1(n5154), .B0(n3691), .Y(n5169) );
BUFX3TS U3029 ( .A(n4318), .Y(n5629) );
BUFX3TS U3030 ( .A(n4322), .Y(n5612) );
MX2X1TS U3031 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U3032 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
MX2X1TS U3033 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
INVX2TS U3034 ( .A(n2419), .Y(n5015) );
NAND2X1TS U3035 ( .A(n4159), .B(n4158), .Y(n5010) );
CLKAND2X2TS U3036 ( .A(n5935), .B(FPADDSUB_DMP_SFG[12]), .Y(n5139) );
AOI2BB2X1TS U3037 ( .B0(n2802), .B1(n2801), .A0N(n2800), .A1N(n2799), .Y(
n2803) );
AOI221X1TS U3038 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n2256), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n2489), .C0(n2798), .Y(n2800) );
BUFX3TS U3039 ( .A(n4530), .Y(n4554) );
NAND2X4TS U3040 ( .A(n3776), .B(n3747), .Y(n3771) );
NOR2X1TS U3041 ( .A(n2348), .B(n2499), .Y(n3127) );
NAND2BXLTS U3042 ( .AN(n2442), .B(n2346), .Y(n3019) );
NAND2X1TS U3043 ( .A(n2894), .B(n2892), .Y(n2719) );
INVX2TS U3044 ( .A(n3420), .Y(n3422) );
NAND2X1TS U3045 ( .A(n3430), .B(n3429), .Y(n3431) );
CLKAND2X2TS U3046 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MX[12]), .Y(n2521) );
AOI2BB2XLTS U3047 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n2464), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n2733), .Y(n2735) );
NAND3XLTS U3048 ( .A(n2479), .B(n2753), .C(FPADDSUB_intDX_EWSW[8]), .Y(n2754) );
NAND2BXLTS U3049 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n2755) );
NOR2X1TS U3050 ( .A(n4903), .B(n4905), .Y(n3924) );
NAND2BX1TS U3051 ( .AN(n2773), .B(n2767), .Y(n2768) );
NOR2X1TS U3052 ( .A(n3980), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(n4871) );
AOI211X2TS U3053 ( .A0(n2294), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n5060),
.C0(n4095), .Y(n5083) );
OAI21X1TS U3054 ( .A0(n4967), .A1(n5845), .B0(n4719), .Y(n4892) );
AOI2BB1XLTS U3055 ( .A0N(n4467), .A1N(FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n4468) );
AOI2BB1XLTS U3056 ( .A0N(n5860), .A1N(n4471), .B0(n4470), .Y(n4472) );
AO21XLTS U3057 ( .A0(n2429), .A1(n2378), .B0(n3326), .Y(mult_x_219_n292) );
AO21XLTS U3058 ( .A0(n2427), .A1(n2358), .B0(n2245), .Y(mult_x_219_n306) );
AO21XLTS U3059 ( .A0(n2434), .A1(n3033), .B0(n2508), .Y(mult_x_254_n300) );
AO21XLTS U3060 ( .A0(n2424), .A1(n2354), .B0(n2237), .Y(mult_x_219_n334) );
AOI211X2TS U3061 ( .A0(n2294), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n5060),
.C0(n3670), .Y(n5079) );
AOI21X2TS U3062 ( .A0(n5268), .A1(n5264), .B0(n3690), .Y(n5146) );
NAND2X1TS U3063 ( .A(n3982), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .Y(n4860) );
INVX2TS U3064 ( .A(n4855), .Y(n4882) );
NAND2X1TS U3065 ( .A(n5461), .B(n5460), .Y(n4105) );
INVX2TS U3066 ( .A(n4892), .Y(n4938) );
CLKBUFX2TS U3067 ( .A(n2527), .Y(n4533) );
INVX2TS U3068 ( .A(n2239), .Y(n2404) );
AO21XLTS U3069 ( .A0(n2318), .A1(n2373), .B0(n2348), .Y(n2862) );
OR2X1TS U3070 ( .A(n2866), .B(n2865), .Y(n2868) );
NOR3XLTS U3071 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n5430) );
NAND3XLTS U3072 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n5445) );
AOI31XLTS U3073 ( .A0(n5443), .A1(n5442), .A2(n5441), .B0(n5448), .Y(n5446)
);
INVX4TS U3074 ( .A(n2287), .Y(n2316) );
NOR2X1TS U3075 ( .A(n3166), .B(n3161), .Y(n3153) );
NAND2X1TS U3076 ( .A(n3153), .B(n3158), .Y(n3147) );
NOR2X2TS U3077 ( .A(n2835), .B(n2834), .Y(n3000) );
NAND2BXLTS U3078 ( .AN(n3128), .B(n2345), .Y(n2822) );
AO21XLTS U3079 ( .A0(n2327), .A1(n2392), .B0(n2341), .Y(n3580) );
OR2X1TS U3080 ( .A(n3581), .B(n2422), .Y(n3582) );
CLKAND2X2TS U3081 ( .A(n3589), .B(n3577), .Y(n2533) );
NOR2X1TS U3082 ( .A(mult_x_219_n262), .B(n2671), .Y(n3220) );
NAND2BXLTS U3083 ( .AN(n3324), .B(FPMULT_Op_MX[13]), .Y(n2640) );
INVX2TS U3084 ( .A(n4533), .Y(n4526) );
CLKAND2X2TS U3085 ( .A(n5931), .B(FPADDSUB_DMP_SFG[20]), .Y(n5184) );
AOI21X2TS U3086 ( .A0(n5236), .A1(n5181), .B0(n5180), .Y(n5246) );
CLKAND2X2TS U3087 ( .A(n5932), .B(FPADDSUB_DMP_SFG[18]), .Y(n5180) );
AOI21X2TS U3088 ( .A0(n5257), .A1(n5177), .B0(n5176), .Y(n5227) );
CLKAND2X2TS U3089 ( .A(n5933), .B(FPADDSUB_DMP_SFG[16]), .Y(n5176) );
CLKAND2X2TS U3090 ( .A(n5934), .B(FPADDSUB_DMP_SFG[14]), .Y(n5161) );
INVX2TS U3091 ( .A(n5141), .Y(n5143) );
OAI221X1TS U3092 ( .A0(n2484), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n2265),
.B1(FPADDSUB_intDY_EWSW[9]), .C0(n5757), .Y(n5764) );
NAND4XLTS U3093 ( .A(n5776), .B(n5775), .C(n5774), .D(n5773), .Y(n5777) );
OAI221XLTS U3094 ( .A0(n2507), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n5853),
.B1(FPADDSUB_intDY_EWSW[15]), .C0(n5750), .Y(n5755) );
OAI221X1TS U3095 ( .A0(n5863), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n2492),
.B1(FPADDSUB_intDY_EWSW[13]), .C0(n5751), .Y(n5754) );
INVX2TS U3096 ( .A(n4510), .Y(n4538) );
BUFX3TS U3097 ( .A(n2527), .Y(n4542) );
INVX2TS U3098 ( .A(n4510), .Y(n4544) );
INVX2TS U3099 ( .A(n4533), .Y(n4556) );
NOR2BX2TS U3100 ( .AN(n4241), .B(n4315), .Y(n4289) );
MX2X1TS U3101 ( .A(n4724), .B(FPMULT_Add_result[23]), .S0(n4977), .Y(n1597)
);
OAI211XLTS U3102 ( .A0(n4422), .A1(n2477), .B0(n4393), .C0(n4392), .Y(n1835)
);
OAI222X1TS U3103 ( .A0(n5723), .A1(n5906), .B0(n5836), .B1(
FPADDSUB_Shift_reg_FLAGS_7_6), .C0(n2224), .C1(n5722), .Y(n1415) );
AOI32X1TS U3104 ( .A0(n5505), .A1(n5504), .A2(n5503), .B0(n5502), .B1(n5504),
.Y(n2115) );
OAI222X1TS U3105 ( .A0(n5722), .A1(n5897), .B0(n5833), .B1(
FPADDSUB_Shift_reg_FLAGS_7_6), .C0(n2226), .C1(n5723), .Y(n1464) );
OAI222X1TS U3106 ( .A0(n5722), .A1(n5905), .B0(n5835), .B1(
FPADDSUB_Shift_reg_FLAGS_7_6), .C0(n2227), .C1(n5723), .Y(n1462) );
MX2X1TS U3107 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(n5016), .S0(n5427),
.Y(n1585) );
OAI211XLTS U3108 ( .A0(n4422), .A1(n2474), .B0(n4399), .C0(n4398), .Y(n1843)
);
OAI211XLTS U3109 ( .A0(n4422), .A1(n2467), .B0(n4397), .C0(n4396), .Y(n1841)
);
OAI211XLTS U3110 ( .A0(n4422), .A1(n2273), .B0(n4415), .C0(n4414), .Y(n1837)
);
OAI211XLTS U3111 ( .A0(n4422), .A1(n2486), .B0(n4410), .C0(n4409), .Y(n1842)
);
NAND4BXLTS U3112 ( .AN(n5110), .B(FPMULT_Exp_module_Data_S[6]), .C(
FPMULT_Exp_module_Data_S[5]), .D(FPMULT_Exp_module_Data_S[4]), .Y(
n5111) );
NAND4XLTS U3113 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n5110) );
AO21XLTS U3114 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[25]), .A1(n5718), .B0(n3678),
.Y(n1180) );
AOI2BB2XLTS U3115 ( .B0(n2400), .B1(n4002), .A0N(n5054), .A1N(n5055), .Y(
n3677) );
NOR2X1TS U3116 ( .A(n2290), .B(FPMULT_Op_MY[4]), .Y(n2881) );
NAND2X1TS U3117 ( .A(n2718), .B(n2717), .Y(n2892) );
NAND2X1TS U3118 ( .A(n2899), .B(n2898), .Y(n3384) );
XOR2X1TS U3119 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[20]), .Y(n2897) );
XOR2X1TS U3120 ( .A(n2279), .B(FPMULT_Op_MX[18]), .Y(n3390) );
NOR2X2TS U3121 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n3404) );
NOR2X2TS U3122 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n2579) );
NAND2BXLTS U3123 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n2731) );
NOR2X1TS U3124 ( .A(n3840), .B(n3842), .Y(n3837) );
NOR2X1TS U3125 ( .A(n2348), .B(n2509), .Y(n3085) );
NAND2BXLTS U3126 ( .AN(n3128), .B(n2329), .Y(n3076) );
INVX2TS U3127 ( .A(n2483), .Y(n2330) );
NOR2X1TS U3128 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n3437) );
NAND2X1TS U3129 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n3403) );
NOR2X1TS U3130 ( .A(n3418), .B(n3420), .Y(n3425) );
NAND2BXLTS U3131 ( .AN(n3621), .B(n2349), .Y(n3534) );
OR2X1TS U3132 ( .A(n3703), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]), .Y(n3706) );
NOR2X2TS U3133 ( .A(n3709), .B(n3708), .Y(n3869) );
NAND2X1TS U3134 ( .A(n3709), .B(n3708), .Y(n3870) );
NAND2X1TS U3135 ( .A(n3725), .B(n3724), .Y(n3885) );
NAND2X1TS U3136 ( .A(n3753), .B(n3752), .Y(n3831) );
NOR2X2TS U3137 ( .A(n3755), .B(n3754), .Y(n3785) );
NAND2X1TS U3138 ( .A(n3797), .B(n2531), .Y(n3802) );
NOR2X1TS U3139 ( .A(n3935), .B(n3934), .Y(n3939) );
NOR2X1TS U3140 ( .A(n3702), .B(n3701), .Y(n3847) );
NAND2X1TS U3141 ( .A(n3702), .B(n3701), .Y(n3848) );
NOR2XLTS U3142 ( .A(n4045), .B(n4040), .Y(n3681) );
AO21XLTS U3143 ( .A0(n2432), .A1(n2370), .B0(n3044), .Y(mult_x_254_n328) );
CMPR42X1TS U3144 ( .A(mult_x_254_n306), .B(mult_x_254_n330), .C(
mult_x_254_n294), .D(mult_x_254_n342), .ICI(mult_x_254_n207), .S(
mult_x_254_n201), .ICO(mult_x_254_n199), .CO(mult_x_254_n200) );
AO21XLTS U3145 ( .A0(n2431), .A1(n2367), .B0(n2483), .Y(mult_x_254_n342) );
OAI22X1TS U3146 ( .A0(n2317), .A1(n3029), .B0(n2373), .B1(n3028), .Y(
mult_x_254_n296) );
CMPR42X1TS U3147 ( .A(mult_x_254_n322), .B(mult_x_254_n334), .C(
mult_x_254_n273), .D(mult_x_254_n298), .ICI(mult_x_254_n239), .S(
mult_x_254_n236), .ICO(mult_x_254_n234), .CO(mult_x_254_n235) );
CLKBUFX2TS U3148 ( .A(n3130), .Y(n2433) );
NAND2BXLTS U3149 ( .AN(n3128), .B(n2375), .Y(n3129) );
INVX2TS U3150 ( .A(n2235), .Y(n2360) );
NAND2BXLTS U3151 ( .AN(n3128), .B(n2396), .Y(n2812) );
NAND2BXLTS U3152 ( .AN(n3128), .B(n2331), .Y(n2818) );
INVX2TS U3153 ( .A(n3104), .Y(n2431) );
NAND2X1TS U3154 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n3436) );
OAI21X2TS U3155 ( .A0(n3420), .A1(n3429), .B0(n3421), .Y(n3435) );
AND2X2TS U3156 ( .A(n3425), .B(n3426), .Y(n3440) );
AO21X1TS U3157 ( .A0(n2438), .A1(n2387), .B0(n2350), .Y(n3554) );
INVX2TS U3158 ( .A(n3552), .Y(n3414) );
CMPR42X1TS U3159 ( .A(DP_OP_454J16_123_2743_n467), .B(
DP_OP_454J16_123_2743_n415), .C(DP_OP_454J16_123_2743_n428), .D(
DP_OP_454J16_123_2743_n324), .ICI(DP_OP_454J16_123_2743_n328), .S(
DP_OP_454J16_123_2743_n322), .ICO(DP_OP_454J16_123_2743_n320), .CO(
DP_OP_454J16_123_2743_n321) );
OAI22X1TS U3160 ( .A0(n3478), .A1(n2395), .B0(n3541), .B1(n2880), .Y(
DP_OP_454J16_123_2743_n448) );
NAND2BXLTS U3161 ( .AN(n2445), .B(n2335), .Y(n2563) );
INVX2TS U3162 ( .A(n3518), .Y(n2435) );
CLKBUFX2TS U3163 ( .A(n2562), .Y(n3487) );
NAND2X1TS U3164 ( .A(n2543), .B(n2542), .Y(n2544) );
NAND2X2TS U3165 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .Y(n2545) );
CMPR42X1TS U3166 ( .A(n2206), .B(n2207), .C(mult_x_219_n284), .D(
mult_x_219_n308), .ICI(mult_x_219_n296), .S(mult_x_219_n185), .ICO(
mult_x_219_n183), .CO(mult_x_219_n184) );
CMPR42X1TS U3167 ( .A(mult_x_219_n312), .B(mult_x_219_n336), .C(
mult_x_219_n300), .D(n2525), .ICI(mult_x_219_n224), .S(mult_x_219_n217), .ICO(mult_x_219_n215), .CO(mult_x_219_n216) );
CMPR42X1TS U3168 ( .A(mult_x_219_n350), .B(mult_x_219_n338), .C(
mult_x_219_n302), .D(mult_x_219_n236), .ICI(mult_x_219_n240), .S(
mult_x_219_n234), .ICO(mult_x_219_n232), .CO(mult_x_219_n233) );
NAND2BXLTS U3169 ( .AN(n3324), .B(n2398), .Y(n3325) );
NAND2BXLTS U3170 ( .AN(n2444), .B(n2380), .Y(n3314) );
CLKBUFX2TS U3171 ( .A(n3308), .Y(n2425) );
NAND2BXLTS U3172 ( .AN(n3324), .B(n2365), .Y(n2661) );
INVX2TS U3173 ( .A(n3298), .Y(n2423) );
INVX2TS U3174 ( .A(n2638), .Y(n2354) );
NAND2X1TS U3175 ( .A(n2312), .B(n2520), .Y(n3284) );
OAI21XLTS U3176 ( .A0(n5122), .A1(n5121), .B0(n5120), .Y(n5123) );
OAI32X1TS U3177 ( .A0(n2743), .A1(n2742), .A2(n2741), .B0(n2740), .B1(n2742),
.Y(n2749) );
NOR2BX1TS U3178 ( .AN(n2747), .B(n2746), .Y(n2748) );
INVX2TS U3179 ( .A(n2758), .Y(n2747) );
OAI2BB2XLTS U3180 ( .B0(n2759), .B1(n2758), .A0N(n2757), .A1N(n2756), .Y(
n2762) );
OA22X1TS U3181 ( .A0(n2475), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n2478), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n2764) );
OAI21XLTS U3182 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n2494), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n2750) );
NOR2X2TS U3183 ( .A(FPADDSUB_Raw_mant_NRM_SWR[23]), .B(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n4482) );
NAND2X1TS U3184 ( .A(n3759), .B(n3758), .Y(n3893) );
NOR2X1TS U3185 ( .A(n4989), .B(n4979), .Y(n4951) );
NOR2X1TS U3186 ( .A(n4929), .B(n4926), .Y(n4899) );
NAND2X1TS U3187 ( .A(n5070), .B(n5069), .Y(n5073) );
NAND2X1TS U3188 ( .A(n5068), .B(n5067), .Y(n5072) );
INVX2TS U3189 ( .A(n4688), .Y(n4561) );
AND3X1TS U3190 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .C(FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
n4449) );
NOR2XLTS U3191 ( .A(n4023), .B(n4026), .Y(n4028) );
OAI21XLTS U3192 ( .A0(n4026), .A1(n4025), .B0(n4024), .Y(n4027) );
INVX2TS U3193 ( .A(n4035), .Y(n4077) );
CLKAND2X2TS U3194 ( .A(n5936), .B(FPADDSUB_DMP_SFG[9]), .Y(n5131) );
CMPR42X1TS U3195 ( .A(mult_x_254_n226), .B(mult_x_254_n229), .C(
mult_x_254_n227), .D(mult_x_254_n223), .ICI(mult_x_254_n219), .S(
mult_x_254_n216), .ICO(mult_x_254_n214), .CO(mult_x_254_n215) );
CMPR42X1TS U3196 ( .A(mult_x_254_n237), .B(mult_x_254_n234), .C(
mult_x_254_n231), .D(mult_x_254_n235), .ICI(mult_x_254_n228), .S(
mult_x_254_n225), .ICO(mult_x_254_n223), .CO(mult_x_254_n224) );
INVX4TS U3197 ( .A(n2715), .Y(n2341) );
AOI21X2TS U3198 ( .A0(n3568), .A1(n3567), .B0(n3566), .Y(n3590) );
NAND2X1TS U3199 ( .A(n3596), .B(n3615), .Y(n3575) );
NOR2X2TS U3200 ( .A(n2696), .B(n2700), .Y(n2703) );
CMPR42X1TS U3201 ( .A(mult_x_219_n227), .B(mult_x_219_n219), .C(
mult_x_219_n225), .D(mult_x_219_n217), .ICI(mult_x_219_n221), .S(
mult_x_219_n214), .ICO(mult_x_219_n212), .CO(mult_x_219_n213) );
NAND2BXLTS U3202 ( .AN(n2444), .B(FPMULT_Op_MX[15]), .Y(n2646) );
BUFX3TS U3203 ( .A(n3284), .Y(n3323) );
NAND2X1TS U3204 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n4476), .Y(n4144) );
OAI21X1TS U3205 ( .A0(n5278), .A1(n5272), .B0(n5273), .Y(n5268) );
OAI2BB1X1TS U3206 ( .A0N(n2771), .A1N(n2770), .B0(n2769), .Y(n2788) );
INVX2TS U3207 ( .A(n2768), .Y(n2769) );
NAND2BX1TS U3208 ( .AN(n2749), .B(n2748), .Y(n2771) );
OAI221XLTS U3209 ( .A0(n5852), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n2264),
.B1(FPADDSUB_intDY_EWSW[11]), .C0(n5752), .Y(n5753) );
CLKBUFX2TS U3210 ( .A(n2400), .Y(n5105) );
NOR2X1TS U3211 ( .A(n4855), .B(n4723), .Y(n4842) );
INVX2TS U3212 ( .A(n4226), .Y(n5499) );
OAI21XLTS U3213 ( .A0(n5314), .A1(n4023), .B0(n4025), .Y(n4017) );
OAI21XLTS U3214 ( .A0(n4046), .A1(n4045), .B0(n4044), .Y(n4048) );
OAI21XLTS U3215 ( .A0(n4071), .A1(n5118), .B0(n5121), .Y(n4074) );
OAI21XLTS U3216 ( .A0(n5347), .A1(n5300), .B0(n5299), .Y(n5304) );
OR2X1TS U3217 ( .A(n2691), .B(n2690), .Y(n2693) );
MX2X1TS U3218 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
OAI21XLTS U3219 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n4101), .B0(n4707), .Y(
n4102) );
MX2X1TS U3220 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
NAND3XLTS U3221 ( .A(n5009), .B(FPMULT_P_Sgf[47]), .C(n4115), .Y(n4116) );
INVX2TS U3222 ( .A(n5284), .Y(n5285) );
INVX2TS U3223 ( .A(n5283), .Y(n5286) );
NAND2X2TS U3224 ( .A(n4560), .B(n5639), .Y(n4694) );
INVX2TS U3225 ( .A(n4625), .Y(n2315) );
INVX2TS U3226 ( .A(n5330), .Y(n5332) );
INVX2TS U3227 ( .A(n5272), .Y(n5274) );
OAI21X2TS U3228 ( .A0(n3144), .A1(n3140), .B0(n3141), .Y(n3139) );
NAND2X1TS U3229 ( .A(DP_OP_454J16_123_2743_n366), .B(n2616), .Y(n3365) );
NAND2X1TS U3230 ( .A(n2447), .B(n5071), .Y(n5020) );
INVX2TS U3231 ( .A(n2299), .Y(n2300) );
BUFX3TS U3232 ( .A(n4569), .Y(n4608) );
INVX2TS U3233 ( .A(FPSENCOS_d_ff_Yn[31]), .Y(n5585) );
BUFX3TS U3234 ( .A(n5654), .Y(n5644) );
MX2X1TS U3235 ( .A(Data_1[15]), .B(FPMULT_Op_MX[15]), .S0(n2320), .Y(n1673)
);
MX2X1TS U3236 ( .A(Data_1[22]), .B(FPMULT_Op_MX[22]), .S0(n2320), .Y(n1680)
);
MX2X1TS U3237 ( .A(Data_1[17]), .B(FPMULT_Op_MX[17]), .S0(n5013), .Y(n1675)
);
MX2X1TS U3238 ( .A(Data_1[9]), .B(n2282), .S0(n4714), .Y(n1667) );
MX2X1TS U3239 ( .A(Data_2[1]), .B(FPMULT_Op_MY[1]), .S0(n4717), .Y(n1627) );
MX2X1TS U3240 ( .A(Data_2[19]), .B(n2415), .S0(n5013), .Y(n1645) );
MX2X1TS U3241 ( .A(Data_2[15]), .B(n2289), .S0(n4716), .Y(n1641) );
MX2X1TS U3242 ( .A(Data_1[8]), .B(n2281), .S0(n4714), .Y(n1666) );
MX2X1TS U3243 ( .A(Data_1[7]), .B(n2280), .S0(n4714), .Y(n1665) );
MX2X1TS U3244 ( .A(Data_1[19]), .B(FPMULT_Op_MX[19]), .S0(n2320), .Y(n1677)
);
MX2X1TS U3245 ( .A(Data_2[13]), .B(FPMULT_Op_MY[13]), .S0(n4716), .Y(n1639)
);
AOI32X1TS U3246 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n5639), .A2(
n5480), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n4679), .Y(n4170)
);
MX2X1TS U3247 ( .A(FPMULT_P_Sgf[11]), .B(FPMULT_Sgf_operation_Result[11]),
.S0(n5427), .Y(n1540) );
MX2X1TS U3248 ( .A(FPMULT_P_Sgf[7]), .B(FPMULT_Sgf_operation_Result[7]),
.S0(n5426), .Y(n1536) );
MX2X1TS U3249 ( .A(FPMULT_P_Sgf[4]), .B(FPMULT_Sgf_operation_Result[4]),
.S0(n5424), .Y(n1533) );
MX2X1TS U3250 ( .A(FPMULT_P_Sgf[16]), .B(n5378), .S0(n5424), .Y(n1545) );
MX2X1TS U3251 ( .A(FPMULT_P_Sgf[21]), .B(n5406), .S0(n5424), .Y(n1550) );
MX2X1TS U3252 ( .A(FPMULT_P_Sgf[5]), .B(FPMULT_Sgf_operation_Result[5]),
.S0(n5424), .Y(n1534) );
MX2X1TS U3253 ( .A(FPMULT_P_Sgf[17]), .B(n5367), .S0(n5427), .Y(n1546) );
MX2X1TS U3254 ( .A(FPMULT_P_Sgf[18]), .B(n5396), .S0(n5424), .Y(n1547) );
MX2X1TS U3255 ( .A(FPMULT_P_Sgf[3]), .B(FPMULT_Sgf_operation_Result[3]),
.S0(n5424), .Y(n1532) );
MX2X1TS U3256 ( .A(FPMULT_P_Sgf[15]), .B(n5371), .S0(n5427), .Y(n1544) );
MX2X1TS U3257 ( .A(FPMULT_P_Sgf[19]), .B(n5400), .S0(n5424), .Y(n1548) );
AOI2BB2XLTS U3258 ( .B0(n5485), .B1(n5856), .A0N(n5856), .A1N(n5485), .Y(
n2137) );
AO22XLTS U3259 ( .A0(n5656), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n5655), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1732) );
AO22XLTS U3260 ( .A0(n5658), .A1(result_add_subt[30]), .B0(n5657), .B1(
FPSENCOS_d_ff_Yn[30]), .Y(n1730) );
AO22XLTS U3261 ( .A0(n5658), .A1(result_add_subt[29]), .B0(n5657), .B1(
FPSENCOS_d_ff_Yn[29]), .Y(n1767) );
AO22XLTS U3262 ( .A0(n5658), .A1(result_add_subt[25]), .B0(n5515), .B1(
FPSENCOS_d_ff_Yn[25]), .Y(n1779) );
AO22XLTS U3263 ( .A0(n5658), .A1(result_add_subt[23]), .B0(n5519), .B1(
FPSENCOS_d_ff_Yn[23]), .Y(n1785) );
MX2X1TS U3264 ( .A(FPMULT_P_Sgf[24]), .B(n4984), .S0(n5427), .Y(n1553) );
MX2X1TS U3265 ( .A(FPMULT_P_Sgf[25]), .B(n4973), .S0(n5427), .Y(n1554) );
MX2X1TS U3266 ( .A(FPMULT_P_Sgf[27]), .B(n4944), .S0(n4962), .Y(n1556) );
MX2X1TS U3267 ( .A(FPMULT_P_Sgf[28]), .B(n4934), .S0(n4962), .Y(n1557) );
MX2X1TS U3268 ( .A(FPMULT_P_Sgf[29]), .B(n4920), .S0(n4962), .Y(n1558) );
MX2X1TS U3269 ( .A(FPMULT_P_Sgf[30]), .B(n4910), .S0(n4962), .Y(n1559) );
MX2X1TS U3270 ( .A(FPMULT_P_Sgf[31]), .B(n4888), .S0(n4962), .Y(n1560) );
MX2X1TS U3271 ( .A(FPMULT_P_Sgf[32]), .B(n4878), .S0(n4962), .Y(n1561) );
MX2X1TS U3272 ( .A(FPMULT_P_Sgf[34]), .B(n4851), .S0(n4962), .Y(n1563) );
MX2X1TS U3273 ( .A(FPMULT_P_Sgf[35]), .B(n4838), .S0(n4962), .Y(n1564) );
MX2X1TS U3274 ( .A(FPMULT_P_Sgf[36]), .B(n4827), .S0(n4826), .Y(n1565) );
MX2X1TS U3275 ( .A(FPMULT_P_Sgf[39]), .B(n4789), .S0(n4826), .Y(n1568) );
MX2X1TS U3276 ( .A(FPMULT_P_Sgf[40]), .B(n4777), .S0(n4826), .Y(n1569) );
MX2X1TS U3277 ( .A(FPMULT_P_Sgf[41]), .B(n4768), .S0(n4826), .Y(n1570) );
MX2X1TS U3278 ( .A(FPMULT_P_Sgf[42]), .B(n4760), .S0(n4826), .Y(n1571) );
MX2X1TS U3279 ( .A(FPMULT_P_Sgf[43]), .B(n4752), .S0(n4826), .Y(n1572) );
AO22XLTS U3280 ( .A0(n5667), .A1(result_add_subt[30]), .B0(n5659), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(n1729) );
AO22XLTS U3281 ( .A0(n5667), .A1(result_add_subt[23]), .B0(n5520), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(n1784) );
MX2X1TS U3282 ( .A(FPMULT_P_Sgf[45]), .B(n4734), .S0(n4826), .Y(n1574) );
AO22XLTS U3283 ( .A0(n5667), .A1(result_add_subt[29]), .B0(n5659), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(n1766) );
AO22XLTS U3284 ( .A0(n5667), .A1(result_add_subt[25]), .B0(n5516), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(n1778) );
MX2X1TS U3285 ( .A(Data_2[28]), .B(FPMULT_Op_MY[28]), .S0(n5691), .Y(n1654)
);
MX2X1TS U3286 ( .A(Data_2[24]), .B(FPMULT_Op_MY[24]), .S0(n4717), .Y(n1650)
);
MX2X1TS U3287 ( .A(Data_2[26]), .B(FPMULT_Op_MY[26]), .S0(n5014), .Y(n1652)
);
MX2X1TS U3288 ( .A(FPMULT_Exp_module_Data_S[1]), .B(
FPMULT_exp_oper_result[1]), .S0(n4070), .Y(n1593) );
MX2X1TS U3289 ( .A(FPMULT_Exp_module_Data_S[4]), .B(
FPMULT_exp_oper_result[4]), .S0(n4070), .Y(n1590) );
MX2X1TS U3290 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_exp_oper_result[6]), .S0(n4070), .Y(n1588) );
MX2X1TS U3291 ( .A(Data_2[29]), .B(FPMULT_Op_MY[29]), .S0(n4717), .Y(n1655)
);
MX2X1TS U3292 ( .A(Data_2[25]), .B(FPMULT_Op_MY[25]), .S0(n4717), .Y(n1651)
);
MX2X1TS U3293 ( .A(n4731), .B(FPMULT_Add_result[22]), .S0(n4773), .Y(n1598)
);
MX2X1TS U3294 ( .A(n4743), .B(FPMULT_Add_result[21]), .S0(n4773), .Y(n1599)
);
MX2X1TS U3295 ( .A(n4749), .B(FPMULT_Add_result[20]), .S0(n4773), .Y(n1600)
);
MX2X1TS U3296 ( .A(n4757), .B(FPMULT_Add_result[19]), .S0(n4773), .Y(n1601)
);
MX2X1TS U3297 ( .A(n4765), .B(FPMULT_Add_result[18]), .S0(n4773), .Y(n1602)
);
MX2X1TS U3298 ( .A(n4774), .B(FPMULT_Add_result[17]), .S0(n4773), .Y(n1603)
);
MX2X1TS U3299 ( .A(n4783), .B(FPMULT_Add_result[16]), .S0(n5001), .Y(n1604)
);
MX2X1TS U3300 ( .A(n4794), .B(FPMULT_Add_result[15]), .S0(n5001), .Y(n1605)
);
MX2X1TS U3301 ( .A(n4808), .B(FPMULT_Add_result[14]), .S0(n5001), .Y(n1606)
);
MX2X1TS U3302 ( .A(n4819), .B(FPMULT_Add_result[13]), .S0(n5001), .Y(n1607)
);
MX2X1TS U3303 ( .A(n4832), .B(FPMULT_Add_result[12]), .S0(n5001), .Y(n1608)
);
MX2X1TS U3304 ( .A(n4843), .B(FPMULT_Add_result[11]), .S0(n5001), .Y(n1609)
);
MX2X1TS U3305 ( .A(n4858), .B(FPMULT_Add_result[10]), .S0(n5001), .Y(n1610)
);
MX2X1TS U3306 ( .A(n4870), .B(FPMULT_Add_result[9]), .S0(n5001), .Y(n1611)
);
MX2X1TS U3307 ( .A(n4883), .B(FPMULT_Add_result[8]), .S0(n5001), .Y(n1612)
);
MX2X1TS U3308 ( .A(n4950), .B(FPMULT_Add_result[3]), .S0(n4977), .Y(n1617)
);
INVX2TS U3309 ( .A(n4967), .Y(n4948) );
MX2X1TS U3310 ( .A(n4978), .B(FPMULT_Add_result[1]), .S0(n4977), .Y(n1619)
);
MX2X1TS U3311 ( .A(Data_1[25]), .B(FPMULT_Op_MX[25]), .S0(n5691), .Y(n1683)
);
MX2X1TS U3312 ( .A(FPMULT_P_Sgf[6]), .B(FPMULT_Sgf_operation_Result[6]),
.S0(n5426), .Y(n1535) );
MX2X1TS U3313 ( .A(FPMULT_P_Sgf[8]), .B(FPMULT_Sgf_operation_Result[8]),
.S0(n5426), .Y(n1537) );
OAI21XLTS U3314 ( .A0(n5639), .A1(n2267), .B0(n4648), .Y(n2079) );
MX2X1TS U3315 ( .A(Data_1[23]), .B(FPMULT_Op_MX[23]), .S0(n5014), .Y(n1681)
);
MX2X1TS U3316 ( .A(Data_1[26]), .B(FPMULT_Op_MX[26]), .S0(n4717), .Y(n1684)
);
MX2X1TS U3317 ( .A(Data_1[28]), .B(FPMULT_Op_MX[28]), .S0(n5013), .Y(n1686)
);
MX2X1TS U3318 ( .A(Data_1[30]), .B(FPMULT_Op_MX[30]), .S0(n2319), .Y(n1688)
);
AOI32X1TS U3319 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n5639), .A2(
n5480), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n4679), .Y(n4134)
);
MX2X1TS U3320 ( .A(Data_2[12]), .B(FPMULT_Op_MY[12]), .S0(n5013), .Y(n1638)
);
AOI222X1TS U3321 ( .A0(n4297), .A1(cordic_result[23]), .B0(n4310), .B1(
FPSENCOS_d_ff_Yn[23]), .C0(n4309), .C1(FPSENCOS_d_ff_Xn[23]), .Y(n4296) );
AOI222X1TS U3322 ( .A0(n4311), .A1(cordic_result[25]), .B0(n4310), .B1(
FPSENCOS_d_ff_Yn[25]), .C0(n4309), .C1(FPSENCOS_d_ff_Xn[25]), .Y(n4300) );
AOI222X1TS U3323 ( .A0(n4311), .A1(cordic_result[29]), .B0(n4310), .B1(
FPSENCOS_d_ff_Yn[29]), .C0(n4309), .C1(FPSENCOS_d_ff_Xn[29]), .Y(n4306) );
AOI222X1TS U3324 ( .A0(n4311), .A1(cordic_result[30]), .B0(n4310), .B1(
FPSENCOS_d_ff_Yn[30]), .C0(n4276), .C1(FPSENCOS_d_ff_Xn[30]), .Y(n4277) );
AOI222X1TS U3325 ( .A0(n4297), .A1(cordic_result[14]), .B0(n4302), .B1(
FPSENCOS_d_ff_Yn[14]), .C0(n4276), .C1(FPSENCOS_d_ff_Xn[14]), .Y(n4291) );
AOI222X1TS U3326 ( .A0(n4297), .A1(cordic_result[20]), .B0(n4302), .B1(
FPSENCOS_d_ff_Yn[20]), .C0(n4309), .C1(FPSENCOS_d_ff_Xn[20]), .Y(n4298) );
MX2X1TS U3327 ( .A(FPMULT_P_Sgf[20]), .B(n5387), .S0(n5424), .Y(n1549) );
MX2X1TS U3328 ( .A(FPMULT_P_Sgf[13]), .B(n5363), .S0(n5427), .Y(n1542) );
MX2X1TS U3329 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_Sgf_operation_Result[1]),
.S0(n5427), .Y(n1530) );
MX2X1TS U3330 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n5017), .Y(n1453) );
MX2X1TS U3331 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n5017), .Y(n1443) );
MX2X1TS U3332 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n5017), .Y(n1433) );
MX2X1TS U3333 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n5017), .Y(n1423) );
MX2X1TS U3334 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(n5017), .Y(n1438) );
MX2X1TS U3335 ( .A(Data_2[23]), .B(FPMULT_Op_MY[23]), .S0(n5014), .Y(n1649)
);
MX2X1TS U3336 ( .A(FPMULT_Exp_module_Data_S[0]), .B(
FPMULT_exp_oper_result[0]), .S0(n4070), .Y(n1594) );
MX2X1TS U3337 ( .A(FPMULT_Exp_module_Data_S[2]), .B(
FPMULT_exp_oper_result[2]), .S0(n4070), .Y(n1592) );
MX2X1TS U3338 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_exp_oper_result[3]), .S0(n4070), .Y(n1591) );
MX2X1TS U3339 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_exp_oper_result[5]), .S0(n4070), .Y(n1589) );
MX2X1TS U3340 ( .A(Data_2[27]), .B(FPMULT_Op_MY[27]), .S0(n5014), .Y(n1653)
);
MX2X1TS U3341 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n4717), .Y(n1682)
);
MX2X1TS U3342 ( .A(Data_2[30]), .B(FPMULT_Op_MY[30]), .S0(n5691), .Y(n1656)
);
MX2X1TS U3343 ( .A(FPADDSUB_OP_FLAG_SFG), .B(FPADDSUB_OP_FLAG_SHT2), .S0(
n5721), .Y(n1352) );
MX2X1TS U3344 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n5013), .Y(n1685)
);
MX2X1TS U3345 ( .A(n4895), .B(FPMULT_Add_result[7]), .S0(n4977), .Y(n1613)
);
MX2X1TS U3346 ( .A(n4915), .B(FPMULT_Add_result[6]), .S0(n4977), .Y(n1614)
);
MX2X1TS U3347 ( .A(n4925), .B(FPMULT_Add_result[5]), .S0(n4977), .Y(n1615)
);
MX2X1TS U3348 ( .A(n4939), .B(FPMULT_Add_result[4]), .S0(n4977), .Y(n1616)
);
MX2X1TS U3349 ( .A(n4968), .B(FPMULT_Add_result[2]), .S0(n4977), .Y(n1618)
);
MX2X1TS U3350 ( .A(Data_1[29]), .B(FPMULT_Op_MX[29]), .S0(n2319), .Y(n1687)
);
MX2X1TS U3351 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n5017), .Y(n1448) );
MX2X1TS U3352 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(n5017), .Y(n1428) );
MX2X1TS U3353 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n5017), .Y(n1418) );
XOR2XLTS U3354 ( .A(n4034), .B(n4033), .Y(n4039) );
MX2X1TS U3355 ( .A(Data_2[20]), .B(n2448), .S0(n2320), .Y(n1646) );
XOR2XLTS U3356 ( .A(n5314), .B(n5313), .Y(n5319) );
OAI211XLTS U3357 ( .A0(n4367), .A1(n5943), .B0(n4344), .C0(n4343), .Y(n1916)
);
MX2X1TS U3358 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DMP_SHT2_EWSW[22]),
.S0(n5716), .Y(n1206) );
MX2X1TS U3359 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DMP_SHT2_EWSW[12]),
.S0(n5018), .Y(n1266) );
MX2X1TS U3360 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DMP_SHT2_EWSW[20]),
.S0(n5716), .Y(n1226) );
MX2X1TS U3361 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DMP_SHT2_EWSW[14]),
.S0(n5018), .Y(n1258) );
MX2X1TS U3362 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DMP_SHT2_EWSW[16]),
.S0(n5716), .Y(n1246) );
MX2X1TS U3363 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DMP_SHT2_EWSW[18]),
.S0(n5716), .Y(n1214) );
MX2X1TS U3364 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DMP_SHT2_EWSW[13]),
.S0(n5716), .Y(n1242) );
MX2X1TS U3365 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DMP_SHT2_EWSW[17]),
.S0(n5018), .Y(n1230) );
MX2X1TS U3366 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DMP_SHT2_EWSW[21]),
.S0(n5716), .Y(n1218) );
XOR2XLTS U3367 ( .A(n5325), .B(n5324), .Y(n5327) );
MX2X1TS U3368 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DMP_SHT2_EWSW[11]),
.S0(n5019), .Y(n1254) );
MX2X1TS U3369 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DMP_SHT2_EWSW[19]),
.S0(n5716), .Y(n1222) );
MX2X1TS U3370 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DMP_SHT2_EWSW[15]),
.S0(n5721), .Y(n1210) );
MX2X1TS U3371 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DMP_SHT2_EWSW[10]),
.S0(n5019), .Y(n1262) );
XOR2XLTS U3372 ( .A(n4071), .B(n4061), .Y(n4069) );
OAI211XLTS U3373 ( .A0(n4367), .A1(n2252), .B0(n4361), .C0(n4360), .Y(n1918)
);
AOI32X1TS U3374 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n5639), .A2(
n5478), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n4679), .Y(n4149)
);
OAI31X1TS U3375 ( .A0(n5485), .A1(FPSENCOS_cont_var_out[1]), .A2(n5856),
.B0(n4701), .Y(n2136) );
MX2X1TS U3376 ( .A(Data_1[1]), .B(n5681), .S0(n5013), .Y(n1659) );
XOR2XLTS U3377 ( .A(n3232), .B(n3231), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N4) );
MX2X1TS U3378 ( .A(Data_2[0]), .B(FPMULT_Op_MY[0]), .S0(n2319), .Y(n1626) );
MX2X1TS U3379 ( .A(Data_1[0]), .B(FPMULT_Op_MX[0]), .S0(n2319), .Y(n1658) );
MX2X1TS U3380 ( .A(Data_2[8]), .B(FPMULT_Op_MY[8]), .S0(n5014), .Y(n1634) );
MX2X1TS U3381 ( .A(Data_2[9]), .B(n2329), .S0(n5691), .Y(n1635) );
MX2X1TS U3382 ( .A(Data_2[11]), .B(FPMULT_Op_MY[11]), .S0(n5014), .Y(n1637)
);
MX2X1TS U3383 ( .A(Data_2[18]), .B(FPMULT_Op_MY[18]), .S0(n5013), .Y(n1644)
);
MX2X1TS U3384 ( .A(Data_2[22]), .B(n4718), .S0(n2319), .Y(n1648) );
MX2X1TS U3385 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DMP_SHT2_EWSW[2]), .S0(
n5019), .Y(n1307) );
MX2X1TS U3386 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DMP_SHT2_EWSW[3]), .S0(
n5019), .Y(n1323) );
MX2X1TS U3387 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DMP_SHT2_EWSW[4]), .S0(
n5019), .Y(n1234) );
MX2X1TS U3388 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DMP_SHT2_EWSW[5]), .S0(
n5019), .Y(n1272) );
MX2X1TS U3389 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DMP_SHT2_EWSW[6]), .S0(
n5019), .Y(n1238) );
MX2X1TS U3390 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DMP_SHT2_EWSW[7]), .S0(
n5019), .Y(n1300) );
MX2X1TS U3391 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DMP_SHT2_EWSW[8]), .S0(
n5019), .Y(n1250) );
MX2X1TS U3392 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DMP_SHT2_EWSW[9]), .S0(
n5019), .Y(n1279) );
MX2X1TS U3393 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DMP_SHT2_EWSW[0]), .S0(
n5721), .Y(n1293) );
MX2X1TS U3394 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DMP_SHT2_EWSW[1]), .S0(
n5721), .Y(n1286) );
AO21XLTS U3395 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n5480), .B0(n5109),
.Y(n1314) );
MX2X1TS U3396 ( .A(Data_2[21]), .B(FPMULT_Op_MY[21]), .S0(n4716), .Y(n1647)
);
MX2X1TS U3397 ( .A(Data_2[10]), .B(FPMULT_Op_MY[10]), .S0(n4717), .Y(n1636)
);
AO21XLTS U3398 ( .A0(n5483), .A1(n4091), .B0(n4090), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
NAND2BXLTS U3399 ( .AN(FPMULT_zero_flag), .B(n2419), .Y(n5011) );
XOR2XLTS U3400 ( .A(n5821), .B(n4175), .Y(n2138) );
NAND4XLTS U3401 ( .A(n6075), .B(n6074), .C(n6073), .D(n5447), .Y(n5449) );
OAI21XLTS U3402 ( .A0(n5017), .A1(n2211), .B0(n4648), .Y(n1350) );
OAI32X1TS U3403 ( .A0(n5484), .A1(n5482), .A2(n2284), .B0(n5844), .B1(n5484),
.Y(n2140) );
XOR2XLTS U3404 ( .A(n5276), .B(n5275), .Y(n5281) );
AOI2BB2XLTS U3405 ( .B0(n5907), .B1(n5527), .A0N(FPSENCOS_d_ff_Xn[28]),
.A1N(n5584), .Y(n1954) );
CLKAND2X2TS U3406 ( .A(n3063), .B(n3062), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N1) );
AOI21X2TS U3407 ( .A0(n3643), .A1(n2533), .B0(n2532), .Y(n3587) );
OR2X1TS U3408 ( .A(n3583), .B(n3582), .Y(n3585) );
INVX2TS U3409 ( .A(n3376), .Y(n3378) );
CLKAND2X2TS U3410 ( .A(n3512), .B(n3511), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N1) );
OR2X1TS U3411 ( .A(n3510), .B(n3509), .Y(n3512) );
XOR2XLTS U3412 ( .A(n3239), .B(n3287), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N2) );
AO22XLTS U3413 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n5962),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1207) );
AO22XLTS U3414 ( .A0(n5806), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n5812),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1208) );
OAI21XLTS U3415 ( .A0(n2225), .A1(n4526), .B0(n4516), .Y(n1209) );
AO22XLTS U3416 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n5962),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1211) );
AO22XLTS U3417 ( .A0(n5803), .A1(FPADDSUB_DMP_EXP_EWSW[15]), .B0(n2272),
.B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1212) );
AO22XLTS U3418 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n5811),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1215) );
AO22XLTS U3419 ( .A0(n5794), .A1(FPADDSUB_DMP_EXP_EWSW[18]), .B0(n2272),
.B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1216) );
AO22XLTS U3420 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n5962),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1219) );
AO22XLTS U3421 ( .A0(n5741), .A1(FPADDSUB_DMP_EXP_EWSW[21]), .B0(n2272),
.B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1220) );
AO22XLTS U3422 ( .A0(n5810), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n5962),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1223) );
AO22XLTS U3423 ( .A0(n5813), .A1(FPADDSUB_DMP_EXP_EWSW[19]), .B0(n5809),
.B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1224) );
OAI21XLTS U3424 ( .A0(n2260), .A1(n4526), .B0(n4519), .Y(n1225) );
AO22XLTS U3425 ( .A0(n5810), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n5811),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1227) );
AO22XLTS U3426 ( .A0(n5794), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n5809),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1228) );
OAI21XLTS U3427 ( .A0(n5851), .A1(n4526), .B0(n4512), .Y(n1229) );
AO22XLTS U3428 ( .A0(n5810), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n5962),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1231) );
AO22XLTS U3429 ( .A0(n5803), .A1(FPADDSUB_DMP_EXP_EWSW[17]), .B0(n5809),
.B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1232) );
AO22XLTS U3430 ( .A0(n5714), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(
FPADDSUB_DMP_SHT2_EWSW[4]), .B1(n5804), .Y(n5954) );
AO22XLTS U3431 ( .A0(n5806), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n5809), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1236) );
AO22XLTS U3432 ( .A0(n5714), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(
FPADDSUB_DMP_SHT2_EWSW[6]), .B1(n5804), .Y(n5955) );
AO22XLTS U3433 ( .A0(n5803), .A1(FPADDSUB_DMP_EXP_EWSW[6]), .B0(n5809), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1240) );
OAI21XLTS U3434 ( .A0(n2738), .A1(n4526), .B0(n4525), .Y(n1241) );
AO22XLTS U3435 ( .A0(n5810), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n5962),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1243) );
AO22XLTS U3436 ( .A0(n5806), .A1(FPADDSUB_DMP_EXP_EWSW[13]), .B0(n5809),
.B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1244) );
AO22XLTS U3437 ( .A0(n5810), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n5807),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1247) );
AO22XLTS U3438 ( .A0(n5794), .A1(FPADDSUB_DMP_EXP_EWSW[16]), .B0(n5809),
.B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1248) );
AO22XLTS U3439 ( .A0(n5810), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n5962),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1251) );
AO22XLTS U3440 ( .A0(n5794), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n5809), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1252) );
AO22XLTS U3441 ( .A0(n5810), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n5962),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1255) );
AO22XLTS U3442 ( .A0(n5808), .A1(FPADDSUB_DMP_EXP_EWSW[11]), .B0(n5809),
.B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1256) );
AO22XLTS U3443 ( .A0(n5810), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n5807),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1259) );
AO22XLTS U3444 ( .A0(n5808), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n5809),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1260) );
AO22XLTS U3445 ( .A0(n5810), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n5804),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1263) );
AO22XLTS U3446 ( .A0(n5741), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n5805),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1264) );
AO22XLTS U3447 ( .A0(n5810), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n5804),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1267) );
AO22XLTS U3448 ( .A0(n5808), .A1(FPADDSUB_DMP_EXP_EWSW[12]), .B0(n5805),
.B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1268) );
AO22XLTS U3449 ( .A0(n5806), .A1(FPADDSUB_DmP_EXP_EWSW[12]), .B0(n5805),
.B1(FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n1270) );
AO22XLTS U3450 ( .A0(n5714), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(
FPADDSUB_DMP_SHT2_EWSW[5]), .B1(n5804), .Y(n5956) );
AO22XLTS U3451 ( .A0(n5803), .A1(FPADDSUB_DMP_EXP_EWSW[5]), .B0(n5805), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1274) );
AO22XLTS U3452 ( .A0(n5803), .A1(FPADDSUB_DmP_EXP_EWSW[5]), .B0(n5805), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1276) );
AO22XLTS U3453 ( .A0(n6077), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n5962),
.B1(FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1280) );
AO22XLTS U3454 ( .A0(n5808), .A1(FPADDSUB_DMP_EXP_EWSW[9]), .B0(n5805), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1281) );
AO22XLTS U3455 ( .A0(n5741), .A1(FPADDSUB_DmP_EXP_EWSW[9]), .B0(n5805), .B1(
FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n1283) );
AO22XLTS U3456 ( .A0(n5714), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(
FPADDSUB_DMP_SHT2_EWSW[1]), .B1(n5811), .Y(n5957) );
AO22XLTS U3457 ( .A0(n5803), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n5805), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1288) );
OAI21XLTS U3458 ( .A0(n2263), .A1(n4556), .B0(n4547), .Y(n1289) );
AO22XLTS U3459 ( .A0(n5741), .A1(FPADDSUB_DmP_EXP_EWSW[1]), .B0(n5805), .B1(
FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n1290) );
AO22XLTS U3460 ( .A0(n5714), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(
FPADDSUB_DMP_SHT2_EWSW[0]), .B1(n5811), .Y(n5958) );
AO22XLTS U3461 ( .A0(n5813), .A1(FPADDSUB_DMP_EXP_EWSW[0]), .B0(n5805), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1295) );
OAI21XLTS U3462 ( .A0(n2266), .A1(n4556), .B0(n4550), .Y(n1296) );
AO22XLTS U3463 ( .A0(n5794), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n5812), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1297) );
AO22XLTS U3464 ( .A0(n5714), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(
FPADDSUB_DMP_SHT2_EWSW[7]), .B1(n5804), .Y(n5959) );
AO22XLTS U3465 ( .A0(n5813), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n5812), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1302) );
OAI21XLTS U3466 ( .A0(n5828), .A1(n4538), .B0(n4497), .Y(n1303) );
AO22XLTS U3467 ( .A0(n5803), .A1(FPADDSUB_DmP_EXP_EWSW[7]), .B0(n5812), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1304) );
OAI21XLTS U3468 ( .A0(n5865), .A1(n4538), .B0(n4500), .Y(n1305) );
AO22XLTS U3469 ( .A0(n5714), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(
FPADDSUB_DMP_SHT2_EWSW[2]), .B1(n5811), .Y(n5960) );
AO22XLTS U3470 ( .A0(n5806), .A1(FPADDSUB_DMP_EXP_EWSW[2]), .B0(n5812), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1309) );
OAI21XLTS U3471 ( .A0(n2261), .A1(n4556), .B0(n4555), .Y(n1310) );
AO22XLTS U3472 ( .A0(n5813), .A1(FPADDSUB_DmP_EXP_EWSW[2]), .B0(n5812), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1311) );
XOR2XLTS U3473 ( .A(n5208), .B(n5207), .Y(n5213) );
XOR2XLTS U3474 ( .A(n5246), .B(n5245), .Y(n5251) );
XOR2XLTS U3475 ( .A(n5227), .B(n5226), .Y(n5232) );
AO22XLTS U3476 ( .A0(n5714), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(
FPADDSUB_DMP_SHT2_EWSW[3]), .B1(n5811), .Y(n5961) );
AO22XLTS U3477 ( .A0(n5803), .A1(FPADDSUB_DMP_EXP_EWSW[3]), .B0(n5812), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1325) );
OAI21XLTS U3478 ( .A0(n2466), .A1(n4556), .B0(n4549), .Y(n1326) );
AO22XLTS U3479 ( .A0(n5813), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n5812), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1327) );
OAI21XLTS U3480 ( .A0(n2466), .A1(n4538), .B0(n4528), .Y(n1328) );
XOR2XLTS U3481 ( .A(n5175), .B(n5167), .Y(n5172) );
XOR2XLTS U3482 ( .A(n5152), .B(n5144), .Y(n5149) );
XOR2XLTS U3483 ( .A(n5347), .B(n5346), .Y(n5357) );
AO22XLTS U3484 ( .A0(n6077), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n5807), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1353) );
AO22XLTS U3485 ( .A0(n5794), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n5812), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1354) );
AO22XLTS U3486 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_6), .A1(n5791), .B0(n5790),
.B1(FPADDSUB_OP_FLAG_EXP), .Y(n1355) );
AOI2BB2XLTS U3487 ( .B0(FPADDSUB_intDX_EWSW[31]), .B1(n5789), .A0N(n5789),
.A1N(FPADDSUB_intDX_EWSW[31]), .Y(n5791) );
INVX2TS U3488 ( .A(n5726), .Y(n4455) );
AO22XLTS U3489 ( .A0(n2300), .A1(FPADDSUB_SIGN_FLAG_NRM), .B0(n4600), .B1(
FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n1357) );
AO22XLTS U3490 ( .A0(n5788), .A1(FPADDSUB_SIGN_FLAG_SFG), .B0(n2304), .B1(
FPADDSUB_SIGN_FLAG_NRM), .Y(n1358) );
AO22XLTS U3491 ( .A0(n5018), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n5787), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1359) );
AO22XLTS U3492 ( .A0(n6077), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n5807), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1360) );
AO22XLTS U3493 ( .A0(n5741), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n5812), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1361) );
AOI31XLTS U3494 ( .A0(n5783), .A1(n5782), .A2(n5781), .B0(n5784), .Y(n5785)
);
AO22XLTS U3495 ( .A0(n5806), .A1(FPADDSUB_DmP_EXP_EWSW[10]), .B0(n5747),
.B1(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1364) );
OAI21XLTS U3496 ( .A0(n2745), .A1(n4538), .B0(n4537), .Y(n1365) );
AO22XLTS U3497 ( .A0(n5741), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n5747),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1367) );
AO22XLTS U3498 ( .A0(n5741), .A1(FPADDSUB_DmP_EXP_EWSW[11]), .B0(n5747),
.B1(FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1370) );
AO22XLTS U3499 ( .A0(n5808), .A1(FPADDSUB_DmP_EXP_EWSW[8]), .B0(n5747), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1373) );
AO22XLTS U3500 ( .A0(n5741), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n5747),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1376) );
AO22XLTS U3501 ( .A0(n5813), .A1(FPADDSUB_DmP_EXP_EWSW[13]), .B0(n5747),
.B1(FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1379) );
AO22XLTS U3502 ( .A0(n5794), .A1(FPADDSUB_DmP_EXP_EWSW[6]), .B0(n5747), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1382) );
AO22XLTS U3503 ( .A0(n5794), .A1(FPADDSUB_DmP_EXP_EWSW[4]), .B0(n5747), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1385) );
AO22XLTS U3504 ( .A0(n5808), .A1(FPADDSUB_DmP_EXP_EWSW[17]), .B0(n5747),
.B1(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1388) );
OAI21XLTS U3505 ( .A0(n2270), .A1(n4544), .B0(n4459), .Y(n1389) );
AO22XLTS U3506 ( .A0(n5813), .A1(FPADDSUB_DmP_EXP_EWSW[20]), .B0(n5747),
.B1(FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1391) );
OAI21XLTS U3507 ( .A0(n5851), .A1(n4544), .B0(n4457), .Y(n1392) );
AO22XLTS U3508 ( .A0(n5794), .A1(FPADDSUB_DmP_EXP_EWSW[19]), .B0(n5733),
.B1(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1394) );
OAI21XLTS U3509 ( .A0(n2260), .A1(n4544), .B0(n4460), .Y(n1395) );
AO22XLTS U3510 ( .A0(n5803), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n5733),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1397) );
OAI21XLTS U3511 ( .A0(n2269), .A1(n4544), .B0(n4458), .Y(n1398) );
AO22XLTS U3512 ( .A0(n5741), .A1(FPADDSUB_DmP_EXP_EWSW[18]), .B0(n5733),
.B1(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1400) );
AO22XLTS U3513 ( .A0(n5794), .A1(FPADDSUB_DmP_EXP_EWSW[15]), .B0(n5733),
.B1(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1403) );
AO22XLTS U3514 ( .A0(n5808), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n5733),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1406) );
MX2X1TS U3515 ( .A(n5108), .B(FPADDSUB_LZD_output_NRM2_EW[1]), .S0(n5480),
.Y(n1409) );
XOR2XLTS U3516 ( .A(n5190), .B(n5940), .Y(n5194) );
AO22XLTS U3517 ( .A0(n5788), .A1(FPADDSUB_DMP_SFG[30]), .B0(n5715), .B1(
FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1419) );
AO22XLTS U3518 ( .A0(n5721), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n5720),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1420) );
AO22XLTS U3519 ( .A0(n6077), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n5807),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1421) );
AO22XLTS U3520 ( .A0(n5741), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n5733),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1422) );
AO22XLTS U3521 ( .A0(n5788), .A1(FPADDSUB_DMP_SFG[29]), .B0(n2304), .B1(
FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1424) );
AO22XLTS U3522 ( .A0(n5721), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n5718),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1425) );
AO22XLTS U3523 ( .A0(n6077), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n5807),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1426) );
AO22XLTS U3524 ( .A0(n5813), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n5733),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1427) );
AO22XLTS U3525 ( .A0(n5788), .A1(FPADDSUB_DMP_SFG[28]), .B0(n5715), .B1(
FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1429) );
AO22XLTS U3526 ( .A0(n5721), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n5720),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1430) );
AO22XLTS U3527 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n5807),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1431) );
AO22XLTS U3528 ( .A0(n5808), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n5733),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1432) );
AO22XLTS U3529 ( .A0(n5788), .A1(FPADDSUB_DMP_SFG[27]), .B0(n5715), .B1(
FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1434) );
AO22XLTS U3530 ( .A0(n5721), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n5718),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1435) );
AO22XLTS U3531 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n5807),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1436) );
AO22XLTS U3532 ( .A0(n5808), .A1(FPADDSUB_DMP_EXP_EWSW[27]), .B0(n5733),
.B1(FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1437) );
AO22XLTS U3533 ( .A0(n5788), .A1(FPADDSUB_DMP_SFG[26]), .B0(n5715), .B1(
FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1439) );
AO22XLTS U3534 ( .A0(n5721), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n5787),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1440) );
AO22XLTS U3535 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n5807),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1441) );
AO22XLTS U3536 ( .A0(n5788), .A1(FPADDSUB_DMP_SFG[25]), .B0(n5715), .B1(
FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1444) );
AO22XLTS U3537 ( .A0(n5721), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n5787),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1445) );
AO22XLTS U3538 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n5811),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1446) );
AO22XLTS U3539 ( .A0(n5788), .A1(FPADDSUB_DMP_SFG[24]), .B0(n2535), .B1(
FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1449) );
AO22XLTS U3540 ( .A0(n5716), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n5787),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1450) );
AO22XLTS U3541 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n5811),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1451) );
AO22XLTS U3542 ( .A0(n2305), .A1(FPADDSUB_DMP_SFG[23]), .B0(n2535), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1454) );
AO22XLTS U3543 ( .A0(n5716), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n5787),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1455) );
AO22XLTS U3544 ( .A0(n5714), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n5804),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1456) );
OAI21XLTS U3545 ( .A0(n5829), .A1(n4556), .B0(n4536), .Y(n1458) );
AO22XLTS U3546 ( .A0(n5813), .A1(n4089), .B0(n5717), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1474) );
AO22XLTS U3547 ( .A0(n5808), .A1(n5713), .B0(n5733), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1475) );
AO22XLTS U3548 ( .A0(n5813), .A1(n5711), .B0(n5717), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n1476) );
XOR2XLTS U3549 ( .A(n5712), .B(n5710), .Y(n5711) );
AO22XLTS U3550 ( .A0(n5803), .A1(n4084), .B0(n5717), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1477) );
AO22XLTS U3551 ( .A0(n5806), .A1(n5708), .B0(n2272), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1478) );
AO21XLTS U3552 ( .A0(FPMULT_Sgf_normalized_result[23]), .A1(n4865), .B0(
n4729), .Y(n1621) );
MX2X1TS U3553 ( .A(FPMULT_P_Sgf[0]), .B(n5416), .S0(n5426), .Y(n1529) );
MX2X1TS U3554 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_Sgf_operation_Result[2]),
.S0(n5426), .Y(n1531) );
MX2X1TS U3555 ( .A(FPMULT_P_Sgf[9]), .B(FPMULT_Sgf_operation_Result[9]),
.S0(n5426), .Y(n1538) );
MX2X1TS U3556 ( .A(FPMULT_P_Sgf[10]), .B(FPMULT_Sgf_operation_Result[10]),
.S0(n5426), .Y(n1539) );
MX2X1TS U3557 ( .A(FPMULT_P_Sgf[12]), .B(n5425), .S0(n5424), .Y(n1541) );
MX2X1TS U3558 ( .A(FPMULT_P_Sgf[14]), .B(n5420), .S0(n5426), .Y(n1543) );
MX2X1TS U3559 ( .A(FPMULT_P_Sgf[22]), .B(n5415), .S0(n5424), .Y(n1551) );
MX2X1TS U3560 ( .A(FPMULT_P_Sgf[23]), .B(n4994), .S0(n5427), .Y(n1552) );
MX2X1TS U3561 ( .A(Data_2[2]), .B(FPMULT_Op_MY[2]), .S0(n5014), .Y(n1628) );
MX2X1TS U3562 ( .A(Data_2[3]), .B(n2331), .S0(n2319), .Y(n1629) );
MX2X1TS U3563 ( .A(Data_2[4]), .B(FPMULT_Op_MY[4]), .S0(n2319), .Y(n1630) );
MX2X1TS U3564 ( .A(Data_2[5]), .B(n2396), .S0(n5014), .Y(n1631) );
MX2X1TS U3565 ( .A(Data_2[6]), .B(FPMULT_Op_MY[6]), .S0(n5691), .Y(n1632) );
MX2X1TS U3566 ( .A(Data_2[7]), .B(FPMULT_Op_MY[7]), .S0(n4717), .Y(n1633) );
MX2X1TS U3567 ( .A(Data_2[14]), .B(n2421), .S0(n4716), .Y(n1640) );
MX2X1TS U3568 ( .A(Data_2[16]), .B(n2206), .S0(n4716), .Y(n1642) );
MX2X1TS U3569 ( .A(Data_2[17]), .B(n2207), .S0(n4716), .Y(n1643) );
MX2X1TS U3570 ( .A(n5002), .B(FPMULT_FSM_add_overflow_flag), .S0(n5001), .Y(
n1596) );
AO22XLTS U3571 ( .A0(n4715), .A1(Data_1[31]), .B0(n5691), .B1(
FPMULT_Op_MX[31]), .Y(n1657) );
MX2X1TS U3572 ( .A(Data_1[2]), .B(FPMULT_Op_MX[2]), .S0(n4714), .Y(n1660) );
MX2X1TS U3573 ( .A(Data_1[3]), .B(FPMULT_Op_MX[3]), .S0(n4714), .Y(n1661) );
MX2X1TS U3574 ( .A(Data_1[4]), .B(n2209), .S0(n4714), .Y(n1662) );
MX2X1TS U3575 ( .A(Data_1[5]), .B(n2212), .S0(n4714), .Y(n1663) );
MX2X1TS U3576 ( .A(Data_1[6]), .B(n2213), .S0(n4714), .Y(n1664) );
MX2X1TS U3577 ( .A(Data_1[10]), .B(n2214), .S0(n4714), .Y(n1668) );
MX2X1TS U3578 ( .A(Data_1[11]), .B(n2446), .S0(n5691), .Y(n1669) );
MX2X1TS U3579 ( .A(Data_1[12]), .B(FPMULT_Op_MX[12]), .S0(n4717), .Y(n1670)
);
MX2X1TS U3580 ( .A(Data_1[13]), .B(FPMULT_Op_MX[13]), .S0(n5014), .Y(n1671)
);
MX2X1TS U3581 ( .A(Data_1[14]), .B(FPMULT_Op_MX[14]), .S0(n5691), .Y(n1672)
);
MX2X1TS U3582 ( .A(Data_1[16]), .B(FPMULT_Op_MX[16]), .S0(n2320), .Y(n1674)
);
MX2X1TS U3583 ( .A(Data_1[18]), .B(FPMULT_Op_MX[18]), .S0(n2320), .Y(n1676)
);
MX2X1TS U3584 ( .A(Data_1[20]), .B(FPMULT_Op_MX[20]), .S0(n5013), .Y(n1678)
);
MX2X1TS U3585 ( .A(Data_1[21]), .B(n2398), .S0(n2320), .Y(n1679) );
AO22XLTS U3586 ( .A0(n4715), .A1(Data_2[31]), .B0(n5691), .B1(
FPMULT_Op_MY[31]), .Y(n1624) );
AO22XLTS U3587 ( .A0(n5656), .A1(FPSENCOS_d_ff2_X[5]), .B0(n5655), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1994) );
AO22XLTS U3588 ( .A0(n5656), .A1(FPSENCOS_d_ff2_X[7]), .B0(n5655), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1990) );
AO22XLTS U3589 ( .A0(n5656), .A1(FPSENCOS_d_ff2_X[3]), .B0(n5655), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1998) );
AO22XLTS U3590 ( .A0(n5656), .A1(FPSENCOS_d_ff2_X[31]), .B0(n5538), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1942) );
AO22XLTS U3591 ( .A0(n5548), .A1(FPSENCOS_d_ff2_X[14]), .B0(n5655), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1976) );
AO22XLTS U3592 ( .A0(n5656), .A1(FPSENCOS_d_ff2_X[11]), .B0(n5655), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1982) );
AO22XLTS U3593 ( .A0(n5526), .A1(FPSENCOS_d_ff2_X[16]), .B0(n5538), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1972) );
AO22XLTS U3594 ( .A0(n5529), .A1(FPSENCOS_d_ff2_X[13]), .B0(n5655), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1978) );
AO22XLTS U3595 ( .A0(n5583), .A1(FPSENCOS_d_ff2_X[17]), .B0(n5538), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1970) );
CLKBUFX3TS U3596 ( .A(n4112), .Y(n4007) );
AO22XLTS U3597 ( .A0(n5583), .A1(FPSENCOS_d_ff2_X[20]), .B0(n5538), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1964) );
AO22XLTS U3598 ( .A0(n5583), .A1(FPSENCOS_d_ff2_X[19]), .B0(n5538), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1966) );
AO22XLTS U3599 ( .A0(n5656), .A1(FPSENCOS_d_ff2_X[18]), .B0(n5538), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1968) );
AO22XLTS U3600 ( .A0(n5525), .A1(FPSENCOS_d_ff2_X[15]), .B0(n5538), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1974) );
AO22XLTS U3601 ( .A0(n5583), .A1(FPSENCOS_d_ff2_X[22]), .B0(n5538), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1960) );
AO22XLTS U3602 ( .A0(n5654), .A1(result_add_subt[30]), .B0(n5653), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(n1765) );
AO22XLTS U3603 ( .A0(n5654), .A1(result_add_subt[29]), .B0(n5653), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(n1768) );
AO22XLTS U3604 ( .A0(n5644), .A1(result_add_subt[25]), .B0(n5643), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(n1780) );
AO22XLTS U3605 ( .A0(n5654), .A1(result_add_subt[23]), .B0(n5653), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(n1786) );
AOI2BB2XLTS U3606 ( .B0(n5572), .B1(n5530), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n5577), .Y(n1947) );
AOI2BB2XLTS U3607 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n5580), .A0N(n5580),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n5582) );
AOI2BB2XLTS U3608 ( .B0(n5579), .B1(n5578), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n5577), .Y(n1847) );
OAI21XLTS U3609 ( .A0(n5574), .A1(n5573), .B0(n5576), .Y(n5575) );
AOI2BB2XLTS U3610 ( .B0(n5572), .B1(n5571), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n5577), .Y(n1849) );
AO22XLTS U3611 ( .A0(n5656), .A1(intadd_21_SUM_2_), .B0(n5655), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1850) );
AO22XLTS U3612 ( .A0(n5583), .A1(intadd_21_SUM_1_), .B0(n5655), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1851) );
AO22XLTS U3613 ( .A0(n5656), .A1(intadd_21_SUM_0_), .B0(n5655), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1852) );
OAI211XLTS U3614 ( .A0(n5579), .A1(n5949), .B0(n5496), .C0(n4153), .Y(n2120)
);
AOI2BB2XLTS U3615 ( .B0(n5572), .B1(n5497), .A0N(FPSENCOS_d_ff3_LUT_out[13]),
.A1N(n5583), .Y(n2121) );
OAI211XLTS U3616 ( .A0(n5579), .A1(n5947), .B0(n5493), .C0(n4154), .Y(n2124)
);
MX2X1TS U3617 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
FPADDSUB_Shift_reg_FLAGS_7[2]), .S0(n5479), .Y(n2144) );
AOI2BB2XLTS U3618 ( .B0(n5502), .B1(n5484), .A0N(n5484), .A1N(
FPSENCOS_cont_iter_out[2]), .Y(n2139) );
OAI21X4TS U3619 ( .A0(n2852), .A1(n2944), .B0(n2851), .Y(n2918) );
XNOR2X4TS U3620 ( .A(FPMULT_Op_MY[8]), .B(n2374), .Y(n3033) );
NAND2X4TS U3621 ( .A(DP_OP_454J16_123_2743_n310), .B(
DP_OP_454J16_123_2743_n318), .Y(n3334) );
NAND2X2TS U3622 ( .A(DP_OP_454J16_123_2743_n300), .B(
DP_OP_454J16_123_2743_n309), .Y(n2876) );
NOR2X6TS U3623 ( .A(DP_OP_454J16_123_2743_n293), .B(
DP_OP_454J16_123_2743_n299), .Y(n2696) );
OAI21X2TS U3624 ( .A0(n3171), .A1(n2682), .B0(n2681), .Y(n3145) );
OAI21X2TS U3625 ( .A0(n3174), .A1(n3180), .B0(n3175), .Y(n2679) );
AND2X4TS U3626 ( .A(n3258), .B(n2358), .Y(n3315) );
XOR2X4TS U3627 ( .A(n3617), .B(n3616), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N24) );
CMPR42X2TS U3628 ( .A(DP_OP_454J16_123_2743_n447), .B(
DP_OP_454J16_123_2743_n363), .C(DP_OP_454J16_123_2743_n364), .D(
DP_OP_454J16_123_2743_n460), .ICI(DP_OP_454J16_123_2743_n473), .S(
DP_OP_454J16_123_2743_n361), .ICO(DP_OP_454J16_123_2743_n359), .CO(
DP_OP_454J16_123_2743_n360) );
AOI21X2TS U3629 ( .A0(n3194), .A1(n3173), .B0(n3172), .Y(n3183) );
AOI21X4TS U3630 ( .A0(n2968), .A1(n2848), .B0(n2847), .Y(n2944) );
AOI21X2TS U3631 ( .A0(n2945), .A1(n2850), .B0(n2849), .Y(n2851) );
OAI21X4TS U3632 ( .A0(n2846), .A1(n2974), .B0(n2845), .Y(n2968) );
AND2X8TS U3633 ( .A(n2340), .B(n2229), .Y(n2215) );
ADDFX2TS U3634 ( .A(n3318), .B(n2289), .CI(n3241), .CO(mult_x_219_n200), .S(
mult_x_219_n201) );
INVX2TS U3635 ( .A(n2247), .Y(n2374) );
OR2X1TS U3636 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[6]), .Y(n2210) );
INVX4TS U3637 ( .A(n3535), .Y(n2350) );
INVX4TS U3638 ( .A(n2242), .Y(n2398) );
INVX2TS U3639 ( .A(n2240), .Y(n2402) );
CLKXOR2X2TS U3640 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[20]), .Y(n3247) );
OR2X1TS U3641 ( .A(n2446), .B(n2214), .Y(n2219) );
NOR2XLTS U3642 ( .A(n2219), .B(n2257), .Y(n2220) );
OR2X1TS U3643 ( .A(FPMULT_P_Sgf[9]), .B(FPMULT_P_Sgf[10]), .Y(n2221) );
OR2X1TS U3644 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[2]), .Y(n2228) );
OR2X1TS U3645 ( .A(n2591), .B(n2590), .Y(n2231) );
OR2X2TS U3646 ( .A(DP_OP_454J16_123_2743_n271), .B(
DP_OP_454J16_123_2743_n267), .Y(n2232) );
CLKXOR2X2TS U3647 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[14]), .Y(n2638) );
AND2X2TS U3648 ( .A(n2857), .B(n2372), .Y(n2236) );
CLKXOR2X2TS U3649 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[18]), .Y(n3386) );
OR2X4TS U3650 ( .A(n4688), .B(n4694), .Y(n2239) );
CLKXOR2X2TS U3651 ( .A(n2720), .B(n2719), .Y(n2721) );
CLKXOR2X2TS U3652 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[16]), .Y(n2650) );
OR2X4TS U3653 ( .A(n4561), .B(n4694), .Y(n2240) );
BUFX4TS U3654 ( .A(n2893), .Y(n3533) );
BUFX3TS U3655 ( .A(n3385), .Y(n3535) );
CLKXOR2X2TS U3656 ( .A(n2547), .B(n2521), .Y(n2241) );
NAND2X2TS U3657 ( .A(n2725), .B(n2721), .Y(n3629) );
NOR2X2TS U3658 ( .A(n4561), .B(n5640), .Y(n4625) );
INVX2TS U3659 ( .A(n3033), .Y(n2376) );
INVX4TS U3660 ( .A(n2215), .Y(n2311) );
INVX4TS U3661 ( .A(n3247), .Y(n2377) );
XNOR2X2TS U3662 ( .A(n2901), .B(n2900), .Y(n2244) );
CLKBUFX2TS U3663 ( .A(n2856), .Y(n3032) );
INVX2TS U3664 ( .A(n3110), .Y(n2368) );
CLKBUFX2TS U3665 ( .A(n2809), .Y(n3110) );
INVX2TS U3666 ( .A(n2538), .Y(n3508) );
OR2X1TS U3667 ( .A(n2280), .B(FPMULT_Op_MX[0]), .Y(n2257) );
OR2X1TS U3668 ( .A(FPMULT_P_Sgf[14]), .B(FPMULT_P_Sgf[12]), .Y(n2258) );
INVX2TS U3669 ( .A(n4715), .Y(n4716) );
INVX2TS U3670 ( .A(FPSENCOS_cont_iter_out[0]), .Y(n2284) );
NOR4X1TS U3671 ( .A(FPMULT_P_Sgf[8]), .B(FPMULT_P_Sgf[6]), .C(
FPMULT_P_Sgf[7]), .D(FPMULT_P_Sgf[11]), .Y(n2271) );
CLKBUFX2TS U3672 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n5719) );
CLKAND2X4TS U3673 ( .A(n5482), .B(n6008), .Y(n2274) );
INVX2TS U3674 ( .A(rst), .Y(n4112) );
ADDFHX2TS U3675 ( .A(n3557), .B(n3556), .CI(n3555), .CO(
DP_OP_454J16_123_2743_n289), .S(DP_OP_454J16_123_2743_n297) );
OAI22X2TS U3676 ( .A0(n2713), .A1(n2313), .B0(n3628), .B1(n2712), .Y(n3557)
);
NOR2X2TS U3677 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n4713) );
AOI221X1TS U3678 ( .A0(n2261), .A1(FPADDSUB_intDY_EWSW[2]), .B0(
FPADDSUB_intDY_EWSW[3]), .B1(n2466), .C0(n5770), .Y(n5775) );
NOR2X2TS U3679 ( .A(n5841), .B(FPMULT_FS_Module_state_reg[2]), .Y(n5117) );
ADDHX1TS U3680 ( .A(n3329), .B(n3328), .CO(mult_x_219_n248), .S(
mult_x_219_n249) );
OAI21X2TS U3681 ( .A0(n5839), .A1(n4648), .B0(n4601), .Y(n4668) );
OAI21X2TS U3682 ( .A0(n5848), .A1(n4648), .B0(n4576), .Y(n4649) );
BUFX3TS U3683 ( .A(n4494), .Y(n2275) );
INVX2TS U3684 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2276) );
INVX2TS U3685 ( .A(n2501), .Y(n2277) );
INVX2TS U3686 ( .A(n2516), .Y(n2278) );
INVX2TS U3687 ( .A(n2499), .Y(n2279) );
INVX2TS U3688 ( .A(n2498), .Y(n2280) );
INVX2TS U3689 ( .A(n2496), .Y(n2281) );
INVX2TS U3690 ( .A(n2502), .Y(n2282) );
INVX2TS U3691 ( .A(n2284), .Y(n2285) );
INVX4TS U3692 ( .A(n2286), .Y(n2287) );
INVX2TS U3693 ( .A(n2194), .Y(n2288) );
INVX2TS U3694 ( .A(n2524), .Y(n2290) );
INVX2TS U3695 ( .A(n2238), .Y(n2291) );
INVX2TS U3696 ( .A(n2255), .Y(n2293) );
INVX2TS U3697 ( .A(n5800), .Y(n2298) );
INVX2TS U3698 ( .A(n2301), .Y(n2302) );
INVX2TS U3699 ( .A(n2304), .Y(n2305) );
INVX2TS U3700 ( .A(n4494), .Y(n2307) );
INVX2TS U3701 ( .A(n4744), .Y(n2308) );
INVX2TS U3702 ( .A(n2308), .Y(n2309) );
INVX2TS U3703 ( .A(n2308), .Y(n2310) );
INVX2TS U3704 ( .A(n2712), .Y(n2313) );
INVX2TS U3705 ( .A(n2236), .Y(n2317) );
INVX2TS U3706 ( .A(n4715), .Y(n2319) );
INVX2TS U3707 ( .A(n4715), .Y(n2320) );
INVX2TS U3708 ( .A(n2254), .Y(n2321) );
INVX2TS U3709 ( .A(n2321), .Y(n2322) );
INVX2TS U3710 ( .A(n2321), .Y(n2323) );
INVX2TS U3711 ( .A(n2241), .Y(n2325) );
INVX2TS U3712 ( .A(n2508), .Y(n2329) );
INVX2TS U3713 ( .A(n2538), .Y(n2332) );
INVX2TS U3714 ( .A(n2333), .Y(n2335) );
INVX2TS U3715 ( .A(n2197), .Y(n2339) );
INVX4TS U3716 ( .A(n2341), .Y(n2343) );
INVX2TS U3717 ( .A(n2249), .Y(n2345) );
INVX2TS U3718 ( .A(DP_OP_454J16_123_2743_n727), .Y(n2346) );
INVX2TS U3719 ( .A(DP_OP_454J16_123_2743_n727), .Y(n2347) );
INVX2TS U3720 ( .A(n2347), .Y(n2348) );
CLKINVX6TS U3721 ( .A(n2202), .Y(n2349) );
CLKINVX6TS U3722 ( .A(n2350), .Y(n2351) );
INVX2TS U3723 ( .A(n3671), .Y(n2352) );
INVX2TS U3724 ( .A(n3671), .Y(n2353) );
INVX2TS U3725 ( .A(n2638), .Y(n2355) );
INVX2TS U3726 ( .A(n2650), .Y(n2357) );
INVX2TS U3727 ( .A(n3386), .Y(n2359) );
INVX2TS U3728 ( .A(n2235), .Y(n2361) );
INVX2TS U3729 ( .A(n2237), .Y(n2362) );
INVX2TS U3730 ( .A(n2237), .Y(n2363) );
INVX2TS U3731 ( .A(n2246), .Y(n2364) );
INVX2TS U3732 ( .A(n2246), .Y(n2365) );
INVX2TS U3733 ( .A(n2234), .Y(n2366) );
INVX2TS U3734 ( .A(n2234), .Y(n2367) );
INVX2TS U3735 ( .A(n2368), .Y(n2369) );
INVX2TS U3736 ( .A(n2368), .Y(n2370) );
INVX2TS U3737 ( .A(n3032), .Y(n2371) );
INVX2TS U3738 ( .A(n2371), .Y(n2372) );
INVX2TS U3739 ( .A(n2371), .Y(n2373) );
INVX2TS U3740 ( .A(n3247), .Y(n2378) );
INVX4TS U3741 ( .A(n2245), .Y(n2379) );
INVX2TS U3742 ( .A(n2245), .Y(n2380) );
INVX2TS U3743 ( .A(n3672), .Y(n2381) );
INVX2TS U3744 ( .A(n2381), .Y(n2382) );
INVX2TS U3745 ( .A(n2381), .Y(n2383) );
INVX2TS U3746 ( .A(n3674), .Y(n2384) );
INVX2TS U3747 ( .A(n3674), .Y(n2385) );
INVX2TS U3748 ( .A(n2386), .Y(n2387) );
CLKBUFX2TS U3749 ( .A(n2550), .Y(n2393) );
INVX2TS U3750 ( .A(n2394), .Y(n2395) );
INVX2TS U3751 ( .A(n2243), .Y(n2397) );
INVX2TS U3752 ( .A(n2242), .Y(n2399) );
INVX2TS U3753 ( .A(n2222), .Y(n2400) );
INVX2TS U3754 ( .A(n4737), .Y(n2408) );
INVX2TS U3755 ( .A(n4737), .Y(n2409) );
INVX2TS U3756 ( .A(n4737), .Y(n2410) );
OAI21X2TS U3757 ( .A0(n5901), .A1(n4648), .B0(n4597), .Y(n4672) );
OAI21X2TS U3758 ( .A0(n6076), .A1(n4648), .B0(n4562), .Y(n4662) );
OAI21X2TS U3759 ( .A0(n4648), .A1(n5857), .B0(n4617), .Y(n4652) );
OAI21X2TS U3760 ( .A0(n5820), .A1(n4608), .B0(n4607), .Y(n4635) );
AOI211X1TS U3761 ( .A0(n5844), .A1(n2208), .B0(n5501), .C0(n5494), .Y(n4229)
);
NOR4X1TS U3762 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MY[0]), .C(
FPMULT_Op_MY[13]), .D(FPMULT_Op_MY[9]), .Y(n5674) );
NOR2XLTS U3763 ( .A(n2210), .B(n2228), .Y(n5675) );
AOI21X2TS U3764 ( .A0(n2294), .A1(FPADDSUB_Data_array_SWR[25]), .B0(n5030),
.Y(n5054) );
OAI21X2TS U3765 ( .A0(n4608), .A1(n5309), .B0(n4495), .Y(n4687) );
NAND3X2TS U3766 ( .A(n4575), .B(n4574), .C(n4573), .Y(n4682) );
NOR2X2TS U3767 ( .A(n5452), .B(FPSENCOS_cont_iter_out[0]), .Y(n4119) );
OAI21XLTS U3768 ( .A0(n4214), .A1(n5895), .B0(n4213), .Y(op_result[9]) );
OAI21XLTS U3769 ( .A0(n4214), .A1(n5888), .B0(n4210), .Y(op_result[10]) );
OAI21XLTS U3770 ( .A0(n4214), .A1(n5884), .B0(n4181), .Y(op_result[16]) );
OAI21XLTS U3771 ( .A0(n4214), .A1(n5885), .B0(n4202), .Y(op_result[8]) );
OAI21XLTS U3772 ( .A0(n4214), .A1(n5875), .B0(n4178), .Y(op_result[15]) );
NAND2X4TS U3773 ( .A(n2323), .B(n2204), .Y(n5055) );
NOR2X4TS U3774 ( .A(n5452), .B(FPSENCOS_cont_iter_out[1]), .Y(n5487) );
NOR2X1TS U3775 ( .A(n5906), .B(FPADDSUB_intDX_EWSW[25]), .Y(n2789) );
ADDHX1TS U3776 ( .A(n2654), .B(n2653), .CO(n2655), .S(n2648) );
AOI222X1TS U3777 ( .A0(n4297), .A1(cordic_result[17]), .B0(n4302), .B1(
FPSENCOS_d_ff_Yn[17]), .C0(n4276), .C1(FPSENCOS_d_ff_Xn[17]), .Y(n4284) );
AOI222X1TS U3778 ( .A0(n4240), .A1(cordic_result[10]), .B0(n4314), .B1(
FPSENCOS_d_ff_Yn[10]), .C0(n4239), .C1(FPSENCOS_d_ff_Xn[10]), .Y(n4299) );
BUFX3TS U3779 ( .A(n4112), .Y(n4005) );
CLKBUFX3TS U3780 ( .A(n4112), .Y(n6052) );
BUFX3TS U3781 ( .A(n4112), .Y(n4008) );
BUFX3TS U3782 ( .A(n4007), .Y(n6039) );
AOI222X1TS U3783 ( .A0(n4311), .A1(cordic_result[26]), .B0(n4310), .B1(
FPSENCOS_d_ff_Yn[26]), .C0(n4309), .C1(FPSENCOS_d_ff_Xn[26]), .Y(n4312) );
AOI222X1TS U3784 ( .A0(n4311), .A1(cordic_result[24]), .B0(n4310), .B1(
FPSENCOS_d_ff_Yn[24]), .C0(n4309), .C1(FPSENCOS_d_ff_Xn[24]), .Y(n4308) );
AOI222X1TS U3785 ( .A0(n4311), .A1(cordic_result[27]), .B0(n4310), .B1(
FPSENCOS_d_ff_Yn[27]), .C0(n4309), .C1(FPSENCOS_d_ff_Xn[27]), .Y(n4304) );
NOR2X1TS U3786 ( .A(n5922), .B(FPADDSUB_DMP_SFG[13]), .Y(n5151) );
OR2X1TS U3787 ( .A(n5936), .B(FPADDSUB_DMP_SFG[9]), .Y(n5132) );
NOR4X1TS U3788 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_Op_MX[26]), .C(
FPMULT_Op_MX[25]), .D(FPMULT_Op_MX[23]), .Y(n5680) );
NOR4X2TS U3789 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n3659) );
OAI21X2TS U3790 ( .A0(n2216), .A1(n4608), .B0(n4593), .Y(n4633) );
BUFX3TS U3791 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n5803) );
INVX2TS U3792 ( .A(n2253), .Y(n2412) );
INVX2TS U3793 ( .A(n2253), .Y(n2413) );
INVX2TS U3794 ( .A(n2253), .Y(n2414) );
INVX2TS U3795 ( .A(n2233), .Y(n2415) );
NOR2X2TS U3796 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n4967) );
OAI222X1TS U3797 ( .A0(n5722), .A1(n5906), .B0(n2460), .B1(
FPADDSUB_Shift_reg_FLAGS_7_6), .C0(n2224), .C1(n5723), .Y(n1463) );
OAI221XLTS U3798 ( .A0(n5829), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n5864),
.B1(FPADDSUB_intDY_EWSW[29]), .C0(n5758), .Y(n5763) );
AOI32X1TS U3799 ( .A0(n2480), .A1(n2775), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n2465), .Y(n2776) );
OAI211XLTS U3800 ( .A0(n4367), .A1(n5909), .B0(n4366), .C0(n4365), .Y(n1914)
);
OAI211XLTS U3801 ( .A0(n2464), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n2732), .C0(
n2731), .Y(n2736) );
OAI21XLTS U3802 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n2464), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n2733) );
OAI211XLTS U3803 ( .A0(n4367), .A1(n5942), .B0(n4340), .C0(n4339), .Y(n1917)
);
AOI221X1TS U3804 ( .A0(n2266), .A1(FPADDSUB_intDY_EWSW[0]), .B0(
FPADDSUB_intDY_EWSW[26]), .B1(n2227), .C0(n5769), .Y(n5776) );
OAI211XLTS U3805 ( .A0(n4367), .A1(n5566), .B0(n4336), .C0(n4335), .Y(n1920)
);
OAI221X1TS U3806 ( .A0(n2226), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n5855),
.B1(FPADDSUB_intDY_EWSW[23]), .C0(n5765), .Y(n5780) );
AOI221X1TS U3807 ( .A0(n2738), .A1(FPADDSUB_intDY_EWSW[6]), .B0(
FPADDSUB_intDY_EWSW[8]), .B1(n2259), .C0(n5772), .Y(n5773) );
OAI221X1TS U3808 ( .A0(n2223), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n2270),
.B1(FPADDSUB_intDY_EWSW[17]), .C0(n5749), .Y(n5756) );
OAI221X1TS U3809 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n5828), .B0(n5865), .B1(
FPADDSUB_intDY_EWSW[7]), .C0(n5768), .Y(n5778) );
AOI221X1TS U3810 ( .A0(n2260), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[20]), .B1(n5851), .C0(n5767), .Y(n5768) );
OAI221XLTS U3811 ( .A0(n2225), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n2269),
.B1(FPADDSUB_intDY_EWSW[21]), .C0(n5766), .Y(n5779) );
OAI221X1TS U3812 ( .A0(n2505), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n2262),
.B1(FPADDSUB_intDY_EWSW[27]), .C0(n5759), .Y(n5762) );
AOI222X1TS U3813 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2737), .B0(n2736), .B1(
n2735), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n2734), .Y(n2741) );
AOI221X1TS U3814 ( .A0(n2737), .A1(FPADDSUB_intDY_EWSW[4]), .B0(
FPADDSUB_intDY_EWSW[5]), .B1(n2734), .C0(n5771), .Y(n5774) );
INVX2TS U3815 ( .A(n2500), .Y(n2416) );
INVX2TS U3816 ( .A(n2517), .Y(n2417) );
XOR2X1TS U3817 ( .A(n2417), .B(FPMULT_Op_MX[14]), .Y(n2557) );
OAI21X1TS U3818 ( .A0(FPMULT_Op_MX[2]), .A1(FPMULT_Op_MX[14]), .B0(
FPMULT_Op_MX[1]), .Y(n2561) );
OR2X2TS U3819 ( .A(n4725), .B(FPMULT_FS_Module_state_reg[1]), .Y(
FPMULT_FSM_exp_operation_A_S) );
INVX2TS U3820 ( .A(FPMULT_FSM_exp_operation_A_S), .Y(n2418) );
INVX2TS U3821 ( .A(FPMULT_FSM_exp_operation_A_S), .Y(n2419) );
INVX2TS U3822 ( .A(n2420), .Y(n2421) );
BUFX3TS U3823 ( .A(n2712), .Y(n2422) );
NAND2X2TS U3824 ( .A(n2714), .B(FPMULT_Op_MX[11]), .Y(n2712) );
INVX2TS U3825 ( .A(n3315), .Y(n2427) );
AND2X4TS U3826 ( .A(n3248), .B(n2377), .Y(n3327) );
INVX2TS U3827 ( .A(n3327), .Y(n2429) );
INVX2TS U3828 ( .A(n3104), .Y(n2430) );
CLKBUFX2TS U3829 ( .A(n3112), .Y(n2432) );
NAND2X4TS U3830 ( .A(n2810), .B(n3110), .Y(n3112) );
CLKBUFX2TS U3831 ( .A(n3124), .Y(n2434) );
NAND2X6TS U3832 ( .A(n3034), .B(n3033), .Y(n3124) );
INVX2TS U3833 ( .A(n3518), .Y(n2436) );
CLKBUFX2TS U3834 ( .A(n3541), .Y(n2437) );
INVX4TS U3835 ( .A(n3549), .Y(n2438) );
INVX2TS U3836 ( .A(n3549), .Y(n2439) );
INVX4TS U3837 ( .A(n3624), .Y(n2440) );
INVX2TS U3838 ( .A(n3624), .Y(n2441) );
INVX2TS U3839 ( .A(n2510), .Y(n2442) );
BUFX3TS U3840 ( .A(FPMULT_Op_MX[0]), .Y(n3128) );
INVX2TS U3841 ( .A(n2443), .Y(n2444) );
BUFX3TS U3842 ( .A(FPMULT_Op_MY[12]), .Y(n3324) );
OAI22X1TS U3843 ( .A0(n3506), .A1(n2445), .B0(n2552), .B1(n3508), .Y(n3510)
);
INVX2TS U3844 ( .A(n3627), .Y(n3621) );
NAND2X1TS U3845 ( .A(n2518), .B(n2545), .Y(n3627) );
AOI21X2TS U3846 ( .A0(n2837), .A1(n2999), .B0(n2836), .Y(n2997) );
AOI31XLTS U3847 ( .A0(n5439), .A1(n5438), .A2(n5437), .B0(dataB[27]), .Y(
n5450) );
OAI21XLTS U3848 ( .A0(FPADDSUB_DmP_EXP_EWSW[25]), .A1(n2460), .B0(n4086),
.Y(n4083) );
OAI31XLTS U3849 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(
FPSENCOS_cont_iter_out[3]), .A2(n5505), .B0(n4230), .Y(n2127) );
BUFX3TS U3850 ( .A(n4113), .Y(n4010) );
AOI21X1TS U3851 ( .A0(n3172), .A1(n2680), .B0(n2679), .Y(n2681) );
NOR4BX2TS U3852 ( .AN(n4478), .B(n4141), .C(n4133), .D(n4132), .Y(n4136) );
OAI33X4TS U3853 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .A2(n5486), .B0(n5832), .B1(
n5872), .B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n4242) );
OAI211XLTS U3854 ( .A0(n4367), .A1(n5573), .B0(n4363), .C0(n4362), .Y(n1913)
);
NOR4X1TS U3855 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n5965) );
NOR4X1TS U3856 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n5966) );
NOR4X1TS U3857 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n3669),
.Y(n5964) );
NOR2XLTS U3858 ( .A(n2221), .B(n2258), .Y(n3649) );
NOR2X2TS U3859 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n5576), .Y(n5580) );
NOR4X1TS U3860 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[19]), .C(
FPMULT_Op_MX[17]), .D(FPMULT_Op_MX[15]), .Y(n5678) );
OAI22X1TS U3861 ( .A0(n2317), .A1(n3027), .B0(n2372), .B1(n3026), .Y(
mult_x_254_n294) );
NOR4X1TS U3862 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[5]), .C(
FPMULT_Op_MY[3]), .D(FPMULT_Op_MY[1]), .Y(n5676) );
NOR2X2TS U3863 ( .A(n5499), .B(n5489), .Y(n5497) );
OAI21XLTS U3864 ( .A0(n4200), .A1(n5666), .B0(n4199), .Y(op_result[31]) );
OAI21XLTS U3865 ( .A0(n4200), .A1(n5642), .B0(n4198), .Y(op_result[24]) );
OAI21XLTS U3866 ( .A0(n4200), .A1(n5648), .B0(n4197), .Y(op_result[27]) );
OAI21XLTS U3867 ( .A0(n4200), .A1(n5652), .B0(n4196), .Y(op_result[28]) );
OAI21XLTS U3868 ( .A0(n4200), .A1(n5646), .B0(n4195), .Y(op_result[26]) );
OAI21XLTS U3869 ( .A0(n4200), .A1(n5876), .B0(n4182), .Y(op_result[18]) );
AOI21X2TS U3870 ( .A0(n2294), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n5030),
.Y(n5050) );
NOR2X2TS U3871 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n4058) );
NOR2X2TS U3872 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4045) );
NOR2X2TS U3873 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n5349) );
NOR3X4TS U3874 ( .A(n5482), .B(n5844), .C(n2208), .Y(n5484) );
OAI21X2TS U3875 ( .A0(n5495), .A1(n2208), .B0(n5494), .Y(n5489) );
OAI211X4TS U3876 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(
FPSENCOS_cont_iter_out[2]), .B0(n4226), .C0(n5494), .Y(n4124) );
NAND2X2TS U3877 ( .A(FPSENCOS_cont_iter_out[3]), .B(n2301), .Y(n5494) );
CLKBUFX3TS U3878 ( .A(n2274), .Y(n4006) );
BUFX3TS U3879 ( .A(n4112), .Y(n4004) );
AOI222X4TS U3880 ( .A0(n4315), .A1(cordic_result[4]), .B0(n4314), .B1(
FPSENCOS_d_ff_Yn[4]), .C0(n4313), .C1(FPSENCOS_d_ff_Xn[4]), .Y(n4282)
);
AOI222X4TS U3881 ( .A0(n4315), .A1(cordic_result[8]), .B0(n4314), .B1(
FPSENCOS_d_ff_Yn[8]), .C0(n4313), .C1(FPSENCOS_d_ff_Xn[8]), .Y(n4292)
);
AOI222X4TS U3882 ( .A0(n4315), .A1(cordic_result[0]), .B0(n4289), .B1(
FPSENCOS_d_ff_Yn[0]), .C0(n4313), .C1(FPSENCOS_d_ff_Xn[0]), .Y(n4280)
);
AOI222X4TS U3883 ( .A0(n4315), .A1(cordic_result[9]), .B0(n4314), .B1(
FPSENCOS_d_ff_Yn[9]), .C0(n4313), .C1(FPSENCOS_d_ff_Xn[9]), .Y(n4294)
);
AOI222X4TS U3884 ( .A0(n4315), .A1(cordic_result[6]), .B0(n4314), .B1(
FPSENCOS_d_ff_Yn[6]), .C0(n4313), .C1(FPSENCOS_d_ff_Xn[6]), .Y(n4285)
);
AOI222X4TS U3885 ( .A0(n4240), .A1(cordic_result[3]), .B0(n4314), .B1(
FPSENCOS_d_ff_Yn[3]), .C0(n4313), .C1(FPSENCOS_d_ff_Xn[3]), .Y(n4301)
);
AOI222X4TS U3886 ( .A0(n4315), .A1(cordic_result[2]), .B0(n4314), .B1(
FPSENCOS_d_ff_Yn[2]), .C0(n4313), .C1(FPSENCOS_d_ff_Xn[2]), .Y(n4316)
);
AOI222X4TS U3887 ( .A0(n4315), .A1(cordic_result[7]), .B0(n4314), .B1(
FPSENCOS_d_ff_Yn[7]), .C0(n4313), .C1(FPSENCOS_d_ff_Xn[7]), .Y(n4286)
);
AOI222X4TS U3888 ( .A0(n4315), .A1(cordic_result[1]), .B0(n4289), .B1(
FPSENCOS_d_ff_Yn[1]), .C0(n4313), .C1(FPSENCOS_d_ff_Xn[1]), .Y(n4290)
);
AOI222X4TS U3889 ( .A0(n4240), .A1(cordic_result[5]), .B0(n4314), .B1(
FPSENCOS_d_ff_Yn[5]), .C0(n4313), .C1(FPSENCOS_d_ff_Xn[5]), .Y(n4305)
);
NOR2XLTS U3890 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n4101) );
NOR3XLTS U3891 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[12]), .C(
FPMULT_Op_MY[23]), .Y(n5673) );
NOR3XLTS U3892 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[13]), .C(
FPMULT_Op_MX[24]), .Y(n5682) );
OAI211XLTS U3893 ( .A0(n4367), .A1(n5908), .B0(n4356), .C0(n4355), .Y(n1912)
);
NOR2XLTS U3894 ( .A(FPMULT_P_Sgf[47]), .B(n5007), .Y(n5008) );
AOI222X1TS U3895 ( .A0(n4533), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DmP_EXP_EWSW[23]), .B1(n5790), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n4510), .Y(n4505) );
OAI21XLTS U3896 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n5869), .B0(n5712),
.Y(n5713) );
CLKBUFX2TS U3897 ( .A(FPMULT_Op_MX[11]), .Y(n2446) );
XNOR2X1TS U3898 ( .A(n2714), .B(FPMULT_Op_MX[11]), .Y(n2715) );
OAI21X2TS U3899 ( .A0(n5860), .A1(n4648), .B0(n4620), .Y(n4666) );
OAI21X2TS U3900 ( .A0(n5840), .A1(n4648), .B0(n4570), .Y(n4644) );
OAI21X2TS U3901 ( .A0(n5941), .A1(n4608), .B0(n4563), .Y(n4675) );
INVX2TS U3902 ( .A(n5105), .Y(n2447) );
NOR3X1TS U3903 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n5702), .Y(n5694) );
NOR3X1TS U3904 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3657) );
OAI221XLTS U3905 ( .A0(n2224), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2263),
.B1(FPADDSUB_intDY_EWSW[1]), .C0(n5760), .Y(n5761) );
OAI21X1TS U3906 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(n4161), .Y(n4162) );
INVX2TS U3907 ( .A(n2528), .Y(n2448) );
NAND2X1TS U3908 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .Y(n3429) );
NOR2X1TS U3909 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .Y(n3418) );
OAI211XLTS U3910 ( .A0(n4367), .A1(n5944), .B0(n4342), .C0(n4341), .Y(n1915)
);
NOR2X1TS U3911 ( .A(FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4163) );
NOR3X1TS U3912 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n3662) );
INVX2TS U3913 ( .A(n4997), .Y(n2449) );
INVX2TS U3914 ( .A(n4997), .Y(n2450) );
INVX2TS U3915 ( .A(n4997), .Y(n2451) );
OR2X1TS U3916 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n5196) );
OR2X1TS U3917 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]),
.Y(n5264) );
OR2X1TS U3918 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]),
.Y(n5215) );
OR2X1TS U3919 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]),
.Y(n5154) );
OR2X1TS U3920 ( .A(n5934), .B(FPADDSUB_DMP_SFG[14]), .Y(n5162) );
OR2X1TS U3921 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]),
.Y(n5255) );
OR2X1TS U3922 ( .A(n5933), .B(FPADDSUB_DMP_SFG[16]), .Y(n5177) );
OR2X1TS U3923 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]),
.Y(n5234) );
OR2X1TS U3924 ( .A(n5932), .B(FPADDSUB_DMP_SFG[18]), .Y(n5181) );
NOR2X1TS U3925 ( .A(n5918), .B(FPADDSUB_DMP_SFG[21]), .Y(n5187) );
AOI222X1TS U3926 ( .A0(n4554), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DMP_EXP_EWSW[23]), .B1(n5790), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n4531), .Y(n4532) );
AOI21X2TS U3927 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2294), .B0(n5027),
.Y(n5089) );
AOI21X2TS U3928 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n2294), .B0(n5023),
.Y(n5086) );
AOI22X1TS U3929 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n4123), .B0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n2250),
.Y(n5476) );
BUFX3TS U3930 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n5741) );
BUFX3TS U3931 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n5794) );
BUFX3TS U3932 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n5808) );
OAI211XLTS U3933 ( .A0(n4422), .A1(n2456), .B0(n4405), .C0(n4404), .Y(n1833)
);
NOR2XLTS U3934 ( .A(n2773), .B(FPADDSUB_intDY_EWSW[16]), .Y(n2774) );
OR2X2TS U3935 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n5854), .Y(n5036)
);
NAND2X1TS U3936 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n5854), .Y(n4094)
);
INVX2TS U3937 ( .A(n6077), .Y(n5807) );
OR2X1TS U3938 ( .A(n3874), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .Y(n2453) );
OR2X1TS U3939 ( .A(n3875), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .Y(n2454) );
OR2X1TS U3940 ( .A(n2555), .B(n2554), .Y(n2495) );
OR2X1TS U3941 ( .A(n3860), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[14]), .Y(n2497) );
OR2X1TS U3942 ( .A(n2648), .B(n2647), .Y(n2504) );
OR2X1TS U3943 ( .A(n2666), .B(n2665), .Y(n2506) );
BUFX3TS U3944 ( .A(FPMULT_Op_MY[18]), .Y(n5668) );
BUFX3TS U3945 ( .A(FPMULT_Op_MY[22]), .Y(n4718) );
OR2X1TS U3946 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .Y(n2518) );
INVX2TS U3947 ( .A(FPMULT_Op_MX[12]), .Y(n2539) );
AND2X4TS U3948 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .B(n5784), .Y(n2527) );
AO21X1TS U3949 ( .A0(n3435), .A1(n3426), .B0(n2891), .Y(n2529) );
OR2X2TS U3950 ( .A(DP_OP_454J16_123_2743_n349), .B(
DP_OP_454J16_123_2743_n355), .Y(n2530) );
AO21X1TS U3951 ( .A0(n3593), .A1(n3577), .B0(n3576), .Y(n2532) );
CLKBUFX2TS U3952 ( .A(n5516), .Y(n5520) );
CLKBUFX2TS U3953 ( .A(n5515), .Y(n5519) );
OAI21XLTS U3954 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n5816), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n2730) );
NOR2X1TS U3955 ( .A(n5817), .B(FPADDSUB_intDX_EWSW[11]), .Y(n2751) );
OAI21X1TS U3956 ( .A0(n3869), .A1(n3866), .B0(n3870), .Y(n3710) );
NOR2X2TS U3957 ( .A(n3603), .B(n3565), .Y(n3568) );
NAND2X1TS U3958 ( .A(n2536), .B(n2581), .Y(n2537) );
INVX2TS U3959 ( .A(n3826), .Y(n3828) );
NAND2X4TS U3960 ( .A(n2596), .B(n2577), .Y(n3541) );
NAND2X4TS U3961 ( .A(n2658), .B(n2356), .Y(n3308) );
NOR2BX1TS U3962 ( .AN(n2293), .B(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n3672) );
OA22X1TS U3963 ( .A0(n2491), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n2469), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n2784) );
OR2X1TS U3964 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n5288) );
OAI21X1TS U3965 ( .A0(n4035), .A1(n3685), .B0(n3684), .Y(n5291) );
ADDHXLTS U3966 ( .A(n2872), .B(n2871), .CO(mult_x_254_n267), .S(n2838) );
CMPR42X1TS U3967 ( .A(DP_OP_454J16_123_2743_n297), .B(
DP_OP_454J16_123_2743_n412), .C(DP_OP_454J16_123_2743_n400), .D(
DP_OP_454J16_123_2743_n304), .ICI(DP_OP_454J16_123_2743_n301), .S(
DP_OP_454J16_123_2743_n296), .ICO(DP_OP_454J16_123_2743_n294), .CO(
DP_OP_454J16_123_2743_n295) );
CMPR42X1TS U3968 ( .A(DP_OP_454J16_123_2743_n406), .B(
DP_OP_454J16_123_2743_n418), .C(DP_OP_454J16_123_2743_n431), .D(
DP_OP_454J16_123_2743_n352), .ICI(DP_OP_454J16_123_2743_n457), .S(
DP_OP_454J16_123_2743_n346), .ICO(DP_OP_454J16_123_2743_n344), .CO(
DP_OP_454J16_123_2743_n345) );
CMPR42X1TS U3969 ( .A(mult_x_219_n291), .B(mult_x_219_n351), .C(
mult_x_219_n339), .D(mult_x_219_n327), .ICI(mult_x_219_n248), .S(
mult_x_219_n242), .ICO(mult_x_219_n240), .CO(mult_x_219_n241) );
NAND2X1TS U3970 ( .A(n5402), .B(n3910), .Y(n3912) );
NAND2X1TS U3971 ( .A(FPMULT_Sgf_normalized_result[3]), .B(
FPMULT_Sgf_normalized_result[2]), .Y(n4719) );
XOR3X1TS U3972 ( .A(n2864), .B(n2863), .C(n2862), .Y(n2865) );
CMPR42X1TS U3973 ( .A(mult_x_254_n335), .B(mult_x_254_n359), .C(
mult_x_254_n250), .D(mult_x_254_n245), .ICI(mult_x_254_n244), .S(
mult_x_254_n241), .ICO(mult_x_254_n239), .CO(mult_x_254_n240) );
NAND2X1TS U3974 ( .A(n2697), .B(n2703), .Y(n2705) );
CMPR42X1TS U3975 ( .A(DP_OP_454J16_123_2743_n435), .B(
DP_OP_454J16_123_2743_n448), .C(DP_OP_454J16_123_2743_n461), .D(
DP_OP_454J16_123_2743_n369), .ICI(DP_OP_454J16_123_2743_n474), .S(
DP_OP_454J16_123_2743_n366), .ICO(DP_OP_454J16_123_2743_n364), .CO(
DP_OP_454J16_123_2743_n365) );
CMPR42X1TS U3976 ( .A(mult_x_219_n295), .B(mult_x_219_n183), .C(
mult_x_219_n177), .D(mult_x_219_n184), .ICI(mult_x_219_n180), .S(
mult_x_219_n175), .ICO(mult_x_219_n173), .CO(mult_x_219_n174) );
CMPR42X1TS U3977 ( .A(mult_x_219_n325), .B(mult_x_219_n228), .C(
mult_x_219_n233), .D(mult_x_219_n226), .ICI(mult_x_219_n229), .S(
mult_x_219_n223), .ICO(mult_x_219_n221), .CO(mult_x_219_n222) );
NAND3X1TS U3978 ( .A(n2322), .B(FPADDSUB_shift_value_SHT2_EWR[2]), .C(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n5064) );
INVX2TS U3979 ( .A(n4957), .Y(n4959) );
NAND2X1TS U3980 ( .A(n3980), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(n4884) );
OR2X4TS U3981 ( .A(n4471), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n4469) );
OAI21XLTS U3982 ( .A0(n5347), .A1(n5286), .B0(n5285), .Y(n5290) );
OAI21XLTS U3983 ( .A0(n5347), .A1(n5329), .B0(n5328), .Y(n5334) );
OAI21X1TS U3984 ( .A0(n3146), .A1(n3148), .B0(n3149), .Y(n2684) );
OR2X1TS U3985 ( .A(n2824), .B(n2823), .Y(n3016) );
NAND2X1TS U3986 ( .A(DP_OP_454J16_123_2743_n258), .B(n3569), .Y(n3609) );
AOI21X2TS U3987 ( .A0(n2678), .A1(n3195), .B0(n2677), .Y(n3171) );
NAND2X1TS U3988 ( .A(n2648), .B(n2647), .Y(n3233) );
OAI21X2TS U3989 ( .A0(n5227), .A1(n5179), .B0(n5178), .Y(n5236) );
OAI21X2TS U3990 ( .A0(n5152), .A1(n5151), .B0(n5150), .Y(n5163) );
INVX2TS U3991 ( .A(n4896), .Y(n4993) );
AOI21X2TS U3992 ( .A0(n3145), .A1(n2685), .B0(n2684), .Y(n3144) );
OR2X1TS U3993 ( .A(n3061), .B(n3060), .Y(n3063) );
AOI21X2TS U3994 ( .A0(n3643), .A1(n2905), .B0(n2904), .Y(n2908) );
OAI21XLTS U3995 ( .A0(n3219), .A1(n3215), .B0(n3216), .Y(n3214) );
OR2X1TS U3996 ( .A(n3286), .B(n3285), .Y(n3288) );
OAI211X1TS U3997 ( .A0(n4493), .A1(n4492), .B0(n4491), .C0(n4490), .Y(n5108)
);
INVX2TS U3998 ( .A(FPSENCOS_d_ff_Xn[31]), .Y(n5665) );
INVX2TS U3999 ( .A(FPSENCOS_d_ff2_Y[21]), .Y(n5566) );
INVX2TS U4000 ( .A(FPSENCOS_d_ff2_Y[18]), .Y(n5563) );
AND3X1TS U4001 ( .A(n4582), .B(n4581), .C(n4580), .Y(n4685) );
INVX2TS U4002 ( .A(FPSENCOS_d_ff2_Y[28]), .Y(n5573) );
AOI211XLTS U4003 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n5501), .B0(n4229),
.C0(n4228), .Y(n4230) );
AOI211XLTS U4004 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n4116), .B0(n4782),
.C0(n5112), .Y(n6071) );
OAI21XLTS U4005 ( .A0(n2270), .A1(n4526), .B0(n4513), .Y(n1233) );
OAI21XLTS U4006 ( .A0(n2266), .A1(n4538), .B0(n4501), .Y(n1298) );
OAI21XLTS U4007 ( .A0(n2514), .A1(n4544), .B0(n4543), .Y(n1386) );
OAI211XLTS U4008 ( .A0(n4422), .A1(n2462), .B0(n4421), .C0(n4420), .Y(n1910)
);
OAI211XLTS U4009 ( .A0(n4422), .A1(n5910), .B0(n4417), .C0(n4416), .Y(n1911)
);
OAI21XLTS U4010 ( .A0(n4214), .A1(n5880), .B0(n4180), .Y(op_result[17]) );
NOR2X2TS U4012 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[1]), .Y(n2541) );
NAND2X2TS U4013 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[1]), .Y(n2542) );
OAI21X4TS U4014 ( .A0(n2541), .A1(n2545), .B0(n2542), .Y(n2585) );
INVX2TS U4015 ( .A(n2585), .Y(n2565) );
INVX2TS U4016 ( .A(n2579), .Y(n2536) );
CLKXOR2X4TS U4017 ( .A(n2565), .B(n2537), .Y(n3622) );
XNOR2X2TS U4018 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[13]), .Y(n2547) );
XNOR2X1TS U4019 ( .A(n3622), .B(n2324), .Y(n2569) );
XOR2X1TS U4020 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MX[12]), .Y(n2538) );
XOR2X1TS U4021 ( .A(n2539), .B(n2547), .Y(n2540) );
AND2X2TS U4022 ( .A(n2540), .B(n3508), .Y(n2551) );
INVX2TS U4023 ( .A(n2551), .Y(n3504) );
INVX2TS U4024 ( .A(n2541), .Y(n2543) );
CLKXOR2X4TS U4025 ( .A(n2544), .B(n2545), .Y(n3527) );
XNOR2X1TS U4026 ( .A(n3527), .B(n2324), .Y(n2552) );
OAI22X1TS U4027 ( .A0(n2569), .A1(n3508), .B0(n3504), .B1(n2552), .Y(n2555)
);
NOR2X1TS U4028 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[13]), .Y(n2546) );
XNOR2X1TS U4029 ( .A(n2557), .B(n2546), .Y(n2549) );
NAND2X1TS U4030 ( .A(n2547), .B(n2521), .Y(n2548) );
NOR2BX1TS U4031 ( .AN(n2445), .B(n2393), .Y(n2554) );
INVX2TS U4032 ( .A(n2551), .Y(n3506) );
NAND2X1TS U4033 ( .A(n2553), .B(n3506), .Y(n3509) );
NAND2X1TS U4034 ( .A(n3510), .B(n3509), .Y(n3511) );
INVX2TS U4035 ( .A(n3511), .Y(n3382) );
NAND2X1TS U4036 ( .A(n2555), .B(n2554), .Y(n3381) );
INVX2TS U4037 ( .A(n3381), .Y(n2556) );
AOI21X1TS U4038 ( .A0(n2495), .A1(n3382), .B0(n2556), .Y(n3379) );
NOR2X1TS U4039 ( .A(n2638), .B(n2557), .Y(n2558) );
XNOR2X2TS U4040 ( .A(FPMULT_Op_MX[15]), .B(n2416), .Y(n2574) );
XOR2X1TS U4041 ( .A(n2558), .B(n2574), .Y(n2559) );
NAND2X1TS U4042 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .Y(n2560) );
NAND2X2TS U4043 ( .A(n2561), .B(n2560), .Y(n2573) );
XNOR2X1TS U4044 ( .A(n2574), .B(n2573), .Y(n2562) );
OAI22X1TS U4045 ( .A0(n2435), .A1(n2333), .B0(n2200), .B1(n2563), .Y(n2589)
);
XNOR2X1TS U4046 ( .A(n3487), .B(n2445), .Y(n2564) );
XNOR2X1TS U4047 ( .A(n3527), .B(n2334), .Y(n2578) );
OAI22X1TS U4048 ( .A0(n2435), .A1(n2564), .B0(n2578), .B1(n2200), .Y(n2588)
);
OAI21X2TS U4049 ( .A0(n2565), .A1(n2579), .B0(n2581), .Y(n2568) );
INVX2TS U4050 ( .A(n2582), .Y(n2566) );
XNOR2X4TS U4051 ( .A(n2568), .B(n2567), .Y(n3477) );
XNOR2X1TS U4052 ( .A(n3477), .B(n2324), .Y(n2587) );
OAI22X1TS U4053 ( .A0(n2587), .A1(n2332), .B0(n2569), .B1(n3506), .Y(n2570)
);
NAND2X1TS U4054 ( .A(n2571), .B(n2570), .Y(n3377) );
OAI21X2TS U4055 ( .A0(n3379), .A1(n3376), .B0(n3377), .Y(n3374) );
NOR2BX1TS U4056 ( .AN(n2445), .B(n2395), .Y(n2604) );
XNOR2X1TS U4057 ( .A(n3622), .B(n2334), .Y(n2593) );
OAI22X1TS U4058 ( .A0(n2593), .A1(n2200), .B0(n2435), .B1(n2578), .Y(n2603)
);
OAI21X2TS U4059 ( .A0(n2582), .A1(n2581), .B0(n2580), .Y(n2583) );
AOI21X4TS U4060 ( .A0(n2585), .A1(n2584), .B0(n2583), .Y(n2887) );
INVX2TS U4061 ( .A(n2881), .Y(n2606) );
NAND2X2TS U4062 ( .A(n2290), .B(FPMULT_Op_MY[4]), .Y(n2883) );
XNOR2X4TS U4063 ( .A(n3408), .B(n2586), .Y(n3488) );
XNOR2X1TS U4064 ( .A(n3488), .B(n2324), .Y(n2610) );
OAI22X1TS U4065 ( .A0(n2610), .A1(n2332), .B0(n2587), .B1(n3506), .Y(n2602)
);
ADDHX1TS U4066 ( .A(n2589), .B(n2588), .CO(n2590), .S(n2571) );
NAND2X1TS U4067 ( .A(n2591), .B(n2590), .Y(n3373) );
INVX2TS U4068 ( .A(n3373), .Y(n2592) );
AOI21X4TS U4069 ( .A0(n3374), .A1(n2231), .B0(n2592), .Y(n3371) );
XNOR2X1TS U4070 ( .A(n3477), .B(n2334), .Y(n3490) );
OAI22X1TS U4071 ( .A0(n3490), .A1(n2200), .B0(n2593), .B1(n2436), .Y(n2615)
);
XNOR2X2TS U4072 ( .A(FPMULT_Op_MX[17]), .B(n2278), .Y(n3392) );
XOR2X1TS U4073 ( .A(n2595), .B(n3392), .Y(n2596) );
OAI21X1TS U4074 ( .A0(n2277), .A1(FPMULT_Op_MX[16]), .B0(FPMULT_Op_MX[3]),
.Y(n2598) );
NAND2X1TS U4075 ( .A(n2277), .B(FPMULT_Op_MX[16]), .Y(n2597) );
NAND2X2TS U4076 ( .A(n2598), .B(n2597), .Y(n3391) );
XNOR2X1TS U4077 ( .A(n3392), .B(n3391), .Y(n2599) );
NAND2BX1TS U4078 ( .AN(n3621), .B(n2338), .Y(n2600) );
OAI22X1TS U4079 ( .A0(n3541), .A1(n2336), .B0(n2577), .B1(n2600), .Y(n3639)
);
XNOR2X1TS U4080 ( .A(n2337), .B(n3621), .Y(n2601) );
XNOR2X1TS U4081 ( .A(n3527), .B(n2337), .Y(n2880) );
OAI22X1TS U4082 ( .A0(n3541), .A1(n2601), .B0(n2880), .B1(n2577), .Y(n3638)
);
CMPR32X2TS U4083 ( .A(n2604), .B(n2603), .C(n2602), .CO(n2613), .S(n2591) );
INVX2TS U4084 ( .A(n2883), .Y(n2605) );
AOI21X1TS U4085 ( .A0(n3408), .A1(n2606), .B0(n2605), .Y(n2609) );
NOR2X2TS U4086 ( .A(n2291), .B(FPMULT_Op_MY[5]), .Y(n2884) );
INVX2TS U4087 ( .A(n2884), .Y(n2607) );
NAND2X1TS U4088 ( .A(n2291), .B(FPMULT_Op_MY[5]), .Y(n2882) );
NAND2X1TS U4089 ( .A(n2607), .B(n2882), .Y(n2608) );
CLKXOR2X4TS U4090 ( .A(n2609), .B(n2608), .Y(n3485) );
XNOR2X1TS U4091 ( .A(n3485), .B(n2325), .Y(n3507) );
OAI22X1TS U4092 ( .A0(n3507), .A1(n2332), .B0(n2610), .B1(n3504), .Y(n2611)
);
NOR2X2TS U4093 ( .A(n2612), .B(n2611), .Y(n3368) );
CMPR32X2TS U4094 ( .A(n2615), .B(n2614), .C(n2613), .CO(n2616), .S(n2612) );
INVX2TS U4095 ( .A(n3365), .Y(n2617) );
AOI21X4TS U4096 ( .A0(n3366), .A1(n2493), .B0(n2617), .Y(n3357) );
NAND2X2TS U4097 ( .A(n2196), .B(n2526), .Y(n2620) );
INVX2TS U4098 ( .A(n3362), .Y(n3358) );
NAND2X2TS U4099 ( .A(DP_OP_454J16_123_2743_n356), .B(
DP_OP_454J16_123_2743_n360), .Y(n3359) );
INVX2TS U4100 ( .A(n3359), .Y(n2618) );
OAI21X4TS U4101 ( .A0(n3357), .A1(n2620), .B0(n2619), .Y(n3356) );
NAND2X2TS U4102 ( .A(DP_OP_454J16_123_2743_n349), .B(
DP_OP_454J16_123_2743_n355), .Y(n3354) );
INVX2TS U4103 ( .A(n3354), .Y(n2621) );
AOI21X4TS U4104 ( .A0(n3356), .A1(n2530), .B0(n2621), .Y(n3344) );
OR2X4TS U4105 ( .A(DP_OP_454J16_123_2743_n335), .B(
DP_OP_454J16_123_2743_n342), .Y(n3347) );
NOR2X2TS U4106 ( .A(DP_OP_454J16_123_2743_n343), .B(
DP_OP_454J16_123_2743_n348), .Y(n2622) );
INVX2TS U4107 ( .A(n2622), .Y(n3351) );
NAND2X2TS U4108 ( .A(n3347), .B(n3351), .Y(n2625) );
NAND2X2TS U4109 ( .A(DP_OP_454J16_123_2743_n343), .B(
DP_OP_454J16_123_2743_n348), .Y(n3350) );
NAND2X2TS U4110 ( .A(DP_OP_454J16_123_2743_n335), .B(
DP_OP_454J16_123_2743_n342), .Y(n3346) );
INVX2TS U4111 ( .A(n3346), .Y(n2623) );
AOI21X2TS U4112 ( .A0(n3347), .A1(n3345), .B0(n2623), .Y(n2624) );
OAI21X4TS U4113 ( .A0(n3344), .A1(n2625), .B0(n2624), .Y(n3338) );
NOR2X2TS U4114 ( .A(n3339), .B(n3521), .Y(n2627) );
NAND2X2TS U4115 ( .A(DP_OP_454J16_123_2743_n327), .B(
DP_OP_454J16_123_2743_n334), .Y(n3522) );
NAND2X2TS U4116 ( .A(DP_OP_454J16_123_2743_n319), .B(
DP_OP_454J16_123_2743_n326), .Y(n3340) );
OAI21X2TS U4117 ( .A0(n3339), .A1(n3522), .B0(n3340), .Y(n2626) );
AOI21X4TS U4118 ( .A0(n3338), .A1(n2627), .B0(n2626), .Y(n2706) );
INVX4TS U4119 ( .A(n2706), .Y(n3337) );
NOR2X4TS U4120 ( .A(DP_OP_454J16_123_2743_n310), .B(
DP_OP_454J16_123_2743_n318), .Y(n2873) );
NOR2X4TS U4121 ( .A(n2875), .B(n2873), .Y(n2697) );
OAI21X4TS U4122 ( .A0(n2875), .A1(n3334), .B0(n2876), .Y(n2702) );
INVX2TS U4123 ( .A(n2696), .Y(n2628) );
NAND2X1TS U4124 ( .A(n2628), .B(n2699), .Y(n2629) );
INVX2TS U4125 ( .A(n2697), .Y(n2631) );
NOR2X1TS U4126 ( .A(n2631), .B(n2696), .Y(n2634) );
INVX2TS U4127 ( .A(n2702), .Y(n2632) );
NOR2X4TS U4128 ( .A(DP_OP_454J16_123_2743_n285), .B(
DP_OP_454J16_123_2743_n292), .Y(n2700) );
INVX2TS U4129 ( .A(n2700), .Y(n2635) );
NAND2X1TS U4130 ( .A(n2635), .B(n2698), .Y(n2636) );
NOR2X2TS U4131 ( .A(mult_x_219_n223), .B(mult_x_219_n230), .Y(n3196) );
NOR2X2TS U4132 ( .A(mult_x_219_n231), .B(mult_x_219_n238), .Y(n3289) );
NOR2X2TS U4133 ( .A(mult_x_219_n252), .B(mult_x_219_n256), .Y(n3210) );
NOR2X2TS U4134 ( .A(mult_x_219_n257), .B(mult_x_219_n261), .Y(n3215) );
NOR2X1TS U4135 ( .A(n3210), .B(n3215), .Y(n2673) );
BUFX3TS U4136 ( .A(FPMULT_Op_MY[13]), .Y(n3318) );
XNOR2X1TS U4137 ( .A(n2312), .B(n3318), .Y(n2639) );
XNOR2X1TS U4138 ( .A(n2312), .B(FPMULT_Op_MY[14]), .Y(n2643) );
OAI22X1TS U4139 ( .A0(n3323), .A1(n2639), .B0(n2643), .B1(n2520), .Y(n2642)
);
NOR2BX1TS U4140 ( .AN(n3324), .B(n2354), .Y(n2641) );
NOR2X1TS U4141 ( .A(n2642), .B(n2641), .Y(n3236) );
OAI22X1TS U4142 ( .A0(n3323), .A1(n3324), .B0(n2639), .B1(n2520), .Y(n3286)
);
NAND2X1TS U4143 ( .A(n2640), .B(n3323), .Y(n3285) );
NAND2X1TS U4144 ( .A(n3286), .B(n3285), .Y(n3287) );
NAND2X1TS U4145 ( .A(n2642), .B(n2641), .Y(n3237) );
OAI21X1TS U4146 ( .A0(n3236), .A1(n3287), .B0(n3237), .Y(n3234) );
XNOR2X1TS U4147 ( .A(n2312), .B(n2289), .Y(n2651) );
OAI22X1TS U4148 ( .A0(n3323), .A1(n2643), .B0(n2651), .B1(n2539), .Y(n2654)
);
XOR2X1TS U4149 ( .A(n2362), .B(FPMULT_Op_MX[14]), .Y(n2644) );
XNOR2X1TS U4150 ( .A(n2363), .B(n3324), .Y(n2645) );
XNOR2X1TS U4151 ( .A(n2363), .B(n3318), .Y(n2652) );
OAI22X1TS U4152 ( .A0(n2423), .A1(n2645), .B0(n2652), .B1(n2355), .Y(n2653)
);
OAI22X1TS U4153 ( .A0(n2424), .A1(n2237), .B0(n2355), .B1(n2646), .Y(n2647)
);
INVX2TS U4154 ( .A(n3233), .Y(n2649) );
AOI21X1TS U4155 ( .A0(n3234), .A1(n2504), .B0(n2649), .Y(n3231) );
NOR2BX1TS U4156 ( .AN(n2444), .B(n2357), .Y(n2664) );
XNOR2X1TS U4157 ( .A(n2312), .B(n2290), .Y(n2660) );
OAI22X1TS U4158 ( .A0(n3284), .A1(n2651), .B0(n2660), .B1(n2520), .Y(n2663)
);
XNOR2X1TS U4159 ( .A(n2363), .B(FPMULT_Op_MY[14]), .Y(n2657) );
OAI22X1TS U4160 ( .A0(n2424), .A1(n2652), .B0(n2657), .B1(n2354), .Y(n2662)
);
NOR2X1TS U4161 ( .A(n2656), .B(n2655), .Y(n3228) );
NAND2X1TS U4162 ( .A(n2656), .B(n2655), .Y(n3229) );
OAI21X2TS U4163 ( .A0(n3231), .A1(n3228), .B0(n3229), .Y(n3227) );
XNOR2X1TS U4164 ( .A(n2363), .B(n2289), .Y(n3281) );
OAI22X1TS U4165 ( .A0(n2424), .A1(n2657), .B0(n3281), .B1(n2355), .Y(n2670)
);
XOR2X1TS U4166 ( .A(n2364), .B(FPMULT_Op_MX[16]), .Y(n2658) );
XNOR2X1TS U4167 ( .A(n2365), .B(n2444), .Y(n2659) );
XNOR2X1TS U4168 ( .A(n2364), .B(n3318), .Y(n3275) );
OAI22X1TS U4169 ( .A0(n2425), .A1(n2659), .B0(n3275), .B1(n2357), .Y(n2669)
);
XNOR2X1TS U4170 ( .A(n2312), .B(n2207), .Y(n3283) );
OAI22X1TS U4171 ( .A0(n3323), .A1(n2660), .B0(n3283), .B1(n2520), .Y(n3331)
);
OAI22X1TS U4172 ( .A0(n3308), .A1(n2246), .B0(n2356), .B1(n2661), .Y(n3330)
);
CMPR32X2TS U4173 ( .A(n2664), .B(n2663), .C(n2662), .CO(n2665), .S(n2656) );
NAND2X1TS U4174 ( .A(n2666), .B(n2665), .Y(n3225) );
INVX2TS U4175 ( .A(n3225), .Y(n2667) );
AOI21X4TS U4176 ( .A0(n3227), .A1(n2506), .B0(n2667), .Y(n3223) );
CMPR32X2TS U4177 ( .A(n2670), .B(n2669), .C(n2668), .CO(n2671), .S(n2666) );
NAND2X1TS U4178 ( .A(mult_x_219_n262), .B(n2671), .Y(n3221) );
NAND2X1TS U4179 ( .A(mult_x_219_n257), .B(mult_x_219_n261), .Y(n3216) );
NAND2X1TS U4180 ( .A(mult_x_219_n252), .B(mult_x_219_n256), .Y(n3211) );
OAI21X1TS U4181 ( .A0(n3210), .A1(n3216), .B0(n3211), .Y(n2672) );
AOI21X4TS U4182 ( .A0(n2673), .A1(n3209), .B0(n2672), .Y(n3201) );
NAND2X1TS U4183 ( .A(n2523), .B(n2522), .Y(n2676) );
NAND2X1TS U4184 ( .A(mult_x_219_n245), .B(mult_x_219_n251), .Y(n3206) );
INVX2TS U4185 ( .A(n3206), .Y(n3202) );
NAND2X1TS U4186 ( .A(mult_x_219_n239), .B(mult_x_219_n244), .Y(n3203) );
INVX2TS U4187 ( .A(n3203), .Y(n2674) );
AOI21X1TS U4188 ( .A0(n2523), .A1(n3202), .B0(n2674), .Y(n2675) );
OAI21X4TS U4189 ( .A0(n3201), .A1(n2676), .B0(n2675), .Y(n3195) );
NAND2X2TS U4190 ( .A(mult_x_219_n231), .B(mult_x_219_n238), .Y(n3290) );
NAND2X1TS U4191 ( .A(mult_x_219_n223), .B(mult_x_219_n230), .Y(n3197) );
OAI21X1TS U4192 ( .A0(n3196), .A1(n3290), .B0(n3197), .Y(n2677) );
NOR2X2TS U4193 ( .A(mult_x_219_n204), .B(mult_x_219_n213), .Y(n3186) );
NOR2X2TS U4194 ( .A(n3184), .B(n3186), .Y(n3173) );
NOR2X2TS U4195 ( .A(mult_x_219_n196), .B(mult_x_219_n203), .Y(n3179) );
NOR2X2TS U4196 ( .A(mult_x_219_n188), .B(mult_x_219_n195), .Y(n3174) );
NAND2X2TS U4197 ( .A(n3173), .B(n2680), .Y(n2682) );
NAND2X2TS U4198 ( .A(mult_x_219_n214), .B(mult_x_219_n222), .Y(n3191) );
NAND2X1TS U4199 ( .A(mult_x_219_n204), .B(mult_x_219_n213), .Y(n3187) );
NAND2X1TS U4200 ( .A(mult_x_219_n196), .B(mult_x_219_n203), .Y(n3180) );
NAND2X1TS U4201 ( .A(mult_x_219_n188), .B(mult_x_219_n195), .Y(n3175) );
NOR2X2TS U4202 ( .A(mult_x_219_n181), .B(mult_x_219_n175), .Y(n3161) );
NOR2X2TS U4203 ( .A(mult_x_219_n169), .B(mult_x_219_n165), .Y(n3148) );
NOR2X1TS U4204 ( .A(n3147), .B(n3148), .Y(n2685) );
NAND2X1TS U4205 ( .A(mult_x_219_n182), .B(mult_x_219_n187), .Y(n3167) );
NAND2X1TS U4206 ( .A(mult_x_219_n181), .B(mult_x_219_n175), .Y(n3162) );
OAI21X2TS U4207 ( .A0(n3167), .A1(n3161), .B0(n3162), .Y(n3154) );
NAND2X1TS U4208 ( .A(mult_x_219_n174), .B(mult_x_219_n170), .Y(n3157) );
INVX2TS U4209 ( .A(n3157), .Y(n2683) );
NAND2X1TS U4210 ( .A(mult_x_219_n169), .B(mult_x_219_n165), .Y(n3149) );
NOR2X1TS U4211 ( .A(mult_x_219_n162), .B(mult_x_219_n164), .Y(n3140) );
NAND2X1TS U4212 ( .A(mult_x_219_n162), .B(mult_x_219_n164), .Y(n3141) );
INVX2TS U4213 ( .A(n2340), .Y(n2688) );
NAND2X1TS U4214 ( .A(mult_x_219_n161), .B(n2686), .Y(n3136) );
INVX2TS U4215 ( .A(n3136), .Y(n2687) );
AOI21X4TS U4216 ( .A0(n3139), .A1(n3137), .B0(n2687), .Y(n2695) );
CMPR32X2TS U4217 ( .A(n2515), .B(n2688), .C(mult_x_219_n160), .CO(n2691),
.S(n2686) );
CLKAND2X2TS U4218 ( .A(n2201), .B(n2339), .Y(n2689) );
XNOR2X1TS U4219 ( .A(n2689), .B(n4718), .Y(n2690) );
NAND2X1TS U4220 ( .A(n2691), .B(n2690), .Y(n2692) );
NAND2X1TS U4221 ( .A(n2693), .B(n2692), .Y(n2694) );
XOR2X2TS U4222 ( .A(n2695), .B(n2694), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N23) );
OA21X4TS U4223 ( .A0(n2706), .A1(n2705), .B0(n2704), .Y(n2707) );
INVX12TS U4224 ( .A(n2707), .Y(n3643) );
OAI21X4TS U4225 ( .A0(n3640), .A1(n3644), .B0(n3645), .Y(n3593) );
AOI21X2TS U4226 ( .A0(n3643), .A1(n3589), .B0(n3593), .Y(n2709) );
NAND2X2TS U4227 ( .A(DP_OP_454J16_123_2743_n271), .B(
DP_OP_454J16_123_2743_n267), .Y(n2903) );
NAND2X1TS U4228 ( .A(n2232), .B(n2903), .Y(n2708) );
INVX2TS U4229 ( .A(n3622), .Y(n2713) );
OAI21X1TS U4230 ( .A0(n2292), .A1(FPMULT_Op_MX[22]), .B0(FPMULT_Op_MX[9]),
.Y(n2711) );
NAND2X1TS U4231 ( .A(n2292), .B(FPMULT_Op_MX[22]), .Y(n2710) );
NAND2X2TS U4232 ( .A(n2711), .B(n2710), .Y(n2714) );
INVX2TS U4233 ( .A(n3527), .Y(n3628) );
INVX2TS U4234 ( .A(n3557), .Y(n3417) );
INVX2TS U4235 ( .A(n3477), .Y(n3519) );
OAI22X1TS U4236 ( .A0(n3519), .A1(n2314), .B0(n2713), .B1(n2712), .Y(n2727)
);
NOR2X1TS U4237 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[21]), .Y(n2716) );
XNOR2X1TS U4238 ( .A(n2722), .B(n2716), .Y(n2720) );
XNOR2X2TS U4239 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[21]), .Y(n2894) );
OAI21X1TS U4240 ( .A0(FPMULT_Op_MX[8]), .A1(FPMULT_Op_MX[20]), .B0(
FPMULT_Op_MX[7]), .Y(n2718) );
NAND2X1TS U4241 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[20]), .Y(n2717) );
XOR2X1TS U4242 ( .A(FPMULT_Op_MX[21]), .B(n2214), .Y(n2723) );
NOR2X1TS U4243 ( .A(n2723), .B(n2722), .Y(n2724) );
XOR2X1TS U4244 ( .A(n2724), .B(FPMULT_Op_MX[11]), .Y(n2725) );
OAI22X1TS U4245 ( .A0(n3449), .A1(n2391), .B0(n3631), .B1(n3629), .Y(n3416)
);
ADDFHX2TS U4246 ( .A(n3417), .B(n2727), .CI(n2726), .CO(
DP_OP_454J16_123_2743_n304), .S(DP_OP_454J16_123_2743_n305) );
BUFX3TS U4247 ( .A(n5818), .Y(n5477) );
INVX2TS U4248 ( .A(FPADDSUB_intDX_EWSW[5]), .Y(n2734) );
OAI2BB1X1TS U4249 ( .A0N(n2734), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n2728) );
OAI22X1TS U4250 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2728), .B0(n2734), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n2743) );
INVX2TS U4251 ( .A(FPADDSUB_intDX_EWSW[7]), .Y(n2739) );
OAI2BB1X1TS U4252 ( .A0N(n2739), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n2729) );
OAI22X1TS U4253 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n2729), .B0(n2739), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n2742) );
INVX2TS U4254 ( .A(FPADDSUB_intDX_EWSW[4]), .Y(n2737) );
OAI2BB2XLTS U4255 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n2730), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n5816), .Y(n2732) );
INVX2TS U4256 ( .A(FPADDSUB_intDX_EWSW[6]), .Y(n2738) );
AOI22X1TS U4257 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n2739), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n2738), .Y(n2740) );
INVX2TS U4258 ( .A(FPADDSUB_intDX_EWSW[10]), .Y(n2745) );
AOI21X1TS U4259 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n2745), .B0(n2751), .Y(
n2756) );
OAI2BB2XLTS U4260 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n2750), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n2494), .Y(n2763) );
AOI22X1TS U4261 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n5817), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n2752), .Y(n2759) );
AOI21X1TS U4262 ( .A0(n2755), .A1(n2754), .B0(n2758), .Y(n2757) );
OAI2BB2XLTS U4263 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n2760), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n2478), .Y(n2761) );
NOR2X1TS U4264 ( .A(n2485), .B(FPADDSUB_intDX_EWSW[17]), .Y(n2773) );
INVX2TS U4265 ( .A(FPADDSUB_intDX_EWSW[16]), .Y(n2766) );
OAI21X1TS U4266 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n2480), .B0(n2775), .Y(
n2779) );
AOI211X1TS U4267 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n2766), .B0(n2778),
.C0(n2779), .Y(n2767) );
OAI2BB2XLTS U4268 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n2772), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n2461), .Y(n2783) );
AOI22X1TS U4269 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n2485), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n2774), .Y(n2777) );
OAI32X1TS U4270 ( .A0(n2779), .A1(n2778), .A2(n2777), .B0(n2776), .B1(n2778),
.Y(n2782) );
OAI2BB2XLTS U4271 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n2780), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n2469), .Y(n2781) );
AOI211X1TS U4272 ( .A0(n2784), .A1(n2783), .B0(n2782), .C0(n2781), .Y(n2787)
);
OAI21X1TS U4273 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n5905), .B0(n2791), .Y(
n2794) );
INVX2TS U4274 ( .A(FPADDSUB_intDX_EWSW[28]), .Y(n2797) );
NOR2X1TS U4275 ( .A(n2256), .B(FPADDSUB_intDX_EWSW[30]), .Y(n2799) );
NOR2X1TS U4276 ( .A(n2489), .B(FPADDSUB_intDX_EWSW[29]), .Y(n2796) );
NAND4BBX1TS U4277 ( .AN(n2794), .BN(n2789), .C(n2801), .D(n2785), .Y(n2786)
);
AOI22X1TS U4278 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n5906), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n2790), .Y(n2795) );
OAI211X1TS U4279 ( .A0(n2795), .A1(n2794), .B0(n2793), .C0(n2792), .Y(n2802)
);
NOR3X1TS U4280 ( .A(n2797), .B(n2796), .C(FPADDSUB_intDY_EWSW[28]), .Y(n2798) );
CLKBUFX2TS U4281 ( .A(n5818), .Y(n4521) );
AOI22X1TS U4282 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n4542), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n4521), .Y(n2805) );
BUFX3TS U4283 ( .A(n5818), .Y(n4548) );
AOI22X1TS U4284 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n4542), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n4548), .Y(n2807) );
NOR2X2TS U4285 ( .A(mult_x_254_n216), .B(mult_x_254_n224), .Y(n2957) );
NOR2X2TS U4286 ( .A(n2959), .B(n2957), .Y(n2946) );
NOR2X2TS U4287 ( .A(mult_x_254_n198), .B(mult_x_254_n205), .Y(n2952) );
NOR2X2TS U4288 ( .A(mult_x_254_n190), .B(mult_x_254_n197), .Y(n2947) );
NOR2X2TS U4289 ( .A(n2952), .B(n2947), .Y(n2850) );
NAND2X1TS U4290 ( .A(n2977), .B(n2503), .Y(n2846) );
NOR2X2TS U4291 ( .A(mult_x_254_n254), .B(mult_x_254_n258), .Y(n2984) );
NOR2X2TS U4292 ( .A(mult_x_254_n259), .B(mult_x_254_n263), .Y(n2989) );
NOR2X1TS U4293 ( .A(n2984), .B(n2989), .Y(n2843) );
XOR2X1TS U4294 ( .A(FPMULT_Op_MY[2]), .B(n2330), .Y(n2808) );
XNOR2X1TS U4295 ( .A(n2330), .B(FPMULT_Op_MX[2]), .Y(n2813) );
XNOR2X1TS U4296 ( .A(n2331), .B(FPMULT_Op_MX[3]), .Y(n3057) );
OAI22X1TS U4297 ( .A0(n2431), .A1(n2813), .B0(n2367), .B1(n3057), .Y(n2840)
);
XOR2X1TS U4298 ( .A(FPMULT_Op_MY[4]), .B(n2396), .Y(n2810) );
XNOR2X1TS U4299 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[3]), .Y(n2809) );
XNOR2X1TS U4300 ( .A(n2396), .B(n2442), .Y(n2811) );
BUFX3TS U4301 ( .A(FPMULT_Op_MX[1]), .Y(n5681) );
XNOR2X1TS U4302 ( .A(n2397), .B(n5681), .Y(n3050) );
OAI22X1TS U4303 ( .A0(n3112), .A1(n2811), .B0(n2369), .B1(n3050), .Y(n2839)
);
INVX2TS U4304 ( .A(n2397), .Y(n3044) );
OAI22X1TS U4305 ( .A0(n3112), .A1(n3044), .B0(n2369), .B1(n2812), .Y(n2872)
);
XNOR2X1TS U4306 ( .A(n2345), .B(n2209), .Y(n2814) );
XNOR2X1TS U4307 ( .A(FPMULT_Op_MY[1]), .B(n2212), .Y(n3058) );
OAI22X1TS U4308 ( .A0(n3133), .A1(n2814), .B0(n3058), .B1(n2230), .Y(n2871)
);
NOR2BX1TS U4309 ( .AN(n2442), .B(n2370), .Y(n2817) );
XNOR2X1TS U4310 ( .A(n2330), .B(n5681), .Y(n2819) );
OAI22X1TS U4311 ( .A0(n2430), .A1(n2819), .B0(n2366), .B1(n2813), .Y(n2816)
);
XNOR2X1TS U4312 ( .A(n2345), .B(FPMULT_Op_MX[3]), .Y(n2828) );
OAI22X1TS U4313 ( .A0(n3133), .A1(n2828), .B0(n2814), .B1(n2326), .Y(n2815)
);
CMPR32X2TS U4314 ( .A(n2817), .B(n2816), .C(n2815), .CO(n2834), .S(n2833) );
OAI22X1TS U4315 ( .A0(n2431), .A1(n2483), .B0(n2367), .B1(n2818), .Y(n2827)
);
XNOR2X1TS U4316 ( .A(n2331), .B(n3128), .Y(n2820) );
OAI22X1TS U4317 ( .A0(n2431), .A1(n2820), .B0(n2366), .B1(n2819), .Y(n2826)
);
NOR2X2TS U4318 ( .A(n2833), .B(n2832), .Y(n3005) );
NOR2X1TS U4319 ( .A(n3000), .B(n3005), .Y(n2837) );
XNOR2X1TS U4320 ( .A(n2345), .B(n5681), .Y(n2821) );
XNOR2X1TS U4321 ( .A(n2345), .B(FPMULT_Op_MX[2]), .Y(n2829) );
OAI22X1TS U4322 ( .A0(n3059), .A1(n2821), .B0(n2829), .B1(n2326), .Y(n2824)
);
NOR2BX1TS U4323 ( .AN(n2442), .B(n2367), .Y(n2823) );
OAI22X1TS U4324 ( .A0(n3133), .A1(n3128), .B0(n2821), .B1(n2230), .Y(n3061)
);
NAND2X1TS U4325 ( .A(n2822), .B(n3133), .Y(n3060) );
NAND2X1TS U4326 ( .A(n3061), .B(n3060), .Y(n3062) );
INVX2TS U4327 ( .A(n3062), .Y(n3017) );
NAND2X1TS U4328 ( .A(n2824), .B(n2823), .Y(n3015) );
INVX2TS U4329 ( .A(n3015), .Y(n2825) );
AOI21X1TS U4330 ( .A0(n3016), .A1(n3017), .B0(n2825), .Y(n3013) );
ADDHX1TS U4331 ( .A(n2827), .B(n2826), .CO(n2832), .S(n2831) );
OAI22X1TS U4332 ( .A0(n3133), .A1(n2829), .B0(n2828), .B1(n2326), .Y(n2830)
);
NOR2X1TS U4333 ( .A(n2831), .B(n2830), .Y(n3010) );
NAND2X1TS U4334 ( .A(n2831), .B(n2830), .Y(n3011) );
OAI21X1TS U4335 ( .A0(n3013), .A1(n3010), .B0(n3011), .Y(n2999) );
NAND2X1TS U4336 ( .A(n2833), .B(n2832), .Y(n3006) );
NAND2X1TS U4337 ( .A(n2835), .B(n2834), .Y(n3001) );
OAI21X1TS U4338 ( .A0(n3000), .A1(n3006), .B0(n3001), .Y(n2836) );
CMPR32X2TS U4339 ( .A(n2840), .B(n2839), .C(n2838), .CO(n2841), .S(n2835) );
NOR2X1TS U4340 ( .A(mult_x_254_n264), .B(n2841), .Y(n2994) );
NAND2X1TS U4341 ( .A(mult_x_254_n264), .B(n2841), .Y(n2995) );
OAI21X2TS U4342 ( .A0(n2997), .A1(n2994), .B0(n2995), .Y(n2983) );
NAND2X1TS U4343 ( .A(mult_x_254_n254), .B(mult_x_254_n258), .Y(n2985) );
OAI21X1TS U4344 ( .A0(n2984), .A1(n2990), .B0(n2985), .Y(n2842) );
NAND2X1TS U4345 ( .A(mult_x_254_n247), .B(mult_x_254_n253), .Y(n2980) );
INVX2TS U4346 ( .A(n2980), .Y(n2975) );
NAND2X1TS U4347 ( .A(mult_x_254_n241), .B(mult_x_254_n246), .Y(n2976) );
INVX2TS U4348 ( .A(n2976), .Y(n2844) );
AOI21X1TS U4349 ( .A0(n2977), .A1(n2975), .B0(n2844), .Y(n2845) );
NOR2X2TS U4350 ( .A(mult_x_254_n225), .B(mult_x_254_n232), .Y(n2969) );
NOR2X2TS U4351 ( .A(mult_x_254_n233), .B(mult_x_254_n240), .Y(n3070) );
NAND2X1TS U4352 ( .A(mult_x_254_n225), .B(mult_x_254_n232), .Y(n2970) );
OAI21X1TS U4353 ( .A0(n2969), .A1(n3071), .B0(n2970), .Y(n2847) );
NAND2X2TS U4354 ( .A(mult_x_254_n216), .B(mult_x_254_n224), .Y(n2964) );
NAND2X1TS U4355 ( .A(mult_x_254_n206), .B(mult_x_254_n215), .Y(n2960) );
OAI21X4TS U4356 ( .A0(n2959), .A1(n2964), .B0(n2960), .Y(n2945) );
NAND2X1TS U4357 ( .A(mult_x_254_n198), .B(mult_x_254_n205), .Y(n2953) );
NAND2X1TS U4358 ( .A(mult_x_254_n190), .B(mult_x_254_n197), .Y(n2948) );
OAI21X1TS U4359 ( .A0(n2947), .A1(n2953), .B0(n2948), .Y(n2849) );
NOR2X2TS U4360 ( .A(mult_x_254_n184), .B(mult_x_254_n189), .Y(n2939) );
NOR2X2TS U4361 ( .A(mult_x_254_n183), .B(mult_x_254_n177), .Y(n2934) );
NOR2X2TS U4362 ( .A(mult_x_254_n171), .B(mult_x_254_n167), .Y(n2921) );
NAND2X2TS U4363 ( .A(mult_x_254_n184), .B(mult_x_254_n189), .Y(n2940) );
NAND2X1TS U4364 ( .A(mult_x_254_n183), .B(mult_x_254_n177), .Y(n2935) );
NAND2X1TS U4365 ( .A(mult_x_254_n176), .B(mult_x_254_n172), .Y(n2930) );
INVX2TS U4366 ( .A(n2930), .Y(n2853) );
NAND2X1TS U4367 ( .A(mult_x_254_n171), .B(mult_x_254_n167), .Y(n2922) );
AOI21X4TS U4368 ( .A0(n2918), .A1(n2855), .B0(n2854), .Y(n2917) );
NOR2X1TS U4369 ( .A(mult_x_254_n166), .B(mult_x_254_n164), .Y(n2913) );
NAND2X1TS U4370 ( .A(mult_x_254_n166), .B(mult_x_254_n164), .Y(n2914) );
OAI21X4TS U4371 ( .A0(n2917), .A1(n2913), .B0(n2914), .Y(n2912) );
NOR2X1TS U4372 ( .A(DP_OP_454J16_123_2743_n727), .B(n2519), .Y(n2864) );
INVX2TS U4373 ( .A(n2864), .Y(n2861) );
XOR2X1TS U4374 ( .A(FPMULT_Op_MY[10]), .B(n2346), .Y(n2857) );
XNOR2X1TS U4375 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[9]), .Y(n2856) );
XNOR2X1TS U4376 ( .A(FPMULT_Op_MY[11]), .B(n2446), .Y(n3020) );
OAI22X1TS U4377 ( .A0(n2318), .A1(n3020), .B0(n3032), .B1(
DP_OP_454J16_123_2743_n727), .Y(n2860) );
NAND2X1TS U4378 ( .A(mult_x_254_n163), .B(n2858), .Y(n2909) );
INVX2TS U4379 ( .A(n2909), .Y(n2859) );
AOI21X4TS U4380 ( .A0(n2912), .A1(n2910), .B0(n2859), .Y(n2870) );
CMPR32X2TS U4381 ( .A(n2861), .B(n2860), .C(mult_x_254_n162), .CO(n2866),
.S(n2858) );
NOR2X1TS U4382 ( .A(DP_OP_454J16_123_2743_n727), .B(n2455), .Y(n2863) );
NAND2X1TS U4383 ( .A(n2866), .B(n2865), .Y(n2867) );
NAND2X1TS U4384 ( .A(n2868), .B(n2867), .Y(n2869) );
INVX2TS U4385 ( .A(n2873), .Y(n3335) );
INVX2TS U4386 ( .A(n3334), .Y(n2874) );
INVX2TS U4387 ( .A(n2875), .Y(n2877) );
NAND2X1TS U4388 ( .A(n2877), .B(n2876), .Y(n2878) );
XNOR2X1TS U4389 ( .A(n3622), .B(n2337), .Y(n3478) );
NOR2X4TS U4390 ( .A(n2415), .B(FPMULT_Op_MY[7]), .Y(n3409) );
NAND2X1TS U4391 ( .A(n2415), .B(FPMULT_Op_MY[7]), .Y(n3410) );
OAI21X1TS U4392 ( .A0(n3409), .A1(n3403), .B0(n3410), .Y(n2890) );
NOR2X2TS U4393 ( .A(n2881), .B(n2884), .Y(n3400) );
NOR2X4TS U4394 ( .A(n3404), .B(n3409), .Y(n2885) );
NAND2X2TS U4395 ( .A(n3400), .B(n2885), .Y(n2888) );
OR2X8TS U4396 ( .A(n2890), .B(n2889), .Y(n3441) );
NOR2X2TS U4397 ( .A(n2288), .B(FPMULT_Op_MY[9]), .Y(n3420) );
INVX2TS U4398 ( .A(n3437), .Y(n3426) );
NAND2X1TS U4399 ( .A(n2288), .B(FPMULT_Op_MY[9]), .Y(n3421) );
NAND2X1TS U4400 ( .A(n3436), .B(DP_OP_454J16_123_2743_n727), .Y(n2891) );
AOI21X4TS U4401 ( .A0(n3441), .A1(n3440), .B0(n2529), .Y(n3581) );
INVX6TS U4402 ( .A(n3581), .Y(n3492) );
XNOR2X1TS U4403 ( .A(n3492), .B(n2349), .Y(n3451) );
NOR2X1TS U4404 ( .A(n3247), .B(n2897), .Y(n2895) );
XOR2X1TS U4405 ( .A(n2895), .B(n2894), .Y(n2902) );
NOR2X1TS U4406 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[7]), .Y(n2896) );
XNOR2X1TS U4407 ( .A(n2897), .B(n2896), .Y(n2901) );
XNOR2X2TS U4408 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[7]), .Y(n3387) );
OAI21X2TS U4409 ( .A0(n2279), .A1(FPMULT_Op_MX[18]), .B0(n2278), .Y(n2899)
);
NAND2X1TS U4410 ( .A(n2279), .B(FPMULT_Op_MX[18]), .Y(n2898) );
NAND2X2TS U4411 ( .A(n3387), .B(n3384), .Y(n2900) );
XNOR2X1TS U4412 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[2]), .Y(n3029) );
XNOR2X1TS U4413 ( .A(n2346), .B(FPMULT_Op_MX[3]), .Y(n3028) );
XNOR2X1TS U4414 ( .A(FPMULT_Op_MY[11]), .B(n2209), .Y(n3027) );
XNOR2X1TS U4415 ( .A(n2346), .B(n2212), .Y(n3026) );
NOR2X4TS U4416 ( .A(DP_OP_454J16_123_2743_n266), .B(
DP_OP_454J16_123_2743_n262), .Y(n3603) );
INVX2TS U4417 ( .A(n2903), .Y(n3567) );
AOI21X2TS U4418 ( .A0(n3593), .A1(n2232), .B0(n3567), .Y(n3600) );
NAND2X2TS U4419 ( .A(DP_OP_454J16_123_2743_n266), .B(
DP_OP_454J16_123_2743_n262), .Y(n3604) );
OAI21X2TS U4420 ( .A0(n3600), .A1(n3603), .B0(n3604), .Y(n2904) );
NOR2X4TS U4421 ( .A(DP_OP_454J16_123_2743_n259), .B(
DP_OP_454J16_123_2743_n261), .Y(n3565) );
INVX2TS U4422 ( .A(n3565), .Y(n2906) );
NAND2X1TS U4423 ( .A(n2906), .B(n3564), .Y(n2907) );
NAND2X1TS U4424 ( .A(n2910), .B(n2909), .Y(n2911) );
XNOR2X1TS U4425 ( .A(n2912), .B(n2911), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N22) );
INVX2TS U4426 ( .A(n2913), .Y(n2915) );
NAND2X1TS U4427 ( .A(n2915), .B(n2914), .Y(n2916) );
OAI21X1TS U4428 ( .A0(n2943), .A1(n2920), .B0(n2919), .Y(n2925) );
INVX2TS U4429 ( .A(n2921), .Y(n2923) );
NAND2X1TS U4430 ( .A(n2923), .B(n2922), .Y(n2924) );
XNOR2X1TS U4431 ( .A(n2925), .B(n2924), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N20) );
INVX2TS U4432 ( .A(n2927), .Y(n2928) );
OAI21X1TS U4433 ( .A0(n2943), .A1(n2929), .B0(n2928), .Y(n2933) );
NAND2X1TS U4434 ( .A(n2931), .B(n2930), .Y(n2932) );
XNOR2X1TS U4435 ( .A(n2933), .B(n2932), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N19) );
INVX2TS U4436 ( .A(n2934), .Y(n2936) );
NAND2X1TS U4437 ( .A(n2936), .B(n2935), .Y(n2937) );
XNOR2X1TS U4438 ( .A(n2938), .B(n2937), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N18) );
INVX2TS U4439 ( .A(n2939), .Y(n2941) );
NAND2X1TS U4440 ( .A(n2941), .B(n2940), .Y(n2942) );
INVX2TS U4441 ( .A(n2947), .Y(n2949) );
NAND2X1TS U4442 ( .A(n2949), .B(n2948), .Y(n2950) );
XNOR2X1TS U4443 ( .A(n2951), .B(n2950), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N16) );
INVX2TS U4444 ( .A(n2952), .Y(n2954) );
NAND2X1TS U4445 ( .A(n2954), .B(n2953), .Y(n2955) );
INVX2TS U4446 ( .A(n2957), .Y(n2965) );
INVX2TS U4447 ( .A(n2964), .Y(n2958) );
AOI21X1TS U4448 ( .A0(n2967), .A1(n2965), .B0(n2958), .Y(n2963) );
INVX2TS U4449 ( .A(n2959), .Y(n2961) );
NAND2X1TS U4450 ( .A(n2961), .B(n2960), .Y(n2962) );
NAND2X1TS U4451 ( .A(n2965), .B(n2964), .Y(n2966) );
XNOR2X1TS U4452 ( .A(n2967), .B(n2966), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N13) );
INVX2TS U4453 ( .A(n2968), .Y(n3074) );
INVX2TS U4454 ( .A(n2969), .Y(n2971) );
NAND2X1TS U4455 ( .A(n2971), .B(n2970), .Y(n2972) );
XNOR2X1TS U4456 ( .A(n2973), .B(n2972), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N12) );
INVX2TS U4457 ( .A(n2974), .Y(n2982) );
AOI21X1TS U4458 ( .A0(n2982), .A1(n2503), .B0(n2975), .Y(n2979) );
NAND2X1TS U4459 ( .A(n2977), .B(n2976), .Y(n2978) );
NAND2X1TS U4460 ( .A(n2503), .B(n2980), .Y(n2981) );
XNOR2X1TS U4461 ( .A(n2982), .B(n2981), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N9) );
INVX2TS U4462 ( .A(n2983), .Y(n2993) );
INVX2TS U4463 ( .A(n2984), .Y(n2986) );
NAND2X1TS U4464 ( .A(n2986), .B(n2985), .Y(n2987) );
XNOR2X1TS U4465 ( .A(n2988), .B(n2987), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N8) );
INVX2TS U4466 ( .A(n2989), .Y(n2991) );
NAND2X1TS U4467 ( .A(n2991), .B(n2990), .Y(n2992) );
INVX2TS U4468 ( .A(n2994), .Y(n2996) );
NAND2X1TS U4469 ( .A(n2996), .B(n2995), .Y(n2998) );
INVX2TS U4470 ( .A(n2999), .Y(n3009) );
INVX2TS U4471 ( .A(n3000), .Y(n3002) );
NAND2X1TS U4472 ( .A(n3002), .B(n3001), .Y(n3003) );
XNOR2X1TS U4473 ( .A(n3004), .B(n3003), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N5) );
INVX2TS U4474 ( .A(n3005), .Y(n3007) );
NAND2X1TS U4475 ( .A(n3007), .B(n3006), .Y(n3008) );
INVX2TS U4476 ( .A(n3010), .Y(n3012) );
NAND2X1TS U4477 ( .A(n3012), .B(n3011), .Y(n3014) );
NAND2X1TS U4478 ( .A(n3016), .B(n3015), .Y(n3018) );
XNOR2X1TS U4479 ( .A(n3018), .B(n3017), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N2) );
OAI22X1TS U4480 ( .A0(n2317), .A1(DP_OP_454J16_123_2743_n727), .B0(n2373),
.B1(n3019), .Y(mult_x_254_n273) );
XNOR2X1TS U4481 ( .A(n2347), .B(n2214), .Y(n3021) );
OAI22X1TS U4482 ( .A0(n2318), .A1(n3021), .B0(n2373), .B1(n3020), .Y(
mult_x_254_n288) );
XNOR2X1TS U4483 ( .A(FPMULT_Op_MY[11]), .B(n2282), .Y(n3022) );
OAI22X1TS U4484 ( .A0(n2318), .A1(n3022), .B0(n3032), .B1(n3021), .Y(
mult_x_254_n289) );
XNOR2X1TS U4485 ( .A(FPMULT_Op_MY[11]), .B(n2281), .Y(n3023) );
OAI22X1TS U4486 ( .A0(n2318), .A1(n3023), .B0(n3032), .B1(n3022), .Y(
mult_x_254_n290) );
XNOR2X1TS U4487 ( .A(FPMULT_Op_MY[11]), .B(n2280), .Y(n3024) );
OAI22X1TS U4488 ( .A0(n2318), .A1(n3024), .B0(n2373), .B1(n3023), .Y(
mult_x_254_n291) );
XNOR2X1TS U4489 ( .A(n2346), .B(n2213), .Y(n3025) );
OAI22X1TS U4490 ( .A0(n2318), .A1(n3025), .B0(n3032), .B1(n3024), .Y(
mult_x_254_n292) );
OAI22X1TS U4491 ( .A0(n2318), .A1(n3026), .B0(n2373), .B1(n3025), .Y(
mult_x_254_n293) );
OAI22X1TS U4492 ( .A0(n2317), .A1(n3028), .B0(n2373), .B1(n3027), .Y(
mult_x_254_n295) );
XNOR2X1TS U4493 ( .A(n2346), .B(n5681), .Y(n3030) );
OAI22X1TS U4494 ( .A0(n2317), .A1(n3030), .B0(n2373), .B1(n3029), .Y(
mult_x_254_n297) );
XNOR2X1TS U4495 ( .A(n2347), .B(n2442), .Y(n3031) );
OAI22X1TS U4496 ( .A0(n2318), .A1(n3031), .B0(n2373), .B1(n3030), .Y(
mult_x_254_n298) );
NOR2BX1TS U4497 ( .AN(n3128), .B(n2372), .Y(mult_x_254_n299) );
CLKXOR2X2TS U4498 ( .A(FPMULT_Op_MY[8]), .B(n2328), .Y(n3034) );
XNOR2X1TS U4499 ( .A(n2329), .B(n2446), .Y(n3122) );
OAI22X1TS U4500 ( .A0(n2434), .A1(n3122), .B0(n2203), .B1(n2508), .Y(
mult_x_254_n301) );
XNOR2X1TS U4501 ( .A(n2328), .B(n2281), .Y(n3035) );
XNOR2X1TS U4502 ( .A(n2328), .B(n2282), .Y(n3095) );
OAI22X1TS U4503 ( .A0(n3124), .A1(n3035), .B0(n2203), .B1(n3095), .Y(
mult_x_254_n304) );
XNOR2X1TS U4504 ( .A(n2329), .B(n2280), .Y(n3036) );
OAI22X1TS U4505 ( .A0(n2434), .A1(n3036), .B0(n2203), .B1(n3035), .Y(
mult_x_254_n305) );
XNOR2X1TS U4506 ( .A(n2328), .B(n2213), .Y(n3037) );
OAI22X1TS U4507 ( .A0(n3124), .A1(n3037), .B0(n2203), .B1(n3036), .Y(
mult_x_254_n306) );
XNOR2X1TS U4508 ( .A(n2328), .B(n2212), .Y(n3090) );
OAI22X1TS U4509 ( .A0(n3124), .A1(n3090), .B0(n2203), .B1(n3037), .Y(
mult_x_254_n307) );
XNOR2X1TS U4510 ( .A(n2328), .B(n5681), .Y(n3064) );
XNOR2X1TS U4511 ( .A(n2329), .B(FPMULT_Op_MX[2]), .Y(n3117) );
OAI22X1TS U4512 ( .A0(n3124), .A1(n3064), .B0(n2203), .B1(n3117), .Y(
mult_x_254_n311) );
XOR2X1TS U4513 ( .A(FPMULT_Op_MY[6]), .B(n2374), .Y(n3038) );
AO21X1TS U4514 ( .A0(n2433), .A1(n2360), .B0(n2247), .Y(mult_x_254_n314) );
XNOR2X1TS U4515 ( .A(n2375), .B(n2214), .Y(n3039) );
XNOR2X1TS U4516 ( .A(n2375), .B(FPMULT_Op_MX[11]), .Y(n3096) );
OAI22X1TS U4517 ( .A0(n3130), .A1(n3039), .B0(n2361), .B1(n3096), .Y(
mult_x_254_n316) );
XNOR2X1TS U4518 ( .A(n2374), .B(n2282), .Y(n3082) );
OAI22X1TS U4519 ( .A0(n3130), .A1(n3082), .B0(n2361), .B1(n3039), .Y(
mult_x_254_n317) );
XNOR2X1TS U4520 ( .A(n2375), .B(n2213), .Y(n3040) );
XNOR2X1TS U4521 ( .A(n2375), .B(n2280), .Y(n3087) );
OAI22X1TS U4522 ( .A0(n3130), .A1(n3040), .B0(n2361), .B1(n3087), .Y(
mult_x_254_n320) );
XNOR2X1TS U4523 ( .A(n2375), .B(n2212), .Y(n3041) );
OAI22X1TS U4524 ( .A0(n3130), .A1(n3041), .B0(n2360), .B1(n3040), .Y(
mult_x_254_n321) );
XNOR2X1TS U4525 ( .A(n2375), .B(n2209), .Y(n3042) );
OAI22X1TS U4526 ( .A0(n3130), .A1(n3042), .B0(n2361), .B1(n3041), .Y(
mult_x_254_n322) );
XNOR2X1TS U4527 ( .A(n2375), .B(FPMULT_Op_MX[3]), .Y(n3075) );
OAI22X1TS U4528 ( .A0(n3130), .A1(n3075), .B0(n2361), .B1(n3042), .Y(
mult_x_254_n323) );
XNOR2X1TS U4529 ( .A(n2375), .B(n2442), .Y(n3043) );
XNOR2X1TS U4530 ( .A(n2375), .B(n5681), .Y(n3101) );
OAI22X1TS U4531 ( .A0(n2433), .A1(n3043), .B0(n2361), .B1(n3101), .Y(
mult_x_254_n326) );
NOR2BX1TS U4532 ( .AN(n2442), .B(n2360), .Y(mult_x_254_n327) );
XNOR2X1TS U4533 ( .A(n2397), .B(FPMULT_Op_MX[11]), .Y(n3045) );
OAI22X1TS U4534 ( .A0(n3112), .A1(n3045), .B0(n2370), .B1(n3044), .Y(
mult_x_254_n329) );
XNOR2X1TS U4535 ( .A(n2397), .B(n2214), .Y(n3046) );
OAI22X1TS U4536 ( .A0(n3112), .A1(n3046), .B0(n2370), .B1(n3045), .Y(
mult_x_254_n330) );
XNOR2X1TS U4537 ( .A(n2396), .B(n2282), .Y(n3091) );
OAI22X1TS U4538 ( .A0(n3112), .A1(n3091), .B0(n2370), .B1(n3046), .Y(
mult_x_254_n331) );
XNOR2X1TS U4539 ( .A(n2397), .B(n2213), .Y(n3047) );
XNOR2X1TS U4540 ( .A(FPMULT_Op_MY[5]), .B(n2280), .Y(n3111) );
OAI22X1TS U4541 ( .A0(n3112), .A1(n3047), .B0(n2369), .B1(n3111), .Y(
mult_x_254_n334) );
XNOR2X1TS U4542 ( .A(n2397), .B(n2212), .Y(n3077) );
OAI22X1TS U4543 ( .A0(n2432), .A1(n3077), .B0(n2369), .B1(n3047), .Y(
mult_x_254_n335) );
XNOR2X1TS U4544 ( .A(n2397), .B(FPMULT_Op_MX[3]), .Y(n3048) );
XNOR2X1TS U4545 ( .A(n2397), .B(n2209), .Y(n3078) );
OAI22X1TS U4546 ( .A0(n2432), .A1(n3048), .B0(n2369), .B1(n3078), .Y(
mult_x_254_n337) );
XNOR2X1TS U4547 ( .A(n2396), .B(FPMULT_Op_MX[2]), .Y(n3049) );
OAI22X1TS U4548 ( .A0(n2432), .A1(n3049), .B0(n2370), .B1(n3048), .Y(
mult_x_254_n338) );
OAI22X1TS U4549 ( .A0(n3112), .A1(n3050), .B0(n2369), .B1(n3049), .Y(
mult_x_254_n339) );
XNOR2X1TS U4550 ( .A(n2331), .B(n2446), .Y(n3051) );
OAI22X1TS U4551 ( .A0(n2430), .A1(n3051), .B0(n2367), .B1(n2483), .Y(
mult_x_254_n343) );
XNOR2X1TS U4552 ( .A(n2331), .B(n2214), .Y(n3052) );
OAI22X1TS U4553 ( .A0(n2430), .A1(n3052), .B0(n2367), .B1(n3051), .Y(
mult_x_254_n344) );
XNOR2X1TS U4554 ( .A(n2331), .B(n2282), .Y(n3053) );
OAI22X1TS U4555 ( .A0(n2431), .A1(n3053), .B0(n2367), .B1(n3052), .Y(
mult_x_254_n345) );
XNOR2X1TS U4556 ( .A(n2331), .B(n2281), .Y(n3054) );
OAI22X1TS U4557 ( .A0(n2431), .A1(n3054), .B0(n2366), .B1(n3053), .Y(
mult_x_254_n346) );
XNOR2X1TS U4558 ( .A(n2331), .B(n2280), .Y(n3055) );
OAI22X1TS U4559 ( .A0(n2430), .A1(n3055), .B0(n2367), .B1(n3054), .Y(
mult_x_254_n347) );
XNOR2X1TS U4560 ( .A(n2330), .B(n2213), .Y(n3102) );
OAI22X1TS U4561 ( .A0(n2431), .A1(n3102), .B0(n2366), .B1(n3055), .Y(
mult_x_254_n348) );
XNOR2X1TS U4562 ( .A(n2331), .B(n2209), .Y(n3056) );
XNOR2X1TS U4563 ( .A(n2330), .B(n2212), .Y(n3103) );
OAI22X1TS U4564 ( .A0(n2431), .A1(n3056), .B0(n2367), .B1(n3103), .Y(
mult_x_254_n350) );
OAI22X1TS U4565 ( .A0(n2431), .A1(n3057), .B0(n2366), .B1(n3056), .Y(
mult_x_254_n351) );
XNOR2X1TS U4566 ( .A(FPMULT_Op_MY[1]), .B(n2446), .Y(n3118) );
OAI22X1TS U4567 ( .A0(n3059), .A1(n3118), .B0(n2230), .B1(n2249), .Y(
mult_x_254_n357) );
XNOR2X1TS U4568 ( .A(n2345), .B(n2282), .Y(n3066) );
XNOR2X1TS U4569 ( .A(FPMULT_Op_MY[1]), .B(n2214), .Y(n3119) );
OAI22X1TS U4570 ( .A0(n3133), .A1(n3066), .B0(n3119), .B1(n2326), .Y(
mult_x_254_n359) );
XNOR2X1TS U4571 ( .A(n2345), .B(n2280), .Y(n3131) );
XNOR2X1TS U4572 ( .A(n2345), .B(n2281), .Y(n3067) );
OAI22X1TS U4573 ( .A0(n3133), .A1(n3131), .B0(n3067), .B1(n2326), .Y(
mult_x_254_n361) );
XNOR2X1TS U4574 ( .A(n2345), .B(n2213), .Y(n3132) );
OAI22X1TS U4575 ( .A0(n3059), .A1(n3058), .B0(n3132), .B1(n2326), .Y(
mult_x_254_n363) );
XNOR2X1TS U4576 ( .A(n2329), .B(n3128), .Y(n3065) );
OAI22X1TS U4577 ( .A0(n3124), .A1(n3065), .B0(n3033), .B1(n3064), .Y(n3069)
);
OAI22X1TS U4578 ( .A0(n3133), .A1(n3067), .B0(n3066), .B1(n2326), .Y(n3068)
);
ADDHX1TS U4579 ( .A(n3069), .B(n3068), .CO(mult_x_254_n250), .S(
mult_x_254_n251) );
NOR2X1TS U4580 ( .A(n2348), .B(n2516), .Y(mult_x_254_n282) );
INVX2TS U4581 ( .A(n3070), .Y(n3072) );
NAND2X1TS U4582 ( .A(n3072), .B(n3071), .Y(n3073) );
NOR2X1TS U4583 ( .A(DP_OP_454J16_123_2743_n727), .B(n2502), .Y(
mult_x_254_n280) );
INVX2TS U4584 ( .A(mult_x_254_n194), .Y(mult_x_254_n195) );
NOR2X1TS U4585 ( .A(DP_OP_454J16_123_2743_n727), .B(n2496), .Y(
mult_x_254_n168) );
INVX2TS U4586 ( .A(mult_x_254_n168), .Y(mult_x_254_n169) );
XNOR2X1TS U4587 ( .A(n2374), .B(FPMULT_Op_MX[2]), .Y(n3100) );
OAI22X1TS U4588 ( .A0(n3130), .A1(n3100), .B0(n2361), .B1(n3075), .Y(n3081)
);
OAI22X1TS U4589 ( .A0(n3124), .A1(n2508), .B0(n2203), .B1(n3076), .Y(n3080)
);
OAI22X1TS U4590 ( .A0(n3112), .A1(n3078), .B0(n2370), .B1(n3077), .Y(n3079)
);
CMPR32X2TS U4591 ( .A(n3081), .B(n3080), .C(n3079), .CO(mult_x_254_n248),
.S(mult_x_254_n249) );
XNOR2X1TS U4592 ( .A(FPMULT_Op_MY[7]), .B(n2281), .Y(n3086) );
OAI22X1TS U4593 ( .A0(n2433), .A1(n3086), .B0(n2360), .B1(n3082), .Y(n3083)
);
CMPR32X2TS U4594 ( .A(n3085), .B(n3084), .C(n3083), .CO(mult_x_254_n202),
.S(mult_x_254_n203) );
INVX2TS U4595 ( .A(n3085), .Y(n3094) );
OAI22X1TS U4596 ( .A0(n2433), .A1(n3087), .B0(n2360), .B1(n3086), .Y(n3088)
);
CMPR32X2TS U4597 ( .A(n3089), .B(n3094), .C(n3088), .CO(mult_x_254_n210),
.S(mult_x_254_n211) );
XNOR2X1TS U4598 ( .A(n2329), .B(n2209), .Y(n3108) );
OAI22X1TS U4599 ( .A0(n3124), .A1(n3108), .B0(n3033), .B1(n3090), .Y(n3093)
);
XNOR2X1TS U4600 ( .A(n2397), .B(n2281), .Y(n3109) );
OAI22X1TS U4601 ( .A0(n3112), .A1(n3109), .B0(n2369), .B1(n3091), .Y(n3092)
);
CMPR32X2TS U4602 ( .A(n3094), .B(n3093), .C(n3092), .CO(mult_x_254_n220),
.S(mult_x_254_n221) );
INVX2TS U4603 ( .A(n3127), .Y(n3099) );
XNOR2X1TS U4604 ( .A(n2329), .B(n2214), .Y(n3123) );
OAI22X1TS U4605 ( .A0(n3124), .A1(n3095), .B0(n2203), .B1(n3123), .Y(n3098)
);
OAI22X1TS U4606 ( .A0(n2433), .A1(n3096), .B0(n2361), .B1(n2247), .Y(n3097)
);
CMPR32X2TS U4607 ( .A(n3099), .B(n3098), .C(n3097), .CO(mult_x_254_n178),
.S(mult_x_254_n179) );
NOR2BX1TS U4608 ( .AN(n3128), .B(n2203), .Y(n3107) );
OAI22X1TS U4609 ( .A0(n3130), .A1(n3101), .B0(n2360), .B1(n3100), .Y(n3106)
);
OAI22X1TS U4610 ( .A0(n2430), .A1(n3103), .B0(n2366), .B1(n3102), .Y(n3105)
);
CMPR32X2TS U4611 ( .A(n3107), .B(n3106), .C(n3105), .CO(mult_x_254_n255),
.S(mult_x_254_n256) );
NOR2BX1TS U4612 ( .AN(n2442), .B(n2348), .Y(n3115) );
XNOR2X1TS U4613 ( .A(n2329), .B(FPMULT_Op_MX[3]), .Y(n3116) );
OAI22X1TS U4614 ( .A0(n3124), .A1(n3116), .B0(n3033), .B1(n3108), .Y(n3114)
);
OAI22X1TS U4615 ( .A0(n2432), .A1(n3111), .B0(n2370), .B1(n3109), .Y(n3113)
);
CMPR32X2TS U4616 ( .A(n3115), .B(n3114), .C(n3113), .CO(mult_x_254_n229),
.S(mult_x_254_n230) );
OAI22X1TS U4617 ( .A0(n2434), .A1(n3117), .B0(n3033), .B1(n3116), .Y(n3121)
);
OAI22X1TS U4618 ( .A0(n3133), .A1(n3119), .B0(n3118), .B1(n2326), .Y(n3120)
);
ADDHX1TS U4619 ( .A(n3121), .B(n3120), .CO(mult_x_254_n237), .S(
mult_x_254_n238) );
OAI22X1TS U4620 ( .A0(n2434), .A1(n3123), .B0(n2203), .B1(n3122), .Y(n3125)
);
CMPR32X2TS U4621 ( .A(n3127), .B(n3126), .C(n3125), .CO(mult_x_254_n173),
.S(mult_x_254_n174) );
OAI22X1TS U4622 ( .A0(n3130), .A1(n2247), .B0(n2361), .B1(n3129), .Y(n3135)
);
OAI22X1TS U4623 ( .A0(n3133), .A1(n3132), .B0(n3131), .B1(n2326), .Y(n3134)
);
NAND2X1TS U4624 ( .A(n3137), .B(n3136), .Y(n3138) );
XNOR2X1TS U4625 ( .A(n3139), .B(n3138), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N22) );
INVX2TS U4626 ( .A(n3140), .Y(n3142) );
NAND2X1TS U4627 ( .A(n3142), .B(n3141), .Y(n3143) );
INVX2TS U4628 ( .A(n3148), .Y(n3150) );
NAND2X1TS U4629 ( .A(n3150), .B(n3149), .Y(n3151) );
XNOR2X1TS U4630 ( .A(n3152), .B(n3151), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N20) );
INVX2TS U4631 ( .A(n3153), .Y(n3156) );
NAND2X1TS U4632 ( .A(n3158), .B(n3157), .Y(n3159) );
XNOR2X1TS U4633 ( .A(n3160), .B(n3159), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N19) );
INVX2TS U4634 ( .A(n3161), .Y(n3163) );
NAND2X1TS U4635 ( .A(n3163), .B(n3162), .Y(n3164) );
XNOR2X1TS U4636 ( .A(n3165), .B(n3164), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N18) );
INVX2TS U4637 ( .A(n3166), .Y(n3168) );
NAND2X1TS U4638 ( .A(n3168), .B(n3167), .Y(n3169) );
INVX4TS U4639 ( .A(n3171), .Y(n3194) );
INVX2TS U4640 ( .A(n3174), .Y(n3176) );
NAND2X1TS U4641 ( .A(n3176), .B(n3175), .Y(n3177) );
XNOR2X1TS U4642 ( .A(n3178), .B(n3177), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N16) );
INVX2TS U4643 ( .A(n3179), .Y(n3181) );
NAND2X1TS U4644 ( .A(n3181), .B(n3180), .Y(n3182) );
INVX2TS U4645 ( .A(n3184), .Y(n3192) );
INVX2TS U4646 ( .A(n3191), .Y(n3185) );
AOI21X1TS U4647 ( .A0(n3194), .A1(n3192), .B0(n3185), .Y(n3190) );
INVX2TS U4648 ( .A(n3186), .Y(n3188) );
NAND2X1TS U4649 ( .A(n3188), .B(n3187), .Y(n3189) );
NAND2X1TS U4650 ( .A(n3192), .B(n3191), .Y(n3193) );
XNOR2X1TS U4651 ( .A(n3194), .B(n3193), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N13) );
INVX2TS U4652 ( .A(n3195), .Y(n3293) );
INVX2TS U4653 ( .A(n3196), .Y(n3198) );
NAND2X1TS U4654 ( .A(n3198), .B(n3197), .Y(n3199) );
XNOR2X1TS U4655 ( .A(n3200), .B(n3199), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N12) );
INVX2TS U4656 ( .A(n3201), .Y(n3208) );
AOI21X1TS U4657 ( .A0(n3208), .A1(n2522), .B0(n3202), .Y(n3205) );
NAND2X1TS U4658 ( .A(n2523), .B(n3203), .Y(n3204) );
NAND2X1TS U4659 ( .A(n2522), .B(n3206), .Y(n3207) );
XNOR2X1TS U4660 ( .A(n3208), .B(n3207), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N9) );
INVX2TS U4661 ( .A(n3209), .Y(n3219) );
INVX2TS U4662 ( .A(n3210), .Y(n3212) );
NAND2X1TS U4663 ( .A(n3212), .B(n3211), .Y(n3213) );
XNOR2X1TS U4664 ( .A(n3214), .B(n3213), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N8) );
INVX2TS U4665 ( .A(n3215), .Y(n3217) );
NAND2X1TS U4666 ( .A(n3217), .B(n3216), .Y(n3218) );
INVX2TS U4667 ( .A(n3220), .Y(n3222) );
NAND2X1TS U4668 ( .A(n3222), .B(n3221), .Y(n3224) );
NAND2X1TS U4669 ( .A(n2506), .B(n3225), .Y(n3226) );
XNOR2X1TS U4670 ( .A(n3227), .B(n3226), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N5) );
INVX2TS U4671 ( .A(n3228), .Y(n3230) );
NAND2X1TS U4672 ( .A(n3230), .B(n3229), .Y(n3232) );
NAND2X1TS U4673 ( .A(n2504), .B(n3233), .Y(n3235) );
XNOR2X1TS U4674 ( .A(n3235), .B(n3234), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N3) );
INVX2TS U4675 ( .A(n3236), .Y(n3238) );
NAND2X1TS U4676 ( .A(n3238), .B(n3237), .Y(n3239) );
OAI22X1TS U4677 ( .A0(n2311), .A1(n2448), .B0(n2340), .B1(FPMULT_Op_MY[21]),
.Y(n3240) );
CMPR32X2TS U4678 ( .A(n5668), .B(n2415), .C(n3240), .CO(mult_x_219_n171),
.S(mult_x_219_n172) );
OAI22X1TS U4679 ( .A0(n2311), .A1(n2206), .B0(n2339), .B1(n2207), .Y(n3241)
);
OAI22X2TS U4680 ( .A0(n2201), .A1(n2289), .B0(n2339), .B1(n2206), .Y(n3242)
);
OAI22X1TS U4681 ( .A0(n2201), .A1(FPMULT_Op_MY[14]), .B0(n2340), .B1(n2289),
.Y(n3244) );
XNOR2X1TS U4682 ( .A(n2365), .B(n2448), .Y(n3270) );
XNOR2X1TS U4683 ( .A(n2364), .B(FPMULT_Op_MY[21]), .Y(n3269) );
OAI22X1TS U4684 ( .A0(n3308), .A1(n3270), .B0(n3269), .B1(n2356), .Y(n3243)
);
CMPR32X2TS U4685 ( .A(n2248), .B(n3244), .C(n3243), .CO(mult_x_219_n218),
.S(mult_x_219_n219) );
OAI22X1TS U4686 ( .A0(n2311), .A1(n3318), .B0(n2340), .B1(FPMULT_Op_MY[14]),
.Y(n3246) );
CMPR32X2TS U4687 ( .A(n2444), .B(n3246), .C(n3245), .CO(mult_x_219_n227),
.S(mult_x_219_n228) );
OAI22X1TS U4688 ( .A0(n2201), .A1(FPMULT_Op_MY[21]), .B0(n2339), .B1(n4718),
.Y(mult_x_219_n281) );
OAI22X1TS U4689 ( .A0(n2311), .A1(n5668), .B0(n2339), .B1(n2205), .Y(
mult_x_219_n284) );
OAI22X1TS U4690 ( .A0(n2201), .A1(n2207), .B0(n2340), .B1(n5668), .Y(
mult_x_219_n285) );
NOR2BX1TS U4691 ( .AN(n2444), .B(n2340), .Y(mult_x_219_n291) );
XOR2X1TS U4692 ( .A(n2398), .B(FPMULT_Op_MX[20]), .Y(n3248) );
INVX2TS U4693 ( .A(n2398), .Y(n3326) );
OAI22X1TS U4694 ( .A0(n2429), .A1(n2399), .B0(n2377), .B1(n3326), .Y(
mult_x_219_n293) );
XNOR2X1TS U4695 ( .A(n2399), .B(n4718), .Y(n3249) );
OAI22X1TS U4696 ( .A0(n2429), .A1(n3249), .B0(n2378), .B1(n2398), .Y(
mult_x_219_n294) );
XNOR2X1TS U4697 ( .A(n2398), .B(FPMULT_Op_MY[21]), .Y(n3250) );
OAI22X1TS U4698 ( .A0(n2429), .A1(n3250), .B0(n3249), .B1(n2377), .Y(
mult_x_219_n295) );
XNOR2X1TS U4699 ( .A(n2399), .B(n2448), .Y(n3251) );
OAI22X1TS U4700 ( .A0(n2429), .A1(n3251), .B0(n3250), .B1(n2377), .Y(
mult_x_219_n296) );
XNOR2X1TS U4701 ( .A(FPMULT_Op_MX[21]), .B(n2205), .Y(n3252) );
OAI22X1TS U4702 ( .A0(n2429), .A1(n3252), .B0(n3251), .B1(n2377), .Y(
mult_x_219_n297) );
XNOR2X1TS U4703 ( .A(n2399), .B(n5668), .Y(n3253) );
OAI22X1TS U4704 ( .A0(n2429), .A1(n3253), .B0(n3252), .B1(n2378), .Y(
mult_x_219_n298) );
XNOR2X1TS U4705 ( .A(n2398), .B(n2207), .Y(n3254) );
OAI22X1TS U4706 ( .A0(n2429), .A1(n3254), .B0(n3253), .B1(n2378), .Y(
mult_x_219_n299) );
XNOR2X1TS U4707 ( .A(n2399), .B(n2206), .Y(n3255) );
OAI22X1TS U4708 ( .A0(n2428), .A1(n3255), .B0(n3254), .B1(n2377), .Y(
mult_x_219_n300) );
XNOR2X1TS U4709 ( .A(n2399), .B(n2289), .Y(n3256) );
OAI22X1TS U4710 ( .A0(n2428), .A1(n3256), .B0(n3255), .B1(n2378), .Y(
mult_x_219_n301) );
XNOR2X1TS U4711 ( .A(n2399), .B(FPMULT_Op_MY[14]), .Y(n3257) );
OAI22X1TS U4712 ( .A0(n2428), .A1(n3257), .B0(n3256), .B1(n2377), .Y(
mult_x_219_n302) );
XNOR2X1TS U4713 ( .A(n2399), .B(n3318), .Y(n3304) );
OAI22X1TS U4714 ( .A0(n2429), .A1(n3304), .B0(n3257), .B1(n2378), .Y(
mult_x_219_n303) );
XOR2X1TS U4715 ( .A(n2379), .B(FPMULT_Op_MX[18]), .Y(n3258) );
XNOR2X1TS U4716 ( .A(n2380), .B(FPMULT_Op_MY[22]), .Y(n3259) );
OAI22X1TS U4717 ( .A0(n2427), .A1(n3259), .B0(n2358), .B1(n2380), .Y(
mult_x_219_n308) );
XNOR2X1TS U4718 ( .A(n2379), .B(FPMULT_Op_MY[21]), .Y(n3260) );
OAI22X1TS U4719 ( .A0(n2427), .A1(n3260), .B0(n3259), .B1(n2359), .Y(
mult_x_219_n309) );
XNOR2X1TS U4720 ( .A(n2379), .B(FPMULT_Op_MY[20]), .Y(n3261) );
OAI22X1TS U4721 ( .A0(n2426), .A1(n3261), .B0(n3260), .B1(n2359), .Y(
mult_x_219_n310) );
XNOR2X1TS U4722 ( .A(n2379), .B(n2415), .Y(n3262) );
OAI22X1TS U4723 ( .A0(n2426), .A1(n3262), .B0(n3261), .B1(n2358), .Y(
mult_x_219_n311) );
XNOR2X1TS U4724 ( .A(n2379), .B(n5668), .Y(n3263) );
OAI22X1TS U4725 ( .A0(n2426), .A1(n3263), .B0(n3262), .B1(n2359), .Y(
mult_x_219_n312) );
XNOR2X1TS U4726 ( .A(n2379), .B(n2207), .Y(n3264) );
OAI22X1TS U4727 ( .A0(n2426), .A1(n3264), .B0(n3263), .B1(n2358), .Y(
mult_x_219_n313) );
XNOR2X1TS U4728 ( .A(n2380), .B(n2206), .Y(n3265) );
OAI22X1TS U4729 ( .A0(n2427), .A1(n3265), .B0(n3264), .B1(n2358), .Y(
mult_x_219_n314) );
XNOR2X1TS U4730 ( .A(n2379), .B(n2289), .Y(n3302) );
OAI22X1TS U4731 ( .A0(n2427), .A1(n3302), .B0(n3265), .B1(n2359), .Y(
mult_x_219_n315) );
XNOR2X1TS U4732 ( .A(n2380), .B(n3318), .Y(n3266) );
XNOR2X1TS U4733 ( .A(n2380), .B(FPMULT_Op_MY[14]), .Y(n3303) );
OAI22X1TS U4734 ( .A0(n2427), .A1(n3266), .B0(n3303), .B1(n2358), .Y(
mult_x_219_n317) );
XNOR2X1TS U4735 ( .A(n2380), .B(n2444), .Y(n3267) );
OAI22X1TS U4736 ( .A0(n2427), .A1(n3267), .B0(n3266), .B1(n2359), .Y(
mult_x_219_n318) );
NOR2BX1TS U4737 ( .AN(n2444), .B(n2359), .Y(mult_x_219_n319) );
OAI22X1TS U4738 ( .A0(n3308), .A1(n2364), .B0(n2356), .B1(n2246), .Y(
mult_x_219_n321) );
XNOR2X1TS U4739 ( .A(n2364), .B(n4718), .Y(n3268) );
OAI22X1TS U4740 ( .A0(n3308), .A1(n3268), .B0(n2357), .B1(n2364), .Y(
mult_x_219_n322) );
OAI22X1TS U4741 ( .A0(n3308), .A1(n3269), .B0(n3268), .B1(n2356), .Y(
mult_x_219_n323) );
XNOR2X1TS U4742 ( .A(n2365), .B(n2205), .Y(n3271) );
OAI22X1TS U4743 ( .A0(n2425), .A1(n3271), .B0(n3270), .B1(n2357), .Y(
mult_x_219_n325) );
XNOR2X1TS U4744 ( .A(n2365), .B(n5668), .Y(n3272) );
OAI22X1TS U4745 ( .A0(n2425), .A1(n3272), .B0(n3271), .B1(n2357), .Y(
mult_x_219_n326) );
XNOR2X1TS U4746 ( .A(n2365), .B(n2207), .Y(n3306) );
OAI22X1TS U4747 ( .A0(n3308), .A1(n3306), .B0(n3272), .B1(n2357), .Y(
mult_x_219_n327) );
XNOR2X1TS U4748 ( .A(n2365), .B(n2289), .Y(n3273) );
XNOR2X1TS U4749 ( .A(n2365), .B(n2206), .Y(n3307) );
OAI22X1TS U4750 ( .A0(n3308), .A1(n3273), .B0(n3307), .B1(n2356), .Y(
mult_x_219_n329) );
XNOR2X1TS U4751 ( .A(n2365), .B(FPMULT_Op_MY[14]), .Y(n3274) );
OAI22X1TS U4752 ( .A0(n3308), .A1(n3274), .B0(n3273), .B1(n2357), .Y(
mult_x_219_n330) );
OAI22X1TS U4753 ( .A0(n2425), .A1(n3275), .B0(n3274), .B1(n2357), .Y(
mult_x_219_n331) );
OAI22X1TS U4754 ( .A0(n2423), .A1(n2363), .B0(n2354), .B1(n2237), .Y(
mult_x_219_n335) );
XNOR2X1TS U4755 ( .A(n2363), .B(n4718), .Y(n3276) );
OAI22X1TS U4756 ( .A0(n2423), .A1(n3276), .B0(n2355), .B1(n2362), .Y(
mult_x_219_n336) );
XNOR2X1TS U4757 ( .A(n2362), .B(n2288), .Y(n3277) );
OAI22X1TS U4758 ( .A0(n2423), .A1(n3277), .B0(n3276), .B1(n2355), .Y(
mult_x_219_n337) );
XNOR2X1TS U4759 ( .A(n2363), .B(n2448), .Y(n3278) );
OAI22X1TS U4760 ( .A0(n2423), .A1(n3278), .B0(n3277), .B1(n2355), .Y(
mult_x_219_n338) );
XNOR2X1TS U4761 ( .A(n2363), .B(n2205), .Y(n3279) );
OAI22X1TS U4762 ( .A0(n2424), .A1(n3279), .B0(n3278), .B1(n2355), .Y(
mult_x_219_n339) );
XNOR2X1TS U4763 ( .A(n2362), .B(n5668), .Y(n3296) );
OAI22X1TS U4764 ( .A0(n2424), .A1(n3296), .B0(n3279), .B1(n2355), .Y(
mult_x_219_n340) );
XNOR2X1TS U4765 ( .A(FPMULT_Op_MX[15]), .B(n2206), .Y(n3280) );
XNOR2X1TS U4766 ( .A(n2363), .B(n2291), .Y(n3297) );
OAI22X1TS U4767 ( .A0(n2424), .A1(n3280), .B0(n3297), .B1(n2354), .Y(
mult_x_219_n342) );
OAI22X1TS U4768 ( .A0(n2424), .A1(n3281), .B0(n3280), .B1(n2354), .Y(
mult_x_219_n343) );
XNOR2X1TS U4769 ( .A(n2312), .B(n4718), .Y(n3282) );
OAI22X1TS U4770 ( .A0(n3323), .A1(n3282), .B0(n2520), .B1(FPMULT_Op_MX[13]),
.Y(mult_x_219_n350) );
XNOR2X1TS U4771 ( .A(n2312), .B(n2288), .Y(n3321) );
OAI22X1TS U4772 ( .A0(n3323), .A1(n3321), .B0(n3282), .B1(n2520), .Y(
mult_x_219_n351) );
XNOR2X1TS U4773 ( .A(FPMULT_Op_MX[13]), .B(n5668), .Y(n3313) );
OAI22X1TS U4774 ( .A0(n3284), .A1(n3283), .B0(n3313), .B1(n2539), .Y(
mult_x_219_n355) );
NOR2BX1TS U4775 ( .AN(n2444), .B(n2539), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N0) );
CLKAND2X2TS U4776 ( .A(n3288), .B(n3287), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N1) );
INVX2TS U4777 ( .A(n3289), .Y(n3291) );
NAND2X1TS U4778 ( .A(n3291), .B(n3290), .Y(n3292) );
NOR2X1TS U4779 ( .A(n2201), .B(n4718), .Y(mult_x_219_n280) );
OAI22X1TS U4780 ( .A0(n2201), .A1(n2415), .B0(n2339), .B1(n2448), .Y(n3295)
);
OAI22X1TS U4781 ( .A0(n2427), .A1(n2380), .B0(n2359), .B1(n2245), .Y(n3294)
);
CMPR32X2TS U4782 ( .A(n2512), .B(n3295), .C(n3294), .CO(mult_x_219_n176),
.S(mult_x_219_n177) );
NOR2BX1TS U4783 ( .AN(n3324), .B(n2377), .Y(n3301) );
XNOR2X1TS U4784 ( .A(n2312), .B(n2415), .Y(n3312) );
XNOR2X1TS U4785 ( .A(n2312), .B(FPMULT_Op_MY[20]), .Y(n3322) );
OAI22X1TS U4786 ( .A0(n3323), .A1(n3312), .B0(n3322), .B1(n2520), .Y(n3300)
);
OAI22X1TS U4787 ( .A0(n2424), .A1(n3297), .B0(n3296), .B1(n2355), .Y(n3299)
);
CMPR32X2TS U4788 ( .A(n3301), .B(n3300), .C(n3299), .CO(mult_x_219_n253),
.S(mult_x_219_n254) );
OAI22X1TS U4789 ( .A0(n2426), .A1(n3303), .B0(n3302), .B1(n2359), .Y(n3311)
);
XNOR2X1TS U4790 ( .A(n2399), .B(n3324), .Y(n3305) );
OAI22X1TS U4791 ( .A0(n2428), .A1(n3305), .B0(n3304), .B1(n2378), .Y(n3310)
);
OAI22X1TS U4792 ( .A0(n3308), .A1(n3307), .B0(n3306), .B1(n2357), .Y(n3309)
);
CMPR32X2TS U4793 ( .A(n3311), .B(n3310), .C(n3309), .CO(mult_x_219_n246),
.S(mult_x_219_n247) );
OAI22X1TS U4794 ( .A0(n3323), .A1(n3313), .B0(n3312), .B1(n2520), .Y(n3317)
);
OAI22X1TS U4795 ( .A0(n2427), .A1(n2245), .B0(n2359), .B1(n3314), .Y(n3316)
);
OAI21X1TS U4796 ( .A0(n2339), .A1(n3324), .B0(n2311), .Y(n3320) );
OAI22X1TS U4797 ( .A0(n2311), .A1(n3324), .B0(n2340), .B1(n3318), .Y(n3319)
);
ADDHX1TS U4798 ( .A(n3320), .B(n3319), .CO(mult_x_219_n235), .S(
mult_x_219_n236) );
OAI22X1TS U4799 ( .A0(n3323), .A1(n3322), .B0(n3321), .B1(n2539), .Y(n3329)
);
OAI22X1TS U4800 ( .A0(n2428), .A1(n3326), .B0(n2377), .B1(n3325), .Y(n3328)
);
ADDHXLTS U4801 ( .A(n3331), .B(n3330), .CO(mult_x_219_n265), .S(n2668) );
INVX2TS U4802 ( .A(n3332), .Y(n3642) );
NAND2X1TS U4803 ( .A(n3642), .B(n3640), .Y(n3333) );
XNOR2X1TS U4804 ( .A(n3643), .B(n3333), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N18) );
NAND2X1TS U4805 ( .A(n3335), .B(n3334), .Y(n3336) );
XNOR2X1TS U4806 ( .A(n3337), .B(n3336), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N14) );
INVX2TS U4807 ( .A(n3338), .Y(n3525) );
INVX2TS U4808 ( .A(n3339), .Y(n3341) );
NAND2X1TS U4809 ( .A(n3341), .B(n3340), .Y(n3342) );
INVX2TS U4810 ( .A(n3344), .Y(n3353) );
AOI21X1TS U4811 ( .A0(n3353), .A1(n3351), .B0(n3345), .Y(n3349) );
NAND2X1TS U4812 ( .A(n3347), .B(n3346), .Y(n3348) );
NAND2X1TS U4813 ( .A(n3351), .B(n3350), .Y(n3352) );
XNOR2X1TS U4814 ( .A(n3353), .B(n3352), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N10) );
NAND2X1TS U4815 ( .A(n2530), .B(n3354), .Y(n3355) );
XNOR2X1TS U4816 ( .A(n3356), .B(n3355), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N9) );
INVX2TS U4817 ( .A(n3357), .Y(n3363) );
AOI21X1TS U4818 ( .A0(n2526), .A1(n3363), .B0(n3358), .Y(n3361) );
NAND2X1TS U4819 ( .A(n2196), .B(n3359), .Y(n3360) );
NAND2X1TS U4820 ( .A(n3362), .B(n2526), .Y(n3364) );
XNOR2X1TS U4821 ( .A(n3364), .B(n3363), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N7) );
NAND2X1TS U4822 ( .A(n2493), .B(n3365), .Y(n3367) );
XNOR2X1TS U4823 ( .A(n3367), .B(n3366), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N6) );
INVX2TS U4824 ( .A(n3368), .Y(n3370) );
NAND2X1TS U4825 ( .A(n3370), .B(n3369), .Y(n3372) );
NAND2X1TS U4826 ( .A(n2231), .B(n3373), .Y(n3375) );
XNOR2X1TS U4827 ( .A(n3375), .B(n3374), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N4) );
NAND2X1TS U4828 ( .A(n3378), .B(n3377), .Y(n3380) );
NAND2X1TS U4829 ( .A(n2495), .B(n3381), .Y(n3383) );
XNOR2X1TS U4830 ( .A(n3383), .B(n3382), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N2) );
XNOR2X1TS U4831 ( .A(n3387), .B(n3384), .Y(n3385) );
XNOR2X1TS U4832 ( .A(n3492), .B(n2351), .Y(n3460) );
NOR2X1TS U4833 ( .A(n3386), .B(n3390), .Y(n3388) );
XOR2X1TS U4834 ( .A(n3388), .B(n3387), .Y(n3396) );
NOR2X1TS U4835 ( .A(FPMULT_Op_MX[17]), .B(n2278), .Y(n3389) );
OAI22X1TS U4836 ( .A0(n3460), .A1(n2439), .B0(n2199), .B1(n2350), .Y(n3415)
);
AOI21X1TS U4837 ( .A0(n3408), .A1(n3400), .B0(n3402), .Y(n3399) );
INVX2TS U4838 ( .A(n3404), .Y(n3397) );
NAND2X1TS U4839 ( .A(n3397), .B(n3403), .Y(n3398) );
CLKXOR2X4TS U4840 ( .A(n3399), .B(n3398), .Y(n3502) );
INVX2TS U4841 ( .A(n3502), .Y(n3433) );
INVX2TS U4842 ( .A(n3400), .Y(n3401) );
NOR2X1TS U4843 ( .A(n3401), .B(n3404), .Y(n3407) );
INVX2TS U4844 ( .A(n3402), .Y(n3405) );
OAI21X1TS U4845 ( .A0(n3405), .A1(n3404), .B0(n3403), .Y(n3406) );
AOI21X2TS U4846 ( .A0(n3408), .A1(n3407), .B0(n3406), .Y(n3413) );
INVX2TS U4847 ( .A(n3409), .Y(n3411) );
NAND2X1TS U4848 ( .A(n3411), .B(n3410), .Y(n3412) );
CLKXOR2X4TS U4849 ( .A(n3413), .B(n3412), .Y(n3500) );
INVX2TS U4850 ( .A(n3500), .Y(n3551) );
CMPR32X2TS U4851 ( .A(n3415), .B(n3414), .C(DP_OP_454J16_123_2743_n280),
.CO(DP_OP_454J16_123_2743_n273), .S(DP_OP_454J16_123_2743_n274) );
CMPR32X2TS U4852 ( .A(n3417), .B(n2241), .C(n3416), .CO(n2726), .S(
DP_OP_454J16_123_2743_n315) );
INVX2TS U4853 ( .A(n3418), .Y(n3430) );
INVX2TS U4854 ( .A(n3429), .Y(n3419) );
NAND2X1TS U4855 ( .A(n3422), .B(n3421), .Y(n3423) );
CLKXOR2X4TS U4856 ( .A(n3424), .B(n3423), .Y(n3496) );
INVX2TS U4857 ( .A(n3496), .Y(n3432) );
AOI21X1TS U4858 ( .A0(n3441), .A1(n3425), .B0(n3435), .Y(n3428) );
NAND2X1TS U4859 ( .A(n3426), .B(n3436), .Y(n3427) );
CLKXOR2X4TS U4860 ( .A(n3428), .B(n3427), .Y(n3494) );
INVX2TS U4861 ( .A(n3494), .Y(n3560) );
OAI22X1TS U4862 ( .A0(n3432), .A1(n2422), .B0(n3560), .B1(n2314), .Y(
DP_OP_454J16_123_2743_n384) );
XNOR2X4TS U4863 ( .A(n3441), .B(n3431), .Y(n3498) );
INVX2TS U4864 ( .A(n3498), .Y(n3550) );
OAI22X1TS U4865 ( .A0(n3432), .A1(n2314), .B0(n3550), .B1(n2422), .Y(
DP_OP_454J16_123_2743_n385) );
INVX2TS U4866 ( .A(n3485), .Y(n3434) );
OAI22X1TS U4867 ( .A0(n3434), .A1(n2422), .B0(n3433), .B1(n2314), .Y(
DP_OP_454J16_123_2743_n387) );
INVX2TS U4868 ( .A(n3488), .Y(n3520) );
OAI22X1TS U4869 ( .A0(n3434), .A1(n2314), .B0(n3520), .B1(n2422), .Y(
DP_OP_454J16_123_2743_n388) );
INVX2TS U4870 ( .A(n3435), .Y(n3438) );
OAI21X1TS U4871 ( .A0(n3438), .A1(n3437), .B0(n3436), .Y(n3439) );
AOI21X2TS U4872 ( .A0(n3441), .A1(n3440), .B0(n3439), .Y(n3442) );
CLKXOR2X4TS U4873 ( .A(n3442), .B(FPMULT_Op_MY[11]), .Y(n3559) );
XNOR2X1TS U4874 ( .A(n3492), .B(n2343), .Y(n3558) );
OAI22X1TS U4875 ( .A0(n3443), .A1(n2327), .B0(n3558), .B1(n2391), .Y(
DP_OP_454J16_123_2743_n394) );
XNOR2X1TS U4876 ( .A(n3494), .B(n2343), .Y(n3444) );
OAI22X1TS U4877 ( .A0(n3444), .A1(n2327), .B0(n3443), .B1(n2391), .Y(
DP_OP_454J16_123_2743_n395) );
XNOR2X1TS U4878 ( .A(n3496), .B(n2343), .Y(n3445) );
OAI22X1TS U4879 ( .A0(n3445), .A1(n2327), .B0(n3444), .B1(n2391), .Y(
DP_OP_454J16_123_2743_n396) );
XNOR2X1TS U4880 ( .A(n3498), .B(n2343), .Y(n3446) );
OAI22X1TS U4881 ( .A0(n3445), .A1(n2392), .B0(n3446), .B1(n2327), .Y(
DP_OP_454J16_123_2743_n397) );
XNOR2X1TS U4882 ( .A(n3500), .B(n2343), .Y(n3447) );
OAI22X1TS U4883 ( .A0(n3447), .A1(n2327), .B0(n3446), .B1(n2392), .Y(
DP_OP_454J16_123_2743_n398) );
XNOR2X1TS U4884 ( .A(n3502), .B(n2343), .Y(n3448) );
OAI22X1TS U4885 ( .A0(n3448), .A1(n2327), .B0(n3447), .B1(n2392), .Y(
DP_OP_454J16_123_2743_n399) );
XNOR2X1TS U4886 ( .A(n3485), .B(n2343), .Y(n3450) );
OAI22X1TS U4887 ( .A0(n3450), .A1(n2327), .B0(n3448), .B1(n2391), .Y(
DP_OP_454J16_123_2743_n400) );
OAI22X1TS U4888 ( .A0(n3450), .A1(n2391), .B0(n3449), .B1(n2327), .Y(
DP_OP_454J16_123_2743_n401) );
NOR2BX1TS U4889 ( .AN(n2445), .B(n2391), .Y(DP_OP_454J16_123_2743_n406) );
AO21X1TS U4890 ( .A0(n2441), .A1(n2389), .B0(n2202), .Y(
DP_OP_454J16_123_2743_n407) );
XNOR2X1TS U4891 ( .A(n3559), .B(n2349), .Y(n3452) );
OAI22X1TS U4892 ( .A0(n3452), .A1(n2441), .B0(n3451), .B1(n2388), .Y(
DP_OP_454J16_123_2743_n408) );
XNOR2X1TS U4893 ( .A(n3494), .B(n2349), .Y(n3453) );
OAI22X1TS U4894 ( .A0(n3453), .A1(n2441), .B0(n3452), .B1(n2389), .Y(
DP_OP_454J16_123_2743_n409) );
XNOR2X1TS U4895 ( .A(n3496), .B(n2349), .Y(n3454) );
OAI22X1TS U4896 ( .A0(n3454), .A1(n2441), .B0(n3453), .B1(n2389), .Y(
DP_OP_454J16_123_2743_n410) );
XNOR2X1TS U4897 ( .A(n3498), .B(n2349), .Y(n3455) );
OAI22X1TS U4898 ( .A0(n3454), .A1(n2389), .B0(n3455), .B1(n2441), .Y(
DP_OP_454J16_123_2743_n411) );
XNOR2X1TS U4899 ( .A(n3500), .B(n2349), .Y(n3456) );
OAI22X1TS U4900 ( .A0(n3456), .A1(n2440), .B0(n3455), .B1(n2388), .Y(
DP_OP_454J16_123_2743_n412) );
XNOR2X1TS U4901 ( .A(n3502), .B(n2349), .Y(n3457) );
OAI22X1TS U4902 ( .A0(n3457), .A1(n2441), .B0(n3456), .B1(n2388), .Y(
DP_OP_454J16_123_2743_n413) );
XNOR2X1TS U4903 ( .A(n3485), .B(n2349), .Y(n3458) );
OAI22X1TS U4904 ( .A0(n3458), .A1(n2441), .B0(n3457), .B1(n2389), .Y(
DP_OP_454J16_123_2743_n414) );
OAI22X1TS U4905 ( .A0(n3458), .A1(n2389), .B0(n3626), .B1(n2441), .Y(
DP_OP_454J16_123_2743_n415) );
XNOR2X1TS U4906 ( .A(n3477), .B(n3533), .Y(n3625) );
XNOR2X1TS U4907 ( .A(n3622), .B(n3533), .Y(n3459) );
OAI22X1TS U4908 ( .A0(n3625), .A1(n2388), .B0(n3459), .B1(n2440), .Y(
DP_OP_454J16_123_2743_n417) );
XNOR2X1TS U4909 ( .A(n3527), .B(n3533), .Y(n3531) );
OAI22X1TS U4910 ( .A0(n3459), .A1(n2389), .B0(n2440), .B1(n3531), .Y(
DP_OP_454J16_123_2743_n418) );
XNOR2X1TS U4911 ( .A(n3559), .B(n2351), .Y(n3461) );
OAI22X1TS U4912 ( .A0(n3461), .A1(n2439), .B0(n3460), .B1(n2199), .Y(
DP_OP_454J16_123_2743_n423) );
XNOR2X1TS U4913 ( .A(n3494), .B(n2351), .Y(n3462) );
OAI22X1TS U4914 ( .A0(n3462), .A1(n2439), .B0(n3461), .B1(n2199), .Y(
DP_OP_454J16_123_2743_n424) );
XNOR2X1TS U4915 ( .A(n3496), .B(n2351), .Y(n3463) );
OAI22X1TS U4916 ( .A0(n3463), .A1(n2439), .B0(n3462), .B1(n2199), .Y(
DP_OP_454J16_123_2743_n425) );
XNOR2X1TS U4917 ( .A(n3498), .B(n2351), .Y(n3464) );
OAI22X1TS U4918 ( .A0(n3463), .A1(n2387), .B0(n3464), .B1(n2439), .Y(
DP_OP_454J16_123_2743_n426) );
XNOR2X1TS U4919 ( .A(n3500), .B(n2351), .Y(n3465) );
OAI22X1TS U4920 ( .A0(n3465), .A1(n2439), .B0(n3464), .B1(n2387), .Y(
DP_OP_454J16_123_2743_n427) );
XNOR2X1TS U4921 ( .A(n3502), .B(n2351), .Y(n3466) );
OAI22X1TS U4922 ( .A0(n3466), .A1(n2439), .B0(n3465), .B1(n2387), .Y(
DP_OP_454J16_123_2743_n428) );
XNOR2X1TS U4923 ( .A(n3485), .B(n2351), .Y(n3467) );
OAI22X1TS U4924 ( .A0(n3467), .A1(n2439), .B0(n3466), .B1(n2199), .Y(
DP_OP_454J16_123_2743_n429) );
XNOR2X1TS U4925 ( .A(n3488), .B(n3535), .Y(n3468) );
OAI22X1TS U4926 ( .A0(n3467), .A1(n2199), .B0(n3468), .B1(n2439), .Y(
DP_OP_454J16_123_2743_n430) );
XNOR2X1TS U4927 ( .A(n3477), .B(n3535), .Y(n3536) );
OAI22X1TS U4928 ( .A0(n3468), .A1(n2199), .B0(n3536), .B1(n2438), .Y(
DP_OP_454J16_123_2743_n431) );
NOR2BX1TS U4929 ( .AN(n2445), .B(n2387), .Y(DP_OP_454J16_123_2743_n435) );
AO21X1TS U4930 ( .A0(n3541), .A1(n2395), .B0(n2336), .Y(
DP_OP_454J16_123_2743_n436) );
XNOR2X1TS U4931 ( .A(n3492), .B(n2338), .Y(n3469) );
OAI22X1TS U4932 ( .A0(n3469), .A1(n3541), .B0(n2577), .B1(n2336), .Y(
DP_OP_454J16_123_2743_n437) );
XNOR2X1TS U4933 ( .A(n3559), .B(n2338), .Y(n3470) );
OAI22X1TS U4934 ( .A0(n3470), .A1(n2437), .B0(n3469), .B1(n2577), .Y(
DP_OP_454J16_123_2743_n438) );
XNOR2X1TS U4935 ( .A(n3494), .B(n2338), .Y(n3471) );
OAI22X1TS U4936 ( .A0(n3471), .A1(n2437), .B0(n3470), .B1(n2395), .Y(
DP_OP_454J16_123_2743_n439) );
XNOR2X1TS U4937 ( .A(n3496), .B(n2338), .Y(n3472) );
OAI22X1TS U4938 ( .A0(n3472), .A1(n2437), .B0(n3471), .B1(n2577), .Y(
DP_OP_454J16_123_2743_n440) );
XNOR2X1TS U4939 ( .A(n3498), .B(n2338), .Y(n3473) );
OAI22X1TS U4940 ( .A0(n3472), .A1(n2395), .B0(n3473), .B1(n2437), .Y(
DP_OP_454J16_123_2743_n441) );
XNOR2X1TS U4941 ( .A(n3500), .B(n2338), .Y(n3474) );
OAI22X1TS U4942 ( .A0(n3474), .A1(n3541), .B0(n3473), .B1(n2395), .Y(
DP_OP_454J16_123_2743_n442) );
XNOR2X1TS U4943 ( .A(n3502), .B(n2338), .Y(n3475) );
OAI22X1TS U4944 ( .A0(n3475), .A1(n2437), .B0(n3474), .B1(n2577), .Y(
DP_OP_454J16_123_2743_n443) );
XNOR2X1TS U4945 ( .A(n3485), .B(n2338), .Y(n3476) );
OAI22X1TS U4946 ( .A0(n3476), .A1(n2437), .B0(n3475), .B1(n2577), .Y(
DP_OP_454J16_123_2743_n444) );
XNOR2X1TS U4947 ( .A(n3488), .B(n2337), .Y(n3544) );
OAI22X1TS U4948 ( .A0(n3476), .A1(n2395), .B0(n3544), .B1(n3541), .Y(
DP_OP_454J16_123_2743_n445) );
XNOR2X1TS U4949 ( .A(n3477), .B(n2337), .Y(n3542) );
OAI22X1TS U4950 ( .A0(n3542), .A1(n2395), .B0(n3478), .B1(n3541), .Y(
DP_OP_454J16_123_2743_n447) );
XNOR2X1TS U4951 ( .A(n3492), .B(n2335), .Y(n3479) );
OAI22X1TS U4952 ( .A0(n3479), .A1(n2436), .B0(n2393), .B1(n2333), .Y(
DP_OP_454J16_123_2743_n452) );
XNOR2X1TS U4953 ( .A(n3559), .B(n3487), .Y(n3480) );
OAI22X1TS U4954 ( .A0(n3480), .A1(n2436), .B0(n3479), .B1(n2393), .Y(
DP_OP_454J16_123_2743_n453) );
XNOR2X1TS U4955 ( .A(n3494), .B(n2335), .Y(n3481) );
OAI22X1TS U4956 ( .A0(n3481), .A1(n2436), .B0(n3480), .B1(n2200), .Y(
DP_OP_454J16_123_2743_n454) );
XNOR2X1TS U4957 ( .A(n3496), .B(n2335), .Y(n3482) );
OAI22X1TS U4958 ( .A0(n3482), .A1(n2436), .B0(n3481), .B1(n2200), .Y(
DP_OP_454J16_123_2743_n455) );
XNOR2X1TS U4959 ( .A(n3498), .B(n2335), .Y(n3483) );
OAI22X1TS U4960 ( .A0(n3482), .A1(n2200), .B0(n3483), .B1(n2436), .Y(
DP_OP_454J16_123_2743_n456) );
XNOR2X1TS U4961 ( .A(n3500), .B(n2335), .Y(n3484) );
OAI22X1TS U4962 ( .A0(n3484), .A1(n2436), .B0(n3483), .B1(n2393), .Y(
DP_OP_454J16_123_2743_n457) );
XNOR2X1TS U4963 ( .A(n3502), .B(n3487), .Y(n3486) );
OAI22X1TS U4964 ( .A0(n3486), .A1(n2436), .B0(n3484), .B1(n2393), .Y(
DP_OP_454J16_123_2743_n458) );
XNOR2X1TS U4965 ( .A(n3485), .B(n2335), .Y(n3489) );
OAI22X1TS U4966 ( .A0(n3489), .A1(n2436), .B0(n3486), .B1(n2200), .Y(
DP_OP_454J16_123_2743_n459) );
XNOR2X1TS U4967 ( .A(n3488), .B(n2334), .Y(n3491) );
OAI22X1TS U4968 ( .A0(n3489), .A1(n2200), .B0(n3491), .B1(n2435), .Y(
DP_OP_454J16_123_2743_n460) );
OAI22X1TS U4969 ( .A0(n3491), .A1(n2200), .B0(n3490), .B1(n2435), .Y(
DP_OP_454J16_123_2743_n461) );
XNOR2X1TS U4970 ( .A(n3492), .B(n2325), .Y(n3493) );
OAI22X1TS U4971 ( .A0(n3493), .A1(n3506), .B0(n2241), .B1(n2332), .Y(
DP_OP_454J16_123_2743_n467) );
XNOR2X1TS U4972 ( .A(n3559), .B(n2325), .Y(n3495) );
OAI22X1TS U4973 ( .A0(n3495), .A1(n3504), .B0(n3493), .B1(n3508), .Y(
DP_OP_454J16_123_2743_n468) );
XNOR2X1TS U4974 ( .A(n3494), .B(n2325), .Y(n3497) );
OAI22X1TS U4975 ( .A0(n3497), .A1(n3504), .B0(n3495), .B1(n2332), .Y(
DP_OP_454J16_123_2743_n469) );
XNOR2X1TS U4976 ( .A(n3496), .B(n2325), .Y(n3499) );
OAI22X1TS U4977 ( .A0(n3499), .A1(n3506), .B0(n3497), .B1(n3508), .Y(
DP_OP_454J16_123_2743_n470) );
XNOR2X1TS U4978 ( .A(n3498), .B(n2325), .Y(n3501) );
OAI22X1TS U4979 ( .A0(n3499), .A1(n2332), .B0(n3501), .B1(n3504), .Y(
DP_OP_454J16_123_2743_n471) );
XNOR2X1TS U4980 ( .A(n3500), .B(n2325), .Y(n3503) );
OAI22X1TS U4981 ( .A0(n3503), .A1(n3506), .B0(n3501), .B1(n2332), .Y(
DP_OP_454J16_123_2743_n472) );
XNOR2X1TS U4982 ( .A(n3502), .B(n2325), .Y(n3505) );
OAI22X1TS U4983 ( .A0(n3505), .A1(n3504), .B0(n3503), .B1(n2332), .Y(
DP_OP_454J16_123_2743_n473) );
OAI22X1TS U4984 ( .A0(n3507), .A1(n3506), .B0(n3505), .B1(n2332), .Y(
DP_OP_454J16_123_2743_n474) );
NOR2BX1TS U4985 ( .AN(n2445), .B(n3508), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N0) );
OAI22X1TS U4986 ( .A0(n2438), .A1(n2350), .B0(n2387), .B1(n3513), .Y(n3516)
);
XNOR2X1TS U4987 ( .A(n2351), .B(n3621), .Y(n3514) );
XNOR2X1TS U4988 ( .A(n3527), .B(n3535), .Y(n3539) );
OAI22X1TS U4989 ( .A0(n2438), .A1(n3514), .B0(n2387), .B1(n3539), .Y(n3515)
);
ADDHX1TS U4990 ( .A(n3516), .B(n3515), .CO(DP_OP_454J16_123_2743_n362), .S(
DP_OP_454J16_123_2743_n363) );
INVX2TS U4991 ( .A(DP_OP_454J16_123_2743_n263), .Y(
DP_OP_454J16_123_2743_n264) );
AO21X4TS U4992 ( .A0(n2435), .A1(n2393), .B0(n2333), .Y(n3556) );
OAI22X1TS U4993 ( .A0(n3520), .A1(n2313), .B0(n3519), .B1(n2712), .Y(n3555)
);
INVX2TS U4994 ( .A(DP_OP_454J16_123_2743_n289), .Y(
DP_OP_454J16_123_2743_n290) );
INVX2TS U4995 ( .A(n3521), .Y(n3523) );
NAND2X1TS U4996 ( .A(n3523), .B(n3522), .Y(n3524) );
OAI22X1TS U4997 ( .A0(n3629), .A1(n2341), .B0(n2391), .B1(n3526), .Y(n3530)
);
XNOR2X1TS U4998 ( .A(n2342), .B(n3621), .Y(n3528) );
OAI22X1TS U4999 ( .A0(n3629), .A1(n3528), .B0(n3623), .B1(n2392), .Y(n3529)
);
ADDHX1TS U5000 ( .A(n3530), .B(n3529), .CO(DP_OP_454J16_123_2743_n339), .S(
DP_OP_454J16_123_2743_n340) );
XNOR2X1TS U5001 ( .A(n2349), .B(n3621), .Y(n3532) );
OAI22X1TS U5002 ( .A0(n2440), .A1(n3532), .B0(n3531), .B1(n2388), .Y(n3538)
);
OAI22X1TS U5003 ( .A0(n2440), .A1(n2202), .B0(n2388), .B1(n3534), .Y(n3537)
);
XNOR2X1TS U5004 ( .A(n3622), .B(n3535), .Y(n3540) );
OAI22X1TS U5005 ( .A0(n3536), .A1(n2199), .B0(n3540), .B1(n2438), .Y(n3547)
);
ADDHX1TS U5006 ( .A(n3538), .B(n3537), .CO(DP_OP_454J16_123_2743_n352), .S(
n3546) );
NOR2BX1TS U5007 ( .AN(n2445), .B(n2389), .Y(n3620) );
OAI22X1TS U5008 ( .A0(n3540), .A1(n2199), .B0(n2438), .B1(n3539), .Y(n3619)
);
OAI22X1TS U5009 ( .A0(n3544), .A1(n2395), .B0(n3542), .B1(n3541), .Y(n3618)
);
OAI22X1TS U5010 ( .A0(n3551), .A1(n2422), .B0(n3550), .B1(n2314), .Y(n3553)
);
NAND2X2TS U5011 ( .A(n3568), .B(n2232), .Y(n3588) );
OAI22X1TS U5012 ( .A0(n3558), .A1(n2327), .B0(n2392), .B1(n2341), .Y(n3579)
);
INVX2TS U5013 ( .A(n3579), .Y(n3562) );
INVX2TS U5014 ( .A(n3559), .Y(n3563) );
OAI22X1TS U5015 ( .A0(n3560), .A1(n2422), .B0(n3563), .B1(n2314), .Y(n3561)
);
NOR2X2TS U5016 ( .A(DP_OP_454J16_123_2743_n258), .B(n3569), .Y(n3610) );
INVX2TS U5017 ( .A(n3610), .Y(n3596) );
CMPR32X2TS U5018 ( .A(n3562), .B(n3561), .C(DP_OP_454J16_123_2743_n257),
.CO(n3571), .S(n3569) );
OAI22X1TS U5019 ( .A0(n3563), .A1(n2422), .B0(n2314), .B1(n3581), .Y(n3578)
);
OAI21X1TS U5020 ( .A0(n3604), .A1(n3565), .B0(n3564), .Y(n3566) );
INVX2TS U5021 ( .A(n3609), .Y(n3573) );
NAND2X1TS U5022 ( .A(n3571), .B(n3570), .Y(n3614) );
INVX2TS U5023 ( .A(n3614), .Y(n3572) );
AOI21X1TS U5024 ( .A0(n3573), .A1(n3615), .B0(n3572), .Y(n3574) );
OAI21X1TS U5025 ( .A0(n3590), .A1(n3575), .B0(n3574), .Y(n3576) );
CMPR32X2TS U5026 ( .A(n3580), .B(n3579), .C(n3578), .CO(n3583), .S(n3570) );
NAND2X1TS U5027 ( .A(n3583), .B(n3582), .Y(n3584) );
NAND2X1TS U5028 ( .A(n3585), .B(n3584), .Y(n3586) );
NAND2X2TS U5029 ( .A(n3589), .B(n3592), .Y(n3608) );
INVX2TS U5030 ( .A(n3608), .Y(n3595) );
INVX2TS U5031 ( .A(n3590), .Y(n3591) );
INVX2TS U5032 ( .A(n3611), .Y(n3594) );
AOI21X2TS U5033 ( .A0(n3643), .A1(n3595), .B0(n3594), .Y(n3598) );
NAND2X1TS U5034 ( .A(n3596), .B(n3609), .Y(n3597) );
INVX2TS U5035 ( .A(n3599), .Y(n3602) );
INVX2TS U5036 ( .A(n3600), .Y(n3601) );
AOI21X2TS U5037 ( .A0(n3643), .A1(n3602), .B0(n3601), .Y(n3607) );
INVX2TS U5038 ( .A(n3603), .Y(n3605) );
NAND2X1TS U5039 ( .A(n3605), .B(n3604), .Y(n3606) );
NOR2X1TS U5040 ( .A(n3608), .B(n3610), .Y(n3613) );
OAI21X1TS U5041 ( .A0(n3611), .A1(n3610), .B0(n3609), .Y(n3612) );
AOI21X2TS U5042 ( .A0(n3643), .A1(n3613), .B0(n3612), .Y(n3617) );
NAND2X1TS U5043 ( .A(n3615), .B(n3614), .Y(n3616) );
NOR2BX1TS U5044 ( .AN(n2445), .B(n2313), .Y(n3634) );
OAI22X2TS U5045 ( .A0(n3630), .A1(n2392), .B0(n3629), .B1(n3623), .Y(n3633)
);
OAI22X1TS U5046 ( .A0(n3626), .A1(n2389), .B0(n3625), .B1(n2440), .Y(n3632)
);
OAI22X1TS U5047 ( .A0(n3628), .A1(n2314), .B0(n2422), .B1(n3627), .Y(n3637)
);
OAI22X1TS U5048 ( .A0(n3631), .A1(n2391), .B0(n3630), .B1(n3629), .Y(n3636)
);
CMPR32X2TS U5049 ( .A(n3634), .B(n3633), .C(n3632), .CO(n3635), .S(
DP_OP_454J16_123_2743_n332) );
CMPR32X2TS U5050 ( .A(n3637), .B(n3636), .C(n3635), .CO(
DP_OP_454J16_123_2743_n323), .S(DP_OP_454J16_123_2743_n324) );
INVX2TS U5051 ( .A(n3640), .Y(n3641) );
AOI21X4TS U5052 ( .A0(n3643), .A1(n3642), .B0(n3641), .Y(n3648) );
INVX2TS U5053 ( .A(n3644), .Y(n3646) );
NAND2X2TS U5054 ( .A(n5117), .B(n5858), .Y(n4695) );
NOR4X1TS U5055 ( .A(FPMULT_P_Sgf[13]), .B(FPMULT_P_Sgf[17]), .C(
FPMULT_P_Sgf[15]), .D(FPMULT_P_Sgf[16]), .Y(n3654) );
NOR4X1TS U5056 ( .A(FPMULT_P_Sgf[20]), .B(FPMULT_P_Sgf[18]), .C(
FPMULT_P_Sgf[19]), .D(FPMULT_P_Sgf[21]), .Y(n3653) );
NOR4X1TS U5057 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_P_Sgf[5]), .C(
FPMULT_P_Sgf[3]), .D(FPMULT_P_Sgf[4]), .Y(n3651) );
NOR3XLTS U5058 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[2]), .C(
FPMULT_P_Sgf[0]), .Y(n3650) );
AND4X1TS U5059 ( .A(n3651), .B(n3650), .C(n3649), .D(n2271), .Y(n3652) );
XOR2X1TS U5060 ( .A(FPMULT_Op_MY[31]), .B(FPMULT_Op_MX[31]), .Y(n5695) );
MXI2X1TS U5061 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n5695), .Y(n3655) );
OAI211X1TS U5062 ( .A0(r_mode[0]), .A1(r_mode[1]), .B0(n3656), .C0(n3655),
.Y(n4697) );
OAI31X1TS U5063 ( .A0(n2283), .A1(n4695), .A2(n4697), .B0(n5873), .Y(n1528)
);
AOI21X1TS U5064 ( .A0(operation[1]), .A1(ack_operation), .B0(n4236), .Y(
n5456) );
NAND2X1TS U5065 ( .A(n3658), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]),
.Y(n3660) );
NAND2BX2TS U5066 ( .AN(n3660), .B(n3698), .Y(n5482) );
NAND2X2TS U5067 ( .A(FPSENCOS_cont_iter_out[3]), .B(n2302), .Y(n4137) );
INVX2TS U5068 ( .A(n4137), .Y(n5495) );
OR2X1TS U5069 ( .A(n5456), .B(n4237), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
OR4X2TS U5070 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3663) );
NAND4X2TS U5071 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n3661),
.C(n5824), .D(n5846), .Y(n5461) );
INVX2TS U5072 ( .A(n5644), .Y(n5650) );
NAND2X1TS U5073 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n5459) );
NAND3X2TS U5074 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n4188),
.C(n5846), .Y(n5460) );
NOR4X1TS U5075 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n3668) );
NOR4X1TS U5076 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n3667) );
NOR4X1TS U5077 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n3666) );
INVX2TS U5078 ( .A(n5018), .Y(n5787) );
BUFX3TS U5079 ( .A(n5787), .Y(n5718) );
NAND2X2TS U5080 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n5035) );
NOR2X2TS U5081 ( .A(n5854), .B(n5035), .Y(n5060) );
OAI22X1TS U5082 ( .A0(n5831), .A1(n5036), .B0(n5870), .B1(n4094), .Y(n3670)
);
AOI22X1TS U5083 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n2353), .B0(
FPADDSUB_Data_array_SWR[0]), .B1(n2383), .Y(n3676) );
INVX2TS U5084 ( .A(n5064), .Y(n3673) );
AOI22X1TS U5085 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2303), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n2384), .Y(n3675) );
OAI211X1TS U5086 ( .A0(n5079), .A1(n2254), .B0(n3676), .C0(n3675), .Y(n4002)
);
NOR2X2TS U5087 ( .A(n2293), .B(n2267), .Y(n5030) );
NOR2X4TS U5088 ( .A(n2322), .B(n2267), .Y(n5071) );
AOI21X1TS U5089 ( .A0(n3677), .A1(n5020), .B0(n5787), .Y(n3678) );
NOR2X1TS U5090 ( .A(n5819), .B(FPMULT_FS_Module_state_reg[0]), .Y(n3679) );
NAND2X2TS U5091 ( .A(n5841), .B(n3679), .Y(n4725) );
NOR2X1TS U5092 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n5310) );
NAND2X1TS U5093 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n5322) );
NAND2X1TS U5094 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n5311) );
OAI21X1TS U5095 ( .A0(n5310), .A1(n5322), .B0(n5311), .Y(n4018) );
NOR2X2TS U5096 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n4040) );
NAND2X1TS U5097 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4044) );
NAND2X1TS U5098 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n4041) );
NOR2X1TS U5099 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n4032) );
NOR2X1TS U5100 ( .A(n4032), .B(n4058), .Y(n4076) );
NOR2X2TS U5101 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n5343) );
NOR2X1TS U5102 ( .A(n5349), .B(n5343), .Y(n3683) );
NAND2X1TS U5103 ( .A(n4076), .B(n3683), .Y(n3685) );
NAND2X1TS U5104 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n4062) );
NAND2X1TS U5105 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n4059) );
OAI21X1TS U5106 ( .A0(n4058), .A1(n4062), .B0(n4059), .Y(n4075) );
NAND2X1TS U5107 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n5348) );
NAND2X1TS U5108 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n5344) );
AOI21X1TS U5109 ( .A0(n4075), .A1(n3683), .B0(n3682), .Y(n3684) );
NOR2X1TS U5110 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n5292) );
INVX2TS U5111 ( .A(n5292), .Y(n5302) );
NAND2X1TS U5112 ( .A(n5302), .B(n5288), .Y(n5336) );
NOR2X2TS U5113 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]),
.Y(n5330) );
NOR2X1TS U5114 ( .A(n5336), .B(n5330), .Y(n3689) );
NAND2X1TS U5115 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n5301) );
INVX2TS U5116 ( .A(n5301), .Y(n3687) );
NAND2X1TS U5117 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n5287) );
INVX2TS U5118 ( .A(n5287), .Y(n3686) );
AOI21X1TS U5119 ( .A0(n5288), .A1(n3687), .B0(n3686), .Y(n5335) );
NAND2X1TS U5120 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n5331) );
OAI21X1TS U5121 ( .A0(n5335), .A1(n5330), .B0(n5331), .Y(n3688) );
NOR2X1TS U5122 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]),
.Y(n5272) );
NAND2X1TS U5123 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n5273) );
NAND2X1TS U5124 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n5263) );
INVX2TS U5125 ( .A(n5263), .Y(n3690) );
NOR2X1TS U5126 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]),
.Y(n5141) );
NAND2X1TS U5127 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n5142) );
NAND2X1TS U5128 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n5153) );
INVX2TS U5129 ( .A(n5153), .Y(n3691) );
NOR2X1TS U5130 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]),
.Y(n5164) );
NAND2X1TS U5131 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n5165) );
NAND2X1TS U5132 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n5254) );
INVX2TS U5133 ( .A(n5254), .Y(n3692) );
NOR2X1TS U5134 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]),
.Y(n5223) );
NAND2X1TS U5135 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n5224) );
OAI21X4TS U5136 ( .A0(n5229), .A1(n5223), .B0(n5224), .Y(n5238) );
NAND2X1TS U5137 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n5233) );
INVX2TS U5138 ( .A(n5233), .Y(n3693) );
AOI21X4TS U5139 ( .A0(n5238), .A1(n5234), .B0(n3693), .Y(n5248) );
NOR2X1TS U5140 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]),
.Y(n5242) );
NAND2X1TS U5141 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n5243) );
NAND2X1TS U5142 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n5214) );
INVX2TS U5143 ( .A(n5214), .Y(n3694) );
AOI21X4TS U5144 ( .A0(n5219), .A1(n5215), .B0(n3694), .Y(n5210) );
NOR2X1TS U5145 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]),
.Y(n5204) );
NAND2X1TS U5146 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n5205) );
NAND2X1TS U5147 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n5195) );
INVX2TS U5148 ( .A(n5195), .Y(n3695) );
NAND2X1TS U5149 ( .A(n5191), .B(n5940), .Y(n3696) );
BUFX3TS U5150 ( .A(n5715), .Y(n5353) );
INVX2TS U5151 ( .A(n6077), .Y(n5804) );
INVX2TS U5152 ( .A(n5804), .Y(n5714) );
NOR2X1TS U5153 ( .A(n2218), .B(n5861), .Y(n4586) );
INVX2TS U5154 ( .A(n4586), .Y(n4480) );
INVX2TS U5155 ( .A(n4480), .Y(n4686) );
BUFX3TS U5156 ( .A(n5552), .Y(n6069) );
INVX2TS U5157 ( .A(FPMULT_Sgf_operation_Result[1]), .Y(n3703) );
XNOR2X1TS U5158 ( .A(n3703), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]), .Y(n3702) );
INVX2TS U5159 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(n3701) );
INVX2TS U5160 ( .A(n5815), .Y(n5416) );
OR2X2TS U5161 ( .A(n5815), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]), .Y(n3853) );
INVX2TS U5162 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .Y(n3854) );
NAND2X2TS U5163 ( .A(n5815), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]), .Y(n3852) );
INVX2TS U5164 ( .A(n3852), .Y(n3700) );
AOI21X1TS U5165 ( .A0(n3853), .A1(n3854), .B0(n3700), .Y(n3850) );
OAI21X2TS U5166 ( .A0(n3847), .A1(n3850), .B0(n3848), .Y(n3857) );
INVX2TS U5167 ( .A(FPMULT_Sgf_operation_Result[2]), .Y(n3705) );
INVX2TS U5168 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .Y(n3704) );
NOR2X2TS U5169 ( .A(n3707), .B(n3706), .Y(n3867) );
INVX2TS U5170 ( .A(FPMULT_Sgf_operation_Result[3]), .Y(n3713) );
INVX2TS U5171 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .Y(n3712) );
CMPR32X2TS U5172 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]), .B(
n3705), .C(n3704), .CO(n3708), .S(n3707) );
AOI21X4TS U5173 ( .A0(n3857), .A1(n3711), .B0(n3710), .Y(n3835) );
INVX2TS U5174 ( .A(FPMULT_Sgf_operation_Result[4]), .Y(n3715) );
INVX2TS U5175 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(n3714) );
CMPR32X2TS U5176 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]), .B(
n3713), .C(n3712), .CO(n3720), .S(n3709) );
INVX2TS U5177 ( .A(FPMULT_Sgf_operation_Result[5]), .Y(n3717) );
INVX2TS U5178 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .Y(n3716) );
CMPR32X2TS U5179 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]), .B(
n3715), .C(n3714), .CO(n3722), .S(n3721) );
INVX2TS U5180 ( .A(FPMULT_Sgf_operation_Result[6]), .Y(n3719) );
INVX2TS U5181 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .Y(n3718) );
CMPR32X2TS U5182 ( .A(n3717), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]), .C(n3716), .CO(
n3724), .S(n3723) );
NOR2X2TS U5183 ( .A(n3725), .B(n3724), .Y(n3886) );
INVX2TS U5184 ( .A(FPMULT_Sgf_operation_Result[7]), .Y(n3738) );
INVX2TS U5185 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(n3737) );
CMPR32X2TS U5186 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]), .B(
n3719), .C(n3718), .CO(n3726), .S(n3725) );
NOR2X2TS U5187 ( .A(n3727), .B(n3726), .Y(n3888) );
NOR2X2TS U5188 ( .A(n3886), .B(n3888), .Y(n3729) );
NAND2X2TS U5189 ( .A(n3837), .B(n3729), .Y(n3731) );
NAND2X2TS U5190 ( .A(n3721), .B(n3720), .Y(n3862) );
NAND2X1TS U5191 ( .A(n3723), .B(n3722), .Y(n3843) );
OAI21X2TS U5192 ( .A0(n3842), .A1(n3862), .B0(n3843), .Y(n3836) );
NAND2X1TS U5193 ( .A(n3727), .B(n3726), .Y(n3889) );
AOI21X4TS U5194 ( .A0(n3836), .A1(n3729), .B0(n3728), .Y(n3730) );
OAI21X4TS U5195 ( .A0(n3835), .A1(n3731), .B0(n3730), .Y(n3776) );
INVX2TS U5196 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .Y(
n3733) );
INVX2TS U5197 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(
n3732) );
INVX2TS U5198 ( .A(FPMULT_Sgf_operation_Result[11]), .Y(n3744) );
INVX2TS U5199 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .Y(
n3743) );
NOR2X2TS U5200 ( .A(n3749), .B(n3748), .Y(n3819) );
INVX2TS U5201 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .Y(
n3735) );
INVX2TS U5202 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]), .Y(
n3734) );
CMPR32X2TS U5203 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]),
.B(n3733), .C(n3732), .CO(n3750), .S(n3749) );
NOR2X2TS U5204 ( .A(n3751), .B(n3750), .Y(n3826) );
NOR2X2TS U5205 ( .A(n3819), .B(n3826), .Y(n3779) );
INVX4TS U5206 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[14]), .Y(
n4801) );
INVX2TS U5207 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[14]), .Y(
n3736) );
CMPR32X2TS U5208 ( .A(n3735), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]), .C(n3734), .CO(
n3752), .S(n3751) );
NOR2X2TS U5209 ( .A(n3753), .B(n3752), .Y(n3783) );
INVX2TS U5210 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .Y(
n4787) );
INVX2TS U5211 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .Y(
n3772) );
CMPR32X2TS U5212 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]),
.B(n4801), .C(n3736), .CO(n3754), .S(n3753) );
NOR2X2TS U5213 ( .A(n3783), .B(n3785), .Y(n3757) );
NAND2X2TS U5214 ( .A(n3779), .B(n3757), .Y(n3768) );
INVX2TS U5215 ( .A(FPMULT_Sgf_operation_Result[8]), .Y(n3740) );
INVX2TS U5216 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .Y(n3739) );
CMPR32X2TS U5217 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]), .B(
n3738), .C(n3737), .CO(n3758), .S(n3727) );
NOR2X2TS U5218 ( .A(n3759), .B(n3758), .Y(n3894) );
INVX2TS U5219 ( .A(FPMULT_Sgf_operation_Result[9]), .Y(n3742) );
INVX2TS U5220 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .Y(n3741) );
NOR2X2TS U5221 ( .A(n3761), .B(n3760), .Y(n3896) );
NOR2X2TS U5222 ( .A(n3894), .B(n3896), .Y(n3808) );
INVX2TS U5223 ( .A(FPMULT_Sgf_operation_Result[10]), .Y(n3746) );
INVX2TS U5224 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .Y(
n3745) );
CMPR32X2TS U5225 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]), .B(
n3742), .C(n3741), .CO(n3762), .S(n3761) );
NOR2X2TS U5226 ( .A(n3763), .B(n3762), .Y(n3812) );
CMPR32X2TS U5227 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]),
.B(n3744), .C(n3743), .CO(n3748), .S(n3765) );
CMPR32X2TS U5228 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]),
.B(n3746), .C(n3745), .CO(n3764), .S(n3763) );
NOR2X2TS U5229 ( .A(n3765), .B(n3764), .Y(n3814) );
NOR2X2TS U5230 ( .A(n3812), .B(n3814), .Y(n3767) );
NAND2X2TS U5231 ( .A(n3808), .B(n3767), .Y(n3778) );
NOR2X2TS U5232 ( .A(n3768), .B(n3778), .Y(n3747) );
NAND2X2TS U5233 ( .A(n3749), .B(n3748), .Y(n3822) );
NAND2X1TS U5234 ( .A(n3751), .B(n3750), .Y(n3827) );
NAND2X1TS U5235 ( .A(n3755), .B(n3754), .Y(n3786) );
OAI21X1TS U5236 ( .A0(n3785), .A1(n3831), .B0(n3786), .Y(n3756) );
AOI21X2TS U5237 ( .A0(n3780), .A1(n3757), .B0(n3756), .Y(n3770) );
NAND2X1TS U5238 ( .A(n3761), .B(n3760), .Y(n3897) );
NAND2X2TS U5239 ( .A(n3763), .B(n3762), .Y(n3901) );
NAND2X1TS U5240 ( .A(n3765), .B(n3764), .Y(n3815) );
OAI21X1TS U5241 ( .A0(n3814), .A1(n3901), .B0(n3815), .Y(n3766) );
AOI21X4TS U5242 ( .A0(n3809), .A1(n3767), .B0(n3766), .Y(n3777) );
OR2X4TS U5243 ( .A(n3777), .B(n3768), .Y(n3769) );
INVX2TS U5244 ( .A(n3803), .Y(n3791) );
INVX2TS U5245 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[16]), .Y(
n4775) );
INVX2TS U5246 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .Y(
n3792) );
CMPR32X2TS U5247 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]),
.B(n4787), .C(n3772), .CO(n3773), .S(n3755) );
NAND2X1TS U5248 ( .A(n3774), .B(n3773), .Y(n3790) );
NAND2X1TS U5249 ( .A(n3797), .B(n3790), .Y(n3775) );
XNOR2X1TS U5250 ( .A(n3791), .B(n3775), .Y(n3920) );
NOR2X2TS U5251 ( .A(n3920), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(n4929) );
INVX4TS U5252 ( .A(n3776), .Y(n3895) );
OAI21X4TS U5253 ( .A0(n3895), .A1(n3778), .B0(n3777), .Y(n3825) );
INVX4TS U5254 ( .A(n3825), .Y(n3821) );
INVX2TS U5255 ( .A(n3779), .Y(n3782) );
INVX2TS U5256 ( .A(n3780), .Y(n3781) );
INVX2TS U5257 ( .A(n3783), .Y(n3832) );
INVX2TS U5258 ( .A(n3831), .Y(n3784) );
AOI21X1TS U5259 ( .A0(n3834), .A1(n3832), .B0(n3784), .Y(n3789) );
INVX2TS U5260 ( .A(n3785), .Y(n3787) );
NAND2X1TS U5261 ( .A(n3787), .B(n3786), .Y(n3788) );
CLKXOR2X2TS U5262 ( .A(n3789), .B(n3788), .Y(n3919) );
NOR2X2TS U5263 ( .A(n3919), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .Y(n4926) );
INVX2TS U5264 ( .A(n3790), .Y(n3800) );
AOI21X1TS U5265 ( .A0(n3791), .A1(n3797), .B0(n3800), .Y(n3796) );
INVX2TS U5266 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[17]), .Y(
n4767) );
INVX2TS U5267 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]), .Y(
n3804) );
CMPR32X2TS U5268 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]),
.B(n4775), .C(n3792), .CO(n3793), .S(n3774) );
NAND2X1TS U5269 ( .A(n3794), .B(n3793), .Y(n3798) );
NAND2X1TS U5270 ( .A(n2531), .B(n3798), .Y(n3795) );
CLKXOR2X2TS U5271 ( .A(n3796), .B(n3795), .Y(n3921) );
NOR2X2TS U5272 ( .A(n3921), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .Y(n4903) );
INVX2TS U5273 ( .A(n3798), .Y(n3799) );
AOI21X1TS U5274 ( .A0(n2531), .A1(n3800), .B0(n3799), .Y(n3801) );
OAI21X4TS U5275 ( .A0(n3803), .A1(n3802), .B0(n3801), .Y(n3932) );
INVX2TS U5276 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[18]), .Y(
n4758) );
INVX2TS U5277 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]), .Y(
n3933) );
CMPR32X2TS U5278 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]),
.B(n4767), .C(n3804), .CO(n3805), .S(n3794) );
NAND2X1TS U5279 ( .A(n3806), .B(n3805), .Y(n3929) );
NAND2X1TS U5280 ( .A(n3931), .B(n3929), .Y(n3807) );
XNOR2X1TS U5281 ( .A(n3932), .B(n3807), .Y(n3922) );
NOR2X2TS U5282 ( .A(n3922), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .Y(n4905) );
NAND2X2TS U5283 ( .A(n4899), .B(n3924), .Y(n3926) );
INVX2TS U5284 ( .A(n3808), .Y(n3811) );
INVX2TS U5285 ( .A(n3809), .Y(n3810) );
INVX2TS U5286 ( .A(n3812), .Y(n3902) );
INVX2TS U5287 ( .A(n3901), .Y(n3813) );
AOI21X1TS U5288 ( .A0(n3904), .A1(n3902), .B0(n3813), .Y(n3818) );
NAND2X1TS U5289 ( .A(n3816), .B(n3815), .Y(n3817) );
CLKXOR2X2TS U5290 ( .A(n3818), .B(n3817), .Y(n3913) );
NOR2X2TS U5291 ( .A(n3913), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .Y(n4989) );
INVX2TS U5292 ( .A(n3819), .Y(n3824) );
NAND2X1TS U5293 ( .A(n3824), .B(n3822), .Y(n3820) );
XOR2X1TS U5294 ( .A(n3821), .B(n3820), .Y(n3914) );
NOR2X2TS U5295 ( .A(n3914), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .Y(n4979) );
INVX2TS U5296 ( .A(n3822), .Y(n3823) );
AOI21X1TS U5297 ( .A0(n3825), .A1(n3824), .B0(n3823), .Y(n3830) );
NAND2X1TS U5298 ( .A(n3828), .B(n3827), .Y(n3829) );
XOR2X1TS U5299 ( .A(n3830), .B(n3829), .Y(n3915) );
NAND2X1TS U5300 ( .A(n3832), .B(n3831), .Y(n3833) );
XNOR2X1TS U5301 ( .A(n3834), .B(n3833), .Y(n3916) );
NOR2X2TS U5302 ( .A(n3916), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .Y(n4957) );
NOR2X2TS U5303 ( .A(n3926), .B(n4898), .Y(n3928) );
NAND2X1TS U5304 ( .A(n3838), .B(n3885), .Y(n3839) );
XOR2X1TS U5305 ( .A(n3887), .B(n3839), .Y(n3880) );
NOR2X2TS U5306 ( .A(n3880), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]), .Y(n5391) );
INVX2TS U5307 ( .A(n3840), .Y(n3863) );
INVX2TS U5308 ( .A(n3862), .Y(n3841) );
AOI21X1TS U5309 ( .A0(n3865), .A1(n3863), .B0(n3841), .Y(n3846) );
NAND2X1TS U5310 ( .A(n3844), .B(n3843), .Y(n3845) );
XOR2X1TS U5311 ( .A(n3846), .B(n3845), .Y(n3879) );
NOR2X2TS U5312 ( .A(n3879), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]), .Y(n5389) );
NOR2X1TS U5313 ( .A(n5391), .B(n5389), .Y(n3882) );
NAND2X1TS U5314 ( .A(n3849), .B(n3848), .Y(n3851) );
XOR2X1TS U5315 ( .A(n3851), .B(n3850), .Y(n3856) );
NOR2X1TS U5316 ( .A(n3856), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]), .Y(n5359) );
NAND2X1TS U5317 ( .A(n3853), .B(n3852), .Y(n3855) );
XNOR2X1TS U5318 ( .A(n3855), .B(n3854), .Y(n5421) );
NAND2X1TS U5319 ( .A(n5421), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(n5422) );
NAND2X1TS U5320 ( .A(n3856), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]), .Y(n5360) );
OAI21X1TS U5321 ( .A0(n5359), .A1(n5422), .B0(n5360), .Y(n5418) );
INVX2TS U5322 ( .A(n3857), .Y(n3868) );
INVX2TS U5323 ( .A(n3867), .Y(n3858) );
NAND2X1TS U5324 ( .A(n3858), .B(n3866), .Y(n3859) );
XOR2X1TS U5325 ( .A(n3868), .B(n3859), .Y(n3860) );
NAND2X1TS U5326 ( .A(n3860), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[14]), .Y(n5417) );
INVX2TS U5327 ( .A(n5417), .Y(n3861) );
AOI21X1TS U5328 ( .A0(n5418), .A1(n2497), .B0(n3861), .Y(n5368) );
NAND2X1TS U5329 ( .A(n3863), .B(n3862), .Y(n3864) );
XNOR2X1TS U5330 ( .A(n3865), .B(n3864), .Y(n3875) );
OAI21X1TS U5331 ( .A0(n3868), .A1(n3867), .B0(n3866), .Y(n3873) );
INVX2TS U5332 ( .A(n3869), .Y(n3871) );
NAND2X1TS U5333 ( .A(n3871), .B(n3870), .Y(n3872) );
XNOR2X1TS U5334 ( .A(n3873), .B(n3872), .Y(n3874) );
NAND2X1TS U5335 ( .A(n2454), .B(n2453), .Y(n3878) );
NAND2X1TS U5336 ( .A(n3874), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .Y(n5369) );
INVX2TS U5337 ( .A(n5369), .Y(n5372) );
NAND2X1TS U5338 ( .A(n3875), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .Y(n5374) );
INVX2TS U5339 ( .A(n5374), .Y(n3876) );
AOI21X1TS U5340 ( .A0(n2454), .A1(n5372), .B0(n3876), .Y(n3877) );
NAND2X1TS U5341 ( .A(n3879), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]), .Y(n5388) );
NAND2X1TS U5342 ( .A(n3880), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]), .Y(n5392) );
OAI21X1TS U5343 ( .A0(n5391), .A1(n5388), .B0(n5392), .Y(n3881) );
AOI21X2TS U5344 ( .A0(n3882), .A1(n5364), .B0(n3881), .Y(n5379) );
INVX2TS U5345 ( .A(n3894), .Y(n3883) );
NAND2X1TS U5346 ( .A(n3883), .B(n3893), .Y(n3884) );
XOR2X1TS U5347 ( .A(n3895), .B(n3884), .Y(n3906) );
NOR2X2TS U5348 ( .A(n3906), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]), .Y(n5382) );
OAI21X1TS U5349 ( .A0(n3887), .A1(n3886), .B0(n3885), .Y(n3892) );
NAND2X1TS U5350 ( .A(n3890), .B(n3889), .Y(n3891) );
OAI21X1TS U5351 ( .A0(n3895), .A1(n3894), .B0(n3893), .Y(n3900) );
NAND2X1TS U5352 ( .A(n3898), .B(n3897), .Y(n3899) );
XNOR2X1TS U5353 ( .A(n3900), .B(n3899), .Y(n3907) );
NOR2X2TS U5354 ( .A(n3907), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[21]), .Y(n5408) );
NAND2X1TS U5355 ( .A(n3902), .B(n3901), .Y(n3903) );
XNOR2X1TS U5356 ( .A(n3904), .B(n3903), .Y(n3908) );
NOR2X2TS U5357 ( .A(n3908), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[22]), .Y(n5410) );
NOR2X2TS U5358 ( .A(n5408), .B(n5410), .Y(n3910) );
NAND2X2TS U5359 ( .A(n3905), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]), .Y(n5397) );
NAND2X1TS U5360 ( .A(n3906), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]), .Y(n5383) );
OAI21X1TS U5361 ( .A0(n5382), .A1(n5397), .B0(n5383), .Y(n5401) );
NAND2X1TS U5362 ( .A(n3907), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[21]), .Y(n5407) );
NAND2X1TS U5363 ( .A(n3908), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[22]), .Y(n5411) );
AOI21X1TS U5364 ( .A0(n5401), .A1(n3910), .B0(n3909), .Y(n3911) );
NAND2X1TS U5365 ( .A(n3914), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .Y(n4980) );
NAND2X1TS U5366 ( .A(n3915), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(n4969) );
NAND2X1TS U5367 ( .A(n3916), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .Y(n4958) );
OAI21X1TS U5368 ( .A0(n4957), .A1(n4969), .B0(n4958), .Y(n3917) );
AOI21X2TS U5369 ( .A0(n4952), .A1(n3918), .B0(n3917), .Y(n4897) );
NAND2X2TS U5370 ( .A(n3919), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .Y(n4940) );
NAND2X1TS U5371 ( .A(n3920), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(n4930) );
OAI21X1TS U5372 ( .A0(n4929), .A1(n4940), .B0(n4930), .Y(n4900) );
NAND2X1TS U5373 ( .A(n3922), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .Y(n4906) );
AOI21X1TS U5374 ( .A0(n4900), .A1(n3924), .B0(n3923), .Y(n3925) );
OAI21X2TS U5375 ( .A0(n3926), .A1(n4897), .B0(n3925), .Y(n3927) );
AOI21X4TS U5376 ( .A0(n3928), .A1(n4896), .B0(n3927), .Y(n4784) );
INVX2TS U5377 ( .A(n3929), .Y(n3930) );
AOI21X4TS U5378 ( .A0(n3932), .A1(n3931), .B0(n3930), .Y(n3940) );
INVX2TS U5379 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[19]), .Y(
n4750) );
INVX2TS U5380 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]), .Y(
n3941) );
CMPR32X2TS U5381 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]),
.B(n4758), .C(n3933), .CO(n3934), .S(n3806) );
INVX2TS U5382 ( .A(n3939), .Y(n3936) );
NAND2X1TS U5383 ( .A(n3935), .B(n3934), .Y(n3938) );
NAND2X1TS U5384 ( .A(n3936), .B(n3938), .Y(n3937) );
XOR2X1TS U5385 ( .A(n3940), .B(n3937), .Y(n3980) );
OAI21X4TS U5386 ( .A0(n3940), .A1(n3939), .B0(n3938), .Y(n3948) );
INVX2TS U5387 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[20]), .Y(
n3998) );
INVX2TS U5388 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]), .Y(
n3949) );
CMPR32X2TS U5389 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]),
.B(n4750), .C(n3941), .CO(n3942), .S(n3935) );
NAND2X1TS U5390 ( .A(n3943), .B(n3942), .Y(n3945) );
NAND2X1TS U5391 ( .A(n3947), .B(n3945), .Y(n3944) );
XNOR2X1TS U5392 ( .A(n3948), .B(n3944), .Y(n3981) );
NOR2X2TS U5393 ( .A(n3981), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .Y(n4873) );
NOR2X2TS U5394 ( .A(n4871), .B(n4873), .Y(n4845) );
INVX2TS U5395 ( .A(n3945), .Y(n3946) );
AOI21X4TS U5396 ( .A0(n3948), .A1(n3947), .B0(n3946), .Y(n3956) );
INVX2TS U5397 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[21]), .Y(
n4732) );
INVX2TS U5398 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[21]), .Y(
n3957) );
CMPR32X2TS U5399 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]),
.B(n3998), .C(n3949), .CO(n3950), .S(n3943) );
NOR2X1TS U5400 ( .A(n3951), .B(n3950), .Y(n3955) );
INVX2TS U5401 ( .A(n3955), .Y(n3952) );
NAND2X1TS U5402 ( .A(n3951), .B(n3950), .Y(n3954) );
NAND2X1TS U5403 ( .A(n3952), .B(n3954), .Y(n3953) );
NOR2X2TS U5404 ( .A(n3982), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .Y(n4859) );
OAI21X4TS U5405 ( .A0(n3956), .A1(n3955), .B0(n3954), .Y(n3964) );
INVX2TS U5406 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[22]), .Y(
n3995) );
INVX2TS U5407 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[22]), .Y(
n3965) );
CMPR32X2TS U5408 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]),
.B(n4732), .C(n3957), .CO(n3958), .S(n3951) );
NAND2X1TS U5409 ( .A(n3959), .B(n3958), .Y(n3961) );
NAND2X1TS U5410 ( .A(n3963), .B(n3961), .Y(n3960) );
NOR2X2TS U5411 ( .A(n3983), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .Y(n4846) );
NOR2X2TS U5412 ( .A(n4859), .B(n4846), .Y(n3985) );
NAND2X2TS U5413 ( .A(n4845), .B(n3985), .Y(n4795) );
INVX2TS U5414 ( .A(n3961), .Y(n3962) );
INVX2TS U5415 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[23]), .Y(
n5004) );
CMPR32X2TS U5416 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]),
.B(n3995), .C(n3965), .CO(n3966), .S(n3959) );
NOR2X1TS U5417 ( .A(n3967), .B(n3966), .Y(n3971) );
INVX2TS U5418 ( .A(n3971), .Y(n3968) );
NAND2X1TS U5419 ( .A(n3967), .B(n3966), .Y(n3970) );
NAND2X1TS U5420 ( .A(n3968), .B(n3970), .Y(n3969) );
CLKXOR2X2TS U5421 ( .A(n3972), .B(n3969), .Y(n3986) );
NOR2X2TS U5422 ( .A(n3986), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .Y(n4833) );
CMPR32X2TS U5423 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]),
.B(n5004), .C(DP_OP_453J16_122_8745_n227), .CO(n3973), .S(n3967) );
NAND2X1TS U5424 ( .A(n3973), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]), .Y(n3975) );
NAND2X1TS U5425 ( .A(n3977), .B(n3975), .Y(n3974) );
XNOR2X4TS U5426 ( .A(n3978), .B(n3974), .Y(n3987) );
NOR2X4TS U5427 ( .A(n3987), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .Y(n4821) );
NOR2X4TS U5428 ( .A(n4833), .B(n4821), .Y(n4800) );
INVX2TS U5429 ( .A(n3975), .Y(n3976) );
XOR2X4TS U5430 ( .A(n3979), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]), .Y(n3988) );
NOR2X4TS U5431 ( .A(n3988), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .Y(n4809) );
NOR2X4TS U5432 ( .A(n4809), .B(n4801), .Y(n3990) );
NAND2X4TS U5433 ( .A(n4800), .B(n3990), .Y(n3992) );
NOR2X4TS U5434 ( .A(n4795), .B(n3992), .Y(n4786) );
NAND2X2TS U5435 ( .A(n4786), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .Y(n3994) );
NAND2X1TS U5436 ( .A(n3981), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .Y(n4874) );
NAND2X1TS U5437 ( .A(n3983), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .Y(n4847) );
OAI21X1TS U5438 ( .A0(n4846), .A1(n4860), .B0(n4847), .Y(n3984) );
AOI21X2TS U5439 ( .A0(n4844), .A1(n3985), .B0(n3984), .Y(n4796) );
NAND2X2TS U5440 ( .A(n3986), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .Y(n4834) );
NAND2X2TS U5441 ( .A(n3988), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .Y(n4810) );
AOI21X2TS U5442 ( .A0(n4799), .A1(n3990), .B0(n3989), .Y(n3991) );
OAI21X4TS U5443 ( .A0(n4796), .A1(n3992), .B0(n3991), .Y(n4785) );
OAI21X4TS U5444 ( .A0(n4784), .A1(n3994), .B0(n3993), .Y(n4776) );
NOR2X8TS U5445 ( .A(n4766), .B(n4767), .Y(n4759) );
NAND2X4TS U5446 ( .A(n3999), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[20]), .Y(n4733) );
NAND2X1TS U5447 ( .A(n4727), .B(n2283), .Y(n3996) );
NAND2X2TS U5448 ( .A(n3996), .B(n4725), .Y(n5377) );
BUFX3TS U5449 ( .A(n5377), .Y(n5426) );
XNOR2X1TS U5450 ( .A(n3999), .B(n3998), .Y(n4000) );
BUFX3TS U5451 ( .A(n5377), .Y(n4826) );
NAND2X4TS U5452 ( .A(n2400), .B(n2323), .Y(n5101) );
AND2X4TS U5453 ( .A(n5071), .B(n2400), .Y(n5103) );
AOI211X1TS U5454 ( .A0(n4002), .A1(n2204), .B0(n4001), .C0(n5103), .Y(n4003)
);
BUFX3TS U5455 ( .A(n5018), .Y(n5716) );
MXI2X1TS U5456 ( .A(n4003), .B(n5945), .S0(n5082), .Y(n1205) );
BUFX3TS U5457 ( .A(n4113), .Y(n6061) );
BUFX3TS U5458 ( .A(n4010), .Y(n6060) );
BUFX3TS U5459 ( .A(n4113), .Y(n6063) );
BUFX3TS U5460 ( .A(n4010), .Y(n6064) );
BUFX3TS U5461 ( .A(n4010), .Y(n6065) );
BUFX3TS U5462 ( .A(n4113), .Y(n6062) );
BUFX3TS U5463 ( .A(n4010), .Y(n6066) );
BUFX3TS U5464 ( .A(n4010), .Y(n6067) );
BUFX3TS U5465 ( .A(n4007), .Y(n6025) );
BUFX3TS U5466 ( .A(n6020), .Y(n6026) );
BUFX3TS U5467 ( .A(n6015), .Y(n6008) );
CLKBUFX2TS U5468 ( .A(n2274), .Y(n4009) );
BUFX3TS U5469 ( .A(n5982), .Y(n5976) );
BUFX3TS U5470 ( .A(n6015), .Y(n6027) );
BUFX3TS U5471 ( .A(n4005), .Y(n6028) );
BUFX3TS U5472 ( .A(n4004), .Y(n6029) );
BUFX3TS U5473 ( .A(n5980), .Y(n6006) );
BUFX3TS U5474 ( .A(n4113), .Y(n6053) );
BUFX3TS U5475 ( .A(n4010), .Y(n6054) );
BUFX3TS U5476 ( .A(n4113), .Y(n6055) );
BUFX3TS U5477 ( .A(n6020), .Y(n6022) );
BUFX3TS U5478 ( .A(n4004), .Y(n6023) );
BUFX3TS U5479 ( .A(n6015), .Y(n6042) );
BUFX3TS U5480 ( .A(n6039), .Y(n6043) );
BUFX3TS U5481 ( .A(n5980), .Y(n5968) );
BUFX3TS U5482 ( .A(n6020), .Y(n6046) );
BUFX3TS U5483 ( .A(n6014), .Y(n6047) );
BUFX3TS U5484 ( .A(n6018), .Y(n6049) );
BUFX3TS U5485 ( .A(n6015), .Y(n6050) );
CLKBUFX3TS U5486 ( .A(n6052), .Y(n6051) );
BUFX3TS U5487 ( .A(n6020), .Y(n6031) );
BUFX3TS U5488 ( .A(n6014), .Y(n6032) );
BUFX3TS U5489 ( .A(n6018), .Y(n6033) );
CLKBUFX2TS U5490 ( .A(n5979), .Y(n6007) );
BUFX3TS U5491 ( .A(n6039), .Y(n6009) );
BUFX3TS U5492 ( .A(n6014), .Y(n6010) );
BUFX3TS U5493 ( .A(n6039), .Y(n6011) );
BUFX3TS U5494 ( .A(n6014), .Y(n6012) );
BUFX3TS U5495 ( .A(n6015), .Y(n6013) );
BUFX3TS U5496 ( .A(n5979), .Y(n5972) );
CLKBUFX2TS U5497 ( .A(n4008), .Y(n6037) );
BUFX3TS U5498 ( .A(n6037), .Y(n6016) );
BUFX3TS U5499 ( .A(n4008), .Y(n6017) );
BUFX3TS U5500 ( .A(n6039), .Y(n6019) );
BUFX3TS U5501 ( .A(n6018), .Y(n6045) );
BUFX3TS U5502 ( .A(n5978), .Y(n5970) );
BUFX3TS U5503 ( .A(n4005), .Y(n6040) );
BUFX3TS U5504 ( .A(n4004), .Y(n6041) );
CLKBUFX2TS U5505 ( .A(n4008), .Y(n6038) );
BUFX3TS U5506 ( .A(n5983), .Y(n5971) );
CLKBUFX2TS U5507 ( .A(n2274), .Y(n4012) );
BUFX3TS U5508 ( .A(n2411), .Y(n5974) );
BUFX3TS U5509 ( .A(n4009), .Y(n5973) );
BUFX3TS U5510 ( .A(n5982), .Y(n5975) );
CLKBUFX2TS U5511 ( .A(n2274), .Y(n4011) );
BUFX3TS U5512 ( .A(n5980), .Y(n5977) );
BUFX3TS U5513 ( .A(n4005), .Y(n6034) );
BUFX3TS U5514 ( .A(n4010), .Y(n6058) );
BUFX3TS U5515 ( .A(n5980), .Y(n5987) );
BUFX3TS U5516 ( .A(n4006), .Y(n5981) );
BUFX3TS U5517 ( .A(n2411), .Y(n5993) );
BUFX3TS U5518 ( .A(n5979), .Y(n5988) );
BUFX3TS U5519 ( .A(n5978), .Y(n5984) );
BUFX3TS U5520 ( .A(n5983), .Y(n5985) );
BUFX3TS U5521 ( .A(n5979), .Y(n5998) );
BUFX3TS U5522 ( .A(n4004), .Y(n6021) );
BUFX3TS U5523 ( .A(n4012), .Y(n5967) );
BUFX3TS U5524 ( .A(n6052), .Y(n6044) );
BUFX3TS U5525 ( .A(n6020), .Y(n6036) );
BUFX3TS U5526 ( .A(n5978), .Y(n5996) );
BUFX3TS U5527 ( .A(n6018), .Y(n6030) );
BUFX3TS U5528 ( .A(n5979), .Y(n6004) );
BUFX3TS U5529 ( .A(n2411), .Y(n5994) );
BUFX3TS U5530 ( .A(n5978), .Y(n6005) );
BUFX3TS U5531 ( .A(n4008), .Y(n6024) );
BUFX3TS U5532 ( .A(n5983), .Y(n6001) );
BUFX3TS U5533 ( .A(n2274), .Y(n5969) );
BUFX3TS U5534 ( .A(n2411), .Y(n5992) );
BUFX3TS U5535 ( .A(n6014), .Y(n6035) );
BUFX3TS U5536 ( .A(n4004), .Y(n6048) );
BUFX3TS U5537 ( .A(n4113), .Y(n6068) );
BUFX3TS U5538 ( .A(n4006), .Y(n5986) );
BUFX3TS U5539 ( .A(n4006), .Y(n5999) );
BUFX3TS U5540 ( .A(n5982), .Y(n5989) );
BUFX3TS U5541 ( .A(n5982), .Y(n6000) );
BUFX3TS U5542 ( .A(n5983), .Y(n6003) );
BUFX3TS U5543 ( .A(n4006), .Y(n6002) );
BUFX3TS U5544 ( .A(n2411), .Y(n5990) );
BUFX3TS U5545 ( .A(n4010), .Y(n6056) );
BUFX3TS U5546 ( .A(n5980), .Y(n5997) );
BUFX3TS U5547 ( .A(n2411), .Y(n5995) );
BUFX3TS U5548 ( .A(n2411), .Y(n5991) );
NAND2X1TS U5549 ( .A(n5838), .B(n5945), .Y(n5324) );
NAND2X1TS U5550 ( .A(n5929), .B(FPADDSUB_DMP_SFG[0]), .Y(n4013) );
INVX2TS U5551 ( .A(n4029), .Y(n5314) );
NOR2X1TS U5552 ( .A(n5928), .B(FPADDSUB_DMP_SFG[1]), .Y(n4023) );
NAND2X1TS U5553 ( .A(n5928), .B(FPADDSUB_DMP_SFG[1]), .Y(n4025) );
INVX2TS U5554 ( .A(n4045), .Y(n4015) );
NAND2X1TS U5555 ( .A(n4015), .B(n4044), .Y(n4019) );
INVX2TS U5556 ( .A(n4019), .Y(n4016) );
XNOR2X1TS U5557 ( .A(n4017), .B(n4016), .Y(n4022) );
XOR2X1TS U5558 ( .A(n4046), .B(n4019), .Y(n4020) );
BUFX3TS U5559 ( .A(n4049), .Y(n5354) );
AOI22X1TS U5560 ( .A0(n4020), .A1(n5354), .B0(FPADDSUB_Raw_mant_NRM_SWR[4]),
.B1(n5353), .Y(n4021) );
OAI2BB1X1TS U5561 ( .A0N(n5253), .A1N(n4022), .B0(n4021), .Y(n1345) );
NOR2X1TS U5562 ( .A(n5917), .B(FPADDSUB_DMP_SFG[2]), .Y(n4026) );
NAND2X1TS U5563 ( .A(n5917), .B(FPADDSUB_DMP_SFG[2]), .Y(n4024) );
AOI21X1TS U5564 ( .A0(n4029), .A1(n4028), .B0(n4027), .Y(n5128) );
INVX2TS U5565 ( .A(n5128), .Y(n4057) );
NOR2X1TS U5566 ( .A(n5927), .B(FPADDSUB_DMP_SFG[3]), .Y(n4053) );
INVX2TS U5567 ( .A(n4053), .Y(n4031) );
NAND2X1TS U5568 ( .A(n5927), .B(FPADDSUB_DMP_SFG[3]), .Y(n4055) );
INVX2TS U5569 ( .A(n4055), .Y(n4030) );
AOI21X1TS U5570 ( .A0(n4057), .A1(n4031), .B0(n4030), .Y(n4034) );
INVX2TS U5571 ( .A(n4032), .Y(n4064) );
NAND2X1TS U5572 ( .A(n4064), .B(n4062), .Y(n4036) );
INVX2TS U5573 ( .A(n4036), .Y(n4033) );
XNOR2X1TS U5574 ( .A(n4077), .B(n4036), .Y(n4037) );
AOI22X1TS U5575 ( .A0(n4037), .A1(n5354), .B0(FPADDSUB_Raw_mant_NRM_SWR[6]),
.B1(n5353), .Y(n4038) );
OAI2BB1X1TS U5576 ( .A0N(n5253), .A1N(n4039), .B0(n4038), .Y(n1343) );
INVX2TS U5577 ( .A(n4040), .Y(n4042) );
NAND2X1TS U5578 ( .A(n4042), .B(n4041), .Y(n4047) );
INVX2TS U5579 ( .A(n4047), .Y(n4043) );
XNOR2X1TS U5580 ( .A(n4057), .B(n4043), .Y(n4052) );
XNOR2X1TS U5581 ( .A(n4048), .B(n4047), .Y(n4050) );
BUFX3TS U5582 ( .A(n4049), .Y(n5295) );
AOI22X1TS U5583 ( .A0(n4050), .A1(n5295), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.B1(n5353), .Y(n4051) );
OAI2BB1X1TS U5584 ( .A0N(n5253), .A1N(n4052), .B0(n4051), .Y(n1344) );
NOR2X1TS U5585 ( .A(n5916), .B(FPADDSUB_DMP_SFG[4]), .Y(n4056) );
NOR2X1TS U5586 ( .A(n4053), .B(n4056), .Y(n5119) );
NAND2X1TS U5587 ( .A(n5916), .B(FPADDSUB_DMP_SFG[4]), .Y(n4054) );
OAI21X1TS U5588 ( .A0(n4056), .A1(n4055), .B0(n4054), .Y(n5125) );
AOI21X1TS U5589 ( .A0(n4057), .A1(n5119), .B0(n5125), .Y(n4071) );
INVX2TS U5590 ( .A(n4058), .Y(n4060) );
NAND2X1TS U5591 ( .A(n4060), .B(n4059), .Y(n4065) );
INVX2TS U5592 ( .A(n4065), .Y(n4061) );
INVX2TS U5593 ( .A(n4062), .Y(n4063) );
AOI21X1TS U5594 ( .A0(n4077), .A1(n4064), .B0(n4063), .Y(n4066) );
XOR2X1TS U5595 ( .A(n4066), .B(n4065), .Y(n4067) );
AOI22X1TS U5596 ( .A0(n4067), .A1(n5354), .B0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.B1(n5353), .Y(n4068) );
OAI2BB1X1TS U5597 ( .A0N(n5253), .A1N(n4069), .B0(n4068), .Y(n1342) );
INVX2TS U5598 ( .A(n2283), .Y(n4700) );
NOR2X1TS U5599 ( .A(n4700), .B(n5858), .Y(n5116) );
NAND2X1TS U5600 ( .A(n4713), .B(n5116), .Y(n5690) );
INVX2TS U5601 ( .A(n5690), .Y(n5112) );
NOR2X1TS U5602 ( .A(n5926), .B(FPADDSUB_DMP_SFG[5]), .Y(n5118) );
NAND2X1TS U5603 ( .A(n5926), .B(FPADDSUB_DMP_SFG[5]), .Y(n5121) );
INVX2TS U5604 ( .A(n5349), .Y(n4072) );
NAND2X1TS U5605 ( .A(n4072), .B(n5348), .Y(n4078) );
INVX2TS U5606 ( .A(n4078), .Y(n4073) );
XNOR2X1TS U5607 ( .A(n4074), .B(n4073), .Y(n4081) );
AOI21X1TS U5608 ( .A0(n4077), .A1(n4076), .B0(n4075), .Y(n5350) );
XOR2X1TS U5609 ( .A(n5350), .B(n4078), .Y(n4079) );
AOI22X1TS U5610 ( .A0(n4079), .A1(n5354), .B0(FPADDSUB_Raw_mant_NRM_SWR[8]),
.B1(n5353), .Y(n4080) );
OAI2BB1X1TS U5611 ( .A0N(n5253), .A1N(n4081), .B0(n4080), .Y(n1341) );
CLKBUFX2TS U5612 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n5806) );
NAND2X1TS U5613 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n5869), .Y(n5712) );
INVX2TS U5614 ( .A(n5712), .Y(n4082) );
NOR2X1TS U5615 ( .A(n2268), .B(FPADDSUB_DMP_EXP_EWSW[24]), .Y(n5709) );
OAI22X1TS U5616 ( .A0(n4082), .A1(n5709), .B0(FPADDSUB_DmP_EXP_EWSW[24]),
.B1(n5833), .Y(n4085) );
NAND2X1TS U5617 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n2460), .Y(n4086) );
XNOR2X1TS U5618 ( .A(n4085), .B(n4083), .Y(n4084) );
INVX2TS U5619 ( .A(n5719), .Y(n5717) );
NOR2X1TS U5620 ( .A(n2463), .B(FPADDSUB_DMP_EXP_EWSW[26]), .Y(n5705) );
AOI22X1TS U5621 ( .A0(FPADDSUB_DMP_EXP_EWSW[25]), .A1(n5836), .B0(n4086),
.B1(n4085), .Y(n5707) );
OAI22X1TS U5622 ( .A0(n5705), .A1(n5707), .B0(FPADDSUB_DmP_EXP_EWSW[26]),
.B1(n5835), .Y(n4088) );
XNOR2X1TS U5623 ( .A(FPADDSUB_DmP_EXP_EWSW[27]), .B(
FPADDSUB_DMP_EXP_EWSW[27]), .Y(n4087) );
XOR2X1TS U5624 ( .A(n4088), .B(n4087), .Y(n4089) );
OAI33X4TS U5625 ( .A0(n5826), .A1(n2250), .A2(n5871), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n5479) );
BUFX3TS U5626 ( .A(n5807), .Y(n5811) );
OAI2BB2XLTS U5627 ( .B0(n5479), .B1(n5811), .A0N(n5479), .A1N(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2145) );
BUFX3TS U5628 ( .A(n5525), .Y(n5656) );
INVX2TS U5629 ( .A(n5525), .Y(n5655) );
BUFX3TS U5630 ( .A(n5525), .Y(n5583) );
BUFX3TS U5631 ( .A(n5525), .Y(n5577) );
OR2X1TS U5632 ( .A(FPSENCOS_d_ff3_LUT_out[27]), .B(n5577), .Y(n2113) );
NOR3XLTS U5633 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n5859),
.C(n4189), .Y(n4090) );
NAND2X1TS U5634 ( .A(n5821), .B(n2302), .Y(n4226) );
AOI22X1TS U5635 ( .A0(n5579), .A1(n4124), .B0(FPSENCOS_d_ff3_LUT_out[7]),
.B1(n5452), .Y(n4092) );
NOR2X2TS U5636 ( .A(n5501), .B(n5844), .Y(n5490) );
NAND2X1TS U5637 ( .A(n5490), .B(n4137), .Y(n5496) );
NAND2X1TS U5638 ( .A(n4092), .B(n5496), .Y(n2126) );
AOI22X1TS U5639 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n5501), .B0(n5487),
.B1(n4124), .Y(n4093) );
BUFX3TS U5640 ( .A(n5525), .Y(n5548) );
INVX2TS U5641 ( .A(n5548), .Y(n5581) );
AO21X1TS U5642 ( .A0(n5494), .A1(n4226), .B0(n5581), .Y(n4153) );
NAND2X1TS U5643 ( .A(n4093), .B(n4153), .Y(n2132) );
OAI22X1TS U5644 ( .A0(n5830), .A1(n5036), .B0(n5868), .B1(n4094), .Y(n4095)
);
AOI22X1TS U5645 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n3673), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n2385), .Y(n4097) );
AOI22X1TS U5646 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2352), .B0(
FPADDSUB_Data_array_SWR[1]), .B1(n2382), .Y(n4096) );
OAI211X1TS U5647 ( .A0(n5083), .A1(n2322), .B0(n4097), .C0(n4096), .Y(n5022)
);
AOI211X1TS U5648 ( .A0(n5022), .A1(n2447), .B0(n4098), .C0(n5103), .Y(n4099)
);
MXI2X1TS U5649 ( .A(n4099), .B(n5838), .S0(n5082), .Y(n1204) );
NOR2X1TS U5650 ( .A(FPMULT_FSM_selector_B[1]), .B(n5843), .Y(n4100) );
INVX2TS U5651 ( .A(n4100), .Y(n4707) );
XOR2X1TS U5652 ( .A(n2418), .B(n4102), .Y(DP_OP_234J16_127_8543_n22) );
NOR3BX1TS U5653 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n4103) );
XOR2X1TS U5654 ( .A(n2419), .B(n4103), .Y(DP_OP_234J16_127_8543_n15) );
INVX2TS U5655 ( .A(n5465), .Y(n4123) );
AO22X4TS U5656 ( .A0(operation[1]), .A1(n4105), .B0(begin_operation), .B1(
n4104), .Y(n4121) );
NOR2X4TS U5657 ( .A(n5454), .B(n4321), .Y(n4107) );
BUFX3TS U5658 ( .A(n4106), .Y(n5661) );
BUFX3TS U5659 ( .A(n4321), .Y(n5660) );
AOI22X1TS U5660 ( .A0(FPSENCOS_d_ff3_sh_x_out[30]), .A1(n5661), .B0(
FPADDSUB_intDY_EWSW[30]), .B1(n5660), .Y(n4111) );
NOR2X2TS U5661 ( .A(operation[1]), .B(n4444), .Y(n4109) );
AOI22X1TS U5662 ( .A0(n4322), .A1(FPSENCOS_d_ff3_sh_y_out[30]), .B0(n4109),
.B1(Data_2[30]), .Y(n4110) );
NAND2X1TS U5663 ( .A(n4111), .B(n4110), .Y(n1813) );
BUFX3TS U5664 ( .A(n2274), .Y(n5980) );
BUFX3TS U5665 ( .A(n2274), .Y(n5979) );
BUFX3TS U5666 ( .A(n2274), .Y(n5978) );
BUFX3TS U5667 ( .A(n4112), .Y(n6020) );
BUFX3TS U5668 ( .A(n4112), .Y(n6014) );
BUFX3TS U5669 ( .A(n4112), .Y(n6015) );
BUFX3TS U5670 ( .A(n4112), .Y(n6018) );
BUFX3TS U5671 ( .A(n2274), .Y(n5982) );
BUFX3TS U5672 ( .A(n2274), .Y(n5983) );
BUFX3TS U5673 ( .A(n4113), .Y(n6059) );
BUFX3TS U5674 ( .A(n4113), .Y(n6057) );
NOR2X2TS U5675 ( .A(n5858), .B(n2283), .Y(n5009) );
NAND2X1TS U5676 ( .A(n4977), .B(FPMULT_Add_result[0]), .Y(n4114) );
NAND2X1TS U5677 ( .A(FPMULT_FS_Module_state_reg[2]), .B(n5841), .Y(n5007) );
OAI31X1TS U5678 ( .A0(n4782), .A1(n5112), .A2(n5822), .B0(n4116), .Y(n1622)
);
NAND2X1TS U5679 ( .A(n2285), .B(n2252), .Y(intadd_21_CI) );
AOI22X1TS U5680 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n4119), .B0(
FPSENCOS_d_ff3_sh_y_out[23]), .B1(n5452), .Y(n4117) );
AOI22X1TS U5681 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n4119), .B0(
FPSENCOS_d_ff3_sh_x_out[23]), .B1(n5452), .Y(n4118) );
INVX2TS U5682 ( .A(n4119), .Y(n5503) );
AOI32X1TS U5683 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n5579), .A2(n4137),
.B0(FPSENCOS_d_ff3_LUT_out[23]), .B1(n5501), .Y(n4120) );
AOI22X1TS U5684 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n5826), .B0(n4121), .B1(n2250), .Y(n4122) );
NAND2X1TS U5685 ( .A(n5490), .B(n4124), .Y(n5493) );
NAND2X1TS U5686 ( .A(n5487), .B(n4137), .Y(n4154) );
INVX2TS U5687 ( .A(n5962), .Y(busy) );
NOR2X2TS U5688 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n4481) );
INVX2TS U5689 ( .A(n4481), .Y(n4125) );
NOR2X4TS U5690 ( .A(n4125), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(n4143) );
NOR2X2TS U5691 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n4485) );
AND2X4TS U5692 ( .A(n4485), .B(n4482), .Y(n4130) );
NOR2BX4TS U5693 ( .AN(n4143), .B(n4469), .Y(n4140) );
OAI22X1TS U5694 ( .A0(n4144), .A1(FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n5857),
.B1(n4471), .Y(n4488) );
NOR3BX4TS U5695 ( .AN(n4476), .B(FPADDSUB_Raw_mant_NRM_SWR[12]), .C(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n4165) );
NAND2X1TS U5696 ( .A(n5842), .B(n6076), .Y(n4164) );
NOR2BX4TS U5697 ( .AN(n4165), .B(n4164), .Y(n4161) );
NAND2X4TS U5698 ( .A(n4475), .B(n5840), .Y(n4131) );
AOI21X1TS U5699 ( .A0(n5903), .A1(n5837), .B0(n4128), .Y(n4141) );
NOR2BX1TS U5700 ( .AN(n4130), .B(n4129), .Y(n4133) );
NAND3X4TS U5701 ( .A(n4169), .B(n5820), .C(n5848), .Y(n4166) );
OAI22X1TS U5702 ( .A0(n5820), .A1(n4131), .B0(n4166), .B1(n2216), .Y(n4132)
);
BUFX3TS U5703 ( .A(n4600), .Y(n5480) );
BUFX3TS U5704 ( .A(n4600), .Y(n4616) );
NAND2X1TS U5705 ( .A(n2299), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n4135)
);
AOI22X1TS U5706 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n5501), .B0(n5487),
.B1(n4138), .Y(n4139) );
NAND2X1TS U5707 ( .A(n4140), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n4490) );
INVX2TS U5708 ( .A(n4141), .Y(n4142) );
OAI211XLTS U5709 ( .A0(n4143), .A1(n4469), .B0(n4490), .C0(n4142), .Y(n4147)
);
OAI31X1TS U5710 ( .A0(n4166), .A1(n4145), .A2(n2251), .B0(n4144), .Y(n4146)
);
AOI211X1TS U5711 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n4148), .B0(n4147), .C0(n4146), .Y(n4151) );
BUFX3TS U5712 ( .A(n4600), .Y(n5478) );
NAND2X1TS U5713 ( .A(n2299), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n4150)
);
INVX2TS U5714 ( .A(n5490), .Y(n5498) );
AOI21X1TS U5715 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n5502), .B0(
FPSENCOS_cont_iter_out[3]), .Y(n4155) );
AOI22X1TS U5716 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n5501), .B0(n5487),
.B1(n4155), .Y(n4152) );
INVX2TS U5717 ( .A(n5487), .Y(n5505) );
AOI22X1TS U5718 ( .A0(n5579), .A1(n4155), .B0(FPSENCOS_d_ff3_LUT_out[26]),
.B1(n5452), .Y(n4156) );
BUFX3TS U5719 ( .A(n4157), .Y(n4186) );
BUFX3TS U5720 ( .A(n4186), .Y(n5469) );
NAND2X1TS U5721 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[3]), .Y(n4696) );
NOR3X1TS U5722 ( .A(n2283), .B(FPMULT_FS_Module_state_reg[0]), .C(n4696),
.Y(n5472) );
OAI2BB1X1TS U5723 ( .A0N(ack_operation), .A1N(n4157), .B0(n5472), .Y(n4158)
);
AOI32X1TS U5724 ( .A0(n2283), .A1(n5819), .A2(FPMULT_FS_Module_state_reg[0]),
.B0(FPMULT_FS_Module_state_reg[2]), .B1(n5010), .Y(n4160) );
OAI21X4TS U5725 ( .A0(n4163), .A1(n4166), .B0(n4162), .Y(n4487) );
AOI22X1TS U5726 ( .A0(n4475), .A1(FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n4165),
.B1(n4164), .Y(n4167) );
INVX1TS U5727 ( .A(FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n5309) );
AOI32X1TS U5728 ( .A0(n2251), .A1(n4167), .A2(n5309), .B0(n4166), .B1(n4167),
.Y(n4168) );
AOI211X1TS U5729 ( .A0(n4169), .A1(FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n4487),
.C0(n4168), .Y(n4172) );
NAND2X1TS U5730 ( .A(n2299), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n4171)
);
NAND2X1TS U5731 ( .A(n4695), .B(n5007), .Y(n4173) );
INVX2TS U5732 ( .A(n4735), .Y(n4865) );
NAND2X1TS U5733 ( .A(n5502), .B(n5484), .Y(n4175) );
INVX2TS U5734 ( .A(n4104), .Y(n4200) );
BUFX3TS U5735 ( .A(n4176), .Y(n4203) );
AOI22X1TS U5736 ( .A0(n4203), .A1(cordic_result[19]), .B0(n4157), .B1(
mult_result[19]), .Y(n4177) );
INVX2TS U5737 ( .A(n4104), .Y(n4214) );
AOI22X1TS U5738 ( .A0(n4203), .A1(cordic_result[15]), .B0(n4157), .B1(
mult_result[15]), .Y(n4178) );
AOI22X1TS U5739 ( .A0(cordic_result[14]), .A1(n4203), .B0(n4157), .B1(
mult_result[14]), .Y(n4179) );
AOI22X1TS U5740 ( .A0(cordic_result[17]), .A1(n4203), .B0(n4157), .B1(
mult_result[17]), .Y(n4180) );
AOI22X1TS U5741 ( .A0(n4203), .A1(cordic_result[16]), .B0(n4157), .B1(
mult_result[16]), .Y(n4181) );
AOI22X1TS U5742 ( .A0(n4203), .A1(cordic_result[18]), .B0(n4157), .B1(
mult_result[18]), .Y(n4182) );
AOI22X1TS U5743 ( .A0(n4203), .A1(cordic_result[13]), .B0(n4157), .B1(
mult_result[13]), .Y(n4183) );
AOI22X1TS U5744 ( .A0(n4203), .A1(cordic_result[21]), .B0(n4186), .B1(
mult_result[21]), .Y(n4184) );
BUFX3TS U5745 ( .A(n4176), .Y(n5470) );
AOI22X1TS U5746 ( .A0(n5470), .A1(cordic_result[22]), .B0(n4186), .B1(
mult_result[22]), .Y(n4185) );
AOI22X1TS U5747 ( .A0(cordic_result[20]), .A1(n4203), .B0(n4186), .B1(
mult_result[20]), .Y(n4187) );
OAI31X1TS U5748 ( .A0(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .A1(n5859),
.A2(n4189), .B0(n5457), .Y(n4190) );
INVX2TS U5749 ( .A(n5513), .Y(n5512) );
AOI32X1TS U5750 ( .A0(n5512), .A1(operation[0]), .A2(operation[1]), .B0(
FPSENCOS_d_ff1_operation_out), .B1(n5507), .Y(n4191) );
INVX2TS U5751 ( .A(n4191), .Y(n2080) );
INVX2TS U5752 ( .A(n4104), .Y(n4209) );
BUFX3TS U5753 ( .A(n4157), .Y(n5473) );
AOI22X1TS U5754 ( .A0(n4176), .A1(cordic_result[0]), .B0(n5473), .B1(
mult_result[0]), .Y(n4192) );
BUFX3TS U5755 ( .A(n4176), .Y(n4212) );
AOI22X1TS U5756 ( .A0(n4212), .A1(cordic_result[2]), .B0(n5473), .B1(
mult_result[2]), .Y(n4193) );
AOI22X1TS U5757 ( .A0(n4176), .A1(cordic_result[1]), .B0(n5473), .B1(
mult_result[1]), .Y(n4194) );
INVX1TS U5758 ( .A(result_add_subt[26]), .Y(n5646) );
AOI22X1TS U5759 ( .A0(cordic_result[26]), .A1(n5470), .B0(n5469), .B1(
mult_result[26]), .Y(n4195) );
INVX1TS U5760 ( .A(result_add_subt[28]), .Y(n5652) );
AOI22X1TS U5761 ( .A0(n5470), .A1(cordic_result[28]), .B0(n5469), .B1(
mult_result[28]), .Y(n4196) );
INVX1TS U5762 ( .A(result_add_subt[27]), .Y(n5648) );
AOI22X1TS U5763 ( .A0(cordic_result[27]), .A1(n5470), .B0(n5469), .B1(
mult_result[27]), .Y(n4197) );
INVX1TS U5764 ( .A(result_add_subt[24]), .Y(n5642) );
AOI22X1TS U5765 ( .A0(cordic_result[24]), .A1(n5470), .B0(n5469), .B1(
mult_result[24]), .Y(n4198) );
INVX2TS U5766 ( .A(result_add_subt[31]), .Y(n5666) );
AOI22X1TS U5767 ( .A0(cordic_result[31]), .A1(n5470), .B0(n5469), .B1(
mult_result[31]), .Y(n4199) );
AOI22X1TS U5768 ( .A0(n4212), .A1(cordic_result[5]), .B0(n5473), .B1(
mult_result[5]), .Y(n4201) );
AOI22X1TS U5769 ( .A0(n4212), .A1(cordic_result[8]), .B0(n5473), .B1(
mult_result[8]), .Y(n4202) );
AOI22X1TS U5770 ( .A0(n4203), .A1(cordic_result[12]), .B0(n5473), .B1(
mult_result[12]), .Y(n4204) );
AOI22X1TS U5771 ( .A0(n4212), .A1(cordic_result[4]), .B0(n5473), .B1(
mult_result[4]), .Y(n4205) );
AOI22X1TS U5772 ( .A0(n4212), .A1(cordic_result[6]), .B0(n5473), .B1(
mult_result[6]), .Y(n4206) );
AOI22X1TS U5773 ( .A0(n4212), .A1(cordic_result[3]), .B0(n5473), .B1(
mult_result[3]), .Y(n4207) );
AOI22X1TS U5774 ( .A0(n4212), .A1(cordic_result[7]), .B0(n4186), .B1(
mult_result[7]), .Y(n4208) );
AOI22X1TS U5775 ( .A0(cordic_result[10]), .A1(n4212), .B0(n4186), .B1(
mult_result[10]), .Y(n4210) );
AOI22X1TS U5776 ( .A0(n4212), .A1(cordic_result[11]), .B0(n4186), .B1(
mult_result[11]), .Y(n4211) );
AOI22X1TS U5777 ( .A0(n4212), .A1(cordic_result[9]), .B0(n4186), .B1(
mult_result[9]), .Y(n4213) );
BUFX3TS U5778 ( .A(n5556), .Y(n4271) );
NOR2X4TS U5779 ( .A(n5527), .B(n4216), .Y(n4233) );
CLKBUFX2TS U5780 ( .A(n4233), .Y(n4246) );
INVX2TS U5781 ( .A(n4217), .Y(n1746) );
INVX2TS U5782 ( .A(n4218), .Y(n1745) );
INVX2TS U5783 ( .A(n4219), .Y(n1750) );
INVX2TS U5784 ( .A(n4220), .Y(n1747) );
INVX2TS U5785 ( .A(n4221), .Y(n1748) );
INVX2TS U5786 ( .A(n4222), .Y(n1751) );
INVX2TS U5787 ( .A(n4223), .Y(n1752) );
INVX2TS U5788 ( .A(n4224), .Y(n1749) );
INVX2TS U5789 ( .A(n5526), .Y(n5588) );
NOR3X1TS U5790 ( .A(n2302), .B(n2208), .C(n5498), .Y(n4228) );
AOI21X1TS U5791 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n5588), .B0(n4228),
.Y(n4225) );
AOI211X1TS U5792 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n5821), .B0(n5502),
.C0(n5505), .Y(n5492) );
AOI21X1TS U5793 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n5588), .B0(n5492),
.Y(n4227) );
INVX2TS U5794 ( .A(n4231), .Y(n1753) );
INVX2TS U5795 ( .A(n4232), .Y(n1754) );
INVX2TS U5796 ( .A(n4234), .Y(n1733) );
INVX2TS U5797 ( .A(n4235), .Y(n1734) );
XOR2X1TS U5798 ( .A(n4242), .B(n5665), .Y(n4245) );
INVX2TS U5799 ( .A(n4236), .Y(n5475) );
XOR2X1TS U5800 ( .A(n5832), .B(FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(
n4238) );
XOR2X1TS U5801 ( .A(n5486), .B(n4238), .Y(n4241) );
NOR2X2TS U5802 ( .A(n4311), .B(n4241), .Y(n4239) );
INVX2TS U5803 ( .A(n4239), .Y(n4275) );
BUFX3TS U5804 ( .A(n4289), .Y(n4310) );
XNOR2X1TS U5805 ( .A(n5585), .B(n4242), .Y(n4243) );
AOI22X1TS U5806 ( .A0(n4311), .A1(cordic_result[31]), .B0(n4310), .B1(n4243),
.Y(n4244) );
INVX2TS U5807 ( .A(n5569), .Y(n5537) );
BUFX3TS U5808 ( .A(n4246), .Y(n4257) );
BUFX3TS U5809 ( .A(n4267), .Y(n5570) );
INVX2TS U5810 ( .A(n4247), .Y(n1764) );
INVX2TS U5811 ( .A(n4248), .Y(n1763) );
INVX2TS U5812 ( .A(n4249), .Y(n1760) );
INVX2TS U5813 ( .A(n4250), .Y(n1756) );
INVX2TS U5814 ( .A(n4251), .Y(n1757) );
INVX2TS U5815 ( .A(n4252), .Y(n1755) );
INVX2TS U5816 ( .A(n4253), .Y(n1759) );
INVX2TS U5817 ( .A(n4254), .Y(n1762) );
INVX2TS U5818 ( .A(n4256), .Y(n1758) );
INVX2TS U5819 ( .A(n4258), .Y(n1761) );
AOI2BB2XLTS U5820 ( .B0(FPSENCOS_d_ff3_sign_out), .B1(n5856), .A0N(n5856),
.A1N(FPSENCOS_d_ff3_sign_out), .Y(n4260) );
BUFX3TS U5821 ( .A(n4387), .Y(n5634) );
AOI22X1TS U5822 ( .A0(operation[0]), .A1(n5634), .B0(FPADDSUB_intAS), .B1(
n5660), .Y(n4259) );
CLKBUFX2TS U5823 ( .A(n5556), .Y(n5523) );
INVX2TS U5824 ( .A(n4262), .Y(n1742) );
INVX2TS U5825 ( .A(n4263), .Y(n1738) );
INVX2TS U5826 ( .A(n4264), .Y(n1739) );
INVX2TS U5827 ( .A(n4265), .Y(n1740) );
INVX2TS U5828 ( .A(n4266), .Y(n1737) );
INVX2TS U5829 ( .A(n4268), .Y(n1735) );
INVX2TS U5830 ( .A(n4269), .Y(n1741) );
INVX2TS U5831 ( .A(n4270), .Y(n1743) );
INVX2TS U5832 ( .A(n4273), .Y(n1744) );
INVX2TS U5833 ( .A(n4274), .Y(n1736) );
INVX2TS U5834 ( .A(n4275), .Y(n4276) );
INVX2TS U5835 ( .A(n4277), .Y(n1696) );
BUFX3TS U5836 ( .A(n4240), .Y(n4297) );
BUFX3TS U5837 ( .A(n4289), .Y(n4302) );
INVX2TS U5838 ( .A(n4278), .Y(n1705) );
INVX2TS U5839 ( .A(n4279), .Y(n1707) );
INVX2TS U5840 ( .A(n4280), .Y(n1726) );
INVX2TS U5841 ( .A(n4281), .Y(n1710) );
BUFX3TS U5842 ( .A(n4289), .Y(n4314) );
INVX2TS U5843 ( .A(n4282), .Y(n1722) );
INVX2TS U5844 ( .A(n4283), .Y(n1711) );
INVX2TS U5845 ( .A(n4284), .Y(n1709) );
INVX2TS U5846 ( .A(n4285), .Y(n1720) );
INVX2TS U5847 ( .A(n4286), .Y(n1719) );
INVX2TS U5848 ( .A(n4287), .Y(n1708) );
INVX2TS U5849 ( .A(n4288), .Y(n1713) );
INVX2TS U5850 ( .A(n4290), .Y(n1725) );
INVX2TS U5851 ( .A(n4291), .Y(n1712) );
INVX2TS U5852 ( .A(n4292), .Y(n1718) );
INVX2TS U5853 ( .A(n4293), .Y(n1715) );
INVX2TS U5854 ( .A(n4294), .Y(n1717) );
INVX2TS U5855 ( .A(n4295), .Y(n1698) );
INVX2TS U5856 ( .A(n4296), .Y(n1703) );
INVX2TS U5857 ( .A(n4298), .Y(n1706) );
INVX2TS U5858 ( .A(n4299), .Y(n1716) );
INVX2TS U5859 ( .A(n4300), .Y(n1701) );
INVX2TS U5860 ( .A(n4301), .Y(n1723) );
INVX2TS U5861 ( .A(n4303), .Y(n1714) );
INVX2TS U5862 ( .A(n4304), .Y(n1699) );
INVX2TS U5863 ( .A(n4305), .Y(n1721) );
INVX2TS U5864 ( .A(n4306), .Y(n1697) );
INVX2TS U5865 ( .A(n4307), .Y(n1704) );
INVX2TS U5866 ( .A(n4308), .Y(n1702) );
INVX2TS U5867 ( .A(n4312), .Y(n1700) );
INVX2TS U5868 ( .A(n4316), .Y(n1724) );
INVX2TS U5869 ( .A(FPSENCOS_d_ff2_Y[11]), .Y(n5553) );
BUFX3TS U5870 ( .A(n4387), .Y(n4437) );
BUFX3TS U5871 ( .A(n4444), .Y(n4436) );
AOI22X1TS U5872 ( .A0(Data_1[11]), .A1(n4437), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n4436), .Y(n4320) );
BUFX3TS U5873 ( .A(n4322), .Y(n4351) );
BUFX3TS U5874 ( .A(n4318), .Y(n4433) );
AOI22X1TS U5875 ( .A0(n4351), .A1(FPSENCOS_d_ff2_X[11]), .B0(n4433), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n4319) );
INVX2TS U5876 ( .A(FPSENCOS_d_ff2_Y[22]), .Y(n5568) );
BUFX3TS U5877 ( .A(n4387), .Y(n4358) );
BUFX3TS U5878 ( .A(n4321), .Y(n4357) );
AOI22X1TS U5879 ( .A0(Data_1[22]), .A1(n4358), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n4357), .Y(n4324) );
BUFX3TS U5880 ( .A(n4322), .Y(n4364) );
BUFX3TS U5881 ( .A(n4318), .Y(n4359) );
AOI22X1TS U5882 ( .A0(n4364), .A1(FPSENCOS_d_ff2_X[22]), .B0(n4359), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n4323) );
AOI22X1TS U5883 ( .A0(Data_1[18]), .A1(n4358), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n4357), .Y(n4326) );
AOI22X1TS U5884 ( .A0(n4351), .A1(FPSENCOS_d_ff2_X[18]), .B0(n4359), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n4325) );
INVX2TS U5885 ( .A(FPSENCOS_d_ff2_Y[19]), .Y(n5565) );
AOI22X1TS U5886 ( .A0(Data_1[19]), .A1(n4358), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n4357), .Y(n4328) );
AOI22X1TS U5887 ( .A0(n4351), .A1(FPSENCOS_d_ff2_X[19]), .B0(n4359), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n4327) );
AOI22X1TS U5888 ( .A0(Data_1[17]), .A1(n4358), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n4357), .Y(n4330) );
AOI22X1TS U5889 ( .A0(n4351), .A1(FPSENCOS_d_ff2_X[17]), .B0(n4359), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n4329) );
INVX2TS U5890 ( .A(FPSENCOS_d_ff2_Y[13]), .Y(n5557) );
AOI22X1TS U5891 ( .A0(Data_1[13]), .A1(n4437), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n4436), .Y(n4332) );
AOI22X1TS U5892 ( .A0(n4351), .A1(FPSENCOS_d_ff2_X[13]), .B0(n4433), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n4331) );
INVX2TS U5893 ( .A(FPSENCOS_d_ff2_Y[16]), .Y(n5560) );
AOI22X1TS U5894 ( .A0(Data_1[16]), .A1(n4358), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n4357), .Y(n4334) );
AOI22X1TS U5895 ( .A0(n4351), .A1(FPSENCOS_d_ff2_X[16]), .B0(n4433), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n4333) );
AOI22X1TS U5896 ( .A0(Data_1[21]), .A1(n4358), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n4357), .Y(n4336) );
AOI22X1TS U5897 ( .A0(n4364), .A1(FPSENCOS_d_ff2_X[21]), .B0(n4359), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n4335) );
AOI22X1TS U5898 ( .A0(Data_1[10]), .A1(n4437), .B0(FPADDSUB_intDX_EWSW[10]),
.B1(n4436), .Y(n4338) );
AOI22X1TS U5899 ( .A0(n4351), .A1(FPSENCOS_d_ff2_X[10]), .B0(n4433), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n4337) );
AOI22X1TS U5900 ( .A0(Data_1[24]), .A1(n4358), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n4357), .Y(n4340) );
AOI22X1TS U5901 ( .A0(n4364), .A1(FPSENCOS_d_ff2_X[24]), .B0(n4359), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n4339) );
BUFX3TS U5902 ( .A(n4387), .Y(n5608) );
BUFX3TS U5903 ( .A(n4444), .Y(n4418) );
AOI22X1TS U5904 ( .A0(Data_1[26]), .A1(n5608), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n4418), .Y(n4342) );
BUFX3TS U5905 ( .A(n4318), .Y(n4419) );
AOI22X1TS U5906 ( .A0(n4364), .A1(FPSENCOS_d_ff2_X[26]), .B0(n4419), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n4341) );
AOI22X1TS U5907 ( .A0(Data_1[25]), .A1(n5608), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n4418), .Y(n4344) );
AOI22X1TS U5908 ( .A0(n4364), .A1(FPSENCOS_d_ff2_X[25]), .B0(n4359), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n4343) );
INVX2TS U5909 ( .A(FPSENCOS_d_ff2_Y[15]), .Y(n5558) );
AOI22X1TS U5910 ( .A0(Data_1[15]), .A1(n4358), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n4357), .Y(n4346) );
AOI22X1TS U5911 ( .A0(n4351), .A1(FPSENCOS_d_ff2_X[15]), .B0(n4433), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n4345) );
AOI22X1TS U5912 ( .A0(Data_1[14]), .A1(n4437), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n4436), .Y(n4348) );
AOI22X1TS U5913 ( .A0(n4351), .A1(FPSENCOS_d_ff2_X[14]), .B0(n4433), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n4347) );
AOI22X1TS U5914 ( .A0(Data_1[20]), .A1(n4358), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n4357), .Y(n4350) );
AOI22X1TS U5915 ( .A0(n4364), .A1(FPSENCOS_d_ff2_X[20]), .B0(n4359), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n4349) );
INVX2TS U5916 ( .A(FPSENCOS_d_ff2_Y[12]), .Y(n5555) );
AOI22X1TS U5917 ( .A0(Data_1[12]), .A1(n4437), .B0(FPADDSUB_intDX_EWSW[12]),
.B1(n4436), .Y(n4353) );
AOI22X1TS U5918 ( .A0(n4351), .A1(FPSENCOS_d_ff2_X[12]), .B0(n4359), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n4352) );
AOI22X1TS U5919 ( .A0(Data_1[29]), .A1(n5608), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n4418), .Y(n4356) );
AOI22X1TS U5920 ( .A0(n4364), .A1(FPSENCOS_d_ff2_X[29]), .B0(n4419), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n4355) );
AOI22X1TS U5921 ( .A0(Data_1[23]), .A1(n4358), .B0(FPADDSUB_intDX_EWSW[23]),
.B1(n4357), .Y(n4361) );
AOI22X1TS U5922 ( .A0(n4364), .A1(FPSENCOS_d_ff2_X[23]), .B0(n4359), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n4360) );
AOI22X1TS U5923 ( .A0(Data_1[28]), .A1(n5608), .B0(FPADDSUB_intDX_EWSW[28]),
.B1(n4418), .Y(n4363) );
AOI22X1TS U5924 ( .A0(n4364), .A1(FPSENCOS_d_ff2_X[28]), .B0(n4419), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n4362) );
AOI22X1TS U5925 ( .A0(Data_1[27]), .A1(n5608), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n4418), .Y(n4366) );
AOI22X1TS U5926 ( .A0(n4364), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4419), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n4365) );
INVX2TS U5927 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(n4374) );
INVX2TS U5928 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n4381) );
INVX2TS U5929 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n4379) );
NOR2BX1TS U5930 ( .AN(n4370), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n4371)
);
NOR2BX1TS U5931 ( .AN(n4371), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n4372)
);
NAND2BX2TS U5932 ( .AN(n4453), .B(n4372), .Y(n5726) );
BUFX3TS U5933 ( .A(n5953), .Y(n5737) );
NOR2X2TS U5934 ( .A(n5726), .B(n5737), .Y(n5724) );
INVX2TS U5935 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n4376) );
NAND2X1TS U5936 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(n5802), .Y(n4377) );
NAND2X1TS U5937 ( .A(n5737), .B(result_add_subt[25]), .Y(n4378) );
NAND2X1TS U5938 ( .A(n5737), .B(result_add_subt[26]), .Y(n4380) );
NAND2X1TS U5939 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(n5802), .Y(n4382) );
INVX2TS U5940 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n4451) );
INVX2TS U5941 ( .A(n4106), .Y(n4408) );
BUFX3TS U5942 ( .A(n4387), .Y(n5624) );
BUFX3TS U5943 ( .A(n4444), .Y(n5596) );
AOI22X1TS U5944 ( .A0(Data_2[12]), .A1(n5624), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n5596), .Y(n4386) );
BUFX3TS U5945 ( .A(n4318), .Y(n4413) );
AOI22X1TS U5946 ( .A0(n5612), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n4413),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n4385) );
BUFX3TS U5947 ( .A(n4387), .Y(n5597) );
AOI22X1TS U5948 ( .A0(Data_2[9]), .A1(n5597), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n5596), .Y(n4389) );
AOI22X1TS U5949 ( .A0(n5612), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n4413),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n4388) );
BUFX3TS U5950 ( .A(n4444), .Y(n5623) );
AOI22X1TS U5951 ( .A0(Data_2[21]), .A1(n5624), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n5623), .Y(n4391) );
BUFX3TS U5952 ( .A(n4322), .Y(n5628) );
AOI22X1TS U5953 ( .A0(n5628), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n4413),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n4390) );
AOI22X1TS U5954 ( .A0(Data_2[8]), .A1(n5597), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n5596), .Y(n4393) );
AOI22X1TS U5955 ( .A0(n5612), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n4413),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n4392) );
AOI22X1TS U5956 ( .A0(Data_2[23]), .A1(n5634), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n5660), .Y(n4395) );
AOI22X1TS U5957 ( .A0(n5628), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n4413),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n4394) );
AOI22X1TS U5958 ( .A0(Data_2[2]), .A1(n5597), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n4418), .Y(n4397) );
BUFX3TS U5959 ( .A(n4322), .Y(n5593) );
AOI22X1TS U5960 ( .A0(n5593), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n4419),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n4396) );
AOI22X1TS U5961 ( .A0(Data_2[0]), .A1(n5608), .B0(FPADDSUB_intDY_EWSW[0]),
.B1(n4418), .Y(n4399) );
AOI22X1TS U5962 ( .A0(n5593), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n4419),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n4398) );
AOI22X1TS U5963 ( .A0(Data_2[26]), .A1(n5634), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n5660), .Y(n4401) );
AOI22X1TS U5964 ( .A0(n5628), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n4413),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n4400) );
AOI22X1TS U5965 ( .A0(Data_2[24]), .A1(n5634), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n5660), .Y(n4403) );
AOI22X1TS U5966 ( .A0(n5628), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n4413),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n4402) );
AOI22X1TS U5967 ( .A0(Data_2[10]), .A1(n5597), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n5596), .Y(n4405) );
AOI22X1TS U5968 ( .A0(n5612), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n4413),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n4404) );
AOI22X1TS U5969 ( .A0(Data_2[25]), .A1(n5634), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n5660), .Y(n4407) );
AOI22X1TS U5970 ( .A0(n5628), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n4413),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n4406) );
AOI22X1TS U5971 ( .A0(Data_2[1]), .A1(n5608), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n4418), .Y(n4410) );
AOI22X1TS U5972 ( .A0(n5593), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n4419),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n4409) );
AOI22X1TS U5973 ( .A0(Data_2[4]), .A1(n5597), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n5596), .Y(n4412) );
AOI22X1TS U5974 ( .A0(n5593), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n4419),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n4411) );
AOI22X1TS U5975 ( .A0(Data_2[6]), .A1(n5597), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n5596), .Y(n4415) );
AOI22X1TS U5976 ( .A0(n5593), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n4413),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n4414) );
AOI22X1TS U5977 ( .A0(Data_1[30]), .A1(n5608), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n4418), .Y(n4417) );
AOI22X1TS U5978 ( .A0(n5593), .A1(FPSENCOS_d_ff2_X[30]), .B0(n4419), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n4416) );
AOI22X1TS U5979 ( .A0(Data_1[31]), .A1(n5608), .B0(FPADDSUB_intDX_EWSW[31]),
.B1(n4418), .Y(n4421) );
AOI22X1TS U5980 ( .A0(n5593), .A1(FPSENCOS_d_ff2_X[31]), .B0(n4419), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n4420) );
INVX2TS U5981 ( .A(FPSENCOS_d_ff2_Y[5]), .Y(n5546) );
AOI22X1TS U5982 ( .A0(Data_1[5]), .A1(n4437), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n4436), .Y(n4424) );
BUFX3TS U5983 ( .A(n4322), .Y(n4445) );
AOI22X1TS U5984 ( .A0(n4445), .A1(FPSENCOS_d_ff2_X[5]), .B0(n4433), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n4423) );
INVX2TS U5985 ( .A(FPSENCOS_d_ff2_Y[3]), .Y(n5544) );
AOI22X1TS U5986 ( .A0(Data_1[3]), .A1(n4387), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n4444), .Y(n4426) );
AOI22X1TS U5987 ( .A0(n4445), .A1(FPSENCOS_d_ff2_X[3]), .B0(n5629), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n4425) );
AOI22X1TS U5988 ( .A0(Data_1[7]), .A1(n4437), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n4436), .Y(n4428) );
AOI22X1TS U5989 ( .A0(n4445), .A1(FPSENCOS_d_ff2_X[7]), .B0(n4433), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n4427) );
INVX2TS U5990 ( .A(FPSENCOS_d_ff2_Y[4]), .Y(n5545) );
AOI22X1TS U5991 ( .A0(Data_1[4]), .A1(n4387), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n4444), .Y(n4430) );
AOI22X1TS U5992 ( .A0(n4445), .A1(FPSENCOS_d_ff2_X[4]), .B0(n5629), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n4429) );
INVX2TS U5993 ( .A(FPSENCOS_d_ff2_Y[8]), .Y(n5549) );
AOI22X1TS U5994 ( .A0(Data_1[8]), .A1(n4437), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n4436), .Y(n4432) );
AOI22X1TS U5995 ( .A0(n4445), .A1(FPSENCOS_d_ff2_X[8]), .B0(n4433), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n4431) );
INVX2TS U5996 ( .A(FPSENCOS_d_ff2_Y[9]), .Y(n5551) );
AOI22X1TS U5997 ( .A0(Data_1[9]), .A1(n4437), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n4436), .Y(n4435) );
AOI22X1TS U5998 ( .A0(n4445), .A1(FPSENCOS_d_ff2_X[9]), .B0(n4433), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n4434) );
INVX2TS U5999 ( .A(FPSENCOS_d_ff2_Y[6]), .Y(n5547) );
AOI22X1TS U6000 ( .A0(Data_1[6]), .A1(n4437), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n4436), .Y(n4439) );
AOI22X1TS U6001 ( .A0(n4445), .A1(FPSENCOS_d_ff2_X[6]), .B0(n5629), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n4438) );
INVX2TS U6002 ( .A(FPSENCOS_d_ff2_Y[2]), .Y(n5543) );
AOI22X1TS U6003 ( .A0(Data_1[2]), .A1(n4387), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n4444), .Y(n4441) );
AOI22X1TS U6004 ( .A0(n4445), .A1(FPSENCOS_d_ff2_X[2]), .B0(n5629), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n4440) );
INVX2TS U6005 ( .A(FPSENCOS_d_ff2_Y[1]), .Y(n5541) );
AOI22X1TS U6006 ( .A0(Data_1[1]), .A1(n5634), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n4444), .Y(n4443) );
AOI22X1TS U6007 ( .A0(n4445), .A1(FPSENCOS_d_ff2_X[1]), .B0(n5629), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n4442) );
AOI22X1TS U6008 ( .A0(n5634), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n4444), .Y(n4447) );
AOI22X1TS U6009 ( .A0(n4445), .A1(FPSENCOS_d_ff2_X[0]), .B0(
FPSENCOS_d_ff2_Z[0]), .B1(n5629), .Y(n4446) );
INVX2TS U6010 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n5114) );
AND3X2TS U6011 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[3]), .C(n4449), .Y(n4450) );
NAND3BX1TS U6012 ( .AN(n4451), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .C(n4450),
.Y(n4452) );
NOR2X1TS U6013 ( .A(n5114), .B(n4452), .Y(n4454) );
OAI2BB1X4TS U6014 ( .A0N(n4454), .A1N(n4453), .B0(n5802), .Y(n5115) );
BUFX3TS U6015 ( .A(n5818), .Y(n4541) );
AOI22X1TS U6016 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n2527), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n4541), .Y(n4457) );
AOI22X1TS U6017 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n2527), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n4541), .Y(n4458) );
AOI22X1TS U6018 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n2527), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n4541), .Y(n4459) );
AOI22X1TS U6019 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n2527), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n4541), .Y(n4460) );
AOI22X1TS U6020 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n2527), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n4541), .Y(n4461) );
AOI22X1TS U6021 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n2527), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n4541), .Y(n4462) );
AOI22X1TS U6022 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n2527), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n4541), .Y(n4463) );
NAND2X1TS U6023 ( .A(n4686), .B(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n4466) );
NAND2X1TS U6024 ( .A(n4612), .B(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n4465) );
NAND2X1TS U6025 ( .A(n4616), .B(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n4464) );
NAND3X1TS U6026 ( .A(n4466), .B(n4465), .C(n4464), .Y(n4626) );
INVX2TS U6027 ( .A(n4626), .Y(n4689) );
AOI21X1TS U6028 ( .A0(n5862), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n4467) );
AOI211X1TS U6029 ( .A0(n4475), .A1(FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n4474),
.C0(n4473), .Y(n4479) );
AOI31X1TS U6030 ( .A0(n4479), .A1(n4478), .A2(n4477), .B0(n5478), .Y(n5109)
);
INVX2TS U6031 ( .A(n4480), .Y(n4611) );
AOI211X4TS U6032 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[0]), .A1(n5480), .B0(
n5109), .C0(n4611), .Y(n4688) );
INVX2TS U6033 ( .A(n4569), .Y(n4596) );
AOI21X1TS U6034 ( .A0(n4481), .A1(FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n4483) );
OAI31X1TS U6035 ( .A0(n4483), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(
FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n4482), .Y(n4484) );
INVX2TS U6036 ( .A(n4484), .Y(n4493) );
NOR2X1TS U6037 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(n4486), .Y(n4489) );
INVX2TS U6038 ( .A(n5639), .Y(n4692) );
OR2X4TS U6039 ( .A(n4560), .B(n4692), .Y(n5640) );
AOI21X1TS U6040 ( .A0(n4608), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n5480),
.Y(n4495) );
AOI22X1TS U6041 ( .A0(n4692), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n2275),
.B1(n4687), .Y(n4496) );
OAI21X1TS U6042 ( .A0(n4689), .A1(n2316), .B0(n4496), .Y(n1811) );
BUFX3TS U6043 ( .A(n5818), .Y(n4553) );
AOI22X1TS U6044 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n4531), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n4553), .Y(n4497) );
AOI22X1TS U6045 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n4531), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n4541), .Y(n4498) );
AOI22X1TS U6046 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n4531), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n4553), .Y(n4499) );
AOI22X1TS U6047 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n4531), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n4553), .Y(n4500) );
AOI22X1TS U6048 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n4531), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n4553), .Y(n4501) );
AOI22X1TS U6049 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n4531), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n4553), .Y(n4502) );
AOI22X1TS U6050 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n4531), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n4548), .Y(n4503) );
BUFX3TS U6051 ( .A(n5818), .Y(n5790) );
AOI22X1TS U6052 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n4531), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n5790), .Y(n4504) );
INVX2TS U6053 ( .A(n4505), .Y(n1417) );
AOI22X1TS U6054 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n4523), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n5477), .Y(n4506) );
AOI22X1TS U6055 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n4523), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n5477), .Y(n4507) );
AOI22X1TS U6056 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n4523), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n5477), .Y(n4508) );
AOI22X1TS U6057 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n4530), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n4521), .Y(n4509) );
AOI22X1TS U6058 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n4510), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n4521), .Y(n4511) );
AOI22X1TS U6059 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n4523), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n5477), .Y(n4512) );
AOI22X1TS U6060 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n4523), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n5477), .Y(n4513) );
AOI22X1TS U6061 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n4523), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n4521), .Y(n4514) );
AOI22X1TS U6062 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n4530), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n4521), .Y(n4515) );
AOI22X1TS U6063 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n4530), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n4553), .Y(n4516) );
AOI22X1TS U6064 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n4530), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n5818), .Y(n4517) );
AOI22X1TS U6065 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n4530), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n5790), .Y(n4518) );
AOI22X1TS U6066 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n4523), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n5477), .Y(n4519) );
AOI22X1TS U6067 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4523), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n5477), .Y(n4520) );
AOI22X1TS U6068 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n4530), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n4521), .Y(n4522) );
AOI22X1TS U6069 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n4523), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n5790), .Y(n4524) );
AOI22X1TS U6070 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n4530), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n5477), .Y(n4525) );
AOI22X1TS U6071 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n4542), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n4548), .Y(n4527) );
AOI22X1TS U6072 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n4542), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n4548), .Y(n4528) );
AOI22X1TS U6073 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n4542), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n4548), .Y(n4529) );
INVX2TS U6074 ( .A(n4532), .Y(n1465) );
INVX2TS U6075 ( .A(n4533), .Y(n4546) );
AOI22X1TS U6076 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n4554), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n4541), .Y(n4534) );
AOI22X1TS U6077 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n4542), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n4548), .Y(n4535) );
AOI22X1TS U6078 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n4554), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n5790), .Y(n4536) );
AOI22X1TS U6079 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n4542), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n4548), .Y(n4537) );
AOI22X1TS U6080 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n4542), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n4548), .Y(n4539) );
AOI22X1TS U6081 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n4542), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n4548), .Y(n4540) );
AOI22X1TS U6082 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4542), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n4541), .Y(n4543) );
AOI22X1TS U6083 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n4554), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n5790), .Y(n4545) );
AOI22X1TS U6084 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n4554), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n4553), .Y(n4547) );
AOI22X1TS U6085 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n4554), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n4548), .Y(n4549) );
AOI22X1TS U6086 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n4554), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n4553), .Y(n4550) );
AOI22X1TS U6087 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n4554), .B0(
FPADDSUB_DMP_EXP_EWSW[27]), .B1(n5790), .Y(n4551) );
AOI22X1TS U6088 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n4554), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n4553), .Y(n4552) );
AOI22X1TS U6089 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n4554), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n4553), .Y(n4555) );
NAND2X1TS U6090 ( .A(n4611), .B(FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n4559) );
NAND2X1TS U6091 ( .A(n4612), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n4558) );
NAND2X1TS U6092 ( .A(n4600), .B(FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n4557) );
NAND3X1TS U6093 ( .A(n4559), .B(n4558), .C(n4557), .Y(n4639) );
INVX2TS U6094 ( .A(n4639), .Y(n4647) );
AOI222X4TS U6095 ( .A0(n5478), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n4686), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n4596), .Y(n4665) );
INVX2TS U6096 ( .A(n4665), .Y(n4643) );
AOI22X1TS U6097 ( .A0(n4679), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n2402),
.B1(n4643), .Y(n4565) );
AOI22X1TS U6098 ( .A0(n4612), .A1(FPADDSUB_Raw_mant_NRM_SWR[17]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[6]), .B1(n4616), .Y(n4562) );
AOI22X1TS U6099 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1(n4686), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n5478), .Y(n4563) );
AOI22X1TS U6100 ( .A0(n4494), .A1(n4662), .B0(n2297), .B1(n4675), .Y(n4564)
);
NAND2X1TS U6101 ( .A(n4611), .B(FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n4568) );
NAND2X1TS U6102 ( .A(n4612), .B(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n4567) );
NAND2X1TS U6103 ( .A(n4600), .B(FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n4566) );
NAND3X1TS U6104 ( .A(n4568), .B(n4567), .C(n4566), .Y(n4583) );
INVX2TS U6105 ( .A(n4583), .Y(n4642) );
AOI22X1TS U6106 ( .A0(n4679), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n2295),
.B1(n4639), .Y(n4572) );
AOI22X1TS U6107 ( .A0(n4680), .A1(FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n4616), .Y(n4570) );
AOI22X1TS U6108 ( .A0(n2275), .A1(n4644), .B0(n2404), .B1(n4662), .Y(n4571)
);
NAND2X1TS U6109 ( .A(n4611), .B(FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n4575) );
NAND2X1TS U6110 ( .A(n4612), .B(FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n4574) );
NAND2X1TS U6111 ( .A(n2299), .B(FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n4573) );
INVX2TS U6112 ( .A(n4682), .Y(n4579) );
AOI22X1TS U6113 ( .A0(n4679), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n2401),
.B1(n4583), .Y(n4578) );
AOI22X1TS U6114 ( .A0(n4680), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[2]), .B1(n4616), .Y(n4576) );
AOI22X1TS U6115 ( .A0(n4494), .A1(n4649), .B0(n2403), .B1(n4644), .Y(n4577)
);
NAND2X1TS U6116 ( .A(n4686), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4582) );
NAND2X1TS U6117 ( .A(n4612), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n4581) );
AOI22X1TS U6118 ( .A0(n4679), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n2401),
.B1(n4649), .Y(n4585) );
AOI22X1TS U6119 ( .A0(n4494), .A1(n4682), .B0(n2403), .B1(n4583), .Y(n4584)
);
NAND2X1TS U6120 ( .A(n4612), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n4588) );
NAND2X1TS U6121 ( .A(n4616), .B(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n4587) );
NAND3X1TS U6122 ( .A(n4589), .B(n4588), .C(n4587), .Y(n4629) );
INVX2TS U6123 ( .A(n4629), .Y(n4638) );
NAND2X1TS U6124 ( .A(n4686), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n4592) );
NAND2X1TS U6125 ( .A(n4612), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4591) );
NAND2X1TS U6126 ( .A(n4616), .B(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n4590) );
NAND3X1TS U6127 ( .A(n4592), .B(n4591), .C(n4590), .Y(n4634) );
AOI22X1TS U6128 ( .A0(n4692), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n2295),
.B1(n4634), .Y(n4595) );
AOI22X1TS U6129 ( .A0(n4611), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n5480), .Y(n4593) );
AOI22X1TS U6130 ( .A0(n4494), .A1(n4633), .B0(n2403), .B1(n4626), .Y(n4594)
);
AOI222X4TS U6131 ( .A0(n5478), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n4611), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n4596), .Y(n4678) );
INVX2TS U6132 ( .A(n4678), .Y(n4661) );
AOI22X1TS U6133 ( .A0(n4673), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n2401),
.B1(n4661), .Y(n4599) );
AOI22X1TS U6134 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[13]), .A1(n4680), .B0(
FPADDSUB_DmP_mant_SHT1_SW[10]), .B1(n5478), .Y(n4597) );
AOI22X1TS U6135 ( .A0(n2275), .A1(n4675), .B0(n2403), .B1(n4672), .Y(n4598)
);
AOI222X4TS U6136 ( .A0(n4600), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n4611), .C0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .C1(n4680), .Y(n4660) );
INVX2TS U6137 ( .A(n4660), .Y(n4674) );
AOI22X1TS U6138 ( .A0(n4673), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n2295),
.B1(n4674), .Y(n4603) );
AOI22X1TS U6139 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n4680), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n5478), .Y(n4601) );
AOI22X1TS U6140 ( .A0(n2275), .A1(n4672), .B0(n2403), .B1(n4668), .Y(n4602)
);
NAND2X1TS U6141 ( .A(n4686), .B(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n4606) );
NAND2X1TS U6142 ( .A(n4612), .B(FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n4605) );
NAND2X1TS U6143 ( .A(n4600), .B(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n4604) );
NAND3X1TS U6144 ( .A(n4606), .B(n4605), .C(n4604), .Y(n4653) );
INVX2TS U6145 ( .A(n4653), .Y(n4632) );
AOI22X1TS U6146 ( .A0(n4692), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n2295),
.B1(n4629), .Y(n4610) );
AOI22X1TS U6147 ( .A0(n4611), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[18]), .B1(n4616), .Y(n4607) );
AOI22X1TS U6148 ( .A0(n2275), .A1(n4635), .B0(n2297), .B1(n4633), .Y(n4609)
);
OAI211X1TS U6149 ( .A0(n4632), .A1(n2316), .B0(n4610), .C0(n4609), .Y(n1806)
);
NAND2X1TS U6150 ( .A(n4686), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n4615) );
NAND2X1TS U6151 ( .A(n4612), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n4614) );
NAND2X1TS U6152 ( .A(n4616), .B(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n4613) );
NAND3X1TS U6153 ( .A(n4615), .B(n4614), .C(n4613), .Y(n4667) );
INVX2TS U6154 ( .A(n4667), .Y(n4656) );
AOI22X1TS U6155 ( .A0(n4692), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n2295),
.B1(n4653), .Y(n4619) );
AOI22X1TS U6156 ( .A0(n4680), .A1(FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n4616), .Y(n4617) );
AOI22X1TS U6157 ( .A0(n2275), .A1(n4652), .B0(n2297), .B1(n4635), .Y(n4618)
);
OAI211X1TS U6158 ( .A0(n4656), .A1(n2316), .B0(n4619), .C0(n4618), .Y(n1804)
);
AOI222X4TS U6159 ( .A0(n5478), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n4680), .C0(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(n4686), .Y(n4671) );
AOI22X1TS U6160 ( .A0(n4673), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n2401),
.B1(n4667), .Y(n4622) );
AOI22X1TS U6161 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n4680), .B0(
FPADDSUB_DmP_mant_SHT1_SW[14]), .B1(n5478), .Y(n4620) );
AOI22X1TS U6162 ( .A0(n2275), .A1(n4666), .B0(n2404), .B1(n4652), .Y(n4621)
);
INVX2TS U6163 ( .A(n4671), .Y(n4657) );
AOI22X1TS U6164 ( .A0(n4673), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n2295),
.B1(n4657), .Y(n4624) );
AOI22X1TS U6165 ( .A0(n4494), .A1(n4668), .B0(n2404), .B1(n4666), .Y(n4623)
);
INVX2TS U6166 ( .A(n4634), .Y(n4690) );
AOI22X1TS U6167 ( .A0(n4692), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n2287),
.B1(n4633), .Y(n4628) );
AOI22X1TS U6168 ( .A0(n2401), .A1(n4626), .B0(n2297), .B1(n4687), .Y(n4627)
);
OAI211X1TS U6169 ( .A0(n4690), .A1(n2307), .B0(n4628), .C0(n4627), .Y(n1809)
);
AOI22X1TS U6170 ( .A0(n4692), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n2401),
.B1(n4635), .Y(n4631) );
AOI22X1TS U6171 ( .A0(n2287), .A1(n4652), .B0(n2297), .B1(n4629), .Y(n4630)
);
OAI211X1TS U6172 ( .A0(n4632), .A1(n2307), .B0(n4631), .C0(n4630), .Y(n1805)
);
AOI22X1TS U6173 ( .A0(n4692), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n2295),
.B1(n4633), .Y(n4637) );
AOI22X1TS U6174 ( .A0(n2287), .A1(n4635), .B0(n2403), .B1(n4634), .Y(n4636)
);
AOI22X1TS U6175 ( .A0(n4679), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n2401),
.B1(n4644), .Y(n4641) );
AOI22X1TS U6176 ( .A0(n4625), .A1(n4649), .B0(n2403), .B1(n4639), .Y(n4640)
);
AOI22X1TS U6177 ( .A0(n4679), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n2295),
.B1(n4662), .Y(n4646) );
AOI22X1TS U6178 ( .A0(n2287), .A1(n4644), .B0(n2297), .B1(n4643), .Y(n4645)
);
AOI22X1TS U6179 ( .A0(n4673), .A1(FPADDSUB_Data_array_SWR[1]), .B0(n2402),
.B1(n4682), .Y(n4651) );
OAI2BB2X1TS U6180 ( .B0(n4648), .B1(n2251), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[24]), .A1N(n4680), .Y(n4681) );
AOI22X1TS U6181 ( .A0(n2287), .A1(n4681), .B0(n2403), .B1(n4649), .Y(n4650)
);
AOI22X1TS U6182 ( .A0(n4673), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n2401),
.B1(n4652), .Y(n4655) );
AOI22X1TS U6183 ( .A0(n2287), .A1(n4666), .B0(n2403), .B1(n4653), .Y(n4654)
);
AOI22X1TS U6184 ( .A0(n4673), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n2401),
.B1(n4668), .Y(n4659) );
AOI22X1TS U6185 ( .A0(n2287), .A1(n4672), .B0(n2404), .B1(n4657), .Y(n4658)
);
AOI22X1TS U6186 ( .A0(n4673), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n2295),
.B1(n4675), .Y(n4664) );
AOI22X1TS U6187 ( .A0(n2287), .A1(n4662), .B0(n2404), .B1(n4661), .Y(n4663)
);
AOI22X1TS U6188 ( .A0(n4673), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n2401),
.B1(n4666), .Y(n4670) );
AOI22X1TS U6189 ( .A0(n2287), .A1(n4668), .B0(n2404), .B1(n4667), .Y(n4669)
);
AOI22X1TS U6190 ( .A0(n4673), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n2295),
.B1(n4672), .Y(n4677) );
AOI22X1TS U6191 ( .A0(n4625), .A1(n4675), .B0(n2297), .B1(n4674), .Y(n4676)
);
AOI22X1TS U6192 ( .A0(n4680), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n4679),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n4684) );
AOI21X1TS U6193 ( .A0(n2297), .A1(n4682), .B0(n4681), .Y(n4683) );
AOI21X1TS U6194 ( .A0(n4688), .A1(n4687), .B0(n4611), .Y(n5641) );
OAI22X1TS U6195 ( .A0(n4690), .A1(n2315), .B0(n4689), .B1(n2306), .Y(n4691)
);
AOI21X1TS U6196 ( .A0(n4692), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n4691),
.Y(n4693) );
OAI21X1TS U6197 ( .A0(n5641), .A1(n4694), .B0(n4693), .Y(n1810) );
AOI22X1TS U6198 ( .A0(n4698), .A1(n4697), .B0(n5009), .B1(n4696), .Y(n4699)
);
NAND2X1TS U6199 ( .A(n5460), .B(n5482), .Y(n5451) );
NOR2X2TS U6200 ( .A(ready_add_subt), .B(n5451), .Y(n5485) );
OAI2BB1X1TS U6201 ( .A0N(FPMULT_Op_MY[29]), .A1N(n5822), .B0(n4707), .Y(
n4702) );
XOR2X1TS U6202 ( .A(n2419), .B(n4702), .Y(DP_OP_234J16_127_8543_n16) );
OAI2BB1X1TS U6203 ( .A0N(FPMULT_Op_MY[28]), .A1N(n5822), .B0(n4707), .Y(
n4703) );
XOR2X1TS U6204 ( .A(n2419), .B(n4703), .Y(DP_OP_234J16_127_8543_n17) );
OAI2BB1X1TS U6205 ( .A0N(FPMULT_Op_MY[27]), .A1N(n5822), .B0(n4707), .Y(
n4704) );
XOR2X1TS U6206 ( .A(n2419), .B(n4704), .Y(DP_OP_234J16_127_8543_n18) );
OAI2BB1X1TS U6207 ( .A0N(FPMULT_Op_MY[26]), .A1N(n5822), .B0(n4707), .Y(
n4705) );
XOR2X1TS U6208 ( .A(n2419), .B(n4705), .Y(DP_OP_234J16_127_8543_n19) );
OAI2BB1X1TS U6209 ( .A0N(FPMULT_Op_MY[25]), .A1N(n5822), .B0(n4707), .Y(
n4706) );
XOR2X1TS U6210 ( .A(n2419), .B(n4706), .Y(DP_OP_234J16_127_8543_n20) );
OAI2BB1X1TS U6211 ( .A0N(FPMULT_Op_MY[24]), .A1N(n5822), .B0(n4707), .Y(
n4708) );
XOR2X1TS U6212 ( .A(n2418), .B(n4708), .Y(DP_OP_234J16_127_8543_n21) );
NOR2BX1TS U6213 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4709) );
XOR2X1TS U6214 ( .A(n2211), .B(n4709), .Y(DP_OP_26J16_124_9022_n14) );
NOR2BX1TS U6215 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4710) );
XOR2X1TS U6216 ( .A(n2211), .B(n4710), .Y(DP_OP_26J16_124_9022_n15) );
NOR2BX1TS U6217 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4711) );
XOR2X1TS U6218 ( .A(n2211), .B(n4711), .Y(DP_OP_26J16_124_9022_n16) );
NOR2BX1TS U6219 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4712) );
XOR2X1TS U6220 ( .A(n2276), .B(n4712), .Y(DP_OP_26J16_124_9022_n17) );
INVX2TS U6221 ( .A(n4715), .Y(n5013) );
NAND2X1TS U6222 ( .A(FPMULT_Sgf_normalized_result[6]), .B(
FPMULT_Sgf_normalized_result[7]), .Y(n4720) );
NAND2X1TS U6223 ( .A(FPMULT_Sgf_normalized_result[5]), .B(
FPMULT_Sgf_normalized_result[4]), .Y(n4893) );
NOR2X1TS U6224 ( .A(n5825), .B(n5847), .Y(n4856) );
NAND2X1TS U6225 ( .A(n4856), .B(FPMULT_Sgf_normalized_result[10]), .Y(n4723)
);
OAI21X2TS U6226 ( .A0(n4727), .A1(n4726), .B0(n2283), .Y(n4738) );
MXI2X1TS U6227 ( .A(FPMULT_P_Sgf[46]), .B(FPMULT_Add_result[23]), .S0(
FPMULT_FSM_selector_C), .Y(n4728) );
AOI21X1TS U6228 ( .A0(n4738), .A1(n4728), .B0(n4865), .Y(n4729) );
AHHCINX2TS U6229 ( .A(FPMULT_Sgf_normalized_result[22]), .CIN(n4730), .S(
n4731), .CO(n5000) );
INVX2TS U6230 ( .A(n4782), .Y(n4773) );
XOR2X1TS U6231 ( .A(n4733), .B(n4732), .Y(n4734) );
NAND2X1TS U6232 ( .A(n4735), .B(n4738), .Y(n4736) );
AOI22X1TS U6233 ( .A0(n2309), .A1(FPMULT_Add_result[23]), .B0(
FPMULT_Sgf_normalized_result[22]), .B1(n4865), .Y(n4739) );
OAI2BB1X1TS U6234 ( .A0N(FPMULT_P_Sgf[46]), .A1N(n2450), .B0(n4739), .Y(
n4740) );
AOI21X1TS U6235 ( .A0(n2408), .A1(FPMULT_Add_result[22]), .B0(n4740), .Y(
n4741) );
OAI2BB1X1TS U6236 ( .A0N(n2412), .A1N(FPMULT_P_Sgf[45]), .B0(n4741), .Y(
n1527) );
AHHCONX2TS U6237 ( .A(FPMULT_Sgf_normalized_result[21]), .CI(n4742), .CON(
n4730), .S(n4743) );
AOI22X1TS U6238 ( .A0(n4744), .A1(FPMULT_Add_result[22]), .B0(
FPMULT_Sgf_normalized_result[21]), .B1(n4865), .Y(n4745) );
OAI2BB1X1TS U6239 ( .A0N(FPMULT_P_Sgf[45]), .A1N(n2449), .B0(n4745), .Y(
n4746) );
AOI21X1TS U6240 ( .A0(n2408), .A1(FPMULT_Add_result[21]), .B0(n4746), .Y(
n4747) );
OAI2BB1X1TS U6241 ( .A0N(n2412), .A1N(FPMULT_P_Sgf[44]), .B0(n4747), .Y(
n1526) );
AHHCINX2TS U6242 ( .A(FPMULT_Sgf_normalized_result[20]), .CIN(n4748), .S(
n4749), .CO(n4742) );
XOR2X1TS U6243 ( .A(n4751), .B(n4750), .Y(n4752) );
AOI22X1TS U6244 ( .A0(n2309), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Sgf_normalized_result[20]), .B1(n4865), .Y(n4753) );
OAI2BB1X1TS U6245 ( .A0N(n2449), .A1N(FPMULT_P_Sgf[44]), .B0(n4753), .Y(
n4754) );
AOI21X1TS U6246 ( .A0(n2408), .A1(FPMULT_Add_result[20]), .B0(n4754), .Y(
n4755) );
OAI2BB1X1TS U6247 ( .A0N(n2412), .A1N(FPMULT_P_Sgf[43]), .B0(n4755), .Y(
n1525) );
AHHCONX2TS U6248 ( .A(FPMULT_Sgf_normalized_result[19]), .CI(n4756), .CON(
n4748), .S(n4757) );
XNOR2X1TS U6249 ( .A(n4759), .B(n4758), .Y(n4760) );
BUFX3TS U6250 ( .A(n4865), .Y(n4995) );
AOI22X1TS U6251 ( .A0(n4744), .A1(FPMULT_Add_result[20]), .B0(
FPMULT_Sgf_normalized_result[19]), .B1(n4995), .Y(n4761) );
OAI2BB1X1TS U6252 ( .A0N(n2450), .A1N(FPMULT_P_Sgf[43]), .B0(n4761), .Y(
n4762) );
AOI21X1TS U6253 ( .A0(n2408), .A1(FPMULT_Add_result[19]), .B0(n4762), .Y(
n4763) );
OAI2BB1X1TS U6254 ( .A0N(n2412), .A1N(FPMULT_P_Sgf[42]), .B0(n4763), .Y(
n1524) );
AHHCINX2TS U6255 ( .A(FPMULT_Sgf_normalized_result[18]), .CIN(n4764), .S(
n4765), .CO(n4756) );
XOR2X1TS U6256 ( .A(n4767), .B(n4766), .Y(n4768) );
AOI22X1TS U6257 ( .A0(n2309), .A1(FPMULT_Add_result[19]), .B0(
FPMULT_Sgf_normalized_result[18]), .B1(n4995), .Y(n4769) );
OAI2BB1X1TS U6258 ( .A0N(n2451), .A1N(FPMULT_P_Sgf[42]), .B0(n4769), .Y(
n4770) );
AOI21X1TS U6259 ( .A0(n2408), .A1(FPMULT_Add_result[18]), .B0(n4770), .Y(
n4771) );
OAI2BB1X1TS U6260 ( .A0N(n2412), .A1N(FPMULT_P_Sgf[41]), .B0(n4771), .Y(
n1523) );
AHHCONX2TS U6261 ( .A(FPMULT_Sgf_normalized_result[17]), .CI(n4772), .CON(
n4764), .S(n4774) );
XNOR2X1TS U6262 ( .A(n4776), .B(n4775), .Y(n4777) );
AOI22X1TS U6263 ( .A0(n2310), .A1(FPMULT_Add_result[18]), .B0(
FPMULT_Sgf_normalized_result[17]), .B1(n4995), .Y(n4778) );
OAI2BB1X1TS U6264 ( .A0N(n2449), .A1N(FPMULT_P_Sgf[41]), .B0(n4778), .Y(
n4779) );
AOI21X1TS U6265 ( .A0(n2410), .A1(FPMULT_Add_result[17]), .B0(n4779), .Y(
n4780) );
OAI2BB1X1TS U6266 ( .A0N(n2412), .A1N(FPMULT_P_Sgf[40]), .B0(n4780), .Y(
n1522) );
AHHCINX2TS U6267 ( .A(FPMULT_Sgf_normalized_result[16]), .CIN(n4781), .S(
n4783), .CO(n4772) );
AOI21X1TS U6268 ( .A0(n4887), .A1(n4786), .B0(n4785), .Y(n4788) );
XOR2X1TS U6269 ( .A(n4788), .B(n4787), .Y(n4789) );
AOI22X1TS U6270 ( .A0(n2309), .A1(FPMULT_Add_result[17]), .B0(
FPMULT_Sgf_normalized_result[16]), .B1(n4995), .Y(n4790) );
OAI2BB1X1TS U6271 ( .A0N(n2450), .A1N(FPMULT_P_Sgf[40]), .B0(n4790), .Y(
n4791) );
AOI21X1TS U6272 ( .A0(n2409), .A1(FPMULT_Add_result[16]), .B0(n4791), .Y(
n4792) );
OAI2BB1X1TS U6273 ( .A0N(n2413), .A1N(FPMULT_P_Sgf[39]), .B0(n4792), .Y(
n1521) );
AHHCONX2TS U6274 ( .A(FPMULT_Sgf_normalized_result[15]), .CI(n4793), .CON(
n4781), .S(n4794) );
INVX2TS U6275 ( .A(n4795), .Y(n4798) );
INVX2TS U6276 ( .A(n4796), .Y(n4797) );
AOI21X4TS U6277 ( .A0(n4887), .A1(n4798), .B0(n4797), .Y(n4820) );
INVX2TS U6278 ( .A(n4820), .Y(n4837) );
AOI22X1TS U6279 ( .A0(n2310), .A1(FPMULT_Add_result[16]), .B0(
FPMULT_Sgf_normalized_result[15]), .B1(n4995), .Y(n4804) );
OAI2BB1X1TS U6280 ( .A0N(n2451), .A1N(FPMULT_P_Sgf[39]), .B0(n4804), .Y(
n4805) );
AOI21X1TS U6281 ( .A0(n2410), .A1(FPMULT_Add_result[15]), .B0(n4805), .Y(
n4806) );
OAI2BB1X1TS U6282 ( .A0N(n2414), .A1N(FPMULT_P_Sgf[38]), .B0(n4806), .Y(
n1520) );
AHHCINX2TS U6283 ( .A(FPMULT_Sgf_normalized_result[14]), .CIN(n4807), .S(
n4808), .CO(n4793) );
INVX2TS U6284 ( .A(n4809), .Y(n4811) );
NAND2X1TS U6285 ( .A(n4811), .B(n4810), .Y(n4812) );
XOR2X1TS U6286 ( .A(n4813), .B(n4812), .Y(n4814) );
AOI22X1TS U6287 ( .A0(n2310), .A1(FPMULT_Add_result[15]), .B0(
FPMULT_Sgf_normalized_result[14]), .B1(n4995), .Y(n4815) );
OAI2BB1X1TS U6288 ( .A0N(n2449), .A1N(FPMULT_P_Sgf[38]), .B0(n4815), .Y(
n4816) );
AOI21X1TS U6289 ( .A0(n2409), .A1(FPMULT_Add_result[14]), .B0(n4816), .Y(
n4817) );
OAI2BB1X1TS U6290 ( .A0N(n2413), .A1N(FPMULT_P_Sgf[37]), .B0(n4817), .Y(
n1519) );
AHHCONX2TS U6291 ( .A(FPMULT_Sgf_normalized_result[13]), .CI(n4818), .CON(
n4807), .S(n4819) );
INVX2TS U6292 ( .A(n4821), .Y(n4823) );
NAND2X1TS U6293 ( .A(n4823), .B(n4822), .Y(n4824) );
XNOR2X1TS U6294 ( .A(n4825), .B(n4824), .Y(n4827) );
AOI22X1TS U6295 ( .A0(n4744), .A1(FPMULT_Add_result[14]), .B0(
FPMULT_Sgf_normalized_result[13]), .B1(n4995), .Y(n4828) );
OAI2BB1X1TS U6296 ( .A0N(n2450), .A1N(FPMULT_P_Sgf[37]), .B0(n4828), .Y(
n4829) );
AOI21X1TS U6297 ( .A0(n2410), .A1(FPMULT_Add_result[13]), .B0(n4829), .Y(
n4830) );
OAI2BB1X1TS U6298 ( .A0N(n2414), .A1N(FPMULT_P_Sgf[36]), .B0(n4830), .Y(
n1518) );
AHHCINX2TS U6299 ( .A(FPMULT_Sgf_normalized_result[12]), .CIN(n4831), .S(
n4832), .CO(n4818) );
INVX2TS U6300 ( .A(n4833), .Y(n4835) );
NAND2X1TS U6301 ( .A(n4835), .B(n4834), .Y(n4836) );
XNOR2X1TS U6302 ( .A(n4837), .B(n4836), .Y(n4838) );
BUFX3TS U6303 ( .A(n5377), .Y(n4962) );
AOI22X1TS U6304 ( .A0(n2310), .A1(FPMULT_Add_result[13]), .B0(
FPMULT_Sgf_normalized_result[12]), .B1(n4995), .Y(n4839) );
OAI2BB1X1TS U6305 ( .A0N(n2451), .A1N(FPMULT_P_Sgf[36]), .B0(n4839), .Y(
n4840) );
AOI21X1TS U6306 ( .A0(n2409), .A1(FPMULT_Add_result[12]), .B0(n4840), .Y(
n4841) );
OAI2BB1X1TS U6307 ( .A0N(n2413), .A1N(FPMULT_P_Sgf[35]), .B0(n4841), .Y(
n1517) );
AHHCONX2TS U6308 ( .A(FPMULT_Sgf_normalized_result[11]), .CI(n4842), .CON(
n4831), .S(n4843) );
NAND2X1TS U6309 ( .A(n4848), .B(n4847), .Y(n4849) );
XNOR2X1TS U6310 ( .A(n4850), .B(n4849), .Y(n4851) );
AOI22X1TS U6311 ( .A0(n4744), .A1(FPMULT_Add_result[12]), .B0(
FPMULT_Sgf_normalized_result[11]), .B1(n4995), .Y(n4852) );
OAI2BB1X1TS U6312 ( .A0N(n2449), .A1N(FPMULT_P_Sgf[35]), .B0(n4852), .Y(
n4853) );
AOI21X1TS U6313 ( .A0(n2410), .A1(FPMULT_Add_result[11]), .B0(n4853), .Y(
n4854) );
OAI2BB1X1TS U6314 ( .A0N(n2414), .A1N(FPMULT_P_Sgf[34]), .B0(n4854), .Y(
n1516) );
NAND2X1TS U6315 ( .A(n4882), .B(n4856), .Y(n4857) );
XOR2X1TS U6316 ( .A(n4857), .B(n5938), .Y(n4858) );
INVX2TS U6317 ( .A(n4859), .Y(n4861) );
NAND2X1TS U6318 ( .A(n4861), .B(n4860), .Y(n4862) );
XOR2X1TS U6319 ( .A(n4863), .B(n4862), .Y(n4864) );
BUFX3TS U6320 ( .A(n4865), .Y(n4985) );
AOI22X1TS U6321 ( .A0(n2310), .A1(FPMULT_Add_result[11]), .B0(
FPMULT_Sgf_normalized_result[10]), .B1(n4985), .Y(n4866) );
OAI2BB1X1TS U6322 ( .A0N(n2450), .A1N(FPMULT_P_Sgf[34]), .B0(n4866), .Y(
n4867) );
AOI21X1TS U6323 ( .A0(n2409), .A1(FPMULT_Add_result[10]), .B0(n4867), .Y(
n4868) );
OAI2BB1X1TS U6324 ( .A0N(n2413), .A1N(FPMULT_P_Sgf[33]), .B0(n4868), .Y(
n1515) );
NAND2X1TS U6325 ( .A(n4882), .B(FPMULT_Sgf_normalized_result[8]), .Y(n4869)
);
XOR2X1TS U6326 ( .A(n4869), .B(n5847), .Y(n4870) );
INVX2TS U6327 ( .A(n4871), .Y(n4885) );
INVX2TS U6328 ( .A(n4884), .Y(n4872) );
AOI21X1TS U6329 ( .A0(n4887), .A1(n4885), .B0(n4872), .Y(n4877) );
NAND2X1TS U6330 ( .A(n4875), .B(n4874), .Y(n4876) );
XOR2X1TS U6331 ( .A(n4877), .B(n4876), .Y(n4878) );
AOI22X1TS U6332 ( .A0(n2310), .A1(FPMULT_Add_result[10]), .B0(
FPMULT_Sgf_normalized_result[9]), .B1(n4985), .Y(n4879) );
OAI2BB1X1TS U6333 ( .A0N(n2451), .A1N(FPMULT_P_Sgf[33]), .B0(n4879), .Y(
n4880) );
AOI21X1TS U6334 ( .A0(n2410), .A1(FPMULT_Add_result[9]), .B0(n4880), .Y(
n4881) );
OAI2BB1X1TS U6335 ( .A0N(n2414), .A1N(FPMULT_P_Sgf[32]), .B0(n4881), .Y(
n1514) );
XNOR2X1TS U6336 ( .A(n4882), .B(n5825), .Y(n4883) );
NAND2X1TS U6337 ( .A(n4885), .B(n4884), .Y(n4886) );
XNOR2X1TS U6338 ( .A(n4887), .B(n4886), .Y(n4888) );
AOI22X1TS U6339 ( .A0(n2310), .A1(FPMULT_Add_result[9]), .B0(
FPMULT_Sgf_normalized_result[8]), .B1(n4985), .Y(n4889) );
OAI2BB1X1TS U6340 ( .A0N(n2449), .A1N(FPMULT_P_Sgf[32]), .B0(n4889), .Y(
n4890) );
AOI21X1TS U6341 ( .A0(n2409), .A1(FPMULT_Add_result[8]), .B0(n4890), .Y(
n4891) );
OAI2BB1X1TS U6342 ( .A0N(n2413), .A1N(FPMULT_P_Sgf[31]), .B0(n4891), .Y(
n1513) );
OAI21X1TS U6343 ( .A0(n4938), .A1(n5849), .B0(n4893), .Y(n4914) );
NAND2X1TS U6344 ( .A(n4914), .B(FPMULT_Sgf_normalized_result[6]), .Y(n4894)
);
XOR2X1TS U6345 ( .A(n4894), .B(n5939), .Y(n4895) );
OAI21X2TS U6346 ( .A0(n4993), .A1(n4898), .B0(n4897), .Y(n4928) );
INVX2TS U6347 ( .A(n4928), .Y(n4943) );
INVX2TS U6348 ( .A(n4899), .Y(n4902) );
INVX2TS U6349 ( .A(n4900), .Y(n4901) );
OAI21X2TS U6350 ( .A0(n4943), .A1(n4902), .B0(n4901), .Y(n4919) );
INVX2TS U6351 ( .A(n4903), .Y(n4917) );
INVX2TS U6352 ( .A(n4916), .Y(n4904) );
AOI21X1TS U6353 ( .A0(n4919), .A1(n4917), .B0(n4904), .Y(n4909) );
INVX2TS U6354 ( .A(n4905), .Y(n4907) );
NAND2X1TS U6355 ( .A(n4907), .B(n4906), .Y(n4908) );
XOR2X1TS U6356 ( .A(n4909), .B(n4908), .Y(n4910) );
AOI22X1TS U6357 ( .A0(n4744), .A1(FPMULT_Add_result[8]), .B0(
FPMULT_Sgf_normalized_result[7]), .B1(n4985), .Y(n4911) );
OAI2BB1X1TS U6358 ( .A0N(n2450), .A1N(FPMULT_P_Sgf[31]), .B0(n4911), .Y(
n4912) );
AOI21X1TS U6359 ( .A0(n2410), .A1(FPMULT_Add_result[7]), .B0(n4912), .Y(
n4913) );
OAI2BB1X1TS U6360 ( .A0N(n2414), .A1N(FPMULT_P_Sgf[30]), .B0(n4913), .Y(
n1512) );
XNOR2X1TS U6361 ( .A(n4914), .B(n5899), .Y(n4915) );
NAND2X1TS U6362 ( .A(n4917), .B(n4916), .Y(n4918) );
XNOR2X1TS U6363 ( .A(n4919), .B(n4918), .Y(n4920) );
AOI22X1TS U6364 ( .A0(n2310), .A1(FPMULT_Add_result[7]), .B0(
FPMULT_Sgf_normalized_result[6]), .B1(n4985), .Y(n4921) );
OAI2BB1X1TS U6365 ( .A0N(n2451), .A1N(FPMULT_P_Sgf[30]), .B0(n4921), .Y(
n4922) );
AOI21X1TS U6366 ( .A0(n2409), .A1(FPMULT_Add_result[6]), .B0(n4922), .Y(
n4923) );
OAI2BB1X1TS U6367 ( .A0N(n2413), .A1N(FPMULT_P_Sgf[29]), .B0(n4923), .Y(
n1511) );
NAND2X1TS U6368 ( .A(n4938), .B(n5898), .Y(n4924) );
XNOR2X1TS U6369 ( .A(n4924), .B(n5849), .Y(n4925) );
INVX2TS U6370 ( .A(n4926), .Y(n4941) );
INVX2TS U6371 ( .A(n4940), .Y(n4927) );
AOI21X1TS U6372 ( .A0(n4928), .A1(n4941), .B0(n4927), .Y(n4933) );
INVX2TS U6373 ( .A(n4929), .Y(n4931) );
NAND2X1TS U6374 ( .A(n4931), .B(n4930), .Y(n4932) );
XOR2X1TS U6375 ( .A(n4933), .B(n4932), .Y(n4934) );
AOI22X1TS U6376 ( .A0(n4744), .A1(FPMULT_Add_result[6]), .B0(
FPMULT_Sgf_normalized_result[5]), .B1(n4985), .Y(n4935) );
OAI2BB1X1TS U6377 ( .A0N(n2449), .A1N(FPMULT_P_Sgf[29]), .B0(n4935), .Y(
n4936) );
AOI21X1TS U6378 ( .A0(n2410), .A1(FPMULT_Add_result[5]), .B0(n4936), .Y(
n4937) );
OAI2BB1X1TS U6379 ( .A0N(n2414), .A1N(FPMULT_P_Sgf[28]), .B0(n4937), .Y(
n1510) );
XOR2X1TS U6380 ( .A(n4938), .B(FPMULT_Sgf_normalized_result[4]), .Y(n4939)
);
NAND2X1TS U6381 ( .A(n4941), .B(n4940), .Y(n4942) );
XOR2X1TS U6382 ( .A(n4943), .B(n4942), .Y(n4944) );
AOI22X1TS U6383 ( .A0(n2310), .A1(FPMULT_Add_result[5]), .B0(
FPMULT_Sgf_normalized_result[4]), .B1(n4985), .Y(n4945) );
OAI2BB1X1TS U6384 ( .A0N(n2450), .A1N(FPMULT_P_Sgf[28]), .B0(n4945), .Y(
n4946) );
AOI21X1TS U6385 ( .A0(n2409), .A1(FPMULT_Add_result[4]), .B0(n4946), .Y(
n4947) );
OAI2BB1X1TS U6386 ( .A0N(n2413), .A1N(FPMULT_P_Sgf[27]), .B0(n4947), .Y(
n1509) );
XOR2X1TS U6387 ( .A(n4949), .B(n5845), .Y(n4950) );
INVX2TS U6388 ( .A(n4951), .Y(n4954) );
INVX2TS U6389 ( .A(n4952), .Y(n4953) );
OAI21X1TS U6390 ( .A0(n4993), .A1(n4954), .B0(n4953), .Y(n4972) );
INVX2TS U6391 ( .A(n4955), .Y(n4970) );
INVX2TS U6392 ( .A(n4969), .Y(n4956) );
AOI21X1TS U6393 ( .A0(n4972), .A1(n4970), .B0(n4956), .Y(n4961) );
NAND2X1TS U6394 ( .A(n4959), .B(n4958), .Y(n4960) );
XOR2X1TS U6395 ( .A(n4961), .B(n4960), .Y(n4963) );
AOI22X1TS U6396 ( .A0(n2309), .A1(FPMULT_Add_result[4]), .B0(
FPMULT_Sgf_normalized_result[3]), .B1(n4985), .Y(n4964) );
OAI2BB1X1TS U6397 ( .A0N(n2451), .A1N(FPMULT_P_Sgf[27]), .B0(n4964), .Y(
n4965) );
AOI21X1TS U6398 ( .A0(n2410), .A1(FPMULT_Add_result[3]), .B0(n4965), .Y(
n4966) );
OAI2BB1X1TS U6399 ( .A0N(n2414), .A1N(FPMULT_P_Sgf[26]), .B0(n4966), .Y(
n1508) );
XOR2X1TS U6400 ( .A(n4967), .B(FPMULT_Sgf_normalized_result[2]), .Y(n4968)
);
NAND2X1TS U6401 ( .A(n4970), .B(n4969), .Y(n4971) );
XNOR2X1TS U6402 ( .A(n4972), .B(n4971), .Y(n4973) );
BUFX3TS U6403 ( .A(n5377), .Y(n5427) );
AOI22X1TS U6404 ( .A0(n2309), .A1(FPMULT_Add_result[3]), .B0(
FPMULT_Sgf_normalized_result[2]), .B1(n4985), .Y(n4974) );
OAI2BB1X1TS U6405 ( .A0N(n2450), .A1N(FPMULT_P_Sgf[26]), .B0(n4974), .Y(
n4975) );
AOI21X1TS U6406 ( .A0(n2408), .A1(FPMULT_Add_result[2]), .B0(n4975), .Y(
n4976) );
OAI2BB1X1TS U6407 ( .A0N(n2412), .A1N(FPMULT_P_Sgf[25]), .B0(n4976), .Y(
n1507) );
XNOR2X1TS U6408 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n4978) );
INVX2TS U6409 ( .A(n4979), .Y(n4981) );
NAND2X1TS U6410 ( .A(n4981), .B(n4980), .Y(n4982) );
XNOR2X1TS U6411 ( .A(n4983), .B(n4982), .Y(n4984) );
AOI22X1TS U6412 ( .A0(n2309), .A1(FPMULT_Add_result[2]), .B0(
FPMULT_Sgf_normalized_result[1]), .B1(n4985), .Y(n4986) );
OAI2BB1X1TS U6413 ( .A0N(n2451), .A1N(FPMULT_P_Sgf[25]), .B0(n4986), .Y(
n4987) );
AOI21X1TS U6414 ( .A0(n2409), .A1(FPMULT_Add_result[1]), .B0(n4987), .Y(
n4988) );
OAI2BB1X1TS U6415 ( .A0N(n2413), .A1N(FPMULT_P_Sgf[24]), .B0(n4988), .Y(
n1506) );
INVX2TS U6416 ( .A(n4989), .Y(n4991) );
NAND2X1TS U6417 ( .A(n4991), .B(n4990), .Y(n4992) );
XOR2X1TS U6418 ( .A(n4993), .B(n4992), .Y(n4994) );
AOI22X1TS U6419 ( .A0(n2309), .A1(FPMULT_Add_result[1]), .B0(
FPMULT_Sgf_normalized_result[0]), .B1(n4995), .Y(n4996) );
OAI2BB1X1TS U6420 ( .A0N(n2449), .A1N(FPMULT_P_Sgf[24]), .B0(n4996), .Y(
n4998) );
AOI21X1TS U6421 ( .A0(n2408), .A1(FPMULT_Add_result[0]), .B0(n4998), .Y(
n4999) );
OAI2BB1X1TS U6422 ( .A0N(FPMULT_P_Sgf[23]), .A1N(n2414), .B0(n4999), .Y(
n1505) );
ADDHXLTS U6423 ( .A(FPMULT_Sgf_normalized_result[23]), .B(n5000), .CO(n5002),
.S(n4724) );
XOR2X4TS U6424 ( .A(n5005), .B(n5004), .Y(n5006) );
AOI22X1TS U6425 ( .A0(n5009), .A1(n5008), .B0(n5858), .B1(n5819), .Y(n5012)
);
AOI21X1TS U6426 ( .A0(n5012), .A1(n5011), .B0(n5010), .Y(n1692) );
NAND2X1TS U6427 ( .A(n5690), .B(n5900), .Y(n1689) );
XNOR2X1TS U6428 ( .A(DP_OP_234J16_127_8543_n1), .B(n5015), .Y(n5016) );
BUFX3TS U6429 ( .A(n5018), .Y(n5721) );
BUFX3TS U6430 ( .A(n5018), .Y(n5019) );
AOI211X1TS U6431 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5022), .B0(n5057),
.C0(n5021), .Y(n5728) );
MXI2X1TS U6432 ( .A(n5728), .B(n5930), .S0(n5787), .Y(n1181) );
OAI21X1TS U6433 ( .A0(n5866), .A1(n5036), .B0(n5035), .Y(n5023) );
AOI22X1TS U6434 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n2352), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n2382), .Y(n5025) );
AOI22X1TS U6435 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2303), .B0(
FPADDSUB_Data_array_SWR[6]), .B1(n2384), .Y(n5024) );
OAI211X1TS U6436 ( .A0(n5086), .A1(n2323), .B0(n5025), .C0(n5024), .Y(n5106)
);
AOI21X2TS U6437 ( .A0(n2294), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n5030),
.Y(n5102) );
AOI211X1TS U6438 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5106), .B0(n5057),
.C0(n5026), .Y(n5731) );
MXI2X1TS U6439 ( .A(n5731), .B(n5918), .S0(n5718), .Y(n1182) );
OAI21X1TS U6440 ( .A0(n5867), .A1(n5036), .B0(n5035), .Y(n5027) );
AOI22X1TS U6441 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n2352), .B0(
FPADDSUB_Data_array_SWR[3]), .B1(n2382), .Y(n5029) );
AOI22X1TS U6442 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n2303), .B0(
FPADDSUB_Data_array_SWR[7]), .B1(n2384), .Y(n5028) );
OAI211X1TS U6443 ( .A0(n5089), .A1(n2323), .B0(n5029), .C0(n5028), .Y(n5100)
);
AOI21X2TS U6444 ( .A0(n2294), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n5030),
.Y(n5098) );
AOI211X1TS U6445 ( .A0(n2400), .A1(n5100), .B0(n5057), .C0(n5031), .Y(n5734)
);
BUFX3TS U6446 ( .A(n5787), .Y(n5720) );
MXI2X1TS U6447 ( .A(n5734), .B(n5931), .S0(n5720), .Y(n1183) );
OAI21X1TS U6448 ( .A0(n5870), .A1(n5036), .B0(n5035), .Y(n5032) );
AOI21X2TS U6449 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2293), .B0(n5032),
.Y(n5092) );
AOI22X1TS U6450 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2352), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n2382), .Y(n5034) );
AOI22X1TS U6451 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2303), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n2384), .Y(n5033) );
OAI211X1TS U6452 ( .A0(n5092), .A1(n2322), .B0(n5034), .C0(n5033), .Y(n5097)
);
OAI21X1TS U6453 ( .A0(n5868), .A1(n5036), .B0(n5035), .Y(n5037) );
AOI21X2TS U6454 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2294), .B0(n5037),
.Y(n5095) );
AOI211X1TS U6455 ( .A0(n5105), .A1(n5097), .B0(n5057), .C0(n5038), .Y(n5732)
);
MXI2X1TS U6456 ( .A(n5732), .B(n5919), .S0(n5720), .Y(n1184) );
AOI22X1TS U6457 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2353), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n2383), .Y(n5040) );
AOI22X1TS U6458 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n2303), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n2384), .Y(n5039) );
OAI211X1TS U6459 ( .A0(n5095), .A1(n2254), .B0(n5040), .C0(n5039), .Y(n5094)
);
AOI211X1TS U6460 ( .A0(n2400), .A1(n5094), .B0(n5057), .C0(n5041), .Y(n5730)
);
MXI2X1TS U6461 ( .A(n5730), .B(n5932), .S0(n5718), .Y(n1185) );
AOI22X1TS U6462 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n3673), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n2385), .Y(n5043) );
AOI22X1TS U6463 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2352), .B0(
FPADDSUB_Data_array_SWR[6]), .B1(n2382), .Y(n5042) );
OAI211X1TS U6464 ( .A0(n5098), .A1(n2323), .B0(n5043), .C0(n5042), .Y(n5091)
);
AOI211X1TS U6465 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5091), .B0(n5057),
.C0(n5044), .Y(n5735) );
MXI2X1TS U6466 ( .A(n5735), .B(n5920), .S0(n5720), .Y(n1186) );
AOI22X1TS U6467 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2303), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2384), .Y(n5046) );
AOI22X1TS U6468 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n2352), .B0(
FPADDSUB_Data_array_SWR[7]), .B1(n2382), .Y(n5045) );
OAI211X1TS U6469 ( .A0(n5102), .A1(n2323), .B0(n5046), .C0(n5045), .Y(n5088)
);
AOI211X1TS U6470 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5088), .B0(n5057),
.C0(n5047), .Y(n5742) );
MXI2X1TS U6471 ( .A(n5742), .B(n5933), .S0(n5720), .Y(n1187) );
AOI22X1TS U6472 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n3673), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n2384), .Y(n5049) );
AOI22X1TS U6473 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2352), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n2382), .Y(n5048) );
OAI211X1TS U6474 ( .A0(n5050), .A1(n2323), .B0(n5049), .C0(n5048), .Y(n5085)
);
AOI211X1TS U6475 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5085), .B0(n5057),
.C0(n5051), .Y(n5729) );
MXI2X1TS U6476 ( .A(n5729), .B(n5921), .S0(n5718), .Y(n1188) );
AOI22X1TS U6477 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2303), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n2384), .Y(n5053) );
AOI22X1TS U6478 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n2352), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n2382), .Y(n5052) );
OAI211X1TS U6479 ( .A0(n5054), .A1(n2323), .B0(n5053), .C0(n5052), .Y(n5081)
);
AOI211X1TS U6480 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5081), .B0(n5057),
.C0(n5056), .Y(n5745) );
MXI2X1TS U6481 ( .A(n5745), .B(n5934), .S0(n5720), .Y(n1189) );
AOI21X1TS U6482 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2385), .B0(n5071),
.Y(n5059) );
AOI22X1TS U6483 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n2353), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n2383), .Y(n5058) );
OAI211X1TS U6484 ( .A0(n5866), .A1(n5064), .B0(n5059), .C0(n5058), .Y(n5076)
);
NOR2X1TS U6485 ( .A(n5071), .B(n5060), .Y(n5066) );
AOI22X1TS U6486 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2385), .B0(
FPADDSUB_Data_array_SWR[15]), .B1(n2383), .Y(n5061) );
OAI211X1TS U6487 ( .A0(n5867), .A1(n3671), .B0(n5066), .C0(n5061), .Y(n5077)
);
AOI22X1TS U6488 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5076), .B0(n5077),
.B1(n2204), .Y(n5739) );
MXI2X1TS U6489 ( .A(n5739), .B(n5922), .S0(n5718), .Y(n1190) );
AOI21X1TS U6490 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n2385), .B0(n5071),
.Y(n5063) );
AOI22X1TS U6491 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2353), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2383), .Y(n5062) );
OAI211X1TS U6492 ( .A0(n5867), .A1(n5064), .B0(n5063), .C0(n5062), .Y(n5074)
);
AOI22X1TS U6493 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n2385), .B0(
FPADDSUB_Data_array_SWR[14]), .B1(n2383), .Y(n5065) );
OAI211X1TS U6494 ( .A0(n5866), .A1(n3671), .B0(n5066), .C0(n5065), .Y(n5075)
);
AOI22X1TS U6495 ( .A0(n2400), .A1(n5074), .B0(n5075), .B1(n2447), .Y(n5748)
);
MXI2X1TS U6496 ( .A(n5748), .B(n5935), .S0(n5720), .Y(n1191) );
AOI22X1TS U6497 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2353), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n2383), .Y(n5068) );
AOI22X1TS U6498 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2385), .B0(
FPADDSUB_Data_array_SWR[24]), .B1(n3673), .Y(n5067) );
AOI22X1TS U6499 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2353), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n2383), .Y(n5070) );
AOI22X1TS U6500 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n2385), .B0(
FPADDSUB_Data_array_SWR[25]), .B1(n3673), .Y(n5069) );
AOI221X1TS U6501 ( .A0(n2400), .A1(n5072), .B0(n2204), .B1(n5073), .C0(n5071), .Y(n5744) );
MXI2X1TS U6502 ( .A(n5744), .B(n5923), .S0(n5718), .Y(n1192) );
AOI221X1TS U6503 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5073), .B0(n2447),
.B1(n5072), .C0(n5071), .Y(n5746) );
MXI2X1TS U6504 ( .A(n5746), .B(n5924), .S0(n5718), .Y(n1193) );
AOI22X1TS U6505 ( .A0(n5105), .A1(n5075), .B0(n5074), .B1(n2447), .Y(n5799)
);
MXI2X1TS U6506 ( .A(n5799), .B(n5936), .S0(n5720), .Y(n1194) );
AOI22X1TS U6507 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5077), .B0(n5076),
.B1(n2204), .Y(n5743) );
MXI2X1TS U6508 ( .A(n5743), .B(n5914), .S0(n5718), .Y(n1195) );
AOI211X1TS U6509 ( .A0(n5081), .A1(n2447), .B0(n5080), .C0(n5103), .Y(n5795)
);
MXI2X1TS U6510 ( .A(n5795), .B(n5925), .S0(n5082), .Y(n1196) );
AOI211X1TS U6511 ( .A0(n5085), .A1(n2204), .B0(n5084), .C0(n5103), .Y(n5738)
);
MXI2X1TS U6512 ( .A(n5738), .B(n5915), .S0(n5082), .Y(n1197) );
AOI211X1TS U6513 ( .A0(n5088), .A1(n2447), .B0(n5087), .C0(n5103), .Y(n5801)
);
MXI2X1TS U6514 ( .A(n5801), .B(n5926), .S0(n5082), .Y(n1198) );
AOI211X1TS U6515 ( .A0(n5091), .A1(n2204), .B0(n5090), .C0(n5103), .Y(n5736)
);
MXI2X1TS U6516 ( .A(n5736), .B(n5916), .S0(n5082), .Y(n1199) );
AOI211X1TS U6517 ( .A0(n5094), .A1(n2447), .B0(n5093), .C0(n5103), .Y(n5792)
);
MXI2X1TS U6518 ( .A(n5792), .B(n5927), .S0(n5082), .Y(n1200) );
AOI211X1TS U6519 ( .A0(n5097), .A1(n2204), .B0(n5096), .C0(n5103), .Y(n5793)
);
MXI2X1TS U6520 ( .A(n5793), .B(n5917), .S0(n5082), .Y(n1201) );
AOI211X1TS U6521 ( .A0(n5100), .A1(n2447), .B0(n5099), .C0(n5103), .Y(n5798)
);
MXI2X1TS U6522 ( .A(n5798), .B(n5928), .S0(n5082), .Y(n1202) );
AOI211X1TS U6523 ( .A0(n5106), .A1(n2204), .B0(n5104), .C0(n5103), .Y(n5797)
);
MXI2X1TS U6524 ( .A(n5797), .B(n5929), .S0(n5082), .Y(n1203) );
OAI22X1TS U6525 ( .A0(FPMULT_Exp_module_Data_S[8]), .A1(n5113), .B0(n5112),
.B1(n5937), .Y(n1586) );
OAI22X1TS U6526 ( .A0(n5115), .A1(n5114), .B0(n5802), .B1(n5913), .Y(n1466)
);
OR4X2TS U6527 ( .A(n5702), .B(FPMULT_Exp_module_Overflow_flag_A), .C(
FPMULT_exp_oper_result[8]), .D(underflow_flag_mult), .Y(n5692) );
INVX2TS U6528 ( .A(n5698), .Y(n5704) );
BUFX3TS U6529 ( .A(n5253), .Y(n5252) );
NOR2X1TS U6530 ( .A(n5915), .B(FPADDSUB_DMP_SFG[6]), .Y(n5122) );
NOR2X1TS U6531 ( .A(n5118), .B(n5122), .Y(n5124) );
NAND2X1TS U6532 ( .A(n5119), .B(n5124), .Y(n5127) );
NAND2X1TS U6533 ( .A(n5915), .B(FPADDSUB_DMP_SFG[6]), .Y(n5120) );
AOI21X1TS U6534 ( .A0(n5125), .A1(n5124), .B0(n5123), .Y(n5126) );
OAI21X2TS U6535 ( .A0(n5128), .A1(n5127), .B0(n5126), .Y(n5282) );
NOR2X1TS U6536 ( .A(n5925), .B(FPADDSUB_DMP_SFG[7]), .Y(n5300) );
NOR2X1TS U6537 ( .A(n5914), .B(FPADDSUB_DMP_SFG[8]), .Y(n5130) );
NOR2X1TS U6538 ( .A(n5300), .B(n5130), .Y(n5283) );
NAND2X1TS U6539 ( .A(n5283), .B(n5132), .Y(n5329) );
NOR2X1TS U6540 ( .A(n5924), .B(FPADDSUB_DMP_SFG[10]), .Y(n5134) );
NOR2X1TS U6541 ( .A(n5329), .B(n5134), .Y(n5136) );
NAND2X1TS U6542 ( .A(n5925), .B(FPADDSUB_DMP_SFG[7]), .Y(n5299) );
NAND2X1TS U6543 ( .A(n5914), .B(FPADDSUB_DMP_SFG[8]), .Y(n5129) );
OAI21X1TS U6544 ( .A0(n5130), .A1(n5299), .B0(n5129), .Y(n5284) );
AOI21X1TS U6545 ( .A0(n5284), .A1(n5132), .B0(n5131), .Y(n5328) );
NAND2X1TS U6546 ( .A(n5924), .B(FPADDSUB_DMP_SFG[10]), .Y(n5133) );
OAI21X1TS U6547 ( .A0(n5328), .A1(n5134), .B0(n5133), .Y(n5135) );
NOR2X1TS U6548 ( .A(n5923), .B(FPADDSUB_DMP_SFG[11]), .Y(n5138) );
NAND2X1TS U6549 ( .A(n5923), .B(FPADDSUB_DMP_SFG[11]), .Y(n5137) );
OR2X1TS U6550 ( .A(n5935), .B(FPADDSUB_DMP_SFG[12]), .Y(n5140) );
AOI21X4TS U6551 ( .A0(n5266), .A1(n5140), .B0(n5139), .Y(n5152) );
NAND2X1TS U6552 ( .A(n5143), .B(n5142), .Y(n5145) );
INVX2TS U6553 ( .A(n5145), .Y(n5144) );
XOR2X1TS U6554 ( .A(n5146), .B(n5145), .Y(n5147) );
AOI22X1TS U6555 ( .A0(n5147), .A1(n4049), .B0(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B1(n2304), .Y(n5148) );
OAI2BB1X1TS U6556 ( .A0N(n5252), .A1N(n5149), .B0(n5148), .Y(n1334) );
NAND2X1TS U6557 ( .A(n5922), .B(FPADDSUB_DMP_SFG[13]), .Y(n5150) );
NAND2X1TS U6558 ( .A(n5154), .B(n5153), .Y(n5156) );
INVX2TS U6559 ( .A(n5156), .Y(n5155) );
XNOR2X1TS U6560 ( .A(n5163), .B(n5155), .Y(n5160) );
XNOR2X1TS U6561 ( .A(n5157), .B(n5156), .Y(n5158) );
AOI22X1TS U6562 ( .A0(n5158), .A1(n4049), .B0(FPADDSUB_Raw_mant_NRM_SWR[16]),
.B1(n5715), .Y(n5159) );
OAI2BB1X1TS U6563 ( .A0N(n5252), .A1N(n5160), .B0(n5159), .Y(n1333) );
INVX2TS U6564 ( .A(n5164), .Y(n5166) );
NAND2X1TS U6565 ( .A(n5166), .B(n5165), .Y(n5168) );
INVX2TS U6566 ( .A(n5168), .Y(n5167) );
XOR2X1TS U6567 ( .A(n5169), .B(n5168), .Y(n5170) );
AOI22X1TS U6568 ( .A0(n5170), .A1(n4049), .B0(FPADDSUB_Raw_mant_NRM_SWR[17]),
.B1(n5715), .Y(n5171) );
OAI2BB1X1TS U6569 ( .A0N(n5252), .A1N(n5172), .B0(n5171), .Y(n1332) );
NOR2X1TS U6570 ( .A(n5921), .B(FPADDSUB_DMP_SFG[15]), .Y(n5174) );
NAND2X1TS U6571 ( .A(n5921), .B(FPADDSUB_DMP_SFG[15]), .Y(n5173) );
OAI21X4TS U6572 ( .A0(n5175), .A1(n5174), .B0(n5173), .Y(n5257) );
NAND2X1TS U6573 ( .A(n5920), .B(FPADDSUB_DMP_SFG[17]), .Y(n5178) );
NOR2X1TS U6574 ( .A(n5919), .B(FPADDSUB_DMP_SFG[19]), .Y(n5183) );
NAND2X1TS U6575 ( .A(n5919), .B(FPADDSUB_DMP_SFG[19]), .Y(n5182) );
OAI21X4TS U6576 ( .A0(n5246), .A1(n5183), .B0(n5182), .Y(n5217) );
OR2X1TS U6577 ( .A(n5931), .B(FPADDSUB_DMP_SFG[20]), .Y(n5185) );
AOI21X2TS U6578 ( .A0(n5217), .A1(n5185), .B0(n5184), .Y(n5208) );
NAND2X1TS U6579 ( .A(n5918), .B(FPADDSUB_DMP_SFG[21]), .Y(n5186) );
OAI21X4TS U6580 ( .A0(n5208), .A1(n5187), .B0(n5186), .Y(n5198) );
OR2X1TS U6581 ( .A(n5930), .B(FPADDSUB_DMP_SFG[22]), .Y(n5189) );
CLKAND2X2TS U6582 ( .A(n5930), .B(FPADDSUB_DMP_SFG[22]), .Y(n5188) );
AOI21X1TS U6583 ( .A0(n5198), .A1(n5189), .B0(n5188), .Y(n5190) );
XOR2X1TS U6584 ( .A(n5191), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n5192) );
NAND2X1TS U6585 ( .A(n5196), .B(n5195), .Y(n5199) );
INVX2TS U6586 ( .A(n5199), .Y(n5197) );
XNOR2X1TS U6587 ( .A(n5198), .B(n5197), .Y(n5203) );
XNOR2X1TS U6588 ( .A(n5200), .B(n5199), .Y(n5201) );
AOI22X1TS U6589 ( .A0(n5201), .A1(n4049), .B0(FPADDSUB_Raw_mant_NRM_SWR[24]),
.B1(n5107), .Y(n5202) );
OAI2BB1X1TS U6590 ( .A0N(n5252), .A1N(n5203), .B0(n5202), .Y(n1315) );
INVX2TS U6591 ( .A(n5204), .Y(n5206) );
NAND2X1TS U6592 ( .A(n5206), .B(n5205), .Y(n5209) );
INVX2TS U6593 ( .A(n5209), .Y(n5207) );
XOR2X1TS U6594 ( .A(n5210), .B(n5209), .Y(n5211) );
AOI22X1TS U6595 ( .A0(n5211), .A1(n5295), .B0(FPADDSUB_Raw_mant_NRM_SWR[23]),
.B1(n5107), .Y(n5212) );
OAI2BB1X1TS U6596 ( .A0N(n5252), .A1N(n5213), .B0(n5212), .Y(n1316) );
NAND2X1TS U6597 ( .A(n5215), .B(n5214), .Y(n5218) );
INVX2TS U6598 ( .A(n5218), .Y(n5216) );
XNOR2X1TS U6599 ( .A(n5217), .B(n5216), .Y(n5222) );
XNOR2X1TS U6600 ( .A(n5219), .B(n5218), .Y(n5220) );
BUFX3TS U6601 ( .A(n5715), .Y(n5316) );
AOI22X1TS U6602 ( .A0(n5220), .A1(n5295), .B0(FPADDSUB_Raw_mant_NRM_SWR[22]),
.B1(n5316), .Y(n5221) );
OAI2BB1X1TS U6603 ( .A0N(n5252), .A1N(n5222), .B0(n5221), .Y(n1317) );
INVX2TS U6604 ( .A(n5223), .Y(n5225) );
NAND2X1TS U6605 ( .A(n5225), .B(n5224), .Y(n5228) );
INVX2TS U6606 ( .A(n5228), .Y(n5226) );
XOR2X1TS U6607 ( .A(n5229), .B(n5228), .Y(n5230) );
AOI22X1TS U6608 ( .A0(n5230), .A1(n5295), .B0(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B1(n5316), .Y(n5231) );
OAI2BB1X1TS U6609 ( .A0N(n5252), .A1N(n5232), .B0(n5231), .Y(n1321) );
NAND2X1TS U6610 ( .A(n5234), .B(n5233), .Y(n5237) );
INVX2TS U6611 ( .A(n5237), .Y(n5235) );
XNOR2X1TS U6612 ( .A(n5236), .B(n5235), .Y(n5241) );
XNOR2X1TS U6613 ( .A(n5238), .B(n5237), .Y(n5239) );
AOI22X1TS U6614 ( .A0(n5239), .A1(n5295), .B0(FPADDSUB_Raw_mant_NRM_SWR[20]),
.B1(n5316), .Y(n5240) );
OAI2BB1X1TS U6615 ( .A0N(n5252), .A1N(n5241), .B0(n5240), .Y(n1320) );
INVX2TS U6616 ( .A(n5242), .Y(n5244) );
NAND2X1TS U6617 ( .A(n5244), .B(n5243), .Y(n5247) );
INVX2TS U6618 ( .A(n5247), .Y(n5245) );
XOR2X1TS U6619 ( .A(n5248), .B(n5247), .Y(n5249) );
AOI22X1TS U6620 ( .A0(n5249), .A1(n5295), .B0(FPADDSUB_Raw_mant_NRM_SWR[21]),
.B1(n5316), .Y(n5250) );
OAI2BB1X1TS U6621 ( .A0N(n5252), .A1N(n5251), .B0(n5250), .Y(n1319) );
BUFX3TS U6622 ( .A(n5253), .Y(n5358) );
NAND2X1TS U6623 ( .A(n5255), .B(n5254), .Y(n5258) );
INVX2TS U6624 ( .A(n5258), .Y(n5256) );
XNOR2X1TS U6625 ( .A(n5257), .B(n5256), .Y(n5262) );
XNOR2X1TS U6626 ( .A(n5259), .B(n5258), .Y(n5260) );
AOI22X1TS U6627 ( .A0(n5260), .A1(n5295), .B0(FPADDSUB_Raw_mant_NRM_SWR[18]),
.B1(n5316), .Y(n5261) );
OAI2BB1X1TS U6628 ( .A0N(n5358), .A1N(n5262), .B0(n5261), .Y(n1331) );
NAND2X1TS U6629 ( .A(n5264), .B(n5263), .Y(n5267) );
INVX2TS U6630 ( .A(n5267), .Y(n5265) );
XNOR2X1TS U6631 ( .A(n5266), .B(n5265), .Y(n5271) );
XNOR2X1TS U6632 ( .A(n5268), .B(n5267), .Y(n5269) );
AOI22X1TS U6633 ( .A0(n5269), .A1(n5295), .B0(FPADDSUB_Raw_mant_NRM_SWR[14]),
.B1(n5316), .Y(n5270) );
OAI2BB1X1TS U6634 ( .A0N(n5358), .A1N(n5271), .B0(n5270), .Y(n1335) );
NAND2X1TS U6635 ( .A(n5274), .B(n5273), .Y(n5277) );
INVX2TS U6636 ( .A(n5277), .Y(n5275) );
XOR2X1TS U6637 ( .A(n5278), .B(n5277), .Y(n5279) );
AOI22X1TS U6638 ( .A0(n5279), .A1(n5295), .B0(FPADDSUB_Raw_mant_NRM_SWR[13]),
.B1(n5316), .Y(n5280) );
OAI2BB1X1TS U6639 ( .A0N(n5358), .A1N(n5281), .B0(n5280), .Y(n1336) );
INVX2TS U6640 ( .A(n5282), .Y(n5347) );
NAND2X1TS U6641 ( .A(n5288), .B(n5287), .Y(n5293) );
INVX2TS U6642 ( .A(n5293), .Y(n5289) );
XNOR2X1TS U6643 ( .A(n5290), .B(n5289), .Y(n5298) );
XNOR2X1TS U6644 ( .A(n5294), .B(n5293), .Y(n5296) );
AOI22X1TS U6645 ( .A0(n5296), .A1(n5295), .B0(FPADDSUB_Raw_mant_NRM_SWR[11]),
.B1(n5316), .Y(n5297) );
OAI2BB1X1TS U6646 ( .A0N(n5358), .A1N(n5298), .B0(n5297), .Y(n1338) );
NAND2X1TS U6647 ( .A(n5302), .B(n5301), .Y(n5305) );
INVX2TS U6648 ( .A(n5305), .Y(n5303) );
XNOR2X1TS U6649 ( .A(n5304), .B(n5303), .Y(n5308) );
XOR2X1TS U6650 ( .A(n5337), .B(n5305), .Y(n5306) );
AOI22X1TS U6651 ( .A0(n5306), .A1(n5354), .B0(FPADDSUB_Raw_mant_NRM_SWR[10]),
.B1(n5316), .Y(n5307) );
OAI2BB1X1TS U6652 ( .A0N(n5358), .A1N(n5308), .B0(n5307), .Y(n1339) );
MXI2X1TS U6653 ( .A(n5309), .B(n5945), .S0(n5788), .Y(n1349) );
INVX2TS U6654 ( .A(n5310), .Y(n5312) );
NAND2X1TS U6655 ( .A(n5312), .B(n5311), .Y(n5315) );
INVX2TS U6656 ( .A(n5315), .Y(n5313) );
XOR2X1TS U6657 ( .A(n5315), .B(n5322), .Y(n5317) );
AOI22X1TS U6658 ( .A0(n5317), .A1(n5354), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.B1(n5316), .Y(n5318) );
OAI2BB1X1TS U6659 ( .A0N(n5358), .A1N(n5319), .B0(n5318), .Y(n1346) );
XNOR2X1TS U6660 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(n5945), .Y(n5321) );
AOI22X1TS U6661 ( .A0(n5354), .A1(FPADDSUB_DmP_mant_SFG_SWR[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n5353), .Y(n5320) );
OAI2BB1X1TS U6662 ( .A0N(n5358), .A1N(n5321), .B0(n5320), .Y(n1348) );
OR2X1TS U6663 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n5323) );
CLKAND2X2TS U6664 ( .A(n5323), .B(n5322), .Y(n5325) );
AOI22X1TS U6665 ( .A0(n5325), .A1(n5354), .B0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.B1(n5353), .Y(n5326) );
OAI2BB1X1TS U6666 ( .A0N(n5358), .A1N(n5327), .B0(n5326), .Y(n1347) );
NAND2X1TS U6667 ( .A(n5332), .B(n5331), .Y(n5338) );
INVX2TS U6668 ( .A(n5338), .Y(n5333) );
XNOR2X1TS U6669 ( .A(n5334), .B(n5333), .Y(n5342) );
XNOR2X1TS U6670 ( .A(n5339), .B(n5338), .Y(n5340) );
AOI22X1TS U6671 ( .A0(n5340), .A1(n5354), .B0(FPADDSUB_Raw_mant_NRM_SWR[12]),
.B1(n5353), .Y(n5341) );
OAI2BB1X1TS U6672 ( .A0N(n5358), .A1N(n5342), .B0(n5341), .Y(n1337) );
INVX2TS U6673 ( .A(n5343), .Y(n5345) );
NAND2X1TS U6674 ( .A(n5345), .B(n5344), .Y(n5351) );
INVX2TS U6675 ( .A(n5351), .Y(n5346) );
XNOR2X1TS U6676 ( .A(n5352), .B(n5351), .Y(n5355) );
AOI22X1TS U6677 ( .A0(n5355), .A1(n5354), .B0(FPADDSUB_Raw_mant_NRM_SWR[9]),
.B1(n5353), .Y(n5356) );
OAI2BB1X1TS U6678 ( .A0N(n5358), .A1N(n5357), .B0(n5356), .Y(n1340) );
INVX2TS U6679 ( .A(n5359), .Y(n5361) );
NAND2X1TS U6680 ( .A(n5361), .B(n5360), .Y(n5362) );
XOR2X1TS U6681 ( .A(n5362), .B(n5422), .Y(n5363) );
INVX2TS U6682 ( .A(n5364), .Y(n5390) );
INVX2TS U6683 ( .A(n5389), .Y(n5365) );
NAND2X1TS U6684 ( .A(n5365), .B(n5388), .Y(n5366) );
XOR2X1TS U6685 ( .A(n5390), .B(n5366), .Y(n5367) );
INVX2TS U6686 ( .A(n5368), .Y(n5373) );
NAND2X1TS U6687 ( .A(n2453), .B(n5369), .Y(n5370) );
XNOR2X1TS U6688 ( .A(n5373), .B(n5370), .Y(n5371) );
AOI21X1TS U6689 ( .A0(n5373), .A1(n2453), .B0(n5372), .Y(n5376) );
NAND2X1TS U6690 ( .A(n2454), .B(n5374), .Y(n5375) );
XOR2X1TS U6691 ( .A(n5376), .B(n5375), .Y(n5378) );
BUFX3TS U6692 ( .A(n5377), .Y(n5424) );
INVX2TS U6693 ( .A(n5379), .Y(n5403) );
INVX2TS U6694 ( .A(n5380), .Y(n5398) );
INVX2TS U6695 ( .A(n5397), .Y(n5381) );
AOI21X1TS U6696 ( .A0(n5403), .A1(n5398), .B0(n5381), .Y(n5386) );
INVX2TS U6697 ( .A(n5382), .Y(n5384) );
NAND2X1TS U6698 ( .A(n5384), .B(n5383), .Y(n5385) );
XOR2X1TS U6699 ( .A(n5386), .B(n5385), .Y(n5387) );
INVX2TS U6700 ( .A(n5391), .Y(n5393) );
NAND2X1TS U6701 ( .A(n5393), .B(n5392), .Y(n5394) );
XNOR2X1TS U6702 ( .A(n5395), .B(n5394), .Y(n5396) );
NAND2X1TS U6703 ( .A(n5398), .B(n5397), .Y(n5399) );
XNOR2X1TS U6704 ( .A(n5403), .B(n5399), .Y(n5400) );
AOI21X1TS U6705 ( .A0(n5403), .A1(n5402), .B0(n5401), .Y(n5409) );
INVX2TS U6706 ( .A(n5408), .Y(n5404) );
NAND2X1TS U6707 ( .A(n5404), .B(n5407), .Y(n5405) );
XOR2X1TS U6708 ( .A(n5409), .B(n5405), .Y(n5406) );
NAND2X1TS U6709 ( .A(n5412), .B(n5411), .Y(n5413) );
XNOR2X1TS U6710 ( .A(n5414), .B(n5413), .Y(n5415) );
NAND2X1TS U6711 ( .A(n2497), .B(n5417), .Y(n5419) );
XNOR2X1TS U6712 ( .A(n5419), .B(n5418), .Y(n5420) );
OR2X1TS U6713 ( .A(n5421), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(n5423) );
CLKAND2X2TS U6714 ( .A(n5423), .B(n5422), .Y(n5425) );
NOR4X1TS U6715 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n5434) );
NOR4X1TS U6716 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n5433) );
NOR4X1TS U6717 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n5431) );
NOR4X1TS U6718 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n5429) );
NOR4X1TS U6719 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n5428) );
AND4X1TS U6720 ( .A(n5431), .B(n5430), .C(n5429), .D(n5428), .Y(n5432) );
NOR4BX1TS U6721 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n5439) );
NOR4X1TS U6722 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n5438) );
NAND4XLTS U6723 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n5436) );
NAND4XLTS U6724 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n5435) );
OR3X1TS U6725 ( .A(n6072), .B(n5436), .C(n5435), .Y(n5440) );
NOR4X1TS U6726 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n5443) );
NOR4X1TS U6727 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n5442) );
NOR4BX1TS U6728 ( .AN(operation_reg[1]), .B(dataA[31]), .C(operation_reg[0]),
.D(n6072), .Y(n5441) );
NOR2X1TS U6729 ( .A(operation_reg[1]), .B(n5440), .Y(n5448) );
NAND4XLTS U6730 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n5444) );
OAI31X1TS U6731 ( .A0(n5446), .A1(n5445), .A2(n5444), .B0(dataB[27]), .Y(
n5447) );
OAI2BB2XLTS U6732 ( .B0(n5450), .B1(n5449), .A0N(n5448), .A1N(
operation_reg[0]), .Y(NaN_reg) );
AOI22X1TS U6733 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n5465), .B1(n2250),
.Y(FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
NOR3X1TS U6734 ( .A(n5586), .B(n5512), .C(n5451), .Y(n5453) );
NOR2BX1TS U6735 ( .AN(begin_operation), .B(n5454), .Y(n5458) );
OAI22X1TS U6736 ( .A0(n5456), .A1(n5455), .B0(n5458), .B1(n5457), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U6737 ( .AN(n5458), .B(n5457), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U6738 ( .A0(n5644), .A1(n5461), .B0(n5460), .B1(n5459), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
OR2X1TS U6739 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .Y(n5462) );
AO22XLTS U6740 ( .A0(operation[2]), .A1(n5462), .B0(n5463), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U6741 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n5463),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
AOI22X1TS U6742 ( .A0(cordic_result[30]), .A1(n5470), .B0(n5469), .B1(
mult_result[30]), .Y(n5466) );
OAI2BB1X1TS U6743 ( .A0N(n4104), .A1N(result_add_subt[30]), .B0(n5466), .Y(
op_result[30]) );
AOI22X1TS U6744 ( .A0(cordic_result[29]), .A1(n5470), .B0(n5469), .B1(
mult_result[29]), .Y(n5467) );
OAI2BB1X1TS U6745 ( .A0N(n4104), .A1N(result_add_subt[29]), .B0(n5467), .Y(
op_result[29]) );
AOI22X1TS U6746 ( .A0(cordic_result[25]), .A1(n5470), .B0(n5469), .B1(
mult_result[25]), .Y(n5468) );
OAI2BB1X1TS U6747 ( .A0N(n4104), .A1N(result_add_subt[25]), .B0(n5468), .Y(
op_result[25]) );
AOI22X1TS U6748 ( .A0(cordic_result[23]), .A1(n5470), .B0(n5469), .B1(
mult_result[23]), .Y(n5471) );
OAI2BB1X1TS U6749 ( .A0N(n4104), .A1N(result_add_subt[23]), .B0(n5471), .Y(
op_result[23]) );
AOI22X1TS U6750 ( .A0(n4104), .A1(ready_add_subt), .B0(n5473), .B1(n5472),
.Y(n5474) );
OAI2BB1X1TS U6751 ( .A0N(n5475), .A1N(n4176), .B0(n5474), .Y(operation_ready) );
INVX2TS U6752 ( .A(n5479), .Y(n5481) );
OAI2BB2XLTS U6753 ( .B0(n5481), .B1(n5790), .A0N(n5481), .A1N(n5476), .Y(
n2148) );
AOI22X1TS U6754 ( .A0(n5481), .A1(n5477), .B0(n2272), .B1(n5479), .Y(n2147)
);
AOI22X1TS U6755 ( .A0(n5481), .A1(n2272), .B0(n5811), .B1(n5479), .Y(n2146)
);
AOI22X1TS U6756 ( .A0(n5481), .A1(n2304), .B0(n5478), .B1(n5479), .Y(n2143)
);
AOI22X1TS U6757 ( .A0(n5481), .A1(n5480), .B0(n5737), .B1(n5479), .Y(n2142)
);
AOI22X1TS U6758 ( .A0(n5483), .A1(FPSENCOS_cont_iter_out[0]), .B0(n2208),
.B1(n5482), .Y(n2141) );
INVX2TS U6759 ( .A(n5511), .Y(n5506) );
OAI2BB2XLTS U6760 ( .B0(n5512), .B1(n5486), .A0N(n5506), .A1N(region_flag[0]), .Y(n2135) );
OAI2BB2XLTS U6761 ( .B0(n5512), .B1(n5872), .A0N(n5506), .A1N(region_flag[1]), .Y(n2134) );
AOI22X1TS U6762 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n5501), .B0(n5487),
.B1(n5489), .Y(n5488) );
NAND2X1TS U6763 ( .A(n5488), .B(n5493), .Y(n2128) );
INVX2TS U6764 ( .A(n5525), .Y(n5559) );
INVX2TS U6765 ( .A(n5526), .Y(n5587) );
OAI2BB2XLTS U6766 ( .B0(n5559), .B1(n5502), .A0N(n5587), .A1N(
FPSENCOS_d_ff3_LUT_out[8]), .Y(n2125) );
AOI22X1TS U6767 ( .A0(FPSENCOS_d_ff3_LUT_out[10]), .A1(n5501), .B0(n5490),
.B1(n5489), .Y(n5491) );
BUFX3TS U6768 ( .A(n5525), .Y(n5572) );
OAI221XLTS U6769 ( .A0(n5572), .A1(n5950), .B0(n5588), .B1(n5494), .C0(n5493), .Y(n2122) );
OAI2BB2XLTS U6770 ( .B0(n5559), .B1(n5495), .A0N(n5587), .A1N(
FPSENCOS_d_ff3_LUT_out[19]), .Y(n2119) );
OAI221XLTS U6771 ( .A0(n5572), .A1(n5951), .B0(n5588), .B1(n5497), .C0(n5496), .Y(n2118) );
AOI22X1TS U6772 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n5501), .B0(n5500),
.B1(n5499), .Y(n5504) );
INVX2TS U6773 ( .A(n5511), .Y(n5508) );
INVX2TS U6774 ( .A(n5511), .Y(n5510) );
BUFX3TS U6775 ( .A(n5513), .Y(n5509) );
OAI2BB2XLTS U6776 ( .B0(n5650), .B1(n5893), .A0N(n5514), .A1N(
FPSENCOS_d_ff_Zn[0]), .Y(n2074) );
NOR3X4TS U6777 ( .A(FPSENCOS_cont_var_out[1]), .B(n5856), .C(n5823), .Y(
n5658) );
BUFX3TS U6778 ( .A(n5515), .Y(n5651) );
BUFX3TS U6779 ( .A(n5519), .Y(n5657) );
OAI2BB2XLTS U6780 ( .B0(n5651), .B1(n5893), .A0N(n5657), .A1N(
FPSENCOS_d_ff_Yn[0]), .Y(n2073) );
NOR3X4TS U6781 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n5823), .Y(n5667) );
BUFX3TS U6782 ( .A(n5516), .Y(n5664) );
BUFX3TS U6783 ( .A(n5520), .Y(n5522) );
OAI2BB2XLTS U6784 ( .B0(n5664), .B1(n5893), .A0N(n5522), .A1N(
FPSENCOS_d_ff_Xn[0]), .Y(n2072) );
INVX2TS U6785 ( .A(n5644), .Y(n5649) );
OAI2BB2XLTS U6786 ( .B0(n5650), .B1(n5894), .A0N(n5649), .A1N(
FPSENCOS_d_ff_Zn[1]), .Y(n2071) );
BUFX3TS U6787 ( .A(n5519), .Y(n5517) );
OAI2BB2XLTS U6788 ( .B0(n5651), .B1(n5894), .A0N(n5517), .A1N(
FPSENCOS_d_ff_Yn[1]), .Y(n2070) );
BUFX3TS U6789 ( .A(n5520), .Y(n5659) );
OAI2BB2XLTS U6790 ( .B0(n5664), .B1(n5894), .A0N(n5659), .A1N(
FPSENCOS_d_ff_Xn[1]), .Y(n2069) );
OAI2BB2XLTS U6791 ( .B0(n5650), .B1(n5891), .A0N(n5649), .A1N(
FPSENCOS_d_ff_Zn[2]), .Y(n2068) );
OAI2BB2XLTS U6792 ( .B0(n5651), .B1(n5891), .A0N(n5517), .A1N(
FPSENCOS_d_ff_Yn[2]), .Y(n2067) );
BUFX3TS U6793 ( .A(n5520), .Y(n5518) );
OAI2BB2XLTS U6794 ( .B0(n5664), .B1(n5891), .A0N(n5518), .A1N(
FPSENCOS_d_ff_Xn[2]), .Y(n2066) );
OAI2BB2XLTS U6795 ( .B0(n5650), .B1(n5890), .A0N(n5649), .A1N(
FPSENCOS_d_ff_Zn[3]), .Y(n2065) );
OAI2BB2XLTS U6796 ( .B0(n5651), .B1(n5890), .A0N(n5517), .A1N(
FPSENCOS_d_ff_Yn[3]), .Y(n2064) );
OAI2BB2XLTS U6797 ( .B0(n5664), .B1(n5890), .A0N(n5518), .A1N(
FPSENCOS_d_ff_Xn[3]), .Y(n2063) );
INVX2TS U6798 ( .A(n5644), .Y(n5540) );
OAI2BB2XLTS U6799 ( .B0(n5540), .B1(n5881), .A0N(n5649), .A1N(
FPSENCOS_d_ff_Zn[4]), .Y(n2062) );
OAI2BB2XLTS U6800 ( .B0(n5651), .B1(n5881), .A0N(n5517), .A1N(
FPSENCOS_d_ff_Yn[4]), .Y(n2061) );
OAI2BB2XLTS U6801 ( .B0(n5664), .B1(n5881), .A0N(n5518), .A1N(
FPSENCOS_d_ff_Xn[4]), .Y(n2060) );
OAI2BB2XLTS U6802 ( .B0(n5540), .B1(n5896), .A0N(n5649), .A1N(
FPSENCOS_d_ff_Zn[5]), .Y(n2059) );
OAI2BB2XLTS U6803 ( .B0(n5651), .B1(n5896), .A0N(n5517), .A1N(
FPSENCOS_d_ff_Yn[5]), .Y(n2058) );
OAI2BB2XLTS U6804 ( .B0(n5664), .B1(n5896), .A0N(n5518), .A1N(
FPSENCOS_d_ff_Xn[5]), .Y(n2057) );
OAI2BB2XLTS U6805 ( .B0(n5540), .B1(n5882), .A0N(n5649), .A1N(
FPSENCOS_d_ff_Zn[6]), .Y(n2056) );
BUFX3TS U6806 ( .A(n5515), .Y(n5645) );
OAI2BB2XLTS U6807 ( .B0(n5645), .B1(n5882), .A0N(n5517), .A1N(
FPSENCOS_d_ff_Yn[6]), .Y(n2055) );
BUFX3TS U6808 ( .A(n5516), .Y(n5647) );
OAI2BB2XLTS U6809 ( .B0(n5647), .B1(n5882), .A0N(n5518), .A1N(
FPSENCOS_d_ff_Xn[6]), .Y(n2054) );
INVX2TS U6810 ( .A(n5644), .Y(n5539) );
OAI2BB2XLTS U6811 ( .B0(n5540), .B1(n5892), .A0N(n5539), .A1N(
FPSENCOS_d_ff_Zn[7]), .Y(n2053) );
OAI2BB2XLTS U6812 ( .B0(n5645), .B1(n5892), .A0N(n5517), .A1N(
FPSENCOS_d_ff_Yn[7]), .Y(n2052) );
OAI2BB2XLTS U6813 ( .B0(n5647), .B1(n5892), .A0N(n5518), .A1N(
FPSENCOS_d_ff_Xn[7]), .Y(n2051) );
OAI2BB2XLTS U6814 ( .B0(n5540), .B1(n5885), .A0N(n5539), .A1N(
FPSENCOS_d_ff_Zn[8]), .Y(n2050) );
OAI2BB2XLTS U6815 ( .B0(n5651), .B1(n5885), .A0N(n5517), .A1N(
FPSENCOS_d_ff_Yn[8]), .Y(n2049) );
OAI2BB2XLTS U6816 ( .B0(n5647), .B1(n5885), .A0N(n5518), .A1N(
FPSENCOS_d_ff_Xn[8]), .Y(n2048) );
INVX2TS U6817 ( .A(n5644), .Y(n5643) );
OAI2BB2XLTS U6818 ( .B0(n5643), .B1(n5895), .A0N(n5539), .A1N(
FPSENCOS_d_ff_Zn[9]), .Y(n2047) );
OAI2BB2XLTS U6819 ( .B0(n5645), .B1(n5895), .A0N(n5517), .A1N(
FPSENCOS_d_ff_Yn[9]), .Y(n2046) );
OAI2BB2XLTS U6820 ( .B0(n5647), .B1(n5895), .A0N(n5518), .A1N(
FPSENCOS_d_ff_Xn[9]), .Y(n2045) );
OAI2BB2XLTS U6821 ( .B0(n5643), .B1(n5888), .A0N(n5539), .A1N(
FPSENCOS_d_ff_Zn[10]), .Y(n2044) );
BUFX3TS U6822 ( .A(n5519), .Y(n5521) );
OAI2BB2XLTS U6823 ( .B0(n5645), .B1(n5888), .A0N(n5521), .A1N(
FPSENCOS_d_ff_Yn[10]), .Y(n2043) );
OAI2BB2XLTS U6824 ( .B0(n5647), .B1(n5888), .A0N(n5518), .A1N(
FPSENCOS_d_ff_Xn[10]), .Y(n2042) );
OAI2BB2XLTS U6825 ( .B0(n5643), .B1(n5886), .A0N(n5539), .A1N(
FPSENCOS_d_ff_Zn[11]), .Y(n2041) );
OAI2BB2XLTS U6826 ( .B0(n5645), .B1(n5886), .A0N(n5521), .A1N(
FPSENCOS_d_ff_Yn[11]), .Y(n2040) );
OAI2BB2XLTS U6827 ( .B0(n5647), .B1(n5886), .A0N(n5522), .A1N(
FPSENCOS_d_ff_Xn[11]), .Y(n2039) );
OAI2BB2XLTS U6828 ( .B0(n5643), .B1(n5889), .A0N(n5539), .A1N(
FPSENCOS_d_ff_Zn[12]), .Y(n2038) );
OAI2BB2XLTS U6829 ( .B0(n5515), .B1(n5889), .A0N(n5521), .A1N(
FPSENCOS_d_ff_Yn[12]), .Y(n2037) );
OAI2BB2XLTS U6830 ( .B0(n5664), .B1(n5889), .A0N(n5522), .A1N(
FPSENCOS_d_ff_Xn[12]), .Y(n2036) );
INVX2TS U6831 ( .A(n5644), .Y(n5653) );
OAI2BB2XLTS U6832 ( .B0(n5643), .B1(n5883), .A0N(n5653), .A1N(
FPSENCOS_d_ff_Zn[13]), .Y(n2035) );
OAI2BB2XLTS U6833 ( .B0(n5515), .B1(n5883), .A0N(n5521), .A1N(
FPSENCOS_d_ff_Yn[13]), .Y(n2034) );
OAI2BB2XLTS U6834 ( .B0(n5647), .B1(n5883), .A0N(n5522), .A1N(
FPSENCOS_d_ff_Xn[13]), .Y(n2033) );
OAI2BB2XLTS U6835 ( .B0(n5643), .B1(n5887), .A0N(n5653), .A1N(
FPSENCOS_d_ff_Zn[14]), .Y(n2032) );
OAI2BB2XLTS U6836 ( .B0(n5645), .B1(n5887), .A0N(n5521), .A1N(
FPSENCOS_d_ff_Yn[14]), .Y(n2031) );
OAI2BB2XLTS U6837 ( .B0(n5516), .B1(n5887), .A0N(n5522), .A1N(
FPSENCOS_d_ff_Xn[14]), .Y(n2030) );
OAI2BB2XLTS U6838 ( .B0(n5540), .B1(n5875), .A0N(n5653), .A1N(
FPSENCOS_d_ff_Zn[15]), .Y(n2029) );
OAI2BB2XLTS U6839 ( .B0(n5515), .B1(n5875), .A0N(n5521), .A1N(
FPSENCOS_d_ff_Yn[15]), .Y(n2028) );
OAI2BB2XLTS U6840 ( .B0(n5516), .B1(n5875), .A0N(n5522), .A1N(
FPSENCOS_d_ff_Xn[15]), .Y(n2027) );
OAI2BB2XLTS U6841 ( .B0(n5643), .B1(n5884), .A0N(n5653), .A1N(
FPSENCOS_d_ff_Zn[16]), .Y(n2026) );
OAI2BB2XLTS U6842 ( .B0(n5515), .B1(n5884), .A0N(n5521), .A1N(
FPSENCOS_d_ff_Yn[16]), .Y(n2025) );
OAI2BB2XLTS U6843 ( .B0(n5516), .B1(n5884), .A0N(n5522), .A1N(
FPSENCOS_d_ff_Xn[16]), .Y(n2024) );
OAI2BB2XLTS U6844 ( .B0(n5643), .B1(n5880), .A0N(n5653), .A1N(
FPSENCOS_d_ff_Zn[17]), .Y(n2023) );
OAI2BB2XLTS U6845 ( .B0(n5645), .B1(n5880), .A0N(n5521), .A1N(
FPSENCOS_d_ff_Yn[17]), .Y(n2022) );
OAI2BB2XLTS U6846 ( .B0(n5520), .B1(n5880), .A0N(n5522), .A1N(
FPSENCOS_d_ff_Xn[17]), .Y(n2021) );
OAI2BB2XLTS U6847 ( .B0(n5540), .B1(n5876), .A0N(n5653), .A1N(
FPSENCOS_d_ff_Zn[18]), .Y(n2020) );
OAI2BB2XLTS U6848 ( .B0(n5515), .B1(n5876), .A0N(n5521), .A1N(
FPSENCOS_d_ff_Yn[18]), .Y(n2019) );
OAI2BB2XLTS U6849 ( .B0(n5516), .B1(n5876), .A0N(n5522), .A1N(
FPSENCOS_d_ff_Xn[18]), .Y(n2018) );
OAI2BB2XLTS U6850 ( .B0(n5643), .B1(n5878), .A0N(n5653), .A1N(
FPSENCOS_d_ff_Zn[19]), .Y(n2017) );
OAI2BB2XLTS U6851 ( .B0(n5515), .B1(n5878), .A0N(n5521), .A1N(
FPSENCOS_d_ff_Yn[19]), .Y(n2016) );
OAI2BB2XLTS U6852 ( .B0(n5516), .B1(n5878), .A0N(n5522), .A1N(
FPSENCOS_d_ff_Xn[19]), .Y(n2015) );
OAI2BB2XLTS U6853 ( .B0(n5540), .B1(n5879), .A0N(n5539), .A1N(
FPSENCOS_d_ff_Zn[20]), .Y(n2014) );
OAI2BB2XLTS U6854 ( .B0(n5517), .B1(n5879), .A0N(n5657), .A1N(
FPSENCOS_d_ff_Yn[20]), .Y(n2013) );
OAI2BB2XLTS U6855 ( .B0(n5516), .B1(n5879), .A0N(n5659), .A1N(
FPSENCOS_d_ff_Xn[20]), .Y(n2012) );
OAI2BB2XLTS U6856 ( .B0(n5650), .B1(n5877), .A0N(n5539), .A1N(
FPSENCOS_d_ff_Zn[21]), .Y(n2011) );
OAI2BB2XLTS U6857 ( .B0(n5519), .B1(n5877), .A0N(n5657), .A1N(
FPSENCOS_d_ff_Yn[21]), .Y(n2010) );
OAI2BB2XLTS U6858 ( .B0(n5647), .B1(n5877), .A0N(n5659), .A1N(
FPSENCOS_d_ff_Xn[21]), .Y(n2009) );
OAI2BB2XLTS U6859 ( .B0(n5540), .B1(n5874), .A0N(n5539), .A1N(
FPSENCOS_d_ff_Zn[22]), .Y(n2008) );
OAI2BB2XLTS U6860 ( .B0(n5645), .B1(n5874), .A0N(n5657), .A1N(
FPSENCOS_d_ff_Yn[22]), .Y(n2007) );
OAI2BB2XLTS U6861 ( .B0(n5518), .B1(n5874), .A0N(n5659), .A1N(
FPSENCOS_d_ff_Xn[22]), .Y(n2006) );
INVX2TS U6862 ( .A(n5552), .Y(n5524) );
BUFX3TS U6863 ( .A(n5525), .Y(n5529) );
OAI2BB2XLTS U6864 ( .B0(n5529), .B1(n2474), .A0N(n5548), .A1N(
FPSENCOS_d_ff2_X[0]), .Y(n2004) );
BUFX3TS U6865 ( .A(n5552), .Y(n5528) );
OA22X1TS U6866 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n2407), .B0(
FPSENCOS_d_ff2_X[1]), .B1(n5528), .Y(n2003) );
OAI2BB2XLTS U6867 ( .B0(n5529), .B1(n2486), .A0N(n5548), .A1N(
FPSENCOS_d_ff2_X[1]), .Y(n2002) );
OA22X1TS U6868 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n5584), .B0(
FPSENCOS_d_ff2_X[2]), .B1(n6069), .Y(n2001) );
OAI2BB2XLTS U6869 ( .B0(n5529), .B1(n2467), .A0N(n5548), .A1N(
FPSENCOS_d_ff2_X[2]), .Y(n2000) );
OA22X1TS U6870 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n4215), .B0(
FPSENCOS_d_ff2_X[3]), .B1(n6069), .Y(n1999) );
OAI2BB2XLTS U6871 ( .B0(n5529), .B1(n2490), .A0N(n5548), .A1N(
FPSENCOS_d_ff2_X[4]), .Y(n1996) );
OA22X1TS U6872 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n5584), .B0(
FPSENCOS_d_ff2_X[5]), .B1(n6069), .Y(n1995) );
OA22X1TS U6873 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n4215), .B0(
FPSENCOS_d_ff2_X[6]), .B1(n6069), .Y(n1993) );
OAI2BB2XLTS U6874 ( .B0(n5529), .B1(n2273), .A0N(n5548), .A1N(
FPSENCOS_d_ff2_X[6]), .Y(n1992) );
OA22X1TS U6875 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n5584), .B0(
FPSENCOS_d_ff2_X[7]), .B1(n6069), .Y(n1991) );
OAI2BB2XLTS U6876 ( .B0(n5529), .B1(n2477), .A0N(n5548), .A1N(
FPSENCOS_d_ff2_X[8]), .Y(n1988) );
OAI2BB2XLTS U6877 ( .B0(n5572), .B1(n2488), .A0N(n5577), .A1N(
FPSENCOS_d_ff2_X[9]), .Y(n1986) );
OA22X1TS U6878 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n4215), .B0(
FPSENCOS_d_ff2_X[10]), .B1(n6069), .Y(n1985) );
OAI2BB2XLTS U6879 ( .B0(n5529), .B1(n2456), .A0N(n5577), .A1N(
FPSENCOS_d_ff2_X[10]), .Y(n1984) );
BUFX3TS U6880 ( .A(n5556), .Y(n5542) );
OA22X1TS U6881 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n5584), .B0(
FPSENCOS_d_ff2_X[12]), .B1(n6069), .Y(n1981) );
OAI2BB2XLTS U6882 ( .B0(n5572), .B1(n2457), .A0N(n5548), .A1N(
FPSENCOS_d_ff2_X[12]), .Y(n1980) );
OA22X1TS U6883 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n4215), .B0(
FPSENCOS_d_ff2_X[13]), .B1(n6069), .Y(n1979) );
OA22X1TS U6884 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n5584), .B0(
FPSENCOS_d_ff2_X[14]), .B1(n5528), .Y(n1977) );
INVX2TS U6885 ( .A(n5525), .Y(n5538) );
OA22X1TS U6886 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n4215), .B0(
FPSENCOS_d_ff2_X[16]), .B1(n5528), .Y(n1973) );
OA22X1TS U6887 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n4215), .B0(
FPSENCOS_d_ff2_X[17]), .B1(n5552), .Y(n1971) );
OA22X1TS U6888 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n5584), .B0(
FPSENCOS_d_ff2_X[19]), .B1(n5528), .Y(n1967) );
OA22X1TS U6889 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n2407), .B0(
FPSENCOS_d_ff2_X[20]), .B1(n5528), .Y(n1965) );
OAI2BB2XLTS U6890 ( .B0(n5529), .B1(n2458), .A0N(n5577), .A1N(
FPSENCOS_d_ff2_X[21]), .Y(n1962) );
OA22X1TS U6891 ( .A0(FPSENCOS_d_ff_Xn[24]), .A1(n4215), .B0(
FPSENCOS_d_ff2_X[24]), .B1(n5528), .Y(n1958) );
OA22X1TS U6892 ( .A0(FPSENCOS_d_ff_Xn[25]), .A1(n5584), .B0(
FPSENCOS_d_ff2_X[25]), .B1(n5528), .Y(n1957) );
OA22X1TS U6893 ( .A0(FPSENCOS_d_ff_Xn[26]), .A1(n4215), .B0(
FPSENCOS_d_ff2_X[26]), .B1(n5528), .Y(n1956) );
OA22X1TS U6894 ( .A0(FPSENCOS_d_ff_Xn[27]), .A1(n2407), .B0(
FPSENCOS_d_ff2_X[27]), .B1(n5528), .Y(n1955) );
OA22X1TS U6895 ( .A0(FPSENCOS_d_ff_Xn[29]), .A1(n5584), .B0(
FPSENCOS_d_ff2_X[29]), .B1(n5528), .Y(n1953) );
OAI2BB2XLTS U6896 ( .B0(n5572), .B1(n2452), .A0N(n5577), .A1N(
intadd_22_SUM_0_), .Y(n1950) );
OAI2BB2XLTS U6897 ( .B0(n5572), .B1(n2468), .A0N(n5577), .A1N(
intadd_22_SUM_1_), .Y(n1949) );
OAI2BB2XLTS U6898 ( .B0(n5529), .B1(n2487), .A0N(n5577), .A1N(
intadd_22_SUM_2_), .Y(n1948) );
NOR2X1TS U6899 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_22_n1), .Y(n5531) );
AOI21X1TS U6900 ( .A0(intadd_22_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n5531),
.Y(n5530) );
OR3X1TS U6901 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_22_n1), .Y(n5533) );
NOR2X1TS U6902 ( .A(FPSENCOS_d_ff2_X[29]), .B(n5533), .Y(n5535) );
AOI21X1TS U6903 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n5533), .B0(n5535), .Y(
n5534) );
XOR2X1TS U6904 ( .A(FPSENCOS_d_ff2_X[30]), .B(n5535), .Y(n5536) );
OAI2BB2XLTS U6905 ( .B0(n5665), .B1(n2407), .A0N(FPSENCOS_d_ff2_X[31]),
.A1N(n5537), .Y(n1943) );
OAI2BB2XLTS U6906 ( .B0(n5540), .B1(n5666), .A0N(n5539), .A1N(
FPSENCOS_d_ff_Zn[31]), .Y(n1909) );
AOI22X1TS U6907 ( .A0(n5658), .A1(n5666), .B0(n5585), .B1(n5651), .Y(n1908)
);
BUFX3TS U6908 ( .A(n5552), .Y(n5550) );
OAI2BB2XLTS U6909 ( .B0(n2473), .B1(n5550), .A0N(FPSENCOS_d_ff_Yn[0]), .A1N(
n5542), .Y(n1907) );
INVX2TS U6910 ( .A(n5579), .Y(n5562) );
OAI2BB2XLTS U6911 ( .B0(n5559), .B1(n2473), .A0N(n5562), .A1N(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1906) );
OAI2BB2XLTS U6912 ( .B0(n5541), .B1(n5550), .A0N(FPSENCOS_d_ff_Yn[1]), .A1N(
n5542), .Y(n1905) );
OAI2BB2XLTS U6913 ( .B0(n5559), .B1(n5541), .A0N(n5587), .A1N(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1904) );
OAI2BB2XLTS U6914 ( .B0(n5543), .B1(n5550), .A0N(FPSENCOS_d_ff_Yn[2]), .A1N(
n5542), .Y(n1903) );
OAI2BB2XLTS U6915 ( .B0(n5559), .B1(n5543), .A0N(n5581), .A1N(
FPSENCOS_d_ff3_sh_y_out[2]), .Y(n1902) );
BUFX3TS U6916 ( .A(n5556), .Y(n5554) );
OAI2BB2XLTS U6917 ( .B0(n5544), .B1(n5550), .A0N(FPSENCOS_d_ff_Yn[3]), .A1N(
n5554), .Y(n1901) );
OAI2BB2XLTS U6918 ( .B0(n5559), .B1(n5544), .A0N(n5581), .A1N(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1900) );
OAI2BB2XLTS U6919 ( .B0(n5545), .B1(n5550), .A0N(FPSENCOS_d_ff_Yn[4]), .A1N(
n5554), .Y(n1899) );
OAI2BB2XLTS U6920 ( .B0(n5559), .B1(n5545), .A0N(n5581), .A1N(
FPSENCOS_d_ff3_sh_y_out[4]), .Y(n1898) );
OAI2BB2XLTS U6921 ( .B0(n5546), .B1(n5550), .A0N(FPSENCOS_d_ff_Yn[5]), .A1N(
n5554), .Y(n1897) );
OAI2BB2XLTS U6922 ( .B0(n5559), .B1(n5546), .A0N(n5581), .A1N(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1896) );
OAI2BB2XLTS U6923 ( .B0(n5547), .B1(n5550), .A0N(FPSENCOS_d_ff_Yn[6]), .A1N(
n5554), .Y(n1895) );
OAI2BB2XLTS U6924 ( .B0(n5559), .B1(n5547), .A0N(n5581), .A1N(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1894) );
OAI2BB2XLTS U6925 ( .B0(n2471), .B1(n5550), .A0N(FPSENCOS_d_ff_Yn[7]), .A1N(
n5554), .Y(n1893) );
INVX2TS U6926 ( .A(n5548), .Y(n5561) );
OAI2BB2XLTS U6927 ( .B0(n5561), .B1(n2471), .A0N(n5581), .A1N(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1892) );
OAI2BB2XLTS U6928 ( .B0(n5549), .B1(n5550), .A0N(FPSENCOS_d_ff_Yn[8]), .A1N(
n5554), .Y(n1891) );
OAI2BB2XLTS U6929 ( .B0(n5561), .B1(n5549), .A0N(n5581), .A1N(
FPSENCOS_d_ff3_sh_y_out[8]), .Y(n1890) );
OAI2BB2XLTS U6930 ( .B0(n5551), .B1(n5550), .A0N(FPSENCOS_d_ff_Yn[9]), .A1N(
n5554), .Y(n1889) );
OAI2BB2XLTS U6931 ( .B0(n5561), .B1(n5551), .A0N(n5562), .A1N(
FPSENCOS_d_ff3_sh_y_out[9]), .Y(n1888) );
BUFX3TS U6932 ( .A(n5552), .Y(n5564) );
OAI2BB2XLTS U6933 ( .B0(n2482), .B1(n5564), .A0N(FPSENCOS_d_ff_Yn[10]),
.A1N(n5554), .Y(n1887) );
OAI2BB2XLTS U6934 ( .B0(n5561), .B1(n2482), .A0N(n5562), .A1N(
FPSENCOS_d_ff3_sh_y_out[10]), .Y(n1886) );
OAI2BB2XLTS U6935 ( .B0(n5553), .B1(n5564), .A0N(FPSENCOS_d_ff_Yn[11]),
.A1N(n5554), .Y(n1885) );
OAI2BB2XLTS U6936 ( .B0(n5561), .B1(n5553), .A0N(n5562), .A1N(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1884) );
OAI2BB2XLTS U6937 ( .B0(n5555), .B1(n5564), .A0N(FPSENCOS_d_ff_Yn[12]),
.A1N(n5554), .Y(n1883) );
OAI2BB2XLTS U6938 ( .B0(n5561), .B1(n5555), .A0N(n5562), .A1N(
FPSENCOS_d_ff3_sh_y_out[12]), .Y(n1882) );
BUFX3TS U6939 ( .A(n5556), .Y(n5567) );
OAI2BB2XLTS U6940 ( .B0(n5557), .B1(n5564), .A0N(FPSENCOS_d_ff_Yn[13]),
.A1N(n5567), .Y(n1881) );
OAI2BB2XLTS U6941 ( .B0(n5561), .B1(n5557), .A0N(n5562), .A1N(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1880) );
OAI2BB2XLTS U6942 ( .B0(n2481), .B1(n5564), .A0N(FPSENCOS_d_ff_Yn[14]),
.A1N(n5567), .Y(n1879) );
OAI2BB2XLTS U6943 ( .B0(n5561), .B1(n2481), .A0N(n5562), .A1N(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1878) );
OAI2BB2XLTS U6944 ( .B0(n5558), .B1(n5564), .A0N(FPSENCOS_d_ff_Yn[15]),
.A1N(n5567), .Y(n1877) );
OAI2BB2XLTS U6945 ( .B0(n5559), .B1(n5558), .A0N(n5562), .A1N(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1876) );
OAI2BB2XLTS U6946 ( .B0(n5560), .B1(n5564), .A0N(FPSENCOS_d_ff_Yn[16]),
.A1N(n5567), .Y(n1875) );
OAI2BB2XLTS U6947 ( .B0(n5561), .B1(n5560), .A0N(n5587), .A1N(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1874) );
OAI2BB2XLTS U6948 ( .B0(n2476), .B1(n5564), .A0N(FPSENCOS_d_ff_Yn[17]),
.A1N(n5567), .Y(n1873) );
OAI2BB2XLTS U6949 ( .B0(n5561), .B1(n2476), .A0N(n5562), .A1N(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1872) );
OAI2BB2XLTS U6950 ( .B0(n5563), .B1(n5564), .A0N(FPSENCOS_d_ff_Yn[18]),
.A1N(n5567), .Y(n1871) );
OAI2BB2XLTS U6951 ( .B0(n5588), .B1(n5563), .A0N(n5562), .A1N(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1870) );
OAI2BB2XLTS U6952 ( .B0(n5565), .B1(n5564), .A0N(FPSENCOS_d_ff_Yn[19]),
.A1N(n5567), .Y(n1869) );
OAI2BB2XLTS U6953 ( .B0(n5588), .B1(n5565), .A0N(n5587), .A1N(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1868) );
OAI2BB2XLTS U6954 ( .B0(n2470), .B1(n5586), .A0N(FPSENCOS_d_ff_Yn[20]),
.A1N(n5567), .Y(n1867) );
OAI2BB2XLTS U6955 ( .B0(n5588), .B1(n2470), .A0N(n5587), .A1N(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1866) );
OAI2BB2XLTS U6956 ( .B0(n5566), .B1(n5569), .A0N(FPSENCOS_d_ff_Yn[21]),
.A1N(n5567), .Y(n1865) );
OAI2BB2XLTS U6957 ( .B0(n5588), .B1(n5566), .A0N(n5587), .A1N(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1864) );
OAI2BB2XLTS U6958 ( .B0(n5568), .B1(n5569), .A0N(FPSENCOS_d_ff_Yn[22]),
.A1N(n5567), .Y(n1863) );
OAI2BB2XLTS U6959 ( .B0(n5588), .B1(n5568), .A0N(n5587), .A1N(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1862) );
OAI2BB2XLTS U6960 ( .B0(n2252), .B1(n5569), .A0N(FPSENCOS_d_ff_Yn[23]),
.A1N(n5570), .Y(n1861) );
OAI2BB2XLTS U6961 ( .B0(n5942), .B1(n5569), .A0N(FPSENCOS_d_ff_Yn[24]),
.A1N(n5570), .Y(n1860) );
OAI2BB2XLTS U6962 ( .B0(n5943), .B1(n5569), .A0N(FPSENCOS_d_ff_Yn[25]),
.A1N(n5570), .Y(n1859) );
OAI2BB2XLTS U6963 ( .B0(n5944), .B1(n5569), .A0N(FPSENCOS_d_ff_Yn[26]),
.A1N(n5570), .Y(n1858) );
OAI2BB2XLTS U6964 ( .B0(n5909), .B1(n5586), .A0N(FPSENCOS_d_ff_Yn[27]),
.A1N(n5570), .Y(n1857) );
OAI2BB2XLTS U6965 ( .B0(n5573), .B1(n5586), .A0N(FPSENCOS_d_ff_Yn[28]),
.A1N(n5570), .Y(n1856) );
OAI2BB2XLTS U6966 ( .B0(n5908), .B1(n5586), .A0N(FPSENCOS_d_ff_Yn[29]),
.A1N(n5570), .Y(n1855) );
OAI2BB2XLTS U6967 ( .B0(n5910), .B1(n5586), .A0N(FPSENCOS_d_ff_Yn[30]),
.A1N(n5570), .Y(n1854) );
NOR2X2TS U6968 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_21_n1), .Y(n5574) );
AOI21X1TS U6969 ( .A0(intadd_21_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n5574),
.Y(n5571) );
NAND2X1TS U6970 ( .A(n5574), .B(n5573), .Y(n5576) );
AOI21X1TS U6971 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n5576), .B0(n5580), .Y(
n5578) );
OAI22X1TS U6972 ( .A0(n5586), .A1(n2462), .B0(n5585), .B1(n2407), .Y(n1845)
);
OAI2BB2XLTS U6973 ( .B0(n5588), .B1(n2462), .A0N(n5587), .A1N(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1844) );
AOI22X1TS U6974 ( .A0(Data_2[3]), .A1(n5597), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n5596), .Y(n5590) );
AOI22X1TS U6975 ( .A0(n5593), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n5661),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n5589) );
NAND2X1TS U6976 ( .A(n5629), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n5609) );
AOI22X1TS U6977 ( .A0(Data_2[5]), .A1(n5597), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n5596), .Y(n5592) );
AOI22X1TS U6978 ( .A0(n5593), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n5661),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n5591) );
NAND2X1TS U6979 ( .A(n4318), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n5603) );
AOI22X1TS U6980 ( .A0(Data_2[7]), .A1(n5597), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n5596), .Y(n5595) );
AOI22X1TS U6981 ( .A0(n5593), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n4106),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n5594) );
NAND2X1TS U6982 ( .A(n4318), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n5598) );
AOI22X1TS U6983 ( .A0(Data_2[11]), .A1(n5597), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n5596), .Y(n5600) );
AOI22X1TS U6984 ( .A0(n5612), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n4106),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n5599) );
AOI22X1TS U6985 ( .A0(Data_2[13]), .A1(n5624), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n5623), .Y(n5602) );
AOI22X1TS U6986 ( .A0(n5612), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n4106),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n5601) );
NAND2X1TS U6987 ( .A(n4318), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n5615) );
AOI22X1TS U6988 ( .A0(Data_2[14]), .A1(n5624), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n5623), .Y(n5605) );
AOI22X1TS U6989 ( .A0(n5612), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n4106),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n5604) );
AOI22X1TS U6990 ( .A0(Data_2[15]), .A1(n5624), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n5623), .Y(n5607) );
AOI22X1TS U6991 ( .A0(n5612), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n5635),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n5606) );
NAND2X1TS U6992 ( .A(n4318), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n5620) );
AOI22X1TS U6993 ( .A0(Data_2[16]), .A1(n5608), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n5623), .Y(n5611) );
AOI22X1TS U6994 ( .A0(n5612), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n5635),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n5610) );
AOI22X1TS U6995 ( .A0(Data_2[17]), .A1(n5624), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n5623), .Y(n5614) );
AOI22X1TS U6996 ( .A0(n5612), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n5635),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n5613) );
AOI22X1TS U6997 ( .A0(Data_2[18]), .A1(n5624), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n5623), .Y(n5617) );
AOI22X1TS U6998 ( .A0(n5628), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n5635),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n5616) );
AOI22X1TS U6999 ( .A0(Data_2[19]), .A1(n5624), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n5623), .Y(n5619) );
AOI22X1TS U7000 ( .A0(n5628), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n5635),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n5618) );
NAND2X1TS U7001 ( .A(n4318), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n5625) );
AOI22X1TS U7002 ( .A0(Data_2[20]), .A1(n5624), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n5623), .Y(n5622) );
AOI22X1TS U7003 ( .A0(n5628), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n5635),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n5621) );
AOI22X1TS U7004 ( .A0(Data_2[22]), .A1(n5624), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n5623), .Y(n5627) );
AOI22X1TS U7005 ( .A0(n5628), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n5635),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n5626) );
AOI22X1TS U7006 ( .A0(Data_2[27]), .A1(n5634), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n5660), .Y(n5631) );
AOI22X1TS U7007 ( .A0(n5628), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n5635),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n5630) );
NAND2X1TS U7008 ( .A(n5629), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n5636) );
AOI22X1TS U7009 ( .A0(Data_2[28]), .A1(n5634), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n5660), .Y(n5633) );
AOI22X1TS U7010 ( .A0(n4322), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n5635),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n5632) );
AOI22X1TS U7011 ( .A0(Data_2[29]), .A1(n5634), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n5660), .Y(n5638) );
AOI22X1TS U7012 ( .A0(n4322), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n5635),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n5637) );
OAI22X1TS U7013 ( .A0(n5641), .A1(n5640), .B0(n5639), .B1(n5868), .Y(n1812)
);
OAI2BB2XLTS U7014 ( .B0(n5650), .B1(n5642), .A0N(n5649), .A1N(
FPSENCOS_d_ff_Zn[24]), .Y(n1783) );
OAI2BB2XLTS U7015 ( .B0(n5645), .B1(n5642), .A0N(n5657), .A1N(
FPSENCOS_d_ff_Yn[24]), .Y(n1782) );
OAI2BB2XLTS U7016 ( .B0(n5647), .B1(n5642), .A0N(n5659), .A1N(
FPSENCOS_d_ff_Xn[24]), .Y(n1781) );
OAI2BB2XLTS U7017 ( .B0(n5650), .B1(n5646), .A0N(n5649), .A1N(
FPSENCOS_d_ff_Zn[26]), .Y(n1777) );
OAI2BB2XLTS U7018 ( .B0(n5645), .B1(n5646), .A0N(n5657), .A1N(
FPSENCOS_d_ff_Yn[26]), .Y(n1776) );
OAI2BB2XLTS U7019 ( .B0(n5647), .B1(n5646), .A0N(n5659), .A1N(
FPSENCOS_d_ff_Xn[26]), .Y(n1775) );
OAI2BB2XLTS U7020 ( .B0(n5650), .B1(n5648), .A0N(n5649), .A1N(
FPSENCOS_d_ff_Zn[27]), .Y(n1774) );
OAI2BB2XLTS U7021 ( .B0(n5651), .B1(n5648), .A0N(n5657), .A1N(
FPSENCOS_d_ff_Yn[27]), .Y(n1773) );
OAI2BB2XLTS U7022 ( .B0(n5664), .B1(n5648), .A0N(n5659), .A1N(
FPSENCOS_d_ff_Xn[27]), .Y(n1772) );
OAI2BB2XLTS U7023 ( .B0(n5650), .B1(n5652), .A0N(n5649), .A1N(
FPSENCOS_d_ff_Zn[28]), .Y(n1771) );
OAI2BB2XLTS U7024 ( .B0(n5651), .B1(n5652), .A0N(n5657), .A1N(
FPSENCOS_d_ff_Yn[28]), .Y(n1770) );
OAI2BB2XLTS U7025 ( .B0(n5664), .B1(n5652), .A0N(n5659), .A1N(
FPSENCOS_d_ff_Xn[28]), .Y(n1769) );
AOI22X1TS U7026 ( .A0(FPSENCOS_d_ff3_sh_x_out[31]), .A1(n5661), .B0(
FPADDSUB_intDY_EWSW[31]), .B1(n5660), .Y(n5663) );
AOI22X1TS U7027 ( .A0(n4322), .A1(FPSENCOS_d_ff3_sh_y_out[31]), .B0(n4109),
.B1(Data_2[31]), .Y(n5662) );
NAND2X1TS U7028 ( .A(n5663), .B(n5662), .Y(n1728) );
AOI22X1TS U7029 ( .A0(n5667), .A1(n5666), .B0(n5665), .B1(n5664), .Y(n1727)
);
NOR4X1TS U7030 ( .A(FPMULT_Op_MY[27]), .B(FPMULT_Op_MY[26]), .C(
FPMULT_Op_MY[25]), .D(FPMULT_Op_MY[24]), .Y(n5672) );
NOR4X1TS U7031 ( .A(n2448), .B(n5668), .C(n2289), .D(n2206), .Y(n5671) );
NOR4X1TS U7032 ( .A(FPMULT_Op_MY[21]), .B(n2207), .C(n2421), .D(n2415), .Y(
n5670) );
NOR4X1TS U7033 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[30]), .C(
FPMULT_Op_MY[29]), .D(FPMULT_Op_MY[28]), .Y(n5669) );
NAND4XLTS U7034 ( .A(n5672), .B(n5671), .C(n5670), .D(n5669), .Y(n5688) );
NAND4XLTS U7035 ( .A(n5676), .B(n5675), .C(n5674), .D(n5673), .Y(n5687) );
NOR4X1TS U7036 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[18]), .C(
FPMULT_Op_MX[16]), .D(FPMULT_Op_MX[14]), .Y(n5679) );
NOR4X1TS U7037 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MX[30]), .C(
FPMULT_Op_MX[29]), .D(FPMULT_Op_MX[28]), .Y(n5677) );
NAND4XLTS U7038 ( .A(n5680), .B(n5679), .C(n5678), .D(n5677), .Y(n5686) );
NOR4X1TS U7039 ( .A(n2282), .B(n2212), .C(FPMULT_Op_MX[3]), .D(n5681), .Y(
n5684) );
NOR4X1TS U7040 ( .A(n2281), .B(n2213), .C(n2209), .D(FPMULT_Op_MX[2]), .Y(
n5683) );
NAND4XLTS U7041 ( .A(n5684), .B(n5683), .C(n2220), .D(n5682), .Y(n5685) );
OA22X1TS U7042 ( .A0(n5688), .A1(n5687), .B0(n5686), .B1(n5685), .Y(n5689)
);
OAI2BB2XLTS U7043 ( .B0(n5690), .B1(n5689), .A0N(n5690), .A1N(
FPMULT_zero_flag), .Y(n1625) );
OA22X1TS U7044 ( .A0(n5700), .A1(mult_result[23]), .B0(
FPMULT_exp_oper_result[0]), .B1(n5698), .Y(n1584) );
OA22X1TS U7045 ( .A0(n5700), .A1(mult_result[24]), .B0(
FPMULT_exp_oper_result[1]), .B1(n5692), .Y(n1583) );
OA22X1TS U7046 ( .A0(n5693), .A1(mult_result[25]), .B0(
FPMULT_exp_oper_result[2]), .B1(n5692), .Y(n1582) );
OA22X1TS U7047 ( .A0(n5693), .A1(mult_result[26]), .B0(
FPMULT_exp_oper_result[3]), .B1(n5698), .Y(n1581) );
OA22X1TS U7048 ( .A0(n5693), .A1(mult_result[27]), .B0(
FPMULT_exp_oper_result[4]), .B1(n5692), .Y(n1580) );
OA22X1TS U7049 ( .A0(n5693), .A1(mult_result[28]), .B0(
FPMULT_exp_oper_result[5]), .B1(n5692), .Y(n1579) );
OA22X1TS U7050 ( .A0(n5693), .A1(mult_result[29]), .B0(
FPMULT_exp_oper_result[6]), .B1(n5692), .Y(n1578) );
OA22X1TS U7051 ( .A0(n5700), .A1(mult_result[30]), .B0(
FPMULT_exp_oper_result[7]), .B1(n5698), .Y(n1577) );
INVX2TS U7052 ( .A(n5700), .Y(n5699) );
OAI2BB1X1TS U7053 ( .A0N(mult_result[31]), .A1N(n5699), .B0(n5696), .Y(n1576) );
INVX2TS U7054 ( .A(n5698), .Y(n5697) );
INVX2TS U7055 ( .A(n5698), .Y(n5701) );
INVX2TS U7056 ( .A(n5700), .Y(n5703) );
AOI21X1TS U7057 ( .A0(FPADDSUB_DMP_EXP_EWSW[26]), .A1(n2463), .B0(n5705),
.Y(n5706) );
XNOR2X1TS U7058 ( .A(n5707), .B(n5706), .Y(n5708) );
AOI21X1TS U7059 ( .A0(FPADDSUB_DMP_EXP_EWSW[24]), .A1(n2268), .B0(n5709),
.Y(n5710) );
INVX2TS U7060 ( .A(n5719), .Y(n5733) );
OAI2BB2XLTS U7061 ( .B0(n2272), .B1(n5869), .A0N(n5717), .A1N(
FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1457) );
OAI2BB2XLTS U7062 ( .B0(n2272), .B1(n5833), .A0N(n5717), .A1N(
FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1452) );
OAI2BB2XLTS U7063 ( .B0(n2272), .B1(n2460), .A0N(n5717), .A1N(
FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1447) );
OAI2BB2XLTS U7064 ( .B0(n2272), .B1(n5835), .A0N(n5717), .A1N(
FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1442) );
OAI222X1TS U7065 ( .A0(n5723), .A1(n5897), .B0(n2268), .B1(
FPADDSUB_Shift_reg_FLAGS_7_6), .C0(n2226), .C1(n5722), .Y(n1416) );
OAI222X1TS U7066 ( .A0(n5723), .A1(n5905), .B0(n2463), .B1(
FPADDSUB_Shift_reg_FLAGS_7_6), .C0(n2227), .C1(n5722), .Y(n1414) );
OAI22X1TS U7067 ( .A0(n5740), .A1(n5874), .B0(n5728), .B1(n2198), .Y(n1408)
);
OAI22X1TS U7068 ( .A0(n5740), .A1(n5875), .B0(n5729), .B1(n2298), .Y(n1405)
);
OAI22X1TS U7069 ( .A0(n5740), .A1(n5876), .B0(n5730), .B1(n2405), .Y(n1402)
);
OAI22X1TS U7070 ( .A0(n5740), .A1(n5877), .B0(n5731), .B1(n2405), .Y(n1399)
);
OAI22X1TS U7071 ( .A0(n5740), .A1(n5878), .B0(n5732), .B1(n2405), .Y(n1396)
);
OAI22X1TS U7072 ( .A0(n5740), .A1(n5879), .B0(n5734), .B1(n2405), .Y(n1393)
);
INVX2TS U7073 ( .A(n5719), .Y(n5747) );
OAI22X1TS U7074 ( .A0(n5740), .A1(n5880), .B0(n5735), .B1(n2405), .Y(n1390)
);
OAI22X1TS U7075 ( .A0(n5740), .A1(n5881), .B0(n5736), .B1(n2405), .Y(n1387)
);
OAI22X1TS U7076 ( .A0(n5796), .A1(n5882), .B0(n5738), .B1(n2298), .Y(n1384)
);
OAI22X1TS U7077 ( .A0(n5740), .A1(n5883), .B0(n5739), .B1(n2298), .Y(n1381)
);
OAI22X1TS U7078 ( .A0(n5796), .A1(n5884), .B0(n5742), .B1(n2198), .Y(n1378)
);
OAI22X1TS U7079 ( .A0(n5796), .A1(n5885), .B0(n5743), .B1(n2298), .Y(n1375)
);
OAI22X1TS U7080 ( .A0(n5796), .A1(n5886), .B0(n5744), .B1(n2198), .Y(n1372)
);
OAI22X1TS U7081 ( .A0(n5796), .A1(n5887), .B0(n5745), .B1(n2198), .Y(n1369)
);
OAI22X1TS U7082 ( .A0(n5796), .A1(n5888), .B0(n5746), .B1(n2198), .Y(n1366)
);
OAI22X1TS U7083 ( .A0(n5796), .A1(n5889), .B0(n5748), .B1(n2198), .Y(n1363)
);
AOI22X1TS U7084 ( .A0(n2223), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n2270), .B1(
FPADDSUB_intDY_EWSW[17]), .Y(n5749) );
AOI22X1TS U7085 ( .A0(n2507), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n5853), .B1(
FPADDSUB_intDY_EWSW[15]), .Y(n5750) );
AOI22X1TS U7086 ( .A0(n5863), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n2492), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n5751) );
AOI22X1TS U7087 ( .A0(n5852), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n2264), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n5752) );
NOR4X1TS U7088 ( .A(n5756), .B(n5755), .C(n5754), .D(n5753), .Y(n5783) );
AOI22X1TS U7089 ( .A0(n2484), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n2265), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n5757) );
AOI22X1TS U7090 ( .A0(n5829), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n5864), .B1(
FPADDSUB_intDY_EWSW[29]), .Y(n5758) );
AOI22X1TS U7091 ( .A0(n2505), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n2262), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n5759) );
AOI22X1TS U7092 ( .A0(n2224), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2263), .B1(
FPADDSUB_intDY_EWSW[1]), .Y(n5760) );
NOR4X1TS U7093 ( .A(n5764), .B(n5763), .C(n5762), .D(n5761), .Y(n5782) );
AOI22X1TS U7094 ( .A0(n2226), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n5855), .B1(
FPADDSUB_intDY_EWSW[23]), .Y(n5765) );
AOI22X1TS U7095 ( .A0(n2225), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n2269), .B1(
FPADDSUB_intDY_EWSW[21]), .Y(n5766) );
OAI22X1TS U7096 ( .A0(n2260), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n5851), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n5767) );
OAI22X1TS U7097 ( .A0(n2266), .A1(FPADDSUB_intDY_EWSW[0]), .B0(n2227), .B1(
FPADDSUB_intDY_EWSW[26]), .Y(n5769) );
OAI22X1TS U7098 ( .A0(n2261), .A1(FPADDSUB_intDY_EWSW[2]), .B0(n2466), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n5770) );
OAI22X1TS U7099 ( .A0(n2514), .A1(FPADDSUB_intDY_EWSW[4]), .B0(n2513), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n5771) );
OAI22X1TS U7100 ( .A0(n2511), .A1(FPADDSUB_intDY_EWSW[6]), .B0(n2259), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n5772) );
NOR4X1TS U7101 ( .A(n5780), .B(n5779), .C(n5778), .D(n5777), .Y(n5781) );
CLKXOR2X2TS U7102 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(
n5789) );
OAI22X1TS U7103 ( .A0(FPADDSUB_intDX_EWSW[31]), .A1(n5785), .B0(n5784), .B1(
n5789), .Y(n5786) );
BUFX3TS U7104 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n5813) );
INVX2TS U7105 ( .A(n5719), .Y(n5812) );
OAI22X1TS U7106 ( .A0(n5796), .A1(n5890), .B0(n5792), .B1(n2405), .Y(n1329)
);
OAI22X1TS U7107 ( .A0(n5796), .A1(n5891), .B0(n5793), .B1(n2198), .Y(n1313)
);
OAI22X1TS U7108 ( .A0(n5796), .A1(n5892), .B0(n5795), .B1(n2405), .Y(n1306)
);
OAI22X1TS U7109 ( .A0(n5802), .A1(n5893), .B0(n5797), .B1(n2405), .Y(n1299)
);
INVX2TS U7110 ( .A(n5719), .Y(n5805) );
OAI22X1TS U7111 ( .A0(n5802), .A1(n5894), .B0(n5798), .B1(n2198), .Y(n1292)
);
OAI22X1TS U7112 ( .A0(n5802), .A1(n5895), .B0(n5799), .B1(n2198), .Y(n1285)
);
OAI22X1TS U7113 ( .A0(n5802), .A1(n5896), .B0(n5801), .B1(n2405), .Y(n1278)
);
INVX2TS U7114 ( .A(n5804), .Y(n5810) );
INVX2TS U7115 ( .A(n5719), .Y(n5809) );
CMPR42X1TS U7116 ( .A(mult_x_254_n168), .B(mult_x_254_n280), .C(
mult_x_254_n288), .D(mult_x_254_n300), .ICI(mult_x_254_n165), .S(
mult_x_254_n164), .ICO(mult_x_254_n162), .CO(mult_x_254_n163) );
CMPR42X1TS U7117 ( .A(mult_x_254_n169), .B(mult_x_254_n301), .C(
mult_x_254_n289), .D(mult_x_254_n173), .ICI(mult_x_254_n170), .S(
mult_x_254_n167), .ICO(mult_x_254_n165), .CO(mult_x_254_n166) );
CMPR42X1TS U7118 ( .A(mult_x_254_n290), .B(mult_x_254_n314), .C(
mult_x_254_n174), .D(mult_x_254_n178), .ICI(mult_x_254_n175), .S(
mult_x_254_n172), .ICO(mult_x_254_n170), .CO(mult_x_254_n171) );
CMPR42X1TS U7119 ( .A(n2448), .B(FPMULT_Op_MY[21]), .C(mult_x_219_n280), .D(
mult_x_219_n292), .ICI(mult_x_219_n163), .S(mult_x_219_n162), .ICO(
mult_x_219_n160), .CO(mult_x_219_n161) );
CMPR42X1TS U7120 ( .A(n2528), .B(mult_x_219_n281), .C(mult_x_219_n293), .D(
mult_x_219_n171), .ICI(mult_x_219_n168), .S(mult_x_219_n165), .ICO(
mult_x_219_n163), .CO(mult_x_219_n164) );
CMPR42X1TS U7121 ( .A(mult_x_219_n294), .B(mult_x_219_n306), .C(
mult_x_219_n172), .D(mult_x_219_n176), .ICI(mult_x_219_n173), .S(
mult_x_219_n170), .ICO(mult_x_219_n168), .CO(mult_x_219_n169) );
CMPR42X1TS U7122 ( .A(DP_OP_454J16_123_2743_n407), .B(
DP_OP_454J16_123_2743_n263), .C(DP_OP_454J16_123_2743_n384), .D(
DP_OP_454J16_123_2743_n394), .ICI(DP_OP_454J16_123_2743_n260), .S(
DP_OP_454J16_123_2743_n259), .ICO(DP_OP_454J16_123_2743_n257), .CO(
DP_OP_454J16_123_2743_n258) );
initial $sdf_annotate("FPU_Interface2_syn.sdf");
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: tx_crc_combine
*
*/
`default_nettype none
module tx_crc_combine #(
parameter LOG_FPW = 2,
parameter FPW = 4,
parameter DWIDTH = 512
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----Input data
//----------------------------------
input wire [FPW-1:0] d_in_hdr,
input wire [FPW-1:0] d_in_tail,
input wire [DWIDTH-1:0] d_in_data,
//----------------------------------
//----Outputs
//----------------------------------
output wire [DWIDTH-1:0] d_out_data
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
`include "hmc_field_functions.h"
//------------------------------------------------------------------------------------General Assignments
integer i_f; //counts to FPW
integer i_f2; //counts to FPW inside another i_f loop
integer i_c; //depth of the crc data pipeline
genvar f, f2;
//------------------------------------------------------------------------------------Split input data into FLITs
wire [128-1:0] d_in_flit [FPW-1:0];
generate
for(f = 0; f < (FPW); f = f + 1) begin : SPLIT_FLITs_TX
assign d_in_flit[f] = d_in_data[(f*128)+128-1:f*128];
end
endgenerate
reg [3:0] d_in_flit_lng_dly [FPW-1:0];
reg [DWIDTH-1:0] d_in_data_dly;
reg [FPW-1:0] d_in_tail_dly;
reg [FPW-1:0] d_in_hdr_dly;
reg [LOG_FPW-1:0] d_in_flit_target_crc [FPW-1:0];
//------------------------------------------------------------------------------------CRC Target Assignment
reg swap_crc;
//Retrieve the target crc from the header and assign to corresponding tail
reg [LOG_FPW-1:0] target_crc_per_tail [FPW-1:0];
reg [LOG_FPW-1:0] target_crc_per_tail1 [FPW-1:0];
reg [LOG_FPW-1:0] target_crc_per_tail_comb [FPW-1:0];
reg [LOG_FPW-1:0] target_crc_comb;
reg [LOG_FPW-1:0] target_crc_temp;
//------------------------------------------------------------------------------------CRC Modules Input stage
wire [31:0] crc_init_out [FPW-1:0];
reg [31:0] crc_accu_in [FPW-1:0];
reg [FPW-1:0] crc_accu_in_valid [FPW-1:0];
reg [FPW-1:0] crc_accu_in_tail [FPW-1:0];
wire [31:0] crc_per_flit [FPW-1:0];
//------------------------------------------------------------------------------------Inter CRC stage
reg [3:0] payload_remain [FPW-1:0];
wire [(FPW*32)-1:0] crc_accu_in_combined [FPW-1:0];
generate
for(f=0;f<FPW;f=f+1) begin : INTER_CRC_1_TX
for(f2=0;f2<FPW;f2=f2+1) begin : INTER_CRC_2_TX
assign crc_accu_in_combined[f][(f2*32)+31:(f2*32)] = crc_accu_in_valid[f][f2] ? crc_accu_in[f2] : 32'h0;
end
end
endgenerate
//------------------------------------------------------------------------------------Data Pipeline signals
reg [DWIDTH-1:0] crc_data_pipe_in_data [1:0];
reg [FPW-1:0] crc_data_pipe_in_tail [1:0];
wire [128-1:0] crc_data_pipe_out_data_flit [FPW-1:0];
generate
for(f = 0; f < (FPW); f = f + 1) begin : assign_data_pipe_output
assign crc_data_pipe_out_data_flit[f] = crc_data_pipe_in_data[1][(f*128)+128-1:f*128];
end
endgenerate
reg [128-1:0] data_rdy_flit [FPW-1:0];
generate
for(f = 0; f < (FPW); f = f + 1) begin : reorder_flits_to_word
assign d_out_data[(f*128)+128-1:(f*128)] = data_rdy_flit[f];
end
endgenerate
//==================================================================================
//---------------------------------Retrieve the lengths to invalide FLITs
//==================================================================================
always @(*) begin
//Retrieve the length from the header and assign it to the tail. This information will be used in the
//invalidation stage to the correct number of FLITs
target_crc_comb = target_crc_temp;
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
if(d_in_hdr_dly[i_f]) begin
target_crc_comb = d_in_flit_target_crc[i_f];
end
if(d_in_tail_dly[i_f]) begin
target_crc_per_tail_comb[i_f] = target_crc_comb;
end else begin
target_crc_per_tail_comb[i_f] = {4{1'b0}};
end
end
end
//Register combinational values
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
target_crc_per_tail[i_f] <= 0;
end
target_crc_temp <= {4{1'b0}};
end else begin
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
target_crc_per_tail[i_f] <= target_crc_per_tail_comb[i_f];
end
target_crc_temp <= target_crc_comb;
end
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------LOGIC STARTS HERE---------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//====================================================================
//---------------------------------Assign input data stream to target CRCs
//====================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
d_in_flit_target_crc[i_f] <= {LOG_FPW{1'b0}};
end
swap_crc <= 1'b0;
end else begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
d_in_flit_target_crc[i_f] <= {LOG_FPW{1'b0}};
end
//Reset if seen a tail
if(|d_in_tail) begin
swap_crc <= 1'b0;
end
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
if(d_in_hdr[i_f])begin
if(i_f+lng(d_in_flit[i_f])>FPW) begin
//If the current packet spreads over multiple cycles
if(swap_crc) begin
//If the last packet was swapped and the current packet also spreads over the more than 1 cycle use crc 0 now
d_in_flit_target_crc[i_f] <= 3'h0;
end else begin
d_in_flit_target_crc[i_f] <= FPW-1'b1;
swap_crc <= 1'b1;
end
end else begin
d_in_flit_target_crc[i_f] <= i_f;
//If the highest order CRC contains a data packet that ends in this cycle, dont use this crc
//It's ok always to decrement by 1 since we know the lowest order CRC would not be used (at least FLIT0 goes to highest order CRC)
if(swap_crc && !(d_in_hdr > d_in_tail)) begin
d_in_flit_target_crc[i_f] <= i_f-1;
end
end
end
end
end
end
//Register input values to be used in CRC assignment logic after crc init stage
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
d_in_flit_lng_dly[i_f] <= 4'h0;
end
d_in_data_dly <= {DWIDTH{1'b0}};
d_in_tail_dly <= {FPW{1'b0}};
d_in_hdr_dly <= {FPW{1'b0}};
end else begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
d_in_flit_lng_dly[i_f] <= lng(d_in_flit[i_f]);
end
d_in_data_dly <= d_in_data;
d_in_tail_dly <= d_in_tail;
d_in_hdr_dly <= d_in_hdr;
end
end
//====================================================================
//---------------------------------Inter CRC stage, CRC assignment Logic
//====================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
crc_accu_in[i_f] <= {32{1'b0}};
crc_accu_in_valid[i_f] <= {FPW{1'b0}};
crc_accu_in_tail[i_f] <= {FPW{1'b0}};
payload_remain[i_f] <= 4'h0;
end
end else begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
crc_accu_in[i_f] <= crc_init_out[i_f];
crc_accu_in_valid[i_f] <= 4'h0;
crc_accu_in_tail[i_f] <= 4'h0;
end
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
//First go through accu crcs
if(|payload_remain[i_f]) begin
if(payload_remain[i_f] > FPW) begin
crc_accu_in_valid[i_f] <= {FPW{1'b1}};
payload_remain[i_f] <= payload_remain[i_f]-FPW;
end else begin
crc_accu_in_valid[i_f] <= {FPW{1'b1}} >> (FPW-payload_remain[i_f]);
crc_accu_in_tail[i_f] <= 1'b1 << (payload_remain[i_f]-1);
payload_remain[i_f] <= 4'h0;
end
end
for(i_f2=0;i_f2<FPW;i_f2=i_f2+1)begin
if(i_f==d_in_flit_target_crc[i_f2] && d_in_hdr_dly[i_f2]) begin
//Then go through all input crcs from the init crc and find the crc's that must be assigned to the currently selected crc
if( (i_f2+d_in_flit_lng_dly[i_f2]) >FPW ) begin
payload_remain[i_f] <= (d_in_flit_lng_dly[i_f2]-FPW+i_f2);
crc_accu_in_valid[i_f] <= {FPW{1'b1}} >> i_f2 << i_f2;
end else begin
crc_accu_in_tail[i_f] <= 1'b1 << d_in_flit_lng_dly[i_f2]+i_f2-1;
crc_accu_in_valid[i_f] <= ({FPW{1'b1}} >> (FPW-i_f2-d_in_flit_lng_dly[i_f2])) >> i_f2 << i_f2;
end
end
end
end
end
end
//====================================================================
//---------------------------------Constant propagation of the data pipeline
//====================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_c=0;i_c<2;i_c=i_c+1)begin
crc_data_pipe_in_data[i_c] <= {DWIDTH{1'b0}};
crc_data_pipe_in_tail[i_c] <= {FPW{1'b0}};
end
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
target_crc_per_tail1[i_f] <= 3'h0;
end
end else begin
//We keep the tails per FLIT so they are not part of the data pipe
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
target_crc_per_tail1[i_f] <= target_crc_per_tail[i_f];
end
//Set the first stage of the data pipeline
crc_data_pipe_in_data[0] <= d_in_data_dly;
crc_data_pipe_in_tail[0] <= d_in_tail_dly;
//Data Pipeline propagation
for(i_c=0;i_c<(1);i_c=i_c+1)begin
crc_data_pipe_in_data[i_c+1] <= crc_data_pipe_in_data[i_c];
crc_data_pipe_in_tail[i_c+1] <= crc_data_pipe_in_tail[i_c];
end
end
end
//====================================================================
//---------------------------------At the end of the data pipeline get and add CRCs
//====================================================================
//Data Pipeline output stage to final FLIT reg
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
data_rdy_flit[i_f] <= {128{1'b0}};
end
end else begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
data_rdy_flit[i_f] <= crc_data_pipe_out_data_flit[i_f];
if(crc_data_pipe_in_tail[1][i_f])begin //Finally add the crc
data_rdy_flit[i_f][128-1:128-32] <= crc_per_flit[target_crc_per_tail1[i_f]];
end
end
end
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//Init CRC: Calculate the remainders of each input FLIT individually
generate
for(f=0;f<FPW;f=f+1) begin : crc_init_gen
crc_128_init crc_init_I
(
.clk(clk),
.res_n(res_n),
.inData(d_in_flit[f]),
.crc(crc_init_out[f])
);
end
endgenerate
//Calculate the actual CRC over all valid remainders
generate
for(f=0;f<FPW;f=f+1) begin : crc_accu_gen
crc_accu #(
.FPW(FPW)
)
crc_accu_I
(
.clk(clk),
.res_n(res_n),
.tail(crc_accu_in_tail[f]),
.d_in(crc_accu_in_combined[f]),
.valid(crc_accu_in_valid[f]),
.crc_out(crc_per_flit[f])
);
end
endgenerate
endmodule
`default_nettype wire |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX4_BLACKBOX_V
`define SKY130_FD_SC_HS__MUX4_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX4_BLACKBOX_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:27:51 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n1701, Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP,
ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1,
left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM,
SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n511, n512, n513, n514, n515,
n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526,
n527, n528, n529, n530, n531, n532, n533, n534, n535, n536, n537,
n538, n539, n540, n541, n542, n543, n544, n545, n546, n547, n548,
n549, n550, n551, n552, n553, n554, n555, n556, n557, n558, n559,
n560, n561, n562, n563, n564, n565, n566, n567, n568, n569, n570,
n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581,
n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592,
n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603,
n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614,
n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625,
n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636,
n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647,
n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658,
n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669,
n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680,
n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691,
n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702,
n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713,
n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724,
n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746,
n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768,
n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779,
n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790,
n791, n792, n793, n794, n795, n796, n797, n798, n799, n800, n801,
n802, n803, n804, n805, n806, n807, n808, n809, n810, n811, n812,
n813, n814, n815, n817, n818, n819, n820, n821, n822, n823, n824,
n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846,
n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857,
n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868,
n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879,
n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890,
n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901,
n902, n903, n904, n905, n906, n907, n908, n909, n910, n912, n914,
n915, n916, n917, n918, n919, DP_OP_15J34_125_2314_n8,
DP_OP_15J34_125_2314_n7, DP_OP_15J34_125_2314_n6,
DP_OP_15J34_125_2314_n5, DP_OP_15J34_125_2314_n4, intadd_35_B_12_,
intadd_35_B_11_, intadd_35_B_10_, intadd_35_B_9_, intadd_35_B_8_,
intadd_35_B_7_, intadd_35_B_6_, intadd_35_B_5_, intadd_35_B_4_,
intadd_35_B_3_, intadd_35_B_2_, intadd_35_B_1_, intadd_35_B_0_,
intadd_35_CI, intadd_35_SUM_12_, intadd_35_SUM_11_, intadd_35_SUM_10_,
intadd_35_SUM_9_, intadd_35_SUM_8_, intadd_35_SUM_7_,
intadd_35_SUM_6_, intadd_35_SUM_5_, intadd_35_SUM_4_,
intadd_35_SUM_3_, intadd_35_SUM_2_, intadd_35_SUM_1_,
intadd_35_SUM_0_, intadd_35_n13, intadd_35_n12, intadd_35_n11,
intadd_35_n10, intadd_35_n9, intadd_35_n8, intadd_35_n7, intadd_35_n6,
intadd_35_n5, intadd_35_n4, intadd_35_n3, intadd_35_n2, intadd_35_n1,
intadd_36_B_2_, intadd_36_B_1_, intadd_36_B_0_, intadd_36_CI,
intadd_36_SUM_2_, intadd_36_SUM_1_, intadd_36_SUM_0_, intadd_36_n3,
intadd_36_n2, intadd_36_n1, intadd_37_B_2_, intadd_37_B_1_,
intadd_37_B_0_, intadd_37_CI, intadd_37_SUM_2_, intadd_37_SUM_1_,
intadd_37_SUM_0_, intadd_37_n3, intadd_37_n2, intadd_37_n1, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429,
n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439,
n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449,
n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459,
n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469,
n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479,
n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489,
n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499,
n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509,
n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519,
n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529,
n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549,
n1550, n1551, n1552, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1700;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:2] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:1] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n914), .CK(clk), .RN(n1665), .QN(
n941) );
DFFRXLTS inst_ShiftRegister_Q_reg_1_ ( .D(n912), .CK(clk), .RN(n1668), .Q(
Shift_reg_FLAGS_7[1]), .QN(n925) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n878), .CK(clk), .RN(n1666), .Q(
intAS) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n813), .CK(clk), .RN(n1694),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n812), .CK(clk), .RN(n1692),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n811), .CK(clk), .RN(n1693),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n810), .CK(clk), .RN(n1688),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n801), .CK(clk), .RN(n1667), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n800), .CK(clk), .RN(n1687), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n799), .CK(clk), .RN(n1693), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n798), .CK(clk), .RN(n1685), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n797), .CK(clk), .RN(n1688), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n796), .CK(clk), .RN(n1685), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n795), .CK(clk), .RN(n1683), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n794), .CK(clk), .RN(n1695), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n793), .CK(clk), .RN(n1690), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n792), .CK(clk), .RN(n1693), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n791), .CK(clk), .RN(n1691), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n790), .CK(clk), .RN(n1680), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n789), .CK(clk), .RN(n1682), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n788), .CK(clk), .RN(n1690), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n787), .CK(clk), .RN(n1687), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1671), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n785), .CK(clk), .RN(n1667), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n784), .CK(clk), .RN(n1695), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n783), .CK(clk), .RN(n1689), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n782), .CK(clk), .RN(n1672), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n781), .CK(clk), .RN(n1693), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n780), .CK(clk), .RN(n1676), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n779), .CK(clk), .RN(n1673), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n774), .CK(clk), .RN(n1675), .QN(n949)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n773), .CK(clk), .RN(n1029), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n772), .CK(clk), .RN(n962), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n771), .CK(clk), .RN(n1676), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n770), .CK(clk), .RN(n1673), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n769), .CK(clk), .RN(n1675), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n768), .CK(clk), .RN(n1678), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n767), .CK(clk), .RN(n1677), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1674), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n764), .CK(clk), .RN(n1673), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n763), .CK(clk), .RN(n1676), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n761), .CK(clk), .RN(n1675), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n760), .CK(clk), .RN(n1678), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n759), .CK(clk), .RN(n1676), .Q(
DMP_SFG[2]), .QN(n1646) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n758), .CK(clk), .RN(n1677), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n757), .CK(clk), .RN(n1674), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n755), .CK(clk), .RN(n1674), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n754), .CK(clk), .RN(n962), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n752), .CK(clk), .RN(n1676), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n751), .CK(clk), .RN(n1673), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n749), .CK(clk), .RN(n1675), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n748), .CK(clk), .RN(n1029), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1678), .QN(n932)
);
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1677), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n745), .CK(clk), .RN(n1674), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n743), .CK(clk), .RN(n962), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n742), .CK(clk), .RN(n1676), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n740), .CK(clk), .RN(n1673), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n739), .CK(clk), .RN(n1675), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n737), .CK(clk), .RN(n1029), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n736), .CK(clk), .RN(n1678), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n735), .CK(clk), .RN(n962), .Q(
DMP_SFG[10]), .QN(n1594) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n734), .CK(clk), .RN(n1677), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n733), .CK(clk), .RN(n1674), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n732), .CK(clk), .RN(n1678), .Q(
DMP_SFG[11]), .QN(n1593) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n731), .CK(clk), .RN(n1673), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n730), .CK(clk), .RN(n1675), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n729), .CK(clk), .RN(n1674), .Q(
DMP_SFG[12]), .QN(n1605) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n728), .CK(clk), .RN(n1678), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n727), .CK(clk), .RN(n1677), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n726), .CK(clk), .RN(n1677), .Q(
DMP_SFG[13]), .QN(n1604) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n725), .CK(clk), .RN(n1674), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n724), .CK(clk), .RN(n1676), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n723), .CK(clk), .RN(n1676), .Q(
DMP_SFG[14]), .QN(n1610) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n722), .CK(clk), .RN(n1673), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n721), .CK(clk), .RN(n1675), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n720), .CK(clk), .RN(n1673), .Q(
DMP_SFG[15]), .QN(n1628) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n719), .CK(clk), .RN(n1673), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n718), .CK(clk), .RN(n1675), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n717), .CK(clk), .RN(n1675), .Q(
DMP_SFG[16]), .QN(n1627) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n716), .CK(clk), .RN(n1029), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n715), .CK(clk), .RN(n1678), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n714), .CK(clk), .RN(n1029), .Q(
DMP_SFG[17]), .QN(n1639) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n713), .CK(clk), .RN(n1677), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n712), .CK(clk), .RN(n1674), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n711), .CK(clk), .RN(n1678), .Q(
DMP_SFG[18]), .QN(n1638) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n710), .CK(clk), .RN(n962), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n709), .CK(clk), .RN(n1676), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n708), .CK(clk), .RN(n1686), .Q(
DMP_SFG[19]), .QN(n1648) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n707), .CK(clk), .RN(n1694), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n706), .CK(clk), .RN(n1664), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n705), .CK(clk), .RN(n1692), .Q(
DMP_SFG[20]), .QN(n1647) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n704), .CK(clk), .RN(n1679), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n703), .CK(clk), .RN(n1681), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n702), .CK(clk), .RN(n1694), .Q(
DMP_SFG[21]), .QN(n1661) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n701), .CK(clk), .RN(n1683), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n700), .CK(clk), .RN(n1684), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n699), .CK(clk), .RN(n1679), .Q(
DMP_SFG[22]), .QN(n1660) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n698), .CK(clk), .RN(n1685), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n697), .CK(clk), .RN(n1669), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n696), .CK(clk), .RN(n1689), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n695), .CK(clk), .RN(n1672), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n693), .CK(clk), .RN(n1693), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n692), .CK(clk), .RN(n1691), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n691), .CK(clk), .RN(n1680), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n690), .CK(clk), .RN(n1682), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n688), .CK(clk), .RN(n1690), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n687), .CK(clk), .RN(n1687), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n686), .CK(clk), .RN(n1671), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n685), .CK(clk), .RN(n1667), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n683), .CK(clk), .RN(n1695), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n682), .CK(clk), .RN(n1689), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n681), .CK(clk), .RN(n1683), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n680), .CK(clk), .RN(n1688), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n678), .CK(clk), .RN(n1664), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n677), .CK(clk), .RN(n1684), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n676), .CK(clk), .RN(n1685), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n675), .CK(clk), .RN(n1669), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n673), .CK(clk), .RN(n1686), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n672), .CK(clk), .RN(n1669), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n671), .CK(clk), .RN(n1686), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n670), .CK(clk), .RN(n1685), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n668), .CK(clk), .RN(n1688), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n667), .CK(clk), .RN(n1692), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n666), .CK(clk), .RN(n1691), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n665), .CK(clk), .RN(n1680), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n663), .CK(clk), .RN(n1682), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n662), .CK(clk), .RN(n1690), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n661), .CK(clk), .RN(n1687), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n660), .CK(clk), .RN(n1671), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n658), .CK(clk), .RN(n1690), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n657), .CK(clk), .RN(n1687), .QN(
n943) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n656), .CK(clk), .RN(n1671), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n655), .CK(clk), .RN(n1667), .QN(
n944) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n654), .CK(clk), .RN(n1695), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n652), .CK(clk), .RN(n1679), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n651), .CK(clk), .RN(n1681), .QN(
n947) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n650), .CK(clk), .RN(n1683), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n649), .CK(clk), .RN(n1684), .QN(
n930) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n648), .CK(clk), .RN(n1669), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n647), .CK(clk), .RN(n1686), .QN(
n945) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n646), .CK(clk), .RN(n1685), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n645), .CK(clk), .RN(n1692), .QN(
n927) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n644), .CK(clk), .RN(n1694), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n643), .CK(clk), .RN(n1679), .QN(
n948) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n642), .CK(clk), .RN(n1681), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n640), .CK(clk), .RN(n1685), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n639), .CK(clk), .RN(n1692), .QN(
n946) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n638), .CK(clk), .RN(n1694), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n636), .CK(clk), .RN(n1679), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n635), .CK(clk), .RN(n1681),
.QN(n928) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n634), .CK(clk), .RN(n1683), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n632), .CK(clk), .RN(n1664), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n631), .CK(clk), .RN(n1688),
.QN(n929) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n630), .CK(clk), .RN(n1684), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n628), .CK(clk), .RN(n1683), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n626), .CK(clk), .RN(n1672), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n624), .CK(clk), .RN(n1686), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n622), .CK(clk), .RN(n1672), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n620), .CK(clk), .RN(n1686), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n618), .CK(clk), .RN(n1681), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n616), .CK(clk), .RN(n1680), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n614), .CK(clk), .RN(n1694), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n605), .CK(clk), .RN(n1669), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n604), .CK(clk), .RN(n1664), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n1669), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n1691), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n601), .CK(clk), .RN(n1667), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n599), .CK(clk), .RN(n1684), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n598), .CK(clk), .RN(n1695), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n596), .CK(clk), .RN(n1679), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n595), .CK(clk), .RN(n1680), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n594), .CK(clk), .RN(n1686), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n593), .CK(clk), .RN(n1684), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n592), .CK(clk), .RN(n1693), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n576), .CK(clk), .RN(n1689), .QN(
n933) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n574), .CK(clk), .RN(n1687), .Q(
LZD_output_NRM2_EW[4]), .QN(n1611) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n573), .CK(clk), .RN(n1682), .Q(
DmP_mant_SFG_SWR[1]), .QN(n992) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n571), .CK(clk), .RN(n1682), .Q(
LZD_output_NRM2_EW[2]), .QN(n1607) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n570), .CK(clk), .RN(n1689), .Q(
DmP_mant_SFG_SWR[8]), .QN(n994) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n566), .CK(clk), .RN(n1671), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n564), .CK(clk), .RN(n1669), .QN(
n937) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n560), .CK(clk), .RN(n1690), .Q(
LZD_output_NRM2_EW[3]), .QN(n1606) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n559), .CK(clk), .RN(n1671), .Q(
LZD_output_NRM2_EW[1]), .QN(n1595) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n537), .CK(clk), .RN(n1694), .QN(
n931) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n534), .CK(clk), .RN(n1679), .QN(
n939) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n519), .CK(clk), .RN(n1671), .Q(
DmP_mant_SFG_SWR[17]), .QN(n996) );
CMPR32X2TS intadd_35_U14 ( .A(n1594), .B(intadd_35_B_0_), .C(intadd_35_CI),
.CO(intadd_35_n13), .S(intadd_35_SUM_0_) );
CMPR32X2TS intadd_35_U13 ( .A(n1593), .B(intadd_35_B_1_), .C(intadd_35_n13),
.CO(intadd_35_n12), .S(intadd_35_SUM_1_) );
CMPR32X2TS intadd_35_U12 ( .A(n1605), .B(intadd_35_B_2_), .C(intadd_35_n12),
.CO(intadd_35_n11), .S(intadd_35_SUM_2_) );
CMPR32X2TS intadd_35_U11 ( .A(n1604), .B(intadd_35_B_3_), .C(intadd_35_n11),
.CO(intadd_35_n10), .S(intadd_35_SUM_3_) );
CMPR32X2TS intadd_35_U10 ( .A(n1610), .B(intadd_35_B_4_), .C(intadd_35_n10),
.CO(intadd_35_n9), .S(intadd_35_SUM_4_) );
CMPR32X2TS intadd_35_U9 ( .A(n1628), .B(intadd_35_B_5_), .C(intadd_35_n9),
.CO(intadd_35_n8), .S(intadd_35_SUM_5_) );
CMPR32X2TS intadd_35_U8 ( .A(n1627), .B(intadd_35_B_6_), .C(intadd_35_n8),
.CO(intadd_35_n7), .S(intadd_35_SUM_6_) );
CMPR32X2TS intadd_35_U7 ( .A(n1639), .B(intadd_35_B_7_), .C(intadd_35_n7),
.CO(intadd_35_n6), .S(intadd_35_SUM_7_) );
CMPR32X2TS intadd_35_U6 ( .A(n1638), .B(intadd_35_B_8_), .C(intadd_35_n6),
.CO(intadd_35_n5), .S(intadd_35_SUM_8_) );
CMPR32X2TS intadd_35_U5 ( .A(n1648), .B(intadd_35_B_9_), .C(intadd_35_n5),
.CO(intadd_35_n4), .S(intadd_35_SUM_9_) );
CMPR32X2TS intadd_35_U4 ( .A(n1647), .B(intadd_35_B_10_), .C(intadd_35_n4),
.CO(intadd_35_n3), .S(intadd_35_SUM_10_) );
CMPR32X2TS intadd_35_U3 ( .A(n1661), .B(intadd_35_B_11_), .C(intadd_35_n3),
.CO(intadd_35_n2), .S(intadd_35_SUM_11_) );
CMPR32X2TS intadd_35_U2 ( .A(n1660), .B(intadd_35_B_12_), .C(intadd_35_n2),
.CO(intadd_35_n1), .S(intadd_35_SUM_12_) );
CMPR32X2TS intadd_36_U4 ( .A(n1646), .B(intadd_36_B_0_), .C(intadd_36_CI),
.CO(intadd_36_n3), .S(intadd_36_SUM_0_) );
CMPR32X2TS intadd_36_U3 ( .A(n940), .B(intadd_36_B_1_), .C(intadd_36_n3),
.CO(intadd_36_n2), .S(intadd_36_SUM_1_) );
CMPR32X2TS intadd_36_U2 ( .A(n1645), .B(intadd_36_B_2_), .C(intadd_36_n2),
.CO(intadd_36_n1), .S(intadd_36_SUM_2_) );
CMPR32X2TS intadd_37_U4 ( .A(n980), .B(intadd_37_B_0_), .C(intadd_37_CI),
.CO(intadd_37_n3), .S(intadd_37_SUM_0_) );
CMPR32X2TS intadd_37_U3 ( .A(DMP_SFG[7]), .B(intadd_37_B_1_), .C(
intadd_37_n3), .CO(intadd_37_n2), .S(intadd_37_SUM_1_) );
CMPR32X2TS intadd_37_U2 ( .A(DMP_SFG[8]), .B(intadd_37_B_2_), .C(
intadd_37_n2), .CO(intadd_37_n1), .S(intadd_37_SUM_2_) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1668),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n600), .CK(clk), .RN(n1671), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n549), .CK(clk), .RN(n1682), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n548), .CK(clk), .RN(n1690), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n541), .CK(clk), .RN(n1687), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n540), .CK(clk), .RN(n1671), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n529), .CK(clk), .RN(n1681), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n528), .CK(clk), .RN(n1683), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n525), .CK(clk), .RN(n1682), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1672), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1683), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n552), .CK(clk), .RN(n1680), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n551), .CK(clk), .RN(n1664), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n547), .CK(clk), .RN(n1667), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n546), .CK(clk), .RN(n1695), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n544), .CK(clk), .RN(n1689), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n543), .CK(clk), .RN(n1672), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n539), .CK(clk), .RN(n1693), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n538), .CK(clk), .RN(n1690), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n536), .CK(clk), .RN(n1688), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n535), .CK(clk), .RN(n1664), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n533), .CK(clk), .RN(n1684), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n532), .CK(clk), .RN(n1669), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n531), .CK(clk), .RN(n1686), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n530), .CK(clk), .RN(n1685), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n527), .CK(clk), .RN(n1692), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n526), .CK(clk), .RN(n1694), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n809), .CK(clk), .RN(n1680), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n808), .CK(clk), .RN(n1688), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n807), .CK(clk), .RN(n1664), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n806), .CK(clk), .RN(n1684), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n805), .CK(clk), .RN(n1669), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n804), .CK(clk), .RN(n1686), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n803), .CK(clk), .RN(n1685), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n802), .CK(clk), .RN(n1685), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n591), .CK(clk), .RN(n1669), .Q(
final_result_ieee[31]) );
DFFSX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n993), .CK(clk), .SN(n1031), .Q(
n1696), .QN(Shift_reg_FLAGS_7[0]) );
DFFSX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n926), .CK(clk), .SN(n1030), .Q(
n1698), .QN(n1697) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1665), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1567) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n916), .CK(clk), .RN(n1666), .Q(
n1560), .QN(n1659) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n561), .CK(clk), .RN(n1672), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1634) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n555), .CK(clk), .RN(n1669), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1588) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n568), .CK(clk), .RN(n1690), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1597) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n575), .CK(clk), .RN(n1686), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1581) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n588), .CK(clk), .RN(n1671), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1580) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n873), .CK(clk), .RN(n1670), .Q(
intDY_EWSW[3]), .QN(n1612) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n854), .CK(clk), .RN(n1669),
.Q(intDY_EWSW[22]), .QN(n1570) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n855), .CK(clk), .RN(n1670),
.Q(intDY_EWSW[21]), .QN(n1616) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n850), .CK(clk), .RN(n962), .Q(
intDY_EWSW[26]), .QN(n1629) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n851), .CK(clk), .RN(n1665),
.Q(intDY_EWSW[25]), .QN(n1630) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n858), .CK(clk), .RN(n1668),
.Q(intDY_EWSW[18]), .QN(n1636) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n859), .CK(clk), .RN(n1670),
.Q(intDY_EWSW[17]), .QN(n1632) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n861), .CK(clk), .RN(n1666),
.Q(intDY_EWSW[15]), .QN(n1631) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n862), .CK(clk), .RN(n1666),
.Q(intDY_EWSW[14]), .QN(n1569) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n863), .CK(clk), .RN(n1665),
.Q(intDY_EWSW[13]), .QN(n1615) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n864), .CK(clk), .RN(n1692),
.Q(intDY_EWSW[12]), .QN(n1619) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n868), .CK(clk), .RN(n1687), .Q(
intDY_EWSW[8]), .QN(n1633) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n882), .CK(clk), .RN(n1670),
.Q(intDX_EWSW[28]), .QN(n1635) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n884), .CK(clk), .RN(n961), .Q(
intDX_EWSW[26]), .QN(n1578) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n885), .CK(clk), .RN(n1686),
.Q(intDX_EWSW[25]), .QN(n1577) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n886), .CK(clk), .RN(n1680),
.Q(intDX_EWSW[24]), .QN(n1653) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n894), .CK(clk), .RN(n1689),
.Q(intDX_EWSW[16]), .QN(n1596) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n903), .CK(clk), .RN(n1668), .Q(
intDX_EWSW[7]), .QN(n1563) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n904), .CK(clk), .RN(n1666), .Q(
intDX_EWSW[6]), .QN(n1589) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n905), .CK(clk), .RN(n1665), .Q(
intDX_EWSW[5]), .QN(n1587) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n906), .CK(clk), .RN(n1668), .Q(
intDX_EWSW[4]), .QN(n1562) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n586), .CK(clk), .RN(n1664), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1643) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n815), .CK(clk), .RN(n1665), .Q(
shift_value_SHT2_EWR[4]), .QN(n1566) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n844), .CK(clk), .RN(n1694), .Q(
Data_array_SWR[25]), .QN(n1573) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n831), .CK(clk), .RN(n1681), .Q(
Data_array_SWR[12]), .QN(n1652) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n659), .CK(clk), .RN(n1030), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1637) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n664), .CK(clk), .RN(n1031), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1626) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n669), .CK(clk), .RN(n1671), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1609) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n694), .CK(clk), .RN(n1672), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1592) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n562), .CK(clk), .RN(n1691), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1585) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n753), .CK(clk), .RN(n1674), .Q(
DMP_SFG[4]), .QN(n1645) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n741), .CK(clk), .RN(n1676), .Q(
DMP_SFG[8]), .QN(n1583) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n918), .CK(clk), .RN(
n1668), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1608) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n590), .CK(clk), .RN(n1672), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1582) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n554), .CK(clk), .RN(n1694), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1584) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n846), .CK(clk), .RN(n1670),
.Q(intDY_EWSW[30]), .QN(n1602) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n567), .CK(clk), .RN(n1695), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1586) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n871), .CK(clk), .RN(n1674), .Q(
intDY_EWSW[5]), .QN(n1568) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n872), .CK(clk), .RN(n1665), .Q(
intDY_EWSW[4]), .QN(n1618) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n849), .CK(clk), .RN(n1666),
.Q(intDY_EWSW[27]), .QN(n1622) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n852), .CK(clk), .RN(n1668),
.Q(intDY_EWSW[24]), .QN(n1559) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n853), .CK(clk), .RN(n1670),
.Q(intDY_EWSW[23]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n857), .CK(clk), .RN(n1666),
.Q(intDY_EWSW[19]), .QN(n1572) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n860), .CK(clk), .RN(n1680),
.Q(intDY_EWSW[16]), .QN(n1620) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n867), .CK(clk), .RN(n1668), .Q(
intDY_EWSW[9]), .QN(n1614) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n870), .CK(clk), .RN(n1670), .Q(
intDY_EWSW[6]), .QN(n1613) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n874), .CK(clk), .RN(n1668), .Q(
intDY_EWSW[2]), .QN(n1617) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n869), .CK(clk), .RN(n1666), .Q(
intDY_EWSW[7]), .QN(n1623) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n847), .CK(clk), .RN(n1692),
.Q(intDY_EWSW[29]), .QN(n1565) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n585), .CK(clk), .RN(n1679), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1598) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n581), .CK(clk), .RN(n1669), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1590) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n775), .CK(clk), .RN(n1675), .Q(
DMP_EXP_EWSW[26]), .QN(n1655) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n776), .CK(clk), .RN(n1678), .Q(
DMP_EXP_EWSW[25]), .QN(n1642) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n777), .CK(clk), .RN(n1677), .Q(
DMP_EXP_EWSW[24]), .QN(n1575) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n609), .CK(clk), .RN(n1686), .Q(
DmP_EXP_EWSW[26]), .QN(n1651) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n610), .CK(clk), .RN(n1688), .Q(
DmP_EXP_EWSW[25]), .QN(n1656) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n611), .CK(clk), .RN(n1682), .Q(
DmP_EXP_EWSW[24]), .QN(n1574) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n580), .CK(clk), .RN(n1687), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1561) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n579), .CK(clk), .RN(n1664), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1557) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n578), .CK(clk), .RN(n1681), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1558) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n577), .CK(clk), .RN(n1686), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1579) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n829), .CK(clk), .RN(n1684), .Q(
Data_array_SWR[10]), .QN(n1644) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n841), .CK(clk), .RN(n1687), .Q(
Data_array_SWR[22]), .QN(n1640) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n826), .CK(clk), .RN(n1693), .Q(
Data_array_SWR[7]), .QN(n1650) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n839), .CK(clk), .RN(n1682), .Q(
Data_array_SWR[20]), .QN(n1657) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n825), .CK(clk), .RN(n1671), .Q(
Data_array_SWR[6]), .QN(n1649) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n833), .CK(clk), .RN(n1669), .Q(
Data_array_SWR[14]), .QN(n1576) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n840), .CK(clk), .RN(n1664), .Q(
Data_array_SWR[21]), .QN(n1625) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n842), .CK(clk), .RN(n1681), .Q(
Data_array_SWR[23]), .QN(n1641) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n828), .CK(clk), .RN(n1691), .Q(
Data_array_SWR[9]), .QN(n1654) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n907), .CK(clk), .RN(n961), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n887), .CK(clk), .RN(n961), .Q(
intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n889), .CK(clk), .RN(n1668),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n897), .CK(clk), .RN(n1670),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n895), .CK(clk), .RN(n1670),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n902), .CK(clk), .RN(n1666), .Q(
intDX_EWSW[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n582), .CK(clk), .RN(n1687), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n843), .CK(clk), .RN(n1690), .Q(
Data_array_SWR[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n893), .CK(clk), .RN(n1666),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n899), .CK(clk), .RN(n1668),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n901), .CK(clk), .RN(n1665), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n883), .CK(clk), .RN(n1670),
.Q(intDX_EWSW[27]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n556), .CK(clk), .RN(n1671), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n832), .CK(clk), .RN(n1693), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n587), .CK(clk), .RN(n1689), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n589), .CK(clk), .RN(n1679), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n910), .CK(clk), .RN(n1685), .Q(
intDX_EWSW[0]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n583), .CK(clk), .RN(n1688), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n569), .CK(clk), .RN(n1684), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n892), .CK(clk), .RN(n1665),
.Q(intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n572), .CK(clk), .RN(n1690), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n834), .CK(clk), .RN(n962), .Q(
Data_array_SWR[15]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n919), .CK(clk), .RN(
n1691), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n838), .CK(clk), .RN(n1670), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n827), .CK(clk), .RN(n1683), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n837), .CK(clk), .RN(n1666), .Q(
Data_array_SWR[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n584), .CK(clk), .RN(n1667), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n835), .CK(clk), .RN(n1668), .Q(
Data_array_SWR[16]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n738), .CK(clk), .RN(n1029), .Q(
DMP_SFG[9]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n823), .CK(clk), .RN(n1671), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n824), .CK(clk), .RN(n1689), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n762), .CK(clk), .RN(n1678), .Q(
DMP_SFG[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n744), .CK(clk), .RN(n1673), .Q(
DMP_SFG[7]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n879), .CK(clk), .RN(n1665),
.Q(intDX_EWSW[31]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n557), .CK(clk), .RN(n1683), .Q(
Raw_mant_NRM_SWR[4]), .QN(n935) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n880), .CK(clk), .RN(n1670),
.Q(intDX_EWSW[30]), .QN(n1571) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n881), .CK(clk), .RN(n1666),
.Q(intDX_EWSW[29]), .QN(n1624) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n866), .CK(clk), .RN(n1688),
.Q(intDY_EWSW[10]), .QN(n936) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n876), .CK(clk), .RN(n1668), .Q(
intDY_EWSW[0]), .QN(n942) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n750), .CK(clk), .RN(n962), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n765), .CK(clk), .RN(n1677), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n513), .CK(clk), .RN(n1694), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n514), .CK(clk), .RN(n1672), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n517), .CK(clk), .RN(n1667), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n518), .CK(clk), .RN(n1695), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n520), .CK(clk), .RN(n1689), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n521), .CK(clk), .RN(n1693), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n522), .CK(clk), .RN(n1687), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n523), .CK(clk), .RN(n1690), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n524), .CK(clk), .RN(n1671), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n545), .CK(clk), .RN(n1687), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n553), .CK(clk), .RN(n1680), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n558), .CK(clk), .RN(n1690), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n814), .CK(clk), .RN(n1665),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n778), .CK(clk), .RN(n1674), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n679), .CK(clk), .RN(n1667), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n684), .CK(clk), .RN(n1695), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n689), .CK(clk), .RN(n1689), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n821), .CK(clk), .RN(n1670), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n822), .CK(clk), .RN(n1666), .Q(
Data_array_SWR[3]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n865), .CK(clk), .RN(n1667),
.Q(intDY_EWSW[11]), .QN(n1603) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n845), .CK(clk), .RN(n1695),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n898), .CK(clk), .RN(n1685),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n890), .CK(clk), .RN(n1672),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n896), .CK(clk), .RN(n962), .Q(
intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n888), .CK(clk), .RN(n1668),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n909), .CK(clk), .RN(n1665), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n908), .CK(clk), .RN(n1682), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n900), .CK(clk), .RN(n1666),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n848), .CK(clk), .RN(n1678),
.Q(intDY_EWSW[28]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n891), .CK(clk), .RN(n1670),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n836), .CK(clk), .RN(n1665), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n830), .CK(clk), .RN(n1695), .Q(
Data_array_SWR[11]) );
DFFRX2TS inst_ShiftRegister_Q_reg_4_ ( .D(n915), .CK(clk), .RN(n961), .Q(
n1701), .QN(n1700) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n875), .CK(clk), .RN(n1681), .Q(
intDY_EWSW[1]), .QN(n1663) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n641), .CK(clk), .RN(n1685), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n637), .CK(clk), .RN(n1669), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n633), .CK(clk), .RN(n1686), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n621), .CK(clk), .RN(n1685), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n629), .CK(clk), .RN(n1685), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n653), .CK(clk), .RN(n1690), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n613), .CK(clk), .RN(n1667), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n615), .CK(clk), .RN(n1664), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n627), .CK(clk), .RN(n1683), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n617), .CK(clk), .RN(n1687), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n619), .CK(clk), .RN(n1684), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n625), .CK(clk), .RN(n1679), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n623), .CK(clk), .RN(n1693), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n563), .CK(clk), .RN(n1692), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n817), .CK(clk), .RN(n962), .Q(
shift_value_SHT2_EWR[3]), .QN(n1599) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n818), .CK(clk), .RN(n1668), .Q(
shift_value_SHT2_EWR[2]), .QN(n1591) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n856), .CK(clk), .RN(n1665),
.Q(intDY_EWSW[20]), .QN(n1621) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n542), .CK(clk), .RN(n1687), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1601) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n612), .CK(clk), .RN(n1679), .Q(
DmP_EXP_EWSW[23]), .QN(n991) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n674), .CK(clk), .RN(n1691), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n819), .CK(clk), .RN(n1670), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n820), .CK(clk), .RN(n1682), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n608), .CK(clk), .RN(n1691), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n756), .CK(clk), .RN(n1677), .Q(
DMP_SFG[3]), .QN(n940) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n565), .CK(clk), .RN(n1681), .Q(
DmP_mant_SFG_SWR[0]), .QN(n995) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n550), .CK(clk), .RN(n1691), .Q(
DmP_mant_SFG_SWR[4]), .QN(n1600) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n516), .CK(clk), .RN(n1691), .Q(
DmP_mant_SFG_SWR[20]), .QN(n997) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n515), .CK(clk), .RN(n1680), .Q(
DmP_mant_SFG_SWR[21]), .QN(n998) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n512), .CK(clk), .RN(n1686), .Q(
DmP_mant_SFG_SWR[24]), .QN(n1658) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n511), .CK(clk), .RN(n1692), .Q(
DmP_mant_SFG_SWR[25]), .QN(n1662) );
ADDFX1TS DP_OP_15J34_125_2314_U8 ( .A(n1595), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J34_125_2314_n8), .CO(DP_OP_15J34_125_2314_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J34_125_2314_U7 ( .A(n1607), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J34_125_2314_n7), .CO(DP_OP_15J34_125_2314_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J34_125_2314_U6 ( .A(n1606), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J34_125_2314_n6), .CO(DP_OP_15J34_125_2314_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J34_125_2314_U5 ( .A(n1611), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J34_125_2314_n5), .CO(DP_OP_15J34_125_2314_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n597), .CK(clk), .RN(n1690), .Q(
OP_FLAG_SFG), .QN(n1564) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n877), .CK(clk), .RN(n1665), .Q(
left_right_SHT2), .QN(n924) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n917), .CK(clk), .RN(n1666), .Q(
Shift_reg_FLAGS_7_6), .QN(n999) );
AOI222X1TS U927 ( .A0(n1527), .A1(left_right_SHT2), .B0(Data_array_SWR[8]),
.B1(n1526), .C0(n1525), .C1(n1524), .Y(n1540) );
AOI222X4TS U928 ( .A0(Data_array_SWR[21]), .A1(n1424), .B0(
Data_array_SWR[17]), .B1(n1425), .C0(Data_array_SWR[25]), .C1(n1423),
.Y(n1488) );
AOI222X4TS U929 ( .A0(Data_array_SWR[21]), .A1(n1477), .B0(
Data_array_SWR[17]), .B1(n1478), .C0(Data_array_SWR[25]), .C1(n1442),
.Y(n1441) );
NOR2XLTS U930 ( .A(n1229), .B(n1384), .Y(n1230) );
AOI31XLTS U931 ( .A0(n1020), .A1(Raw_mant_NRM_SWR[8]), .A2(n1597), .B0(n1345), .Y(n1021) );
BUFX3TS U932 ( .A(n1112), .Y(n920) );
INVX4TS U933 ( .A(n1395), .Y(n921) );
CLKINVX3TS U934 ( .A(n1529), .Y(n1554) );
CLKINVX3TS U935 ( .A(n1520), .Y(n1526) );
INVX3TS U936 ( .A(n955), .Y(n922) );
CLKBUFX2TS U937 ( .A(n1621), .Y(n965) );
INVX1TS U938 ( .A(LZD_output_NRM2_EW[0]), .Y(n1327) );
CLKBUFX2TS U939 ( .A(n1663), .Y(n983) );
AOI211X1TS U940 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n950), .B0(n1382), .C0(
n1371), .Y(n1376) );
INVX3TS U941 ( .A(n1299), .Y(n1287) );
AOI222X1TS U942 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1370), .B0(n958), .B1(n972), .C0(n1382), .C1(DmP_mant_SHT1_SW[14]), .Y(n1235) );
AOI222X1TS U943 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1370), .B0(n958), .B1(
DmP_mant_SHT1_SW[21]), .C0(n1282), .C1(DmP_mant_SHT1_SW[22]), .Y(n1262) );
AOI222X1TS U944 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1386), .B0(n957), .B1(n975), .C0(n1282), .C1(n969), .Y(n1300) );
AOI222X1TS U945 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1370), .B0(n957), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1282), .C1(DmP_mant_SHT1_SW[17]), .Y(n1294) );
INVX3TS U946 ( .A(n1374), .Y(n1386) );
INVX3TS U947 ( .A(n1374), .Y(n1370) );
AND2X2TS U948 ( .A(n1227), .B(n1395), .Y(n1228) );
NOR2X1TS U949 ( .A(n1314), .B(n1309), .Y(n1313) );
INVX3TS U950 ( .A(n920), .Y(n1207) );
INVX3TS U951 ( .A(n920), .Y(n1413) );
INVX3TS U952 ( .A(n1151), .Y(n1411) );
INVX3TS U953 ( .A(n1151), .Y(n1142) );
NOR2X4TS U954 ( .A(n1111), .B(n999), .Y(n1112) );
NOR3X1TS U955 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1218),
.Y(n1003) );
AO21X1TS U956 ( .A0(n1015), .A1(Raw_mant_NRM_SWR[18]), .B0(n1337), .Y(n1016)
);
INVX3TS U957 ( .A(n1024), .Y(n958) );
AO22XLTS U958 ( .A0(n1359), .A1(add_subt), .B0(n963), .B1(intAS), .Y(n878)
);
OR2X1TS U959 ( .A(n951), .B(Shift_amount_SHT1_EWR[0]), .Y(n1024) );
NAND2BXLTS U960 ( .AN(intadd_36_CI), .B(DMP_SFG[2]), .Y(n1427) );
AOI211XLTS U961 ( .A0(intDY_EWSW[16]), .A1(n1596), .B0(n1097), .C0(n1161),
.Y(n1089) );
OAI211X2TS U962 ( .A0(intDX_EWSW[20]), .A1(n965), .B0(n1102), .C0(n1088),
.Y(n1097) );
NOR2X6TS U963 ( .A(shift_value_SHT2_EWR[4]), .B(n1481), .Y(n1425) );
NOR2X4TS U964 ( .A(n1482), .B(shift_value_SHT2_EWR[4]), .Y(n938) );
BUFX3TS U965 ( .A(n1359), .Y(n923) );
INVX4TS U966 ( .A(n1470), .Y(n1424) );
INVX3TS U967 ( .A(n1490), .Y(n1423) );
OAI211X2TS U968 ( .A0(intDX_EWSW[12]), .A1(n1619), .B0(n1083), .C0(n1069),
.Y(n1085) );
NAND2X4TS U969 ( .A(n966), .B(n1696), .Y(n1404) );
INVX3TS U970 ( .A(OP_FLAG_SFG), .Y(n1419) );
CLKBUFX3TS U971 ( .A(n1698), .Y(n1462) );
INVX4TS U972 ( .A(rst), .Y(n962) );
NAND2X1TS U973 ( .A(n1018), .B(n1581), .Y(n1002) );
AOI31XLTS U974 ( .A0(n1015), .A1(Raw_mant_NRM_SWR[16]), .A2(n1598), .B0(
n1014), .Y(n1022) );
NAND2X1TS U975 ( .A(n1330), .B(n1580), .Y(n1001) );
CLKAND2X2TS U976 ( .A(n1331), .B(n1332), .Y(n1330) );
NOR2X1TS U977 ( .A(Raw_mant_NRM_SWR[10]), .B(n1002), .Y(n1020) );
NAND2X1TS U978 ( .A(n1003), .B(n1584), .Y(n1217) );
AO22XLTS U979 ( .A0(DMP_SFG[7]), .A1(intadd_37_B_1_), .B0(intadd_37_CI),
.B1(n980), .Y(n1323) );
NOR2XLTS U980 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .Y(n1005)
);
OAI21XLTS U981 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1003), .Y(n1004) );
NAND2X1TS U982 ( .A(n1020), .B(n1582), .Y(n1218) );
AOI222X1TS U983 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1370), .B0(n958), .B1(n970), .C0(n1282), .C1(n971), .Y(n1279) );
AOI222X1TS U984 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1386), .B0(n958), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1282), .C1(n970), .Y(n1290) );
AOI2BB2XLTS U985 ( .B0(DmP_mant_SFG_SWR[18]), .B1(n1447), .A0N(n1419), .A1N(
DmP_mant_SFG_SWR[18]), .Y(intadd_35_B_6_) );
AOI222X1TS U986 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1370), .B0(n958), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1282), .C1(DmP_mant_SHT1_SW[18]), .Y(n1268) );
AOI222X1TS U987 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1370), .B0(n958), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1282), .C1(DmP_mant_SHT1_SW[16]), .Y(n1253) );
AOI2BB2XLTS U988 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1419), .A0N(n1564), .A1N(
DmP_mant_SFG_SWR[13]), .Y(intadd_35_B_1_) );
AOI2BB2XLTS U989 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n1447), .A0N(n1419), .A1N(
DmP_mant_SFG_SWR[15]), .Y(intadd_35_B_3_) );
AOI222X1TS U990 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1370), .B0(n958), .B1(n973), .C0(n1282), .C1(DmP_mant_SHT1_SW[12]), .Y(n1272) );
AOI222X1TS U991 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1370), .B0(n958), .B1(n974), .C0(n1282), .C1(DmP_mant_SHT1_SW[10]), .Y(n1275) );
AOI222X1TS U992 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1370), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1282), .C0(n958), .C1(DmP_mant_SHT1_SW[19]), .Y(n1265) );
OAI21XLTS U993 ( .A0(n1597), .A1(n1374), .B0(n1291), .Y(n1292) );
OAI21XLTS U994 ( .A0(n935), .A1(n1384), .B0(n1280), .Y(n1281) );
AOI222X1TS U995 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1370), .B0(n958), .B1(n969), .C0(n1282), .C1(DmP_mant_SHT1_SW[8]), .Y(n1271) );
OAI21XLTS U996 ( .A0(n1580), .A1(n1384), .B0(n1297), .Y(n1298) );
AOI2BB2XLTS U997 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n1419), .A0N(n1419), .A1N(
DmP_mant_SFG_SWR[23]), .Y(intadd_35_B_11_) );
OAI2BB2XLTS U998 ( .B0(intDY_EWSW[0]), .B1(n1059), .A0N(intDX_EWSW[1]),
.A1N(n983), .Y(n1061) );
NAND2BXLTS U999 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n1060) );
AOI2BB2XLTS U1000 ( .B0(intDX_EWSW[3]), .B1(n1612), .A0N(intDY_EWSW[2]),
.A1N(n1062), .Y(n1063) );
NAND2BXLTS U1001 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1075) );
NAND3XLTS U1002 ( .A(n1633), .B(n1073), .C(intDX_EWSW[8]), .Y(n1074) );
NAND2BXLTS U1003 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1094) );
NOR2XLTS U1004 ( .A(n1105), .B(intDY_EWSW[24]), .Y(n1047) );
NAND2BXLTS U1005 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1048) );
NAND2BXLTS U1006 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1073) );
NAND2BXLTS U1007 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1069) );
NAND2BXLTS U1008 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1088) );
NOR2XLTS U1009 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1006) );
INVX2TS U1010 ( .A(n1478), .Y(n1482) );
AOI221X1TS U1011 ( .A0(n983), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1632), .C0(n1160), .Y(n1167) );
OAI2BB2XLTS U1012 ( .B0(intDY_EWSW[22]), .B1(n1098), .A0N(intDX_EWSW[23]),
.A1N(n982), .Y(n1099) );
OAI211XLTS U1013 ( .A0(n1051), .A1(n1106), .B0(n1050), .C0(n1049), .Y(n1056)
);
NAND2BXLTS U1014 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1049) );
NAND3XLTS U1015 ( .A(n1629), .B(n1048), .C(intDX_EWSW[26]), .Y(n1050) );
NAND2BXLTS U1016 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1103) );
NAND3BXLTS U1017 ( .AN(n1092), .B(n1090), .C(n1089), .Y(n1109) );
OAI21XLTS U1018 ( .A0(n1625), .A1(n1490), .B0(n1489), .Y(n1491) );
OAI21XLTS U1019 ( .A0(n1576), .A1(n1470), .B0(n1469), .Y(n1471) );
NAND2BXLTS U1020 ( .AN(n1308), .B(n1350), .Y(n1309) );
NAND3XLTS U1021 ( .A(n1349), .B(exp_rslt_NRM2_EW1[4]), .C(n1306), .Y(n1308)
);
OAI21XLTS U1022 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1585), .B0(n935), .Y(n1017)
);
NAND2BXLTS U1023 ( .AN(n1217), .B(Raw_mant_NRM_SWR[5]), .Y(n1342) );
AOI221X1TS U1024 ( .A0(n1570), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n982), .C0(n1163), .Y(n1164) );
AOI221X1TS U1025 ( .A0(n965), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]), .B1(
n1616), .C0(n1162), .Y(n1165) );
AOI222X1TS U1026 ( .A0(n1303), .A1(DMP_SFG[1]), .B0(n1303), .B1(n1455), .C0(
DMP_SFG[1]), .C1(n1455), .Y(intadd_36_B_0_) );
AOI2BB2XLTS U1027 ( .B0(DmP_mant_SFG_SWR[19]), .B1(n1447), .A0N(n1419),
.A1N(DmP_mant_SFG_SWR[19]), .Y(intadd_35_B_7_) );
OAI21XLTS U1028 ( .A0(n1634), .A1(n1374), .B0(n1373), .Y(n1375) );
AO22XLTS U1029 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1370), .B0(n988), .B1(n1372),
.Y(n1371) );
AOI2BB2XLTS U1030 ( .B0(DmP_mant_SFG_SWR[22]), .B1(n1447), .A0N(n1419),
.A1N(DmP_mant_SFG_SWR[22]), .Y(intadd_35_B_10_) );
AOI2BB2XLTS U1031 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1419), .A0N(n1564),
.A1N(DmP_mant_SFG_SWR[12]), .Y(intadd_35_CI) );
NAND3XLTS U1032 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1567), .C(
n1608), .Y(n1352) );
OAI21XLTS U1033 ( .A0(n1586), .A1(n1384), .B0(n1379), .Y(n1380) );
OAI21XLTS U1034 ( .A0(n1582), .A1(n1384), .B0(n1383), .Y(n1385) );
AOI2BB2XLTS U1035 ( .B0(DmP_mant_SFG_SWR[16]), .B1(n1447), .A0N(n1447),
.A1N(DmP_mant_SFG_SWR[16]), .Y(intadd_35_B_4_) );
AOI2BB2XLTS U1036 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n1419), .A0N(n1564),
.A1N(DmP_mant_SFG_SWR[14]), .Y(intadd_35_B_2_) );
CLKAND2X2TS U1037 ( .A(n1637), .B(n1311), .Y(n1312) );
OR2X1TS U1038 ( .A(n1321), .B(n1320), .Y(n1414) );
NAND2BXLTS U1039 ( .AN(n1350), .B(n1319), .Y(n1321) );
NAND4BXLTS U1040 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1317), .C(n1316), .D(n1315), .Y(n1318) );
NAND4XLTS U1041 ( .A(n1335), .B(n1338), .C(n1334), .D(n1333), .Y(n1336) );
AOI222X1TS U1042 ( .A0(n1527), .A1(n922), .B0(n1554), .B1(Data_array_SWR[8]),
.C0(n1525), .C1(n1499), .Y(n1523) );
OAI21XLTS U1043 ( .A0(n1219), .A1(n1218), .B0(n1342), .Y(n1220) );
BUFX4TS U1044 ( .A(n1113), .Y(n1213) );
AO22XLTS U1045 ( .A0(n1364), .A1(intDY_EWSW[20]), .B0(n923), .B1(Data_Y[20]),
.Y(n856) );
AO22XLTS U1046 ( .A0(n1556), .A1(n1522), .B0(n1451), .B1(DmP_mant_SFG_SWR[2]), .Y(n563) );
AO22XLTS U1047 ( .A0(n1560), .A1(DmP_EXP_EWSW[17]), .B0(n1659), .B1(
DmP_mant_SHT1_SW[17]), .Y(n623) );
AO22XLTS U1048 ( .A0(n990), .A1(DmP_EXP_EWSW[16]), .B0(n1659), .B1(
DmP_mant_SHT1_SW[16]), .Y(n625) );
AO22XLTS U1049 ( .A0(n1560), .A1(DmP_EXP_EWSW[19]), .B0(n1659), .B1(
DmP_mant_SHT1_SW[19]), .Y(n619) );
AO22XLTS U1050 ( .A0(n1560), .A1(DmP_EXP_EWSW[20]), .B0(n1659), .B1(
DmP_mant_SHT1_SW[20]), .Y(n617) );
AO22XLTS U1051 ( .A0(n1560), .A1(DmP_EXP_EWSW[15]), .B0(n1659), .B1(
DmP_mant_SHT1_SW[15]), .Y(n627) );
AO22XLTS U1052 ( .A0(n1560), .A1(DmP_EXP_EWSW[21]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[21]), .Y(n615) );
AO22XLTS U1053 ( .A0(n1560), .A1(DmP_EXP_EWSW[22]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[22]), .Y(n613) );
AO22XLTS U1054 ( .A0(n990), .A1(DmP_EXP_EWSW[2]), .B0(n1410), .B1(
DmP_mant_SHT1_SW[2]), .Y(n653) );
AO22XLTS U1055 ( .A0(n1560), .A1(DmP_EXP_EWSW[14]), .B0(n1417), .B1(
DmP_mant_SHT1_SW[14]), .Y(n629) );
AO22XLTS U1056 ( .A0(n1560), .A1(DmP_EXP_EWSW[18]), .B0(n1659), .B1(
DmP_mant_SHT1_SW[18]), .Y(n621) );
AO22XLTS U1057 ( .A0(n1560), .A1(DmP_EXP_EWSW[12]), .B0(n1417), .B1(
DmP_mant_SHT1_SW[12]), .Y(n633) );
AO22XLTS U1058 ( .A0(n990), .A1(DmP_EXP_EWSW[10]), .B0(n1410), .B1(
DmP_mant_SHT1_SW[10]), .Y(n637) );
AO22XLTS U1059 ( .A0(n990), .A1(DmP_EXP_EWSW[8]), .B0(n1410), .B1(
DmP_mant_SHT1_SW[8]), .Y(n641) );
AO22XLTS U1060 ( .A0(n1364), .A1(intDY_EWSW[1]), .B0(n1360), .B1(Data_Y[1]),
.Y(n875) );
AOI2BB2XLTS U1061 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1287), .A0N(n1272),
.A1N(n1232), .Y(n1273) );
OAI211XLTS U1062 ( .A0(n1253), .A1(n985), .B0(n1252), .C0(n1251), .Y(n836)
);
AOI2BB2XLTS U1063 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1287), .A0N(n1268), .A1N(
n1232), .Y(n1251) );
AO22XLTS U1064 ( .A0(n1359), .A1(Data_X[19]), .B0(n1362), .B1(intDX_EWSW[19]), .Y(n891) );
AO22XLTS U1065 ( .A0(n964), .A1(Data_Y[28]), .B0(n1361), .B1(intDY_EWSW[28]),
.Y(n848) );
AO22XLTS U1066 ( .A0(n1360), .A1(Data_X[10]), .B0(n1365), .B1(intDX_EWSW[10]), .Y(n900) );
AO22XLTS U1067 ( .A0(n1368), .A1(Data_X[2]), .B0(n1365), .B1(intDX_EWSW[2]),
.Y(n908) );
AO22XLTS U1068 ( .A0(n1368), .A1(Data_X[1]), .B0(n1361), .B1(intDX_EWSW[1]),
.Y(n909) );
AO22XLTS U1069 ( .A0(n923), .A1(Data_X[22]), .B0(n1361), .B1(intDX_EWSW[22]),
.Y(n888) );
AO22XLTS U1070 ( .A0(n1368), .A1(Data_X[14]), .B0(n1366), .B1(intDX_EWSW[14]), .Y(n896) );
AO22XLTS U1071 ( .A0(n923), .A1(Data_X[20]), .B0(n963), .B1(intDX_EWSW[20]),
.Y(n890) );
AO22XLTS U1072 ( .A0(n1360), .A1(Data_X[12]), .B0(n1362), .B1(intDX_EWSW[12]), .Y(n898) );
AO22XLTS U1073 ( .A0(n1360), .A1(Data_Y[31]), .B0(n1362), .B1(intDY_EWSW[31]), .Y(n845) );
AO22XLTS U1074 ( .A0(n1367), .A1(intDY_EWSW[11]), .B0(n964), .B1(Data_Y[11]),
.Y(n865) );
AO22XLTS U1075 ( .A0(n1556), .A1(DMP_SHT2_EWSW[0]), .B0(n1550), .B1(
DMP_SFG[0]), .Y(n765) );
AO22XLTS U1076 ( .A0(n1542), .A1(DMP_SHT2_EWSW[5]), .B0(n1550), .B1(
DMP_SFG[5]), .Y(n750) );
AO22XLTS U1077 ( .A0(n1361), .A1(intDY_EWSW[0]), .B0(n1368), .B1(Data_Y[0]),
.Y(n876) );
AO22XLTS U1078 ( .A0(n1362), .A1(intDY_EWSW[10]), .B0(n964), .B1(Data_Y[10]),
.Y(n866) );
AO22XLTS U1079 ( .A0(n963), .A1(intDX_EWSW[29]), .B0(n1368), .B1(Data_X[29]),
.Y(n881) );
AO22XLTS U1080 ( .A0(n1367), .A1(intDX_EWSW[30]), .B0(n1360), .B1(Data_X[30]), .Y(n880) );
AO22XLTS U1081 ( .A0(n923), .A1(Data_X[31]), .B0(n1361), .B1(intDX_EWSW[31]),
.Y(n879) );
AO22XLTS U1082 ( .A0(n1542), .A1(DMP_SHT2_EWSW[7]), .B0(n1451), .B1(
DMP_SFG[7]), .Y(n744) );
AO22XLTS U1083 ( .A0(n1549), .A1(DMP_SHT2_EWSW[1]), .B0(n1550), .B1(
DMP_SFG[1]), .Y(n762) );
OAI211XLTS U1084 ( .A0(n1279), .A1(n985), .B0(n1278), .C0(n1277), .Y(n824)
);
OAI211XLTS U1085 ( .A0(n1290), .A1(n985), .B0(n1289), .C0(n1288), .Y(n823)
);
AO22XLTS U1086 ( .A0(n1542), .A1(DMP_SHT2_EWSW[9]), .B0(n1451), .B1(
DMP_SFG[9]), .Y(n738) );
OAI21XLTS U1087 ( .A0(n1381), .A1(n985), .B0(n1296), .Y(n835) );
AOI2BB2XLTS U1088 ( .B0(n1461), .B1(intadd_35_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1697), .Y(n584) );
OAI21XLTS U1089 ( .A0(n1377), .A1(n1390), .B0(n1284), .Y(n837) );
OAI21XLTS U1090 ( .A0(n1388), .A1(n1390), .B0(n1302), .Y(n827) );
OAI211XLTS U1091 ( .A0(n1268), .A1(n985), .B0(n1267), .C0(n1266), .Y(n838)
);
AOI2BB2XLTS U1092 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1287), .A0N(n1265), .A1N(
n1390), .Y(n1266) );
OAI211XLTS U1093 ( .A0(n1235), .A1(n985), .B0(n1234), .C0(n1233), .Y(n834)
);
AOI2BB2XLTS U1094 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1287), .A0N(n1253), .A1N(
n1390), .Y(n1233) );
AO22XLTS U1095 ( .A0(n1368), .A1(Data_X[18]), .B0(n1365), .B1(intDX_EWSW[18]), .Y(n892) );
AO22XLTS U1096 ( .A0(n1697), .A1(intadd_37_SUM_0_), .B0(n1466), .B1(
Raw_mant_NRM_SWR[8]), .Y(n569) );
AOI2BB2XLTS U1097 ( .B0(n1461), .B1(intadd_35_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1697), .Y(n583) );
AO22XLTS U1098 ( .A0(n1359), .A1(Data_X[0]), .B0(n1367), .B1(intDX_EWSW[0]),
.Y(n910) );
AOI2BB2XLTS U1099 ( .B0(n1461), .B1(intadd_35_SUM_1_), .A0N(
Raw_mant_NRM_SWR[13]), .A1N(n1697), .Y(n589) );
AOI2BB2XLTS U1100 ( .B0(n1461), .B1(intadd_35_SUM_3_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1697), .Y(n587) );
AOI2BB2XLTS U1101 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1287), .A0N(n1235),
.A1N(n1232), .Y(n1236) );
AO22XLTS U1102 ( .A0(n1359), .A1(Data_X[27]), .B0(n1367), .B1(intDX_EWSW[27]), .Y(n883) );
AO22XLTS U1103 ( .A0(n1363), .A1(Data_X[9]), .B0(n1365), .B1(intDX_EWSW[9]),
.Y(n901) );
AO22XLTS U1104 ( .A0(n923), .A1(Data_X[11]), .B0(n1362), .B1(intDX_EWSW[11]),
.Y(n899) );
AO22XLTS U1105 ( .A0(n1368), .A1(Data_X[17]), .B0(n1365), .B1(intDX_EWSW[17]), .Y(n893) );
AOI2BB2XLTS U1106 ( .B0(n1461), .B1(intadd_35_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1697), .Y(n582) );
AO22XLTS U1107 ( .A0(n923), .A1(Data_X[8]), .B0(n1361), .B1(intDX_EWSW[8]),
.Y(n902) );
AO22XLTS U1108 ( .A0(n1360), .A1(Data_X[15]), .B0(n963), .B1(intDX_EWSW[15]),
.Y(n895) );
AO22XLTS U1109 ( .A0(n1360), .A1(Data_X[13]), .B0(n963), .B1(intDX_EWSW[13]),
.Y(n897) );
AO22XLTS U1110 ( .A0(n964), .A1(Data_X[21]), .B0(n1366), .B1(intDX_EWSW[21]),
.Y(n889) );
AO22XLTS U1111 ( .A0(n1363), .A1(Data_X[23]), .B0(n1367), .B1(intDX_EWSW[23]), .Y(n887) );
AO22XLTS U1112 ( .A0(n1368), .A1(Data_X[3]), .B0(n1362), .B1(intDX_EWSW[3]),
.Y(n907) );
AOI2BB2XLTS U1113 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1287), .A0N(n1275),
.A1N(n1232), .Y(n1269) );
OAI21XLTS U1114 ( .A0(n1369), .A1(n1232), .B0(n1264), .Y(n842) );
OAI211XLTS U1115 ( .A0(n1265), .A1(n985), .B0(n1243), .C0(n1242), .Y(n840)
);
AOI2BB2XLTS U1116 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1287), .A0N(n1262), .A1N(
n1390), .Y(n1242) );
OAI211XLTS U1117 ( .A0(n1271), .A1(n1390), .B0(n1250), .C0(n1249), .Y(n826)
);
AO22XLTS U1118 ( .A0(n923), .A1(Data_Y[29]), .B0(n963), .B1(intDY_EWSW[29]),
.Y(n847) );
AO22XLTS U1119 ( .A0(n1362), .A1(intDY_EWSW[7]), .B0(n964), .B1(Data_Y[7]),
.Y(n869) );
AO22XLTS U1120 ( .A0(n1365), .A1(intDY_EWSW[2]), .B0(n1360), .B1(Data_Y[2]),
.Y(n874) );
AO22XLTS U1121 ( .A0(n963), .A1(intDY_EWSW[6]), .B0(n1360), .B1(Data_Y[6]),
.Y(n870) );
AO22XLTS U1122 ( .A0(n1365), .A1(intDY_EWSW[9]), .B0(n1368), .B1(Data_Y[9]),
.Y(n867) );
AO22XLTS U1123 ( .A0(n1364), .A1(intDY_EWSW[16]), .B0(n964), .B1(Data_Y[16]),
.Y(n860) );
AO22XLTS U1124 ( .A0(n1367), .A1(intDY_EWSW[19]), .B0(n964), .B1(Data_Y[19]),
.Y(n857) );
AO22XLTS U1125 ( .A0(n1364), .A1(intDY_EWSW[23]), .B0(n923), .B1(Data_Y[23]),
.Y(n853) );
AO22XLTS U1126 ( .A0(n1364), .A1(intDY_EWSW[24]), .B0(n923), .B1(Data_Y[24]),
.Y(n852) );
AO22XLTS U1127 ( .A0(n1366), .A1(intDY_EWSW[27]), .B0(n1363), .B1(Data_Y[27]), .Y(n849) );
AO22XLTS U1128 ( .A0(n1366), .A1(intDY_EWSW[4]), .B0(n1368), .B1(Data_Y[4]),
.Y(n872) );
AO22XLTS U1129 ( .A0(n1361), .A1(intDY_EWSW[5]), .B0(n923), .B1(Data_Y[5]),
.Y(n871) );
AO22XLTS U1130 ( .A0(n1466), .A1(Raw_mant_NRM_SWR[10]), .B0(n1697), .B1(
intadd_37_SUM_2_), .Y(n567) );
AO22XLTS U1131 ( .A0(n1363), .A1(Data_Y[30]), .B0(n1367), .B1(intDY_EWSW[30]), .Y(n846) );
OAI21XLTS U1132 ( .A0(n1395), .A1(n1566), .B0(n1226), .Y(n815) );
AOI31XLTS U1133 ( .A0(n986), .A1(Shift_amount_SHT1_EWR[4]), .A2(n950), .B0(
n1329), .Y(n1226) );
AO22XLTS U1134 ( .A0(n1360), .A1(Data_X[4]), .B0(n963), .B1(intDX_EWSW[4]),
.Y(n906) );
AO22XLTS U1135 ( .A0(n923), .A1(Data_X[5]), .B0(n1366), .B1(intDX_EWSW[5]),
.Y(n905) );
AO22XLTS U1136 ( .A0(n964), .A1(Data_X[6]), .B0(n1366), .B1(intDX_EWSW[6]),
.Y(n904) );
AO22XLTS U1137 ( .A0(n964), .A1(Data_X[7]), .B0(n1366), .B1(intDX_EWSW[7]),
.Y(n903) );
AO22XLTS U1138 ( .A0(n923), .A1(Data_X[16]), .B0(n1367), .B1(intDX_EWSW[16]),
.Y(n894) );
AO22XLTS U1139 ( .A0(n963), .A1(intDX_EWSW[24]), .B0(n1360), .B1(Data_X[24]),
.Y(n886) );
AO22XLTS U1140 ( .A0(n1361), .A1(intDX_EWSW[25]), .B0(n1368), .B1(Data_X[25]), .Y(n885) );
AO22XLTS U1141 ( .A0(n1365), .A1(intDX_EWSW[26]), .B0(n1360), .B1(Data_X[26]), .Y(n884) );
AO22XLTS U1142 ( .A0(n1366), .A1(intDX_EWSW[28]), .B0(n1360), .B1(Data_X[28]), .Y(n882) );
AO22XLTS U1143 ( .A0(n1366), .A1(intDY_EWSW[8]), .B0(n1368), .B1(Data_Y[8]),
.Y(n868) );
AO22XLTS U1144 ( .A0(n1365), .A1(intDY_EWSW[12]), .B0(n964), .B1(Data_Y[12]),
.Y(n864) );
AO22XLTS U1145 ( .A0(n1361), .A1(intDY_EWSW[13]), .B0(n964), .B1(Data_Y[13]),
.Y(n863) );
AO22XLTS U1146 ( .A0(n963), .A1(intDY_EWSW[14]), .B0(n964), .B1(Data_Y[14]),
.Y(n862) );
AO22XLTS U1147 ( .A0(n1361), .A1(intDY_EWSW[15]), .B0(n964), .B1(Data_Y[15]),
.Y(n861) );
AO22XLTS U1148 ( .A0(n1366), .A1(intDY_EWSW[17]), .B0(n964), .B1(Data_Y[17]),
.Y(n859) );
AO22XLTS U1149 ( .A0(n1365), .A1(intDY_EWSW[18]), .B0(n964), .B1(Data_Y[18]),
.Y(n858) );
AO22XLTS U1150 ( .A0(n1362), .A1(intDY_EWSW[25]), .B0(n1360), .B1(Data_Y[25]), .Y(n851) );
AO22XLTS U1151 ( .A0(n1367), .A1(intDY_EWSW[26]), .B0(n1368), .B1(Data_Y[26]), .Y(n850) );
AO22XLTS U1152 ( .A0(n1362), .A1(intDY_EWSW[21]), .B0(n1368), .B1(Data_Y[21]), .Y(n855) );
AO22XLTS U1153 ( .A0(n1362), .A1(intDY_EWSW[22]), .B0(n923), .B1(Data_Y[22]),
.Y(n854) );
AO22XLTS U1154 ( .A0(n1367), .A1(intDY_EWSW[3]), .B0(n923), .B1(Data_Y[3]),
.Y(n873) );
AO22XLTS U1155 ( .A0(n1698), .A1(Raw_mant_NRM_SWR[9]), .B0(n1697), .B1(
intadd_37_SUM_1_), .Y(n568) );
NOR2XLTS U1156 ( .A(n1473), .B(SIGN_FLAG_SHT1SHT2), .Y(n1322) );
AO22XLTS U1157 ( .A0(n953), .A1(n1548), .B0(final_result_ieee[21]), .B1(n989), .Y(n526) );
AO22XLTS U1158 ( .A0(n953), .A1(n1547), .B0(final_result_ieee[20]), .B1(n989), .Y(n527) );
AO22XLTS U1159 ( .A0(n953), .A1(n1522), .B0(final_result_ieee[0]), .B1(n989),
.Y(n530) );
AO22XLTS U1160 ( .A0(n953), .A1(n1521), .B0(final_result_ieee[1]), .B1(n989),
.Y(n531) );
AO22XLTS U1161 ( .A0(n953), .A1(n1541), .B0(final_result_ieee[16]), .B1(n989), .Y(n532) );
AO22XLTS U1162 ( .A0(n953), .A1(n1516), .B0(final_result_ieee[5]), .B1(n989),
.Y(n533) );
AO22XLTS U1163 ( .A0(n953), .A1(n1536), .B0(final_result_ieee[13]), .B1(n989), .Y(n535) );
AO22XLTS U1164 ( .A0(n953), .A1(n1508), .B0(final_result_ieee[8]), .B1(n989),
.Y(n536) );
AO22XLTS U1165 ( .A0(n953), .A1(n1535), .B0(final_result_ieee[12]), .B1(n989), .Y(n538) );
AO22XLTS U1166 ( .A0(n953), .A1(n1503), .B0(final_result_ieee[9]), .B1(n989),
.Y(n539) );
AO22XLTS U1167 ( .A0(n953), .A1(n1537), .B0(final_result_ieee[14]), .B1(n989), .Y(n543) );
AO22XLTS U1168 ( .A0(n953), .A1(n1492), .B0(final_result_ieee[7]), .B1(n989),
.Y(n544) );
AO22XLTS U1169 ( .A0(n952), .A1(n1534), .B0(final_result_ieee[11]), .B1(n989), .Y(n546) );
AO22XLTS U1170 ( .A0(n952), .A1(n1533), .B0(final_result_ieee[10]), .B1(
n1696), .Y(n547) );
AO22XLTS U1171 ( .A0(n952), .A1(n1543), .B0(final_result_ieee[17]), .B1(
n1696), .Y(n551) );
AO22XLTS U1172 ( .A0(n952), .A1(n1474), .B0(final_result_ieee[4]), .B1(n1696), .Y(n552) );
OAI2BB2XLTS U1173 ( .B0(n1551), .B1(n1532), .A0N(final_result_ieee[22]),
.A1N(n989), .Y(n525) );
AO21XLTS U1174 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1394), .B0(n1347), .Y(n559) );
AO21XLTS U1175 ( .A0(LZD_output_NRM2_EW[4]), .A1(n1394), .B0(n1329), .Y(n574) );
AO22XLTS U1176 ( .A0(n1556), .A1(n1503), .B0(n1539), .B1(n981), .Y(n576) );
OAI21XLTS U1177 ( .A0(n1570), .A1(n1411), .B0(n1116), .Y(n614) );
OAI21XLTS U1178 ( .A0(n1616), .A1(n1411), .B0(n1122), .Y(n616) );
OAI21XLTS U1179 ( .A0(n965), .A1(n1411), .B0(n1124), .Y(n618) );
OAI21XLTS U1180 ( .A0(n1572), .A1(n1411), .B0(n1117), .Y(n620) );
OAI21XLTS U1181 ( .A0(n1636), .A1(n1411), .B0(n1129), .Y(n622) );
OAI21XLTS U1182 ( .A0(n1632), .A1(n1411), .B0(n1121), .Y(n624) );
OAI21XLTS U1183 ( .A0(n1620), .A1(n1142), .B0(n1120), .Y(n626) );
OAI21XLTS U1184 ( .A0(n1631), .A1(n1142), .B0(n1141), .Y(n628) );
OAI21XLTS U1185 ( .A0(n1569), .A1(n1142), .B0(n1114), .Y(n630) );
AO22XLTS U1186 ( .A0(n1405), .A1(DmP_EXP_EWSW[13]), .B0(n1417), .B1(n972),
.Y(n631) );
OAI21XLTS U1187 ( .A0(n1615), .A1(n1142), .B0(n1123), .Y(n632) );
OAI21XLTS U1188 ( .A0(n1619), .A1(n1142), .B0(n1133), .Y(n634) );
AO22XLTS U1189 ( .A0(n1405), .A1(DmP_EXP_EWSW[11]), .B0(n1410), .B1(n973),
.Y(n635) );
OAI21XLTS U1190 ( .A0(n1203), .A1(n1142), .B0(n1137), .Y(n636) );
OAI21XLTS U1191 ( .A0(n936), .A1(n1142), .B0(n1132), .Y(n638) );
AO22XLTS U1192 ( .A0(n990), .A1(DmP_EXP_EWSW[9]), .B0(n1410), .B1(n974), .Y(
n639) );
OAI21XLTS U1193 ( .A0(n1614), .A1(n1142), .B0(n1135), .Y(n640) );
OAI21XLTS U1194 ( .A0(n1633), .A1(n1142), .B0(n1134), .Y(n642) );
AO22XLTS U1195 ( .A0(n990), .A1(DmP_EXP_EWSW[7]), .B0(n1410), .B1(n969), .Y(
n643) );
OAI21XLTS U1196 ( .A0(n1623), .A1(n1142), .B0(n1125), .Y(n644) );
AO22XLTS U1197 ( .A0(n990), .A1(DmP_EXP_EWSW[6]), .B0(n1410), .B1(n975), .Y(
n645) );
OAI21XLTS U1198 ( .A0(n1613), .A1(n1142), .B0(n1128), .Y(n646) );
AO22XLTS U1199 ( .A0(n990), .A1(DmP_EXP_EWSW[5]), .B0(n1410), .B1(n976), .Y(
n647) );
OAI21XLTS U1200 ( .A0(n1568), .A1(n1142), .B0(n1126), .Y(n648) );
AO22XLTS U1201 ( .A0(n990), .A1(DmP_EXP_EWSW[4]), .B0(n1410), .B1(n971), .Y(
n649) );
OAI21XLTS U1202 ( .A0(n1618), .A1(n1188), .B0(n1127), .Y(n650) );
AO22XLTS U1203 ( .A0(n990), .A1(DmP_EXP_EWSW[3]), .B0(n1410), .B1(n970), .Y(
n651) );
OAI21XLTS U1204 ( .A0(n1612), .A1(n1188), .B0(n1138), .Y(n652) );
OAI21XLTS U1205 ( .A0(n1617), .A1(n1188), .B0(n1136), .Y(n654) );
AO22XLTS U1206 ( .A0(n990), .A1(DmP_EXP_EWSW[1]), .B0(n1410), .B1(n977), .Y(
n655) );
OAI21XLTS U1207 ( .A0(n983), .A1(n1188), .B0(n1130), .Y(n656) );
AO22XLTS U1208 ( .A0(n990), .A1(DmP_EXP_EWSW[0]), .B0(n1417), .B1(n978), .Y(
n657) );
OAI21XLTS U1209 ( .A0(n942), .A1(n1188), .B0(n1131), .Y(n658) );
AO22XLTS U1210 ( .A0(n1542), .A1(DMP_SHT2_EWSW[6]), .B0(n1550), .B1(n980),
.Y(n747) );
OAI21XLTS U1211 ( .A0(n1192), .A1(n1113), .B0(n1188), .Y(n1190) );
OAI21XLTS U1212 ( .A0(n1571), .A1(n1188), .B0(n1118), .Y(n771) );
OAI21XLTS U1213 ( .A0(n1624), .A1(n1188), .B0(n1119), .Y(n772) );
OAI21XLTS U1214 ( .A0(n1635), .A1(n1411), .B0(n1115), .Y(n773) );
OAI21XLTS U1215 ( .A0(n1622), .A1(n1413), .B0(n1148), .Y(n774) );
OAI21XLTS U1216 ( .A0(n1570), .A1(n1413), .B0(n1198), .Y(n779) );
OAI21XLTS U1217 ( .A0(n1616), .A1(n1413), .B0(n1144), .Y(n780) );
OAI21XLTS U1218 ( .A0(n965), .A1(n1413), .B0(n1150), .Y(n781) );
OAI21XLTS U1219 ( .A0(n1572), .A1(n1413), .B0(n1193), .Y(n782) );
OAI21XLTS U1220 ( .A0(n1636), .A1(n1207), .B0(n1194), .Y(n783) );
OAI21XLTS U1221 ( .A0(n1632), .A1(n1207), .B0(n1199), .Y(n784) );
OAI21XLTS U1222 ( .A0(n1620), .A1(n1207), .B0(n1146), .Y(n785) );
OAI21XLTS U1223 ( .A0(n1631), .A1(n1207), .B0(n1206), .Y(n786) );
OAI21XLTS U1224 ( .A0(n1569), .A1(n1207), .B0(n1197), .Y(n787) );
OAI21XLTS U1225 ( .A0(n1615), .A1(n1207), .B0(n1204), .Y(n788) );
OAI21XLTS U1226 ( .A0(n1619), .A1(n1207), .B0(n1200), .Y(n789) );
OAI21XLTS U1227 ( .A0(n1203), .A1(n1207), .B0(n1202), .Y(n790) );
OAI21XLTS U1228 ( .A0(n936), .A1(n1207), .B0(n1195), .Y(n791) );
OAI21XLTS U1229 ( .A0(n1614), .A1(n1207), .B0(n1147), .Y(n792) );
OAI21XLTS U1230 ( .A0(n1633), .A1(n1207), .B0(n1143), .Y(n793) );
OAI21XLTS U1231 ( .A0(n1623), .A1(n1207), .B0(n1145), .Y(n794) );
OAI21XLTS U1232 ( .A0(n1613), .A1(n1216), .B0(n1215), .Y(n795) );
OAI21XLTS U1233 ( .A0(n1568), .A1(n1216), .B0(n1211), .Y(n796) );
OAI21XLTS U1234 ( .A0(n1618), .A1(n1216), .B0(n1212), .Y(n797) );
OAI21XLTS U1235 ( .A0(n1612), .A1(n1216), .B0(n1209), .Y(n798) );
OAI21XLTS U1236 ( .A0(n1617), .A1(n1216), .B0(n1210), .Y(n799) );
OAI21XLTS U1237 ( .A0(n983), .A1(n1216), .B0(n1208), .Y(n800) );
OAI21XLTS U1238 ( .A0(n942), .A1(n1413), .B0(n1149), .Y(n801) );
AO22XLTS U1239 ( .A0(n1357), .A1(busy), .B0(n1356), .B1(n966), .Y(n914) );
INVX2TS U1240 ( .A(n951), .Y(n1394) );
INVX2TS U1241 ( .A(n986), .Y(n987) );
AOI22X1TS U1242 ( .A0(n1356), .A1(n1468), .B0(n1357), .B1(n966), .Y(n926) );
BUFX3TS U1243 ( .A(n1232), .Y(n1390) );
OR2X1TS U1244 ( .A(n1473), .B(n1472), .Y(n934) );
BUFX3TS U1245 ( .A(n921), .Y(n1393) );
CLKBUFX2TS U1246 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1343) );
INVX2TS U1247 ( .A(n1343), .Y(n950) );
INVX2TS U1248 ( .A(n950), .Y(n951) );
INVX2TS U1249 ( .A(n1363), .Y(n1364) );
INVX2TS U1250 ( .A(n934), .Y(n952) );
CLKINVX3TS U1251 ( .A(n934), .Y(n953) );
INVX2TS U1252 ( .A(left_right_SHT2), .Y(n954) );
INVX2TS U1253 ( .A(n954), .Y(n955) );
INVX2TS U1254 ( .A(n1394), .Y(n956) );
CLKINVX3TS U1255 ( .A(n1024), .Y(n957) );
INVX2TS U1256 ( .A(n987), .Y(n959) );
INVX2TS U1257 ( .A(n959), .Y(n960) );
OAI21XLTS U1258 ( .A0(n1622), .A1(n1142), .B0(n1140), .Y(n608) );
OAI211XLTS U1259 ( .A0(n1257), .A1(n985), .B0(n1256), .C0(n1255), .Y(n820)
);
INVX2TS U1260 ( .A(rst), .Y(n961) );
INVX2TS U1261 ( .A(n1363), .Y(n963) );
INVX4TS U1262 ( .A(n1364), .Y(n964) );
NOR2X4TS U1263 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1478) );
NOR2X4TS U1264 ( .A(shift_value_SHT2_EWR[3]), .B(n1591), .Y(n1477) );
BUFX4TS U1265 ( .A(n1677), .Y(n1670) );
BUFX4TS U1266 ( .A(n1673), .Y(n1665) );
BUFX4TS U1267 ( .A(n1676), .Y(n1666) );
BUFX4TS U1268 ( .A(n1675), .Y(n1668) );
BUFX3TS U1269 ( .A(n961), .Y(n1031) );
INVX2TS U1270 ( .A(n941), .Y(n966) );
INVX2TS U1271 ( .A(n939), .Y(n967) );
INVX2TS U1272 ( .A(n931), .Y(n968) );
INVX2TS U1273 ( .A(n948), .Y(n969) );
INVX2TS U1274 ( .A(n947), .Y(n970) );
INVX2TS U1275 ( .A(n930), .Y(n971) );
INVX2TS U1276 ( .A(n929), .Y(n972) );
INVX2TS U1277 ( .A(n928), .Y(n973) );
INVX2TS U1278 ( .A(n946), .Y(n974) );
INVX2TS U1279 ( .A(n927), .Y(n975) );
INVX2TS U1280 ( .A(n945), .Y(n976) );
INVX2TS U1281 ( .A(n944), .Y(n977) );
INVX2TS U1282 ( .A(n943), .Y(n978) );
INVX2TS U1283 ( .A(n949), .Y(n979) );
INVX2TS U1284 ( .A(n932), .Y(n980) );
INVX2TS U1285 ( .A(n933), .Y(n981) );
INVX2TS U1286 ( .A(intDY_EWSW[23]), .Y(n982) );
BUFX4TS U1287 ( .A(n920), .Y(n1139) );
INVX2TS U1288 ( .A(n1228), .Y(n984) );
INVX4TS U1289 ( .A(n1228), .Y(n985) );
INVX2TS U1290 ( .A(n1700), .Y(n986) );
INVX2TS U1291 ( .A(n937), .Y(n988) );
OAI211XLTS U1292 ( .A0(n1275), .A1(n984), .B0(n1274), .C0(n1273), .Y(n830)
);
AOI32X1TS U1293 ( .A0(n1636), .A1(n1094), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1572), .Y(n1095) );
AOI221X1TS U1294 ( .A0(n1636), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1572), .C0(n1161), .Y(n1166) );
AOI221X1TS U1295 ( .A0(n1622), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1635), .C0(n1154), .Y(n1158) );
AOI221X1TS U1296 ( .A0(n936), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1203), .C0(n1169), .Y(n1174) );
AOI221X1TS U1297 ( .A0(n1617), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1612), .C0(n1177), .Y(n1182) );
AOI221X1TS U1298 ( .A0(n1569), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1631), .C0(n1171), .Y(n1172) );
AOI221X1TS U1299 ( .A0(n1619), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1615), .C0(n1170), .Y(n1173) );
OAI211XLTS U1300 ( .A0(n1300), .A1(n1390), .B0(n1261), .C0(n1260), .Y(n825)
);
AOI222X4TS U1301 ( .A0(n940), .A1(intadd_36_B_1_), .B0(n940), .B1(n1427),
.C0(intadd_36_B_1_), .C1(n1427), .Y(n1428) );
OAI211XLTS U1302 ( .A0(n1279), .A1(n1232), .B0(n1241), .C0(n1240), .Y(n822)
);
OAI211XLTS U1303 ( .A0(n1290), .A1(n1232), .B0(n1246), .C0(n1245), .Y(n821)
);
OAI31XLTS U1304 ( .A0(n1403), .A1(n1192), .A2(n1413), .B0(n1191), .Y(n768)
);
NOR2X2TS U1305 ( .A(shift_value_SHT2_EWR[2]), .B(n1599), .Y(n1442) );
NOR2X2TS U1306 ( .A(n991), .B(DMP_EXP_EWSW[23]), .Y(n1398) );
XNOR2X2TS U1307 ( .A(DMP_exp_NRM2_EW[0]), .B(n1327), .Y(n1348) );
XNOR2X2TS U1308 ( .A(DMP_exp_NRM2_EW[6]), .B(n1307), .Y(n1350) );
OAI22X2TS U1309 ( .A0(n1625), .A1(n1482), .B0(n1573), .B1(n1481), .Y(n1495)
);
NOR2XLTS U1310 ( .A(n1318), .B(n1349), .Y(n1319) );
XNOR2X2TS U1311 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J34_125_2314_n4), .Y(
n1349) );
BUFX4TS U1312 ( .A(n1030), .Y(n1685) );
BUFX4TS U1313 ( .A(n1031), .Y(n1671) );
BUFX4TS U1314 ( .A(n1030), .Y(n1669) );
BUFX4TS U1315 ( .A(n1031), .Y(n1690) );
BUFX4TS U1316 ( .A(n1030), .Y(n1686) );
BUFX4TS U1317 ( .A(n1031), .Y(n1687) );
BUFX3TS U1318 ( .A(n961), .Y(n1030) );
AOI2BB2X2TS U1319 ( .B0(DmP_mant_SFG_SWR[3]), .B1(OP_FLAG_SFG), .A0N(
OP_FLAG_SFG), .A1N(DmP_mant_SFG_SWR[3]), .Y(n1455) );
NOR2XLTS U1320 ( .A(n1071), .B(intDY_EWSW[10]), .Y(n1072) );
AOI221X1TS U1321 ( .A0(intDX_EWSW[30]), .A1(n1602), .B0(intDX_EWSW[29]),
.B1(n1565), .C0(n1053), .Y(n1055) );
AOI2BB2X2TS U1322 ( .B0(DmP_mant_SFG_SWR[9]), .B1(n1446), .A0N(OP_FLAG_SFG),
.A1N(DmP_mant_SFG_SWR[9]), .Y(intadd_37_B_1_) );
AOI22X2TS U1323 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1447), .B0(n1446), .B1(
n1601), .Y(intadd_36_B_1_) );
BUFX4TS U1324 ( .A(OP_FLAG_SFG), .Y(n1446) );
INVX4TS U1325 ( .A(n1701), .Y(n1408) );
NAND2X4TS U1326 ( .A(n1394), .B(n960), .Y(n1395) );
AOI222X1TS U1327 ( .A0(n1502), .A1(n954), .B0(n1554), .B1(Data_array_SWR[5]),
.C0(n1501), .C1(n1499), .Y(n1500) );
AOI222X1TS U1328 ( .A0(n1502), .A1(left_right_SHT2), .B0(Data_array_SWR[5]),
.B1(n1526), .C0(n1501), .C1(n1524), .Y(n1545) );
AOI222X1TS U1329 ( .A0(n1484), .A1(n954), .B0(n1554), .B1(Data_array_SWR[4]),
.C0(n1495), .C1(n1499), .Y(n1483) );
AOI222X1TS U1330 ( .A0(n1484), .A1(left_right_SHT2), .B0(Data_array_SWR[4]),
.B1(n1526), .C0(n1495), .C1(n1524), .Y(n1546) );
AOI222X4TS U1331 ( .A0(n1432), .A1(DMP_SFG[9]), .B0(n1432), .B1(n1326), .C0(
DMP_SFG[9]), .C1(n1326), .Y(intadd_35_B_0_) );
AOI222X4TS U1332 ( .A0(Data_array_SWR[20]), .A1(n1424), .B0(
Data_array_SWR[24]), .B1(n1423), .C0(Data_array_SWR[16]), .C1(n1425),
.Y(n1487) );
AOI222X4TS U1333 ( .A0(Data_array_SWR[20]), .A1(n1477), .B0(
Data_array_SWR[24]), .B1(n1442), .C0(Data_array_SWR[16]), .C1(n1478),
.Y(n1494) );
NOR2BX1TS U1334 ( .AN(n1015), .B(Raw_mant_NRM_SWR[18]), .Y(n1331) );
AOI22X2TS U1335 ( .A0(Data_array_SWR[22]), .A1(n1477), .B0(
Data_array_SWR[18]), .B1(n1478), .Y(n1518) );
AOI222X4TS U1336 ( .A0(Data_array_SWR[22]), .A1(n1423), .B0(
Data_array_SWR[14]), .B1(n1425), .C0(Data_array_SWR[18]), .C1(n1424),
.Y(n1510) );
AOI222X4TS U1337 ( .A0(Data_array_SWR[23]), .A1(n1423), .B0(
Data_array_SWR[19]), .B1(n1424), .C0(Data_array_SWR[15]), .C1(n1425),
.Y(n1505) );
AOI22X2TS U1338 ( .A0(Data_array_SWR[23]), .A1(n1477), .B0(
Data_array_SWR[19]), .B1(n1478), .Y(n1476) );
NOR2X2TS U1339 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1608), .Y(n1354) );
OAI21X2TS U1340 ( .A0(intDX_EWSW[18]), .A1(n1636), .B0(n1094), .Y(n1161) );
AOI32X1TS U1341 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1007), .A2(n1006), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1007), .Y(n1008) );
NOR3X1TS U1342 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1340) );
OAI21XLTS U1343 ( .A0(intDX_EWSW[1]), .A1(n983), .B0(intDX_EWSW[0]), .Y(
n1059) );
NOR2X2TS U1344 ( .A(Raw_mant_NRM_SWR[13]), .B(n1001), .Y(n1018) );
OAI211XLTS U1345 ( .A0(n1272), .A1(n984), .B0(n1237), .C0(n1236), .Y(n832)
);
INVX4TS U1346 ( .A(Shift_reg_FLAGS_7[0]), .Y(n989) );
NOR2XLTS U1347 ( .A(n1414), .B(n1696), .Y(n1415) );
OAI211XLTS U1348 ( .A0(intDX_EWSW[8]), .A1(n1633), .B0(n1073), .C0(n1076),
.Y(n1087) );
OAI21XLTS U1349 ( .A0(intDX_EWSW[13]), .A1(n1615), .B0(intDX_EWSW[12]), .Y(
n1070) );
OAI21XLTS U1350 ( .A0(intDX_EWSW[21]), .A1(n1616), .B0(intDX_EWSW[20]), .Y(
n1091) );
OAI21XLTS U1351 ( .A0(intDX_EWSW[23]), .A1(n982), .B0(intDX_EWSW[22]), .Y(
n1098) );
OAI21XLTS U1352 ( .A0(intDX_EWSW[3]), .A1(n1612), .B0(intDX_EWSW[2]), .Y(
n1062) );
OAI211XLTS U1353 ( .A0(n1612), .A1(intDX_EWSW[3]), .B0(n1061), .C0(n1060),
.Y(n1064) );
BUFX3TS U1354 ( .A(n1560), .Y(n990) );
AO22XLTS U1355 ( .A0(n1357), .A1(n950), .B0(n989), .B1(n1356), .Y(n993) );
NOR2XLTS U1356 ( .A(n1603), .B(intDX_EWSW[11]), .Y(n1071) );
OAI21XLTS U1357 ( .A0(intDX_EWSW[15]), .A1(n1631), .B0(intDX_EWSW[14]), .Y(
n1079) );
NOR2XLTS U1358 ( .A(n1092), .B(intDY_EWSW[16]), .Y(n1093) );
NOR2XLTS U1359 ( .A(n1348), .B(exp_rslt_NRM2_EW1[1]), .Y(n1317) );
NOR2XLTS U1360 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1009) );
AOI31XLTS U1361 ( .A0(n1582), .A1(Raw_mant_NRM_SWR[11]), .A2(n1018), .B0(
n1016), .Y(n1011) );
NAND2X1TS U1362 ( .A(n1222), .B(n935), .Y(n1341) );
OAI211XLTS U1363 ( .A0(n1271), .A1(n984), .B0(n1270), .C0(n1269), .Y(n828)
);
OAI21XLTS U1364 ( .A0(n1354), .A1(n1046), .B0(n1352), .Y(n918) );
OAI21XLTS U1365 ( .A0(n982), .A1(n1207), .B0(n1152), .Y(n778) );
NOR2XLTS U1366 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1000) );
AOI32X4TS U1367 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1000), .B1(n1608), .Y(n1357)
);
INVX2TS U1368 ( .A(n1357), .Y(n1356) );
INVX4TS U1369 ( .A(n1462), .Y(n1468) );
NAND4X1TS U1370 ( .A(n1557), .B(n1561), .C(n1579), .D(n1558), .Y(n1339) );
NOR2BX2TS U1371 ( .AN(n1340), .B(n1339), .Y(n1015) );
NOR3X1TS U1372 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[17]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1332) );
NAND2X1TS U1373 ( .A(Raw_mant_NRM_SWR[14]), .B(n1330), .Y(n1013) );
NOR3X1TS U1374 ( .A(Raw_mant_NRM_SWR[12]), .B(n1586), .C(n1002), .Y(n1337)
);
NOR3X2TS U1375 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1217),
.Y(n1222) );
OAI21X1TS U1376 ( .A0(n1005), .A1(n1341), .B0(n1004), .Y(n1221) );
NOR2X1TS U1377 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1007) );
AOI211X1TS U1378 ( .A0(n1009), .A1(n1008), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1010) );
NOR4BBX2TS U1379 ( .AN(n1013), .BN(n1011), .C(n1221), .D(n1010), .Y(n1229)
);
AOI32X1TS U1380 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1557), .A2(n1590), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1557), .Y(n1012) );
AOI32X1TS U1381 ( .A0(n1558), .A1(n1013), .A2(n1012), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1013), .Y(n1014) );
NOR3X1TS U1382 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .C(n1341),
.Y(n1223) );
NAND2X1TS U1383 ( .A(n1223), .B(n988), .Y(n1224) );
AOI21X1TS U1384 ( .A0(n1222), .A1(n1017), .B0(n1016), .Y(n1019) );
NAND2X1TS U1385 ( .A(Raw_mant_NRM_SWR[12]), .B(n1018), .Y(n1335) );
OAI211X1TS U1386 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1224), .B0(n1019), .C0(
n1335), .Y(n1345) );
OAI211X1TS U1387 ( .A0(n1588), .A1(n1217), .B0(n1022), .C0(n1021), .Y(n1023)
);
NAND2X2TS U1388 ( .A(n1023), .B(n951), .Y(n1384) );
INVX2TS U1389 ( .A(n1384), .Y(n1372) );
NAND2X1TS U1390 ( .A(n1229), .B(n1372), .Y(n1299) );
AOI22X1TS U1391 ( .A0(n921), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1287), .Y(n1028) );
OR2X2TS U1392 ( .A(n1394), .B(n1023), .Y(n1374) );
NOR2X1TS U1393 ( .A(n1229), .B(n950), .Y(n1347) );
AOI21X1TS U1394 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n1394), .B0(n1347), .Y(
n1227) );
NOR2X2TS U1395 ( .A(n921), .B(n1227), .Y(n1286) );
NOR2BX1TS U1396 ( .AN(Shift_amount_SHT1_EWR[0]), .B(n1343), .Y(n1231) );
BUFX3TS U1397 ( .A(n1231), .Y(n1382) );
AOI22X1TS U1398 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1372), .B0(n1382), .B1(
n977), .Y(n1026) );
AOI22X1TS U1399 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1386), .B0(n957), .B1(n978), .Y(n1025) );
NAND2X1TS U1400 ( .A(n1026), .B(n1025), .Y(n1244) );
AOI22X1TS U1401 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1386), .B0(n1286), .B1(
n1244), .Y(n1027) );
NAND2X1TS U1402 ( .A(n1028), .B(n1027), .Y(n819) );
CLKBUFX2TS U1403 ( .A(n962), .Y(n1029) );
BUFX3TS U1404 ( .A(n1030), .Y(n1679) );
BUFX3TS U1405 ( .A(n1031), .Y(n1680) );
BUFX3TS U1406 ( .A(n1030), .Y(n1681) );
BUFX3TS U1407 ( .A(n1031), .Y(n1682) );
BUFX3TS U1408 ( .A(n1030), .Y(n1684) );
BUFX3TS U1409 ( .A(n1031), .Y(n1672) );
BUFX3TS U1410 ( .A(n961), .Y(n1674) );
BUFX3TS U1411 ( .A(n961), .Y(n1677) );
BUFX3TS U1412 ( .A(n961), .Y(n1678) );
BUFX3TS U1413 ( .A(n1030), .Y(n1683) );
BUFX3TS U1414 ( .A(n962), .Y(n1675) );
BUFX3TS U1415 ( .A(n962), .Y(n1676) );
BUFX3TS U1416 ( .A(n962), .Y(n1673) );
BUFX3TS U1417 ( .A(n1031), .Y(n1695) );
BUFX3TS U1418 ( .A(n1030), .Y(n1692) );
BUFX3TS U1419 ( .A(n1031), .Y(n1691) );
BUFX3TS U1420 ( .A(n1030), .Y(n1688) );
BUFX3TS U1421 ( .A(n1030), .Y(n1694) );
BUFX3TS U1422 ( .A(n1030), .Y(n1664) );
BUFX3TS U1423 ( .A(n1031), .Y(n1689) );
BUFX3TS U1424 ( .A(n1031), .Y(n1693) );
BUFX3TS U1425 ( .A(n1031), .Y(n1667) );
AO22XLTS U1426 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n925),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n592) );
AO22XLTS U1427 ( .A0(n1343), .A1(ZERO_FLAG_NRM), .B0(n950), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n601) );
AO22XLTS U1428 ( .A0(n1697), .A1(ZERO_FLAG_SFG), .B0(n1466), .B1(
ZERO_FLAG_NRM), .Y(n602) );
BUFX3TS U1429 ( .A(n1659), .Y(n1416) );
INVX2TS U1430 ( .A(n1416), .Y(n1405) );
NOR2X1TS U1431 ( .A(n1574), .B(DMP_EXP_EWSW[24]), .Y(n1034) );
AOI21X1TS U1432 ( .A0(DMP_EXP_EWSW[24]), .A1(n1574), .B0(n1034), .Y(n1032)
);
XNOR2X1TS U1433 ( .A(n1398), .B(n1032), .Y(n1033) );
AO22XLTS U1434 ( .A0(n1405), .A1(n1033), .B0(n1416), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n813) );
OAI22X1TS U1435 ( .A0(n1398), .A1(n1034), .B0(DmP_EXP_EWSW[24]), .B1(n1575),
.Y(n1037) );
NAND2X1TS U1436 ( .A(DmP_EXP_EWSW[25]), .B(n1642), .Y(n1038) );
OAI21XLTS U1437 ( .A0(DmP_EXP_EWSW[25]), .A1(n1642), .B0(n1038), .Y(n1035)
);
XNOR2X1TS U1438 ( .A(n1037), .B(n1035), .Y(n1036) );
BUFX3TS U1439 ( .A(n1659), .Y(n1406) );
AO22XLTS U1440 ( .A0(n1405), .A1(n1036), .B0(n1406), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n812) );
AOI22X1TS U1441 ( .A0(DMP_EXP_EWSW[25]), .A1(n1656), .B0(n1038), .B1(n1037),
.Y(n1041) );
NOR2X1TS U1442 ( .A(n1651), .B(DMP_EXP_EWSW[26]), .Y(n1042) );
AOI21X1TS U1443 ( .A0(DMP_EXP_EWSW[26]), .A1(n1651), .B0(n1042), .Y(n1039)
);
XNOR2X1TS U1444 ( .A(n1041), .B(n1039), .Y(n1040) );
AO22XLTS U1445 ( .A0(n1405), .A1(n1040), .B0(n1406), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n811) );
OAI22X1TS U1446 ( .A0(n1042), .A1(n1041), .B0(DmP_EXP_EWSW[26]), .B1(n1655),
.Y(n1044) );
XNOR2X1TS U1447 ( .A(DmP_EXP_EWSW[27]), .B(n979), .Y(n1043) );
XOR2XLTS U1448 ( .A(n1044), .B(n1043), .Y(n1045) );
AO22XLTS U1449 ( .A0(n1405), .A1(n1045), .B0(n1406), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n810) );
INVX4TS U1450 ( .A(n1408), .Y(busy) );
OAI21XLTS U1451 ( .A0(n959), .A1(n922), .B0(n1394), .Y(n877) );
AOI2BB2XLTS U1452 ( .B0(beg_OP), .B1(n1567), .A0N(n1567), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1046) );
AOI2BB2X1TS U1453 ( .B0(DmP_mant_SFG_SWR[6]), .B1(n1419), .A0N(n1419), .A1N(
DmP_mant_SFG_SWR[6]), .Y(intadd_36_B_2_) );
NOR2X1TS U1454 ( .A(n1630), .B(intDX_EWSW[25]), .Y(n1105) );
AOI22X1TS U1455 ( .A0(intDX_EWSW[25]), .A1(n1630), .B0(intDX_EWSW[24]), .B1(
n1047), .Y(n1051) );
OAI21X1TS U1456 ( .A0(intDX_EWSW[26]), .A1(n1629), .B0(n1048), .Y(n1106) );
NOR2X1TS U1457 ( .A(n1602), .B(intDX_EWSW[30]), .Y(n1054) );
NOR2X1TS U1458 ( .A(n1565), .B(intDX_EWSW[29]), .Y(n1052) );
AOI211X1TS U1459 ( .A0(intDY_EWSW[28]), .A1(n1635), .B0(n1054), .C0(n1052),
.Y(n1104) );
NOR3X1TS U1460 ( .A(n1635), .B(n1052), .C(intDY_EWSW[28]), .Y(n1053) );
AOI2BB2X1TS U1461 ( .B0(n1056), .B1(n1104), .A0N(n1055), .A1N(n1054), .Y(
n1110) );
NOR2X1TS U1462 ( .A(n1632), .B(intDX_EWSW[17]), .Y(n1092) );
INVX2TS U1463 ( .A(intDY_EWSW[11]), .Y(n1203) );
OAI22X1TS U1464 ( .A0(n936), .A1(intDX_EWSW[10]), .B0(n1203), .B1(
intDX_EWSW[11]), .Y(n1169) );
INVX2TS U1465 ( .A(n1169), .Y(n1076) );
OAI2BB1X1TS U1466 ( .A0N(n1587), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1057) );
OAI22X1TS U1467 ( .A0(intDY_EWSW[4]), .A1(n1057), .B0(n1587), .B1(
intDY_EWSW[5]), .Y(n1068) );
OAI2BB1X1TS U1468 ( .A0N(n1563), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1058) );
OAI22X1TS U1469 ( .A0(intDY_EWSW[6]), .A1(n1058), .B0(n1563), .B1(
intDY_EWSW[7]), .Y(n1067) );
AOI222X1TS U1470 ( .A0(intDY_EWSW[4]), .A1(n1562), .B0(n1064), .B1(n1063),
.C0(intDY_EWSW[5]), .C1(n1587), .Y(n1066) );
AOI22X1TS U1471 ( .A0(intDY_EWSW[7]), .A1(n1563), .B0(intDY_EWSW[6]), .B1(
n1589), .Y(n1065) );
OAI32X1TS U1472 ( .A0(n1068), .A1(n1067), .A2(n1066), .B0(n1065), .B1(n1067),
.Y(n1086) );
OA22X1TS U1473 ( .A0(n1569), .A1(intDX_EWSW[14]), .B0(n1631), .B1(
intDX_EWSW[15]), .Y(n1083) );
OAI2BB2XLTS U1474 ( .B0(intDY_EWSW[12]), .B1(n1070), .A0N(intDX_EWSW[13]),
.A1N(n1615), .Y(n1082) );
AOI22X1TS U1475 ( .A0(intDX_EWSW[11]), .A1(n1603), .B0(intDX_EWSW[10]), .B1(
n1072), .Y(n1078) );
AOI21X1TS U1476 ( .A0(n1075), .A1(n1074), .B0(n1085), .Y(n1077) );
OAI2BB2XLTS U1477 ( .B0(n1078), .B1(n1085), .A0N(n1077), .A1N(n1076), .Y(
n1081) );
OAI2BB2XLTS U1478 ( .B0(intDY_EWSW[14]), .B1(n1079), .A0N(intDX_EWSW[15]),
.A1N(n1631), .Y(n1080) );
AOI211X1TS U1479 ( .A0(n1083), .A1(n1082), .B0(n1081), .C0(n1080), .Y(n1084)
);
OAI31X1TS U1480 ( .A0(n1087), .A1(n1086), .A2(n1085), .B0(n1084), .Y(n1090)
);
OA22X1TS U1481 ( .A0(n1570), .A1(intDX_EWSW[22]), .B0(n982), .B1(
intDX_EWSW[23]), .Y(n1102) );
OAI2BB2XLTS U1482 ( .B0(intDY_EWSW[20]), .B1(n1091), .A0N(intDX_EWSW[21]),
.A1N(n1616), .Y(n1101) );
AOI22X1TS U1483 ( .A0(intDX_EWSW[17]), .A1(n1632), .B0(intDX_EWSW[16]), .B1(
n1093), .Y(n1096) );
OAI32X1TS U1484 ( .A0(n1161), .A1(n1097), .A2(n1096), .B0(n1095), .B1(n1097),
.Y(n1100) );
AOI211X1TS U1485 ( .A0(n1102), .A1(n1101), .B0(n1100), .C0(n1099), .Y(n1108)
);
NAND4BBX1TS U1486 ( .AN(n1106), .BN(n1105), .C(n1104), .D(n1103), .Y(n1107)
);
AOI32X1TS U1487 ( .A0(n1110), .A1(n1109), .A2(n1108), .B0(n1107), .B1(n1110),
.Y(n1111) );
AND2X2TS U1488 ( .A(Shift_reg_FLAGS_7_6), .B(n1111), .Y(n1151) );
INVX2TS U1489 ( .A(Shift_reg_FLAGS_7_6), .Y(n1113) );
BUFX3TS U1490 ( .A(n1213), .Y(n1189) );
AOI22X1TS U1491 ( .A0(intDX_EWSW[14]), .A1(n1112), .B0(DmP_EXP_EWSW[14]),
.B1(n1189), .Y(n1114) );
BUFX3TS U1492 ( .A(n1113), .Y(n1201) );
AOI22X1TS U1493 ( .A0(intDY_EWSW[28]), .A1(n1112), .B0(DMP_EXP_EWSW[28]),
.B1(n1201), .Y(n1115) );
BUFX3TS U1494 ( .A(n1213), .Y(n1355) );
AOI22X1TS U1495 ( .A0(intDX_EWSW[22]), .A1(n1112), .B0(DmP_EXP_EWSW[22]),
.B1(n1355), .Y(n1116) );
AOI22X1TS U1496 ( .A0(intDX_EWSW[19]), .A1(n1112), .B0(DmP_EXP_EWSW[19]),
.B1(n1355), .Y(n1117) );
INVX2TS U1497 ( .A(n1151), .Y(n1188) );
AOI22X1TS U1498 ( .A0(intDY_EWSW[30]), .A1(n920), .B0(DMP_EXP_EWSW[30]),
.B1(n1201), .Y(n1118) );
AOI22X1TS U1499 ( .A0(intDY_EWSW[29]), .A1(n920), .B0(DMP_EXP_EWSW[29]),
.B1(n1201), .Y(n1119) );
AOI22X1TS U1500 ( .A0(intDX_EWSW[16]), .A1(n920), .B0(DmP_EXP_EWSW[16]),
.B1(n1355), .Y(n1120) );
AOI22X1TS U1501 ( .A0(intDX_EWSW[17]), .A1(n920), .B0(DmP_EXP_EWSW[17]),
.B1(n1355), .Y(n1121) );
AOI22X1TS U1502 ( .A0(intDX_EWSW[21]), .A1(n920), .B0(DmP_EXP_EWSW[21]),
.B1(n1355), .Y(n1122) );
AOI22X1TS U1503 ( .A0(intDX_EWSW[13]), .A1(n920), .B0(DmP_EXP_EWSW[13]),
.B1(n1355), .Y(n1123) );
AOI22X1TS U1504 ( .A0(intDX_EWSW[20]), .A1(n920), .B0(DmP_EXP_EWSW[20]),
.B1(n1355), .Y(n1124) );
AOI22X1TS U1505 ( .A0(intDX_EWSW[7]), .A1(n1139), .B0(DmP_EXP_EWSW[7]), .B1(
n1189), .Y(n1125) );
AOI22X1TS U1506 ( .A0(intDX_EWSW[5]), .A1(n1139), .B0(DmP_EXP_EWSW[5]), .B1(
n1189), .Y(n1126) );
AOI22X1TS U1507 ( .A0(intDX_EWSW[4]), .A1(n1139), .B0(DmP_EXP_EWSW[4]), .B1(
n1189), .Y(n1127) );
AOI22X1TS U1508 ( .A0(intDX_EWSW[6]), .A1(n1139), .B0(DmP_EXP_EWSW[6]), .B1(
n1189), .Y(n1128) );
AOI22X1TS U1509 ( .A0(intDX_EWSW[18]), .A1(n1139), .B0(DmP_EXP_EWSW[18]),
.B1(n1355), .Y(n1129) );
AOI22X1TS U1510 ( .A0(intDX_EWSW[1]), .A1(n1139), .B0(DmP_EXP_EWSW[1]), .B1(
n1189), .Y(n1130) );
AOI22X1TS U1511 ( .A0(intDX_EWSW[0]), .A1(n1139), .B0(DmP_EXP_EWSW[0]), .B1(
n1201), .Y(n1131) );
AOI22X1TS U1512 ( .A0(intDX_EWSW[10]), .A1(n1139), .B0(DmP_EXP_EWSW[10]),
.B1(n1201), .Y(n1132) );
AOI22X1TS U1513 ( .A0(intDX_EWSW[12]), .A1(n1139), .B0(DmP_EXP_EWSW[12]),
.B1(n1189), .Y(n1133) );
AOI22X1TS U1514 ( .A0(intDX_EWSW[8]), .A1(n1139), .B0(DmP_EXP_EWSW[8]), .B1(
n1189), .Y(n1134) );
AOI22X1TS U1515 ( .A0(intDX_EWSW[9]), .A1(n1139), .B0(DmP_EXP_EWSW[9]), .B1(
n1189), .Y(n1135) );
AOI22X1TS U1516 ( .A0(intDX_EWSW[2]), .A1(n1139), .B0(DmP_EXP_EWSW[2]), .B1(
n1189), .Y(n1136) );
AOI22X1TS U1517 ( .A0(intDX_EWSW[11]), .A1(n1139), .B0(DmP_EXP_EWSW[11]),
.B1(n1189), .Y(n1137) );
AOI22X1TS U1518 ( .A0(intDX_EWSW[3]), .A1(n1139), .B0(DmP_EXP_EWSW[3]), .B1(
n1189), .Y(n1138) );
AOI22X1TS U1519 ( .A0(DmP_EXP_EWSW[27]), .A1(n1355), .B0(intDX_EWSW[27]),
.B1(n1139), .Y(n1140) );
AOI22X1TS U1520 ( .A0(intDX_EWSW[15]), .A1(n1112), .B0(DmP_EXP_EWSW[15]),
.B1(n1355), .Y(n1141) );
BUFX3TS U1521 ( .A(n1151), .Y(n1214) );
AOI22X1TS U1522 ( .A0(intDX_EWSW[8]), .A1(n1214), .B0(DMP_EXP_EWSW[8]), .B1(
n1213), .Y(n1143) );
AOI22X1TS U1523 ( .A0(intDX_EWSW[21]), .A1(n1214), .B0(DMP_EXP_EWSW[21]),
.B1(n1201), .Y(n1144) );
AOI22X1TS U1524 ( .A0(intDX_EWSW[7]), .A1(n1214), .B0(DMP_EXP_EWSW[7]), .B1(
n1213), .Y(n1145) );
BUFX3TS U1525 ( .A(n1214), .Y(n1205) );
AOI22X1TS U1526 ( .A0(intDX_EWSW[16]), .A1(n1205), .B0(DMP_EXP_EWSW[16]),
.B1(n1201), .Y(n1146) );
AOI22X1TS U1527 ( .A0(intDX_EWSW[9]), .A1(n1214), .B0(DMP_EXP_EWSW[9]), .B1(
n1213), .Y(n1147) );
AOI22X1TS U1528 ( .A0(n979), .A1(n1355), .B0(intDX_EWSW[27]), .B1(n1151),
.Y(n1148) );
AOI22X1TS U1529 ( .A0(intDX_EWSW[0]), .A1(n1214), .B0(DMP_EXP_EWSW[0]), .B1(
n1113), .Y(n1149) );
AOI22X1TS U1530 ( .A0(intDX_EWSW[20]), .A1(n1151), .B0(DMP_EXP_EWSW[20]),
.B1(n1201), .Y(n1150) );
AOI22X1TS U1531 ( .A0(DMP_EXP_EWSW[23]), .A1(n1355), .B0(intDX_EWSW[23]),
.B1(n1151), .Y(n1152) );
OAI22X1TS U1532 ( .A0(n1630), .A1(intDX_EWSW[25]), .B0(n1629), .B1(
intDX_EWSW[26]), .Y(n1153) );
AOI221X1TS U1533 ( .A0(n1630), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1629), .C0(n1153), .Y(n1159) );
OAI22X1TS U1534 ( .A0(n1622), .A1(intDX_EWSW[27]), .B0(n1635), .B1(
intDY_EWSW[28]), .Y(n1154) );
OAI22X1TS U1535 ( .A0(n1624), .A1(intDY_EWSW[29]), .B0(n1571), .B1(
intDY_EWSW[30]), .Y(n1155) );
AOI221X1TS U1536 ( .A0(n1624), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1571), .C0(n1155), .Y(n1157) );
AOI2BB2XLTS U1537 ( .B0(intDX_EWSW[7]), .B1(n1623), .A0N(n1623), .A1N(
intDX_EWSW[7]), .Y(n1156) );
NAND4XLTS U1538 ( .A(n1159), .B(n1158), .C(n1157), .D(n1156), .Y(n1187) );
OAI22X1TS U1539 ( .A0(n983), .A1(intDX_EWSW[1]), .B0(n1632), .B1(
intDX_EWSW[17]), .Y(n1160) );
OAI22X1TS U1540 ( .A0(n965), .A1(intDX_EWSW[20]), .B0(n1616), .B1(
intDX_EWSW[21]), .Y(n1162) );
OAI22X1TS U1541 ( .A0(n1570), .A1(intDX_EWSW[22]), .B0(n982), .B1(
intDX_EWSW[23]), .Y(n1163) );
NAND4XLTS U1542 ( .A(n1167), .B(n1166), .C(n1165), .D(n1164), .Y(n1186) );
OAI22X1TS U1543 ( .A0(n1559), .A1(intDX_EWSW[24]), .B0(n1614), .B1(
intDX_EWSW[9]), .Y(n1168) );
AOI221X1TS U1544 ( .A0(n1559), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1614), .C0(n1168), .Y(n1175) );
OAI22X1TS U1545 ( .A0(n1619), .A1(intDX_EWSW[12]), .B0(n1615), .B1(
intDX_EWSW[13]), .Y(n1170) );
OAI22X1TS U1546 ( .A0(n1569), .A1(intDX_EWSW[14]), .B0(n1631), .B1(
intDX_EWSW[15]), .Y(n1171) );
NAND4XLTS U1547 ( .A(n1175), .B(n1174), .C(n1173), .D(n1172), .Y(n1185) );
OAI22X1TS U1548 ( .A0(n1620), .A1(intDX_EWSW[16]), .B0(n942), .B1(
intDX_EWSW[0]), .Y(n1176) );
AOI221X1TS U1549 ( .A0(n1620), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n942), .C0(n1176), .Y(n1183) );
OAI22X1TS U1550 ( .A0(n1617), .A1(intDX_EWSW[2]), .B0(n1612), .B1(
intDX_EWSW[3]), .Y(n1177) );
OAI22X1TS U1551 ( .A0(n1618), .A1(intDX_EWSW[4]), .B0(n1568), .B1(
intDX_EWSW[5]), .Y(n1178) );
AOI221X1TS U1552 ( .A0(n1618), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1568), .C0(n1178), .Y(n1181) );
OAI22X1TS U1553 ( .A0(n1633), .A1(intDX_EWSW[8]), .B0(n1613), .B1(
intDX_EWSW[6]), .Y(n1179) );
AOI221X1TS U1554 ( .A0(n1633), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1613), .C0(n1179), .Y(n1180) );
NAND4XLTS U1555 ( .A(n1183), .B(n1182), .C(n1181), .D(n1180), .Y(n1184) );
NOR4X1TS U1556 ( .A(n1187), .B(n1186), .C(n1185), .D(n1184), .Y(n1403) );
CLKXOR2X2TS U1557 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1401) );
INVX2TS U1558 ( .A(n1401), .Y(n1192) );
AOI22X1TS U1559 ( .A0(intDX_EWSW[31]), .A1(n1190), .B0(SIGN_FLAG_EXP), .B1(
n1189), .Y(n1191) );
AOI22X1TS U1560 ( .A0(intDX_EWSW[19]), .A1(n1205), .B0(DMP_EXP_EWSW[19]),
.B1(n1201), .Y(n1193) );
AOI22X1TS U1561 ( .A0(intDX_EWSW[18]), .A1(n1205), .B0(DMP_EXP_EWSW[18]),
.B1(n1201), .Y(n1194) );
AOI22X1TS U1562 ( .A0(intDX_EWSW[10]), .A1(n1205), .B0(DMP_EXP_EWSW[10]),
.B1(n1213), .Y(n1195) );
AOI222X1TS U1563 ( .A0(n920), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1113), .C0(intDY_EWSW[23]), .C1(n1205), .Y(n1196) );
INVX2TS U1564 ( .A(n1196), .Y(n612) );
AOI22X1TS U1565 ( .A0(intDX_EWSW[14]), .A1(n1205), .B0(DMP_EXP_EWSW[14]),
.B1(n1213), .Y(n1197) );
AOI22X1TS U1566 ( .A0(intDX_EWSW[22]), .A1(n1205), .B0(DMP_EXP_EWSW[22]),
.B1(n1201), .Y(n1198) );
AOI22X1TS U1567 ( .A0(intDX_EWSW[17]), .A1(n1205), .B0(DMP_EXP_EWSW[17]),
.B1(n1201), .Y(n1199) );
AOI22X1TS U1568 ( .A0(intDX_EWSW[12]), .A1(n1205), .B0(DMP_EXP_EWSW[12]),
.B1(n1213), .Y(n1200) );
AOI22X1TS U1569 ( .A0(intDX_EWSW[11]), .A1(n1205), .B0(DMP_EXP_EWSW[11]),
.B1(n1201), .Y(n1202) );
AOI22X1TS U1570 ( .A0(intDX_EWSW[13]), .A1(n1205), .B0(DMP_EXP_EWSW[13]),
.B1(n1213), .Y(n1204) );
AOI22X1TS U1571 ( .A0(intDX_EWSW[15]), .A1(n1205), .B0(DMP_EXP_EWSW[15]),
.B1(n1213), .Y(n1206) );
INVX2TS U1572 ( .A(n920), .Y(n1216) );
AOI22X1TS U1573 ( .A0(intDX_EWSW[1]), .A1(n1214), .B0(DMP_EXP_EWSW[1]), .B1(
n1113), .Y(n1208) );
AOI22X1TS U1574 ( .A0(intDX_EWSW[3]), .A1(n1214), .B0(DMP_EXP_EWSW[3]), .B1(
n1213), .Y(n1209) );
AOI22X1TS U1575 ( .A0(intDX_EWSW[2]), .A1(n1214), .B0(DMP_EXP_EWSW[2]), .B1(
n1213), .Y(n1210) );
AOI22X1TS U1576 ( .A0(intDX_EWSW[5]), .A1(n1214), .B0(DMP_EXP_EWSW[5]), .B1(
n1213), .Y(n1211) );
AOI22X1TS U1577 ( .A0(intDX_EWSW[4]), .A1(n1214), .B0(DMP_EXP_EWSW[4]), .B1(
n1213), .Y(n1212) );
AOI22X1TS U1578 ( .A0(intDX_EWSW[6]), .A1(n1214), .B0(DMP_EXP_EWSW[6]), .B1(
n1213), .Y(n1215) );
NOR2XLTS U1579 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1219)
);
AOI211X1TS U1580 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1222), .B0(n1221), .C0(
n1220), .Y(n1225) );
NAND2X1TS U1581 ( .A(Raw_mant_NRM_SWR[1]), .B(n1223), .Y(n1334) );
AOI31X1TS U1582 ( .A0(n1225), .A1(n1224), .A2(n1334), .B0(n925), .Y(n1329)
);
AOI2BB2X1TS U1583 ( .B0(n968), .B1(n1446), .A0N(n1446), .A1N(n968), .Y(
intadd_37_B_2_) );
BUFX3TS U1584 ( .A(n1230), .Y(n1293) );
AOI22X1TS U1585 ( .A0(n921), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1293), .Y(n1234) );
BUFX3TS U1586 ( .A(n1231), .Y(n1282) );
INVX2TS U1587 ( .A(n1286), .Y(n1232) );
AOI22X1TS U1588 ( .A0(n921), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1293), .Y(n1237) );
AOI22X1TS U1589 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1372), .B0(n1382), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1239) );
AOI22X1TS U1590 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1386), .B0(n957), .B1(n977), .Y(n1238) );
NAND2X1TS U1591 ( .A(n1239), .B(n1238), .Y(n1254) );
AOI22X1TS U1592 ( .A0(n1393), .A1(Data_array_SWR[3]), .B0(n1228), .B1(n1254),
.Y(n1241) );
NAND2X1TS U1593 ( .A(Raw_mant_NRM_SWR[19]), .B(n1293), .Y(n1240) );
AOI22X1TS U1594 ( .A0(n921), .A1(Data_array_SWR[21]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n1293), .Y(n1243) );
AOI22X1TS U1595 ( .A0(n921), .A1(Data_array_SWR[2]), .B0(n1228), .B1(n1244),
.Y(n1246) );
NAND2X1TS U1596 ( .A(Raw_mant_NRM_SWR[20]), .B(n1293), .Y(n1245) );
AOI22X1TS U1597 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1372), .B0(n1382), .B1(
n975), .Y(n1248) );
AOI22X1TS U1598 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1386), .B0(n957), .B1(n976), .Y(n1247) );
NAND2X1TS U1599 ( .A(n1248), .B(n1247), .Y(n1276) );
AOI22X1TS U1600 ( .A0(n1393), .A1(Data_array_SWR[7]), .B0(n1228), .B1(n1276),
.Y(n1250) );
NAND2X1TS U1601 ( .A(Raw_mant_NRM_SWR[15]), .B(n1293), .Y(n1249) );
AOI22X1TS U1602 ( .A0(n1393), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1293), .Y(n1252) );
AOI22X1TS U1603 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n1386), .B0(n1382), .B1(
n978), .Y(n1257) );
AOI22X1TS U1604 ( .A0(n1393), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1287), .Y(n1256) );
NAND2X1TS U1605 ( .A(n1286), .B(n1254), .Y(n1255) );
AOI22X1TS U1606 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1372), .B0(n1382), .B1(
n976), .Y(n1259) );
AOI22X1TS U1607 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1386), .B0(n957), .B1(n971), .Y(n1258) );
NAND2X1TS U1608 ( .A(n1259), .B(n1258), .Y(n1285) );
AOI22X1TS U1609 ( .A0(n1393), .A1(Data_array_SWR[6]), .B0(n1228), .B1(n1285),
.Y(n1261) );
NAND2X1TS U1610 ( .A(Raw_mant_NRM_SWR[16]), .B(n1293), .Y(n1260) );
AOI21X1TS U1611 ( .A0(n1386), .A1(n988), .B0(n958), .Y(n1369) );
OAI22X1TS U1612 ( .A0(n1262), .A1(n984), .B0(n1395), .B1(n1641), .Y(n1263)
);
AOI21X1TS U1613 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1287), .B0(n1263), .Y(n1264) );
AOI22X1TS U1614 ( .A0(n921), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1293), .Y(n1267) );
AOI22X1TS U1615 ( .A0(n1393), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1293), .Y(n1270) );
AOI22X1TS U1616 ( .A0(n921), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1293), .Y(n1274) );
AOI22X1TS U1617 ( .A0(n1393), .A1(Data_array_SWR[5]), .B0(n1286), .B1(n1276),
.Y(n1278) );
NAND2X1TS U1618 ( .A(Raw_mant_NRM_SWR[19]), .B(n1287), .Y(n1277) );
AOI22X1TS U1619 ( .A0(n957), .A1(DmP_mant_SHT1_SW[18]), .B0(n1382), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1280) );
AOI21X1TS U1620 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n1386), .B0(n1281), .Y(n1377) );
OAI22X1TS U1621 ( .A0(n1294), .A1(n984), .B0(n1588), .B1(n1299), .Y(n1283)
);
AOI21X1TS U1622 ( .A0(n1393), .A1(Data_array_SWR[18]), .B0(n1283), .Y(n1284)
);
AOI22X1TS U1623 ( .A0(n921), .A1(Data_array_SWR[4]), .B0(n1286), .B1(n1285),
.Y(n1289) );
NAND2X1TS U1624 ( .A(Raw_mant_NRM_SWR[20]), .B(n1287), .Y(n1288) );
AOI22X1TS U1625 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1372), .B0(n1382), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1291) );
AOI21X1TS U1626 ( .A0(n958), .A1(DmP_mant_SHT1_SW[14]), .B0(n1292), .Y(n1381) );
OAI2BB2XLTS U1627 ( .B0(n1294), .B1(n1232), .A0N(Raw_mant_NRM_SWR[6]), .A1N(
n1293), .Y(n1295) );
AOI21X1TS U1628 ( .A0(n921), .A1(Data_array_SWR[16]), .B0(n1295), .Y(n1296)
);
AOI22X1TS U1629 ( .A0(n957), .A1(DmP_mant_SHT1_SW[8]), .B0(n1382), .B1(n974),
.Y(n1297) );
AOI21X1TS U1630 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1386), .B0(n1298), .Y(
n1388) );
OAI22X1TS U1631 ( .A0(n1300), .A1(n984), .B0(n1643), .B1(n1299), .Y(n1301)
);
AOI21X1TS U1632 ( .A0(n1393), .A1(Data_array_SWR[8]), .B0(n1301), .Y(n1302)
);
AOI2BB2X1TS U1633 ( .B0(DmP_mant_SFG_SWR[2]), .B1(OP_FLAG_SFG), .A0N(n1446),
.A1N(DmP_mant_SFG_SWR[2]), .Y(n1452) );
NAND2X1TS U1634 ( .A(n1452), .B(DMP_SFG[0]), .Y(n1454) );
INVX2TS U1635 ( .A(n1454), .Y(n1303) );
INVX2TS U1636 ( .A(DP_OP_15J34_125_2314_n4), .Y(n1304) );
NAND2X1TS U1637 ( .A(n1609), .B(n1304), .Y(n1307) );
INVX2TS U1638 ( .A(n1307), .Y(n1305) );
NAND2X1TS U1639 ( .A(n1626), .B(n1305), .Y(n1310) );
XNOR2X1TS U1640 ( .A(DMP_exp_NRM2_EW[7]), .B(n1310), .Y(n1320) );
INVX2TS U1641 ( .A(n1320), .Y(n1314) );
AND4X1TS U1642 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1348), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1306) );
INVX2TS U1643 ( .A(n1310), .Y(n1311) );
OAI2BB1X1TS U1644 ( .A0N(n1313), .A1N(n1312), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1472) );
OAI2BB2XLTS U1645 ( .B0(n1472), .B1(n1314), .A0N(n1696), .A1N(
final_result_ieee[30]), .Y(n802) );
INVX2TS U1646 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1316) );
INVX2TS U1647 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1315) );
INVX2TS U1648 ( .A(n1414), .Y(n1473) );
OAI2BB2XLTS U1649 ( .B0(n1322), .B1(n1472), .A0N(n1696), .A1N(
final_result_ieee[31]), .Y(n591) );
INVX4TS U1650 ( .A(OP_FLAG_SFG), .Y(n1447) );
AOI22X1TS U1651 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n1446), .B0(n1419), .B1(n994), .Y(intadd_37_CI) );
AOI2BB2X2TS U1652 ( .B0(n981), .B1(n1446), .A0N(n1446), .A1N(n981), .Y(n1432) );
INVX2TS U1653 ( .A(intadd_37_B_2_), .Y(n1325) );
OAI21X1TS U1654 ( .A0(DMP_SFG[7]), .A1(intadd_37_B_1_), .B0(n1323), .Y(n1324) );
AOI222X1TS U1655 ( .A0(n1583), .A1(n1325), .B0(n1583), .B1(n1324), .C0(n1325), .C1(n1324), .Y(n1326) );
INVX2TS U1656 ( .A(n1327), .Y(n1328) );
NAND2X1TS U1657 ( .A(n1592), .B(n1328), .Y(DP_OP_15J34_125_2314_n8) );
MX2X1TS U1658 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n951),
.Y(n659) );
MX2X1TS U1659 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n1343),
.Y(n664) );
MX2X1TS U1660 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n951),
.Y(n669) );
MX2X1TS U1661 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1343),
.Y(n674) );
MX2X1TS U1662 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n951),
.Y(n679) );
MX2X1TS U1663 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1343),
.Y(n684) );
MX2X1TS U1664 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n951),
.Y(n689) );
MX2X1TS U1665 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n956),
.Y(n694) );
OAI211X1TS U1666 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1330), .C0(n1580), .Y(n1338) );
OAI2BB1X1TS U1667 ( .A0N(n1332), .A1N(n1580), .B0(n1331), .Y(n1333) );
OAI21X1TS U1668 ( .A0(n1337), .A1(n1336), .B0(n951), .Y(n1396) );
OAI2BB1X1TS U1669 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n950), .B0(n1396), .Y(
n560) );
OAI21XLTS U1670 ( .A0(n1340), .A1(n1339), .B0(n1338), .Y(n1346) );
OAI22X1TS U1671 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1342), .B0(n1341), .B1(
n1634), .Y(n1344) );
OAI31X1TS U1672 ( .A0(n1346), .A1(n1345), .A2(n1344), .B0(n956), .Y(n1391)
);
OAI2BB1X1TS U1673 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n950), .B0(n1391), .Y(
n571) );
OAI2BB1X1TS U1674 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n1394), .B0(n1384),
.Y(n566) );
NAND2X2TS U1675 ( .A(n1414), .B(Shift_reg_FLAGS_7[0]), .Y(n1351) );
OA22X1TS U1676 ( .A0(n1351), .A1(n1348), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n809) );
OA22X1TS U1677 ( .A0(n1351), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n808) );
OA22X1TS U1678 ( .A0(n1351), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n807) );
OA22X1TS U1679 ( .A0(n1351), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n806) );
OA22X1TS U1680 ( .A0(n1351), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n805) );
OA22X1TS U1681 ( .A0(n1351), .A1(n1349), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n804) );
OA22X1TS U1682 ( .A0(n1351), .A1(n1350), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n803) );
OA21XLTS U1683 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1472),
.Y(n606) );
INVX2TS U1684 ( .A(n1354), .Y(n1353) );
AOI22X1TS U1685 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1353), .B1(n1567), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1686 ( .A(n1353), .B(n1352), .Y(n919) );
AOI22X1TS U1687 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1354), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1567), .Y(n1358) );
AO22XLTS U1688 ( .A0(n1356), .A1(Shift_reg_FLAGS_7_6), .B0(n1357), .B1(n1358), .Y(n917) );
AOI22X1TS U1689 ( .A0(n1357), .A1(n1355), .B0(n1416), .B1(n1356), .Y(n916)
);
AOI22X1TS U1690 ( .A0(n1357), .A1(n1416), .B0(n960), .B1(n1356), .Y(n915) );
AOI22X1TS U1691 ( .A0(n1357), .A1(n1462), .B0(n1394), .B1(n1356), .Y(n912)
);
AND2X2TS U1692 ( .A(beg_OP), .B(n1358), .Y(n1359) );
INVX2TS U1693 ( .A(n1363), .Y(n1366) );
INVX2TS U1694 ( .A(n1363), .Y(n1365) );
BUFX3TS U1695 ( .A(n1359), .Y(n1363) );
BUFX3TS U1696 ( .A(n1359), .Y(n1368) );
BUFX3TS U1697 ( .A(n1359), .Y(n1360) );
INVX2TS U1698 ( .A(n1363), .Y(n1367) );
INVX2TS U1699 ( .A(n1363), .Y(n1361) );
INVX2TS U1700 ( .A(n1363), .Y(n1362) );
OAI22X1TS U1701 ( .A0(n1369), .A1(n985), .B0(n1395), .B1(n1573), .Y(n844) );
OAI2BB2XLTS U1702 ( .B0(n1376), .B1(n984), .A0N(n1393), .A1N(
Data_array_SWR[24]), .Y(n843) );
AOI22X1TS U1703 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1372), .B0(
DmP_mant_SHT1_SW[21]), .B1(n1382), .Y(n1373) );
AOI21X1TS U1704 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n958), .B0(n1375), .Y(n1378) );
OAI222X1TS U1705 ( .A0(n1395), .A1(n1640), .B0(n1390), .B1(n1376), .C0(n985),
.C1(n1378), .Y(n841) );
OAI222X1TS U1706 ( .A0(n1657), .A1(n1395), .B0(n1390), .B1(n1378), .C0(n985),
.C1(n1377), .Y(n839) );
AOI22X1TS U1707 ( .A0(n957), .A1(DmP_mant_SHT1_SW[12]), .B0(n1382), .B1(n972), .Y(n1379) );
AOI21X1TS U1708 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1386), .B0(n1380), .Y(
n1387) );
OAI222X1TS U1709 ( .A0(n1576), .A1(n1395), .B0(n1390), .B1(n1381), .C0(n985),
.C1(n1387), .Y(n833) );
AOI22X1TS U1710 ( .A0(n957), .A1(DmP_mant_SHT1_SW[10]), .B0(n1382), .B1(n973), .Y(n1383) );
AOI21X1TS U1711 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n1386), .B0(n1385), .Y(
n1389) );
OAI222X1TS U1712 ( .A0(n1652), .A1(n1395), .B0(n1390), .B1(n1387), .C0(n985),
.C1(n1389), .Y(n831) );
OAI222X1TS U1713 ( .A0(n1644), .A1(n1395), .B0(n1390), .B1(n1389), .C0(n985),
.C1(n1388), .Y(n829) );
AOI32X1TS U1714 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1395), .A2(n950), .B0(
shift_value_SHT2_EWR[2]), .B1(n921), .Y(n1392) );
NAND2X1TS U1715 ( .A(n1392), .B(n1391), .Y(n818) );
AOI32X1TS U1716 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1395), .A2(n950), .B0(
shift_value_SHT2_EWR[3]), .B1(n1393), .Y(n1397) );
NAND2X1TS U1717 ( .A(n1397), .B(n1396), .Y(n817) );
INVX4TS U1718 ( .A(n1416), .Y(n1407) );
AOI21X1TS U1719 ( .A0(DMP_EXP_EWSW[23]), .A1(n991), .B0(n1398), .Y(n1399) );
AOI2BB2XLTS U1720 ( .B0(n1407), .B1(n1399), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1405), .Y(n814) );
OAI222X1TS U1721 ( .A0(n1411), .A1(n1653), .B0(n1575), .B1(
Shift_reg_FLAGS_7_6), .C0(n1559), .C1(n1413), .Y(n777) );
OAI222X1TS U1722 ( .A0(n1411), .A1(n1577), .B0(n1642), .B1(
Shift_reg_FLAGS_7_6), .C0(n1630), .C1(n1413), .Y(n776) );
OAI222X1TS U1723 ( .A0(n1411), .A1(n1578), .B0(n1655), .B1(
Shift_reg_FLAGS_7_6), .C0(n1629), .C1(n1413), .Y(n775) );
OAI21XLTS U1724 ( .A0(n1401), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1400) );
AOI21X1TS U1725 ( .A0(n1401), .A1(intDX_EWSW[31]), .B0(n1400), .Y(n1402) );
AO21XLTS U1726 ( .A0(OP_FLAG_EXP), .A1(n1113), .B0(n1402), .Y(n770) );
AO22XLTS U1727 ( .A0(n1403), .A1(n1402), .B0(ZERO_FLAG_EXP), .B1(n1113), .Y(
n769) );
AO22XLTS U1728 ( .A0(n1405), .A1(DMP_EXP_EWSW[0]), .B0(n1406), .B1(
DMP_SHT1_EWSW[0]), .Y(n767) );
AO22XLTS U1729 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1408), .B1(
DMP_SHT2_EWSW[0]), .Y(n766) );
BUFX3TS U1730 ( .A(n1404), .Y(n1550) );
INVX4TS U1731 ( .A(n1550), .Y(n1556) );
AO22XLTS U1732 ( .A0(n1405), .A1(DMP_EXP_EWSW[1]), .B0(n1406), .B1(
DMP_SHT1_EWSW[1]), .Y(n764) );
AO22XLTS U1733 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n960), .B1(
DMP_SHT2_EWSW[1]), .Y(n763) );
INVX4TS U1734 ( .A(n1404), .Y(n1549) );
AO22XLTS U1735 ( .A0(n1405), .A1(DMP_EXP_EWSW[2]), .B0(n1406), .B1(
DMP_SHT1_EWSW[2]), .Y(n761) );
AO22XLTS U1736 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1700), .B1(
DMP_SHT2_EWSW[2]), .Y(n760) );
BUFX3TS U1737 ( .A(n1404), .Y(n1539) );
AO22XLTS U1738 ( .A0(n1539), .A1(DMP_SFG[2]), .B0(n1549), .B1(
DMP_SHT2_EWSW[2]), .Y(n759) );
AO22XLTS U1739 ( .A0(n1407), .A1(DMP_EXP_EWSW[3]), .B0(n1406), .B1(
DMP_SHT1_EWSW[3]), .Y(n758) );
AO22XLTS U1740 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1408), .B1(
DMP_SHT2_EWSW[3]), .Y(n757) );
AO22XLTS U1741 ( .A0(n1539), .A1(DMP_SFG[3]), .B0(n1549), .B1(
DMP_SHT2_EWSW[3]), .Y(n756) );
AO22XLTS U1742 ( .A0(n1407), .A1(DMP_EXP_EWSW[4]), .B0(n1406), .B1(
DMP_SHT1_EWSW[4]), .Y(n755) );
AO22XLTS U1743 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1700), .B1(
DMP_SHT2_EWSW[4]), .Y(n754) );
AO22XLTS U1744 ( .A0(n1539), .A1(DMP_SFG[4]), .B0(n1556), .B1(
DMP_SHT2_EWSW[4]), .Y(n753) );
AO22XLTS U1745 ( .A0(n1407), .A1(DMP_EXP_EWSW[5]), .B0(n1406), .B1(
DMP_SHT1_EWSW[5]), .Y(n752) );
AO22XLTS U1746 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1408), .B1(
DMP_SHT2_EWSW[5]), .Y(n751) );
INVX4TS U1747 ( .A(n1550), .Y(n1542) );
AO22XLTS U1748 ( .A0(n1407), .A1(DMP_EXP_EWSW[6]), .B0(n1406), .B1(
DMP_SHT1_EWSW[6]), .Y(n749) );
AO22XLTS U1749 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1700), .B1(
DMP_SHT2_EWSW[6]), .Y(n748) );
AO22XLTS U1750 ( .A0(n1407), .A1(DMP_EXP_EWSW[7]), .B0(n1406), .B1(
DMP_SHT1_EWSW[7]), .Y(n746) );
AO22XLTS U1751 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n987), .B1(
DMP_SHT2_EWSW[7]), .Y(n745) );
BUFX3TS U1752 ( .A(n1550), .Y(n1451) );
AO22XLTS U1753 ( .A0(n1407), .A1(DMP_EXP_EWSW[8]), .B0(n1406), .B1(
DMP_SHT1_EWSW[8]), .Y(n743) );
AO22XLTS U1754 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1700), .B1(
DMP_SHT2_EWSW[8]), .Y(n742) );
INVX4TS U1755 ( .A(n1404), .Y(n1544) );
AO22XLTS U1756 ( .A0(n1451), .A1(DMP_SFG[8]), .B0(n1544), .B1(
DMP_SHT2_EWSW[8]), .Y(n741) );
AO22XLTS U1757 ( .A0(n1407), .A1(DMP_EXP_EWSW[9]), .B0(n1406), .B1(
DMP_SHT1_EWSW[9]), .Y(n740) );
AO22XLTS U1758 ( .A0(n986), .A1(DMP_SHT1_EWSW[9]), .B0(n987), .B1(
DMP_SHT2_EWSW[9]), .Y(n739) );
AO22XLTS U1759 ( .A0(n1407), .A1(DMP_EXP_EWSW[10]), .B0(n1406), .B1(
DMP_SHT1_EWSW[10]), .Y(n737) );
AO22XLTS U1760 ( .A0(n959), .A1(DMP_SHT1_EWSW[10]), .B0(n1408), .B1(
DMP_SHT2_EWSW[10]), .Y(n736) );
AO22XLTS U1761 ( .A0(n1451), .A1(DMP_SFG[10]), .B0(n1549), .B1(
DMP_SHT2_EWSW[10]), .Y(n735) );
CLKBUFX3TS U1762 ( .A(n1416), .Y(n1409) );
AO22XLTS U1763 ( .A0(n1407), .A1(DMP_EXP_EWSW[11]), .B0(n1409), .B1(
DMP_SHT1_EWSW[11]), .Y(n734) );
AO22XLTS U1764 ( .A0(busy), .A1(DMP_SHT1_EWSW[11]), .B0(n1408), .B1(
DMP_SHT2_EWSW[11]), .Y(n733) );
BUFX3TS U1765 ( .A(n1404), .Y(n1538) );
AO22XLTS U1766 ( .A0(n1538), .A1(DMP_SFG[11]), .B0(n1549), .B1(
DMP_SHT2_EWSW[11]), .Y(n732) );
AO22XLTS U1767 ( .A0(n1407), .A1(DMP_EXP_EWSW[12]), .B0(n1409), .B1(
DMP_SHT1_EWSW[12]), .Y(n731) );
AO22XLTS U1768 ( .A0(busy), .A1(DMP_SHT1_EWSW[12]), .B0(n1700), .B1(
DMP_SHT2_EWSW[12]), .Y(n730) );
AO22XLTS U1769 ( .A0(n1539), .A1(DMP_SFG[12]), .B0(n1549), .B1(
DMP_SHT2_EWSW[12]), .Y(n729) );
AO22XLTS U1770 ( .A0(n1407), .A1(DMP_EXP_EWSW[13]), .B0(n1409), .B1(
DMP_SHT1_EWSW[13]), .Y(n728) );
AO22XLTS U1771 ( .A0(busy), .A1(DMP_SHT1_EWSW[13]), .B0(n987), .B1(
DMP_SHT2_EWSW[13]), .Y(n727) );
AO22XLTS U1772 ( .A0(n1451), .A1(DMP_SFG[13]), .B0(n1549), .B1(
DMP_SHT2_EWSW[13]), .Y(n726) );
AO22XLTS U1773 ( .A0(n1407), .A1(DMP_EXP_EWSW[14]), .B0(n1409), .B1(
DMP_SHT1_EWSW[14]), .Y(n725) );
AO22XLTS U1774 ( .A0(busy), .A1(DMP_SHT1_EWSW[14]), .B0(n1408), .B1(
DMP_SHT2_EWSW[14]), .Y(n724) );
AO22XLTS U1775 ( .A0(n1539), .A1(DMP_SFG[14]), .B0(n1549), .B1(
DMP_SHT2_EWSW[14]), .Y(n723) );
AO22XLTS U1776 ( .A0(n1407), .A1(DMP_EXP_EWSW[15]), .B0(n1409), .B1(
DMP_SHT1_EWSW[15]), .Y(n722) );
AO22XLTS U1777 ( .A0(busy), .A1(DMP_SHT1_EWSW[15]), .B0(n1408), .B1(
DMP_SHT2_EWSW[15]), .Y(n721) );
AO22XLTS U1778 ( .A0(n1451), .A1(DMP_SFG[15]), .B0(n1549), .B1(
DMP_SHT2_EWSW[15]), .Y(n720) );
AO22XLTS U1779 ( .A0(n1407), .A1(DMP_EXP_EWSW[16]), .B0(n1409), .B1(
DMP_SHT1_EWSW[16]), .Y(n719) );
AO22XLTS U1780 ( .A0(n1701), .A1(DMP_SHT1_EWSW[16]), .B0(n1408), .B1(
DMP_SHT2_EWSW[16]), .Y(n718) );
AO22XLTS U1781 ( .A0(n1451), .A1(DMP_SFG[16]), .B0(n1544), .B1(
DMP_SHT2_EWSW[16]), .Y(n717) );
INVX4TS U1782 ( .A(n1416), .Y(n1418) );
AO22XLTS U1783 ( .A0(n1418), .A1(DMP_EXP_EWSW[17]), .B0(n1409), .B1(
DMP_SHT1_EWSW[17]), .Y(n716) );
AO22XLTS U1784 ( .A0(n1701), .A1(DMP_SHT1_EWSW[17]), .B0(n1408), .B1(
DMP_SHT2_EWSW[17]), .Y(n715) );
AO22XLTS U1785 ( .A0(n1451), .A1(DMP_SFG[17]), .B0(n1544), .B1(
DMP_SHT2_EWSW[17]), .Y(n714) );
AO22XLTS U1786 ( .A0(n1418), .A1(DMP_EXP_EWSW[18]), .B0(n1409), .B1(
DMP_SHT1_EWSW[18]), .Y(n713) );
AO22XLTS U1787 ( .A0(n1701), .A1(DMP_SHT1_EWSW[18]), .B0(n1408), .B1(
DMP_SHT2_EWSW[18]), .Y(n712) );
AO22XLTS U1788 ( .A0(n1451), .A1(DMP_SFG[18]), .B0(n1544), .B1(
DMP_SHT2_EWSW[18]), .Y(n711) );
AO22XLTS U1789 ( .A0(n1418), .A1(DMP_EXP_EWSW[19]), .B0(n1409), .B1(
DMP_SHT1_EWSW[19]), .Y(n710) );
AO22XLTS U1790 ( .A0(n1701), .A1(DMP_SHT1_EWSW[19]), .B0(n1408), .B1(
DMP_SHT2_EWSW[19]), .Y(n709) );
AO22XLTS U1791 ( .A0(n1451), .A1(DMP_SFG[19]), .B0(n1549), .B1(
DMP_SHT2_EWSW[19]), .Y(n708) );
AO22XLTS U1792 ( .A0(n1418), .A1(DMP_EXP_EWSW[20]), .B0(n1409), .B1(
DMP_SHT1_EWSW[20]), .Y(n707) );
AO22XLTS U1793 ( .A0(n1701), .A1(DMP_SHT1_EWSW[20]), .B0(n1408), .B1(
DMP_SHT2_EWSW[20]), .Y(n706) );
AO22XLTS U1794 ( .A0(n1451), .A1(DMP_SFG[20]), .B0(n1544), .B1(
DMP_SHT2_EWSW[20]), .Y(n705) );
AO22XLTS U1795 ( .A0(n1418), .A1(DMP_EXP_EWSW[21]), .B0(n1409), .B1(
DMP_SHT1_EWSW[21]), .Y(n704) );
AO22XLTS U1796 ( .A0(n1701), .A1(DMP_SHT1_EWSW[21]), .B0(n1700), .B1(
DMP_SHT2_EWSW[21]), .Y(n703) );
AO22XLTS U1797 ( .A0(n1451), .A1(DMP_SFG[21]), .B0(n1544), .B1(
DMP_SHT2_EWSW[21]), .Y(n702) );
BUFX3TS U1798 ( .A(n1659), .Y(n1417) );
AO22XLTS U1799 ( .A0(n1418), .A1(DMP_EXP_EWSW[22]), .B0(n1417), .B1(
DMP_SHT1_EWSW[22]), .Y(n701) );
AO22XLTS U1800 ( .A0(n986), .A1(DMP_SHT1_EWSW[22]), .B0(n987), .B1(
DMP_SHT2_EWSW[22]), .Y(n700) );
AO22XLTS U1801 ( .A0(n1451), .A1(DMP_SFG[22]), .B0(n1549), .B1(
DMP_SHT2_EWSW[22]), .Y(n699) );
AO22XLTS U1802 ( .A0(n1418), .A1(DMP_EXP_EWSW[23]), .B0(n1417), .B1(
DMP_SHT1_EWSW[23]), .Y(n698) );
AO22XLTS U1803 ( .A0(n986), .A1(DMP_SHT1_EWSW[23]), .B0(n1700), .B1(
DMP_SHT2_EWSW[23]), .Y(n697) );
AO22XLTS U1804 ( .A0(n1542), .A1(DMP_SHT2_EWSW[23]), .B0(n1539), .B1(
DMP_SFG[23]), .Y(n696) );
AO22XLTS U1805 ( .A0(n1697), .A1(DMP_SFG[23]), .B0(n1466), .B1(
DMP_exp_NRM_EW[0]), .Y(n695) );
AO22XLTS U1806 ( .A0(n1418), .A1(DMP_EXP_EWSW[24]), .B0(n1417), .B1(
DMP_SHT1_EWSW[24]), .Y(n693) );
AO22XLTS U1807 ( .A0(n986), .A1(DMP_SHT1_EWSW[24]), .B0(n987), .B1(
DMP_SHT2_EWSW[24]), .Y(n692) );
AO22XLTS U1808 ( .A0(n1542), .A1(DMP_SHT2_EWSW[24]), .B0(n1539), .B1(
DMP_SFG[24]), .Y(n691) );
AO22XLTS U1809 ( .A0(n1697), .A1(DMP_SFG[24]), .B0(n1698), .B1(
DMP_exp_NRM_EW[1]), .Y(n690) );
AO22XLTS U1810 ( .A0(n1418), .A1(DMP_EXP_EWSW[25]), .B0(n1417), .B1(
DMP_SHT1_EWSW[25]), .Y(n688) );
AO22XLTS U1811 ( .A0(n959), .A1(DMP_SHT1_EWSW[25]), .B0(n1700), .B1(
DMP_SHT2_EWSW[25]), .Y(n687) );
AO22XLTS U1812 ( .A0(n1542), .A1(DMP_SHT2_EWSW[25]), .B0(n1539), .B1(
DMP_SFG[25]), .Y(n686) );
AO22XLTS U1813 ( .A0(n1697), .A1(DMP_SFG[25]), .B0(n1698), .B1(
DMP_exp_NRM_EW[2]), .Y(n685) );
AO22XLTS U1814 ( .A0(n1418), .A1(DMP_EXP_EWSW[26]), .B0(n1417), .B1(
DMP_SHT1_EWSW[26]), .Y(n683) );
AO22XLTS U1815 ( .A0(n1701), .A1(DMP_SHT1_EWSW[26]), .B0(n987), .B1(
DMP_SHT2_EWSW[26]), .Y(n682) );
AO22XLTS U1816 ( .A0(n1542), .A1(DMP_SHT2_EWSW[26]), .B0(n1539), .B1(
DMP_SFG[26]), .Y(n681) );
AO22XLTS U1817 ( .A0(n1697), .A1(DMP_SFG[26]), .B0(n1698), .B1(
DMP_exp_NRM_EW[3]), .Y(n680) );
AO22XLTS U1818 ( .A0(n1418), .A1(n979), .B0(n1417), .B1(DMP_SHT1_EWSW[27]),
.Y(n678) );
AO22XLTS U1819 ( .A0(n959), .A1(DMP_SHT1_EWSW[27]), .B0(n987), .B1(
DMP_SHT2_EWSW[27]), .Y(n677) );
AO22XLTS U1820 ( .A0(n1542), .A1(DMP_SHT2_EWSW[27]), .B0(n1404), .B1(
DMP_SFG[27]), .Y(n676) );
AO22XLTS U1821 ( .A0(n1697), .A1(DMP_SFG[27]), .B0(n1698), .B1(
DMP_exp_NRM_EW[4]), .Y(n675) );
AO22XLTS U1822 ( .A0(n1418), .A1(DMP_EXP_EWSW[28]), .B0(n1417), .B1(
DMP_SHT1_EWSW[28]), .Y(n673) );
AO22XLTS U1823 ( .A0(n986), .A1(DMP_SHT1_EWSW[28]), .B0(n987), .B1(
DMP_SHT2_EWSW[28]), .Y(n672) );
AO22XLTS U1824 ( .A0(n1542), .A1(DMP_SHT2_EWSW[28]), .B0(n1539), .B1(
DMP_SFG[28]), .Y(n671) );
INVX4TS U1825 ( .A(n1462), .Y(n1461) );
AO22XLTS U1826 ( .A0(n1461), .A1(DMP_SFG[28]), .B0(n1698), .B1(
DMP_exp_NRM_EW[5]), .Y(n670) );
AO22XLTS U1827 ( .A0(n1418), .A1(DMP_EXP_EWSW[29]), .B0(n1417), .B1(
DMP_SHT1_EWSW[29]), .Y(n668) );
AO22XLTS U1828 ( .A0(n959), .A1(DMP_SHT1_EWSW[29]), .B0(n1408), .B1(
DMP_SHT2_EWSW[29]), .Y(n667) );
AO22XLTS U1829 ( .A0(n1542), .A1(DMP_SHT2_EWSW[29]), .B0(n1550), .B1(
DMP_SFG[29]), .Y(n666) );
AO22XLTS U1830 ( .A0(n1697), .A1(DMP_SFG[29]), .B0(n1698), .B1(
DMP_exp_NRM_EW[6]), .Y(n665) );
AO22XLTS U1831 ( .A0(n990), .A1(DMP_EXP_EWSW[30]), .B0(n1417), .B1(
DMP_SHT1_EWSW[30]), .Y(n663) );
AO22XLTS U1832 ( .A0(n986), .A1(DMP_SHT1_EWSW[30]), .B0(n960), .B1(
DMP_SHT2_EWSW[30]), .Y(n662) );
AO22XLTS U1833 ( .A0(n1542), .A1(DMP_SHT2_EWSW[30]), .B0(n1539), .B1(
DMP_SFG[30]), .Y(n661) );
AO22XLTS U1834 ( .A0(n1461), .A1(DMP_SFG[30]), .B0(n1698), .B1(
DMP_exp_NRM_EW[7]), .Y(n660) );
CLKBUFX3TS U1835 ( .A(n1659), .Y(n1410) );
OAI222X1TS U1836 ( .A0(n1413), .A1(n1653), .B0(n1574), .B1(
Shift_reg_FLAGS_7_6), .C0(n1559), .C1(n1411), .Y(n611) );
OAI222X1TS U1837 ( .A0(n1413), .A1(n1577), .B0(n1656), .B1(
Shift_reg_FLAGS_7_6), .C0(n1630), .C1(n1411), .Y(n610) );
OAI222X1TS U1838 ( .A0(n1413), .A1(n1578), .B0(n1651), .B1(
Shift_reg_FLAGS_7_6), .C0(n1629), .C1(n1411), .Y(n609) );
AO21XLTS U1839 ( .A0(underflow_flag), .A1(n1696), .B0(n1415), .Y(n607) );
AO22XLTS U1840 ( .A0(n990), .A1(ZERO_FLAG_EXP), .B0(n1416), .B1(
ZERO_FLAG_SHT1), .Y(n605) );
AO22XLTS U1841 ( .A0(n959), .A1(ZERO_FLAG_SHT1), .B0(n1408), .B1(
ZERO_FLAG_SHT2), .Y(n604) );
AO22XLTS U1842 ( .A0(n1542), .A1(ZERO_FLAG_SHT2), .B0(n1550), .B1(
ZERO_FLAG_SFG), .Y(n603) );
AO22XLTS U1843 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1696), .B1(zero_flag), .Y(n600) );
AO22XLTS U1844 ( .A0(n1418), .A1(OP_FLAG_EXP), .B0(n1416), .B1(OP_FLAG_SHT1),
.Y(n599) );
AO22XLTS U1845 ( .A0(n1701), .A1(OP_FLAG_SHT1), .B0(n1700), .B1(OP_FLAG_SHT2), .Y(n598) );
AO22XLTS U1846 ( .A0(n1538), .A1(OP_FLAG_SFG), .B0(n1549), .B1(OP_FLAG_SHT2),
.Y(n597) );
AO22XLTS U1847 ( .A0(n1418), .A1(SIGN_FLAG_EXP), .B0(n1417), .B1(
SIGN_FLAG_SHT1), .Y(n596) );
AO22XLTS U1848 ( .A0(n986), .A1(SIGN_FLAG_SHT1), .B0(n987), .B1(
SIGN_FLAG_SHT2), .Y(n595) );
AO22XLTS U1849 ( .A0(n1542), .A1(SIGN_FLAG_SHT2), .B0(n1404), .B1(
SIGN_FLAG_SFG), .Y(n594) );
AO22XLTS U1850 ( .A0(n1461), .A1(SIGN_FLAG_SFG), .B0(n1698), .B1(
SIGN_FLAG_NRM), .Y(n593) );
BUFX3TS U1851 ( .A(n1698), .Y(n1466) );
AOI22X1TS U1852 ( .A0(n1461), .A1(intadd_35_SUM_0_), .B0(n1582), .B1(n1466),
.Y(n590) );
AOI22X1TS U1853 ( .A0(n1468), .A1(intadd_35_SUM_2_), .B0(n1580), .B1(n1466),
.Y(n588) );
AOI22X1TS U1854 ( .A0(n1468), .A1(intadd_35_SUM_4_), .B0(n1643), .B1(n1466),
.Y(n586) );
AOI22X1TS U1855 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n1447), .B0(n1446), .B1(
n996), .Y(intadd_35_B_5_) );
AOI22X1TS U1856 ( .A0(n1468), .A1(intadd_35_SUM_5_), .B0(n1598), .B1(n1466),
.Y(n585) );
AOI22X1TS U1857 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1447), .B0(OP_FLAG_SFG),
.B1(n997), .Y(intadd_35_B_8_) );
AOI22X1TS U1858 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1447), .B0(n1446), .B1(
n998), .Y(intadd_35_B_9_) );
AOI22X1TS U1859 ( .A0(n1468), .A1(intadd_35_SUM_9_), .B0(n1590), .B1(n1466),
.Y(n581) );
AOI22X1TS U1860 ( .A0(n1468), .A1(intadd_35_SUM_10_), .B0(n1561), .B1(n1466),
.Y(n580) );
AOI22X1TS U1861 ( .A0(n1461), .A1(intadd_35_SUM_11_), .B0(n1557), .B1(n1466),
.Y(n579) );
AOI22X1TS U1862 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1447), .B0(n1446), .B1(
n1658), .Y(intadd_35_B_12_) );
AOI22X1TS U1863 ( .A0(n1468), .A1(intadd_35_SUM_12_), .B0(n1558), .B1(n1466),
.Y(n578) );
AOI22X1TS U1864 ( .A0(DmP_mant_SFG_SWR[25]), .A1(OP_FLAG_SFG), .B0(n1419),
.B1(n1662), .Y(n1421) );
XNOR2X1TS U1865 ( .A(intadd_35_n1), .B(n1421), .Y(n1422) );
AOI22X1TS U1866 ( .A0(n1468), .A1(n1422), .B0(n1579), .B1(n1462), .Y(n577)
);
NAND3X1TS U1867 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1566), .Y(n1490) );
NAND2X1TS U1868 ( .A(n1566), .B(n1442), .Y(n1470) );
INVX2TS U1869 ( .A(n1477), .Y(n1481) );
AOI22X1TS U1870 ( .A0(Data_array_SWR[22]), .A1(n1424), .B0(
Data_array_SWR[18]), .B1(n1425), .Y(n1506) );
NAND2X2TS U1871 ( .A(n955), .B(n938), .Y(n1520) );
NAND2X2TS U1872 ( .A(n922), .B(n938), .Y(n1529) );
AOI22X1TS U1873 ( .A0(Data_array_SWR[14]), .A1(n1526), .B0(
Data_array_SWR[11]), .B1(n1554), .Y(n1426) );
OAI221X1TS U1874 ( .A0(left_right_SHT2), .A1(n1505), .B0(n922), .B1(n1506),
.C0(n1426), .Y(n1503) );
AOI22X1TS U1875 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n1447), .B0(n1446), .B1(
n1600), .Y(intadd_36_CI) );
INVX2TS U1876 ( .A(intadd_36_B_2_), .Y(n1429) );
AOI222X1TS U1877 ( .A0(DMP_SFG[4]), .A1(n1429), .B0(DMP_SFG[4]), .B1(n1428),
.C0(n1429), .C1(n1428), .Y(n1431) );
AOI2BB2X1TS U1878 ( .B0(n967), .B1(OP_FLAG_SFG), .A0N(n1446), .A1N(n967),
.Y(n1430) );
NAND2X1TS U1879 ( .A(n1430), .B(DMP_SFG[5]), .Y(n1463) );
NOR2X1TS U1880 ( .A(n1430), .B(DMP_SFG[5]), .Y(n1464) );
AOI21X1TS U1881 ( .A0(n1431), .A1(n1463), .B0(n1464), .Y(intadd_37_B_0_) );
AOI2BB2XLTS U1882 ( .B0(n1432), .B1(DMP_SFG[9]), .A0N(DMP_SFG[9]), .A1N(
n1432), .Y(n1433) );
XNOR2X1TS U1883 ( .A(intadd_37_n1), .B(n1433), .Y(n1434) );
AOI22X1TS U1884 ( .A0(n1468), .A1(n1434), .B0(n1581), .B1(n1462), .Y(n575)
);
AOI22X1TS U1885 ( .A0(Data_array_SWR[13]), .A1(n1423), .B0(Data_array_SWR[9]), .B1(n1424), .Y(n1436) );
AOI22X1TS U1886 ( .A0(Data_array_SWR[5]), .A1(n1425), .B0(Data_array_SWR[1]),
.B1(n938), .Y(n1435) );
OAI211X1TS U1887 ( .A0(n1441), .A1(n1566), .B0(n1436), .C0(n1435), .Y(n1531)
);
AOI22X1TS U1888 ( .A0(Data_array_SWR[24]), .A1(n1526), .B0(n922), .B1(n1531),
.Y(n1437) );
AOI22X1TS U1889 ( .A0(n1556), .A1(n1437), .B0(n1538), .B1(n992), .Y(n573) );
AOI22X1TS U1890 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1447), .B0(n1446), .B1(n992), .Y(n1438) );
AOI2BB2XLTS U1891 ( .B0(n1461), .B1(n1438), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1461), .Y(n572) );
AOI22X1TS U1892 ( .A0(Data_array_SWR[12]), .A1(n1425), .B0(
Data_array_SWR[16]), .B1(n1424), .Y(n1440) );
NOR2X2TS U1893 ( .A(n1566), .B(n1482), .Y(n1514) );
AOI22X1TS U1894 ( .A0(Data_array_SWR[20]), .A1(n1423), .B0(
Data_array_SWR[24]), .B1(n1514), .Y(n1439) );
NAND2X1TS U1895 ( .A(n1440), .B(n1439), .Y(n1527) );
INVX2TS U1896 ( .A(n1441), .Y(n1525) );
NOR2X2TS U1897 ( .A(shift_value_SHT2_EWR[4]), .B(n922), .Y(n1499) );
AOI22X1TS U1898 ( .A0(n1556), .A1(n1523), .B0(n1538), .B1(n994), .Y(n570) );
AOI22X1TS U1899 ( .A0(Data_array_SWR[12]), .A1(n1423), .B0(Data_array_SWR[8]), .B1(n1424), .Y(n1444) );
AOI22X1TS U1900 ( .A0(Data_array_SWR[4]), .A1(n1425), .B0(Data_array_SWR[0]),
.B1(n938), .Y(n1443) );
OAI211X1TS U1901 ( .A0(n1494), .A1(n1566), .B0(n1444), .C0(n1443), .Y(n1552)
);
AOI22X1TS U1902 ( .A0(Data_array_SWR[25]), .A1(n1526), .B0(n954), .B1(n1552),
.Y(n1445) );
AOI22X1TS U1903 ( .A0(n1556), .A1(n1445), .B0(n995), .B1(n1404), .Y(n565) );
AOI22X1TS U1904 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1447), .B0(n1446), .B1(n995), .Y(n1448) );
AOI2BB2XLTS U1905 ( .B0(n1461), .B1(n1448), .A0N(n988), .A1N(n1468), .Y(n564) );
OAI22X1TS U1906 ( .A0(n1576), .A1(n1490), .B0(n1644), .B1(n1470), .Y(n1450)
);
INVX2TS U1907 ( .A(n1425), .Y(n1458) );
OAI22X1TS U1908 ( .A0(n1518), .A1(n1566), .B0(n1649), .B1(n1458), .Y(n1449)
);
AOI211X1TS U1909 ( .A0(Data_array_SWR[2]), .A1(n938), .B0(n1450), .C0(n1449),
.Y(n1530) );
OAI22X1TS U1910 ( .A0(n955), .A1(n1530), .B0(n1641), .B1(n1520), .Y(n1522)
);
OAI21XLTS U1911 ( .A0(n1452), .A1(DMP_SFG[0]), .B0(n1454), .Y(n1453) );
AOI22X1TS U1912 ( .A0(n1468), .A1(n1453), .B0(n1585), .B1(n1462), .Y(n562)
);
XNOR2X1TS U1913 ( .A(DMP_SFG[1]), .B(n1454), .Y(n1456) );
XNOR2X1TS U1914 ( .A(n1456), .B(n1455), .Y(n1457) );
AOI22X1TS U1915 ( .A0(n1468), .A1(n1457), .B0(n1634), .B1(n1462), .Y(n561)
);
AO22XLTS U1916 ( .A0(Data_array_SWR[15]), .A1(n1423), .B0(Data_array_SWR[11]), .B1(n1424), .Y(n1460) );
OAI22X1TS U1917 ( .A0(n1476), .A1(n1566), .B0(n1650), .B1(n1458), .Y(n1459)
);
AOI211X1TS U1918 ( .A0(Data_array_SWR[3]), .A1(n938), .B0(n1460), .C0(n1459),
.Y(n1528) );
OAI22X1TS U1919 ( .A0(n955), .A1(n1528), .B0(n1640), .B1(n1520), .Y(n1521)
);
AO22XLTS U1920 ( .A0(n1538), .A1(DmP_mant_SFG_SWR[3]), .B0(n1544), .B1(n1521), .Y(n558) );
AOI22X1TS U1921 ( .A0(n1468), .A1(intadd_36_SUM_0_), .B0(n935), .B1(n1462),
.Y(n557) );
AOI2BB2XLTS U1922 ( .B0(n1461), .B1(intadd_36_SUM_1_), .A0N(
Raw_mant_NRM_SWR[5]), .A1N(n1461), .Y(n556) );
AOI22X1TS U1923 ( .A0(n1468), .A1(intadd_36_SUM_2_), .B0(n1588), .B1(n1462),
.Y(n555) );
NAND2BXLTS U1924 ( .AN(n1464), .B(n1463), .Y(n1465) );
XNOR2X1TS U1925 ( .A(intadd_36_n1), .B(n1465), .Y(n1467) );
AOI22X1TS U1926 ( .A0(n1468), .A1(n1467), .B0(n1584), .B1(n1466), .Y(n554)
);
AOI22X1TS U1927 ( .A0(Data_array_SWR[10]), .A1(n1425), .B0(
Data_array_SWR[18]), .B1(n1423), .Y(n1469) );
AOI21X1TS U1928 ( .A0(Data_array_SWR[22]), .A1(n1514), .B0(n1471), .Y(n1475)
);
INVX2TS U1929 ( .A(n1499), .Y(n1515) );
OAI222X1TS U1930 ( .A0(n1529), .A1(n1649), .B0(left_right_SHT2), .B1(n1475),
.C0(n1515), .C1(n1476), .Y(n1474) );
AO22XLTS U1931 ( .A0(n1538), .A1(DmP_mant_SFG_SWR[6]), .B0(n1544), .B1(n1474), .Y(n553) );
NOR2X2TS U1932 ( .A(shift_value_SHT2_EWR[4]), .B(n955), .Y(n1524) );
INVX2TS U1933 ( .A(n1524), .Y(n1519) );
OAI222X1TS U1934 ( .A0(n1520), .A1(n1649), .B0(n1519), .B1(n1476), .C0(n954),
.C1(n1475), .Y(n1543) );
AOI22X1TS U1935 ( .A0(Data_array_SWR[20]), .A1(n1478), .B0(
Data_array_SWR[24]), .B1(n1477), .Y(n1498) );
AOI22X1TS U1936 ( .A0(Data_array_SWR[12]), .A1(n1424), .B0(Data_array_SWR[8]), .B1(n1425), .Y(n1480) );
NAND2X1TS U1937 ( .A(Data_array_SWR[16]), .B(n1423), .Y(n1479) );
OAI211X1TS U1938 ( .A0(n1498), .A1(n1566), .B0(n1480), .C0(n1479), .Y(n1484)
);
AOI22X1TS U1939 ( .A0(n1556), .A1(n1483), .B0(n1600), .B1(n1404), .Y(n550)
);
INVX2TS U1940 ( .A(n952), .Y(n1532) );
OAI2BB2XLTS U1941 ( .B0(n1483), .B1(n1532), .A0N(final_result_ieee[2]),
.A1N(n1696), .Y(n549) );
OAI2BB2XLTS U1942 ( .B0(n1546), .B1(n1532), .A0N(final_result_ieee[19]),
.A1N(n1696), .Y(n548) );
AOI22X1TS U1943 ( .A0(Data_array_SWR[12]), .A1(n1554), .B0(
Data_array_SWR[13]), .B1(n1526), .Y(n1485) );
OAI221X1TS U1944 ( .A0(left_right_SHT2), .A1(n1487), .B0(n922), .B1(n1488),
.C0(n1485), .Y(n1533) );
AOI22X1TS U1945 ( .A0(Data_array_SWR[12]), .A1(n1526), .B0(
Data_array_SWR[13]), .B1(n1554), .Y(n1486) );
OAI221X1TS U1946 ( .A0(n955), .A1(n1488), .B0(n922), .B1(n1487), .C0(n1486),
.Y(n1534) );
AOI22X1TS U1947 ( .A0(Data_array_SWR[17]), .A1(n1424), .B0(
Data_array_SWR[13]), .B1(n1425), .Y(n1489) );
AOI21X1TS U1948 ( .A0(Data_array_SWR[25]), .A1(n1514), .B0(n1491), .Y(n1493)
);
OAI222X1TS U1949 ( .A0(n1529), .A1(n1654), .B0(left_right_SHT2), .B1(n1493),
.C0(n1515), .C1(n1494), .Y(n1492) );
AO22XLTS U1950 ( .A0(n1538), .A1(DmP_mant_SFG_SWR[9]), .B0(n1544), .B1(n1492), .Y(n545) );
OAI222X1TS U1951 ( .A0(n1520), .A1(n1654), .B0(n1519), .B1(n1494), .C0(n954),
.C1(n1493), .Y(n1537) );
AOI22X1TS U1952 ( .A0(Data_array_SWR[13]), .A1(n1424), .B0(Data_array_SWR[9]), .B1(n1425), .Y(n1497) );
AOI22X1TS U1953 ( .A0(Data_array_SWR[17]), .A1(n1423), .B0(
shift_value_SHT2_EWR[4]), .B1(n1495), .Y(n1496) );
NAND2X1TS U1954 ( .A(n1497), .B(n1496), .Y(n1502) );
INVX2TS U1955 ( .A(n1498), .Y(n1501) );
AOI22X1TS U1956 ( .A0(n1556), .A1(n1500), .B0(n1601), .B1(n1550), .Y(n542)
);
OAI2BB2XLTS U1957 ( .B0(n1500), .B1(n1532), .A0N(final_result_ieee[3]),
.A1N(n1696), .Y(n541) );
OAI2BB2XLTS U1958 ( .B0(n1545), .B1(n1532), .A0N(final_result_ieee[18]),
.A1N(n1696), .Y(n540) );
AOI22X1TS U1959 ( .A0(Data_array_SWR[14]), .A1(n1554), .B0(
Data_array_SWR[11]), .B1(n1526), .Y(n1504) );
OAI221X1TS U1960 ( .A0(left_right_SHT2), .A1(n1506), .B0(n924), .B1(n1505),
.C0(n1504), .Y(n1535) );
AOI22X1TS U1961 ( .A0(Data_array_SWR[23]), .A1(n1424), .B0(
Data_array_SWR[19]), .B1(n1425), .Y(n1511) );
AOI22X1TS U1962 ( .A0(Data_array_SWR[10]), .A1(n1554), .B0(
Data_array_SWR[15]), .B1(n1526), .Y(n1507) );
OAI221X1TS U1963 ( .A0(left_right_SHT2), .A1(n1510), .B0(n954), .B1(n1511),
.C0(n1507), .Y(n1508) );
AO22XLTS U1964 ( .A0(n1538), .A1(n968), .B0(n1544), .B1(n1508), .Y(n537) );
AOI22X1TS U1965 ( .A0(Data_array_SWR[10]), .A1(n1526), .B0(
Data_array_SWR[15]), .B1(n1554), .Y(n1509) );
OAI221X1TS U1966 ( .A0(left_right_SHT2), .A1(n1511), .B0(n922), .B1(n1510),
.C0(n1509), .Y(n1536) );
AOI22X1TS U1967 ( .A0(Data_array_SWR[19]), .A1(n1423), .B0(
Data_array_SWR[11]), .B1(n1425), .Y(n1512) );
OAI2BB1X1TS U1968 ( .A0N(Data_array_SWR[15]), .A1N(n1424), .B0(n1512), .Y(
n1513) );
AOI21X1TS U1969 ( .A0(Data_array_SWR[23]), .A1(n1514), .B0(n1513), .Y(n1517)
);
OAI222X1TS U1970 ( .A0(n1529), .A1(n1650), .B0(left_right_SHT2), .B1(n1517),
.C0(n1515), .C1(n1518), .Y(n1516) );
AO22XLTS U1971 ( .A0(n1538), .A1(n967), .B0(n1544), .B1(n1516), .Y(n534) );
OAI222X1TS U1972 ( .A0(n1520), .A1(n1650), .B0(n1519), .B1(n1518), .C0(n922),
.C1(n1517), .Y(n1541) );
OAI2BB2XLTS U1973 ( .B0(n1523), .B1(n1532), .A0N(final_result_ieee[6]),
.A1N(n1696), .Y(n529) );
OAI2BB2XLTS U1974 ( .B0(n1540), .B1(n1532), .A0N(final_result_ieee[15]),
.A1N(n1696), .Y(n528) );
OAI22X1TS U1975 ( .A0(n1528), .A1(n954), .B0(n1640), .B1(n1529), .Y(n1547)
);
OAI22X1TS U1976 ( .A0(n1530), .A1(n922), .B0(n1641), .B1(n1529), .Y(n1548)
);
AOI22X1TS U1977 ( .A0(Data_array_SWR[24]), .A1(n1554), .B0(n955), .B1(n1531),
.Y(n1551) );
AO22XLTS U1978 ( .A0(n1538), .A1(DmP_mant_SFG_SWR[12]), .B0(n1544), .B1(
n1533), .Y(n524) );
AO22XLTS U1979 ( .A0(n1538), .A1(DmP_mant_SFG_SWR[13]), .B0(n1544), .B1(
n1534), .Y(n523) );
AO22XLTS U1980 ( .A0(n1538), .A1(DmP_mant_SFG_SWR[14]), .B0(n1544), .B1(
n1535), .Y(n522) );
AO22XLTS U1981 ( .A0(n1404), .A1(DmP_mant_SFG_SWR[15]), .B0(n1556), .B1(
n1536), .Y(n521) );
AO22XLTS U1982 ( .A0(n1538), .A1(DmP_mant_SFG_SWR[16]), .B0(n1549), .B1(
n1537), .Y(n520) );
AOI22X1TS U1983 ( .A0(n1556), .A1(n1540), .B0(n1539), .B1(n996), .Y(n519) );
AO22XLTS U1984 ( .A0(n1404), .A1(DmP_mant_SFG_SWR[18]), .B0(n1542), .B1(
n1541), .Y(n518) );
AO22XLTS U1985 ( .A0(n1404), .A1(DmP_mant_SFG_SWR[19]), .B0(n1544), .B1(
n1543), .Y(n517) );
AOI22X1TS U1986 ( .A0(n1556), .A1(n1545), .B0(n997), .B1(n1550), .Y(n516) );
AOI22X1TS U1987 ( .A0(n1556), .A1(n1546), .B0(n998), .B1(n1550), .Y(n515) );
AO22XLTS U1988 ( .A0(n1404), .A1(DmP_mant_SFG_SWR[22]), .B0(n1549), .B1(
n1547), .Y(n514) );
AO22XLTS U1989 ( .A0(n1404), .A1(DmP_mant_SFG_SWR[23]), .B0(n1549), .B1(
n1548), .Y(n513) );
AOI22X1TS U1990 ( .A0(n1556), .A1(n1551), .B0(n1658), .B1(n1550), .Y(n512)
);
AOI22X1TS U1991 ( .A0(Data_array_SWR[25]), .A1(n1554), .B0(left_right_SHT2),
.B1(n1552), .Y(n1555) );
AOI22X1TS U1992 ( .A0(n1556), .A1(n1555), .B0(n1662), .B1(n1404), .Y(n511)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk20.tcl_GDAN16M4P4_syn.sdf");
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream register
*/
module axis_register #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// Register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter REG_TYPE = 2
)
(
input wire clk,
input wire rst,
/*
* AXI Stream input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI Stream output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser
);
generate
if (REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
reg s_axis_tready_reg = 1'b0;
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_input_to_output;
reg store_axis_input_to_temp;
reg store_axis_temp_to_output;
assign s_axis_tready = s_axis_tready_reg;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axis_tready_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !s_axis_tvalid));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_input_to_output = 1'b0;
store_axis_input_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (s_axis_tready_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = s_axis_tvalid;
store_axis_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = s_axis_tvalid;
store_axis_input_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
s_axis_tready_reg <= 1'b0;
m_axis_tvalid_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
s_axis_tready_reg <= s_axis_tready_early;
m_axis_tvalid_reg <= m_axis_tvalid_next;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_input_to_output) begin
m_axis_tdata_reg <= s_axis_tdata;
m_axis_tkeep_reg <= s_axis_tkeep;
m_axis_tlast_reg <= s_axis_tlast;
m_axis_tid_reg <= s_axis_tid;
m_axis_tdest_reg <= s_axis_tdest;
m_axis_tuser_reg <= s_axis_tuser;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_input_to_temp) begin
temp_m_axis_tdata_reg <= s_axis_tdata;
temp_m_axis_tkeep_reg <= s_axis_tkeep;
temp_m_axis_tlast_reg <= s_axis_tlast;
temp_m_axis_tid_reg <= s_axis_tid;
temp_m_axis_tdest_reg <= s_axis_tdest;
temp_m_axis_tuser_reg <= s_axis_tuser;
end
end
end else if (REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
reg s_axis_tready_reg = 1'b0;
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_input_to_output;
assign s_axis_tready = s_axis_tready_reg;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output buffer will be empty
wire s_axis_tready_early = !m_axis_tvalid_next;
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
store_axis_input_to_output = 1'b0;
if (s_axis_tready_reg) begin
m_axis_tvalid_next = s_axis_tvalid;
store_axis_input_to_output = 1'b1;
end else if (m_axis_tready) begin
m_axis_tvalid_next = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
s_axis_tready_reg <= 1'b0;
m_axis_tvalid_reg <= 1'b0;
end else begin
s_axis_tready_reg <= s_axis_tready_early;
m_axis_tvalid_reg <= m_axis_tvalid_next;
end
// datapath
if (store_axis_input_to_output) begin
m_axis_tdata_reg <= s_axis_tdata;
m_axis_tkeep_reg <= s_axis_tkeep;
m_axis_tlast_reg <= s_axis_tlast;
m_axis_tid_reg <= s_axis_tid;
m_axis_tdest_reg <= s_axis_tdest;
m_axis_tuser_reg <= s_axis_tuser;
end
end
end else begin
// bypass
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = KEEP_ENABLE ? s_axis_tkeep : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tlast = LAST_ENABLE ? s_axis_tlast : 1'b1;
assign m_axis_tid = ID_ENABLE ? s_axis_tid : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? s_axis_tdest : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? s_axis_tuser : {USER_WIDTH{1'b0}};
assign s_axis_tready = m_axis_tready;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_16_V
`define SKY130_FD_SC_HS__CLKINV_16_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkinv_16 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_16_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__AND2B_FUNCTIONAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_FUNCTIONAL_PP_V |
/*
* DSI Core
* Copyright (C) 2013-2014 twl <[email protected]>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 3 of the License, or (at your option) any later version.
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/1ps
/*
* dsi_utils.v
*
* Some utility stuff (parity/CRC generators)
*/
module dsi_parity
(
input [23:0] d_i,
output [7:0] p_o
);
assign p_o[0]=^{d_i[2:0], d_i[5:4], d_i[7], d_i[11:10], d_i[13], d_i[16], d_i[23:20]};
assign p_o[1]=^{d_i[1:0], d_i[4:3], d_i[6], d_i[8], d_i[10], d_i[12], d_i[14], d_i[17], d_i[23:20]};
assign p_o[2]=^{d_i[0], d_i[3:2], d_i[6:5], d_i[9], d_i[12:11], d_i[15], d_i[18], d_i[22:20] };
assign p_o[3]=^{d_i[3:1], d_i[9:7], d_i[15:13], d_i[21:19], d_i[23]};
assign p_o[4]=^{d_i[9:4], d_i[20:16], d_i[23:22]};
assign p_o[5]=^{d_i[19:10], d_i[23:21]};
assign p_o[7:6]=2'b0;
endmodule // dsi_parity
module dsi_crc_comb (input[15:0] crc, input[7:0] x, output [15:0] crc_new);
assign crc_new[0] = crc[8] ^ crc[12] ^ x[7-0] ^ x[7-4];
assign crc_new[1] = crc[9] ^ crc[13] ^ x[7-1] ^ x[7-5];
assign crc_new[2] = crc[10] ^ crc[14] ^ x[7-2] ^ x[7-6];
assign crc_new[3] = crc[11] ^ crc[15] ^ x[7-3] ^ x[7-7];
assign crc_new[4] = crc[12] ^ x[7-4];
assign crc_new[5] = crc[8] ^ crc[12] ^ crc[13] ^ x[7-0] ^ x[7-4] ^ x[7-5];
assign crc_new[6] = crc[9] ^ crc[13] ^ crc[14] ^ x[7-1] ^ x[7-5] ^ x[7-6];
assign crc_new[7] = crc[10] ^ crc[14] ^ crc[15] ^ x[7-2] ^ x[7-6] ^ x[7-7];
assign crc_new[8] = crc[0] ^ crc[11] ^ crc[15] ^ x[7-3] ^ x[7-7];
assign crc_new[9] = crc[1] ^ crc[12] ^ x[7-4];
assign crc_new[10] = crc[2] ^ crc[13] ^ x[7-5];
assign crc_new[11] = crc[3] ^ crc[14] ^ x[7-6];
assign crc_new[12] = crc[4] ^ crc[8] ^ crc[12] ^ crc[15] ^ x[7-0] ^ x[7-4] ^ x[7-7];
assign crc_new[13] = crc[5] ^ crc[9] ^ crc[13] ^ x[7-1] ^ x[7-5];
assign crc_new[14] = crc[6] ^ crc[10] ^ crc[14] ^ x[7-2] ^ x[7-6];
assign crc_new[15] = crc[7] ^ crc[11] ^ crc[15] ^ x[7-3] ^ x[7-7];
endmodule // dsi_crc_comb
module dsi_crc
(
clk_i,
rst_i,
valid_i,
nbytes_i,
d_i,
crc_o);
parameter g_max_data_bytes = 3;
input [g_max_data_bytes*8-1:0] d_i;
input valid_i;
input [2:0] nbytes_i;
input clk_i;
input rst_i;
output [15:0] crc_o;
reg [15:0] crc_cur;
wire [15:0] stages_in [0:g_max_data_bytes-1];
wire [15:0] stages_out [0:g_max_data_bytes-1];
generate
genvar i ;
for(i=0;i<g_max_data_bytes;i=i+1)
begin
if(i != g_max_data_bytes-1)
assign stages_in[i] = (nbytes_i == (i+1) ? crc_cur : stages_out[i+1]);
dsi_crc_comb stageX(stages_in[i], d_i[8*i+7:8*i], stages_out[i]);
end
assign stages_in[g_max_data_bytes-1] = crc_cur;
endgenerate
always@(posedge clk_i)
if(rst_i)
crc_cur <= 16'hffff;
else if(valid_i)
crc_cur <= stages_out[0];
assign crc_o = {crc_cur[0], crc_cur[1],crc_cur[2], crc_cur[3],
crc_cur[4], crc_cur[5],crc_cur[6], crc_cur[7],
crc_cur[8], crc_cur[9],crc_cur[10], crc_cur[11],
crc_cur[12], crc_cur[13],crc_cur[14], crc_cur[15]};
endmodule // dsi_crc
module dsi_wishbone_async_bridge
#(
parameter g_csr_addr_bits = 10
)
(
input clk_wb_i,
input clk_csr_i,
input rst_n_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
output wb_stall_o,
output reg [31:0] wb_dat_o,
output reg [g_csr_addr_bits-1:0] csr_adr_o,
output reg [31:0] csr_dat_o,
output csr_wr_o,
input [31:0] csr_dat_i
);
`define ST_IDLE 0
`define ST_WAIT_ACK 1
`define ST_ACK 2
reg [1:0] state;
reg req_wb, req_write;
wire req_csr;
reg wb_stb_d0 = 0;
reg wb_stall;
reg ack_csr;
wire ack_wb;
dsi_sync_chain sc_req_to_csr (clk_csr_i, rst_n_i, req_wb, req_csr);
dsi_sync_chain sc_ack_to_wb (clk_wb_i, rst_n_i, ack_csr, ack_wb);
reg req_csr_d0;
reg ack_wb_d0;
always@(posedge clk_csr_i) req_csr_d0 <= req_csr;
always@(posedge clk_wb_i) ack_wb_d0 <= ack_wb;
always@(posedge clk_wb_i or negedge rst_n_i)
if(!rst_n_i)
begin
wb_stb_d0 <= 0;
wb_stall <= 1;
end else begin
wb_stb_d0 <= wb_stb_i & wb_cyc_i;
wb_stall <= ~ (wb_stb_i & wb_cyc_i & !wb_stb_d0);
end
always@(posedge clk_wb_i or negedge rst_n_i)
if(!rst_n_i)
begin
state <= `ST_IDLE;
req_wb <= 0;
wb_ack_o <= 0;
end else begin
case (state)
`ST_IDLE: if(wb_cyc_i && wb_stb_i) begin
req_wb <= 1;
wb_ack_o <= 0;
req_write <= wb_we_i;
csr_dat_o <= wb_dat_i;
csr_adr_o <= wb_adr_i[g_csr_addr_bits+1:2];
state <= `ST_WAIT_ACK;
end
`ST_WAIT_ACK:
if(ack_wb) begin
req_wb <= 0;
end else if (ack_wb_d0) begin
wb_dat_o <= csr_dat_i;
wb_ack_o <= 1;
state <= `ST_ACK;
end
`ST_ACK: begin
wb_ack_o <=0;
state <= `ST_IDLE;
end
endcase // case (state)
end // if (!rst_n_i)
assign csr_wr_o = req_wb & req_write & !req_csr_d0 & req_csr;
always@(posedge clk_csr_i)
ack_csr <= req_csr;
assign wb_stall_o = wb_stall;
endmodule // dsi_wishbone_async_bridge
module dsi_sync_chain
#( parameter length = 2)
(
input clk_i,
input rst_n_i,
input d_i,
output q_o );
reg [length-1:0] sync;
always@(posedge clk_i)
begin
sync[0] <= d_i;
sync[length-1:1] <= sync[length-2:0];
end
assign q_o = sync[length-1];
endmodule // dsi_sync_chain
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ddr3_s4_uniphy_p0_pll_memphy.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 208 07/03/2011 SP 1.10 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddr3_s4_uniphy_p0_pll_memphy (
areset,
inclk0,
c0,
c1,
c2,
c3,
c4,
c5,
c6,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output c6;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] sub_wire0;
wire sub_wire8;
wire [0:0] sub_wire11 = 1'h0;
wire [3:3] sub_wire7 = sub_wire0[3:3];
wire [6:6] sub_wire6 = sub_wire0[6:6];
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [5:5] sub_wire2 = sub_wire0[5:5];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c5 = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire c4 = sub_wire5;
wire c6 = sub_wire6;
wire c3 = sub_wire7;
wire locked = sub_wire8;
wire sub_wire9 = inclk0;
wire [1:0] sub_wire10 = {sub_wire11, sub_wire9};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire10),
.clk (sub_wire0),
.locked (sub_wire8),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 80,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 213,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 40,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 213,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 40,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 213,
altpll_component.clk2_phase_shift = "235",
altpll_component.clk3_divide_by = 80,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 213,
altpll_component.clk3_phase_shift = "2817",
altpll_component.clk4_divide_by = 160,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 213,
altpll_component.clk4_phase_shift = "0",
altpll_component.clk5_divide_by = 80,
altpll_component.clk5_duty_cycle = 50,
altpll_component.clk5_multiply_by = 71,
altpll_component.clk5_phase_shift = "0",
altpll_component.clk6_divide_by = 320,
altpll_component.clk6_duty_cycle = 50,
altpll_component.clk6_multiply_by = 71,
altpll_component.clk6_phase_shift = "0",
altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Stratix IV",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=ddr3_s4_uniphy_p0_pll_memphy",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_USED",
altpll_component.port_clk6 = "PORT_USED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "80"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "40"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "40"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "80"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "160"
// Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "80"
// Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "320"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "266.250000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "532.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "532.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "266.250000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "133.125000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "88.750000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE6 STRING "22.187500"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "10000.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "ps"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "71"
// Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "71"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "235.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "2817.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "ddr3_s4_uniphy_p0_pll_memphy.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK5 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK6 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLK5 STRING "1"
// Retrieval info: PRIVATE: USE_CLK6 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "40"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "40"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "235"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2817"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "160"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK6_DIVIDE_BY NUMERIC "320"
// Retrieval info: CONSTANT: CLK6_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK6_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK6_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5"
// Retrieval info: USED_PORT: c6 0 0 0 0 OUTPUT_CLK_EXT VCC "c6"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5
// Retrieval info: CONNECT: c6 0 0 0 0 @clk 0 0 1 6
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_pll_memphy.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_pll_memphy.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_pll_memphy.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_pll_memphy.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_pll_memphy.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_pll_memphy_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_pll_memphy_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// MBT 11/26/2014
//
// bsg_nonsynth_fsb_node_trace_replay
//
// note: generally it is better to use
// bsg_fsb_node_trace_replay
// than this module, because 1)
// it is synthesizeable, and 2)
// it may have races (see fixme)
//
// trace format
//
//
// 0: wait one cycle
// 1: send data
// 2: receive data
// 3: assert done_o; test complete.
// 4: end test; call $finish
`include "bsg_defines.v"
module bsg_nonsynth_fsb_node_trace_replay
#(parameter ring_width_p=80
, parameter `BSG_INV_PARAM(master_id_p)
, parameter `BSG_INV_PARAM(slave_id_p)
, parameter filename_p="trace.in"
)
(input clk_i
, input reset_i
, input en_i
// input channel
, input v_i
, input [ring_width_p-1:0] data_i
, output ready_o
// output channel
, output v_o
, output [ring_width_p-1:0] data_o
, input yumi_i
, output reg done_o
);
integer data_file, result_code;
//logic [7:0] read_line[255:0];
string read_line;
logic [ring_width_p-1:0] data_r;
logic [3:0] op_r;
logic eof;
logic next_line_r;
logic [$bits(byte) * 1000-1:0] filename_string;
string filename_path = filename_p;
initial
begin
// check for command line argument; otherwise use default.
if ($test$plusargs("fsb_trace"))
begin
if ($value$plusargs("fsb_trace=%s", filename_string))
begin
// make it prettier when we print it out
filename_path = string ' (filename_string);
$display("### %m using filename %s", filename_path);
end
end
data_file = $fopen(filename_path,"r");
if (data_file == 0)
begin
$display("############################################################################");
$display("### %m Failed to open file %s", filename_path);
$display("############################################################################");
$finish;
end
else
begin
$display("############################################################################");
$display("### %m OPENED FILE %s", filename_path);
$display("############################################################################");
end
next_line_r = 1;
eof = 0;
op_r = 0;
done_o = 0;
end
assign v_o = ~reset_i & ~eof & (op_r == 1) & en_i;
assign data_o = data_r;
wire receive_op = (op_r == 2);
// we absorb data if we are receiving or if we are done.
assign ready_o = receive_op | done_o;
// mbt fixme: I suspect this should actually
// be done on the negative edge of the clock
// to avoid races.
always @(posedge clk_i)
begin
if (!done_o)
begin
case (op_r)
0: next_line_r = 1;
1:
// send data
if (v_o & yumi_i)
begin
next_line_r = 1;
// for now we just print out the data
$display("### trace %s sent %h", filename_p, data_r);
end
2:
// receive and check
if (v_i)
begin
if (data_i != data_r)
begin
$display("############################################################################");
$display("### %m ");
$display("### ");
$display("### FAIL (trace mismatch) = %h", data_i);
$display("### expected = %h\n", data_r);
$display("############################################################################");
$finish();
end
else
begin
$display("### %m trace %s matched %h", filename_p, data_r);
next_line_r = 1;
end // else: !if(data_i != data_r)
end // if (v_i)
3:
begin
$display("############################################################################");
$display("###### done_o=1 (trace %s finished) (%m)", filename_p);
$display("############################################################################");
done_o = 1;
end
4:
begin
$display("############################################################################");
$display("###### DONE (trace %s finished; CALLING $finish) (%m)", filename_p);
$display("############################################################################");
$finish;
end
default:
$display("%m unknown op %x\n", op_r);
endcase
if (next_line_r)
begin
next_line_r = 0;
result_code = $fgets (read_line, data_file);
if (result_code == 0)
eof = 1;
// skip comments
while (!eof & ((read_line[0] == "\n") || (read_line[0] == " ") || (read_line[0] == "") || (read_line[0] == "#")))
begin
result_code = $fgets (read_line, data_file);
if (result_code == 0)
eof = 1;
end
if (eof)
begin
$display("############################################################################");
$display("###### End of Trace (trace %s finished) (%m)", filename_p);
$display("############################################################################");
end
else
begin
result_code = $sscanf(read_line, "%b\n", {op_r, data_r});
if (result_code == 0)
begin
$display("### error reading file %s:\n", read_line);
$finish();
end
end
end // if (next_line_r)
end // if (!done_o)
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_fsb_node_trace_replay)
|
(**************************************************************)
(** * Coq for POPL Folk *)
(**************************************************************)
(** A streamlined interactive tutorial on fundamentals of Coq,
focusing on a minimal set of features needed for developing
programming language metatheory.
Mostly developed by Aaron Bohannon, with help from Benjamin
Pierce, Dimitrios Vytiniotis, and Steve Zdancewic.
*)
(**************************************************************)
(** * Contents
- Getting Started
- Definitions
- Proofs
-- Working with Implication and Universal Quantification
-- Working with Definitions
-- Working with Conjunction and Disjunction
-- Reasoning by Cases and Induction
-- Working with Existential Quantification
-- Working with Negation
-- Working with Equality
-- Reasoning by Inversion
-- Additional Important Tactics
-- Basic Automation
-- Functions and Conversion
- Solutions to Exercises
*)
(**************************************************************)
(**************************************************************)
(** To get started...
- Install Coq (from the Download page of the main Coq web
site)
- Install an IDE: either CoqIDE (from the same page) or
Proof General (use Google to find it).
- Which should you choose? Their command sets are similar,
so basically the trade-offs are simple:
-- Proof General is an extension of Emacs (or XEmacs,
if you prefer), while CoqIDE uses a simpler
point-and-click model of editing.
-- PG is pretty easy to install; CoqIDE is very easy
to install if you can find a pre-built version for
the OS you are running on but can be a little tricky
to build from scratch because it has lots of
dependencies.
- Familiarize yourself with the most important commands
-- If you are using PG, try this:
--- Open this file and check that the mode line says
something like "coq Holes Scripting"
--- Go down a few pages and do C-C C-return. Notice
that the part of the file above the cursor
changes color (and becomes read-only),
indicating that it has been sent to Coq.
--- Come back here and do C-C C-return again
--- You now know all you really need to navigate in
this file and send parts of it to Coq, but there
are some other navigation commands that are
sometimes more convenient. To see a couple
more, do C-C C-n several times and observe the
result; then do C-C C-u a couple of times and
observe the result.
-- If you are using CoqIDE, try this:
--- Open this file.
--- Scroll down a few pages.
--- Hover the mouse over each the buttons at the top
of the window; this will make the "tool tips"
appear so you can see which is which.
--- Press the "Go to cursor" button. Observe what
happens.
--- Press the forward and backward buttons a few
times. Observe.
--- Scroll back to here again and start reading.
- Open the Coq reference manual (from the Documentation
page of the Coq web site) in a web browser. Spend 30
seconds looking over the table of contents to get an idea
what's there. (There is no need to actually read
anything now.)
*)
(**************************************************************)
(** * Definitions *)
(**************************************************************)
(** In this file, we will be working with a very simple language
of expressions over natural numbers and booleans. First we
need to define the datatype of terms.
The [Inductive] keyword defines a new inductive type. We
name our new type [tm] and declare that [tm] lives in the
sort [Set]. Types in [Set] are datatypes, which can be used
just like those in standard programming languages. After
the inductive definition, the global environment contains
the name of the newly defined type, along with the names of
all of the constructors. Coq also automatically defines a
few operators for eliminating values of the new type
([tm_rec], [tm_ind], etc.); we can ignore these for the time
being, since we will not need to use them directly.
*)
Inductive tm : Set :=
| tm_true : tm
| tm_false : tm
| tm_if : tm -> tm -> tm -> tm
| tm_zero : tm
| tm_succ : tm -> tm
| tm_pred : tm -> tm
| tm_iszero : tm -> tm.
Hint Constructors tm.
(** Next, we want to designate some of our [tm] expressions as
"values" in our object language. Mathematically, the
property of being a value is a unary relation over [tm]s.
The definition of the unary relation [value] will be built
from the definition of two auxiliary relations: [bvalue] for
the set of boolean values and [nvalue] for the set of
numerical values.
We define n-ary relations in Coq much as we do on paper --
by giving a set of inference rules that can be used to
justify the membership of a tuple in the relation. The
definition of such an inference system also uses the keyword
[Inductive]. Although this is exactly the same device we
used to build the set [tm], in this case we want to do
something slightly different: we will be using it to
inductively defining the structures (derivation trees) that
justify the membership of a tuple in a relation, rather than
directly defining a set inductively. These derivation trees
will need to be given a dependent type in order to ensure
that only correct derivation trees can be built. It is
possible to view their type as a datatype such as [tm];
however, it is more natural to interpret it as a
proposition, so it will be declared to live in [Prop]
instead of [Set]. [Prop] is parallel to [Set] in the sort
hierarchy, but types in [Prop] can be thought of as logical
propositions rather than datatypes. The inhabitants of
types in [Prop] can be thought of as proofs rather than
programs.
The unary relations [bvalue] and [nvalue] are defined by
very simple inference systems, each having just two rules.
After defining these inference systems, [bvalue] and
[nvalue] will each be a family of types indexed by elements
of [tm]. We can build inhabitants of some (but not all) of
the types in these families with the constructors from our
inductive definition. Semantically, we consider the
proposition [bvalue t] to be true if it is inhabited and
false if it is not. (It is worth noting at this point that,
by default, Coq's logic is constructive and [P \/ not P] is
provable for some [P] but not for others. However, it is
sound to add the law of the excluded middle as an axiom, if
desired.)
*)
Inductive bvalue : tm -> Prop :=
| b_true : bvalue tm_true
| b_false : bvalue tm_false.
Inductive nvalue : tm -> Prop :=
| n_zero : nvalue tm_zero
| n_succ : forall t,
nvalue t ->
nvalue (tm_succ t).
Hint Constructors bvalue.
Hint Constructors nvalue.
(** The [Definition] keyword is used for defining non-recursive
functions (including 0-ary functions, i.e., constants).
Here we define the unary predicate [value] using disjunction
on propositions (written [\/]).
Note: It is not actually necessary to provide the types of
the arguments nor the return type when they can easily be
inferred; for example, the annotations [: tm] and [: Prop]
are optional here.
*)
Definition value (t : tm) : Prop :=
bvalue t \/ nvalue t.
(** Having defined [tm]s and [value]s, we can define a
call-by-value operational semantics of our language by
giving a definition of the single-step evaluation of one
term to another. We give this as an inductively defined
binary relation.
*)
Inductive eval : tm -> tm -> Prop :=
| e_iftrue : forall t2 t3,
eval (tm_if tm_true t2 t3) t2
| e_iffalse : forall t2 t3,
eval (tm_if tm_false t2 t3) t3
| e_if : forall t1 t1' t2 t3,
eval t1 t1' ->
eval (tm_if t1 t2 t3) (tm_if t1' t2 t3)
| e_succ : forall t t',
eval t t' ->
eval (tm_succ t) (tm_succ t')
| e_predzero :
eval (tm_pred tm_zero) tm_zero
| e_predsucc : forall t,
nvalue t ->
eval (tm_pred (tm_succ t)) t
| e_pred : forall t t',
eval t t' ->
eval (tm_pred t) (tm_pred t')
| e_iszerozero :
eval (tm_iszero tm_zero) tm_true
| e_iszerosucc : forall t,
nvalue t ->
eval (tm_iszero (tm_succ t)) tm_false
| e_iszero : forall t t',
eval t t' ->
eval (tm_iszero t) (tm_iszero t').
Hint Constructors eval.
(** We define multi-step evaluation with the relation
[eval_many]. This relation includes all of the pairs of
terms that are connected by sequences of evaluation steps.
*)
Inductive eval_many : tm -> tm -> Prop :=
| m_refl : forall t,
eval_many t t
| m_step : forall t t' u,
eval t t' ->
eval_many t' u ->
eval_many t u.
Hint Constructors eval_many.
(** a*** Exercise
Multi-step evaluation is often defined as the "reflexive,
transitive closure" of single-step evaluation. Write an
inductively defined relation [eval_rtc] that corresponds to
that verbal description.
In case you get stuck or need a hint, you can find solutions
to all the exercises near the bottom of the file.
*)
Inductive eval_rtc : tm -> tm -> Prop :=
| rtc_eval : forall t t', eval t t' -> eval_rtc t t'
| rtc_refl : forall t, eval_rtc t t
| rtc_trans : forall t u s,
eval_rtc t u -> eval_rtc u s -> eval_rtc t s.
(** A term is a [normal_form] if there is no term to which it
can step. Note the concrete syntax for negation and
existential quantification in the definition below.
*)
Hint Constructors eval_rtc.
Definition normal_form (t : tm) : Prop :=
~ exists t', eval t t'.
(** *** Exercise
Sometimes it is more convenient to use a big-step semantics
for a language. Add the remaining constructors to finish
the inductive definition [full_eval] for the big-step
semantics that corresponds to the small-step semantics
defined by [eval]. Build the inference rules so that
[full_eval t v] logically implies both [eval_many t v] and
[value v]. In order to do this, you may need to add the
premise [nvalue v] to the appropriate cases.
Hint: You should end up with a total of 8 cases.
*)
Inductive full_eval : tm -> tm -> Prop :=
| f_value : forall v,
value v ->
full_eval v v
| f_iftrue : forall t1 t2 t3 v,
full_eval t1 tm_true ->
full_eval t2 v ->
full_eval (tm_if t1 t2 t3) v
| f_iffalse : forall t1 t2 t3 v,
full_eval t1 tm_false ->
full_eval t3 v ->
full_eval (tm_if t1 t2 t3) v
| f_succ : forall t v,
nvalue v ->
full_eval t v ->
full_eval (tm_succ t) (tm_succ v)
| f_predzero : forall t,
full_eval t tm_zero ->
full_eval (tm_pred t) tm_zero
| f_predsucc : forall t v,
nvalue v ->
full_eval t (tm_succ v) ->
full_eval (tm_pred t) v
| f_iszerozero : forall t,
full_eval t tm_zero ->
full_eval (tm_iszero t) tm_true
| f_iszerosucc : forall t v,
nvalue v ->
full_eval t (tm_succ v) ->
full_eval (tm_iszero t) tm_false.
Hint Constructors full_eval.
(** *** Tip
If you want to see the type of an identifier [x], you can
use the command [Check x.] If you want to see the
definition of an identifier [x], you can use the command
[Print x.]
*)
Check tm_if.
Check m_step.
Check value.
Print value.
(**************************************************************)
(** * Proofs *)
(**************************************************************)
(** A proposition and its proof are both represented as terms in
the calculus of inductive constructions, which is
syntactically very small.
Proof terms are most easily built interactively, using
tactics to manipulate a proof state. A proof state consists
of a set of goals (propositions or types for which you must
produce an inhabitant), each with a context of hypotheses
(inhabitants of propositions or types you are allowed to
use). A proof state begins initially with one goal (the
statement of the lemma you are tying to prove) and no
hypotheses. A goal can be solved, and thereby eliminated,
when it exactly matches one of hypotheses in the context. A
proof is completed when all goals are solved.
Tactics can be used for forward reasoning (which, roughly
speaking, means modifying the hypotheses of a context while
leaving the goal unchanged) or backward reasoning (replacing
the current goal with one or more new goals in simpler
contexts). Given the level of detail required in a formal
proof, it would be ridiculously impractical to complete a
proof using forward reasoning alone. However it is usually
both possible and practical to complete a proof using
backward reasoning alone. Therefore, we focus almost
exclusively on backward reasoning in this tutorial. Of
course, most people naturally a significant amount of
forward reasoning in their thinking process, so it may take
you a while to become accustomed to getting by without it.
We use the keyword [Lemma] to state a new proposition we
wish to prove. ([Theorem] and [Fact] are exact synonyms for
[Lemma].) The keyword [Proof], immediately following the
statement of the proposition, indicates the beginning of a
proof script. A proof script is a sequence of tactic
expressions, each concluding with a "[.]". Once all of the
goals are solved, we use the keyword [Qed] to record the
completed proof. If the proof is incomplete, we may tell
Coq to accept the lemma on faith by using [Admitted] instead
of [Qed].
We now proceed to introduce the specific proof tactics.
*)
(**************************************************************)
(** ** Working with Implication and Universal Quantification
- [intros]
- [apply]
- [apply with (x := ...)]
*)
(** *** Example
The tactic [intros x1 ... xn] moves antecedents and
universally quantified variables from the goal into the
context as hypotheses. The tactic [apply] is complementary
to [intros]. If the conclusion (the part following the
rightmost arrow) of a constructor, hypothesis, or lemma [e]
matches our current goal, then [apply e] will replace the
goal with a new goal for each premise/antecedent of [e]. If
[e] has no premises, then the current goal is solved. Using
[apply] allows us to build a proof tree from the bottom up.
In the following example, our proof script will effectively
build the following proof tree:
<<
nvalue t
---------------------------- (e_predsucc)
eval (tm_pred (tm_succ t)) t
------------------------------------------------ (e_succ)
eval (tm_succ (tm_pred (tm_succ t))) (tm_succ t)
>>
Step through the proof to see how this tree is constructed.
For each tactic, we give the corresponding statement in a
written proof. (The uses of [Check] are inessential.)
*)
Lemma e_succ_pred_succ : forall t,
nvalue t ->
eval (tm_succ (tm_pred (tm_succ t))) (tm_succ t).
Proof.
(** Let [t] be a [tm]. *)
intros t.
(** Assume that [t] is an [nvalue] (and let's call that
assumption [Hn] for future reference). *)
intros Hn.
(** By [e_succ], in order to prove our conclusion, it suffices
to prove that [eval (tm_pred (tm_succ t)) t]. *)
Check e_succ.
apply e_succ.
(** That, in turn, can be shown by [e_predsucc], if we are
able to show that [nvalue t]. *)
Check e_predsucc.
apply e_predsucc.
(** But, in fact, we assumed [nvalue t]. *)
apply Hn.
Qed.
(** *** Hint for PG users
If you place the cursor after [Proof.] and do C-c C-return,
you'll notice that the window displaying Coq's responses is
(annoyingly) empty, instead of showing what is to be proved.
The reason for this is that, actually, a different buffer is
being displayed! (To see this, do C-c C-n and C-c C-u a few
times and notice that the buffer name in the mode line
changes.) You can use C-c C-p to switch the display back
from the *response* buffer to the *goals* buffer.
*)
(** *** Example
Now consider, for a moment, the rule [m_step]:
<<
eval t t' eval_many t' u
------------------------- (m_step)
eval_many t u
>>
If we have a goal such as [eval_many e1 e2], we should be
able to use [apply m_step] in order to replace it with the
goals [eval e1 t'] and [eval_many t' e2]. But what exactly
is [t'] here? When and how is it chosen? It stands to
reason the conclusion is justified if we can come up with
any [t'] for which the premises can be justified.
Now we note that, in the Coq syntax for the type of
[m_step], all three variables [t], [t'], and [u] are
universally quantified. The tactic [apply m_step] will use
pattern matching between our goal and the conclusion of
[m_step] to find the only possible instantiation of [t] and
[u]. However, [apply m_step] will raise an error since it
does not know how it should instantiate [t']. In this case,
the [apply] tactic takes a [with] clause that allows us to
provide this instantiation. This is demonstrated in the
proof below. (Note that the use of this feature means that
our proof scripts are not invariant under alpha-equivalence
on the types of our constructors and lemmas. If this is a
concern, there are other means of achieving the same result
in a way that is compatible with alpha-conversion. See the
next example.)
Observe how this works in the proof script below. The proof
tree here gives a visual representation of the proof term we
are going to construct and the proof script has again been
annotated with the steps in English.
<<
Letting s = tm_succ
p = tm_pred
lem = e_succ_pred_succ,
nvalue t
- - - - - - - - - - - - (lem) --------------------- (m_refl)
eval (s (p (s t))) (s t) eval_many (s t) (s t)
--------------------------------------------------- (m_step)
eval_many (s (p (s t))) (s t)
>>
*)
Lemma m_succ_pred_succ : forall t,
nvalue t ->
eval_many (tm_succ (tm_pred (tm_succ t))) (tm_succ t).
Proof.
(** Let [t] be a [tm], and assume [nvalue t]. *)
intros t Hn.
(** By [m_step], to show our conclusion, it suffices to find
some [t'] for which
[eval (tm_succ (tm_pred (tm_succ t))) t']
and
[eval t' (tm_succ t)].
Let us choose [t'] to be [tm_succ t]. *)
Check m_step.
apply m_step with (t' := tm_succ t).
(** By the lemma [e_succ_pred_succ], to show
[eval (tm_succ (tm_pred (tm_succ t))) (tm_succ t)],
it suffices to show [nvalue t]. *)
Check e_succ_pred_succ.
apply e_succ_pred_succ.
(** And, in fact, we assumed [nvluae t]. *)
apply Hn.
(** Moreover, by the rule [m_refl], we also may conclude
[eval (tm_succ t) (tm_succ t)]. *)
Check m_refl.
apply m_refl.
Qed.
(** *** Example
Coq is built around the Curry-Howard correspondence.
Proofs of universally quantified propositions are functions
that take the witness of the quantifier as an argument.
Similarly, proofs of implications are functions that take
one proof as an argument and return another proof. Observe
the types of the following terms.
*)
Check (e_succ_pred_succ).
Check (e_succ_pred_succ tm_zero).
Check (n_zero).
Check (e_succ_pred_succ tm_zero n_zero).
(** *** Example
Any tactic like [apply] that takes the name of a constructor
or lemma as an argument can just as easily be given a more
complicated expression as an argument. Thus, we may use
function application to construct proof objects on the fly
in these cases. Observe how this technique can be used to
rewrite the proof of the previous lemma.
Although, we have eliminated one use of [apply], this is not
necessarily an improvement over the previous proof.
However, there are cases where this technique is quite
valuable.
*)
Lemma m_succ_pred_succ_alt : forall t,
nvalue t ->
eval_many (tm_succ (tm_pred (tm_succ t))) (tm_succ t).
Proof.
intros t Hn.
Check m_step.
apply (m_step
(tm_succ (tm_pred (tm_succ t)))
(tm_succ t)
(tm_succ t)
).
Check e_succ_pred_succ.
apply (e_succ_pred_succ t Hn).
Check m_refl.
apply (m_refl (tm_succ t)).
Qed.
(** *** Hint for PG users
By default, the "." key is "electric" -- it inserts a period
_and_ causes the material up to the cursor to be sent to
Coq. If you find this behavior annoying, it can be toggled
by doing "C-c .".
*)
(*
LAB 1: (10 minutes)
Work on the following three exercises.
*)
(** *** Exercise
Write a proof script to prove the following lemma, based
upon the proof given in English.
Note: The lemma and the next should be useful in later
proofs.
*)
Lemma m_one : forall t1 t2,
eval t1 t2 ->
eval_many t1 t2.
Proof.
(** Let [t1] and [t2] be terms, and assume [eval t1 t2]. We
may conclude [eval_many t1 t2] by [m_step] if we can find
a term [t'] such that [eval t1 t'] and [eval_many t' t2].
We will choose [t'] to be [t2]. Now we can show
[eval t1 t2] by our assumption, and we can show
[eval_many t2 t2] by [m_refl]. *)
eauto.
Qed.
Hint Resolve m_one.
(** *** Exercise *)
Lemma m_two : forall t1 t2 t3,
eval t1 t2 ->
eval t2 t3 ->
eval_many t1 t3.
Proof.
(** Let [t1], [t2], and [t3] be terms. Assume [eval t1 t2]
and [eval t2 t3]. By [m_step], we may conclude that
[eval_many t1 t3] if we can find a term [t'] such that
[eval t1 t'] and [eval_many t' t3]. Let's choose [t'] to
be [t2]. We know [eval t1 t2] holds by assumption. In
the other case, by the lemma [m_one], to show [eval_many
t2 t3], it suffices to show [eval t2 t3], which is one of
our assumptions. *)
eauto.
Qed.
Hint Resolve m_two.
(** *** Exercise *)
Lemma m_iftrue_step : forall t t1 t2 u,
eval t tm_true ->
eval_many t1 u ->
eval_many (tm_if t t1 t2) u.
Proof.
(** Let [t], [t1], [t2], and [u] be terms. Assume that
[eval t tm_true] and [eval_many t1 u]. To show
[eval_many (tm_if t t1 t2) u], by [m_step], it suffices to
find a [t'] for which [eval (tm_if t t1 t2) t'] and
[eval_many t' u]. Let us choose [t'] to be
[tm_if tm_true t1 t2]. Now we can use [e_if] to show that
[eval (tm_if t t1 t2) (tm_if tm_true t1 t2)] if we can
show [eval t tm_true], which is actually one of our
assumptions. Moreover, using [m_step] once more, we can
show [eval_many (tm_if tm_true t1 t2) u] where [t'] is
chosen to be [t1]. Doing so leaves us to show
[eval (tm_if tm_true t1 t2) t1] and [eval_many t1 u]. The
former holds by [e_iftrue] and the latter holds by
assumption. *)
eauto.
Qed.
(**************************************************************)
(** ** Working with Definitions
- [unfold]
*)
(** *** Example
There is a notion of equivalence on Coq terms that arises
from the conversion rules of the underlying calculus of
constructions. It is sometimes useful to be able to replace
one term in a proof with an equivalent one. For instance,
we may want to replace a defined name with its definition.
This sort of replacement can be done the tactic [unfold].
This tactic can be used to manipulate the goal or the
hypotheses.
*)
Definition strongly_diverges t :=
forall u, eval_many t u -> ~ normal_form u.
Lemma unfold_example : forall t t',
strongly_diverges t ->
eval t t' ->
strongly_diverges t'.
Proof.
intros t t' Hd He.
unfold strongly_diverges. intros u Hm.
unfold strongly_diverges in Hd.
apply Hd. apply m_step with (t' := t').
apply He.
apply Hm.
Qed.
(** *** Exercise
In reality, many tactics will perform conversion
automatically as necessary. Try removing the uses of
[unfold] from the above proof to check which ones were
necessary.
*)
Lemma unfold_example' : forall t t',
strongly_diverges t ->
eval t t' ->
strongly_diverges t'.
Proof.
intros t t' Hd He.
intros u Hm.
apply Hd. apply m_step with (t' := t').
apply He.
apply Hm.
Qed.
(**************************************************************)
(** ** Working with Conjunction and Disjunction
- [split]
- [left]
- [right]
- [destruct] (for conjunction and disjunction)
*)
(** *** Example
If [H] is the name of a conjunctive hypothesis, then
[destruct H as p] will replace the hypothesis [H] with its
components using the names in the pattern [p]. Observe the
pattern in the example below.
*)
Lemma m_two_conj : forall t t' t'',
eval t t' /\ eval t' t'' ->
eval_many t t''.
Proof.
intros t t' t'' H.
destruct H as [ He1 He2 ].
apply m_two with (t2 := t').
apply He1.
apply He2.
Qed.
(** *** Example
Patterns may be nested to break apart nested structures.
Note that infix conjunction is right-associative, which is
significant when trying to write nested patterns. We will
later see how to use [destruct] on many different sorts of
hypotheses.
*)
Lemma m_three_conj : forall t t' t'' t''',
eval t t' /\ eval t' t'' /\ eval t'' t''' ->
eval_many t t'''.
Proof.
intros t t' t'' t''' H.
destruct H as [ He1 [ He2 He3 ] ].
apply m_step with (t' := t').
apply He1.
apply m_two with (t2 := t'').
apply He2.
apply He3.
Qed.
(** *** Example
If your goal is a conjunction, use [split] to break it apart
into two separate subgoals.
*)
Lemma m_three : forall t t' t'' t''',
eval t t' ->
eval t' t'' ->
eval t'' t''' ->
eval_many t t'''.
Proof.
intros t t' t'' t''' He1 He2 He3.
apply m_three_conj with (t' := t') (t'' := t'').
split.
apply He1.
split.
apply He2.
apply He3.
Qed.
Hint Resolve m_three.
(** *** Exercise
Hint: You might find lemma [m_three] useful here.
*)
Lemma m_if_iszero_conj : forall v t2 t2' t3 t3',
nvalue v /\ eval t2 t2' /\ eval t3 t3' ->
eval_many (tm_if (tm_iszero tm_zero) t2 t3) t2' /\
eval_many (tm_if (tm_iszero (tm_succ v)) t2 t3) t3'.
Proof.
intros v t2 t2' t3 t3' [H1 [H2 H3]].
split; eauto.
Qed.
(** *** Example
If the goal is a disjunction, we can use the [left] or
[right] tactics to solve it by proving the left or right
side of the conclusion.
*)
Lemma true_and_succ_zero_values :
value tm_true /\ value (tm_succ tm_zero).
Proof.
unfold value. split.
left. apply b_true.
right. apply n_succ. apply n_zero.
Qed.
(** *** Example
If we have a disjunction in the context, we can use
[destruct] to reason by cases on the hypothesis. Note the
syntax of the associated pattern.
*)
Lemma e_if_true_or_false : forall t1 t2,
eval t1 tm_true \/ eval t1 tm_false ->
eval_many (tm_if t1 t2 t2) t2.
Proof.
intros t1 t2 H. destruct H as [ He1 | He2 ].
apply m_two with (t2 := tm_if tm_true t2 t2).
apply e_if. apply He1.
apply e_iftrue.
apply m_two with (t2 := tm_if tm_false t2 t2).
apply e_if. apply He2.
apply e_iffalse.
Qed.
(*
LAB 2: (10 minutes)
Work on the following exercise.
*)
(** *** Exercise *)
Lemma two_values : forall t u,
value t /\ value u ->
bvalue t \/
bvalue u \/
(nvalue t /\ nvalue u).
Proof.
(** We know [value t] and [value u], which means either
[bvalue t] or [nvalue t], and either [bvalue u] or
[nvalue u]. Consider the case in which
[bvalue t] holds. Then one of the disjuncts of our
conclusion is proved. Next, consider the case in which
[nvalue t] holds. Now consider the subcase where
[bvalue u] holds. ... *)
intros t u [ H1 H2 ].
destruct H1; destruct H2; auto.
Qed.
(** *** Example
[destruct] can be used on propositions with implications.
This will have the effect of performing [destruct] on the
conclusion of the implication, while leaving the hypotheses
of the implication as additional subgoals.
*)
Lemma destruct_example : forall bv t t' t'',
bvalue bv ->
(value bv -> eval t t' /\ eval t' t'') ->
eval_many t t''.
Proof.
intros bv t t' t'' Hbv H. destruct H as [ H1 H2 ].
Show 2.
unfold value. left. apply Hbv.
apply m_two with (t2 := t').
apply H1.
apply H2.
Qed.
(** *** Tip
After applying a tactic that introduces multiple subgoals,
it is sometimes useful to see not only the subgoals
themselves but also their hypotheses. Adding the command
[Show n.] to your proof script to cause Coq to display the
nth subgoal in full.
*)
(**************************************************************)
(** ** Reasoning by Cases and Induction
- [destruct] (for inductively defined propositions)
- [induction]
*)
(** *** Example
Use [destruct] to reason by cases on an inductively defined
datatype or proposition.
Note: It is possible to supply [destruct] with a pattern in
these instances also. However, the patterns become
increasingly complex for bigger inductive definitions; so it
is often more practical to omit the pattern (thereby letting
Coq choose the names of the terms and hypotheses in each
case), in spite of the fact that this adds an element of
fragility to the proof script (since the proof script will
mention names that were system-generated).
*)
Lemma e_iszero_nvalue : forall v,
nvalue v ->
eval (tm_iszero v) tm_true \/
eval (tm_iszero v) tm_false.
Proof.
intros v Hn. destruct Hn.
(* Case [n_zero].
Note how [v] becomes [tm_zero] in the goal. *)
left. apply e_iszerozero.
(* Case [n_succ].
Note how [v] becomes [tm_succ v] in the goal. *)
right. apply e_iszerosucc. apply Hn.
Qed.
(** *** Example
You can use [induction] to reason by induction on an
inductively defined datatype or proposition. This is the
same as [destruct], except that it also introduces an
induction hypothesis in the inductive cases.
*)
Lemma m_iszero : forall t u,
eval_many t u ->
eval_many (tm_iszero t) (tm_iszero u).
Proof.
intros t u Hm. induction Hm.
apply m_refl.
apply m_step with (t' := tm_iszero t').
apply e_iszero. apply H.
apply IHHm.
Qed.
(*
LAB 3: (5 minutes)
Work on the following exercise.
*)
(** *** Exercise *)
Lemma m_trans : forall t t' u,
eval_many t t' ->
eval_many t' u ->
eval_many t u.
Proof.
(** We proceed by induction on the derivation of
[eval_many t t'].
Case [m_refl]: Since [t] and [t'] must be the same, our
conclusion holds by assumption.
Case [m_step]: Now let's rename the [t'] from the lemma
statement to [u0] (as Coq likely will) and observe that
there must be some [t'] (from above the line of the
[m_step] rule) such that [eval t t'] and
[eval_many t' u0]. Our conclusion follows from from
an application of [m_step] with our new [t'] and our
induction hypothesis, which allows us to piece together
[eval_many t' u0] and [eval_many u0 u] to get
[eval_many t' u]. *)
intros t t' u H H0.
eauto.
induction H; eauto.
Qed.
Hint Resolve m_trans.
(** *** Exercise
It is possible to use [destruct] not just on hypotheses but
on any lemma we have proved. If we have a lemma
<<
lemma1 : P /\ Q
>>
then we can use the tactic
<<
destruct lemma1 as [ H1 H2 ].
>>
to continue our proof with [H1 : P] and [H2 : Q] in our
context. This works even if the lemma has antecedents (they
become new subgoals); however it fail if the lemma has a
universal quantifier, such as this:
<<
lemma2 : forall x, P(x) /\ Q(x)
>>
However, remember that we can build a proof of
[P(e) /\ Q(e)] (which can be destructed) using the Coq
expression [lemma2 e]. So we need to phrase our tactic as
<<
destruct (lemma2 e) as [ H1 H2 ].
>>
An example of this technique is below.
*)
Lemma m_iszero_nvalue : forall t v,
nvalue v ->
eval_many t v ->
eval_many (tm_iszero t) tm_true \/
eval_many (tm_iszero t) tm_false.
Proof.
intros t v Hnv Hm.
destruct (e_iszero_nvalue v) as [ H1 | H2 ].
apply Hnv.
left. apply m_trans with (t' := tm_iszero v).
apply m_iszero. apply Hm.
apply m_one. apply H1.
right. apply m_trans with (t' := tm_iszero v).
apply m_iszero. apply Hm.
apply m_one. apply H2.
Qed.
(** *** Exercise
Prove the following lemma.
Hint: You may be interested in some previously proved
lemmas, such as [m_one] and [m_trans].
Note: Even though this lemma is in a comment, its solution
is also at the bottom. (Coq will give an error if we leave
it uncommented since it mentions the [eval_rtc] relation,
which was the solution to another exercise.)
*)
Lemma eval_rtc_many : forall t u,
eval_rtc t u ->
eval_many t u.
Proof.
intros t u H.
induction H.
destruct H; eauto.
auto.
apply m_trans with u; auto.
Qed.
(** *** Exercise
Prove the following lemma.
*)
Lemma eval_many_rtc : forall t u,
eval_many t u ->
eval_rtc t u.
Proof.
intros t u H.
induction H; eauto.
Qed.
(** *** Exercise
Prove the following lemma.
*)
Lemma full_eval_to_value : forall t v,
full_eval t v ->
value v.
Proof.
intros t v H.
induction H; eauto.
unfold value. destruct IHfull_eval. destruct H1; inversion H.
auto.
destruct IHfull_eval. inversion H1. destruct H1;
right; auto.
left; auto.
left; auto.
Qed.
(**************************************************************)
(** ** Working with Existential Quantification
- [exists]
- [destruct] (for existential propositions)
*)
(** *** Example
Use [exists] to give the witness for an existential
quantifier in your goal.
*)
Lemma if_bvalue : forall t1 t2 t3,
bvalue t1 ->
exists u, eval (tm_if t1 t2 t3) u.
Proof.
intros t1 t2 t3 Hb. destruct Hb.
exists t2. apply e_iftrue.
exists t3. apply e_iffalse.
Qed.
(** *** Example
You may use [destruct] to break open an existential
hypothesis.
*)
Lemma m_two_exists : forall t u,
(exists w, eval t w /\ eval w u) ->
eval_many t u.
Proof.
intros t u H.
destruct H as [ w He ].
destruct He as [ He1 He2 ].
apply m_two with (t2 := w).
apply He1.
apply He2.
Qed.
(** *** Example
Tip: We can combine patterns that destruct existentials with
patterns that destruct other logical connectives.
Here is the same proof with just one use of [destruct].
*)
Lemma m_two_exists' : forall t u,
(exists w, eval t w /\ eval w u) ->
eval_many t u.
Proof.
intros t u H. destruct H as [ w [ He1 He2 ] ].
apply m_two with (t2 := w).
apply He1.
apply He2.
Qed.
(** *** Example
Tip: We give patterns to the [intros] tactic to destruct
hypotheses as we introduce them.
Here is the same proof again without any uses of [destruct].
*)
Lemma m_two_exists'' : forall t u,
(exists w, eval t w /\ eval w u) ->
eval_many t u.
Proof.
intros t u [ w [ He1 He2 ] ].
apply m_two with (t2 := w).
apply He1.
apply He2.
Qed.
(** *** Exercise *)
Lemma value_can_expand : forall v,
value v ->
exists u, eval u v.
Proof.
intros v H. destruct H as [ [ | ] | [| n ] ].
exists (tm_iszero tm_zero); auto.
exists (tm_iszero (tm_succ tm_zero)). auto.
eexists (tm_pred (tm_succ tm_zero)). auto.
exists (tm_pred (tm_succ (tm_succ n))). auto.
Qed.
(*
LAB 4: (10 minutes)
Work on the following exercise.
*)
(** *** Exercise
Tip: You should find the lemma [m_iszero] useful. Use
[Check m_iszero.] if you've forgotten its statement.
*)
Lemma exists_iszero_nvalue : forall t,
(exists nv, nvalue nv /\ eval_many t nv) ->
exists bv, eval_many (tm_iszero t) bv.
Proof.
(** There exists some [nv] such that [nvalue nv]. Consider
the case where [nv] is [tm_zero]. Then choose [bv] to
be [tm_true]. By [m_trans], we can show that
[eval_many (tm_iszero t) tm_true] by showing
[eval_many (tm_iszero t) (tm_iszero tm_zero)] and
[eval_many (tm_iszero tm_zero) tm_true]. The former
follows from [m_iszero] and our assumption. The latter
follows from [m_one] and the rule [e_iszerozero]. On the
other hand, in the case where [nv] is built from
[tm_succ], we choose [bv] to be [tm_false] and the proof
follows similarly. *)
(* to finish *)
Admitted.
(**************************************************************)
(** ** Working with Negation
- [unfold not]
- [destruct] (for negation)
*)
(** *** Example
The standard library defines an uninhabited type [False] and
defines [not P] to stand for [P -> False]. Furthermore, Coq
defines the notation [~ P] to stand for [not P]. (Such
notations only affect parsing and printing -- Coq views [not
P] and [~ P] as being syntactically equal.)
The most basic way to work with negated statements is to
unfold [not] and treat [False] just as any other
proposition.
(Note how multiple definitions can be unfolded with one use
of [unfold]. Also, as noted earlier, many uses of [unfold]
are not strictly necessary. You can try deleting the uses
from the proof below to check that the proof script still
works.)
*)
Lemma normal_form_succ : forall t,
normal_form (tm_succ t) ->
normal_form t.
Proof.
intros t Hnf.
unfold normal_form. unfold not.
unfold normal_form, not in Hnf.
intros [ t' H' ]. apply Hnf.
exists (tm_succ t'). apply e_succ. apply H'.
Qed.
(** *** Exercise *)
Lemma normal_form_to_forall : forall t,
normal_form t ->
forall u, ~ eval t u.
Proof.
intros t H e He.
apply H. exists e. assumption.
Qed.
(** *** Exercise *)
Lemma normal_form_from_forall : forall t,
(forall u, ~ eval t u) ->
normal_form t.
Proof.
intros t H e. destruct e as [t']. apply (H t'). assumption.
Qed.
(** *** Example
If you happen to have [False] as a hypothesis, you may use
[destruct] on that hypothesis to solve your goal.
*)
Lemma False_hypothesis : forall v,
False ->
value v.
Proof.
intros v H. destruct H.
Qed.
(** *** Example
Recalling that [destruct] can be used on propositions with
antecedents and that negation is simply an abbreviation for
an implication, using [destruct] on a negated hypothesis has
the derived behavior of replacing our goal with the
proposition that was negated in our context.
Tip: We actually don't even need to do the unfolding below
because [destruct] would have done it for us.
*)
Lemma destruct_negation_example : forall t v,
value v ->
eval t tm_zero ->
(value v -> normal_form t) ->
eval tm_true tm_false.
Proof.
intros t v Hnv He Hnf.
unfold normal_form, not in Hnf.
(* As usual, unfolding was optional here. *)
destruct Hnf.
apply Hnv.
exists tm_zero. apply He.
Qed.
(** *** Exercise
This one may be a bit tricky. Start by using [destruct] on
one of your hypotheses.
*)
Lemma negation_exercise : forall v1 v2,
~ (value v1 \/ value v2) ->
~ (~ bvalue v1 /\ ~ bvalue v2) ->
eval tm_true tm_false.
Proof.
(* to finish *)
Admitted.
(**************************************************************)
(** ** Working with Equality
- [reflexivity]
- [subst]
- [rewrite]
- [inversion] (on equalities)
*)
(** *** Example
If you have an equality in your context, there are several
ways to substitute one side of the equality for the other in
your goal or in other hypotheses.
If one side of the equality is a variable [x], then the
tactic [subst x] will replace all occurrences of [x] in the
context and goal with the other side of the quality and will
remove [x] from your context.
Use [reflexivity] to solve a goal of the form [e = e].
*)
Lemma equality_example_1 : forall t1 t2 t3 u1 u2,
t1 = tm_iszero u1 ->
t2 = tm_succ u2 ->
t3 = tm_succ t2 ->
tm_if t1 t2 t3 =
tm_if (tm_iszero u1) (tm_succ u2) (tm_succ (tm_succ u2)).
Proof.
intros t1 t2 t3 u1 u2 Heq1 Heq2 Heq3.
subst t1. subst t2. subst t3. reflexivity.
Qed.
(** *** Example
If neither side of the equality in your context is a
variable (or if you don't want to discard the hypothesis),
you can use the [rewrite] tactic to perform a substitution.
The arrow after [rewrite] indicates the direction of the
substitution. As demonstrated, you may perform rewriting in
the goal or in a hypothesis.
*)
Lemma equality_example_2a : forall t u v,
tm_succ t = tm_succ u ->
eval (tm_succ u) v ->
eval (tm_succ t) v.
Proof.
intros t u v Heq He. rewrite -> Heq. apply He.
Qed.
Lemma equality_example_2b : forall t u v,
tm_succ t = tm_succ u ->
eval (tm_succ u) v ->
eval (tm_succ t) v.
Proof.
intros t u v Heq He. rewrite <- Heq in He. apply He.
Qed.
(** *** Example
We also note that, analogously with [destruct], we may use
[rewrite] even with a hypothesis (or lemma) that has
antecedents.
*)
Lemma equality_example_2c : forall t u v,
nvalue v ->
(nvalue v -> tm_succ t = tm_succ u) ->
eval (tm_succ u) v ->
eval (tm_succ t) v.
Proof.
intros t u v Hnv Heq He. rewrite <- Heq in He.
apply He.
apply Hnv.
Qed.
(** *** Example
If you need to derive additional equalities implied by an
equality in your context (e.g., by the principle of
constructor injectivity), you may use [inversion].
[inversion] is a powerful tactic that uses unification to
introduce more equalities into your context. (You will
observe that it also performs some substitutions in your
goal.)
*)
Lemma equality_example_3 : forall t u,
tm_succ t = tm_succ u ->
t = u.
Proof.
intros t u Heq. inversion Heq. reflexivity.
Qed.
(** *** Exercise *)
Lemma equality_exercise : forall t1 t2 t3 u1 u2 u3 u4,
tm_if t1 t2 t3 = tm_if u1 u2 u2 ->
tm_if t1 t2 t3 = tm_if u3 u3 u4 ->
t1 = u4.
Proof.
intros t1 t2 t3 u1 u2 u3 u4 H H0. inversion H. inversion H0.
rewrite <- H7. rewrite H4. rewrite <- H3. rewrite H6. rewrite <- H5.
rewrite H2. trivial.
Qed.
(** *** Example
[inversion] will also solve a goal when unification fails on
a hypothesis. (Internally, Coq can construct a proof of
[False] from contradictory equalities.)
*)
Lemma equality_example_4 :
tm_zero = tm_true ->
eval tm_true tm_false.
Proof.
intros Heq. inversion Heq.
Qed.
(*
LAB 5: (10 minutes)
Work on [equality_exercise] above and [succ_not_circular]
below.
*)
(** *** Exercise
Note: [e1 <> e2] is a notation for [~ e1 = e2], i.e., the
two are treated as syntactically equal.
Note: This is fairly trivial to prove if we have a size
function on terms and some automation. With just the tools
we have described so far, it requires just a little bit of
work.
Hint: The proof requires induction on [t]. (This is the
first example of induction on datatypes, but it is even more
straightforward than induction on propositions.) In each
case, unfold the negation, pull the equality into the
context, and use [inversion] to eliminate contradictory
equalities.
*)
Lemma succ_not_circular : forall t,
t <> tm_succ t.
Proof.
intros t E. induction t; inversion E. auto.
Qed.
(**************************************************************)
(** ** Reasoning by Inversion
- [inversion] (on propositions)
*)
(** *** Example
The [inversion] tactic also allows you to reason by
inversion on an inductively defined proposition as in paper
proofs: we try to match some proposition with the conclusion
of each inference rule and only consider the cases (possibly
none) where there is a successful unification. In those
cases, we may use the premises of the inference rule in our
reasoning.
Since [inversion] may generate many equalities between
variables, it is useful to know that using [subst] without
an argument will perform all possible substitutions for
variables. It is a little difficult to predict which
variables will be eliminated and which will be kept by this
tactic, but this is a typical sort of trade-off when using
powerful tactics.
(The use of [subst] in this proof is superfluous, but you
can observe that it simplifies the context.)
*)
Lemma value_succ_nvalue : forall t,
value (tm_succ t) ->
nvalue t.
Proof.
intros t H. unfold value in H. destruct H as [ H1 | H2 ].
(* No unification is possible -- [inversion] solves goal. *)
inversion H1.
(* Just the [n_succ] cases unifies with H2. *)
inversion H2. subst. apply H0.
Qed.
(*
LAB 6: (10 minutes)
Work on the exercise below.
*)
(** *** Exercise *)
Lemma inversion_exercise : forall t,
normal_form t ->
eval_many (tm_pred t) tm_zero ->
nvalue t.
Proof.
(** By inversion on the [eval_many] relation, then conclusion
[eval_many (tm_pred t) tm_zero] must have been derived by
the rule [m_step], which means there is some [t'] for
which [eval (tm_pred t) t'] and [eval_many t' tm_zero].
Now, by inversion on the [eval] relation, there are only
three ways that [eval (tm_pred t) t'] could have been
derived:
* By [e_predzero], with [t] and [t'] both being equal to
[tm_zero]. Our conclusion follows from [n_zero].
* By [e_predsucc], with [t] being [tm_succ t0] where we
have [nvalue t0]. In this case, our conclusion is
provable with [n_succ].
* By [e_pred], with [t] taking an evaluation step. This
contradicts our assumption that [t] is a normal form
(which can be shown by using [destruct] on that
assumption). *)
intros. unfold normal_form, not in H. inversion H0; subst.
inversion H1; auto. subst. destruct H. eexists; eauto.
Qed.
(** *** Exercise
Tip: Nested patterns will be useful here.
*)
Lemma contradictory_equalities_exercise :
(exists t, exists u, exists v,
value t /\
t = tm_succ u /\
u = tm_pred v) ->
eval tm_true tm_false.
Proof.
(* to finish *)
Admitted.
(** *** Exercise *)
Lemma eval_fact_exercise : forall t1 t2,
eval (tm_iszero (tm_pred t1)) t2 ->
eval t2 tm_false ->
exists u, t1 = tm_succ u.
Proof.
(* to finish *)
Admitted.
(** *** Exercise *)
Lemma normal_form_if : forall t1 t2 t3,
normal_form (tm_if t1 t2 t3) ->
t1 <> tm_true /\ t1 <> tm_false /\ normal_form t1.
Proof.
(* to finish *)
Admitted.
(**************************************************************)
(** ** Additional Important Tactics
- [generalize dependent]
- [assert]
- [;]
- [clear]
*)
(** *** Example
Sometimes we need to have a tactic that moves hypotheses
from our context back into our goal. Often this is
because we want to perform induction in the middle of a
proof and will not get a sufficiently general induction
hypothesis without a goal of the correct form. (To be
specific, if we need to have an induction hypothesis with a
[forall] quantifier in front, then we must make sure our
goal has a [forall] quantifier in front at the time we
invoke the [induction] tactic.) Observe how [generalize
dependent] achieves this in the proof below, moving the
variable [t] and all dependent hypotheses back into the
goal. You may want to remove the use of [generalize
dependent] to convince yourself that it is performing an
essential role here.
*)
Lemma value_is_normal_form : forall v,
value v ->
normal_form v.
Proof.
intros v [ Hb | Hn ] [ t He ].
destruct Hb.
inversion He.
inversion He.
generalize dependent t. induction Hn.
intros t He. inversion He.
intros u He. inversion He. subst. destruct (IHHn t').
apply H0.
Qed.
(** *** Exercise
Coq has many operations (called "tacticals") to combine
smaller tactics into larger ones.
If [t1] and [t2] are tactics, then [t1; t2] is a tactic that
executes [t1], and then executes [t2] on subgoals left by or
newly generated by [t1]. This can help to eliminate
repetitious use of tactics. Two idiomatic uses are
performing [subst] after [inversion] and performing [intros]
after [induction]. More opportunities to use this tactical
can usually be discovered after writing a proof. (It is
worth noting that some uses of this tactical can make proofs
less readable or more difficult to maintain. Alternatively,
some uses can make proofs more readable or easier to
maintain. It is always good to think about your priorities
when writing a proof script.)
Revise the proof for [value_is_normal_form] to include uses
of the [;] tactical.
*)
(** *** Example
Sometimes it is helpful to be able to use forward reasoning
in a proof. One form of forward reasoning can be done with
the tactic [assert]. [assert] adds a new hypothesis to the
context but asks us to first justify it.
*)
Lemma nvalue_is_normal_form : forall v,
nvalue v ->
normal_form v.
Proof.
intros v Hnv.
assert (value v) as Hv. right. apply Hnv.
apply value_is_normal_form. apply Hv.
Qed.
(** *** Example
[assert] can also be supplied with a tactic that proves the
assertion. We rewrite the above proof using this form.
*)
Lemma nvalue_is_normal_form' : forall v,
nvalue v ->
normal_form v.
Proof.
intros v Hnv.
assert (value v) as Hv by (right; apply Hnv).
apply value_is_normal_form. apply Hv.
Qed.
Hint Resolve nvalue_is_normal_form.
(** *** Example
The proof below introduces two new, simple tactics. First,
the tactic [replace e1 with e2] performs a substitution in
the goal and then requires that you prove [e2 = e1] as a new
subgoal. This often allows us to avoid more cumbersome
forms of forward reasoning. Second, the [clear] tactic
discards a hypothesis from the context. Of course, this
tactic is never needed, but it can be nice to use when there
are complicated, irrelevant hypotheses in the context.
*)
Lemma single_step_to_multi_step_determinacy :
(forall t u1 u2, eval t u1 -> eval t u2 -> u1 = u2) ->
forall t v1 v2,
eval_many t v1 -> normal_form v1 ->
eval_many t v2 -> normal_form v2 ->
v1 = v2.
Proof.
intros H t v1 v2 Hm1 Hnf1 Hm2 Hnf2. induction Hm1.
clear H. destruct Hm2.
reflexivity.
destruct Hnf1. exists t'. apply H.
destruct Hm2.
destruct Hnf2. exists t'. apply H0.
apply IHHm1; clear IHHm1.
apply Hnf1.
replace t' with t'0.
apply Hm2.
apply H with (t := t).
apply H1.
apply H0.
Qed.
(** *** Exercise
This proof is lengthy and thus somewhat challenging. All of
the techniques from this section will be useful; some will
be essential. In particular, you will need to use
[generalize dependent] at the beginning of the proof. You
will find [assert] helpful in the cases where your
assumptions are contradictory but none of them are in a
negative form. In that situation, you can assert a negative
statement that follows from your hypotheses (recall that
[normal_form] is a negative statement). Finally, you will
want to use the above lemma [nvalue_is_normal_form]. Good
luck!
*)
Theorem eval_deterministic : forall t t' t'',
eval t t' ->
eval t t'' ->
t' = t''.
Proof.
intros t t' t'' H H0. generalize dependent t'.
(*
JSTOLAREK: continue here
induction H0; let t':=.
*)
(* to finish *)
Admitted.
(** *** Exercise
Prove the following lemmas. The last is quite long, and you
may wish to wait until you know more about automation.
<<
Lemma full_eval_from_value : forall v w,
value v ->
full_eval v w ->
v = w.
Lemma eval_full_eval : forall t t' v,
eval t t' ->
full_eval t' v ->
full_eval t v.
Lemma full_eval_complete : forall t v,
value v ->
eval_many t v ->
full_eval t v.
>>
*)
(**************************************************************)
(** ** Basic Automation
- [eapply], [esplit]
- [auto], [eauto]
*)
(** *** Example
You can use [eapply e] instead of [apply e with (x := e1)].
This will generate subgoals containing unification variables
that will get unified during subsequent uses of [apply].
*)
Lemma m_if : forall t1 u1 t2 t3,
eval_many t1 u1 ->
eval_many (tm_if t1 t2 t3) (tm_if u1 t2 t3).
Proof.
intros t1 u1 t2 t3 Hm. induction Hm.
apply m_refl.
eapply m_step.
apply e_if. apply H.
apply IHHm.
Qed.
(** *** Example
You can use [esplit] to turn an existentially quantified
variable in your goal into a unification variable.
*)
Lemma exists_pred_zero :
exists u, eval (tm_pred tm_zero) u.
Proof.
esplit. apply e_predzero.
Qed.
(** *** Example
The [auto] tactic solves goals that are solvable by any
combination of
- [intros]
- [apply] (used on some local hypothesis)
- [split], [left], [right]
- [reflexivity]
If [auto] cannot solve the goal, it will leave the proof
state completely unchanged (without generating any errors).
The lemma below is a proposition that has been contrived for
the sake of demonstrating the scope of the [auto] tactic and
does not say anything of practical interest. So instead of
thinking about what it means, you should think about the
operations that [auto] had to perform to solve the goal.
Note: It is important to remember that [auto] does not
destruct hypotheses! There are more advanced forms of
automation available that do destruct hypotheses in some
specific ways.
*)
Lemma auto_example : forall t t' t'',
eval t t' ->
eval t' t'' ->
(forall u, eval t t' -> eval t' u -> eval_many t u) ->
eval t' t \/ t = t /\ eval_many t t''.
Proof.
auto.
Qed.
(** *** Example
The [eauto] tactic solves goals that are solvable by some
combination of
- [intros]
- [eapply] (used on some local hypothesis)
- [split], [left], [right]
- [esplit]
- [reflexivity]
This lemma has two significantly differences from the
previous one, both of which render [auto] useless.
*)
Lemma eauto_example : forall t t' t'',
eval t t' ->
eval t' t'' ->
(forall u, eval t u -> eval u t'' -> eval_many t t'') ->
eval t' t \/ (exists u, t = u) /\ eval_many t t''.
Proof.
eauto.
Qed.
(** *** Example
You can enhance [auto] (or [eauto]) by appending [using x_1,
..., x_n], where each [x_i] is the name of some constructor
or lemma. Then [auto] will attempt to apply those
constructors or lemmas in addition to the assumptions in
the local context.
*)
Lemma eauto_using_example : forall t t' t'',
eval t t' ->
eval t' t'' ->
eval t' t \/ t = t /\ eval_many t t''.
Proof.
eauto using m_step, m_one.
Qed.
(*
LAB 7: (5 minutes)
Work on the following exercise.
*)
(** *** Exercise
Go back and rewrite your proofs for [m_one], [m_two], and
[m_iftrue_step]. You should be able to make them very
succinct given what you know now.
*)
(** *** Exercise
See how short you can make these proofs.
Note: This is an exercise. We are not making the claim that
shorter proofs are necessarily better!
Hint: Remember that we can connect tactics in sequence with
[;]. However, as you can imagine, figuring out the best
thing to write after a [;] usually involves some trial and
error.
*)
Lemma pred_not_circular : forall t,
t <> tm_pred t.
Proof.
(* to finish *)
Admitted.
Lemma m_succ : forall t u,
eval_many t u ->
eval_many (tm_succ t) (tm_succ u).
Proof.
(* to finish *)
Admitted.
Lemma m_pred : forall t u,
eval_many t u ->
eval_many (tm_pred t) (tm_pred u).
Proof.
(* to finish *)
Admitted.
(** *** Exercise
Go back and rewrite your proofs for [m_trans] and
[two_values]. Pulling together several tricks you've
learned, you should be able to prove [two_values] in one
(short) line.
*)
(** *** Note
Sometimes there are lemmas or constructors that are so
frequently needed by [auto] that we don't want to have to
add them to our [using] clause each time. Coq allows us to
request that certain propositions that always be
considered by [auto] and [eauto].
The following command adds four lemmas to the default search
procedure of [auto].
*)
Hint Resolve m_if m_succ m_pred m_iszero.
(** Constructors of inductively defined propositions are some of
the most frequently needed by [auto]. Instead of writing
<<
Hint Resolve b_true b_false.
>>
we may simply write
<<
Hint Constructors bvalue.
>>
Let's add all our constructors to [auto].
*)
Hint Constructors bvalue nvalue eval eval_many.
(** By default [auto] will never try to unfold definitions to
see if a lemma or constructor can be applied. With the
[Hint Unfold] command, we can instruct [auto] to try unfold
definitions in the goal as it is working.
*)
Hint Unfold value normal_form.
(** There are a few more variants on the [Hint] command that can
be used to further customize [auto]. You can learn about
them in the Coq reference manual.
*)
(**************************************************************)
(** ** Functions and Conversion
- [Fixpoint/struct]
- [match ... end]
- [if ... then ... else ...]
- [simpl]
- [remember]
In this section we start to use Coq as a programming
language and learn how to reason about programs defined
within Coq.
*)
(** *** Example
Coq defines many datatypes in its standard libraries. Have
a quick look now through the library [Datatypes] to see some
of the basic ones, in particular [bool] and [nat]. (Note
that constructors of the datatype [nat] are the letter [O]
and the letter [S]. However, Coq will parse and print
[nat]s using a standard decimal representation.)
We define two more datatypes here that will be useful later.
*)
Inductive bool_option : Set :=
| some_bool : bool -> bool_option
| no_bool : bool_option.
Inductive nat_option : Set :=
| some_nat : nat -> nat_option
| no_nat : nat_option.
(** *** Example
We can define simple (non-recursive) functions from one
datatype to another using the [Definition] keyword. The
[match] construct allows us to do case analysis on a
datatype. The [match] expression has a first-match
semantics and allows nested patterns; however, Coq's type
checker demands that pattern-matching be exhaustive.
We define functions below for converting between Coq [bool]s
and boolean values in our object language.
*)
Definition tm_to_bool (t : tm) : bool_option :=
match t with
| tm_true => some_bool true
| tm_false => some_bool false
| _ => no_bool
end.
Definition bool_to_tm (b : bool) : tm :=
match b with
| true => tm_true
| false => tm_false
end.
(** *** Example
Coq also has an [if/then/else] expression. It can be used,
not just with the type [bool] but, in fact, with any
datatype having exactly two constructors (the first
constructor corresponding to the [then] branch and the
second to the [else] branch). Thus, we can define a
function [is_bool] as below.
*)
Definition is_bool (t : tm) : bool :=
if tm_to_bool t then true else false.
(** *** Example
To define a recursive function, use [Fixpoint] instead of
[Definition].
The type system will only allow us to write functions that
terminate. The annotation [{struct t}] here informs the
type-checker that termination is guaranteed because the
function is being defined by structural recursion on [t].
*)
Fixpoint tm_to_nat (t : tm) {struct t} : nat_option :=
match t with
| tm_zero => some_nat O
| tm_succ t1 =>
match tm_to_nat t1 with
| some_nat n => some_nat (S n)
| no_nat => no_nat
end
| _ => no_nat
end.
Fixpoint nat_to_tm (n : nat) {struct n} : tm :=
match n with
| O => tm_zero
| S m => tm_succ (nat_to_tm m)
end.
(** *** Exercise
Write a function [interp : tm -> tm] that returns the
normal form of its argument according to the small-step
semantics given by [eval].
Hint: You will want to use [tm_to_nat] (or another auxiliary
function) to prevent stuck terms from stepping in the cases
[e_predsucc] and [e_iszerosucc].
*)
(** *** Example
The tactic [simpl] (recursively) reduces the application of
a function defined by pattern-matching to an argument with a
constructor at its head. You can supply [simpl] with a
particular expression if you want to prevent it from
simplifying elsewhere.
*)
Lemma bool_tm_bool : forall b,
tm_to_bool (bool_to_tm b) = some_bool b.
Proof.
intros b. destruct b.
simpl (bool_to_tm true). simpl. reflexivity.
(* It turns out that [simpl] is unnecessary above, since
[reflexivity] can automatically check that two terms are
convertible. *)
reflexivity.
Qed.
(** *** Example
We can also apply the tactic [simpl] in our hypotheses.
*)
Lemma tm_bool_tm :forall t b,
tm_to_bool t = some_bool b ->
bool_to_tm b = t.
Proof.
intros t b Heq. destruct t.
simpl in Heq. inversion Heq.
simpl. reflexivity.
(* As with [reflexivity], [inversion] can automatically
perform reduction on terms as necessary, so the above use
of [simpl] was optional. *)
inversion Heq. reflexivity.
simpl in Heq. inversion Heq.
(* Again, the above use of [simpl] was optional. *)
inversion Heq.
inversion Heq.
inversion Heq.
inversion Heq.
Qed.
(** *** Exercise *)
Lemma tm_to_bool_dom_includes_bvalue : forall bv,
bvalue bv -> exists b, tm_to_bool bv = some_bool b.
Proof.
(* to finish *)
Admitted.
(** *** Exercise *)
Lemma tm_to_bool_dom_only_bvalue : forall bv b,
tm_to_bool bv = some_bool b -> bvalue bv.
Proof.
(* to finish *)
Admitted.
(** *** Example
Not all uses of [simpl] are optional. Sometimes they are
necessary so that we can use the [rewrite] tactic. Observe,
also, how using [rewrite] can automatically trigger a
reduction if it creates a redex.
*)
Lemma nat_tm_nat : forall n,
tm_to_nat (nat_to_tm n) = some_nat n.
Proof.
intros n. induction n.
reflexivity.
simpl. rewrite -> IHn. reflexivity.
Qed.
(** *** Example
Here's an example where it is necessary to use [simpl] on a
hypothesis. To trigger a reduction of a [match] expression
in a hypothesis, we use the [destruct] tactic on the
expression being matched.
*)
Lemma tm_nat_tm : forall t n,
tm_to_nat t = some_nat n ->
nat_to_tm n = t.
Proof.
intros t. induction t; intros n Heq.
inversion Heq.
inversion Heq.
inversion Heq.
inversion Heq. reflexivity.
simpl in Heq. destruct (tm_to_nat t).
inversion Heq. simpl. rewrite -> IHt.
(* Note how we may use [rewrite] even on an equation
that is preceded by some other hypotheses. *)
reflexivity.
reflexivity.
inversion Heq.
inversion Heq.
inversion Heq.
Qed.
(** *** Exercise *)
Lemma tm_to_nat_dom_includes_nvalue : forall v,
nvalue v -> exists n, tm_to_nat v = some_nat n.
Proof.
(* to finish *)
Admitted.
(** *** Exercise *)
Lemma tm_to_nat_dom_only_nvalue : forall v n,
tm_to_nat v = some_nat n -> nvalue v.
Proof.
(* to finish *)
Admitted.
(** *** Example
Using the tactic [destruct] (or [induction]) on a complex
expression (i.e., one that is not simply a variable) may not
leave you with enough information for you to finish the
proof. The tactic [remember] can help in these cases. Its
usage is demonstrated below. If you are curious, try to
finish the proof without [remember] to see what goes wrong.
*)
Lemma remember_example : forall v,
eval_many
(tm_pred (tm_succ v))
(match tm_to_nat v with
| some_nat _ => v
| no_nat => tm_pred (tm_succ v)
end).
Proof.
intros v. remember (tm_to_nat v) as x. destruct x.
apply m_one. apply e_predsucc.
eapply tm_to_nat_dom_only_nvalue.
rewrite <- Heqx. reflexivity.
apply m_refl.
Qed.
(** *** Exercise
Prove the following lemmas involving the function [interp]
from a previous exercise:
<<
Lemma interp_reduces : forall t,
eval_many t (interp t).
Lemma interp_fully_reduces : forall t,
normal_form (interp t).
>>
*)
(**************************************************************)
(** * Solutions to Exercises *)
(**************************************************************)
Inductive eval_rtc : tm -> tm -> Prop :=
| r_eval : forall t t',
eval t t' ->
eval_rtc t t'
| r_refl : forall t,
eval_rtc t t
| r_trans : forall t u v,
eval_rtc t u ->
eval_rtc u v ->
eval_rtc t v.
Inductive full_eval : tm -> tm -> Prop :=
| f_value : forall v,
value v ->
full_eval v v
| f_iftrue : forall t1 t2 t3 v,
full_eval t1 tm_true ->
full_eval t2 v ->
full_eval (tm_if t1 t2 t3) v
| f_iffalse : forall t1 t2 t3 v,
full_eval t1 tm_false ->
full_eval t3 v ->
full_eval (tm_if t1 t2 t3) v
| f_succ : forall t v,
nvalue v ->
full_eval t v ->
full_eval (tm_succ t) (tm_succ v)
| f_predzero : forall t,
full_eval t tm_zero ->
full_eval (tm_pred t) tm_zero
| f_predsucc : forall t v,
nvalue v ->
full_eval t (tm_succ v) ->
full_eval (tm_pred t) v
| f_iszerozero : forall t,
full_eval t tm_zero ->
full_eval (tm_iszero t) tm_true
| f_iszerosucc : forall t v,
nvalue v ->
full_eval t (tm_succ v) ->
full_eval (tm_iszero t) tm_false.
Lemma m_one_sol : forall t t',
eval t t' ->
eval_many t t'.
Proof.
intros t t' He. apply m_step with (t' := t').
apply He.
apply m_refl.
Qed.
Lemma m_two_sol : forall t t' t'',
eval t t' ->
eval t' t'' ->
eval_many t t''.
Proof.
intros t t' t'' He1 He2. apply m_step with (t' := t').
apply He1.
apply m_one. apply He2.
Qed.
Lemma m_iftrue_step_sol : forall t t1 t2 u,
eval t tm_true ->
eval_many t1 u ->
eval_many (tm_if t t1 t2) u.
Proof.
intros t t1 t2 u He Hm.
apply m_step with (t' := tm_if tm_true t1 t2).
apply e_if. apply He.
apply m_step with (t' := t1).
apply e_iftrue.
apply Hm.
Qed.
Lemma m_if_iszero_conj_sol : forall v t2 t2' t3 t3',
nvalue v /\ eval t2 t2' /\ eval t3 t3' ->
eval_many (tm_if (tm_iszero tm_zero) t2 t3) t2' /\
eval_many (tm_if (tm_iszero (tm_succ v)) t2 t3) t3'.
Proof.
intros v t2 t2' t3 t3' H.
destruct H as [ Hn [ He1 He2 ] ]. split.
apply m_three with
(t' := tm_if tm_true t2 t3) (t'' := t2).
apply e_if. apply e_iszerozero.
apply e_iftrue.
apply He1.
apply m_three with
(t' := tm_if tm_false t2 t3) (t'' := t3).
apply e_if. apply e_iszerosucc. apply Hn.
apply e_iffalse.
apply He2.
Qed.
Lemma two_values_sol : forall t u,
value t /\ value u ->
bvalue t \/
bvalue u \/
(nvalue t /\ nvalue u).
Proof.
unfold value. intros t u H.
destruct H as [ [ Hb1 | Hn1 ] H2 ].
left. apply Hb1.
destruct H2 as [ Hb2 | Hn2 ].
right. left. apply Hb2.
right. right. split.
apply Hn1.
apply Hn2.
Qed.
Lemma m_trans_sol : forall t u v,
eval_many t u ->
eval_many u v ->
eval_many t v.
Proof.
intros t u v Hm1 Hm2. induction Hm1.
apply Hm2.
apply m_step with (t' := t').
apply H.
apply IHHm1. apply Hm2.
Qed.
Lemma eval_rtc_many_sol : forall t u,
eval_rtc t u ->
eval_many t u.
Proof.
intros t u Hr. induction Hr.
apply m_one. apply H.
apply m_refl.
apply m_trans with (t' := u).
apply IHHr1.
apply IHHr2.
Qed.
Lemma eval_many_rtc_sol : forall t u,
eval_many t u ->
eval_rtc t u.
Proof.
intros t u Hm. induction Hm.
apply r_refl.
apply r_trans with (u := t').
apply r_eval. apply H.
apply IHHm.
Qed.
Lemma full_eval_to_value_sol : forall t v,
full_eval t v ->
value v.
Proof.
intros t v Hf. induction Hf.
apply H.
apply IHHf2.
apply IHHf2.
right. apply n_succ. apply H.
right. apply n_zero.
right. apply H.
left. apply b_true.
left. apply b_false.
Qed.
Lemma value_can_expand_sol : forall v,
value v ->
exists u, eval u v.
Proof.
intros v Hv. exists (tm_if tm_true v v). apply e_iftrue.
Qed.
Lemma exists_iszero_nvalue_sol : forall t,
(exists nv, nvalue nv /\ eval_many t nv) ->
exists bv, eval_many (tm_iszero t) bv.
Proof.
intros t [ nv [ Hnv Hm ]]. destruct Hnv.
exists tm_true.
apply m_trans with (t' := tm_iszero tm_zero).
apply m_iszero. apply Hm.
apply m_one. apply e_iszerozero.
exists tm_false.
apply m_trans with (t' := tm_iszero (tm_succ t0)).
apply m_iszero. apply Hm.
apply m_one. apply e_iszerosucc. apply Hnv.
Qed.
Lemma normal_form_to_forall_sol : forall t,
normal_form t ->
forall u, ~ eval t u.
Proof.
unfold normal_form, not. intros t H u He.
apply H. exists u. apply He.
Qed.
Lemma normal_form_from_forall_sol : forall t,
(forall u, ~ eval t u) ->
normal_form t.
Proof.
unfold normal_form, not. intros t H [ t' Het' ].
apply H with (u := t'). apply Het'.
Qed.
Lemma negation_exercise_sol : forall v1 v2,
~ (value v1 \/ value v2) ->
~ (~ bvalue v1 /\ ~ bvalue v2) ->
eval tm_true tm_false.
Proof.
intros v1 v2 H1 H2. destruct H2.
split.
intros Hb. destruct H1. left. left. apply Hb.
intros Hb. destruct H1. right. left. apply Hb.
Qed.
Lemma equality_exercise_sol : forall t1 t2 t3 u1 u2 u3 u4,
tm_if t1 t2 t3 = tm_if u1 u2 u2 ->
tm_if t1 t2 t3 = tm_if u3 u3 u4 ->
t1 = u4.
Proof.
intros t1 t2 t3 u1 u2 u3 u4 Heq1 Heq2.
inversion Heq1. subst t1. subst t2. subst t3.
inversion Heq2. reflexivity.
Qed.
Lemma succ_not_circular_sol : forall t,
t <> tm_succ t.
Proof.
intros t. induction t.
intros Heq. inversion Heq.
intros Heq. inversion Heq.
intros Heq. inversion Heq.
intros Heq. inversion Heq.
intros Heq. inversion Heq. destruct IHt. apply H0.
intros Heq. inversion Heq.
intros Heq. inversion Heq.
Qed.
Lemma inversion_exercise_sol : forall t,
normal_form t ->
eval_many (tm_pred t) tm_zero ->
nvalue t.
Proof.
intros t Hnf Hm. inversion Hm. subst. inversion H.
apply n_zero.
apply n_succ. apply H2.
destruct Hnf. exists t'0. apply H2.
Qed.
Lemma contradictory_equalities_exercise_sol :
(exists t, exists u, exists v,
value t /\
t = tm_succ u /\
u = tm_pred v) ->
eval tm_true tm_false.
Proof.
intros [ t [ u [ v [ [ Hb | Hn ] [ eq1 eq2 ] ] ] ] ].
destruct Hb.
inversion eq1.
inversion eq1.
destruct Hn.
inversion eq1.
inversion eq1. subst t. subst u. inversion Hn.
Qed.
Lemma eval_fact_exercise_sol : forall t1 t2,
eval (tm_iszero (tm_pred t1)) t2 ->
eval t2 tm_false ->
exists u, t1 = tm_succ u.
Proof.
intros t1 t2 He1 He2. inversion He1. subst t2.
inversion He2. subst t'.
inversion H0. exists (tm_succ t0). reflexivity.
Qed.
Lemma normal_form_if_sol : forall t1 t2 t3,
normal_form (tm_if t1 t2 t3) ->
t1 <> tm_true /\ t1 <> tm_false /\ normal_form t1.
Proof.
intros t1 t2 t3 Hnf. destruct t1.
destruct Hnf. exists t2. apply e_iftrue.
destruct Hnf. exists t3. apply e_iffalse.
split.
intros Heq. inversion Heq.
split.
intros Heq. inversion Heq.
intros [t' He]. destruct Hnf. exists (tm_if t' t2 t3).
apply e_if. apply He.
split.
intros Heq. inversion Heq.
split.
intros Heq. inversion Heq.
intros [t' He]. inversion He.
split.
intros Heq. inversion Heq.
split.
intros Heq. inversion Heq.
intros [t' He]. destruct Hnf. exists (tm_if t' t2 t3).
apply e_if. apply He.
split.
intros Heq. inversion Heq.
split.
intros Heq. inversion Heq.
intros [t' He]. destruct Hnf. exists (tm_if t' t2 t3).
apply e_if. apply He.
split.
intros Heq. inversion Heq.
split.
intros Heq. inversion Heq.
intros [t' He]. destruct Hnf. exists (tm_if t' t2 t3).
apply e_if. apply He.
Qed.
Lemma full_eval_from_value_sol : forall v w,
value v ->
full_eval v w ->
v = w.
Proof.
intros v w Hv Hf. induction Hf.
reflexivity.
destruct Hv as [ Hb | Hn ].
inversion Hb.
inversion Hn.
destruct Hv as [ Hb | Hn ].
inversion Hb.
inversion Hn.
rewrite -> IHHf.
reflexivity.
right. apply value_succ_nvalue. apply Hv.
destruct Hv as [ Hb | Hn ].
inversion Hb.
inversion Hn.
destruct Hv as [ Hb | Hn ].
inversion Hb.
inversion Hn.
destruct Hv as [ Hb | Hn ].
inversion Hb.
inversion Hn.
destruct Hv as [ Hb | Hn ].
inversion Hb.
inversion Hn.
Qed.
Lemma value_is_normal_form_sol : forall v,
value v ->
normal_form v.
Proof.
intros v [ Hb | Hn ] [ t He ].
destruct Hb; inversion He.
generalize dependent t.
induction Hn; intros u He; inversion He; subst.
destruct (IHHn t'). apply H0.
Qed.
Theorem eval_deterministic_sol : forall t t' t'',
eval t t' ->
eval t t'' ->
t' = t''.
Proof.
intros t t' t'' He1. generalize dependent t''.
induction He1; intros t'' He2; inversion He2; subst.
reflexivity.
inversion H3.
reflexivity.
inversion H3.
inversion He1.
inversion He1.
rewrite -> (IHHe1 t1'0).
reflexivity.
apply H3.
rewrite -> (IHHe1 t'0).
reflexivity.
apply H0.
reflexivity.
inversion H0.
reflexivity.
assert (normal_form (tm_succ t)) as Hnf.
apply nvalue_is_normal_form. apply n_succ. apply H.
destruct Hnf. exists t'. apply H1.
inversion He1.
assert (normal_form (tm_succ t'')) as Hnf.
apply nvalue_is_normal_form. apply n_succ. apply H0.
destruct Hnf. exists t'. apply He1.
rewrite -> (IHHe1 t'0).
reflexivity.
apply H0.
reflexivity.
inversion H0.
reflexivity.
assert (normal_form (tm_succ t)) as Hnf.
apply nvalue_is_normal_form. apply n_succ. apply H.
destruct Hnf. exists t'. apply H1.
inversion He1.
assert (normal_form (tm_succ t0)) as Hnf.
apply nvalue_is_normal_form. apply n_succ. apply H0.
destruct Hnf. exists t'. apply He1.
rewrite -> (IHHe1 t'0).
reflexivity.
apply H0.
Qed.
Lemma eval_full_eval_sol : forall t t' v,
eval t t' ->
full_eval t' v ->
full_eval t v.
Proof.
intros t t' v He. generalize dependent v. induction He.
intros v Hf. apply f_iftrue.
apply f_value. left. apply b_true.
apply Hf.
intros v Hf. apply f_iffalse.
apply f_value. left. apply b_false.
apply Hf.
intros v Hf. inversion Hf.
subst. inversion H.
inversion H0.
inversion H0.
subst. apply f_iftrue.
apply IHHe. apply H3.
apply H4.
subst. apply f_iffalse.
apply IHHe. apply H3.
apply H4.
intros v Hf. inversion Hf.
subst. apply f_succ.
apply value_succ_nvalue. apply H.
apply IHHe. apply f_value. right.
apply value_succ_nvalue. apply H.
subst. apply f_succ.
apply H0.
apply IHHe. apply H1.
intros v Hf. inversion Hf. apply f_predzero.
apply f_value. right. apply n_zero.
intros v Hf. assert (t = v).
apply full_eval_from_value_sol.
right. apply H.
apply Hf.
subst v. apply f_predsucc.
apply H.
apply f_succ.
apply H.
apply Hf.
intros v Hf. inversion Hf.
subst. destruct H as [ Hb | Hn ].
inversion Hb.
inversion Hn.
subst. apply f_predzero. apply IHHe. apply H0.
subst. apply f_predsucc.
apply H0.
apply IHHe. apply H1.
intros v Hf. inversion Hf. apply f_iszerozero.
apply f_value. right. apply n_zero.
intros v Hf. inversion Hf.
apply f_iszerosucc with (v := t).
apply H.
apply f_value. right. apply n_succ. apply H.
intros v Hf. inversion Hf.
subst. destruct H as [ Hb | Hn ].
inversion Hb.
inversion Hn.
subst. apply f_iszerozero. apply IHHe. apply H0.
subst. apply f_iszerosucc with (v := v0).
apply H0.
apply IHHe. apply H1.
Qed.
Lemma full_eval_complete_sol : forall t v,
value v ->
eval_many t v ->
full_eval t v.
Proof.
intros t v Hv Hm. induction Hm.
apply f_value. apply Hv.
apply eval_full_eval_sol with (t' := t').
apply H.
apply IHHm. apply Hv.
Qed.
Lemma pred_not_circular_sol : forall t,
t <> tm_pred t.
Proof.
intros t H. induction t; inversion H; auto.
Qed.
Lemma m_succ_sol : forall t u,
eval_many t u ->
eval_many (tm_succ t) (tm_succ u).
Proof.
intros t u Hm.
induction Hm; eauto using m_refl, m_step, e_succ.
Qed.
Lemma m_pred_sol : forall t u,
eval_many t u ->
eval_many (tm_pred t) (tm_pred u).
Proof.
intros t u Hm.
induction Hm; eauto using m_refl, m_step, e_pred.
Qed.
Fixpoint interp (t : tm) {struct t} : tm :=
match t with
| tm_true => tm_true
| tm_false => tm_false
| tm_if t1 t2 t3 =>
match interp t1 with
| tm_true => interp t2
| tm_false => interp t3
| t4 => tm_if t4 t2 t3
end
| tm_zero => tm_zero
| tm_succ t1 => tm_succ (interp t1)
| tm_pred t1 =>
match interp t1 with
| tm_zero => tm_zero
| tm_succ t2 =>
match tm_to_nat t2 with
| some_nat _ => t2
| no_nat => tm_pred (tm_succ t2)
end
| t2 => tm_pred t2
end
| tm_iszero t1 =>
match interp t1 with
| tm_zero => tm_true
| tm_succ t2 =>
match tm_to_nat t2 with
| some_nat _ => tm_false
| no_nat => tm_iszero (tm_succ t2)
end
| t2 => tm_iszero t2
end
end.
Lemma tm_to_bool_dom_includes_bvalue_sol : forall bv,
bvalue bv -> exists b, tm_to_bool bv = some_bool b.
Proof.
intros bv H. destruct H.
exists true. reflexivity.
exists false. reflexivity.
Qed.
Lemma tm_to_bool_dom_only_bvalue_sol : forall bv b,
tm_to_bool bv = some_bool b -> bvalue bv.
Proof.
intros bv b Heq. destruct bv.
apply b_true.
apply b_false.
inversion Heq.
inversion Heq.
inversion Heq.
inversion Heq.
inversion Heq.
Qed.
Lemma tm_to_nat_dom_includes_nvalue_sol : forall v,
nvalue v -> exists n, tm_to_nat v = some_nat n.
Proof.
intros v Hnv. induction Hnv.
exists O. reflexivity.
destruct IHHnv as [ n Heq ]. exists (S n).
simpl. rewrite -> Heq. reflexivity.
Qed.
Lemma tm_to_nat_dom_only_nvalue_sol : forall v n,
tm_to_nat v = some_nat n -> nvalue v.
Proof.
intros v. induction v; intros n Heq.
inversion Heq.
inversion Heq.
inversion Heq.
apply n_zero.
apply n_succ.
simpl in Heq. destruct (tm_to_nat v).
inversion Heq. eapply IHv. reflexivity.
inversion Heq.
inversion Heq.
inversion Heq.
Qed.
Lemma interp_reduces_sol : forall t,
eval_many t (interp t).
Proof.
intros t. induction t.
apply m_refl.
apply m_refl.
simpl. destruct (interp t1).
eapply m_trans.
apply m_if. apply IHt1.
eapply m_trans.
eapply m_one. apply e_iftrue.
apply IHt2.
eapply m_trans.
apply m_if. apply IHt1.
eapply m_trans.
eapply m_one. apply e_iffalse.
apply IHt3.
apply m_if. apply IHt1.
apply m_if. apply IHt1.
apply m_if. apply IHt1.
apply m_if. apply IHt1.
apply m_if. apply IHt1.
apply m_refl.
simpl. apply m_succ. apply IHt.
simpl. destruct (interp t).
apply m_pred. apply IHt.
apply m_pred. apply IHt.
apply m_pred. apply IHt.
eapply m_trans.
apply m_pred. apply IHt.
apply m_one. apply e_predzero.
remember (tm_to_nat t0) as x. destruct x.
eapply m_trans.
apply m_pred. apply IHt.
apply m_one. apply e_predsucc.
eapply tm_to_nat_dom_only_nvalue.
rewrite <- Heqx. reflexivity.
apply m_pred. apply IHt.
apply m_pred. apply IHt.
apply m_pred. apply IHt.
simpl. destruct (interp t).
apply m_iszero. apply IHt.
apply m_iszero. apply IHt.
apply m_iszero. apply IHt.
eapply m_trans.
apply m_iszero. apply IHt.
apply m_one. apply e_iszerozero.
remember (tm_to_nat t0) as x. destruct x.
eapply m_trans.
apply m_iszero. apply IHt.
apply m_one. apply e_iszerosucc.
eapply tm_to_nat_dom_only_nvalue.
rewrite <- Heqx. reflexivity.
apply m_iszero. apply IHt.
apply m_iszero. apply IHt.
apply m_iszero. apply IHt.
Qed.
Lemma interp_fully_reduces_sol : forall t,
normal_form (interp t).
Proof.
induction t; intros [t' H].
inversion H.
inversion H.
simpl in H. destruct (interp t1).
destruct IHt2. eauto.
destruct IHt3. eauto.
destruct IHt1. inversion H. eauto.
destruct IHt1. inversion H. eauto.
destruct IHt1. inversion H. eauto.
destruct IHt1. inversion H. eauto.
destruct IHt1. inversion H. eauto.
inversion H.
destruct IHt. inversion H. eauto.
simpl in H. destruct (interp t).
inversion H. inversion H1.
inversion H. inversion H1.
inversion H. destruct IHt. eauto.
inversion H.
remember (tm_to_nat t0) as x. destruct x.
destruct IHt. exists (tm_succ t').
apply e_succ. apply H.
inversion H; subst.
destruct (tm_to_nat_dom_includes_nvalue t')
as [n Heq].
apply H1.
rewrite <- Heqx in Heq. inversion Heq.
destruct IHt. eauto.
inversion H. destruct IHt. eauto.
inversion H. destruct IHt. eauto.
simpl in H. destruct (interp t).
inversion H. inversion H1.
inversion H. inversion H1.
inversion H. destruct IHt. eauto.
inversion H.
remember (tm_to_nat t0) as x. destruct x.
inversion H.
inversion H; subst.
destruct (tm_to_nat_dom_includes_nvalue t0)
as [n Heq].
apply H1.
rewrite <- Heqx in Heq. inversion Heq.
inversion H. destruct IHt. eauto.
inversion H. destruct IHt. eauto.
inversion H. destruct IHt. eauto.
Qed.
(* vi:set tw=64:
Local Variables:
fill-column: 64
End:
*)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SDFSTP_BEHAVIORAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLCLKP_PP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_PP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module axi_hdmi_tx (
// hdmi interface
hdmi_clk,
hdmi_out_clk,
// 16-bit interface
hdmi_16_hsync,
hdmi_16_vsync,
hdmi_16_data_e,
hdmi_16_data,
hdmi_16_es_data,
// 24-bit interface
hdmi_24_hsync,
hdmi_24_vsync,
hdmi_24_data_e,
hdmi_24_data,
// 36-bit interface
hdmi_36_hsync,
hdmi_36_vsync,
hdmi_36_data_e,
hdmi_36_data,
// vdma interface
vdma_clk,
vdma_fs,
vdma_fs_ret,
vdma_valid,
vdma_data,
vdma_ready,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter ID = 0;
parameter CR_CB_N = 0;
parameter DEVICE_TYPE = 0;
parameter EMBEDDED_SYNC = 0;
/* 0 = Launch on rising edge, 1 = Launch on falling edge */
parameter OUT_CLK_POLARITY = 0;
localparam XILINX_7SERIES = 0;
localparam XILINX_ULTRASCALE = 1;
localparam ALTERA_5SERIES = 16;
// hdmi interface
input hdmi_clk;
output hdmi_out_clk;
// 16-bit interface
output hdmi_16_hsync;
output hdmi_16_vsync;
output hdmi_16_data_e;
output [15:0] hdmi_16_data;
output [15:0] hdmi_16_es_data;
// 24-bit interface
output hdmi_24_hsync;
output hdmi_24_vsync;
output hdmi_24_data_e;
output [23:0] hdmi_24_data;
// 36-bit interface
output hdmi_36_hsync;
output hdmi_36_vsync;
output hdmi_36_data_e;
output [35:0] hdmi_36_data;
// vdma interface
input vdma_clk;
output vdma_fs;
input vdma_fs_ret;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// reset and clocks
wire up_rstn;
wire up_clk;
wire hdmi_rst;
wire vdma_rst;
// internal signals
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
wire hdmi_full_range_s;
wire hdmi_csc_bypass_s;
wire hdmi_ss_bypass_s;
wire [ 1:0] hdmi_srcsel_s;
wire [23:0] hdmi_const_rgb_s;
wire [15:0] hdmi_hl_active_s;
wire [15:0] hdmi_hl_width_s;
wire [15:0] hdmi_hs_width_s;
wire [15:0] hdmi_he_max_s;
wire [15:0] hdmi_he_min_s;
wire [15:0] hdmi_vf_active_s;
wire [15:0] hdmi_vf_width_s;
wire [15:0] hdmi_vs_width_s;
wire [15:0] hdmi_ve_max_s;
wire [15:0] hdmi_ve_min_s;
wire hdmi_fs_toggle_s;
wire [ 8:0] hdmi_raddr_g_s;
wire hdmi_tpm_oos_s;
wire hdmi_status_s;
wire vdma_wr_s;
wire [ 8:0] vdma_waddr_s;
wire [47:0] vdma_wdata_s;
wire vdma_fs_ret_toggle_s;
wire [ 8:0] vdma_fs_waddr_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire vdma_tpm_oos_s;
// signal name changes
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// axi interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// processor interface
up_hdmi_tx i_up (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s),
.hdmi_status (hdmi_status_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_clk_ratio (32'd1),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// vdma interface
axi_hdmi_tx_vdma i_vdma (
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_fs (vdma_fs),
.vdma_fs_ret (vdma_fs_ret),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s));
// hdmi interface
axi_hdmi_tx_core #(
.CR_CB_N(CR_CB_N),
.EMBEDDED_SYNC(EMBEDDED_SYNC))
i_tx_core (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_16_hsync (hdmi_16_hsync),
.hdmi_16_vsync (hdmi_16_vsync),
.hdmi_16_data_e (hdmi_16_data_e),
.hdmi_16_data (hdmi_16_data),
.hdmi_16_es_data (hdmi_16_es_data),
.hdmi_24_hsync (hdmi_24_hsync),
.hdmi_24_vsync (hdmi_24_vsync),
.hdmi_24_data_e (hdmi_24_data_e),
.hdmi_24_data (hdmi_24_data),
.hdmi_36_hsync (hdmi_36_hsync),
.hdmi_36_vsync (hdmi_36_vsync),
.hdmi_36_data_e (hdmi_36_data_e),
.hdmi_36_data (hdmi_36_data),
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_status (hdmi_status_s),
.vdma_clk (vdma_clk),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s));
// hdmi output clock
generate
if (DEVICE_TYPE == XILINX_ULTRASCALE) begin
ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
.SR (1'b0),
.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
.C (hdmi_clk),
.Q (hdmi_out_clk));
end
if (DEVICE_TYPE == ALTERA_5SERIES) begin
altddio_out #(.WIDTH(1)) i_clk_oddr (
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0),
.oe (1'b1),
.outclocken (1'b1),
.datain_h (~OUT_CLK_POLARITY),
.datain_l (OUT_CLK_POLARITY),
.outclock (hdmi_clk),
.oe_out (),
.dataout (hdmi_out_clk));
end
if (DEVICE_TYPE == XILINX_7SERIES) begin
ODDR #(.INIT(1'b0)) i_clk_oddr (
.R (1'b0),
.S (1'b0),
.CE (1'b1),
.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
.C (hdmi_clk),
.Q (hdmi_out_clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
module t_block_memory;
// Inputs
reg clock;
reg reset;
reg enable;
reg [4:0] row1;
reg [4:0] row2;
reg [4:0] col1;
reg [4:0] col2;
reg [1:0] func;
reg [1:0] stage;
// Outputs
wire [2:0] block1;
wire [2:0] block2;
wire busy;
// Instantiate the Unit Under Test (UUT)
block_memory uut (
.clock(clock),
.reset(reset),
.enable(enable),
.row1(row1),
.row2(row2),
.col1(col1),
.col2(col2),
.func(func),
.stage(stage),
.block1(block1),
.block2(block2),
.busy(busy)
);
always #1 clock = ~clock;
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
enable = 0;
row1 = 0;
row2 = 0;
col1 = 0;
col2 = 0;
func = 0;
stage = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1;
#10;
reset = 0;
#10;
// Load stage testing.
enable = 1;
func = 1;
#10;
enable = 0;
func = 0;
#200;
// Clear testing.
col1 = 8;
row1 = 8;
enable = 1;
func = 0;
#10;
// Drop testing.
enable = 1;
func = 2;
#10
enable = 0;
#100;
func = 3;
enable = 1;
#10;
enable = 0;
#200;
end
endmodule
|
`timescale 1us/100ns
module data_whiting(
output [7:0] dout,
output next_indicator,
input [7:0] din,
input indicator,
input clk,
input reset_n
);
localparam RANDOM_INIT = 9'b1_1111_1111;
localparam WAITING = 0,
PADDING = 1,
ENCODING = 2;
reg [1:0] state, next_state;
reg [6:0] count, next_count;
reg [8:0] random_regs, next_random_regs;
reg [7:0] working_random, next_working_random;
wire [8:0] next_random = {random_regs[5] ^ random_regs[0], random_regs[8:1]};
always @(*) begin
case (state)
WAITING: begin
if (indicator)
next_state = PADDING;
else
next_state = WAITING;
next_count = 0;
next_random_regs = RANDOM_INIT;
next_working_random = RANDOM_INIT;
end
PADDING: begin
if (count < 79) begin
next_state = PADDING;
next_count = count + 1;
next_random_regs = RANDOM_INIT;
end else begin
next_state = ENCODING;
next_count = 0;
next_random_regs = next_random;
end
next_working_random = RANDOM_INIT;
end
ENCODING: begin
if (indicator) begin
next_state = WAITING;
next_count = 0;
end else begin
next_state = ENCODING;
next_count = count + 1;
end
next_random_regs = next_random;
next_working_random = (count[2:0] == 7 ?
random_regs :
working_random);
end
default: begin
next_state = WAITING;
next_count = 0;
next_random_regs = RANDOM_INIT;
next_working_random = RANDOM_INIT;
end
endcase
end
// Update states.
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
state <= WAITING;
count <= 0;
random_regs <= RANDOM_INIT;
working_random <= RANDOM_INIT;
end else begin
state <= next_state;
count <= next_count;
random_regs <= next_random_regs;
working_random <= next_working_random;
end
end
assign next_indicator = indicator;
assign dout = (state == ENCODING ? din ^ working_random : din);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:01:16 03/06/2017
// Design Name: DFF
// Module Name: D:/Projects/XilinxISE/HW1/Homework1/testDFF.v
// Project Name: Homework1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DFF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testMUX4_UDP();
// Inputs
reg [3:0] in;
reg [1:0] sel;
// Outputs
wire out;
// Instantiate the DESIGN Under Test (DUT)
MUX4 dut (
.in(in),
.sel(sel),
.out(out)
);
initial begin
$monitor(" in = %b sel = %b out = %b",in,sel,out);
// Initialize Inputs
in = 4'b0000;
sel = 2'b00;
#5 in = 4'b0000; sel = 2'b00;
#5 in = 4'b0001; sel = 2'b00;
#5 in = 4'b0010; sel = 2'b01;
#5 in = 4'b0100; sel = 2'b01;
#5 in = 4'bXXX0; sel = 2'b00;
#5 in = 4'b1X10; sel = 2'b11;
#5 in = 4'b1101; sel = 2'b10;
#5 in = 4'b1001; sel = 2'b10;
#1 $finish;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_tdd_control(
// clock and reset
clk,
rst,
// TDD timming signals
tdd_enable,
tdd_enable_synced,
tdd_secondary,
tdd_tx_only,
tdd_rx_only,
tdd_burst_count,
tdd_counter_init,
tdd_frame_length,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2,
tdd_sync,
tdd_sync_en,
// TDD control signals
tdd_tx_dp_en,
tdd_rx_vco_en,
tdd_tx_vco_en,
tdd_rx_rf_en,
tdd_tx_rf_en,
tdd_counter_status);
// parameters
parameter integer TX_DATA_PATH_DELAY = 0; // internally eliminate the delay introduced by the TX data path
parameter integer CONTROL_PATH_DELAY = 0; // internally eliminate the delay introduced by the control path
localparam ON = 1;
localparam OFF = 0;
// input/output signals
input clk;
input rst;
input tdd_enable;
output tdd_enable_synced;
input tdd_secondary;
input tdd_tx_only;
input tdd_rx_only;
input [ 7:0] tdd_burst_count;
input [23:0] tdd_counter_init;
input [23:0] tdd_frame_length;
input [23:0] tdd_vco_rx_on_1;
input [23:0] tdd_vco_rx_off_1;
input [23:0] tdd_vco_tx_on_1;
input [23:0] tdd_vco_tx_off_1;
input [23:0] tdd_rx_on_1;
input [23:0] tdd_rx_off_1;
input [23:0] tdd_tx_on_1;
input [23:0] tdd_tx_off_1;
input [23:0] tdd_tx_dp_on_1;
input [23:0] tdd_tx_dp_off_1;
input [23:0] tdd_vco_rx_on_2;
input [23:0] tdd_vco_rx_off_2;
input [23:0] tdd_vco_tx_on_2;
input [23:0] tdd_vco_tx_off_2;
input [23:0] tdd_rx_on_2;
input [23:0] tdd_rx_off_2;
input [23:0] tdd_tx_on_2;
input [23:0] tdd_tx_off_2;
input [23:0] tdd_tx_dp_on_2;
input [23:0] tdd_tx_dp_off_2;
input tdd_sync;
output tdd_sync_en;
output tdd_tx_dp_en; // initiate vco tx2rx switch
output tdd_rx_vco_en; // initiate vco rx2tx switch
output tdd_tx_vco_en; // power up RF Rx
output tdd_rx_rf_en; // power up RF Tx
output tdd_tx_rf_en; // enable Tx datapath
output [23:0] tdd_counter_status;
// tdd control related
reg tdd_tx_dp_en = 1'b0;
reg tdd_rx_vco_en = 1'b0;
reg tdd_tx_vco_en = 1'b0;
reg tdd_rx_rf_en = 1'b0;
reg tdd_tx_rf_en = 1'b0;
// tdd counter related
reg [23:0] tdd_counter = 24'h0;
reg [ 5:0] tdd_burst_counter = 6'h0;
reg tdd_cstate = OFF;
reg tdd_cstate_next = OFF;
reg counter_at_tdd_vco_rx_on_1 = 1'b0;
reg counter_at_tdd_vco_rx_off_1 = 1'b0;
reg counter_at_tdd_vco_tx_on_1 = 1'b0;
reg counter_at_tdd_vco_tx_off_1 = 1'b0;
reg counter_at_tdd_rx_on_1 = 1'b0;
reg counter_at_tdd_rx_off_1 = 1'b0;
reg counter_at_tdd_tx_on_1 = 1'b0;
reg counter_at_tdd_tx_off_1 = 1'b0;
reg counter_at_tdd_tx_dp_on_1 = 1'b0;
reg counter_at_tdd_tx_dp_off_1 = 1'b0;
reg counter_at_tdd_vco_rx_on_2 = 1'b0;
reg counter_at_tdd_vco_rx_off_2 = 1'b0;
reg counter_at_tdd_vco_tx_on_2 = 1'b0;
reg counter_at_tdd_vco_tx_off_2 = 1'b0;
reg counter_at_tdd_rx_on_2 = 1'b0;
reg counter_at_tdd_rx_off_2 = 1'b0;
reg counter_at_tdd_tx_on_2 = 1'b0;
reg counter_at_tdd_tx_off_2 = 1'b0;
reg counter_at_tdd_tx_dp_on_2 = 1'b0;
reg counter_at_tdd_tx_dp_off_2 = 1'b0;
reg tdd_enable_synced = 1'h0;
reg tdd_last_burst = 1'b0;
reg tdd_sync_d1 = 1'b0;
reg tdd_sync_d2 = 1'b0;
reg tdd_sync_d3 = 1'b0;
reg tdd_sync_en = 1'b0;
// internal signals
wire [23:0] tdd_vco_rx_on_1_s;
wire [23:0] tdd_vco_rx_off_1_s;
wire [23:0] tdd_vco_tx_on_1_s;
wire [23:0] tdd_vco_tx_off_1_s;
wire [23:0] tdd_rx_on_1_s;
wire [23:0] tdd_rx_off_1_s;
wire [23:0] tdd_tx_on_1_s;
wire [23:0] tdd_tx_off_1_s;
wire [23:0] tdd_tx_dp_on_1_s;
wire [23:0] tdd_tx_dp_off_1_s;
wire [23:0] tdd_vco_rx_on_2_s;
wire [23:0] tdd_vco_rx_off_2_s;
wire [23:0] tdd_vco_tx_on_2_s;
wire [23:0] tdd_vco_tx_off_2_s;
wire [23:0] tdd_rx_on_2_s;
wire [23:0] tdd_rx_off_2_s;
wire [23:0] tdd_tx_on_2_s;
wire [23:0] tdd_tx_off_2_s;
wire [23:0] tdd_tx_dp_on_2_s;
wire [23:0] tdd_tx_dp_off_2_s;
wire tdd_endof_frame;
wire tdd_endof_burst;
wire tdd_txrx_only_en_s;
assign tdd_counter_status = tdd_counter;
// synchronization of tdd_sync
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_sync_en <= 1'b0;
tdd_sync_d1 <= 1'b0;
tdd_sync_d2 <= 1'b0;
tdd_sync_d3 <= 1'b0;
end else begin
tdd_sync_en <= tdd_enable;
tdd_sync_d1 <= tdd_sync;
tdd_sync_d2 <= tdd_sync_d1;
tdd_sync_d3 <= tdd_sync_d2;
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_enable_synced <= 1'b0;
end else begin
tdd_enable_synced <= ((~tdd_sync_d3 & tdd_sync_d2) == 1'b1) ? tdd_enable : tdd_enable_synced;
end
end
// ***************************************************************************
// tdd counter (state machine)
// ***************************************************************************
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_cstate <= OFF;
end else begin
tdd_cstate <= tdd_cstate_next;
end
end
always @* begin
tdd_cstate_next <= tdd_cstate;
case (tdd_cstate)
ON : begin
if ((tdd_enable == 1'b0) || (tdd_endof_burst == 1'b1)) begin
tdd_cstate_next <= OFF;
end
end
OFF : begin
if(tdd_enable == 1'b1) begin
tdd_cstate_next <= ((~tdd_sync_d3 & tdd_sync_d2) == 1'b1) ? ON : OFF;
end
end
endcase
end
assign tdd_endof_frame = (tdd_counter == tdd_frame_length) ? 1'b1 : 1'b0;
assign tdd_endof_burst = ((tdd_last_burst == 1'b1) && (tdd_counter == tdd_frame_length)) ? 1'b1 : 1'b0;
// tdd free running counter
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_counter <= tdd_counter_init;
end else begin
if (tdd_cstate == ON) begin
if ((~tdd_sync_d3 & tdd_sync_d2) == 1'b1) begin
tdd_counter <= 24'b0;
end else begin
tdd_counter <= (tdd_counter < tdd_frame_length) ? tdd_counter + 1 : 24'b0;
end
end else begin
tdd_counter <= tdd_counter_init;
end
end
end
// tdd burst counter
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_burst_counter <= tdd_burst_count;
end else begin
if (tdd_cstate == ON) begin
tdd_burst_counter <= ((tdd_burst_counter > 0) && (tdd_endof_frame == 1'b1)) ? tdd_burst_counter - 1 : tdd_burst_counter;
end else begin
tdd_burst_counter <= tdd_burst_count;
end
end
end
always @(posedge clk) begin
tdd_last_burst <= (tdd_burst_counter == 6'b1) ? 1'b1 : 1'b0;
end
// ***************************************************************************
// generate control signals
// ***************************************************************************
// start/stop rx vco
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_on_1 <= 1'b0;
end else if(tdd_counter == tdd_vco_rx_on_1_s) begin
counter_at_tdd_vco_rx_on_1 <= 1'b1;
end else begin
counter_at_tdd_vco_rx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_on_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_on_2_s)) begin
counter_at_tdd_vco_rx_on_2 <= 1'b1;
end else begin
counter_at_tdd_vco_rx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_off_1 <= 1'b0;
end else if(tdd_counter == tdd_vco_rx_off_1_s) begin
counter_at_tdd_vco_rx_off_1 <= 1'b1;
end else begin
counter_at_tdd_vco_rx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_off_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_off_2_s)) begin
counter_at_tdd_vco_rx_off_2 <= 1'b1;
end else begin
counter_at_tdd_vco_rx_off_2 <= 1'b0;
end
end
// start/stop tx vco
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_on_1 <= 1'b0;
end else if(tdd_counter == tdd_vco_tx_on_1_s) begin
counter_at_tdd_vco_tx_on_1 <= 1'b1;
end else begin
counter_at_tdd_vco_tx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_on_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_on_2_s)) begin
counter_at_tdd_vco_tx_on_2 <= 1'b1;
end else begin
counter_at_tdd_vco_tx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_off_1 <= 1'b0;
end else if(tdd_counter == tdd_vco_tx_off_1_s) begin
counter_at_tdd_vco_tx_off_1 <= 1'b1;
end else begin
counter_at_tdd_vco_tx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_off_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_off_2_s)) begin
counter_at_tdd_vco_tx_off_2 <= 1'b1;
end else begin
counter_at_tdd_vco_tx_off_2 <= 1'b0;
end
end
// start/stop rx rf path
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_on_1 <= 1'b0;
end else if(tdd_counter == tdd_rx_on_1_s) begin
counter_at_tdd_rx_on_1 <= 1'b1;
end else begin
counter_at_tdd_rx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_on_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_on_2_s)) begin
counter_at_tdd_rx_on_2 <= 1'b1;
end else begin
counter_at_tdd_rx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_off_1 <= 1'b0;
end else if(tdd_counter == tdd_rx_off_1_s) begin
counter_at_tdd_rx_off_1 <= 1'b1;
end else begin
counter_at_tdd_rx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_off_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_off_2_s)) begin
counter_at_tdd_rx_off_2 <= 1'b1;
end else begin
counter_at_tdd_rx_off_2 <= 1'b0;
end
end
// start/stop tx rf path
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_on_1 <= 1'b0;
end else if(tdd_counter == tdd_tx_on_1_s) begin
counter_at_tdd_tx_on_1 <= 1'b1;
end else begin
counter_at_tdd_tx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_on_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_on_2_s)) begin
counter_at_tdd_tx_on_2 <= 1'b1;
end else begin
counter_at_tdd_tx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_off_1 <= 1'b0;
end else if(tdd_counter == tdd_tx_off_1_s) begin
counter_at_tdd_tx_off_1 <= 1'b1;
end else begin
counter_at_tdd_tx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_off_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_off_2_s)) begin
counter_at_tdd_tx_off_2 <= 1'b1;
end else begin
counter_at_tdd_tx_off_2 <= 1'b0;
end
end
// start/stop tx data path
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_on_1 <= 1'b0;
end else if(tdd_counter == tdd_tx_dp_on_1_s) begin
counter_at_tdd_tx_dp_on_1 <= 1'b1;
end else begin
counter_at_tdd_tx_dp_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_on_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_on_2_s)) begin
counter_at_tdd_tx_dp_on_2 <= 1'b1;
end else begin
counter_at_tdd_tx_dp_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_off_1 <= 1'b0;
end else if(tdd_counter == tdd_tx_dp_off_1_s) begin
counter_at_tdd_tx_dp_off_1 <= 1'b1;
end else begin
counter_at_tdd_tx_dp_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_off_2 <= 1'b0;
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_off_2_s)) begin
counter_at_tdd_tx_dp_off_2 <= 1'b1;
end else begin
counter_at_tdd_tx_dp_off_2 <= 1'b0;
end
end
// control-path delay compensation
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_vco_rx_on_1_comp (
.clk(clk),
.A(tdd_vco_rx_on_1),
.Amax(tdd_frame_length),
.out(tdd_vco_rx_on_1_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_vco_rx_off_1_comp (
.clk(clk),
.A(tdd_vco_rx_off_1),
.Amax(tdd_frame_length),
.out(tdd_vco_rx_off_1_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_vco_tx_on_1_comp (
.clk(clk),
.A(tdd_vco_tx_on_1),
.Amax(tdd_frame_length),
.out(tdd_vco_tx_on_1_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_vco_tx_off_1_comp (
.clk(clk),
.A(tdd_vco_tx_off_1),
.Amax(tdd_frame_length),
.out(tdd_vco_tx_off_1_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_rx_on_1_comp (
.clk(clk),
.A(tdd_rx_on_1),
.Amax(tdd_frame_length),
.out(tdd_rx_on_1_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_rx_off_1_comp (
.clk(clk),
.A(tdd_rx_off_1),
.Amax(tdd_frame_length),
.out(tdd_rx_off_1_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_tx_on_1_comp (
.clk(clk),
.A(tdd_tx_on_1),
.Amax(tdd_frame_length),
.out(tdd_tx_on_1_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_tx_off_1_comp (
.clk(clk),
.A(tdd_tx_off_1),
.Amax(tdd_frame_length),
.out(tdd_tx_off_1_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_vco_rx_on_2_comp (
.clk(clk),
.A(tdd_vco_rx_on_2),
.Amax(tdd_frame_length),
.out(tdd_vco_rx_on_2_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_vco_rx_off_2_comp (
.clk(clk),
.A(tdd_vco_rx_off_2),
.Amax(tdd_frame_length),
.out(tdd_vco_rx_off_2_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_vco_tx_on_2_comp (
.clk(clk),
.A(tdd_vco_tx_on_2),
.Amax(tdd_frame_length),
.out(tdd_vco_tx_on_2_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_vco_tx_off_2_comp (
.clk(clk),
.A(tdd_vco_tx_off_2),
.Amax(tdd_frame_length),
.out(tdd_vco_tx_off_2_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_rx_on_2_comp (
.clk(clk),
.A(tdd_rx_on_2),
.Amax(tdd_frame_length),
.out(tdd_rx_on_2_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_rx_off_2_comp (
.clk(clk),
.A(tdd_rx_off_2),
.Amax(tdd_frame_length),
.out(tdd_rx_off_2_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_tx_on_2_comp (
.clk(clk),
.A(tdd_tx_on_2),
.Amax(tdd_frame_length),
.out(tdd_tx_on_2_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(CONTROL_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_tx_off_2_comp (
.clk(clk),
.A(tdd_tx_off_2),
.Amax(tdd_frame_length),
.out(tdd_tx_off_2_s),
.CE(1'b1)
);
// internal data-path delay compensation
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(TX_DATA_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_tx_dp_on_1_comp (
.clk(clk),
.A(tdd_tx_dp_on_1),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_on_1_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(TX_DATA_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_tx_dp_on_2_comp (
.clk(clk),
.A(tdd_tx_dp_on_2),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_on_2_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(TX_DATA_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_tx_dp_off_1_comp (
.clk(clk),
.A(tdd_tx_dp_off_1),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_off_1_s),
.CE(1'b1)
);
ad_addsub #(
.A_DATA_WIDTH(24),
.B_DATA_VALUE(TX_DATA_PATH_DELAY),
.ADD_OR_SUB_N(0)
) i_tx_dp_off_2_comp (
.clk(clk),
.A(tdd_tx_dp_off_2),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_off_2_s),
.CE(1'b1)
);
// output logic
assign tdd_txrx_only_en_s = tdd_tx_only ^ tdd_rx_only;
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_rx_vco_en <= 1'b0;
end else if((tdd_cstate == OFF) || (counter_at_tdd_vco_rx_off_1 == 1'b1) || (counter_at_tdd_vco_rx_off_2 == 1'b1)) begin
tdd_rx_vco_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_vco_rx_on_1 == 1'b1) || (counter_at_tdd_vco_rx_on_2 == 1'b1))) begin
tdd_rx_vco_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_rx_vco_en <= tdd_rx_only;
end else begin
tdd_rx_vco_en <= tdd_rx_vco_en;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_tx_vco_en <= 1'b0;
end else if((tdd_cstate == OFF) || (counter_at_tdd_vco_tx_off_1 == 1'b1) || (counter_at_tdd_vco_tx_off_2 == 1'b1)) begin
tdd_tx_vco_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_vco_tx_on_1 == 1'b1) || (counter_at_tdd_vco_tx_on_2 == 1'b1))) begin
tdd_tx_vco_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_tx_vco_en <= tdd_tx_only;
end else begin
tdd_tx_vco_en <= tdd_tx_vco_en;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_rx_rf_en <= 1'b0;
end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin
tdd_rx_rf_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin
tdd_rx_rf_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_rx_rf_en <= tdd_rx_only;
end else begin
tdd_rx_rf_en <= tdd_rx_rf_en;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_tx_rf_en <= 1'b0;
end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin
tdd_tx_rf_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin
tdd_tx_rf_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_tx_rf_en <= tdd_tx_only;
end else begin
tdd_tx_rf_en <= tdd_tx_rf_en;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_tx_dp_en <= 1'b0;
end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin
tdd_tx_dp_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin
tdd_tx_dp_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_tx_dp_en <= tdd_tx_only;
end else begin
tdd_tx_dp_en <= tdd_tx_dp_en;
end
end
endmodule
|
// AJ, Beck, and Ray
// SRAM testbench
// 4/21/15
`include "SRAM2Kby16.v"
module SRAMtest();
// localize variables
wire clk, WrEn;
wire [10:0] adx;
wire [15:0] data;
// declare an instance of the module
SRAM2Kby16 SRAM (clk, adx, WrEn, data);
// Running the GUI part of simulation
SRAMtester tester (clk, adx, WrEn, data);
// file for gtkwave
initial
begin
$dumpfile("SRAMtest.vcd");
$dumpvars(1, SRAM);
end
endmodule
module SRAMtester (clk, adx, WrEn, data);
output reg [10:0] adx;
inout [15:0] data;
output reg clk, WrEn;
reg [15:0] out;
parameter d = 20;
// generate a clock
always #(d/2) clk = ~clk;
assign data = WrEn ? 16'bZ : out;
initial // Response
begin
$display("clk \t WrEn \t adx \t\t data \t\t out Time ");
#d;
clk = 0;
end
reg [31:0] i;
initial // Stimulus
begin
$monitor("%b \t %b \t %b \t %b", clk, WrEn, adx, data, $time);
WrEn = 1; adx = 0; out = 0;
#(10*d)
WrEn = 0;
for(i = 0; i < 128; i = i + 1) begin
adx = i;
out = 127 - i;
#d;
end
WrEn = 1;
for(i = 0; i < 128; i = i + 1) begin
adx = i;
#d;
end
#(2*d); // end bias
$stop;
$finish;
end
endmodule |
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
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//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response AXI3 Slave Converter
// Forwards and re-assembles split transactions.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_r_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_si_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from MI-Side to SI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// USER, ID, DATA and RRESP passes through untouched.
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions). LAST is only removed for the first parts of a split
// transaction. When splitting is unsupported is the LAST filtering completely
// completely removed.
//
/////////////////////////////////////////////////////////////////////////////
// Calculate last, i.e. mask from split transactions.
assign S_AXI_RLAST_I = M_AXI_RLAST &
( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
// Data is passed through.
assign S_AXI_RID_I = M_AXI_RID;
assign S_AXI_RUSER_I = M_AXI_RUSER;
assign S_AXI_RDATA_I = M_AXI_RDATA;
assign S_AXI_RRESP_I = M_AXI_RRESP;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
assign S_AXI_RUSER = S_AXI_RUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response AXI3 Slave Converter
// Forwards and re-assembles split transactions.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_r_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_si_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from MI-Side to SI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// USER, ID, DATA and RRESP passes through untouched.
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions). LAST is only removed for the first parts of a split
// transaction. When splitting is unsupported is the LAST filtering completely
// completely removed.
//
/////////////////////////////////////////////////////////////////////////////
// Calculate last, i.e. mask from split transactions.
assign S_AXI_RLAST_I = M_AXI_RLAST &
( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
// Data is passed through.
assign S_AXI_RID_I = M_AXI_RID;
assign S_AXI_RUSER_I = M_AXI_RUSER;
assign S_AXI_RDATA_I = M_AXI_RDATA;
assign S_AXI_RRESP_I = M_AXI_RRESP;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
assign S_AXI_RUSER = S_AXI_RUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response AXI3 Slave Converter
// Forwards and re-assembles split transactions.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_r_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_si_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from MI-Side to SI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// USER, ID, DATA and RRESP passes through untouched.
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions). LAST is only removed for the first parts of a split
// transaction. When splitting is unsupported is the LAST filtering completely
// completely removed.
//
/////////////////////////////////////////////////////////////////////////////
// Calculate last, i.e. mask from split transactions.
assign S_AXI_RLAST_I = M_AXI_RLAST &
( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
// Data is passed through.
assign S_AXI_RID_I = M_AXI_RID;
assign S_AXI_RUSER_I = M_AXI_RUSER;
assign S_AXI_RDATA_I = M_AXI_RDATA;
assign S_AXI_RRESP_I = M_AXI_RRESP;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
assign S_AXI_RUSER = S_AXI_RUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response AXI3 Slave Converter
// Forwards and re-assembles split transactions.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_r_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_si_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from MI-Side to SI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// USER, ID, DATA and RRESP passes through untouched.
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions). LAST is only removed for the first parts of a split
// transaction. When splitting is unsupported is the LAST filtering completely
// completely removed.
//
/////////////////////////////////////////////////////////////////////////////
// Calculate last, i.e. mask from split transactions.
assign S_AXI_RLAST_I = M_AXI_RLAST &
( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
// Data is passed through.
assign S_AXI_RID_I = M_AXI_RID;
assign S_AXI_RUSER_I = M_AXI_RUSER;
assign S_AXI_RDATA_I = M_AXI_RDATA;
assign S_AXI_RRESP_I = M_AXI_RRESP;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
assign S_AXI_RUSER = S_AXI_RUSER_I;
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
// -- (c) Copyright 2012 -2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_protocol_converter.v
//
// Description:
// This module is a bank of AXI4-Lite and AXI3 protocol converters for a vectored AXI interface.
// The interface of this module consists of a vectored slave and master interface
// which are each concatenations of upper-level AXI pathways,
// plus various vectored parameters.
// This module instantiates a set of individual protocol converter modules.
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_axi_protocol_converter #(
parameter C_FAMILY = "virtex6",
parameter integer C_M_AXI_PROTOCOL = 0,
parameter integer C_S_AXI_PROTOCOL = 0,
parameter integer C_IGNORE_ID = 0,
// 0 = RID/BID are stored by axilite_conv.
// 1 = RID/BID have already been stored in an upstream device, like SASD crossbar.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_TRANSLATION_MODE = 1
// 0 (Unprotected) = Disable all error checking; master is well-behaved.
// 1 (Protection) = Detect SI transaction violations, but perform no splitting.
// AXI4 -> AXI3 must be <= 16 beats; AXI4/3 -> AXI4LITE must be single.
// 2 (Conversion) = Include transaction splitting logic
) (
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
localparam P_AXI4 = 32'h0;
localparam P_AXI3 = 32'h1;
localparam P_AXILITE = 32'h2;
localparam P_AXILITE_SIZE = (C_AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;
localparam P_INCR = 2'b01;
localparam P_DECERR = 2'b11;
localparam P_SLVERR = 2'b10;
localparam integer P_PROTECTION = 1;
localparam integer P_CONVERSION = 2;
wire s_awvalid_i;
wire s_arvalid_i;
wire s_wvalid_i ;
wire s_bready_i ;
wire s_rready_i ;
wire s_awready_i;
wire s_wready_i;
wire s_bvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_bid_i;
wire [1:0] s_bresp_i;
wire [C_AXI_BUSER_WIDTH-1:0] s_buser_i;
wire s_arready_i;
wire s_rvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_rid_i;
wire [1:0] s_rresp_i;
wire [C_AXI_RUSER_WIDTH-1:0] s_ruser_i;
wire [C_AXI_DATA_WIDTH-1:0] s_rdata_i;
wire s_rlast_i;
generate
if ((C_M_AXI_PROTOCOL == P_AXILITE) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite
assign m_axi_awid = 0;
assign m_axi_awlen = 0;
assign m_axi_awsize = P_AXILITE_SIZE;
assign m_axi_awburst = P_INCR;
assign m_axi_awlock = 0;
assign m_axi_awcache = 0;
assign m_axi_awregion = 0;
assign m_axi_awqos = 0;
assign m_axi_awuser = 0;
assign m_axi_wid = 0;
assign m_axi_wlast = 1'b1;
assign m_axi_wuser = 0;
assign m_axi_arid = 0;
assign m_axi_arlen = 0;
assign m_axi_arsize = P_AXILITE_SIZE;
assign m_axi_arburst = P_INCR;
assign m_axi_arlock = 0;
assign m_axi_arcache = 0;
assign m_axi_arregion = 0;
assign m_axi_arqos = 0;
assign m_axi_aruser = 0;
if (((C_IGNORE_ID == 1) && (C_TRANSLATION_MODE != P_CONVERSION)) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite_passthru
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = 0;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = 0;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = 0;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = 1'b1;
assign s_ruser_i = 0;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else if (C_TRANSLATION_MODE == P_CONVERSION) begin : gen_b2s_conv
assign s_buser_i = {C_AXI_BUSER_WIDTH{1'b0}};
assign s_ruser_i = {C_AXI_RUSER_WIDTH{1'b0}};
axi_protocol_converter_v2_1_b2s #(
.C_S_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ)
) axilite_b2s (
.aresetn (aresetn),
.aclk (aclk),
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awprot (s_axi_awprot),
.s_axi_awvalid (s_awvalid_i),
.s_axi_awready (s_awready_i),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_wvalid_i),
.s_axi_wready (s_wready_i),
.s_axi_bid (s_bid_i),
.s_axi_bresp (s_bresp_i),
.s_axi_bvalid (s_bvalid_i),
.s_axi_bready (s_bready_i),
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arprot (s_axi_arprot),
.s_axi_arvalid (s_arvalid_i),
.s_axi_arready (s_arready_i),
.s_axi_rid (s_rid_i),
.s_axi_rdata (s_rdata_i),
.s_axi_rresp (s_rresp_i),
.s_axi_rlast (s_rlast_i),
.s_axi_rvalid (s_rvalid_i),
.s_axi_rready (s_rready_i),
.m_axi_awaddr (m_axi_awaddr),
.m_axi_awprot (m_axi_awprot),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_awready (m_axi_awready),
.m_axi_wdata (m_axi_wdata),
.m_axi_wstrb (m_axi_wstrb),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_wready (m_axi_wready),
.m_axi_bresp (m_axi_bresp),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_bready (m_axi_bready),
.m_axi_araddr (m_axi_araddr),
.m_axi_arprot (m_axi_arprot),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rdata (m_axi_rdata),
.m_axi_rresp (m_axi_rresp),
.m_axi_rvalid (m_axi_rvalid),
.m_axi_rready (m_axi_rready)
);
end else begin : gen_axilite_conv
axi_protocol_converter_v2_1_axilite_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH)
) axilite_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
end
end else if ((C_M_AXI_PROTOCOL == P_AXI3) && (C_S_AXI_PROTOCOL == P_AXI4)) begin : gen_axi4_axi3
axi_protocol_converter_v2_1_axi3_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_SUPPORT_SPLITTING ((C_TRANSLATION_MODE == P_CONVERSION) ? 1 : 0)
) axi3_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWLEN (s_axi_awlen),
.S_AXI_AWSIZE (s_axi_awsize),
.S_AXI_AWBURST (s_axi_awburst),
.S_AXI_AWLOCK (s_axi_awlock),
.S_AXI_AWCACHE (s_axi_awcache),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWQOS (s_axi_awqos),
.S_AXI_AWUSER (s_axi_awuser),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WUSER (s_axi_wuser),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARLEN (s_axi_arlen),
.S_AXI_ARSIZE (s_axi_arsize),
.S_AXI_ARBURST (s_axi_arburst),
.S_AXI_ARLOCK (s_axi_arlock),
.S_AXI_ARCACHE (s_axi_arcache),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARQOS (s_axi_arqos),
.S_AXI_ARUSER (s_axi_aruser),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWID (m_axi_awid),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWLEN (m_axi_awlen),
.M_AXI_AWSIZE (m_axi_awsize),
.M_AXI_AWBURST (m_axi_awburst),
.M_AXI_AWLOCK (m_axi_awlock),
.M_AXI_AWCACHE (m_axi_awcache),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWQOS (m_axi_awqos),
.M_AXI_AWUSER (m_axi_awuser),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WID (m_axi_wid),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WUSER (m_axi_wuser),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BID (m_axi_bid),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BUSER (m_axi_buser),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARID (m_axi_arid),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARLEN (m_axi_arlen),
.M_AXI_ARSIZE (m_axi_arsize),
.M_AXI_ARBURST (m_axi_arburst),
.M_AXI_ARLOCK (m_axi_arlock),
.M_AXI_ARCACHE (m_axi_arcache),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARQOS (m_axi_arqos),
.M_AXI_ARUSER (m_axi_aruser),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RID (m_axi_rid),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RUSER (m_axi_ruser),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
assign m_axi_awregion = 0;
assign m_axi_arregion = 0;
end else if ((C_S_AXI_PROTOCOL == P_AXI3) && (C_M_AXI_PROTOCOL == P_AXI4)) begin : gen_axi3_axi4
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = {4'h0, s_axi_awlen[3:0]};
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock[0];
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = 4'h0;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = {C_AXI_ID_WIDTH{1'b0}} ;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = {4'h0, s_axi_arlen[3:0]};
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock[0];
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = 4'h0;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else begin :gen_no_conv
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = s_axi_awlen;
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock;
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = s_axi_awregion;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = s_axi_wid;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = s_axi_arlen;
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock;
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = s_axi_arregion;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end
if ((C_TRANSLATION_MODE == P_PROTECTION) &&
(((C_S_AXI_PROTOCOL != P_AXILITE) && (C_M_AXI_PROTOCOL == P_AXILITE)) ||
((C_S_AXI_PROTOCOL == P_AXI4) && (C_M_AXI_PROTOCOL == P_AXI3)))) begin : gen_err_detect
wire e_awvalid;
reg e_awvalid_r;
wire e_arvalid;
reg e_arvalid_r;
wire e_wvalid;
wire e_bvalid;
wire e_rvalid;
reg e_awready;
reg e_arready;
wire e_wready;
reg [C_AXI_ID_WIDTH-1:0] e_awid;
reg [C_AXI_ID_WIDTH-1:0] e_arid;
reg [8-1:0] e_arlen;
wire [C_AXI_ID_WIDTH-1:0] e_bid;
wire [C_AXI_ID_WIDTH-1:0] e_rid;
wire e_rlast;
wire w_err;
wire r_err;
wire busy_aw;
wire busy_w;
wire busy_ar;
wire aw_push;
wire aw_pop;
wire w_pop;
wire ar_push;
wire ar_pop;
reg s_awvalid_pending;
reg s_awvalid_en;
reg s_arvalid_en;
reg s_awready_en;
reg s_arready_en;
reg [4:0] aw_cnt;
reg [4:0] ar_cnt;
reg [4:0] w_cnt;
reg w_borrow;
reg err_busy_w;
reg err_busy_r;
assign w_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_awlen != 0) : ((s_axi_awlen>>4) != 0);
assign r_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_arlen != 0) : ((s_axi_arlen>>4) != 0);
assign s_awvalid_i = s_axi_awvalid & s_awvalid_en & ~w_err;
assign e_awvalid = e_awvalid_r & ~busy_aw & ~busy_w;
assign s_arvalid_i = s_axi_arvalid & s_arvalid_en & ~r_err;
assign e_arvalid = e_arvalid_r & ~busy_ar ;
assign s_wvalid_i = s_axi_wvalid & (busy_w | (s_awvalid_pending & ~w_borrow));
assign e_wvalid = s_axi_wvalid & err_busy_w;
assign s_bready_i = s_axi_bready & busy_aw;
assign s_rready_i = s_axi_rready & busy_ar;
assign s_axi_awready = (s_awready_i & s_awready_en) | e_awready;
assign s_axi_wready = (s_wready_i & (busy_w | (s_awvalid_pending & ~w_borrow))) | e_wready;
assign s_axi_bvalid = (s_bvalid_i & busy_aw) | e_bvalid;
assign s_axi_bid = err_busy_w ? e_bid : s_bid_i;
assign s_axi_bresp = err_busy_w ? P_SLVERR : s_bresp_i;
assign s_axi_buser = err_busy_w ? {C_AXI_BUSER_WIDTH{1'b0}} : s_buser_i;
assign s_axi_arready = (s_arready_i & s_arready_en) | e_arready;
assign s_axi_rvalid = (s_rvalid_i & busy_ar) | e_rvalid;
assign s_axi_rid = err_busy_r ? e_rid : s_rid_i;
assign s_axi_rresp = err_busy_r ? P_SLVERR : s_rresp_i;
assign s_axi_ruser = err_busy_r ? {C_AXI_RUSER_WIDTH{1'b0}} : s_ruser_i;
assign s_axi_rdata = err_busy_r ? {C_AXI_DATA_WIDTH{1'b0}} : s_rdata_i;
assign s_axi_rlast = err_busy_r ? e_rlast : s_rlast_i;
assign busy_aw = (aw_cnt != 0);
assign busy_w = (w_cnt != 0);
assign busy_ar = (ar_cnt != 0);
assign aw_push = s_awvalid_i & s_awready_i & s_awready_en;
assign aw_pop = s_bvalid_i & s_bready_i;
assign w_pop = s_wvalid_i & s_wready_i & s_axi_wlast;
assign ar_push = s_arvalid_i & s_arready_i & s_arready_en;
assign ar_pop = s_rvalid_i & s_rready_i & s_rlast_i;
always @(posedge aclk) begin
if (~aresetn) begin
s_awvalid_en <= 1'b0;
s_arvalid_en <= 1'b0;
s_awready_en <= 1'b0;
s_arready_en <= 1'b0;
e_awvalid_r <= 1'b0;
e_arvalid_r <= 1'b0;
e_awready <= 1'b0;
e_arready <= 1'b0;
aw_cnt <= 0;
w_cnt <= 0;
ar_cnt <= 0;
err_busy_w <= 1'b0;
err_busy_r <= 1'b0;
w_borrow <= 1'b0;
s_awvalid_pending <= 1'b0;
end else begin
e_awready <= 1'b0; // One-cycle pulse
if (e_bvalid & s_axi_bready) begin
s_awvalid_en <= 1'b1;
s_awready_en <= 1'b1;
err_busy_w <= 1'b0;
end else if (e_awvalid) begin
e_awvalid_r <= 1'b0;
err_busy_w <= 1'b1;
end else if (s_axi_awvalid & w_err & ~e_awvalid_r & ~err_busy_w) begin
e_awvalid_r <= 1'b1;
e_awready <= ~(s_awready_i & s_awvalid_en); // 1-cycle pulse if awready not already asserted
s_awvalid_en <= 1'b0;
s_awready_en <= 1'b0;
end else if ((&aw_cnt) | (&w_cnt) | aw_push) begin
s_awvalid_en <= 1'b0;
s_awready_en <= 1'b0;
end else if (~err_busy_w & ~e_awvalid_r & ~(s_axi_awvalid & w_err)) begin
s_awvalid_en <= 1'b1;
s_awready_en <= 1'b1;
end
if (aw_push & ~aw_pop) begin
aw_cnt <= aw_cnt + 1;
end else if (~aw_push & aw_pop & (|aw_cnt)) begin
aw_cnt <= aw_cnt - 1;
end
if (aw_push) begin
if (~w_pop & ~w_borrow) begin
w_cnt <= w_cnt + 1;
end
w_borrow <= 1'b0;
end else if (~aw_push & w_pop) begin
if (|w_cnt) begin
w_cnt <= w_cnt - 1;
end else begin
w_borrow <= 1'b1;
end
end
s_awvalid_pending <= s_awvalid_i & ~s_awready_i;
e_arready <= 1'b0; // One-cycle pulse
if (e_rvalid & s_axi_rready & e_rlast) begin
s_arvalid_en <= 1'b1;
s_arready_en <= 1'b1;
err_busy_r <= 1'b0;
end else if (e_arvalid) begin
e_arvalid_r <= 1'b0;
err_busy_r <= 1'b1;
end else if (s_axi_arvalid & r_err & ~e_arvalid_r & ~err_busy_r) begin
e_arvalid_r <= 1'b1;
e_arready <= ~(s_arready_i & s_arvalid_en); // 1-cycle pulse if arready not already asserted
s_arvalid_en <= 1'b0;
s_arready_en <= 1'b0;
end else if ((&ar_cnt) | ar_push) begin
s_arvalid_en <= 1'b0;
s_arready_en <= 1'b0;
end else if (~err_busy_r & ~e_arvalid_r & ~(s_axi_arvalid & r_err)) begin
s_arvalid_en <= 1'b1;
s_arready_en <= 1'b1;
end
if (ar_push & ~ar_pop) begin
ar_cnt <= ar_cnt + 1;
end else if (~ar_push & ar_pop & (|ar_cnt)) begin
ar_cnt <= ar_cnt - 1;
end
end
end
always @(posedge aclk) begin
if (s_axi_awvalid & ~err_busy_w & ~e_awvalid_r ) begin
e_awid <= s_axi_awid;
end
if (s_axi_arvalid & ~err_busy_r & ~e_arvalid_r ) begin
e_arid <= s_axi_arid;
e_arlen <= s_axi_arlen;
end
end
axi_protocol_converter_v2_1_decerr_slave #
(
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_RESP (P_SLVERR),
.C_IGNORE_ID (C_IGNORE_ID)
)
decerr_slave_inst
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (e_awid),
.S_AXI_AWVALID (e_awvalid),
.S_AXI_AWREADY (),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (e_wvalid),
.S_AXI_WREADY (e_wready),
.S_AXI_BID (e_bid),
.S_AXI_BRESP (),
.S_AXI_BUSER (),
.S_AXI_BVALID (e_bvalid),
.S_AXI_BREADY (s_axi_bready),
.S_AXI_ARID (e_arid),
.S_AXI_ARLEN (e_arlen),
.S_AXI_ARVALID (e_arvalid),
.S_AXI_ARREADY (),
.S_AXI_RID (e_rid),
.S_AXI_RDATA (),
.S_AXI_RRESP (),
.S_AXI_RUSER (),
.S_AXI_RLAST (e_rlast),
.S_AXI_RVALID (e_rvalid),
.S_AXI_RREADY (s_axi_rready)
);
end else begin : gen_no_err_detect
assign s_awvalid_i = s_axi_awvalid;
assign s_arvalid_i = s_axi_arvalid;
assign s_wvalid_i = s_axi_wvalid;
assign s_bready_i = s_axi_bready;
assign s_rready_i = s_axi_rready;
assign s_axi_awready = s_awready_i;
assign s_axi_wready = s_wready_i;
assign s_axi_bvalid = s_bvalid_i;
assign s_axi_bid = s_bid_i;
assign s_axi_bresp = s_bresp_i;
assign s_axi_buser = s_buser_i;
assign s_axi_arready = s_arready_i;
assign s_axi_rvalid = s_rvalid_i;
assign s_axi_rid = s_rid_i;
assign s_axi_rresp = s_rresp_i;
assign s_axi_ruser = s_ruser_i;
assign s_axi_rdata = s_rdata_i;
assign s_axi_rlast = s_rlast_i;
end // gen_err_detect
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2012 -2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
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//-----------------------------------------------------------------------------
//
// File name: axi_protocol_converter.v
//
// Description:
// This module is a bank of AXI4-Lite and AXI3 protocol converters for a vectored AXI interface.
// The interface of this module consists of a vectored slave and master interface
// which are each concatenations of upper-level AXI pathways,
// plus various vectored parameters.
// This module instantiates a set of individual protocol converter modules.
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_axi_protocol_converter #(
parameter C_FAMILY = "virtex6",
parameter integer C_M_AXI_PROTOCOL = 0,
parameter integer C_S_AXI_PROTOCOL = 0,
parameter integer C_IGNORE_ID = 0,
// 0 = RID/BID are stored by axilite_conv.
// 1 = RID/BID have already been stored in an upstream device, like SASD crossbar.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_TRANSLATION_MODE = 1
// 0 (Unprotected) = Disable all error checking; master is well-behaved.
// 1 (Protection) = Detect SI transaction violations, but perform no splitting.
// AXI4 -> AXI3 must be <= 16 beats; AXI4/3 -> AXI4LITE must be single.
// 2 (Conversion) = Include transaction splitting logic
) (
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
localparam P_AXI4 = 32'h0;
localparam P_AXI3 = 32'h1;
localparam P_AXILITE = 32'h2;
localparam P_AXILITE_SIZE = (C_AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;
localparam P_INCR = 2'b01;
localparam P_DECERR = 2'b11;
localparam P_SLVERR = 2'b10;
localparam integer P_PROTECTION = 1;
localparam integer P_CONVERSION = 2;
wire s_awvalid_i;
wire s_arvalid_i;
wire s_wvalid_i ;
wire s_bready_i ;
wire s_rready_i ;
wire s_awready_i;
wire s_wready_i;
wire s_bvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_bid_i;
wire [1:0] s_bresp_i;
wire [C_AXI_BUSER_WIDTH-1:0] s_buser_i;
wire s_arready_i;
wire s_rvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_rid_i;
wire [1:0] s_rresp_i;
wire [C_AXI_RUSER_WIDTH-1:0] s_ruser_i;
wire [C_AXI_DATA_WIDTH-1:0] s_rdata_i;
wire s_rlast_i;
generate
if ((C_M_AXI_PROTOCOL == P_AXILITE) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite
assign m_axi_awid = 0;
assign m_axi_awlen = 0;
assign m_axi_awsize = P_AXILITE_SIZE;
assign m_axi_awburst = P_INCR;
assign m_axi_awlock = 0;
assign m_axi_awcache = 0;
assign m_axi_awregion = 0;
assign m_axi_awqos = 0;
assign m_axi_awuser = 0;
assign m_axi_wid = 0;
assign m_axi_wlast = 1'b1;
assign m_axi_wuser = 0;
assign m_axi_arid = 0;
assign m_axi_arlen = 0;
assign m_axi_arsize = P_AXILITE_SIZE;
assign m_axi_arburst = P_INCR;
assign m_axi_arlock = 0;
assign m_axi_arcache = 0;
assign m_axi_arregion = 0;
assign m_axi_arqos = 0;
assign m_axi_aruser = 0;
if (((C_IGNORE_ID == 1) && (C_TRANSLATION_MODE != P_CONVERSION)) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite_passthru
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = 0;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = 0;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = 0;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = 1'b1;
assign s_ruser_i = 0;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else if (C_TRANSLATION_MODE == P_CONVERSION) begin : gen_b2s_conv
assign s_buser_i = {C_AXI_BUSER_WIDTH{1'b0}};
assign s_ruser_i = {C_AXI_RUSER_WIDTH{1'b0}};
axi_protocol_converter_v2_1_b2s #(
.C_S_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ)
) axilite_b2s (
.aresetn (aresetn),
.aclk (aclk),
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awprot (s_axi_awprot),
.s_axi_awvalid (s_awvalid_i),
.s_axi_awready (s_awready_i),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_wvalid_i),
.s_axi_wready (s_wready_i),
.s_axi_bid (s_bid_i),
.s_axi_bresp (s_bresp_i),
.s_axi_bvalid (s_bvalid_i),
.s_axi_bready (s_bready_i),
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arprot (s_axi_arprot),
.s_axi_arvalid (s_arvalid_i),
.s_axi_arready (s_arready_i),
.s_axi_rid (s_rid_i),
.s_axi_rdata (s_rdata_i),
.s_axi_rresp (s_rresp_i),
.s_axi_rlast (s_rlast_i),
.s_axi_rvalid (s_rvalid_i),
.s_axi_rready (s_rready_i),
.m_axi_awaddr (m_axi_awaddr),
.m_axi_awprot (m_axi_awprot),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_awready (m_axi_awready),
.m_axi_wdata (m_axi_wdata),
.m_axi_wstrb (m_axi_wstrb),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_wready (m_axi_wready),
.m_axi_bresp (m_axi_bresp),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_bready (m_axi_bready),
.m_axi_araddr (m_axi_araddr),
.m_axi_arprot (m_axi_arprot),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rdata (m_axi_rdata),
.m_axi_rresp (m_axi_rresp),
.m_axi_rvalid (m_axi_rvalid),
.m_axi_rready (m_axi_rready)
);
end else begin : gen_axilite_conv
axi_protocol_converter_v2_1_axilite_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH)
) axilite_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
end
end else if ((C_M_AXI_PROTOCOL == P_AXI3) && (C_S_AXI_PROTOCOL == P_AXI4)) begin : gen_axi4_axi3
axi_protocol_converter_v2_1_axi3_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_SUPPORT_SPLITTING ((C_TRANSLATION_MODE == P_CONVERSION) ? 1 : 0)
) axi3_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWLEN (s_axi_awlen),
.S_AXI_AWSIZE (s_axi_awsize),
.S_AXI_AWBURST (s_axi_awburst),
.S_AXI_AWLOCK (s_axi_awlock),
.S_AXI_AWCACHE (s_axi_awcache),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWQOS (s_axi_awqos),
.S_AXI_AWUSER (s_axi_awuser),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WUSER (s_axi_wuser),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARLEN (s_axi_arlen),
.S_AXI_ARSIZE (s_axi_arsize),
.S_AXI_ARBURST (s_axi_arburst),
.S_AXI_ARLOCK (s_axi_arlock),
.S_AXI_ARCACHE (s_axi_arcache),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARQOS (s_axi_arqos),
.S_AXI_ARUSER (s_axi_aruser),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWID (m_axi_awid),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWLEN (m_axi_awlen),
.M_AXI_AWSIZE (m_axi_awsize),
.M_AXI_AWBURST (m_axi_awburst),
.M_AXI_AWLOCK (m_axi_awlock),
.M_AXI_AWCACHE (m_axi_awcache),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWQOS (m_axi_awqos),
.M_AXI_AWUSER (m_axi_awuser),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WID (m_axi_wid),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WUSER (m_axi_wuser),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BID (m_axi_bid),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BUSER (m_axi_buser),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARID (m_axi_arid),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARLEN (m_axi_arlen),
.M_AXI_ARSIZE (m_axi_arsize),
.M_AXI_ARBURST (m_axi_arburst),
.M_AXI_ARLOCK (m_axi_arlock),
.M_AXI_ARCACHE (m_axi_arcache),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARQOS (m_axi_arqos),
.M_AXI_ARUSER (m_axi_aruser),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RID (m_axi_rid),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RUSER (m_axi_ruser),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
assign m_axi_awregion = 0;
assign m_axi_arregion = 0;
end else if ((C_S_AXI_PROTOCOL == P_AXI3) && (C_M_AXI_PROTOCOL == P_AXI4)) begin : gen_axi3_axi4
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = {4'h0, s_axi_awlen[3:0]};
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock[0];
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = 4'h0;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = {C_AXI_ID_WIDTH{1'b0}} ;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = {4'h0, s_axi_arlen[3:0]};
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock[0];
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = 4'h0;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else begin :gen_no_conv
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = s_axi_awlen;
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock;
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = s_axi_awregion;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = s_axi_wid;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = s_axi_arlen;
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock;
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = s_axi_arregion;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end
if ((C_TRANSLATION_MODE == P_PROTECTION) &&
(((C_S_AXI_PROTOCOL != P_AXILITE) && (C_M_AXI_PROTOCOL == P_AXILITE)) ||
((C_S_AXI_PROTOCOL == P_AXI4) && (C_M_AXI_PROTOCOL == P_AXI3)))) begin : gen_err_detect
wire e_awvalid;
reg e_awvalid_r;
wire e_arvalid;
reg e_arvalid_r;
wire e_wvalid;
wire e_bvalid;
wire e_rvalid;
reg e_awready;
reg e_arready;
wire e_wready;
reg [C_AXI_ID_WIDTH-1:0] e_awid;
reg [C_AXI_ID_WIDTH-1:0] e_arid;
reg [8-1:0] e_arlen;
wire [C_AXI_ID_WIDTH-1:0] e_bid;
wire [C_AXI_ID_WIDTH-1:0] e_rid;
wire e_rlast;
wire w_err;
wire r_err;
wire busy_aw;
wire busy_w;
wire busy_ar;
wire aw_push;
wire aw_pop;
wire w_pop;
wire ar_push;
wire ar_pop;
reg s_awvalid_pending;
reg s_awvalid_en;
reg s_arvalid_en;
reg s_awready_en;
reg s_arready_en;
reg [4:0] aw_cnt;
reg [4:0] ar_cnt;
reg [4:0] w_cnt;
reg w_borrow;
reg err_busy_w;
reg err_busy_r;
assign w_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_awlen != 0) : ((s_axi_awlen>>4) != 0);
assign r_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_arlen != 0) : ((s_axi_arlen>>4) != 0);
assign s_awvalid_i = s_axi_awvalid & s_awvalid_en & ~w_err;
assign e_awvalid = e_awvalid_r & ~busy_aw & ~busy_w;
assign s_arvalid_i = s_axi_arvalid & s_arvalid_en & ~r_err;
assign e_arvalid = e_arvalid_r & ~busy_ar ;
assign s_wvalid_i = s_axi_wvalid & (busy_w | (s_awvalid_pending & ~w_borrow));
assign e_wvalid = s_axi_wvalid & err_busy_w;
assign s_bready_i = s_axi_bready & busy_aw;
assign s_rready_i = s_axi_rready & busy_ar;
assign s_axi_awready = (s_awready_i & s_awready_en) | e_awready;
assign s_axi_wready = (s_wready_i & (busy_w | (s_awvalid_pending & ~w_borrow))) | e_wready;
assign s_axi_bvalid = (s_bvalid_i & busy_aw) | e_bvalid;
assign s_axi_bid = err_busy_w ? e_bid : s_bid_i;
assign s_axi_bresp = err_busy_w ? P_SLVERR : s_bresp_i;
assign s_axi_buser = err_busy_w ? {C_AXI_BUSER_WIDTH{1'b0}} : s_buser_i;
assign s_axi_arready = (s_arready_i & s_arready_en) | e_arready;
assign s_axi_rvalid = (s_rvalid_i & busy_ar) | e_rvalid;
assign s_axi_rid = err_busy_r ? e_rid : s_rid_i;
assign s_axi_rresp = err_busy_r ? P_SLVERR : s_rresp_i;
assign s_axi_ruser = err_busy_r ? {C_AXI_RUSER_WIDTH{1'b0}} : s_ruser_i;
assign s_axi_rdata = err_busy_r ? {C_AXI_DATA_WIDTH{1'b0}} : s_rdata_i;
assign s_axi_rlast = err_busy_r ? e_rlast : s_rlast_i;
assign busy_aw = (aw_cnt != 0);
assign busy_w = (w_cnt != 0);
assign busy_ar = (ar_cnt != 0);
assign aw_push = s_awvalid_i & s_awready_i & s_awready_en;
assign aw_pop = s_bvalid_i & s_bready_i;
assign w_pop = s_wvalid_i & s_wready_i & s_axi_wlast;
assign ar_push = s_arvalid_i & s_arready_i & s_arready_en;
assign ar_pop = s_rvalid_i & s_rready_i & s_rlast_i;
always @(posedge aclk) begin
if (~aresetn) begin
s_awvalid_en <= 1'b0;
s_arvalid_en <= 1'b0;
s_awready_en <= 1'b0;
s_arready_en <= 1'b0;
e_awvalid_r <= 1'b0;
e_arvalid_r <= 1'b0;
e_awready <= 1'b0;
e_arready <= 1'b0;
aw_cnt <= 0;
w_cnt <= 0;
ar_cnt <= 0;
err_busy_w <= 1'b0;
err_busy_r <= 1'b0;
w_borrow <= 1'b0;
s_awvalid_pending <= 1'b0;
end else begin
e_awready <= 1'b0; // One-cycle pulse
if (e_bvalid & s_axi_bready) begin
s_awvalid_en <= 1'b1;
s_awready_en <= 1'b1;
err_busy_w <= 1'b0;
end else if (e_awvalid) begin
e_awvalid_r <= 1'b0;
err_busy_w <= 1'b1;
end else if (s_axi_awvalid & w_err & ~e_awvalid_r & ~err_busy_w) begin
e_awvalid_r <= 1'b1;
e_awready <= ~(s_awready_i & s_awvalid_en); // 1-cycle pulse if awready not already asserted
s_awvalid_en <= 1'b0;
s_awready_en <= 1'b0;
end else if ((&aw_cnt) | (&w_cnt) | aw_push) begin
s_awvalid_en <= 1'b0;
s_awready_en <= 1'b0;
end else if (~err_busy_w & ~e_awvalid_r & ~(s_axi_awvalid & w_err)) begin
s_awvalid_en <= 1'b1;
s_awready_en <= 1'b1;
end
if (aw_push & ~aw_pop) begin
aw_cnt <= aw_cnt + 1;
end else if (~aw_push & aw_pop & (|aw_cnt)) begin
aw_cnt <= aw_cnt - 1;
end
if (aw_push) begin
if (~w_pop & ~w_borrow) begin
w_cnt <= w_cnt + 1;
end
w_borrow <= 1'b0;
end else if (~aw_push & w_pop) begin
if (|w_cnt) begin
w_cnt <= w_cnt - 1;
end else begin
w_borrow <= 1'b1;
end
end
s_awvalid_pending <= s_awvalid_i & ~s_awready_i;
e_arready <= 1'b0; // One-cycle pulse
if (e_rvalid & s_axi_rready & e_rlast) begin
s_arvalid_en <= 1'b1;
s_arready_en <= 1'b1;
err_busy_r <= 1'b0;
end else if (e_arvalid) begin
e_arvalid_r <= 1'b0;
err_busy_r <= 1'b1;
end else if (s_axi_arvalid & r_err & ~e_arvalid_r & ~err_busy_r) begin
e_arvalid_r <= 1'b1;
e_arready <= ~(s_arready_i & s_arvalid_en); // 1-cycle pulse if arready not already asserted
s_arvalid_en <= 1'b0;
s_arready_en <= 1'b0;
end else if ((&ar_cnt) | ar_push) begin
s_arvalid_en <= 1'b0;
s_arready_en <= 1'b0;
end else if (~err_busy_r & ~e_arvalid_r & ~(s_axi_arvalid & r_err)) begin
s_arvalid_en <= 1'b1;
s_arready_en <= 1'b1;
end
if (ar_push & ~ar_pop) begin
ar_cnt <= ar_cnt + 1;
end else if (~ar_push & ar_pop & (|ar_cnt)) begin
ar_cnt <= ar_cnt - 1;
end
end
end
always @(posedge aclk) begin
if (s_axi_awvalid & ~err_busy_w & ~e_awvalid_r ) begin
e_awid <= s_axi_awid;
end
if (s_axi_arvalid & ~err_busy_r & ~e_arvalid_r ) begin
e_arid <= s_axi_arid;
e_arlen <= s_axi_arlen;
end
end
axi_protocol_converter_v2_1_decerr_slave #
(
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_RESP (P_SLVERR),
.C_IGNORE_ID (C_IGNORE_ID)
)
decerr_slave_inst
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (e_awid),
.S_AXI_AWVALID (e_awvalid),
.S_AXI_AWREADY (),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (e_wvalid),
.S_AXI_WREADY (e_wready),
.S_AXI_BID (e_bid),
.S_AXI_BRESP (),
.S_AXI_BUSER (),
.S_AXI_BVALID (e_bvalid),
.S_AXI_BREADY (s_axi_bready),
.S_AXI_ARID (e_arid),
.S_AXI_ARLEN (e_arlen),
.S_AXI_ARVALID (e_arvalid),
.S_AXI_ARREADY (),
.S_AXI_RID (e_rid),
.S_AXI_RDATA (),
.S_AXI_RRESP (),
.S_AXI_RUSER (),
.S_AXI_RLAST (e_rlast),
.S_AXI_RVALID (e_rvalid),
.S_AXI_RREADY (s_axi_rready)
);
end else begin : gen_no_err_detect
assign s_awvalid_i = s_axi_awvalid;
assign s_arvalid_i = s_axi_arvalid;
assign s_wvalid_i = s_axi_wvalid;
assign s_bready_i = s_axi_bready;
assign s_rready_i = s_axi_rready;
assign s_axi_awready = s_awready_i;
assign s_axi_wready = s_wready_i;
assign s_axi_bvalid = s_bvalid_i;
assign s_axi_bid = s_bid_i;
assign s_axi_bresp = s_bresp_i;
assign s_axi_buser = s_buser_i;
assign s_axi_arready = s_arready_i;
assign s_axi_rvalid = s_rvalid_i;
assign s_axi_rid = s_rid_i;
assign s_axi_rresp = s_rresp_i;
assign s_axi_ruser = s_ruser_i;
assign s_axi_rdata = s_rdata_i;
assign s_axi_rlast = s_rlast_i;
end // gen_err_detect
endgenerate
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/10/2016 04:46:19 PM
// Design Name:
// Module Name: exp_operation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,
input wire load_b_i,
input wire [EW-1:0] Data_A_i,
input wire [EW-1:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW-1:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
//wire [EW-1:0] Data_B;
wire [EW:0] Data_S;
/////////////////////////////////////////7
//genvar j;
//for (j=0; j<EW; j=j+1)begin
// assign Data_B[j] = PreData_B_i[j] ^ Add_Subt_i;
//end
/////////////////////////////////////////
add_sub_carry_out #(.W(EW)) exp_add_subt(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S (Data_S)
);
//assign Overflow_flag_o = 1'b0;
//assign Underflow_flag_o = 1'b0;
Comparators #(.W_Exp(EW+1)) array_comparators(
.exp(Data_S),
.overflow(Overflow_flag),
.underflow(Underflow_flag)
);
RegisterAdd #(.W(EW)) exp_result(
.clk (clk),
.rst (rst),
.load (load_a_i),
.D (Data_S[EW-1:0]),
.Q (Data_Result_o)
);
RegisterAdd #(.W(1)) Overflow (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Overflow_flag),
.Q(Overflow_flag_o)
);
RegisterAdd #(.W(1)) Underflow (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Underflow_flag),
.Q(Underflow_flag_o)
);
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
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