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1.05M
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`timescale 1ns/100ps
module tb_n();
reg clk;
reg reset_n;
reg [15:0] in_data;
reg in_dv;
reg in_fv;
wire out_fv;
wire out_dv;
wire [15:0] out_data;
reg [15:0] out_data_s;
integer fp_out;
integer fp_in;
integer fp_norm;
integer dummy;
reg [31:0] counter;
reg [31:0] toto;
initial begin
$dumpfile("/tmp/tb_n.vcd");
$dumpvars;
fp_out = $fopen("data_out.txt", "w");
fp_norm = $fopen("data_norm.txt", "w");
fp_in = $fopen("input.txt", "r");
clk = 0;
reset_n = 1;
in_dv =0;
in_data =0;
counter = 0;
toto = 0;
#1 reset_n = 1'd0;
#4 reset_n = 1'd1;
end
always #1 clk = ~clk;
always@(posedge clk)
if (reset_n == 0)
in_dv <= 0;
else
if (counter < 15 || toto > 1)
in_dv <= $random;
else
in_dv <= 0;
always@(posedge clk)
if (reset_n == 0)
in_fv <= 0;
else
if (counter < 15 || toto > 1)
in_fv <= 1;
else
in_fv <= 0;
always@(posedge clk)
if (reset_n == 0)
toto <= 0;
else
if(counter >= 15)
toto <= toto + 1;
always@(posedge clk)
if (reset_n == 0)
in_data <= 0;
else
if (counter < 15 || toto > 1)
//in_data <= $random;
dummy = $fscanf(fp_in,"%d\n",in_data);
else
in_data <= 0;
always@(posedge clk)
if (reset_n == 0)
counter <= 0;
else
if (in_dv)
counter <= counter + 1;
always@(posedge clk)
if (in_fv & in_dv)
$fwrite(fp_out, "%d\n", in_data);
always@(*)
out_data_s = out_data;
always@(posedge clk)
if (out_fv & out_dv)
$fwrite(fp_norm, "%d\n", out_data_s);
norm norm_inst(
.clk_proc(clk),
.reset_n(reset_n),
.in_fv(in_fv),
.in_dv(in_dv),
.in_data(in_data),
.out_fv(out_fv),
.out_dv(out_dv),
.out_data(out_data),
.addr_rel_i(),
.wr_i(),
.datawr_i(),
.rd_i(),
.datard_o()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SDLCLKP_BEHAVIORAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDLCLKP_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:12:22 08/30/2014
// Design Name: lab4dpath
// Module Name: C:/ece4743/projects/lab4_part1_solution/tb_lab4dpath.v
// Project Name: lab4_part1_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: lab4dpath
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lab4dpath;
// Inputs
reg [9:0] x1;
reg [9:0] x2;
reg [9:0] x3;
// Outputs
wire [9:0] y;
reg clock;
reg[8*100:1] aline;
`define FSIZE 1024
`define LATENCY 3
integer infifo[(`FSIZE-1):0];
integer head,tail;
integer fd;
integer count,status;
integer i_a, i_b, i_c, i_result;
integer o_a, o_b, o_c, o_result;
integer errors;
integer clock_count;
// Instantiate the Unit Under Test (UUT)
lab4dpath uut (
.x1(x1),
.x2(x2),
.x3(x3),
.clk(clock),
.y(y)
);
initial begin
clock = 0;
#100 //reset delay
forever #25 clock = ~clock;
end
initial begin
// Initialize Inputs
x1 = 0;
x2 = 0;
x3 = 0;
head = 0;
tail = 0;
clock_count = 0;
fd = $fopen("multadd_vectors.txt","r");
count = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
errors = 0;
while ($fgets(aline,fd)) begin
status = $sscanf(aline,"%x %x %x %x",i_a, i_b, i_c, i_result);
@(negedge clock);
x1 = i_a;
x2 = i_b;
x3 = i_c;
infifo[head]=i_a;inc_head;
infifo[head]=i_b;inc_head;
infifo[head]=i_c;inc_head;
infifo[head]=i_result;inc_head;
end //end while
end
task inc_head;
begin
head = head + 1;
if (head == `FSIZE) head = 0;
end
endtask
task inc_tail;
begin
tail = tail + 1;
if (tail == `FSIZE) tail = 0;
end
endtask
always @(negedge clock) begin
clock_count = clock_count + 1;
if (clock_count > `LATENCY+1) begin
o_a = infifo[tail];inc_tail;
o_b = infifo[tail];inc_tail;
o_c = infifo[tail];inc_tail;
o_result = infifo[tail];inc_tail;
if (o_result == y) begin
$display("%d PASS, x1: %x, x2: %x, x3: %x, y: %x\n",count,o_a,o_b,o_c,y);
end else begin
$display("%d FAIL, x1: %x, x2: %x, x3: %x, y (actual): %x, y (expected): %x\n",count,o_a,o_b,o_c,y,o_result);
errors = errors + 1;
end
end //end if
end
endmodule
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module ALU4_LA(a, b, c_in, c_out, less, sel, out, P, G);
input less;
input [3:0] a, b;
input [2:0] sel;
input c_in;
output [3:0] out;
output P,G;
output c_out;
wire [2:0] c;
wire [3:0] p, g;
alu_slice_LA a1(a[0], b[0], c_in, less, sel, out[0], p[0], g[0]);
alu_slice_LA a2(a[1], b[1], c[0], 1'b0, sel, out[1], p[1], g[1]);
alu_slice_LA a3(a[2], b[2], c[1], 1'b0, sel, out[2], p[2], g[2]);
alu_slice_LA a4(a[3], b[3], c[2], 1'b0, sel, out[3], p[3], g[3]);
lookahead l1(c_in, c_out, c, p, g, P, G);
endmodule |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
if (fifo_reset) begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= #1 top_plus_1;
count <= #1 count + 1'b1;
end
2'b01 : if(count>0)
begin
bottom <= #1 bottom + 1'b1;
count <= #1 count - 1'b1;
end
2'b11 : begin
bottom <= #1 bottom + 1'b1;
top <= #1 top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= #1 1'b0;
else
if(fifo_reset | reset_status)
overrun <= #1 1'b0;
else
if(push & (count==fifo_depth))
overrun <= #1 1'b1;
end // always
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V |
`include "hglobal.v"
`default_nettype none
`define NS_DBG_NXT_ADDR(adr) ((adr >= MAX_ADDR)?(MIN_ADDR):(adr + 1))
`define NS_DBG_SRC 9
`define NS_DBG_RED 10
module io_1to2
#(parameter
MIN_ADDR=1,
MAX_ADDR=1,
OPER_1=`NS_GT_OP,
REF_VAL_1=0,
IS_RANGE=`NS_FALSE,
OPER_2=`NS_GT_OP,
REF_VAL_2=0,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
input wire src0_clk,
input wire snk0_clk,
input wire snk1_clk,
input wire reset,
// SRC
`NS_DECLARE_OUT_CHNL(o0),
// SNK_0
`NS_DECLARE_IN_CHNL(i0),
// SNK_1
`NS_DECLARE_IN_CHNL(i1),
`NS_DECLARE_DBG_CHNL(dbg)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
parameter SND_ACK_CKS = `NS_ACK_CKS;
`NS_DEBOUNCER_ACK(src0_clk, reset, o0)
`NS_DEBOUNCER_REQ(snk0_clk, reset, i0)
`NS_DEBOUNCER_REQ(snk1_clk, reset, i1)
`NS_DECLARE_REG_DBG(rg_dbg)
reg [RSZ-1:0] err_mg_redun = 0;
reg [3:0] cnt_0 = 0;
reg [3:0] cnt_1 = 0;
reg [DSZ-1:0] r_dat1 = 0;
// SRC regs
reg [0:0] ro0_has_dst = `NS_OFF;
reg [0:0] ro0_has_dat = `NS_OFF;
reg [0:0] ro0_has_red = `NS_OFF;
reg [0:0] ro0_busy = `NS_OFF;
reg [ASZ-1:0] ro0_src = `NS_DBG_SRC;
reg [DSZ-1:0] ro0_dat = 0;
reg [ASZ-1:0] ro0_dst = MIN_ADDR;
reg [RSZ-1:0] ro0_red = 0;
reg [0:0] ro0_req = `NS_OFF;
reg [0:0] ro0_err = `NS_OFF;
// SNK_0 regs
reg [0:0] has_inp0 = `NS_OFF;
reg [0:0] inp0_has_redun = `NS_OFF;
reg [0:0] inp0_done_cks = `NS_OFF;
`NS_DECLARE_REG_MSG(inp0)
wire [RSZ-1:0] inp0_calc_redun;
reg [RSZ-1:0] inp0_redun = 0;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
md_calc_red0 (inp0_src, inp0_dst, inp0_dat, inp0_calc_redun);
reg [0:0] inp0_ack = `NS_OFF;
reg [DSZ-1:0] inp0_back_dat = 15;
//reg [ASZ-1:0] inp0_back_dst = 0;
reg [0:0] inp0_err = `NS_OFF;
// SNK_1 regs
reg [3:0] err1_case = 0;
reg [0:0] has_inp1 = `NS_OFF;
reg [0:0] inp1_has_redun = `NS_OFF;
reg [0:0] inp1_done_cks = `NS_OFF;
`NS_DECLARE_REG_MSG(inp1)
wire [RSZ-1:0] inp1_calc_redun;
reg [RSZ-1:0] inp1_redun = 0;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
md_calc_red1 (inp1_src, inp1_dst, inp1_dat, inp1_calc_redun);
reg [0:0] inp1_ack = `NS_OFF;
reg [DSZ-1:0] inp1_back_dat = 15;
reg [0:0] inp1_err = `NS_OFF;
//reg r_curr_src = 0;
wire [RSZ-1:0] ro0_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
r1 (ro0_src, ro0_dst, ro0_dat, ro0_redun);
//SRC
always @(posedge src0_clk)
begin
if((! ro0_req) && (! o0_ckd_ack)) begin
if(! ro0_has_dst) begin
ro0_has_dst <= `NS_ON;
ro0_dst <= `NS_DBG_NXT_ADDR(ro0_dst);
end
else
if(! ro0_has_dat) begin
ro0_has_dat <= `NS_ON;
/*if(ro0_dat > 15) begin
ro0_err <= `NS_ON;
end
if(ro0_dat < 0) begin
ro0_err <= `NS_ON;
end*/
if(! `NS_RANGE_CMP_OP(IS_RANGE, OPER_1, REF_VAL_1, ro0_dst, OPER_2, REF_VAL_2, ro0_dst)) begin
ro0_dat[3:0] <= cnt_0;
cnt_0 <= cnt_0 + 1;
end else begin
ro0_dat[3:0] <= cnt_1;
cnt_1 <= cnt_1 + 1;
end
end
else
if(! ro0_has_red) begin
ro0_has_red <= `NS_ON;
ro0_red <= ro0_redun;
end
if(ro0_has_red) begin
ro0_req <= `NS_ON;
end
end
if(ro0_req && o0_ckd_ack) begin
ro0_has_dst <= `NS_OFF;
ro0_has_dat <= `NS_OFF;
ro0_has_red <= `NS_OFF;
ro0_req <= `NS_OFF;
end
end
//SNK_0
always @(posedge snk0_clk)
begin
if(i0_ckd_req && (! inp0_ack)) begin
if(! has_inp0) begin
has_inp0 <= `NS_ON;
`NS_MOV_REG_MSG(inp0, i0)
end
else
if(! inp0_has_redun) begin
inp0_has_redun <= `NS_ON;
inp0_redun <= inp0_calc_redun;
end
else
if(! inp0_done_cks) begin
inp0_done_cks <= `NS_ON;
if(! inp0_err) begin
if(! `NS_RANGE_CMP_OP(IS_RANGE, OPER_1, REF_VAL_1, inp0_dst, OPER_2, REF_VAL_2, inp0_dst)) begin
inp0_err <= `NS_ON;
end
else
if(inp0_src != `NS_DBG_SRC) begin
inp0_err <= `NS_ON;
end
/*else
if(inp0_dat > 15) begin
inp0_err <= `NS_ON;
end
else
if(inp0_dat < 0) begin
inp0_err <= `NS_ON;
end*/
else
if(inp0_red != inp0_redun) begin
inp0_err <= `NS_ON;
end
//else
if((inp0_back_dat <= 14) && ((inp0_back_dat + 1) != inp0_dat)) begin
inp0_err <= `NS_ON;
//rg_dbg_disp0 <= inp0_back_dat[3:0];
//rg_dbg_disp1 <= inp0_dat[3:0];
end
else
begin
inp0_back_dat <= inp0_dat;
end
end
end
if(inp0_done_cks) begin
rg_dbg_disp0 <= inp0_dat[3:0];
has_inp0 <= `NS_OFF;
inp0_has_redun <= `NS_OFF;
inp0_done_cks <= `NS_OFF;
inp0_ack <= `NS_ON;
end
end
else
if((! i0_ckd_req) && inp0_ack) begin
inp0_ack <= `NS_OFF;
end
end
//SNK_1
always @(posedge snk1_clk)
begin
if(i1_ckd_req && (! inp1_ack)) begin
if(! has_inp1) begin
has_inp1 <= `NS_ON;
`NS_MOV_REG_MSG(inp1, i1)
end
else
if(! inp1_has_redun) begin
inp1_has_redun <= `NS_ON;
inp1_redun <= inp1_calc_redun;
end
else
if(! inp1_done_cks) begin
inp1_done_cks <= `NS_ON;
if(! inp1_err) begin
if(`NS_RANGE_CMP_OP(IS_RANGE, OPER_1, REF_VAL_1, inp1_dst, OPER_2, REF_VAL_2, inp1_dst)) begin
inp1_err <= `NS_ON;
end
else
if(inp1_src != `NS_DBG_SRC) begin
inp1_err <= `NS_ON;
end
/*else
if(inp1_dat > 15) begin
inp1_err <= `NS_ON;
end
else
if(inp1_dat < 0) begin
inp1_err <= `NS_ON;
end*/
else
if(inp1_red != inp1_redun) begin
inp1_err <= `NS_ON;
end
//else
if((inp1_back_dat <= 14) && ((inp1_back_dat + 1) != inp1_dat)) begin
inp1_err <= `NS_ON;
end
else
begin
inp1_back_dat <= inp1_dat;
end
end
end
if(inp1_done_cks) begin
rg_dbg_disp1 <= inp1_dat[3:0];
has_inp1 <= `NS_OFF;
inp1_has_redun <= `NS_OFF;
inp1_done_cks <= `NS_OFF;
inp1_ack <= `NS_ON;
end
end
else
if((! i1_ckd_req) && inp1_ack) begin
inp1_ack <= `NS_OFF;
end
end
//DBG
/*
always @(posedge dbg_clk)
begin
case(dbg_case)
8'h30 :
begin
end
endcase
end
*/
//SRC
`NS_ASSIGN_MSG(o0, ro0)
assign o0_req_out = ro0_req;
//SNK_0
assign i0_ack_out = inp0_ack;
//SNK_1
assign i1_ack_out = inp1_ack;
//`NS_ASSIGN_OUT_DBG(dbg, rg_dbg)
assign dbg_leds[0:0] = inp0_err;
assign dbg_leds[1:1] = inp1_err;
assign dbg_leds[2:2] = ro0_err;
assign dbg_leds[3:3] = 0;
assign dbg_disp0 = rg_dbg_disp0;
assign dbg_disp1 = rg_dbg_disp1;
endmodule
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module rom32(address, data_out);
input [31:0] address;
output [31:0] data_out;
reg [31:0] data_out;
parameter BASE_ADDRESS = 25'd0; // address that applies to this memory
wire [5:0] mem_offset;
wire address_select;
assign mem_offset = address[7:2]; // drop 2 LSBs to get word offset
assign address_select = (address[31:8] == BASE_ADDRESS); // address decoding
always @(address_select or mem_offset)
begin
if ((address % 4) != 0) $display($time, " rom32 error: unaligned address %d", address);
if (address_select == 1)
begin
case (mem_offset)
5'd0 : data_out = { 6'd35, 5'd0, 5'd2, 16'd4 };//lw $2, 4($0) r2=1
5'd1 : data_out = { 6'd0, 5'd2, 5'd2, 5'd3, 5'd0, 6'd32 }; //add $3, $2, $2
5'd2 : data_out = { 6'd2, 26'd0 }; //J 0
// add more cases here as desired
default data_out = 32'hxxxx;
endcase
$display($time, " reading data: rom32[%h] => %h", address, data_out);
end
end
endmodule
|
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ([email protected])
//
// Copyright (c) 2004 Guy Hutchison ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80_reg (/*AUTOARG*/
// Outputs
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
// Inputs
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
);
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output [7:0] DOAL;
output [7:0] DOCL;
input [7:0] DIL;
output [7:0] DOBL;
output [7:0] DOCH;
output [7:0] DOAH;
input clk, CEN, WEH, WEL;
reg [7:0] RegsH [0:7];
reg [7:0] RegsL [0:7];
always @(posedge clk)
begin
if (CEN)
begin
if (WEH) RegsH[AddrA] <= DIH;
if (WEL) RegsL[AddrA] <= DIL;
end
end
assign DOAH = RegsH[AddrA];
assign DOAL = RegsL[AddrA];
assign DOBH = RegsH[AddrB];
assign DOBL = RegsL[AddrB];
assign DOCH = RegsH[AddrC];
assign DOCL = RegsL[AddrC];
// break out ram bits for waveform debug
wire [7:0] H = RegsH[2];
wire [7:0] L = RegsL[2];
// synopsys dc_script_begin
// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1 2004/05/16 17:39:57 ghutchis Exp $" -type string -quiet
// synopsys dc_script_end
endmodule
|
Require Export Iron.Language.SystemF2Data.Step.
(********************************************************************)
(* Big Step Evaluation
This is also called 'Natural Semantics'.
It provides a relation between the expression to be reduced
and its final value. *)
Inductive EVAL : exp -> exp -> Prop :=
| EvDone
: forall v2
, wnfX v2
-> EVAL v2 v2
| EVLAMAPP
: forall x1 x12 t2 v3
, EVAL x1 (XLAM x12)
-> EVAL (substTX 0 t2 x12) v3
-> EVAL (XAPP x1 t2) v3
| EvLamApp
: forall x1 t11 x12 x2 v2 v3
, EVAL x1 (XLam t11 x12)
-> EVAL x2 v2
-> EVAL (substXX 0 v2 x12) v3
-> EVAL (XApp x1 x2) v3
| EvCon
: forall dc ts xs vs
, EVALS xs vs
-> EVAL (XCon dc ts xs) (XCon dc ts vs)
| EvCase
: forall x1 x2 v3 dc ts vs alts
, EVAL x1 (XCon dc ts vs)
-> Forall wnfX vs
-> getAlt dc alts = Some (AAlt dc x2)
-> EVAL (substXXs 0 vs x2) v3
-> EVAL (XCase x1 alts) v3
| EvPrim
: forall p xs vs v
, EVALS xs vs
-> Forall wnfX vs
-> stepPrim p vs = Some v
-> EVAL (XPrim p xs) v
with EVALS : list exp -> list exp -> Prop :=
| EvsNil
: EVALS nil nil
| EvsCons
: forall x v xs vs
, EVAL x v
-> EVALS xs vs
-> EVALS (x :: xs) (v :: vs).
Hint Constructors EVAL.
Hint Constructors EVALS.
(********************************************************************)
(* Invert all hypothesis that are compound eval statements. *)
Ltac inverts_eval :=
repeat
(match goal with
| [ H: EVAL (XApp _ _) _ |- _ ] => inverts H
| [ H: EVAL (XAPP _ _) _ |- _ ] => inverts H
| [ H: EVAL (XCon _ _ _) _ |- _ ] => inverts H
| [ H: EVAL (XCase _ _) _ |- _ ] => inverts H
| [ H: EVAL (XPrim _ _) _ |- _ ] => inverts H
end).
(********************************************************************)
Theorem EVAL_mutind
: forall (PE : exp -> exp -> Prop)
(PS : list exp -> list exp -> Prop)
, (forall v2
, wnfX v2
-> PE v2 v2)
-> (forall x1 x12 t2 v3
, EVAL x1 (XLAM x12) -> PE x1 (XLAM x12)
-> EVAL (substTX 0 t2 x12) v3 -> PE (substTX 0 t2 x12) v3
-> PE (XAPP x1 t2) v3)
-> (forall x1 t11 x12 x2 v2 v3
, EVAL x1 (XLam t11 x12 ) -> PE x1 (XLam t11 x12)
-> EVAL x2 v2 -> PE x2 v2
-> EVAL (substXX 0 v2 x12) v3 -> PE (substXX 0 v2 x12) v3
-> PE (XApp x1 x2) v3)
-> (forall dc xs ts vs
, EVALS xs vs -> PS xs vs
-> PE (XCon dc ts xs) (XCon dc ts vs))
-> (forall x1 x2 v3 dc ts vs alts
, EVAL x1 (XCon dc ts vs) -> PE x1 (XCon dc ts vs)
-> Forall wnfX vs
-> getAlt dc alts = Some (AAlt dc x2)
-> EVAL (substXXs 0 vs x2) v3 -> PE (substXXs 0 vs x2) v3
-> PE (XCase x1 alts) v3)
-> (forall p xs vs v
, EVALS xs vs -> PS xs vs
-> Forall wnfX vs
-> stepPrim p vs = Some v
-> PE (XPrim p xs) v)
-> ( PS nil nil)
-> (forall x v xs vs
, EVAL x v -> PE x v
-> EVALS xs vs -> PS xs vs
-> PS (x :: xs) (v :: vs))
-> forall x1 x2
, EVAL x1 x2 -> PE x1 x2.
Proof.
intros PE PS.
intros Hdone HLAM Hlam Hcon Hcase Hprim Hnil Hcons.
refine (fix IHPE x x' (HE: EVAL x x') {struct HE}
: PE x x' := _
with IHPS xs xs' (HS: EVALS xs xs') {struct HS}
: PS xs xs' := _
for IHPE).
case HE; intros.
eapply Hdone; eauto.
eapply HLAM; eauto.
eapply Hlam; eauto.
eapply Hcon; eauto.
eapply Hcase; eauto.
eapply Hprim; eauto.
case HS; intros.
eapply Hnil.
eapply Hcons; eauto.
Qed.
(********************************************************************)
(* Evaluating a wnf is identity. *)
Lemma eval_wnf_id
: forall x v
, wnfX x
-> EVAL x v
-> x = v.
Proof.
intros.
induction H0 using EVAL_mutind with
(PS := fun xs vs
=> Forall wnfX xs
-> EVALS xs vs
-> xs = vs);
inverts H; eauto.
- rip. subst. auto.
- rip. subst. auto.
Qed.
Lemma evals_wnf_id
: forall xs vs
, Forall wnfX xs
-> EVALS xs vs
-> xs = vs.
Proof.
intros.
induction H0; auto.
+ inverts H. rip. subst.
cut (x = v); intros. subst. auto.
eapply eval_wnf_id; auto.
Qed.
Lemma evals_wnfX
: forall vs
, Forall wnfX vs
-> EVALS vs vs.
Proof.
intros.
induction vs. auto.
inverts H. rip.
Qed.
Hint Resolve evals_wnfX.
(* A terminating big-step evaluation always produces a whnf.
The fact that the evaluation terminated is implied by the fact
that we have a finite proof of EVAL to pass to this lemma. *)
Lemma eval_produces_wnfX
: forall x1 v1
, EVAL x1 v1
-> wnfX v1.
Proof.
intros.
induction H using EVAL_mutind with
(PS := fun xs vs
=> EVALS xs vs
-> Forall wnfX vs);
intros; eauto.
Qed.
Hint Resolve eval_produces_wnfX.
Lemma evals_produces_wnfX
: forall xs vs
, EVALS xs vs
-> Forall wnfX vs.
Proof.
intros.
induction H; eauto.
Qed.
Hint Resolve evals_produces_wnfX.
(********************************************************************)
(* Big to Small steps
Convert a big-step evaluation into a list of individual
machine steps. *)
Lemma steps_of_eval
: forall ds x1 t1 x2
, TYPE ds nil nil x1 t1
-> EVAL x1 x2
-> STEPS x1 x2.
Proof.
intros ds x1 t1 v2 HT HE. gen t1.
induction HE using EVAL_mutind with
(PS := fun xs vs => forall ts
, Forall2 (TYPE ds nil nil) xs ts
-> EVALS xs vs
-> Forall2 STEPS xs vs)
; intros.
(*************************************)
- Case "EvDone".
intros. apply EsNone.
(*************************************)
- Case "EVLAMAPP".
intros. inverts HT.
lets E1: IHHE1 H1. clear IHHE1.
lets T1: preservation_steps H1 E1. inverts keep T1.
lets T2: subst_type_exp H2 H3.
simpl in T2.
lets E2: IHHE2 T2.
eapply EsAppend.
+ lets D: steps_context XcAPP. eapply D. eauto.
+ eapply EsAppend.
* eapply EsStep.
eapply EsLAMAPP.
* auto.
(*************************************)
- Case "EvLamApp".
intros. inverts HT.
lets E1: IHHE1 H1.
lets E2: IHHE2 H3.
lets T1: preservation_steps H1 E1. inverts keep T1.
lets T2: preservation_steps H3 E2.
lets T3: subst_exp_exp H6 T2.
lets E3: IHHE3 T3.
eapply EsAppend.
+ lets D: steps_context XcApp1. eapply D. eauto.
+ eapply EsAppend.
* lets D: steps_context (XcApp2 (XLam t0 x12)).
eapply Value. eauto. unfold closedX.
have (0 = @length ki nil). rewrite H at 1.
rrwrite (0 = @length ty nil). eauto.
eapply D. eauto.
* eapply EsAppend.
eapply EsStep.
eapply EsLamApp. eauto.
eauto.
(*************************************)
- Case "EvCon".
intros.
inverts HT.
lets D: IHHE H8 H.
eapply steps_in_XCon; eauto.
(*************************************)
- Case "EvCase".
intros. inverts keep HT.
lets Ex1: IHHE1 H3. clear IHHE1.
eapply EsAppend.
(* evaluate the discriminant *)
+ lets HSx1: steps_context XcCase. eapply HSx1.
eapply Ex1.
(* choose the alternative *)
+ lets HTCon: preservation_steps H3 Ex1. clear Ex1.
have HA: (TYPEA ds nil nil (AAlt dc x2) tObj t1)
by (repeat nforall; eauto).
inverts HA. inverts HTCon.
rewrite H17 in H10. inverts H10.
rewrite H16 in H9. inverts H9.
clear H7.
have (ts = tsParam)
by (eapply makeTApps_args_eq; eauto).
have HL1: (length ts = length ks0).
have HL2: (length tsParam = length ks0).
rewrite <- HL2 in HL1. eauto.
subst.
(* substitute ctor values into alternative *)
eapply EsAppend.
* eapply EsStep.
eapply EsCaseAlt; auto.
rewrite Forall_forall in H; eauto.
* eapply IHHE2.
eapply subst_exp_exp_list; eauto.
(*************************************)
- Case "EvPrim".
inverts keep HT.
lets Ex1: IHHE H6. clear IHHE. rip.
eapply EsAppend.
(* evaluate the arguments. *)
+ eapply steps_in_XPrim; eauto.
(* evaluate the operator. *)
+ eauto.
(*************************************)
- Case "EvsNil".
auto.
- Case "EvsHead".
destruct ts.
+ inverts H0.
+ inverts H0. eauto.
Qed.
(********************************************************************)
(* Small to Big steps
Convert a list of individual machine steps to a big-step
evaluation. The main part of this is the expansion lemma, which
we use to build up the overall big-step evaluation one small-step
at a time. The other lemmas are used to feed it small-steps. *)
(* Given an existing big-step evalution, we can produce a new one
that does an extra step before returning the original value.
*)
Lemma eval_expansion
: forall ds ke te x1 t1 x2 v3
, TYPE ds ke te x1 t1
-> STEP x1 x2 -> EVAL x2 v3
-> EVAL x1 v3.
Proof.
intros ds ke te x1 t1 x2 v3 HT HS. gen ds ke te t1 v3.
induction HS; intros;
try (solve [inverts H; eauto]);
try eauto.
- Case "Context".
destruct H; inverts_type; eauto.
+ SCase "XcApp1".
inverts_eval. inverts H. eauto.
+ SCase "XcApp2".
inverts_eval. inverts H1. eauto.
+ SCase "XcAPP".
inverts_eval. inverts H. eauto.
+ SCase "XcCon".
have (exists t, TYPE ds ke te x t)
by (eapply exps_ctx_Forall2_exists_left; eauto).
dest t.
inverts_eval.
* inverts H2.
eapply EvCon. clear H9.
induction H; intros.
inverts H3.
eapply EvsCons.
eauto.
induction xs.
eauto.
inverts H7. eauto.
inverts H3. eauto.
* eapply EvCon.
clear H5 H6 H9.
gen vs.
induction H; intros.
inverts H11; eauto.
inverts H11; eauto.
+ SCase "XcPrim".
have (exists t, TYPE ds ke te x t)
by (eapply exps_ctx_Forall2_exists_left; eauto).
dest t.
inverts_eval.
* inverts H2.
* eapply EvPrim; eauto.
clear H3 H5 H9.
gen vs.
induction H; intros.
inverts H6; eauto.
inverts H6; eauto.
+ SCase "XcCase".
inverts H0. inverts H. eauto.
- SCase "XcPrim".
eapply EvPrim; eauto.
eapply eval_wnf_id in H1; auto.
+ subst. auto.
+ eapply stepPrim_result_wnfX; eauto.
Qed.
(* Convert a list of small steps to a big-step evaluation. *)
Lemma eval_of_stepsl
: forall ds x1 t1 v2
, TYPE ds nil nil x1 t1
-> STEPSL x1 v2 -> value v2
-> EVAL x1 v2.
Proof.
intros.
induction H0.
- Case "EslNone".
apply EvDone. inverts H1. auto.
- Case "EslCons".
eapply eval_expansion; eauto.
apply IHSTEPSL; auto.
eapply preservation; eauto.
Qed.
(* Convert a multi-step evaluation to a big-step evaluation.
We use stepsl_of_steps to flatten out the append constructors
in the multi-step evaluation, leaving a list of individual
small-steps.
*)
Lemma eval_of_steps
: forall ds x1 t1 v2
, TYPE ds nil nil x1 t1
-> STEPS x1 v2 -> value v2
-> EVAL x1 v2.
Proof.
intros.
eapply eval_of_stepsl; eauto.
apply stepsl_of_steps; auto.
Qed.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:55:28 05/08/2015
// Design Name:
// Module Name: branch
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module branch(
input branch_d,
input [3:0] branch_condition_d,
input Z,
input N,
input V,
input C,
output reg PC_source
);
reg branch_taken;
always @(*) begin
case (branch_condition_d)
4'h0: branch_taken <= Z;
4'h1: branch_taken <= ~Z;
4'h2: branch_taken <= C;
4'h3: branch_taken <= ~C;
4'h4: branch_taken <= N;
4'h5: branch_taken <= ~N;
4'h6: branch_taken <= V;
4'h7: branch_taken <= ~V;
4'h8: branch_taken <= C & ~Z;
4'h9: branch_taken <= Z | ~C;
4'ha: branch_taken <= ~(N ^ V);
4'hb: branch_taken <= N ^ V;
4'hc: branch_taken <= (N & ~Z & V ) | (~N & ~Z & ~V);
4'hd: branch_taken <= (N ^ V) & Z;
4'hf: branch_taken <= 1;
endcase
PC_source <= branch_taken & branch_d;
end
endmodule
|
//======================================================================
//
// mkmif_core.v
// ------------
// The actual core module for the Master Key Memory (MKM) interface.
// The interface is implemented to use the Microchip 23K640 serial
// sram as external storage. The core acts as a SPI Master for the
// external memory including SPI clock generation.
//
// The current version of the core does not provide any functionality
// to protect against remanence.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2016, Assured AB.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module mkmif_core(
input wire clk,
input wire reset_n,
output wire spi_sclk,
output wire spi_cs_n,
input wire spi_do,
output wire spi_di,
input wire read_op,
input wire write_op,
input wire init_op,
output wire ready,
output wire valid,
input wire [15 : 0] sclk_div,
input wire [15 : 0] addr,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam SPI_READ_DATA_CMD = 8'h03;
localparam SPI_WRITE_DATA_CMD = 8'h02;
localparam SPI_READ_STATUS_CMD = 8'h05;
localparam SPI_WRITE_STATUS_CMD = 8'h01;
localparam SEQ_MODE_NO_HOLD = 8'b01000001;
localparam CTRL_IDLE = 0;
localparam CTRL_READY = 1;
localparam CTRL_READ = 2;
localparam CTRL_WRITE = 3;
localparam CTRL_INIT = 4;
localparam CTRL_OP_START = 5;
localparam CTRL_OP_WAIT = 6;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg ready_reg;
reg ready_new;
reg ready_we;
reg valid_reg;
reg valid_new;
reg valid_we;
reg [31 : 0] read_data_reg;
reg read_data_we;
reg [3 : 0] mkmif_ctrl_reg;
reg [3 : 0] mkmif_ctrl_new;
reg mkmif_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [31 : 0] spi_read_data;
reg [55 : 0] spi_write_data;
reg spi_set;
reg spi_start;
wire spi_ready;
reg [2 : 0] spi_length;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_reg;
assign valid = valid_reg;
assign read_data = read_data_reg;
//----------------------------------------------------------------
// spi
// The actual spi interfacce
//----------------------------------------------------------------
mkmif_spi spi(
.clk(clk),
.reset_n(reset_n),
.spi_sclk(spi_sclk),
.spi_cs_n(spi_cs_n),
.spi_do(spi_do),
.spi_di(spi_di),
.set(spi_set),
.start(spi_start),
.length(spi_length),
.divisor(sclk_div),
.ready(spi_ready),
.wr_data(spi_write_data),
.rd_data(spi_read_data)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
ready_reg <= 0;
valid_reg <= 0;
read_data_reg <= 32'h0;
mkmif_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (ready_we)
ready_reg <= ready_new;
if (valid_we)
valid_reg <= valid_new;
if (read_data_we)
read_data_reg <= spi_read_data;
if (mkmif_ctrl_we)
mkmif_ctrl_reg <= mkmif_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// mkmif_ctrl
// Main control FSM.
//----------------------------------------------------------------
always @*
begin : mkmif_ctrl
spi_set = 0;
spi_start = 0;
spi_length = 3'h0;
spi_write_data = 56'h0;
read_data_we = 0;
ready_new = 0;
ready_we = 0;
valid_new = 0;
valid_we = 0;
mkmif_ctrl_new = CTRL_IDLE;
mkmif_ctrl_we = 0;
case (mkmif_ctrl_reg)
CTRL_IDLE:
begin
mkmif_ctrl_new = CTRL_INIT;
mkmif_ctrl_we = 1;
end
CTRL_READY:
begin
ready_new = 1;
ready_we = 1;
if (read_op)
begin
ready_new = 0;
ready_we = 1;
valid_new = 0;
valid_we = 1;
mkmif_ctrl_new = CTRL_READ;
mkmif_ctrl_we = 1;
end
if (write_op)
begin
ready_new = 0;
ready_we = 1;
mkmif_ctrl_new = CTRL_WRITE;
mkmif_ctrl_we = 1;
end
if (init_op)
begin
ready_new = 0;
ready_we = 1;
mkmif_ctrl_new = CTRL_INIT;
mkmif_ctrl_we = 1;
end
end
CTRL_READ:
begin
spi_set = 1;
spi_write_data = {SPI_READ_DATA_CMD, addr, 32'h0};
spi_length = 3'h7;
mkmif_ctrl_new = CTRL_OP_START;
mkmif_ctrl_we = 1;
end
CTRL_WRITE:
begin
spi_set = 1;
spi_write_data = {SPI_WRITE_DATA_CMD, addr, write_data};
spi_length = 3'h7;
mkmif_ctrl_new = CTRL_OP_START;
mkmif_ctrl_we = 1;
end
CTRL_INIT:
begin
if (spi_ready)
begin
spi_set = 1;
spi_write_data = {SPI_WRITE_STATUS_CMD, SEQ_MODE_NO_HOLD, 40'h0};
spi_length = 3'h2;
mkmif_ctrl_new = CTRL_OP_START;
mkmif_ctrl_we = 1;
end
end
CTRL_OP_START:
begin
spi_start = 1;
mkmif_ctrl_new = CTRL_OP_WAIT;
mkmif_ctrl_we = 1;
end
CTRL_OP_WAIT:
begin
if (spi_ready)
begin
read_data_we = 1;
valid_new = 1;
valid_we = 1;
mkmif_ctrl_new = CTRL_READY;
mkmif_ctrl_we = 1;
end
end
default:
begin
end
endcase // case (mkmif_ctrl_reg)
end // mkmif_ctrl
endmodule // mkmif
//======================================================================
// EOF mkmif.v
//======================================================================
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 3 17:58:16 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, ack_add_subt, add_subt_dataA,
add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, ack_add_subt, op_add_subt;
wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg,
data_output2_31_, cordic_FSM_state_next_1_, n331, n336, n337, n338,
n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360,
n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371,
n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382,
n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393,
n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624,
n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635,
n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646,
n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:0] cont_iter_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] d_ff_Yn;
wire [31:0] d_ff_Zn;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [30:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n723), .CK(n811), .RN(n1285), .Q(
d_ff1_operation_out), .QN(n1260) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n353), .CK(n1302), .RN(n1280),
.Q(d_ff2_X[23]), .QN(n1259) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n621), .CK(n1326), .RN(n1286), .Q(
d_ff_Yn[31]), .QN(n1258) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n633), .CK(n1324), .RN(n1300), .Q(
d_ff_Yn[19]), .QN(n1257) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n634), .CK(n1326), .RN(n1291), .Q(
d_ff_Yn[18]), .QN(n1256) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n635), .CK(n1329), .RN(n1287), .Q(
d_ff_Yn[17]), .QN(n1255) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n636), .CK(n1331), .RN(n1290), .Q(
d_ff_Yn[16]), .QN(n1254) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n637), .CK(n1334), .RN(n1289), .Q(
d_ff_Yn[15]), .QN(n1253) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n638), .CK(n809), .RN(n1300), .Q(
d_ff_Yn[14]), .QN(n1252) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n639), .CK(n1330), .RN(n1291), .Q(
d_ff_Yn[13]), .QN(n1251) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n640), .CK(n1334), .RN(n1290), .Q(
d_ff_Yn[12]), .QN(n1250) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n641), .CK(n809), .RN(n1287), .Q(
d_ff_Yn[11]), .QN(n1249) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n642), .CK(n1333), .RN(n1289), .Q(
d_ff_Yn[10]), .QN(n1248) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n643), .CK(n809), .RN(n1300), .Q(d_ff_Yn[9]),
.QN(n1247) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n644), .CK(n1330), .RN(n1291), .Q(d_ff_Yn[8]), .QN(n1246) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n645), .CK(n1334), .RN(n1287), .Q(d_ff_Yn[7]), .QN(n1245) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n646), .CK(n1329), .RN(n1290), .Q(d_ff_Yn[6]), .QN(n1244) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n647), .CK(n1330), .RN(n1289), .Q(d_ff_Yn[5]), .QN(n1243) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n648), .CK(n1330), .RN(n1288), .Q(d_ff_Yn[4]), .QN(n1242) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n649), .CK(n1334), .RN(n1288), .Q(d_ff_Yn[3]), .QN(n1241) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n650), .CK(n1333), .RN(n1299), .Q(d_ff_Yn[2]), .QN(n1240) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n651), .CK(n1334), .RN(n1298), .Q(d_ff_Yn[1]), .QN(n1239) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n652), .CK(n1329), .RN(n1293), .Q(d_ff_Yn[0]), .QN(n1238) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n340), .CK(n1307), .RN(n1265), .QN(n1237) );
DFFRX1TS reg_shift_x_Q_reg_29_ ( .D(n339), .CK(n1315), .RN(n1263), .QN(n1236) );
DFFRX1TS reg_LUT_Q_reg_12_ ( .D(n512), .CK(n1313), .RN(n1263), .QN(n1235) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n411), .CK(n805), .RN(n1272),
.Q(d_ff2_Y[29]), .QN(n1234) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n413), .CK(n1310), .RN(n1274),
.Q(d_ff2_Y[27]), .QN(n1233) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n410), .CK(n1301), .RN(n1276),
.Q(d_ff2_Y[30]), .QN(n1232) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n686), .CK(n1334), .RN(n1285), .Q(
sel_mux_2_reg[0]), .QN(n1231) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n412), .CK(n1307), .RN(n1275),
.Q(d_ff2_Y[28]), .QN(n1230) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n417), .CK(n1309), .RN(n1272),
.Q(d_ff2_Y[23]), .QN(n1229) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n351), .CK(n1305), .RN(n1283),
.Q(d_ff2_X[25]), .QN(n1228) );
DFFRX1TS cont_var_count_reg_0_ ( .D(n724), .CK(n811), .RN(n1281), .Q(
cont_var_out[0]), .QN(n1227) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n416), .CK(n1308), .RN(n1275),
.Q(d_ff2_Y[24]), .QN(n1226) );
DFFRX2TS cordic_FSM_state_reg_reg_0_ ( .D(n730), .CK(n1338), .RN(n331), .Q(
cordic_FSM_state_reg[0]), .QN(n1225) );
DFFRX2TS cont_iter_count_reg_3_ ( .D(n725), .CK(n1338), .RN(n1281), .Q(
cont_iter_out[3]), .QN(n1223) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n722), .CK(n811), .RN(n1281), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n1222) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n630), .CK(n806), .RN(n1300), .Q(
d_ff_Yn[22]), .QN(n1221) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n632), .CK(n1328), .RN(n1300), .Q(
d_ff_Yn[20]), .QN(n1220) );
DFFRX1TS d_ff4_Yn_Q_reg_30_ ( .D(n622), .CK(n806), .RN(n1299), .QN(n1219) );
DFFRX2TS cont_var_count_reg_1_ ( .D(n729), .CK(n1305), .RN(n1281), .Q(
cont_var_out[1]), .QN(n1218) );
DFFRX2TS cont_iter_count_reg_1_ ( .D(n727), .CK(n1338), .RN(n1281), .Q(
cont_iter_out[1]), .QN(n1217) );
DFFRX2TS cont_iter_count_reg_0_ ( .D(n728), .CK(n1338), .RN(n1281), .Q(
cont_iter_out[0]), .QN(n1216) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n721), .CK(n811), .RN(n1281), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n1214) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n626), .CK(n1323), .RN(n1286), .Q(
d_ff_Yn[26]), .QN(n1213) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n627), .CK(n1325), .RN(n1291), .Q(
d_ff_Yn[25]), .QN(n1212) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n631), .CK(n1326), .RN(n1287), .Q(
d_ff_Yn[21]), .QN(n1211) );
DFFRX1TS d_ff4_Yn_Q_reg_29_ ( .D(n623), .CK(n1324), .RN(n1292), .QN(n1210)
);
DFFRX1TS d_ff4_Yn_Q_reg_28_ ( .D(n624), .CK(n1325), .RN(n1292), .QN(n1209)
);
DFFRX1TS d_ff4_Yn_Q_reg_27_ ( .D(n625), .CK(n1328), .RN(n1292), .QN(n1208)
);
DFFRX1TS d_ff4_Yn_Q_reg_24_ ( .D(n628), .CK(n1323), .RN(n1294), .QN(n1207)
);
DFFRX1TS d_ff4_Yn_Q_reg_23_ ( .D(n629), .CK(n1323), .RN(n1292), .QN(n1206)
);
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n587), .CK(n806), .RN(n1299), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n585), .CK(n1327), .RN(n1286), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n583), .CK(n1323), .RN(n1293), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n581), .CK(n1327), .RN(n1262), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n579), .CK(n806), .RN(n1271), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n577), .CK(n1325), .RN(n1295), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n575), .CK(n1324), .RN(n1296), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n573), .CK(n1323), .RN(n1296), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n571), .CK(n1323), .RN(n1262), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n569), .CK(n1324), .RN(n1271), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n567), .CK(n1325), .RN(n1295), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n565), .CK(n1326), .RN(n1271), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n563), .CK(n806), .RN(n1295), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n561), .CK(n1328), .RN(n1297), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n559), .CK(n1323), .RN(n1290), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n557), .CK(n1318), .RN(n1289), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n555), .CK(n1320), .RN(n1300), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n553), .CK(n1322), .RN(n1286), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n551), .CK(n1321), .RN(n1293), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n549), .CK(n807), .RN(n1299), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n547), .CK(n1318), .RN(n1299), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n545), .CK(n1319), .RN(n1288), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n543), .CK(n1322), .RN(n1293), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n541), .CK(n1318), .RN(n1288), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n539), .CK(n1318), .RN(n1289), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n537), .CK(n1322), .RN(n1300), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n535), .CK(n1319), .RN(n1291), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n533), .CK(n1321), .RN(n1291), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n531), .CK(n1321), .RN(n1283), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n529), .CK(n1318), .RN(n1261), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n527), .CK(n1318), .RN(n1261), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n525), .CK(n807), .RN(n1261), .Q(
data_output[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n400), .CK(n1306), .RN(n1274), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n336), .CK(n1305), .RN(n1280), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n338), .CK(n1313), .RN(n1273), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n402), .CK(n808), .RN(n1263), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n505), .CK(n1316), .RN(n1263), .Q(
d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n502), .CK(n1315), .RN(n1278), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n720), .CK(n811), .RN(n1270), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n407), .CK(n1314), .RN(n1263), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n406), .CK(n1313), .RN(n1265), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n462), .CK(n1307), .RN(n1295), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n460), .CK(n1310), .RN(n1282), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n458), .CK(n1312), .RN(n1285), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n456), .CK(n805), .RN(n1270), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n454), .CK(n1309), .RN(n1280), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n452), .CK(n1308), .RN(n1283), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n450), .CK(n1309), .RN(n1271), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n448), .CK(n1312), .RN(n1295), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n444), .CK(n1310), .RN(n1296), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n442), .CK(n1311), .RN(n1262), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n440), .CK(n1308), .RN(n1272), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n436), .CK(n1312), .RN(n1275), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n434), .CK(n805), .RN(n1272), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n432), .CK(n1312), .RN(n1276), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n430), .CK(n1311), .RN(n1263), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n428), .CK(n1308), .RN(n1273), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n426), .CK(n1309), .RN(n1284), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n424), .CK(n1310), .RN(n1267), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n422), .CK(n1311), .RN(n1267), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n420), .CK(n1308), .RN(n1272), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n418), .CK(n1312), .RN(n1276), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n719), .CK(n811), .RN(n1285), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n718), .CK(n811), .RN(n1283), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n717), .CK(n811), .RN(n1282), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n716), .CK(n811), .RN(n1285), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n715), .CK(n811), .RN(n1270), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n714), .CK(n813), .RN(n1280), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n713), .CK(n813), .RN(n1283), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n712), .CK(n813), .RN(n1282), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n711), .CK(n813), .RN(n1285), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n710), .CK(n813), .RN(n1270), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n709), .CK(n813), .RN(n1280), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n708), .CK(n813), .RN(n1283), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n707), .CK(n813), .RN(n1282), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n706), .CK(n813), .RN(n1285), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n705), .CK(n813), .RN(n1270), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n704), .CK(n1335), .RN(n1280), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n703), .CK(n1335), .RN(n1283), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n702), .CK(n1335), .RN(n1282), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n701), .CK(n1335), .RN(n1285), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n700), .CK(n1335), .RN(n1270), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n699), .CK(n1335), .RN(n1280), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n698), .CK(n1335), .RN(n1265), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n697), .CK(n1335), .RN(n1267), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n696), .CK(n1335), .RN(n1273), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n695), .CK(n1338), .RN(n1265), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n694), .CK(n1331), .RN(n1265), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n693), .CK(n1334), .RN(n1284), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n692), .CK(n809), .RN(n1284), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n691), .CK(n809), .RN(n1267), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n690), .CK(n1330), .RN(n1267), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n689), .CK(n809), .RN(n1284), .Q(d_ff1_Z[31])
);
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n684), .CK(n1333), .RN(n1287), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n342), .CK(n1316), .RN(n1273), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n398), .CK(n1306), .RN(n1276), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n396), .CK(n1305), .RN(n1274), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n394), .CK(n1304), .RN(n1275), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n392), .CK(n1301), .RN(n1275), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n390), .CK(n1305), .RN(n1272), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n388), .CK(n1303), .RN(n1276), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n386), .CK(n1302), .RN(n1274), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n384), .CK(n1301), .RN(n1275), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n382), .CK(n1302), .RN(n1279), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n380), .CK(n1301), .RN(n1277), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n378), .CK(n1304), .RN(n1278), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n376), .CK(n804), .RN(n1279), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n372), .CK(n1301), .RN(n1278), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n370), .CK(n1302), .RN(n1279), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n368), .CK(n1304), .RN(n1277), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n366), .CK(n804), .RN(n1278), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n364), .CK(n1303), .RN(n1279), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n362), .CK(n1303), .RN(n1277), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n360), .CK(n1305), .RN(n1278), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n358), .CK(n1304), .RN(n1279), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n356), .CK(n804), .RN(n1277), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n354), .CK(n1302), .RN(n1278), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n683), .CK(n809), .RN(n1282), .Q(d_ff_Zn[1])
);
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n682), .CK(n809), .RN(n1285), .Q(d_ff_Zn[2])
);
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n681), .CK(n1330), .RN(n1270), .Q(d_ff_Zn[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n680), .CK(n1333), .RN(n1280), .Q(d_ff_Zn[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n679), .CK(n809), .RN(n1283), .Q(d_ff_Zn[5])
);
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n678), .CK(n1333), .RN(n1282), .Q(d_ff_Zn[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n677), .CK(n1331), .RN(n1298), .Q(d_ff_Zn[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n676), .CK(n1330), .RN(n1288), .Q(d_ff_Zn[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n675), .CK(n809), .RN(n1298), .Q(d_ff_Zn[9])
);
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n674), .CK(n1331), .RN(n1286), .Q(
d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n673), .CK(n1329), .RN(n1288), .Q(
d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n672), .CK(n1333), .RN(n1288), .Q(
d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n671), .CK(n1330), .RN(n1298), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n670), .CK(n1331), .RN(n1293), .Q(
d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n669), .CK(n1329), .RN(n1288), .Q(
d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n668), .CK(n1331), .RN(n1298), .Q(
d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n667), .CK(n1334), .RN(n1300), .Q(
d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n666), .CK(n1330), .RN(n1291), .Q(
d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n665), .CK(n1329), .RN(n1290), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n664), .CK(n1329), .RN(n1287), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n663), .CK(n1331), .RN(n1289), .Q(
d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n662), .CK(n1333), .RN(n1300), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n661), .CK(n1334), .RN(n1291), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n660), .CK(n1329), .RN(n1287), .Q(
d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n659), .CK(n1331), .RN(n1290), .Q(
d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n658), .CK(n1333), .RN(n1289), .Q(
d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n657), .CK(n1334), .RN(n1299), .Q(
d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n656), .CK(n1329), .RN(n1286), .Q(
d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n655), .CK(n1331), .RN(n1286), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n654), .CK(n1330), .RN(n1293), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n653), .CK(n1333), .RN(n1299), .Q(
d_ff_Zn[31]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n344), .CK(n1315), .RN(n1267), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n516), .CK(n807), .RN(n1262), .Q(
d_ff3_LUT_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n408), .CK(n808), .RN(n1279), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n521), .CK(n1320), .RN(n1271), .Q(
d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n514), .CK(n1314), .RN(n1284), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n509), .CK(n1313), .RN(n1263), .Q(
d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n508), .CK(n1314), .RN(n1263), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n507), .CK(n1313), .RN(n1263), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n504), .CK(n1315), .RN(n1277), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n515), .CK(n807), .RN(n1295), .Q(
d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n503), .CK(n808), .RN(n1278), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n517), .CK(n1322), .RN(n1296), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n511), .CK(n1315), .RN(n1273), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n510), .CK(n1316), .RN(n1265), .Q(
d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n506), .CK(n1314), .RN(n1273), .Q(
d_ff3_LUT_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n343), .CK(n808), .RN(n1273), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n438), .CK(n1307), .RN(n1274), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n405), .CK(n1332), .RN(n1284), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(n588), .CK(n1325), .RN(n1298), .Q(
sign_inv_out[0]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n586), .CK(n1328), .RN(n1286), .Q(
sign_inv_out[1]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n584), .CK(n1325), .RN(n1299), .Q(
sign_inv_out[2]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(n582), .CK(n1328), .RN(n1286), .Q(
sign_inv_out[3]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(n580), .CK(n1324), .RN(n1298), .Q(
sign_inv_out[4]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(n578), .CK(n1328), .RN(n1297), .Q(
sign_inv_out[5]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(n576), .CK(n1325), .RN(n1262), .Q(
sign_inv_out[6]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(n574), .CK(n1324), .RN(n1271), .Q(
sign_inv_out[7]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(n572), .CK(n1323), .RN(n1296), .Q(
sign_inv_out[8]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n570), .CK(n806), .RN(n1297), .Q(
sign_inv_out[9]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n568), .CK(n1324), .RN(n1296), .Q(
sign_inv_out[10]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n566), .CK(n1325), .RN(n1262), .Q(
sign_inv_out[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n564), .CK(n1328), .RN(n1271), .Q(
sign_inv_out[12]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n562), .CK(n1326), .RN(n1295), .Q(
sign_inv_out[13]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n560), .CK(n806), .RN(n1291), .Q(
sign_inv_out[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n558), .CK(n1319), .RN(n1287), .Q(
sign_inv_out[15]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(n556), .CK(n1318), .RN(n1290), .Q(
sign_inv_out[16]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n554), .CK(n1318), .RN(n1299), .Q(
sign_inv_out[17]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n552), .CK(n1321), .RN(n1293), .Q(
sign_inv_out[18]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(n550), .CK(n1320), .RN(n1288), .Q(
sign_inv_out[19]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n548), .CK(n807), .RN(n1298), .Q(
sign_inv_out[20]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n546), .CK(n1318), .RN(n1293), .Q(
sign_inv_out[21]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n544), .CK(n1319), .RN(n1293), .Q(
sign_inv_out[22]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n542), .CK(n1321), .RN(n1298), .Q(
sign_inv_out[23]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n540), .CK(n1320), .RN(n1287), .Q(
sign_inv_out[24]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n538), .CK(n1320), .RN(n1290), .Q(
sign_inv_out[25]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n536), .CK(n1322), .RN(n1289), .Q(
sign_inv_out[26]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n534), .CK(n1321), .RN(n1290), .Q(
sign_inv_out[27]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n532), .CK(n1320), .RN(n1297), .Q(
sign_inv_out[28]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(n530), .CK(n807), .RN(n1261), .Q(
sign_inv_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n374), .CK(n1304), .RN(n1277), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n404), .CK(n1317), .RN(n1284), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n520), .CK(n1319), .RN(n1262), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n341), .CK(n1316), .RN(n1265), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n403), .CK(n1327), .RN(n1267), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n500), .CK(n1306), .RN(n1279), .Q(
d_ff3_LUT_out[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n496), .CK(n1316), .RN(n1266),
.Q(d_ff2_Z[0]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n495), .CK(n1314), .RN(n1273),
.Q(d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n494), .CK(n1315), .RN(n1284),
.Q(d_ff2_Z[2]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n493), .CK(n1314), .RN(n1265),
.Q(d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n492), .CK(n1316), .RN(n1266),
.Q(d_ff2_Z[4]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n491), .CK(n1316), .RN(n1273),
.Q(d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n490), .CK(n808), .RN(n1284), .Q(
d_ff2_Z[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n489), .CK(n1314), .RN(n1265),
.Q(d_ff2_Z[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n488), .CK(n1316), .RN(n1267),
.Q(d_ff2_Z[8]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n487), .CK(n1314), .RN(n1266),
.Q(d_ff2_Z[9]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n486), .CK(n1316), .RN(n1266),
.Q(d_ff2_Z[10]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n485), .CK(n1314), .RN(n1266),
.Q(d_ff2_Z[11]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n484), .CK(n808), .RN(n1266),
.Q(d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n483), .CK(n1313), .RN(n1266),
.Q(d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n482), .CK(n1336), .RN(n1266),
.Q(d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n481), .CK(n1313), .RN(n1266),
.Q(d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n480), .CK(n1337), .RN(n1268),
.Q(d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n479), .CK(n1316), .RN(n1268),
.Q(d_ff2_Z[17]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n478), .CK(n808), .RN(n1268),
.Q(d_ff2_Z[18]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n477), .CK(n1314), .RN(n1268),
.Q(d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n476), .CK(n1332), .RN(n1268),
.Q(d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n475), .CK(n1315), .RN(n1268),
.Q(d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n474), .CK(n1313), .RN(n1268),
.Q(d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n470), .CK(n1308), .RN(n1269),
.Q(d_ff2_Z[26]) );
DFFRX1TS reg_shift_x_Q_reg_23_ ( .D(n345), .CK(n1315), .RN(n1273), .Q(
d_ff3_sh_x_out[23]) );
DFFRX1TS reg_LUT_Q_reg_23_ ( .D(n501), .CK(n1336), .RN(n1264), .Q(
d_ff3_LUT_out[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n473), .CK(n1337), .RN(n1268),
.Q(d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n472), .CK(n1313), .RN(n1268),
.Q(d_ff2_Z[24]) );
DFFRX1TS reg_shift_y_Q_reg_23_ ( .D(n409), .CK(n1317), .RN(n1264), .Q(
d_ff3_sh_y_out[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n471), .CK(n1315), .RN(n1268),
.Q(d_ff2_Z[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n469), .CK(n1310), .RN(n1269),
.Q(d_ff2_Z[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n468), .CK(n1311), .RN(n1269),
.Q(d_ff2_Z[28]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n467), .CK(n1309), .RN(n1269),
.Q(d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n466), .CK(n805), .RN(n1269),
.Q(d_ff2_Z[30]) );
DFFRX1TS reg_LUT_Q_reg_25_ ( .D(n499), .CK(n808), .RN(n1264), .Q(
d_ff3_LUT_out[25]) );
DFFRX1TS d_ff5_Q_reg_31_ ( .D(n526), .CK(n1320), .RN(n1261), .Q(
data_output2_31_) );
DFFRX1TS reg_LUT_Q_reg_1_ ( .D(n523), .CK(n1321), .RN(n1296), .Q(
d_ff3_LUT_out[1]) );
DFFRX1TS reg_LUT_Q_reg_2_ ( .D(n522), .CK(n1322), .RN(n1297), .Q(
d_ff3_LUT_out[2]) );
DFFRX1TS reg_LUT_Q_reg_0_ ( .D(n524), .CK(n1321), .RN(n1262), .Q(
d_ff3_LUT_out[0]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n518), .CK(n1319), .RN(n1271), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n464), .CK(n1311), .RN(n1269), .Q(
d_ff3_sign_out) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n399), .CK(n1303), .RN(n1274),
.Q(d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n391), .CK(n1306), .RN(n1276),
.Q(d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n383), .CK(n1301), .RN(n1264),
.Q(d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n381), .CK(n1306), .RN(n1264),
.Q(d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n377), .CK(n1302), .RN(n1264),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n369), .CK(n1303), .RN(n1277),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n363), .CK(n1305), .RN(n1279),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n357), .CK(n1303), .RN(n1277),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n355), .CK(n1306), .RN(n1278),
.Q(d_ff2_X[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n337), .CK(n1301), .RN(n1261),
.Q(d_ff2_X[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n463), .CK(n1309), .RN(n1269),
.Q(d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n461), .CK(n1310), .RN(n1269),
.Q(d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n459), .CK(n1309), .RN(n1280),
.Q(d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n457), .CK(n1308), .RN(n1283),
.Q(d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n455), .CK(n1307), .RN(n1282),
.Q(d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n453), .CK(n1311), .RN(n1270),
.Q(d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n451), .CK(n805), .RN(n1295), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n449), .CK(n1310), .RN(n1296),
.Q(d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n447), .CK(n1309), .RN(n1297),
.Q(d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n445), .CK(n1308), .RN(n1262),
.Q(d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n443), .CK(n1310), .RN(n1271),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n441), .CK(n805), .RN(n1272),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n439), .CK(n1309), .RN(n1276),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n437), .CK(n1311), .RN(n1274),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n435), .CK(n1308), .RN(n1275),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n433), .CK(n1309), .RN(n1272),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n431), .CK(n805), .RN(n1267),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n429), .CK(n1307), .RN(n1263),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n427), .CK(n1311), .RN(n1284),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n425), .CK(n805), .RN(n1266),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n423), .CK(n1311), .RN(n1267),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n421), .CK(n1310), .RN(n1272),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n419), .CK(n805), .RN(n1276),
.Q(d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n401), .CK(n1305), .RN(n1276),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n397), .CK(n804), .RN(n1274), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n395), .CK(n1303), .RN(n1275),
.Q(d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n393), .CK(n1302), .RN(n1274),
.Q(d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n389), .CK(n804), .RN(n1275), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n387), .CK(n1305), .RN(n1272),
.Q(d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n385), .CK(n1303), .RN(n1276),
.Q(d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n379), .CK(n1302), .RN(n1264),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n375), .CK(n804), .RN(n1264),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n373), .CK(n1302), .RN(n1278),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n371), .CK(n1303), .RN(n1279),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n367), .CK(n804), .RN(n1277),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n365), .CK(n1301), .RN(n1278),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n361), .CK(n804), .RN(n1279),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n359), .CK(n1305), .RN(n1277),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_ch_mux_1_Q_reg_0_ ( .D(n687), .CK(n1333), .RN(n1283), .Q(
sel_mux_1_reg) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n597), .CK(n1320), .RN(n1292), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n595), .CK(n1321), .RN(n1294), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n620), .CK(n1325), .RN(n1292), .Q(d_ff_Xn[0]) );
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n616), .CK(n1323), .RN(n1293), .Q(d_ff_Xn[4]) );
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n612), .CK(n806), .RN(n1297), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n611), .CK(n1327), .RN(n1262), .Q(d_ff_Xn[9]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n609), .CK(n1323), .RN(n1271), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n605), .CK(n1328), .RN(n1294), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n602), .CK(n1319), .RN(n1292), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n599), .CK(n1322), .RN(n1299), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n598), .CK(n1320), .RN(n1292), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n590), .CK(n1322), .RN(n1261), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n589), .CK(n1319), .RN(n1261), .Q(
d_ff_Xn[31]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n465), .CK(n1310), .RN(n1269),
.Q(d_ff2_Z[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n619), .CK(n1324), .RN(n1286), .Q(d_ff_Xn[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n618), .CK(n1324), .RN(n1288), .Q(d_ff_Xn[2]) );
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n617), .CK(n1324), .RN(n1298), .Q(d_ff_Xn[3]) );
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n615), .CK(n1325), .RN(n1297), .Q(d_ff_Xn[5]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n614), .CK(n1327), .RN(n1296), .Q(d_ff_Xn[6]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n613), .CK(n1327), .RN(n1269), .Q(d_ff_Xn[7]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n610), .CK(n806), .RN(n1295), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n608), .CK(n806), .RN(n1295), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n607), .CK(n1328), .RN(n1296), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n606), .CK(n1328), .RN(n1294), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n604), .CK(n1321), .RN(n1294), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n603), .CK(n807), .RN(n1294), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n601), .CK(n1320), .RN(n1292), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n600), .CK(n807), .RN(n1292), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n596), .CK(n1322), .RN(n1294), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n594), .CK(n807), .RN(n1294), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n593), .CK(n1319), .RN(n1294), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n592), .CK(n807), .RN(n1289), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n591), .CK(n1322), .RN(n1261), .Q(
d_ff_Xn[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n346), .CK(n1301), .RN(n1282),
.Q(d_ff2_X[30]) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n688), .CK(n1329), .RN(n1282), .Q(
sel_mux_3_reg) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n414), .CK(n1308), .RN(n1274),
.Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n350), .CK(n1302), .RN(n1285),
.Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n415), .CK(n1311), .RN(n1275),
.Q(d_ff2_Y[25]) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n685), .CK(n1331), .RN(n1270), .Q(
sel_mux_2_reg[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n348), .CK(n804), .RN(n1270),
.Q(d_ff2_X[28]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n497), .CK(n1313), .RN(n1264), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n347), .CK(n1301), .RN(n1280),
.Q(d_ff2_X[29]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n352), .CK(n1303), .RN(n1281),
.Q(d_ff2_X[24]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n349), .CK(n804), .RN(n1281),
.Q(d_ff2_X[27]) );
DFFRX2TS cont_iter_count_reg_2_ ( .D(n726), .CK(n1338), .RN(n1281), .Q(
cont_iter_out[2]), .QN(n1224) );
DFFRX1TS reg_LUT_Q_reg_26_ ( .D(n498), .CK(n1315), .RN(n1264), .Q(
d_ff3_LUT_out[26]) );
DFFRX1TS reg_LUT_Q_reg_11_ ( .D(n513), .CK(n808), .RN(n1265), .Q(
d_ff3_LUT_out[11]) );
DFFRX1TS reg_LUT_Q_reg_5_ ( .D(n519), .CK(n1318), .RN(n1297), .Q(
d_ff3_LUT_out[5]) );
DFFRX4TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(
n1338), .RN(n331), .Q(cordic_FSM_state_reg[1]) );
DFFRX2TS cordic_FSM_state_reg_reg_3_ ( .D(n732), .CK(n1338), .RN(n331), .Q(
cordic_FSM_state_reg[3]), .QN(n799) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n528), .CK(n1319), .RN(n1261), .Q(
sign_inv_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n446), .CK(n805), .RN(n1297), .Q(
d_ff3_sh_y_out[8]) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n731), .CK(n1338), .RN(n331), .Q(
cordic_FSM_state_reg[2]), .QN(n1215) );
CLKBUFX3TS U795 ( .A(n985), .Y(n998) );
OAI32X1TS U796 ( .A0(cont_iter_out[2]), .A1(n1112), .A2(n1166), .B0(n831),
.B1(n1224), .Y(n726) );
AO22XLTS U797 ( .A0(d_ff_Yn[20]), .A1(n1100), .B0(d_ff2_Y[20]), .B1(n1133),
.Y(n423) );
AO22XLTS U798 ( .A0(d_ff_Yn[19]), .A1(n1100), .B0(d_ff2_Y[19]), .B1(n1133),
.Y(n425) );
AO22XLTS U799 ( .A0(n1053), .A1(data_in[0]), .B0(n1167), .B1(d_ff1_Z[0]),
.Y(n720) );
OR3X1TS U800 ( .A(n1215), .B(n799), .C(n821), .Y(n798) );
CLKBUFX3TS U801 ( .A(n983), .Y(n980) );
CLKBUFX3TS U802 ( .A(n1199), .Y(n1195) );
CLKBUFX2TS U803 ( .A(clk), .Y(n836) );
CLKBUFX3TS U804 ( .A(n818), .Y(n817) );
CLKBUFX3TS U805 ( .A(n1172), .Y(n818) );
BUFX3TS U806 ( .A(n818), .Y(n816) );
BUFX3TS U807 ( .A(n816), .Y(n830) );
INVX2TS U808 ( .A(n1193), .Y(n1099) );
CLKBUFX3TS U809 ( .A(n1090), .Y(n1193) );
INVX2TS U810 ( .A(cordic_FSM_state_reg[3]), .Y(n800) );
INVX2TS U811 ( .A(n1193), .Y(n801) );
INVX2TS U812 ( .A(n1193), .Y(n802) );
AOI222X1TS U813 ( .A0(n1010), .A1(d_ff3_LUT_out[8]), .B0(n1151), .B1(
d_ff3_sh_x_out[8]), .C0(n1017), .C1(d_ff3_sh_y_out[8]), .Y(n1011) );
CLKBUFX3TS U814 ( .A(n983), .Y(n1010) );
NOR4X1TS U815 ( .A(cordic_FSM_state_reg[1]), .B(n1215), .C(n1225), .D(n799),
.Y(ready_cordic) );
INVX2TS U816 ( .A(n798), .Y(n803) );
CLKBUFX3TS U817 ( .A(n980), .Y(n988) );
OAI2BB2X2TS U818 ( .B0(n1217), .B1(d_ff2_X[24]), .A0N(n1146), .A1N(n1144),
.Y(n1103) );
NOR2X2TS U819 ( .A(d_ff2_X[23]), .B(n1216), .Y(n1146) );
NOR2X2TS U820 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[3]),
.Y(n1044) );
CLKINVX3TS U821 ( .A(n1108), .Y(n1205) );
CLKBUFX3TS U822 ( .A(n1132), .Y(n1108) );
AOI222X4TS U823 ( .A0(n882), .A1(d_ff2_Z[6]), .B0(n870), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n894), .Y(n864) );
AOI222X1TS U824 ( .A0(n899), .A1(d_ff2_Z[21]), .B0(n885), .B1(d_ff1_Z[21]),
.C0(d_ff_Zn[21]), .C1(n894), .Y(n886) );
AOI222X1TS U825 ( .A0(n899), .A1(d_ff2_Z[25]), .B0(n902), .B1(d_ff1_Z[25]),
.C0(d_ff_Zn[25]), .C1(n894), .Y(n895) );
CLKINVX3TS U826 ( .A(n1194), .Y(n894) );
CLKINVX3TS U827 ( .A(n1195), .Y(n901) );
CLKINVX3TS U828 ( .A(n998), .Y(n1154) );
AOI222X1TS U829 ( .A0(n1067), .A1(d_ff2_Z[9]), .B0(n874), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n894), .Y(n867) );
AOI222X4TS U830 ( .A0(n1067), .A1(d_ff2_Z[8]), .B0(n870), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n898), .Y(n866) );
AOI222X1TS U831 ( .A0(n1067), .A1(d_ff2_Z[7]), .B0(n874), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n894), .Y(n865) );
AOI222X1TS U832 ( .A0(n1067), .A1(d_ff2_Z[5]), .B0(n874), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n894), .Y(n863) );
AOI222X4TS U833 ( .A0(n1067), .A1(d_ff2_Z[4]), .B0(n870), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n894), .Y(n862) );
AOI222X1TS U834 ( .A0(n1067), .A1(d_ff2_Z[3]), .B0(n874), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n894), .Y(n861) );
AOI222X4TS U835 ( .A0(n1067), .A1(d_ff2_Z[2]), .B0(n870), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n1092), .Y(n860) );
AOI222X1TS U836 ( .A0(n1067), .A1(d_ff2_Z[1]), .B0(n870), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n1092), .Y(n859) );
AOI222X1TS U837 ( .A0(n801), .A1(d_ff2_Z[0]), .B0(n901), .B1(d_ff_Zn[0]),
.C0(n870), .C1(d_ff1_Z[0]), .Y(n858) );
NAND2X2TS U838 ( .A(cont_iter_out[2]), .B(n1189), .Y(n1105) );
CLKINVX3TS U839 ( .A(n1108), .Y(n1189) );
NAND2X2TS U840 ( .A(n1217), .B(n1223), .Y(n1094) );
NOR2X2TS U841 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[3]),
.Y(n1135) );
CLKBUFX3TS U842 ( .A(n937), .Y(n928) );
NAND3X2TS U843 ( .A(n1157), .B(cordic_FSM_state_reg[0]), .C(
cordic_FSM_state_reg[3]), .Y(n937) );
CLKINVX3TS U844 ( .A(n830), .Y(n1290) );
CLKINVX3TS U845 ( .A(n830), .Y(n1289) );
CLKINVX3TS U846 ( .A(n830), .Y(n1287) );
CLKINVX3TS U847 ( .A(n830), .Y(n1291) );
CLKINVX3TS U848 ( .A(n830), .Y(n1300) );
CLKINVX3TS U849 ( .A(n816), .Y(n1292) );
CLKINVX3TS U850 ( .A(n816), .Y(n1298) );
CLKINVX3TS U851 ( .A(n816), .Y(n1288) );
CLKINVX3TS U852 ( .A(n816), .Y(n1293) );
CLKINVX3TS U853 ( .A(n830), .Y(n1270) );
CLKINVX3TS U854 ( .A(n816), .Y(n1285) );
CLKINVX3TS U855 ( .A(n816), .Y(n1266) );
CLKINVX3TS U856 ( .A(n817), .Y(n1263) );
CLKINVX3TS U857 ( .A(n830), .Y(n1284) );
CLKINVX3TS U858 ( .A(n818), .Y(n1273) );
CLKINVX3TS U859 ( .A(n817), .Y(n1297) );
CLKINVX3TS U860 ( .A(n830), .Y(n1294) );
CLKINVX3TS U861 ( .A(n817), .Y(n1296) );
CLKINVX3TS U862 ( .A(n1172), .Y(n1261) );
CLKINVX3TS U863 ( .A(n815), .Y(n1264) );
CLKINVX3TS U864 ( .A(n815), .Y(n1278) );
CLKINVX3TS U865 ( .A(n815), .Y(n1279) );
CLKINVX3TS U866 ( .A(n815), .Y(n1277) );
CLKINVX3TS U867 ( .A(n816), .Y(n1299) );
CLKINVX3TS U868 ( .A(n816), .Y(n1286) );
CLKINVX3TS U869 ( .A(n818), .Y(n1272) );
CLKINVX3TS U870 ( .A(n817), .Y(n1269) );
CLKINVX3TS U871 ( .A(n817), .Y(n1262) );
CLKINVX3TS U872 ( .A(n817), .Y(n1271) );
CLKINVX3TS U873 ( .A(n817), .Y(n1295) );
CLKINVX3TS U874 ( .A(n817), .Y(n1267) );
CLKINVX3TS U875 ( .A(n815), .Y(n1265) );
CLKINVX3TS U876 ( .A(n818), .Y(n1268) );
CLKINVX3TS U877 ( .A(n818), .Y(n1276) );
CLKINVX3TS U878 ( .A(n818), .Y(n1274) );
CLKINVX3TS U879 ( .A(n818), .Y(n1275) );
INVX3TS U880 ( .A(n830), .Y(n1281) );
CLKINVX3TS U881 ( .A(n817), .Y(n1283) );
CLKINVX3TS U882 ( .A(n818), .Y(n1282) );
BUFX3TS U883 ( .A(n833), .Y(n1306) );
CLKINVX6TS U884 ( .A(n812), .Y(n804) );
BUFX6TS U885 ( .A(n833), .Y(n1305) );
BUFX6TS U886 ( .A(n833), .Y(n1301) );
BUFX6TS U887 ( .A(n833), .Y(n1302) );
BUFX6TS U888 ( .A(n833), .Y(n1303) );
BUFX3TS U889 ( .A(n835), .Y(n1307) );
CLKINVX6TS U890 ( .A(n810), .Y(n805) );
BUFX6TS U891 ( .A(n835), .Y(n1308) );
BUFX6TS U892 ( .A(n835), .Y(n1311) );
BUFX6TS U893 ( .A(n835), .Y(n1310) );
BUFX6TS U894 ( .A(n835), .Y(n1309) );
BUFX3TS U895 ( .A(n832), .Y(n1327) );
CLKINVX6TS U896 ( .A(n812), .Y(n806) );
BUFX6TS U897 ( .A(n832), .Y(n1325) );
BUFX6TS U898 ( .A(n832), .Y(n1328) );
BUFX6TS U899 ( .A(n832), .Y(n1323) );
BUFX6TS U900 ( .A(n832), .Y(n1324) );
CLKINVX6TS U901 ( .A(n810), .Y(n807) );
CLKBUFX2TS U902 ( .A(n834), .Y(n1317) );
BUFX6TS U903 ( .A(n834), .Y(n1318) );
BUFX6TS U904 ( .A(n834), .Y(n1319) );
BUFX6TS U905 ( .A(n834), .Y(n1320) );
BUFX6TS U906 ( .A(n834), .Y(n1321) );
BUFX6TS U907 ( .A(n834), .Y(n1322) );
BUFX4TS U908 ( .A(n836), .Y(n808) );
BUFX6TS U909 ( .A(n836), .Y(n1315) );
BUFX6TS U910 ( .A(n836), .Y(n1316) );
BUFX6TS U911 ( .A(n836), .Y(n1313) );
BUFX6TS U912 ( .A(n836), .Y(n1314) );
CLKINVX6TS U913 ( .A(n810), .Y(n809) );
CLKBUFX2TS U914 ( .A(clk), .Y(n1332) );
BUFX6TS U915 ( .A(n1317), .Y(n1330) );
BUFX6TS U916 ( .A(n836), .Y(n1331) );
BUFX6TS U917 ( .A(n1312), .Y(n1329) );
BUFX6TS U918 ( .A(n1304), .Y(n1334) );
BUFX6TS U919 ( .A(n1326), .Y(n1333) );
INVX2TS U920 ( .A(n1337), .Y(n810) );
CLKINVX6TS U921 ( .A(n810), .Y(n811) );
CLKBUFX2TS U922 ( .A(clk), .Y(n1337) );
INVX2TS U923 ( .A(n1336), .Y(n812) );
CLKINVX6TS U924 ( .A(n812), .Y(n813) );
CLKBUFX2TS U925 ( .A(clk), .Y(n1336) );
NAND3X2TS U926 ( .A(cordic_FSM_state_reg[2]), .B(n1158), .C(n799), .Y(n1133)
);
NOR2X4TS U927 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.Y(n1158) );
AOI222X4TS U928 ( .A0(d_ff3_LUT_out[24]), .A1(n1005), .B0(d_ff3_sh_y_out[24]), .B1(n1021), .C0(d_ff3_sh_x_out[24]), .C1(n975), .Y(n990) );
AOI221X4TS U929 ( .A0(n1087), .A1(n1205), .B0(d_ff3_LUT_out[24]), .B1(n1203),
.C0(n1082), .Y(n1084) );
NOR2BX2TS U930 ( .AN(n1027), .B(n1026), .Y(n1028) );
NOR3X1TS U931 ( .A(n1159), .B(cont_var_out[0]), .C(n1218), .Y(n1027) );
NOR2X2TS U932 ( .A(d_ff2_Y[23]), .B(n1216), .Y(n1125) );
CLKBUFX3TS U933 ( .A(n1062), .Y(n1052) );
CLKBUFX3TS U934 ( .A(n1149), .Y(n1129) );
CLKBUFX3TS U935 ( .A(n1049), .Y(n1042) );
CLKINVX3TS U936 ( .A(n998), .Y(n1012) );
CLKINVX3TS U937 ( .A(n1194), .Y(n898) );
CLKBUFX3TS U938 ( .A(n1195), .Y(n1194) );
CLKBUFX3TS U939 ( .A(n837), .Y(n983) );
CLKBUFX3TS U940 ( .A(n1101), .Y(n1192) );
CLKINVX3TS U941 ( .A(n1193), .Y(n882) );
CLKINVX3TS U942 ( .A(n1193), .Y(n899) );
CLKINVX3TS U943 ( .A(n830), .Y(n1280) );
BUFX4TS U944 ( .A(clk), .Y(n1335) );
BUFX4TS U945 ( .A(clk), .Y(n1338) );
INVX2TS U946 ( .A(n1224), .Y(n814) );
AOI222X1TS U947 ( .A0(cont_iter_out[2]), .A1(n1103), .B0(n814), .B1(n1228),
.C0(n1103), .C1(n1228), .Y(n1063) );
AOI222X4TS U948 ( .A0(n1114), .A1(cont_iter_out[2]), .B0(n1114), .B1(n1216),
.C0(cont_iter_out[3]), .C1(n1224), .Y(n1186) );
OAI211X2TS U949 ( .A0(n814), .A1(n1094), .B0(n1205), .C0(n1188), .Y(n1190)
);
NOR4X4TS U950 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[1]),
.C(n1225), .D(n799), .Y(ack_add_subt) );
OAI21XLTS U951 ( .A0(n1085), .A1(n1229), .B0(n893), .Y(n409) );
OAI21XLTS U952 ( .A0(n1209), .A1(n918), .B0(n853), .Y(n532) );
OAI21XLTS U953 ( .A0(n1251), .A1(n944), .B0(n943), .Y(n562) );
OAI21XLTS U954 ( .A0(n1235), .A1(n840), .B0(n839), .Y(add_subt_dataB[12]) );
OAI21XLTS U955 ( .A0(n1237), .A1(n985), .B0(n984), .Y(add_subt_dataB[28]) );
OAI21XLTS U956 ( .A0(n1229), .A1(n985), .B0(n951), .Y(add_subt_dataA[23]) );
OAI21XLTS U957 ( .A0(n1230), .A1(n985), .B0(n954), .Y(add_subt_dataA[28]) );
AND3X1TS U958 ( .A(n1158), .B(n1215), .C(n800), .Y(n1172) );
CLKBUFX2TS U959 ( .A(n816), .Y(n815) );
NAND2X2TS U960 ( .A(cont_iter_out[0]), .B(cont_iter_out[1]), .Y(n1112) );
NAND2X2TS U961 ( .A(cont_iter_out[2]), .B(cont_iter_out[3]), .Y(n1188) );
NOR2X2TS U962 ( .A(n1112), .B(n1188), .Y(n1159) );
INVX2TS U963 ( .A(n1159), .Y(n1065) );
XNOR2X1TS U964 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out),
.Y(n819) );
XOR2X1TS U965 ( .A(d_ff1_shift_region_flag_out[0]), .B(n819), .Y(n916) );
NOR2X1TS U966 ( .A(n916), .B(n1065), .Y(n828) );
AOI21X1TS U967 ( .A0(cont_var_out[0]), .A1(n1065), .B0(n828), .Y(n1171) );
NAND4X1TS U968 ( .A(cordic_FSM_state_reg[3]), .B(n1158), .C(ready_add_subt),
.D(n1215), .Y(n1026) );
NOR2XLTS U969 ( .A(n1171), .B(n1026), .Y(n820) );
CLKBUFX2TS U970 ( .A(n820), .Y(n824) );
CLKBUFX2TS U971 ( .A(n824), .Y(n1174) );
CLKBUFX3TS U972 ( .A(n1174), .Y(n1176) );
OAI2BB2XLTS U973 ( .B0(n1176), .B1(n1240), .A0N(n824), .A1N(
result_add_subt[2]), .Y(n650) );
CLKBUFX2TS U974 ( .A(n1174), .Y(n826) );
OAI2BB2XLTS U975 ( .B0(n1176), .B1(n1238), .A0N(n826), .A1N(
result_add_subt[0]), .Y(n652) );
CLKBUFX3TS U976 ( .A(n826), .Y(n1175) );
OAI2BB2XLTS U977 ( .B0(n1175), .B1(n1241), .A0N(n824), .A1N(
result_add_subt[3]), .Y(n649) );
OAI2BB2XLTS U978 ( .B0(n1175), .B1(n1239), .A0N(n826), .A1N(
result_add_subt[1]), .Y(n651) );
OAI2BB2XLTS U979 ( .B0(n1175), .B1(n1242), .A0N(n824), .A1N(
result_add_subt[4]), .Y(n648) );
INVX2TS U980 ( .A(n1158), .Y(n821) );
INVX2TS U981 ( .A(n803), .Y(n1062) );
CLKBUFX2TS U982 ( .A(n1062), .Y(n1068) );
INVX2TS U983 ( .A(n1068), .Y(n1038) );
OAI33X1TS U984 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n1222), .B0(n1214), .B1(n1260), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n822) );
XOR2XLTS U985 ( .A(data_output2_31_), .B(n822), .Y(n823) );
AO22XLTS U986 ( .A0(n1038), .A1(n823), .B0(n798), .B1(data_output[31]), .Y(
n525) );
CLKBUFX3TS U987 ( .A(n1174), .Y(n1177) );
OAI2BB2XLTS U988 ( .B0(n1177), .B1(n1258), .A0N(n826), .A1N(
result_add_subt[31]), .Y(n621) );
CLKBUFX3TS U989 ( .A(n824), .Y(n1179) );
OAI2BB2XLTS U990 ( .B0(n1179), .B1(n1207), .A0N(n1174), .A1N(
result_add_subt[24]), .Y(n628) );
OAI2BB2XLTS U991 ( .B0(n1179), .B1(n1208), .A0N(n826), .A1N(
result_add_subt[27]), .Y(n625) );
OAI2BB2XLTS U992 ( .B0(n1179), .B1(n1209), .A0N(n824), .A1N(
result_add_subt[28]), .Y(n624) );
OAI2BB2XLTS U993 ( .B0(n1179), .B1(n1210), .A0N(n1174), .A1N(
result_add_subt[29]), .Y(n623) );
OAI2BB2XLTS U994 ( .B0(n1179), .B1(n1211), .A0N(n1174), .A1N(
result_add_subt[21]), .Y(n631) );
OAI2BB2XLTS U995 ( .B0(n1179), .B1(n1212), .A0N(n826), .A1N(
result_add_subt[25]), .Y(n627) );
OAI2BB2XLTS U996 ( .B0(n1179), .B1(n1213), .A0N(n824), .A1N(
result_add_subt[26]), .Y(n626) );
NAND2X1TS U997 ( .A(n1215), .B(cordic_FSM_state_reg[1]), .Y(n1048) );
INVX2TS U998 ( .A(n1048), .Y(n1157) );
NAND2X1TS U999 ( .A(n1157), .B(n1044), .Y(n825) );
INVX2TS U1000 ( .A(n825), .Y(n1050) );
CLKBUFX2TS U1001 ( .A(n1050), .Y(n1049) );
INVX2TS U1002 ( .A(n1050), .Y(n1055) );
AO22XLTS U1003 ( .A0(n1049), .A1(data_in[21]), .B0(n1055), .B1(d_ff1_Z[21]),
.Y(n699) );
AO22XLTS U1004 ( .A0(n1049), .A1(data_in[22]), .B0(n1055), .B1(d_ff1_Z[22]),
.Y(n698) );
OAI2BB2XLTS U1005 ( .B0(n1179), .B1(n1219), .A0N(n826), .A1N(
result_add_subt[30]), .Y(n622) );
AOI21X1TS U1006 ( .A0(n1227), .A1(n1218), .B0(n1159), .Y(n827) );
OR3X2TS U1007 ( .A(n828), .B(n827), .C(n1026), .Y(n1149) );
CLKBUFX2TS U1008 ( .A(n1149), .Y(n1139) );
INVX2TS U1009 ( .A(n1139), .Y(n829) );
CLKBUFX2TS U1010 ( .A(n1149), .Y(n1141) );
AO22XLTS U1011 ( .A0(n829), .A1(result_add_subt[31]), .B0(n1141), .B1(
d_ff_Xn[31]), .Y(n589) );
AO22XLTS U1012 ( .A0(n829), .A1(result_add_subt[30]), .B0(n1141), .B1(
d_ff_Xn[30]), .Y(n590) );
INVX2TS U1013 ( .A(n1133), .Y(n1198) );
CLKBUFX3TS U1014 ( .A(n1198), .Y(n1090) );
CLKBUFX3TS U1015 ( .A(n1090), .Y(n1200) );
NAND2X1TS U1016 ( .A(n1198), .B(sel_mux_1_reg), .Y(n1199) );
CLKBUFX3TS U1017 ( .A(n1195), .Y(n1197) );
OA22X1TS U1018 ( .A0(n1200), .A1(d_ff2_X[20]), .B0(d_ff_Xn[20]), .B1(n1197),
.Y(n359) );
OA22X1TS U1019 ( .A0(n1200), .A1(d_ff2_X[19]), .B0(d_ff_Xn[19]), .B1(n1197),
.Y(n361) );
OA22X1TS U1020 ( .A0(n1200), .A1(d_ff2_X[17]), .B0(d_ff_Xn[17]), .B1(n1197),
.Y(n365) );
OA22X1TS U1021 ( .A0(n1200), .A1(d_ff2_X[16]), .B0(d_ff_Xn[16]), .B1(n1197),
.Y(n367) );
OA22X1TS U1022 ( .A0(n1200), .A1(d_ff2_X[14]), .B0(d_ff_Xn[14]), .B1(n1197),
.Y(n371) );
OA22X1TS U1023 ( .A0(n1090), .A1(d_ff2_X[13]), .B0(d_ff_Xn[13]), .B1(n1197),
.Y(n373) );
CLKBUFX2TS U1024 ( .A(n1195), .Y(n1196) );
OA22X1TS U1025 ( .A0(n1090), .A1(d_ff2_X[6]), .B0(d_ff_Xn[6]), .B1(n1196),
.Y(n387) );
OA22X1TS U1026 ( .A0(n1090), .A1(d_ff2_X[3]), .B0(d_ff_Xn[3]), .B1(n1196),
.Y(n393) );
OA22X1TS U1027 ( .A0(n1193), .A1(d_ff2_X[2]), .B0(d_ff_Xn[2]), .B1(n1196),
.Y(n395) );
OA22X1TS U1028 ( .A0(n1090), .A1(d_ff2_X[1]), .B0(d_ff_Xn[1]), .B1(n1195),
.Y(n397) );
OA22X1TS U1029 ( .A0(n1200), .A1(d_ff2_X[26]), .B0(d_ff_Xn[26]), .B1(n1197),
.Y(n350) );
OA22X1TS U1030 ( .A0(n1193), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n1194),
.Y(n348) );
OA22X1TS U1031 ( .A0(n1193), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n1197),
.Y(n347) );
OA22X1TS U1032 ( .A0(d_ff2_X[24]), .A1(n1090), .B0(d_ff_Xn[24]), .B1(n1197),
.Y(n352) );
NAND2X2TS U1033 ( .A(ack_add_subt), .B(n1027), .Y(n1166) );
INVX2TS U1034 ( .A(n1053), .Y(n1167) );
OAI21XLTS U1035 ( .A0(n1112), .A1(n1166), .B0(n1167), .Y(n831) );
CLKBUFX2TS U1036 ( .A(clk), .Y(n832) );
CLKBUFX2TS U1037 ( .A(clk), .Y(n834) );
BUFX3TS U1038 ( .A(n832), .Y(n1326) );
CLKBUFX2TS U1039 ( .A(clk), .Y(n833) );
BUFX3TS U1040 ( .A(n833), .Y(n1304) );
CLKBUFX2TS U1041 ( .A(clk), .Y(n835) );
BUFX3TS U1042 ( .A(n835), .Y(n1312) );
NOR2X1TS U1043 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .Y(n986) );
CLKBUFX2TS U1044 ( .A(n986), .Y(n1003) );
CLKBUFX2TS U1045 ( .A(n1003), .Y(n979) );
CLKBUFX2TS U1046 ( .A(n979), .Y(n1152) );
NAND2X1TS U1047 ( .A(n1231), .B(sel_mux_2_reg[1]), .Y(n840) );
INVX2TS U1048 ( .A(n840), .Y(n837) );
OR2X2TS U1049 ( .A(n1231), .B(sel_mux_2_reg[1]), .Y(n985) );
AOI22X1TS U1050 ( .A0(d_ff2_Z[25]), .A1(n983), .B0(d_ff2_Y[25]), .B1(n1151),
.Y(n838) );
OAI2BB1X1TS U1051 ( .A0N(d_ff2_X[25]), .A1N(n1152), .B0(n838), .Y(
add_subt_dataA[25]) );
CLKBUFX3TS U1052 ( .A(n979), .Y(n1153) );
AOI22X1TS U1053 ( .A0(n1154), .A1(d_ff3_sh_x_out[12]), .B0(n1153), .B1(
d_ff3_sh_y_out[12]), .Y(n839) );
INVX2TS U1054 ( .A(rst), .Y(n331) );
NAND3X1TS U1055 ( .A(cont_iter_out[1]), .B(cont_iter_out[0]), .C(n1223), .Y(
n1081) );
NAND2X1TS U1056 ( .A(cont_iter_out[3]), .B(n1167), .Y(n841) );
OAI31X1TS U1057 ( .A0(n1166), .A1(n1224), .A2(n1081), .B0(n841), .Y(n725) );
NAND2BX1TS U1058 ( .AN(n928), .B(sel_mux_3_reg), .Y(n856) );
CLKBUFX2TS U1059 ( .A(n856), .Y(n918) );
CLKBUFX3TS U1060 ( .A(n918), .Y(n944) );
NOR2X2TS U1061 ( .A(sel_mux_3_reg), .B(n937), .Y(n919) );
CLKBUFX2TS U1062 ( .A(n919), .Y(n854) );
CLKBUFX3TS U1063 ( .A(n854), .Y(n942) );
CLKBUFX3TS U1064 ( .A(n928), .Y(n941) );
AOI22X1TS U1065 ( .A0(d_ff_Xn[18]), .A1(n942), .B0(sign_inv_out[18]), .B1(
n941), .Y(n842) );
OAI21XLTS U1066 ( .A0(n1256), .A1(n944), .B0(n842), .Y(n552) );
AOI22X1TS U1067 ( .A0(d_ff_Xn[19]), .A1(n942), .B0(sign_inv_out[19]), .B1(
n941), .Y(n843) );
OAI21XLTS U1068 ( .A0(n1257), .A1(n944), .B0(n843), .Y(n550) );
AOI22X1TS U1069 ( .A0(d_ff_Xn[20]), .A1(n919), .B0(sign_inv_out[20]), .B1(
n941), .Y(n844) );
OAI21XLTS U1070 ( .A0(n1220), .A1(n918), .B0(n844), .Y(n548) );
CLKBUFX2TS U1071 ( .A(n856), .Y(n908) );
AOI22X1TS U1072 ( .A0(d_ff_Xn[21]), .A1(n919), .B0(sign_inv_out[21]), .B1(
n941), .Y(n845) );
OAI21XLTS U1073 ( .A0(n1211), .A1(n908), .B0(n845), .Y(n546) );
CLKBUFX2TS U1074 ( .A(n854), .Y(n906) );
CLKBUFX3TS U1075 ( .A(n928), .Y(n905) );
AOI22X1TS U1076 ( .A0(d_ff_Xn[22]), .A1(n906), .B0(sign_inv_out[22]), .B1(
n905), .Y(n846) );
OAI21XLTS U1077 ( .A0(n1221), .A1(n918), .B0(n846), .Y(n544) );
AOI22X1TS U1078 ( .A0(d_ff_Xn[23]), .A1(n854), .B0(sign_inv_out[23]), .B1(
n905), .Y(n847) );
OAI21XLTS U1079 ( .A0(n1206), .A1(n908), .B0(n847), .Y(n542) );
AOI22X1TS U1080 ( .A0(d_ff_Xn[24]), .A1(n906), .B0(sign_inv_out[24]), .B1(
n905), .Y(n848) );
OAI21XLTS U1081 ( .A0(n1207), .A1(n918), .B0(n848), .Y(n540) );
AOI22X1TS U1082 ( .A0(d_ff_Xn[25]), .A1(n854), .B0(sign_inv_out[25]), .B1(
n905), .Y(n849) );
OAI21XLTS U1083 ( .A0(n1212), .A1(n908), .B0(n849), .Y(n538) );
NOR2X1TS U1084 ( .A(sel_mux_1_reg), .B(n801), .Y(n872) );
CLKBUFX2TS U1085 ( .A(n872), .Y(n874) );
CLKBUFX3TS U1086 ( .A(n874), .Y(n902) );
AOI222X1TS U1087 ( .A0(n801), .A1(d_ff2_Z[31]), .B0(n902), .B1(d_ff1_Z[31]),
.C0(d_ff_Zn[31]), .C1(n901), .Y(n850) );
INVX2TS U1088 ( .A(n850), .Y(n465) );
AOI22X1TS U1089 ( .A0(d_ff_Xn[26]), .A1(n906), .B0(sign_inv_out[26]), .B1(
n905), .Y(n851) );
OAI21XLTS U1090 ( .A0(n1213), .A1(n918), .B0(n851), .Y(n536) );
AOI22X1TS U1091 ( .A0(d_ff_Xn[27]), .A1(n854), .B0(sign_inv_out[27]), .B1(
n905), .Y(n852) );
OAI21XLTS U1092 ( .A0(n1208), .A1(n908), .B0(n852), .Y(n534) );
AOI22X1TS U1093 ( .A0(d_ff_Xn[28]), .A1(n906), .B0(sign_inv_out[28]), .B1(
n905), .Y(n853) );
AOI22X1TS U1094 ( .A0(d_ff_Xn[29]), .A1(n854), .B0(sign_inv_out[29]), .B1(
n905), .Y(n855) );
OAI21XLTS U1095 ( .A0(n1210), .A1(n856), .B0(n855), .Y(n530) );
AOI22X1TS U1096 ( .A0(d_ff_Xn[30]), .A1(n906), .B0(sign_inv_out[30]), .B1(
n905), .Y(n857) );
OAI21XLTS U1097 ( .A0(n1219), .A1(n908), .B0(n857), .Y(n528) );
INVX2TS U1098 ( .A(n1090), .Y(n1067) );
CLKBUFX2TS U1099 ( .A(n874), .Y(n870) );
INVX2TS U1100 ( .A(n858), .Y(n496) );
INVX2TS U1101 ( .A(n1194), .Y(n1092) );
INVX2TS U1102 ( .A(n859), .Y(n495) );
INVX2TS U1103 ( .A(n860), .Y(n494) );
INVX2TS U1104 ( .A(n861), .Y(n493) );
INVX2TS U1105 ( .A(n862), .Y(n492) );
INVX2TS U1106 ( .A(n863), .Y(n491) );
INVX2TS U1107 ( .A(n864), .Y(n490) );
INVX2TS U1108 ( .A(n865), .Y(n489) );
INVX2TS U1109 ( .A(n866), .Y(n488) );
INVX2TS U1110 ( .A(n867), .Y(n487) );
NOR3X1TS U1111 ( .A(cont_iter_out[0]), .B(cont_iter_out[2]), .C(n1094), .Y(
n909) );
NAND3XLTS U1112 ( .A(cordic_FSM_state_reg[0]), .B(n1157), .C(n800), .Y(n869)
);
NAND3XLTS U1113 ( .A(n869), .B(sel_mux_1_reg), .C(n1287), .Y(n868) );
OAI21XLTS U1114 ( .A0(n909), .A1(n869), .B0(n868), .Y(n687) );
AOI222X1TS U1115 ( .A0(n882), .A1(d_ff2_Z[10]), .B0(n870), .B1(d_ff1_Z[10]),
.C0(d_ff_Zn[10]), .C1(n901), .Y(n871) );
INVX2TS U1116 ( .A(n871), .Y(n486) );
AOI222X1TS U1117 ( .A0(n882), .A1(d_ff2_Z[11]), .B0(n872), .B1(d_ff1_Z[11]),
.C0(d_ff_Zn[11]), .C1(n898), .Y(n873) );
INVX2TS U1118 ( .A(n873), .Y(n485) );
CLKBUFX3TS U1119 ( .A(n874), .Y(n885) );
AOI222X1TS U1120 ( .A0(n882), .A1(d_ff2_Z[12]), .B0(n885), .B1(d_ff1_Z[12]),
.C0(d_ff_Zn[12]), .C1(n898), .Y(n875) );
INVX2TS U1121 ( .A(n875), .Y(n484) );
AOI222X1TS U1122 ( .A0(n882), .A1(d_ff2_Z[13]), .B0(n885), .B1(d_ff1_Z[13]),
.C0(d_ff_Zn[13]), .C1(n898), .Y(n876) );
INVX2TS U1123 ( .A(n876), .Y(n483) );
AOI222X1TS U1124 ( .A0(n882), .A1(d_ff2_Z[14]), .B0(n885), .B1(d_ff1_Z[14]),
.C0(d_ff_Zn[14]), .C1(n901), .Y(n877) );
INVX2TS U1125 ( .A(n877), .Y(n482) );
AOI222X1TS U1126 ( .A0(n882), .A1(d_ff2_Z[15]), .B0(n885), .B1(d_ff1_Z[15]),
.C0(d_ff_Zn[15]), .C1(n898), .Y(n878) );
INVX2TS U1127 ( .A(n878), .Y(n481) );
AOI222X1TS U1128 ( .A0(n882), .A1(d_ff2_Z[16]), .B0(n885), .B1(d_ff1_Z[16]),
.C0(d_ff_Zn[16]), .C1(n898), .Y(n879) );
INVX2TS U1129 ( .A(n879), .Y(n480) );
AOI222X1TS U1130 ( .A0(n882), .A1(d_ff2_Z[17]), .B0(n885), .B1(d_ff1_Z[17]),
.C0(d_ff_Zn[17]), .C1(n901), .Y(n880) );
INVX2TS U1131 ( .A(n880), .Y(n479) );
AOI222X1TS U1132 ( .A0(n899), .A1(d_ff2_Z[18]), .B0(n885), .B1(d_ff1_Z[18]),
.C0(d_ff_Zn[18]), .C1(n901), .Y(n881) );
INVX2TS U1133 ( .A(n881), .Y(n478) );
AOI222X1TS U1134 ( .A0(n882), .A1(d_ff2_Z[19]), .B0(n885), .B1(d_ff1_Z[19]),
.C0(d_ff_Zn[19]), .C1(n901), .Y(n883) );
INVX2TS U1135 ( .A(n883), .Y(n477) );
AOI222X1TS U1136 ( .A0(n899), .A1(d_ff2_Z[20]), .B0(n885), .B1(d_ff1_Z[20]),
.C0(d_ff_Zn[20]), .C1(n901), .Y(n884) );
INVX2TS U1137 ( .A(n884), .Y(n476) );
INVX2TS U1138 ( .A(n886), .Y(n475) );
AOI222X1TS U1139 ( .A0(n899), .A1(d_ff2_Z[22]), .B0(n902), .B1(d_ff1_Z[22]),
.C0(d_ff_Zn[22]), .C1(n898), .Y(n887) );
INVX2TS U1140 ( .A(n887), .Y(n474) );
AOI222X1TS U1141 ( .A0(n801), .A1(d_ff2_Z[26]), .B0(n902), .B1(d_ff1_Z[26]),
.C0(d_ff_Zn[26]), .C1(n901), .Y(n888) );
INVX2TS U1142 ( .A(n888), .Y(n470) );
NAND3XLTS U1143 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[0]),
.C(n1135), .Y(n1025) );
CLKBUFX2TS U1144 ( .A(n1025), .Y(n1096) );
CLKBUFX2TS U1145 ( .A(n1096), .Y(n1132) );
NAND2X1TS U1146 ( .A(n1189), .B(n1216), .Y(n1085) );
CLKBUFX2TS U1147 ( .A(n1096), .Y(n1101) );
CLKBUFX3TS U1148 ( .A(n1101), .Y(n1185) );
AOI22X1TS U1149 ( .A0(n1205), .A1(n1146), .B0(d_ff3_sh_x_out[23]), .B1(n1185), .Y(n889) );
OAI21XLTS U1150 ( .A0(n1259), .A1(n1085), .B0(n889), .Y(n345) );
INVX2TS U1151 ( .A(n1105), .Y(n1088) );
NAND2X1TS U1152 ( .A(cont_iter_out[3]), .B(n1088), .Y(n1083) );
CLKBUFX3TS U1153 ( .A(n1101), .Y(n1203) );
AOI32X1TS U1154 ( .A0(cont_iter_out[0]), .A1(n1205), .A2(n1188), .B0(
d_ff3_LUT_out[23]), .B1(n1203), .Y(n890) );
OAI21XLTS U1155 ( .A0(cont_iter_out[0]), .A1(n1083), .B0(n890), .Y(n501) );
AOI222X1TS U1156 ( .A0(n899), .A1(d_ff2_Z[23]), .B0(n902), .B1(d_ff1_Z[23]),
.C0(d_ff_Zn[23]), .C1(n894), .Y(n891) );
INVX2TS U1157 ( .A(n891), .Y(n473) );
AOI222X1TS U1158 ( .A0(n899), .A1(d_ff2_Z[24]), .B0(n902), .B1(d_ff1_Z[24]),
.C0(d_ff_Zn[24]), .C1(n894), .Y(n892) );
INVX2TS U1159 ( .A(n892), .Y(n472) );
AOI22X1TS U1160 ( .A0(n1205), .A1(n1125), .B0(d_ff3_sh_y_out[23]), .B1(n1185), .Y(n893) );
INVX2TS U1161 ( .A(n895), .Y(n471) );
AOI222X1TS U1162 ( .A0(n899), .A1(d_ff2_Z[27]), .B0(n902), .B1(d_ff1_Z[27]),
.C0(d_ff_Zn[27]), .C1(n898), .Y(n896) );
INVX2TS U1163 ( .A(n896), .Y(n469) );
AOI222X1TS U1164 ( .A0(n899), .A1(d_ff2_Z[28]), .B0(n902), .B1(d_ff1_Z[28]),
.C0(d_ff_Zn[28]), .C1(n898), .Y(n897) );
INVX2TS U1165 ( .A(n897), .Y(n468) );
AOI222X1TS U1166 ( .A0(n899), .A1(d_ff2_Z[29]), .B0(n902), .B1(d_ff1_Z[29]),
.C0(d_ff_Zn[29]), .C1(n898), .Y(n900) );
INVX2TS U1167 ( .A(n900), .Y(n467) );
AOI222X1TS U1168 ( .A0(n801), .A1(d_ff2_Z[30]), .B0(n902), .B1(d_ff1_Z[30]),
.C0(d_ff_Zn[30]), .C1(n901), .Y(n903) );
INVX2TS U1169 ( .A(n903), .Y(n466) );
INVX2TS U1170 ( .A(n1108), .Y(n1183) );
NAND2X2TS U1171 ( .A(n1183), .B(n1224), .Y(n1106) );
INVX2TS U1172 ( .A(n1106), .Y(n1131) );
AOI22X1TS U1173 ( .A0(d_ff3_LUT_out[25]), .A1(n1203), .B0(n1131), .B1(n1112),
.Y(n904) );
OAI21XLTS U1174 ( .A0(n1081), .A1(n1105), .B0(n904), .Y(n499) );
AOI22X1TS U1175 ( .A0(d_ff_Xn[31]), .A1(n906), .B0(data_output2_31_), .B1(
n905), .Y(n907) );
OAI21XLTS U1176 ( .A0(n1258), .A1(n908), .B0(n907), .Y(n526) );
NAND2X1TS U1177 ( .A(n1189), .B(n909), .Y(n1093) );
OAI21X1TS U1178 ( .A0(n1106), .A1(n1223), .B0(n1093), .Y(n1086) );
AOI21X1TS U1179 ( .A0(d_ff3_LUT_out[1]), .A1(n1185), .B0(n1086), .Y(n910) );
OAI21XLTS U1180 ( .A0(cont_iter_out[3]), .A1(n1105), .B0(n910), .Y(n523) );
NOR2X1TS U1181 ( .A(n1112), .B(n1106), .Y(n1082) );
AOI21X1TS U1182 ( .A0(d_ff3_LUT_out[2]), .A1(n1185), .B0(n1082), .Y(n911) );
OAI21XLTS U1183 ( .A0(n1094), .A1(n1105), .B0(n911), .Y(n522) );
OAI211XLTS U1184 ( .A0(cont_iter_out[0]), .A1(cont_iter_out[3]), .B0(
cont_iter_out[1]), .C0(n1224), .Y(n912) );
OAI21X1TS U1185 ( .A0(cont_iter_out[0]), .A1(n1094), .B0(n912), .Y(n1181) );
AOI22X1TS U1186 ( .A0(n1205), .A1(n1181), .B0(d_ff3_LUT_out[6]), .B1(n1203),
.Y(n913) );
OAI31X1TS U1187 ( .A0(n1216), .A1(n1223), .A2(n1106), .B0(n913), .Y(n518) );
NAND3XLTS U1188 ( .A(n1157), .B(cordic_FSM_state_reg[3]), .C(n1225), .Y(n915) );
NAND3XLTS U1189 ( .A(n915), .B(sel_mux_3_reg), .C(n1290), .Y(n914) );
OAI21XLTS U1190 ( .A0(n916), .A1(n915), .B0(n914), .Y(n688) );
NAND3X1TS U1191 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[1]),
.C(n1044), .Y(n1170) );
INVX2TS U1192 ( .A(n1170), .Y(n1173) );
NAND2X1TS U1193 ( .A(sel_mux_2_reg[1]), .B(n1289), .Y(n917) );
OAI32X1TS U1194 ( .A0(n1170), .A1(n1159), .A2(n1218), .B0(n1173), .B1(n917),
.Y(n685) );
CLKBUFX3TS U1195 ( .A(n918), .Y(n932) );
CLKBUFX3TS U1196 ( .A(n919), .Y(n930) );
AOI22X1TS U1197 ( .A0(d_ff_Xn[0]), .A1(n930), .B0(sign_inv_out[0]), .B1(n928), .Y(n920) );
OAI21XLTS U1198 ( .A0(n1238), .A1(n932), .B0(n920), .Y(n588) );
AOI22X1TS U1199 ( .A0(d_ff_Xn[1]), .A1(n930), .B0(sign_inv_out[1]), .B1(n937), .Y(n921) );
OAI21XLTS U1200 ( .A0(n1239), .A1(n932), .B0(n921), .Y(n586) );
AOI22X1TS U1201 ( .A0(d_ff_Xn[2]), .A1(n930), .B0(sign_inv_out[2]), .B1(n937), .Y(n922) );
OAI21XLTS U1202 ( .A0(n1240), .A1(n932), .B0(n922), .Y(n584) );
AOI22X1TS U1203 ( .A0(d_ff_Xn[3]), .A1(n930), .B0(sign_inv_out[3]), .B1(n928), .Y(n923) );
OAI21XLTS U1204 ( .A0(n1241), .A1(n932), .B0(n923), .Y(n582) );
AOI22X1TS U1205 ( .A0(d_ff_Xn[4]), .A1(n930), .B0(sign_inv_out[4]), .B1(n928), .Y(n924) );
OAI21XLTS U1206 ( .A0(n1242), .A1(n932), .B0(n924), .Y(n580) );
AOI22X1TS U1207 ( .A0(d_ff_Xn[5]), .A1(n930), .B0(sign_inv_out[5]), .B1(n928), .Y(n925) );
OAI21XLTS U1208 ( .A0(n1243), .A1(n932), .B0(n925), .Y(n578) );
AOI22X1TS U1209 ( .A0(d_ff_Xn[6]), .A1(n930), .B0(sign_inv_out[6]), .B1(n928), .Y(n926) );
OAI21XLTS U1210 ( .A0(n1244), .A1(n932), .B0(n926), .Y(n576) );
AOI22X1TS U1211 ( .A0(d_ff_Xn[7]), .A1(n930), .B0(sign_inv_out[7]), .B1(n928), .Y(n927) );
OAI21XLTS U1212 ( .A0(n1245), .A1(n932), .B0(n927), .Y(n574) );
AOI22X1TS U1213 ( .A0(d_ff_Xn[8]), .A1(n930), .B0(sign_inv_out[8]), .B1(n928), .Y(n929) );
OAI21XLTS U1214 ( .A0(n1246), .A1(n932), .B0(n929), .Y(n572) );
AOI22X1TS U1215 ( .A0(d_ff_Xn[9]), .A1(n930), .B0(sign_inv_out[9]), .B1(n937), .Y(n931) );
OAI21XLTS U1216 ( .A0(n1247), .A1(n932), .B0(n931), .Y(n570) );
AOI22X1TS U1217 ( .A0(d_ff_Xn[10]), .A1(n942), .B0(sign_inv_out[10]), .B1(
n937), .Y(n933) );
OAI21XLTS U1218 ( .A0(n1248), .A1(n944), .B0(n933), .Y(n568) );
AOI22X1TS U1219 ( .A0(d_ff_Xn[17]), .A1(n942), .B0(sign_inv_out[17]), .B1(
n941), .Y(n934) );
OAI21XLTS U1220 ( .A0(n1255), .A1(n944), .B0(n934), .Y(n554) );
AOI22X1TS U1221 ( .A0(d_ff_Xn[14]), .A1(n942), .B0(sign_inv_out[14]), .B1(
n941), .Y(n935) );
OAI21XLTS U1222 ( .A0(n1252), .A1(n944), .B0(n935), .Y(n560) );
AOI22X1TS U1223 ( .A0(d_ff_Xn[15]), .A1(n942), .B0(sign_inv_out[15]), .B1(
n941), .Y(n936) );
OAI21XLTS U1224 ( .A0(n1253), .A1(n944), .B0(n936), .Y(n558) );
AOI22X1TS U1225 ( .A0(d_ff_Xn[11]), .A1(n942), .B0(sign_inv_out[11]), .B1(
n937), .Y(n938) );
OAI21XLTS U1226 ( .A0(n1249), .A1(n944), .B0(n938), .Y(n566) );
AOI22X1TS U1227 ( .A0(d_ff_Xn[12]), .A1(n942), .B0(sign_inv_out[12]), .B1(
n941), .Y(n939) );
OAI21XLTS U1228 ( .A0(n1250), .A1(n944), .B0(n939), .Y(n564) );
AOI22X1TS U1229 ( .A0(d_ff_Xn[16]), .A1(n942), .B0(sign_inv_out[16]), .B1(
n941), .Y(n940) );
OAI21XLTS U1230 ( .A0(n1254), .A1(n944), .B0(n940), .Y(n556) );
AOI22X1TS U1231 ( .A0(d_ff_Xn[13]), .A1(n942), .B0(sign_inv_out[13]), .B1(
n941), .Y(n943) );
NAND4XLTS U1232 ( .A(n799), .B(cordic_FSM_state_reg[1]), .C(
cordic_FSM_state_reg[2]), .D(cordic_FSM_state_reg[0]), .Y(n1160) );
INVX2TS U1233 ( .A(n1160), .Y(beg_add_subt) );
AOI22X1TS U1234 ( .A0(d_ff2_Z[30]), .A1(n1010), .B0(d_ff2_X[30]), .B1(n1153),
.Y(n945) );
OAI21XLTS U1235 ( .A0(n1232), .A1(n998), .B0(n945), .Y(add_subt_dataA[30])
);
AOI22X1TS U1236 ( .A0(d_ff2_Z[29]), .A1(n983), .B0(d_ff2_X[29]), .B1(n1153),
.Y(n946) );
OAI21XLTS U1237 ( .A0(n1234), .A1(n985), .B0(n946), .Y(add_subt_dataA[29])
);
INVX2TS U1238 ( .A(n998), .Y(n996) );
CLKBUFX3TS U1239 ( .A(n1003), .Y(n1021) );
AOI222X1TS U1240 ( .A0(d_ff2_Z[31]), .A1(n837), .B0(d_ff2_Y[31]), .B1(n1154),
.C0(d_ff2_X[31]), .C1(n1021), .Y(n947) );
INVX2TS U1241 ( .A(n947), .Y(add_subt_dataA[31]) );
AOI22X1TS U1242 ( .A0(d_ff2_Z[27]), .A1(n1010), .B0(d_ff2_X[27]), .B1(n1153),
.Y(n948) );
OAI21XLTS U1243 ( .A0(n1233), .A1(n985), .B0(n948), .Y(add_subt_dataA[27])
);
CLKBUFX3TS U1244 ( .A(n1010), .Y(n1005) );
INVX2TS U1245 ( .A(n998), .Y(n975) );
AOI222X1TS U1246 ( .A0(d_ff2_Z[26]), .A1(n1005), .B0(d_ff2_Y[26]), .B1(n1154), .C0(d_ff2_X[26]), .C1(n1021), .Y(n949) );
INVX2TS U1247 ( .A(n949), .Y(add_subt_dataA[26]) );
AOI22X1TS U1248 ( .A0(d_ff2_X[24]), .A1(n1153), .B0(d_ff2_Z[24]), .B1(n983),
.Y(n950) );
OAI21XLTS U1249 ( .A0(n1226), .A1(n985), .B0(n950), .Y(add_subt_dataA[24])
);
AOI22X1TS U1250 ( .A0(d_ff2_X[23]), .A1(n1153), .B0(d_ff2_Z[23]), .B1(n1010),
.Y(n951) );
CLKBUFX3TS U1251 ( .A(n979), .Y(n964) );
AOI222X1TS U1252 ( .A0(d_ff2_Z[22]), .A1(n988), .B0(d_ff2_Y[22]), .B1(n973),
.C0(d_ff2_X[22]), .C1(n964), .Y(n952) );
INVX2TS U1253 ( .A(n952), .Y(add_subt_dataA[22]) );
AOI222X1TS U1254 ( .A0(d_ff2_Z[21]), .A1(n1005), .B0(d_ff2_Y[21]), .B1(n973),
.C0(d_ff2_X[21]), .C1(n964), .Y(n953) );
INVX2TS U1255 ( .A(n953), .Y(add_subt_dataA[21]) );
AOI22X1TS U1256 ( .A0(d_ff2_Z[28]), .A1(n1010), .B0(d_ff2_X[28]), .B1(n1153),
.Y(n954) );
CLKBUFX3TS U1257 ( .A(n983), .Y(n967) );
AOI222X1TS U1258 ( .A0(d_ff2_Z[19]), .A1(n967), .B0(d_ff2_Y[19]), .B1(n1151),
.C0(d_ff2_X[19]), .C1(n964), .Y(n955) );
INVX2TS U1259 ( .A(n955), .Y(add_subt_dataA[19]) );
AOI222X1TS U1260 ( .A0(d_ff2_Z[18]), .A1(n967), .B0(d_ff2_Y[18]), .B1(n975),
.C0(d_ff2_X[18]), .C1(n964), .Y(n956) );
INVX2TS U1261 ( .A(n956), .Y(add_subt_dataA[18]) );
AOI222X1TS U1262 ( .A0(d_ff2_Z[17]), .A1(n967), .B0(d_ff2_Y[17]), .B1(n1012),
.C0(d_ff2_X[17]), .C1(n964), .Y(n957) );
INVX2TS U1263 ( .A(n957), .Y(add_subt_dataA[17]) );
AOI222X1TS U1264 ( .A0(d_ff2_Z[16]), .A1(n967), .B0(d_ff2_Y[16]), .B1(n1154),
.C0(d_ff2_X[16]), .C1(n964), .Y(n958) );
INVX2TS U1265 ( .A(n958), .Y(add_subt_dataA[16]) );
AOI222X1TS U1266 ( .A0(d_ff2_Z[15]), .A1(n967), .B0(d_ff2_Y[15]), .B1(n973),
.C0(d_ff2_X[15]), .C1(n964), .Y(n959) );
INVX2TS U1267 ( .A(n959), .Y(add_subt_dataA[15]) );
AOI222X1TS U1268 ( .A0(d_ff2_Z[14]), .A1(n967), .B0(d_ff2_Y[14]), .B1(n1151),
.C0(d_ff2_X[14]), .C1(n964), .Y(n960) );
INVX2TS U1269 ( .A(n960), .Y(add_subt_dataA[14]) );
INVX2TS U1270 ( .A(n998), .Y(n973) );
AOI222X1TS U1271 ( .A0(d_ff2_Z[13]), .A1(n967), .B0(d_ff2_Y[13]), .B1(n1154),
.C0(d_ff2_X[13]), .C1(n964), .Y(n961) );
INVX2TS U1272 ( .A(n961), .Y(add_subt_dataA[13]) );
AOI222X1TS U1273 ( .A0(d_ff2_Z[12]), .A1(n967), .B0(d_ff2_Y[12]), .B1(n973),
.C0(d_ff2_X[12]), .C1(n1003), .Y(n962) );
INVX2TS U1274 ( .A(n962), .Y(add_subt_dataA[12]) );
AOI222X1TS U1275 ( .A0(d_ff2_Z[11]), .A1(n967), .B0(d_ff2_Y[11]), .B1(n1151),
.C0(d_ff2_X[11]), .C1(n1152), .Y(n963) );
INVX2TS U1276 ( .A(n963), .Y(add_subt_dataA[11]) );
AOI222X1TS U1277 ( .A0(d_ff2_Z[10]), .A1(n988), .B0(d_ff2_Y[10]), .B1(n975),
.C0(d_ff2_X[10]), .C1(n964), .Y(n965) );
INVX2TS U1278 ( .A(n965), .Y(add_subt_dataA[10]) );
AOI222X1TS U1279 ( .A0(d_ff2_Z[9]), .A1(n980), .B0(d_ff2_Y[9]), .B1(n1012),
.C0(d_ff2_X[9]), .C1(n1003), .Y(n966) );
INVX2TS U1280 ( .A(n966), .Y(add_subt_dataA[9]) );
AOI222X1TS U1281 ( .A0(d_ff2_Z[8]), .A1(n967), .B0(d_ff2_Y[8]), .B1(n1154),
.C0(d_ff2_X[8]), .C1(n1003), .Y(n968) );
INVX2TS U1282 ( .A(n968), .Y(add_subt_dataA[8]) );
AOI222X1TS U1283 ( .A0(d_ff2_Z[7]), .A1(n988), .B0(d_ff2_Y[7]), .B1(n975),
.C0(d_ff2_X[7]), .C1(n1152), .Y(n969) );
INVX2TS U1284 ( .A(n969), .Y(add_subt_dataA[7]) );
AOI222X1TS U1285 ( .A0(d_ff2_Z[6]), .A1(n988), .B0(d_ff2_Y[6]), .B1(n973),
.C0(d_ff2_X[6]), .C1(n979), .Y(n970) );
INVX2TS U1286 ( .A(n970), .Y(add_subt_dataA[6]) );
AOI222X1TS U1287 ( .A0(d_ff2_Z[5]), .A1(n980), .B0(d_ff2_Y[5]), .B1(n1151),
.C0(d_ff2_X[5]), .C1(n979), .Y(n971) );
INVX2TS U1288 ( .A(n971), .Y(add_subt_dataA[5]) );
AOI222X1TS U1289 ( .A0(d_ff2_Z[4]), .A1(n980), .B0(d_ff2_Y[4]), .B1(n975),
.C0(d_ff2_X[4]), .C1(n1003), .Y(n972) );
INVX2TS U1290 ( .A(n972), .Y(add_subt_dataA[4]) );
AOI222X1TS U1291 ( .A0(d_ff2_Z[3]), .A1(n980), .B0(d_ff2_Y[3]), .B1(n1012),
.C0(d_ff2_X[3]), .C1(n979), .Y(n974) );
INVX2TS U1292 ( .A(n974), .Y(add_subt_dataA[3]) );
AOI222X1TS U1293 ( .A0(d_ff2_Z[20]), .A1(n1005), .B0(d_ff2_Y[20]), .B1(n1012), .C0(d_ff2_X[20]), .C1(n1021), .Y(n976) );
INVX2TS U1294 ( .A(n976), .Y(add_subt_dataA[20]) );
INVX2TS U1295 ( .A(n998), .Y(n1151) );
AOI222X1TS U1296 ( .A0(d_ff2_Z[1]), .A1(n988), .B0(d_ff2_Y[1]), .B1(n975),
.C0(d_ff2_X[1]), .C1(n1152), .Y(n977) );
INVX2TS U1297 ( .A(n977), .Y(add_subt_dataA[1]) );
AOI222X1TS U1298 ( .A0(d_ff2_Z[0]), .A1(n1005), .B0(d_ff2_Y[0]), .B1(n1151),
.C0(d_ff2_X[0]), .C1(n1021), .Y(n978) );
INVX2TS U1299 ( .A(n978), .Y(add_subt_dataA[0]) );
AOI222X1TS U1300 ( .A0(d_ff2_Z[2]), .A1(n980), .B0(d_ff2_Y[2]), .B1(n1012),
.C0(d_ff2_X[2]), .C1(n979), .Y(n981) );
INVX2TS U1301 ( .A(n981), .Y(add_subt_dataA[2]) );
AOI22X1TS U1302 ( .A0(d_ff3_sh_y_out[29]), .A1(n1153), .B0(d_ff3_LUT_out[27]), .B1(n983), .Y(n982) );
OAI21XLTS U1303 ( .A0(n1236), .A1(n985), .B0(n982), .Y(add_subt_dataB[29])
);
AOI22X1TS U1304 ( .A0(d_ff3_sh_y_out[28]), .A1(n1153), .B0(d_ff3_LUT_out[27]), .B1(n983), .Y(n984) );
CLKBUFX3TS U1305 ( .A(n986), .Y(n1001) );
AOI222X1TS U1306 ( .A0(d_ff3_LUT_out[26]), .A1(n1005), .B0(n996), .B1(
d_ff3_sh_x_out[26]), .C0(n1001), .C1(d_ff3_sh_y_out[26]), .Y(n987) );
INVX2TS U1307 ( .A(n987), .Y(add_subt_dataB[26]) );
AOI222X1TS U1308 ( .A0(d_ff3_sh_x_out[25]), .A1(n1012), .B0(
d_ff3_LUT_out[25]), .B1(n988), .C0(n1001), .C1(d_ff3_sh_y_out[25]),
.Y(n989) );
INVX2TS U1309 ( .A(n989), .Y(add_subt_dataB[25]) );
INVX2TS U1310 ( .A(n990), .Y(add_subt_dataB[24]) );
AOI222X1TS U1311 ( .A0(d_ff3_LUT_out[23]), .A1(n1005), .B0(
d_ff3_sh_y_out[23]), .B1(n1021), .C0(d_ff3_sh_x_out[23]), .C1(n996),
.Y(n991) );
INVX2TS U1312 ( .A(n991), .Y(add_subt_dataB[23]) );
AOI222X1TS U1313 ( .A0(n1010), .A1(d_ff3_LUT_out[22]), .B0(n996), .B1(
d_ff3_sh_x_out[22]), .C0(n1001), .C1(d_ff3_sh_y_out[22]), .Y(n992) );
INVX2TS U1314 ( .A(n992), .Y(add_subt_dataB[22]) );
AOI222X1TS U1315 ( .A0(d_ff3_LUT_out[21]), .A1(n1005), .B0(n996), .B1(
d_ff3_sh_x_out[21]), .C0(n1001), .C1(d_ff3_sh_y_out[21]), .Y(n993) );
INVX2TS U1316 ( .A(n993), .Y(add_subt_dataB[21]) );
AOI222X1TS U1317 ( .A0(d_ff3_LUT_out[20]), .A1(n1005), .B0(n996), .B1(
d_ff3_sh_x_out[20]), .C0(n1001), .C1(d_ff3_sh_y_out[20]), .Y(n994) );
INVX2TS U1318 ( .A(n994), .Y(add_subt_dataB[20]) );
AOI222X1TS U1319 ( .A0(n1010), .A1(d_ff3_LUT_out[19]), .B0(n996), .B1(
d_ff3_sh_x_out[19]), .C0(n1001), .C1(d_ff3_sh_y_out[19]), .Y(n995) );
INVX2TS U1320 ( .A(n995), .Y(add_subt_dataB[19]) );
AOI222X1TS U1321 ( .A0(d_ff3_LUT_out[18]), .A1(n980), .B0(n996), .B1(
d_ff3_sh_x_out[18]), .C0(n1001), .C1(d_ff3_sh_y_out[18]), .Y(n997) );
INVX2TS U1322 ( .A(n997), .Y(add_subt_dataB[18]) );
AOI222X1TS U1323 ( .A0(d_ff3_LUT_out[17]), .A1(n988), .B0(n1012), .B1(
d_ff3_sh_x_out[17]), .C0(n1001), .C1(d_ff3_sh_y_out[17]), .Y(n999) );
INVX2TS U1324 ( .A(n999), .Y(add_subt_dataB[17]) );
AOI222X1TS U1325 ( .A0(d_ff3_LUT_out[16]), .A1(n988), .B0(n1154), .B1(
d_ff3_sh_x_out[16]), .C0(n1001), .C1(d_ff3_sh_y_out[16]), .Y(n1000) );
INVX2TS U1326 ( .A(n1000), .Y(add_subt_dataB[16]) );
AOI222X1TS U1327 ( .A0(d_ff3_LUT_out[15]), .A1(n1010), .B0(n973), .B1(
d_ff3_sh_x_out[15]), .C0(n1001), .C1(d_ff3_sh_y_out[15]), .Y(n1002) );
INVX2TS U1328 ( .A(n1002), .Y(add_subt_dataB[15]) );
CLKBUFX3TS U1329 ( .A(n1003), .Y(n1017) );
AOI222X1TS U1330 ( .A0(d_ff3_LUT_out[14]), .A1(n983), .B0(n1151), .B1(
d_ff3_sh_x_out[14]), .C0(n1017), .C1(d_ff3_sh_y_out[14]), .Y(n1004) );
INVX2TS U1331 ( .A(n1004), .Y(add_subt_dataB[14]) );
AOI222X1TS U1332 ( .A0(d_ff3_LUT_out[13]), .A1(n1005), .B0(n975), .B1(
d_ff3_sh_x_out[13]), .C0(n1021), .C1(d_ff3_sh_y_out[13]), .Y(n1006) );
INVX2TS U1333 ( .A(n1006), .Y(add_subt_dataB[13]) );
AOI222X1TS U1334 ( .A0(d_ff3_LUT_out[11]), .A1(n980), .B0(n1012), .B1(
d_ff3_sh_x_out[11]), .C0(n1017), .C1(d_ff3_sh_y_out[11]), .Y(n1007) );
INVX2TS U1335 ( .A(n1007), .Y(add_subt_dataB[11]) );
AOI222X1TS U1336 ( .A0(d_ff3_LUT_out[10]), .A1(n988), .B0(n1154), .B1(
d_ff3_sh_x_out[10]), .C0(n1017), .C1(d_ff3_sh_y_out[10]), .Y(n1008) );
INVX2TS U1337 ( .A(n1008), .Y(add_subt_dataB[10]) );
AOI222X1TS U1338 ( .A0(d_ff3_LUT_out[9]), .A1(n1010), .B0(n973), .B1(
d_ff3_sh_x_out[9]), .C0(n1017), .C1(d_ff3_sh_y_out[9]), .Y(n1009) );
INVX2TS U1339 ( .A(n1009), .Y(add_subt_dataB[9]) );
INVX2TS U1340 ( .A(n1011), .Y(add_subt_dataB[8]) );
AOI222X1TS U1341 ( .A0(d_ff3_LUT_out[7]), .A1(n837), .B0(n975), .B1(
d_ff3_sh_x_out[7]), .C0(n1017), .C1(d_ff3_sh_y_out[7]), .Y(n1013) );
INVX2TS U1342 ( .A(n1013), .Y(add_subt_dataB[7]) );
AOI222X1TS U1343 ( .A0(d_ff3_LUT_out[6]), .A1(n837), .B0(n996), .B1(
d_ff3_sh_x_out[6]), .C0(n1017), .C1(d_ff3_sh_y_out[6]), .Y(n1014) );
INVX2TS U1344 ( .A(n1014), .Y(add_subt_dataB[6]) );
AOI222X1TS U1345 ( .A0(d_ff3_LUT_out[5]), .A1(n837), .B0(n996), .B1(
d_ff3_sh_x_out[5]), .C0(n1017), .C1(d_ff3_sh_y_out[5]), .Y(n1015) );
INVX2TS U1346 ( .A(n1015), .Y(add_subt_dataB[5]) );
AOI222X1TS U1347 ( .A0(d_ff3_LUT_out[4]), .A1(n837), .B0(n1154), .B1(
d_ff3_sh_x_out[4]), .C0(n1017), .C1(d_ff3_sh_y_out[4]), .Y(n1016) );
INVX2TS U1348 ( .A(n1016), .Y(add_subt_dataB[4]) );
AOI222X1TS U1349 ( .A0(d_ff3_LUT_out[3]), .A1(n980), .B0(n1012), .B1(
d_ff3_sh_x_out[3]), .C0(n1017), .C1(d_ff3_sh_y_out[3]), .Y(n1018) );
INVX2TS U1350 ( .A(n1018), .Y(add_subt_dataB[3]) );
AOI222X1TS U1351 ( .A0(d_ff3_LUT_out[2]), .A1(n837), .B0(n973), .B1(
d_ff3_sh_x_out[2]), .C0(n1021), .C1(d_ff3_sh_y_out[2]), .Y(n1019) );
INVX2TS U1352 ( .A(n1019), .Y(add_subt_dataB[2]) );
AOI222X1TS U1353 ( .A0(d_ff3_LUT_out[1]), .A1(n837), .B0(n1151), .B1(
d_ff3_sh_x_out[1]), .C0(n1021), .C1(d_ff3_sh_y_out[1]), .Y(n1020) );
INVX2TS U1354 ( .A(n1020), .Y(add_subt_dataB[1]) );
AOI222X1TS U1355 ( .A0(d_ff3_LUT_out[0]), .A1(n837), .B0(n975), .B1(
d_ff3_sh_x_out[0]), .C0(n1021), .C1(d_ff3_sh_y_out[0]), .Y(n1022) );
INVX2TS U1356 ( .A(n1022), .Y(add_subt_dataB[0]) );
INVX2TS U1357 ( .A(n1132), .Y(n1128) );
NAND2X1TS U1358 ( .A(d_ff2_Y[24]), .B(n1217), .Y(n1023) );
AOI22X1TS U1359 ( .A0(cont_iter_out[1]), .A1(n1226), .B0(n1125), .B1(n1023),
.Y(n1029) );
CLKBUFX3TS U1360 ( .A(n1101), .Y(n1126) );
AO22XLTS U1361 ( .A0(n1128), .A1(n1024), .B0(n1126), .B1(d_ff3_sh_y_out[25]),
.Y(n407) );
CLKBUFX2TS U1362 ( .A(n1025), .Y(n1098) );
INVX2TS U1363 ( .A(n1098), .Y(n1072) );
CLKBUFX3TS U1364 ( .A(n1096), .Y(n1071) );
AO22XLTS U1365 ( .A0(n1072), .A1(d_ff2_X[15]), .B0(n1071), .B1(
d_ff3_sh_x_out[15]), .Y(n368) );
AO22XLTS U1366 ( .A0(n1072), .A1(d_ff2_X[20]), .B0(n1071), .B1(
d_ff3_sh_x_out[20]), .Y(n358) );
INVX2TS U1367 ( .A(n1068), .Y(n1070) );
AO22XLTS U1368 ( .A0(n1070), .A1(sign_inv_out[15]), .B0(n1062), .B1(
data_output[15]), .Y(n557) );
INVX2TS U1369 ( .A(n1132), .Y(n1111) );
AO22XLTS U1370 ( .A0(n1111), .A1(d_ff2_Y[0]), .B0(n1096), .B1(
d_ff3_sh_y_out[0]), .Y(n462) );
INVX2TS U1371 ( .A(n1050), .Y(n1041) );
AO22XLTS U1372 ( .A0(n1050), .A1(data_in[1]), .B0(n1041), .B1(d_ff1_Z[1]),
.Y(n719) );
AO22XLTS U1373 ( .A0(n1070), .A1(sign_inv_out[16]), .B0(n1062), .B1(
data_output[16]), .Y(n555) );
INVX2TS U1374 ( .A(n1132), .Y(n1069) );
AO22XLTS U1375 ( .A0(n1069), .A1(d_ff2_X[22]), .B0(n1071), .B1(
d_ff3_sh_x_out[22]), .Y(n354) );
INVX2TS U1376 ( .A(n1098), .Y(n1148) );
AO22XLTS U1377 ( .A0(n1148), .A1(d_ff2_X[17]), .B0(n1071), .B1(
d_ff3_sh_x_out[17]), .Y(n364) );
INVX2TS U1378 ( .A(n1098), .Y(n1119) );
AO22XLTS U1379 ( .A0(n1119), .A1(d_ff2_X[16]), .B0(n1071), .B1(
d_ff3_sh_x_out[16]), .Y(n366) );
AO22XLTS U1380 ( .A0(n1148), .A1(d_ff2_X[21]), .B0(n1071), .B1(
d_ff3_sh_x_out[21]), .Y(n356) );
INVX2TS U1381 ( .A(n1028), .Y(n1036) );
CLKBUFX2TS U1382 ( .A(n1036), .Y(n1032) );
AO22XLTS U1383 ( .A0(n1028), .A1(result_add_subt[2]), .B0(n1032), .B1(
d_ff_Zn[2]), .Y(n682) );
AO22XLTS U1384 ( .A0(n1072), .A1(d_ff2_X[18]), .B0(n1071), .B1(
d_ff3_sh_x_out[18]), .Y(n362) );
AO22XLTS U1385 ( .A0(n1143), .A1(result_add_subt[3]), .B0(n1032), .B1(
d_ff_Zn[3]), .Y(n681) );
AO22XLTS U1386 ( .A0(n1070), .A1(sign_inv_out[17]), .B0(n1062), .B1(
data_output[17]), .Y(n553) );
CMPR32X2TS U1387 ( .A(d_ff2_Y[25]), .B(n1224), .C(n1029), .CO(n1033), .S(
n1024) );
AO22XLTS U1388 ( .A0(n1128), .A1(n1030), .B0(n1126), .B1(d_ff3_sh_y_out[26]),
.Y(n406) );
AO22XLTS U1389 ( .A0(n1072), .A1(d_ff2_X[19]), .B0(n1071), .B1(
d_ff3_sh_x_out[19]), .Y(n360) );
NAND2X1TS U1390 ( .A(d_ff2_X[24]), .B(n1217), .Y(n1144) );
OR3X1TS U1391 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(n1076), .Y(n1202) );
OAI21XLTS U1392 ( .A0(d_ff2_X[27]), .A1(n1076), .B0(d_ff2_X[28]), .Y(n1031)
);
AOI32X1TS U1393 ( .A0(n1202), .A1(n1205), .A2(n1031), .B0(n1237), .B1(n1203),
.Y(n340) );
AO22XLTS U1394 ( .A0(n1143), .A1(result_add_subt[1]), .B0(n1032), .B1(
d_ff_Zn[1]), .Y(n683) );
AO22XLTS U1395 ( .A0(n1143), .A1(result_add_subt[4]), .B0(n1032), .B1(
d_ff_Zn[4]), .Y(n680) );
CLKBUFX3TS U1396 ( .A(n1062), .Y(n1040) );
AO22XLTS U1397 ( .A0(n1070), .A1(sign_inv_out[18]), .B0(n1040), .B1(
data_output[18]), .Y(n551) );
AO22XLTS U1398 ( .A0(n1072), .A1(d_ff2_X[14]), .B0(n1071), .B1(
d_ff3_sh_x_out[14]), .Y(n370) );
AO22XLTS U1399 ( .A0(n1069), .A1(d_ff2_Y[1]), .B0(n1108), .B1(
d_ff3_sh_y_out[1]), .Y(n460) );
AO22XLTS U1400 ( .A0(n1143), .A1(result_add_subt[5]), .B0(n1032), .B1(
d_ff_Zn[5]), .Y(n679) );
AO22XLTS U1401 ( .A0(n1143), .A1(result_add_subt[6]), .B0(n1032), .B1(
d_ff_Zn[6]), .Y(n678) );
AO22XLTS U1402 ( .A0(n1143), .A1(result_add_subt[7]), .B0(n1032), .B1(
d_ff_Zn[7]), .Y(n677) );
AO22XLTS U1403 ( .A0(n1070), .A1(sign_inv_out[19]), .B0(n1040), .B1(
data_output[19]), .Y(n549) );
CMPR32X2TS U1404 ( .A(d_ff2_Y[26]), .B(n1223), .C(n1033), .CO(n1118), .S(
n1030) );
OR3X1TS U1405 ( .A(n1118), .B(d_ff2_Y[28]), .C(d_ff2_Y[27]), .Y(n1079) );
NOR2X1TS U1406 ( .A(d_ff2_Y[29]), .B(n1079), .Y(n1078) );
XOR2XLTS U1407 ( .A(d_ff2_Y[30]), .B(n1078), .Y(n1034) );
AO22XLTS U1408 ( .A0(n1128), .A1(n1034), .B0(n1126), .B1(d_ff3_sh_y_out[30]),
.Y(n402) );
CLKBUFX2TS U1409 ( .A(n1036), .Y(n1142) );
AO22XLTS U1410 ( .A0(n1143), .A1(result_add_subt[8]), .B0(n1142), .B1(
d_ff_Zn[8]), .Y(n676) );
CLKBUFX2TS U1411 ( .A(n1036), .Y(n1140) );
AO22XLTS U1412 ( .A0(n1143), .A1(result_add_subt[9]), .B0(n1140), .B1(
d_ff_Zn[9]), .Y(n675) );
INVX2TS U1413 ( .A(n1140), .Y(n1037) );
AO22XLTS U1414 ( .A0(n1037), .A1(result_add_subt[10]), .B0(n1036), .B1(
d_ff_Zn[10]), .Y(n674) );
NOR2X1TS U1415 ( .A(d_ff2_X[29]), .B(n1202), .Y(n1201) );
XOR2XLTS U1416 ( .A(d_ff2_X[30]), .B(n1201), .Y(n1035) );
AO22XLTS U1417 ( .A0(n1069), .A1(n1035), .B0(n1132), .B1(d_ff3_sh_x_out[30]),
.Y(n338) );
AO22XLTS U1418 ( .A0(n803), .A1(sign_inv_out[20]), .B0(n1040), .B1(
data_output[20]), .Y(n547) );
AO22XLTS U1419 ( .A0(n1037), .A1(result_add_subt[11]), .B0(n1142), .B1(
d_ff_Zn[11]), .Y(n673) );
AO22XLTS U1420 ( .A0(n1037), .A1(result_add_subt[12]), .B0(n1140), .B1(
d_ff_Zn[12]), .Y(n672) );
CLKBUFX3TS U1421 ( .A(n1101), .Y(n1051) );
AO22XLTS U1422 ( .A0(n1111), .A1(d_ff2_X[31]), .B0(n1051), .B1(
d_ff3_sh_x_out[31]), .Y(n336) );
AO22XLTS U1423 ( .A0(n1037), .A1(result_add_subt[13]), .B0(n1140), .B1(
d_ff_Zn[13]), .Y(n671) );
AO22XLTS U1424 ( .A0(n1038), .A1(sign_inv_out[21]), .B0(n1040), .B1(
data_output[21]), .Y(n545) );
AO22XLTS U1425 ( .A0(n1037), .A1(result_add_subt[14]), .B0(n1142), .B1(
d_ff_Zn[14]), .Y(n670) );
AO22XLTS U1426 ( .A0(n1128), .A1(d_ff2_Y[31]), .B0(n1126), .B1(
d_ff3_sh_y_out[31]), .Y(n400) );
AO22XLTS U1427 ( .A0(n1037), .A1(result_add_subt[15]), .B0(n1036), .B1(
d_ff_Zn[15]), .Y(n669) );
AO22XLTS U1428 ( .A0(n1037), .A1(result_add_subt[16]), .B0(n1036), .B1(
d_ff_Zn[16]), .Y(n668) );
AO22XLTS U1429 ( .A0(n1037), .A1(result_add_subt[17]), .B0(n1036), .B1(
d_ff_Zn[17]), .Y(n667) );
AO22XLTS U1430 ( .A0(n803), .A1(sign_inv_out[22]), .B0(n1040), .B1(
data_output[22]), .Y(n543) );
CLKBUFX3TS U1431 ( .A(n1036), .Y(n1039) );
AO22XLTS U1432 ( .A0(n1037), .A1(result_add_subt[18]), .B0(n1039), .B1(
d_ff_Zn[18]), .Y(n666) );
AO22XLTS U1433 ( .A0(n1037), .A1(result_add_subt[19]), .B0(n1039), .B1(
d_ff_Zn[19]), .Y(n665) );
AO22XLTS U1434 ( .A0(n1038), .A1(sign_inv_out[30]), .B0(n798), .B1(
data_output[30]), .Y(n527) );
INVX2TS U1435 ( .A(n1140), .Y(n1138) );
AO22XLTS U1436 ( .A0(n1138), .A1(result_add_subt[20]), .B0(n1039), .B1(
d_ff_Zn[20]), .Y(n664) );
AO22XLTS U1437 ( .A0(n1038), .A1(sign_inv_out[23]), .B0(n1040), .B1(
data_output[23]), .Y(n541) );
AO22XLTS U1438 ( .A0(n1138), .A1(result_add_subt[21]), .B0(n1039), .B1(
d_ff_Zn[21]), .Y(n663) );
AO22XLTS U1439 ( .A0(n803), .A1(sign_inv_out[29]), .B0(n1068), .B1(
data_output[29]), .Y(n529) );
AO22XLTS U1440 ( .A0(n1138), .A1(result_add_subt[22]), .B0(n1039), .B1(
d_ff_Zn[22]), .Y(n662) );
AO22XLTS U1441 ( .A0(n1138), .A1(result_add_subt[23]), .B0(n1039), .B1(
d_ff_Zn[23]), .Y(n661) );
AO22XLTS U1442 ( .A0(n1038), .A1(sign_inv_out[24]), .B0(n1040), .B1(
data_output[24]), .Y(n539) );
AO22XLTS U1443 ( .A0(n1138), .A1(result_add_subt[24]), .B0(n1039), .B1(
d_ff_Zn[24]), .Y(n660) );
AO22XLTS U1444 ( .A0(n803), .A1(sign_inv_out[27]), .B0(n1040), .B1(
data_output[27]), .Y(n533) );
AO22XLTS U1445 ( .A0(n1138), .A1(result_add_subt[25]), .B0(n1039), .B1(
d_ff_Zn[25]), .Y(n659) );
AO22XLTS U1446 ( .A0(n1138), .A1(result_add_subt[26]), .B0(n1039), .B1(
d_ff_Zn[26]), .Y(n658) );
INVX2TS U1447 ( .A(n1199), .Y(n1100) );
AO22XLTS U1448 ( .A0(d_ff2_X[23]), .A1(n802), .B0(d_ff_Xn[23]), .B1(n1100),
.Y(n353) );
AO22XLTS U1449 ( .A0(n1038), .A1(sign_inv_out[26]), .B0(n1040), .B1(
data_output[26]), .Y(n535) );
AO22XLTS U1450 ( .A0(n1138), .A1(result_add_subt[27]), .B0(n1039), .B1(
d_ff_Zn[27]), .Y(n657) );
AO22XLTS U1451 ( .A0(n803), .A1(sign_inv_out[25]), .B0(n1040), .B1(
data_output[25]), .Y(n537) );
CLKBUFX2TS U1452 ( .A(n1049), .Y(n1053) );
AO22XLTS U1453 ( .A0(n1167), .A1(d_ff1_operation_out), .B0(n1061), .B1(
operation), .Y(n723) );
INVX2TS U1454 ( .A(n1052), .Y(n1054) );
AO22XLTS U1455 ( .A0(n1054), .A1(sign_inv_out[0]), .B0(n1068), .B1(
data_output[0]), .Y(n587) );
AO22XLTS U1456 ( .A0(n1050), .A1(data_in[2]), .B0(n1041), .B1(d_ff1_Z[2]),
.Y(n718) );
AO22XLTS U1457 ( .A0(n1128), .A1(d_ff2_Y[22]), .B0(n1126), .B1(
d_ff3_sh_y_out[22]), .Y(n418) );
AO22XLTS U1458 ( .A0(n1050), .A1(data_in[3]), .B0(n1041), .B1(d_ff1_Z[3]),
.Y(n717) );
AO22XLTS U1459 ( .A0(n1050), .A1(data_in[4]), .B0(n1041), .B1(d_ff1_Z[4]),
.Y(n716) );
AO22XLTS U1460 ( .A0(n1183), .A1(d_ff2_Y[21]), .B0(n1051), .B1(
d_ff3_sh_y_out[21]), .Y(n420) );
AO22XLTS U1461 ( .A0(n1053), .A1(data_in[5]), .B0(n1041), .B1(d_ff1_Z[5]),
.Y(n715) );
AO22XLTS U1462 ( .A0(n1054), .A1(sign_inv_out[2]), .B0(n1052), .B1(
data_output[2]), .Y(n583) );
AO22XLTS U1463 ( .A0(n1061), .A1(data_in[6]), .B0(n1041), .B1(d_ff1_Z[6]),
.Y(n714) );
AO22XLTS U1464 ( .A0(n1128), .A1(d_ff2_Y[20]), .B0(n1051), .B1(
d_ff3_sh_y_out[20]), .Y(n422) );
AO22XLTS U1465 ( .A0(n1042), .A1(data_in[7]), .B0(n1041), .B1(d_ff1_Z[7]),
.Y(n713) );
AO22XLTS U1466 ( .A0(n1061), .A1(data_in[8]), .B0(n1041), .B1(d_ff1_Z[8]),
.Y(n712) );
AO22XLTS U1467 ( .A0(n1054), .A1(sign_inv_out[3]), .B0(n1052), .B1(
data_output[3]), .Y(n581) );
AO22XLTS U1468 ( .A0(n1183), .A1(d_ff2_Y[19]), .B0(n1051), .B1(
d_ff3_sh_y_out[19]), .Y(n424) );
AO22XLTS U1469 ( .A0(n1042), .A1(data_in[9]), .B0(n1041), .B1(d_ff1_Z[9]),
.Y(n711) );
AO22XLTS U1470 ( .A0(n1061), .A1(data_in[10]), .B0(n1041), .B1(d_ff1_Z[10]),
.Y(n710) );
INVX2TS U1471 ( .A(n1049), .Y(n1060) );
AO22XLTS U1472 ( .A0(n1042), .A1(data_in[11]), .B0(n1060), .B1(d_ff1_Z[11]),
.Y(n709) );
AO22XLTS U1473 ( .A0(n1111), .A1(d_ff2_Y[18]), .B0(n1051), .B1(
d_ff3_sh_y_out[18]), .Y(n426) );
AO22XLTS U1474 ( .A0(n1054), .A1(sign_inv_out[4]), .B0(n1052), .B1(
data_output[4]), .Y(n579) );
CLKBUFX3TS U1475 ( .A(n1049), .Y(n1061) );
AO22XLTS U1476 ( .A0(n1061), .A1(data_in[12]), .B0(n1060), .B1(d_ff1_Z[12]),
.Y(n708) );
AO22XLTS U1477 ( .A0(n1042), .A1(data_in[13]), .B0(n1060), .B1(d_ff1_Z[13]),
.Y(n707) );
AO22XLTS U1478 ( .A0(n1183), .A1(d_ff2_Y[17]), .B0(n1051), .B1(
d_ff3_sh_y_out[17]), .Y(n428) );
AO22XLTS U1479 ( .A0(n1061), .A1(data_in[14]), .B0(n1060), .B1(d_ff1_Z[14]),
.Y(n706) );
AO22XLTS U1480 ( .A0(n1054), .A1(sign_inv_out[5]), .B0(n1052), .B1(
data_output[5]), .Y(n577) );
AO22XLTS U1481 ( .A0(n1042), .A1(data_in[15]), .B0(n1060), .B1(d_ff1_Z[15]),
.Y(n705) );
AO22XLTS U1482 ( .A0(n1167), .A1(d_ff1_shift_region_flag_out[1]), .B0(n1042),
.B1(shift_region_flag[1]), .Y(n721) );
AO22XLTS U1483 ( .A0(n1069), .A1(d_ff2_Y[16]), .B0(n1051), .B1(
d_ff3_sh_y_out[16]), .Y(n430) );
AO22XLTS U1484 ( .A0(n1061), .A1(data_in[16]), .B0(n1060), .B1(d_ff1_Z[16]),
.Y(n704) );
AOI31XLTS U1485 ( .A0(cordic_FSM_state_reg[3]), .A1(cordic_FSM_state_reg[0]),
.A2(ack_cordic), .B0(cordic_FSM_state_reg[1]), .Y(n1043) );
OAI21X1TS U1486 ( .A0(n1044), .A1(n1043), .B0(cordic_FSM_state_reg[2]), .Y(
n1047) );
NAND2X1TS U1487 ( .A(cont_var_out[1]), .B(n1227), .Y(n1045) );
NAND4XLTS U1488 ( .A(cordic_FSM_state_reg[3]), .B(n1215), .C(n1065), .D(
n1045), .Y(n1046) );
AOI32X1TS U1489 ( .A0(n1048), .A1(n1047), .A2(n1046), .B0(n1225), .B1(n1047),
.Y(n731) );
AO22XLTS U1490 ( .A0(n1050), .A1(data_in[17]), .B0(n1060), .B1(d_ff1_Z[17]),
.Y(n703) );
AO22XLTS U1491 ( .A0(n1183), .A1(d_ff2_Y[15]), .B0(n1051), .B1(
d_ff3_sh_y_out[15]), .Y(n432) );
AO22XLTS U1492 ( .A0(n1050), .A1(data_in[18]), .B0(n1060), .B1(d_ff1_Z[18]),
.Y(n702) );
AO22XLTS U1493 ( .A0(n1054), .A1(sign_inv_out[6]), .B0(n1052), .B1(
data_output[6]), .Y(n575) );
AO22XLTS U1494 ( .A0(n1049), .A1(data_in[19]), .B0(n1060), .B1(d_ff1_Z[19]),
.Y(n701) );
AO22XLTS U1495 ( .A0(n1050), .A1(data_in[20]), .B0(n1055), .B1(d_ff1_Z[20]),
.Y(n700) );
AO22XLTS U1496 ( .A0(n1111), .A1(d_ff2_Y[14]), .B0(n1051), .B1(
d_ff3_sh_y_out[14]), .Y(n434) );
AO22XLTS U1497 ( .A0(n1054), .A1(sign_inv_out[7]), .B0(n1052), .B1(
data_output[7]), .Y(n573) );
AO22XLTS U1498 ( .A0(n1183), .A1(d_ff2_Y[13]), .B0(n1051), .B1(
d_ff3_sh_y_out[13]), .Y(n436) );
AO22XLTS U1499 ( .A0(n1053), .A1(data_in[23]), .B0(n1055), .B1(d_ff1_Z[23]),
.Y(n697) );
AO22XLTS U1500 ( .A0(n1053), .A1(data_in[24]), .B0(n1055), .B1(d_ff1_Z[24]),
.Y(n696) );
AO22XLTS U1501 ( .A0(n1054), .A1(sign_inv_out[1]), .B0(n1052), .B1(
data_output[1]), .Y(n585) );
CLKBUFX3TS U1502 ( .A(n1096), .Y(n1110) );
AO22XLTS U1503 ( .A0(n1111), .A1(d_ff2_Y[11]), .B0(n1110), .B1(
d_ff3_sh_y_out[11]), .Y(n440) );
AO22XLTS U1504 ( .A0(n1053), .A1(data_in[25]), .B0(n1055), .B1(d_ff1_Z[25]),
.Y(n695) );
AO22XLTS U1505 ( .A0(n1054), .A1(sign_inv_out[8]), .B0(n1062), .B1(
data_output[8]), .Y(n571) );
AO22XLTS U1506 ( .A0(n1053), .A1(data_in[26]), .B0(n1055), .B1(d_ff1_Z[26]),
.Y(n694) );
AO22XLTS U1507 ( .A0(n1128), .A1(d_ff2_Y[10]), .B0(n1110), .B1(
d_ff3_sh_y_out[10]), .Y(n442) );
AO22XLTS U1508 ( .A0(n1042), .A1(data_in[27]), .B0(n1055), .B1(d_ff1_Z[27]),
.Y(n693) );
AO22XLTS U1509 ( .A0(n1167), .A1(d_ff1_shift_region_flag_out[0]), .B0(n1061),
.B1(shift_region_flag[0]), .Y(n722) );
AO22XLTS U1510 ( .A0(n1061), .A1(data_in[28]), .B0(n1055), .B1(d_ff1_Z[28]),
.Y(n692) );
AO22XLTS U1511 ( .A0(n1054), .A1(sign_inv_out[9]), .B0(n1068), .B1(
data_output[9]), .Y(n569) );
AO22XLTS U1512 ( .A0(n1042), .A1(data_in[29]), .B0(n1055), .B1(d_ff1_Z[29]),
.Y(n691) );
AO22XLTS U1513 ( .A0(n1111), .A1(d_ff2_Y[9]), .B0(n1110), .B1(
d_ff3_sh_y_out[9]), .Y(n444) );
AO22XLTS U1514 ( .A0(n1061), .A1(data_in[30]), .B0(n1167), .B1(d_ff1_Z[30]),
.Y(n690) );
INVX2TS U1515 ( .A(beg_fsm_cordic), .Y(n1056) );
AOI32X1TS U1516 ( .A0(n1135), .A1(n1215), .A2(n1056), .B0(n1158), .B1(
cordic_FSM_state_reg[2]), .Y(n1059) );
OR4X2TS U1517 ( .A(ack_cordic), .B(n1215), .C(n800), .D(
cordic_FSM_state_reg[1]), .Y(n1161) );
NOR2BX1TS U1518 ( .AN(ready_add_subt), .B(cordic_FSM_state_reg[2]), .Y(n1057) );
OAI31X1TS U1519 ( .A0(n1157), .A1(n1057), .A2(n800), .B0(n1225), .Y(n1058)
);
NAND4XLTS U1520 ( .A(n1059), .B(n1166), .C(n1161), .D(n1058), .Y(n730) );
AO22XLTS U1521 ( .A0(n1042), .A1(data_in[31]), .B0(n1060), .B1(d_ff1_Z[31]),
.Y(n689) );
AO22XLTS U1522 ( .A0(n1111), .A1(d_ff2_Y[8]), .B0(n1110), .B1(
d_ff3_sh_y_out[8]), .Y(n446) );
AO22XLTS U1523 ( .A0(n1028), .A1(result_add_subt[0]), .B0(n1140), .B1(
d_ff_Zn[0]), .Y(n684) );
AO22XLTS U1524 ( .A0(n1070), .A1(sign_inv_out[10]), .B0(n1062), .B1(
data_output[10]), .Y(n567) );
CMPR32X2TS U1525 ( .A(n1223), .B(d_ff2_X[26]), .C(n1063), .CO(n1076), .S(
n1064) );
AO22XLTS U1526 ( .A0(n1069), .A1(n1064), .B0(n1108), .B1(d_ff3_sh_x_out[26]),
.Y(n342) );
NAND3X1TS U1527 ( .A(cont_var_out[0]), .B(ack_add_subt), .C(n1065), .Y(n1164) );
AOI31XLTS U1528 ( .A0(ack_add_subt), .A1(n1065), .A2(n1218), .B0(
cont_var_out[0]), .Y(n1066) );
NOR3BXLTS U1529 ( .AN(n1164), .B(n1205), .C(n1066), .Y(n724) );
AO22XLTS U1530 ( .A0(n1069), .A1(d_ff2_Y[7]), .B0(n1110), .B1(
d_ff3_sh_y_out[7]), .Y(n448) );
AO22XLTS U1531 ( .A0(n1128), .A1(d_ff2_X[0]), .B0(n1126), .B1(
d_ff3_sh_x_out[0]), .Y(n398) );
AOI2BB2XLTS U1532 ( .B0(n1228), .B1(n1067), .A0N(d_ff_Xn[25]), .A1N(n1196),
.Y(n351) );
AO22XLTS U1533 ( .A0(n1072), .A1(d_ff2_X[1]), .B0(n1126), .B1(
d_ff3_sh_x_out[1]), .Y(n396) );
AO22XLTS U1534 ( .A0(n1070), .A1(sign_inv_out[11]), .B0(n1062), .B1(
data_output[11]), .Y(n565) );
AO22XLTS U1535 ( .A0(n1069), .A1(d_ff2_Y[6]), .B0(n1110), .B1(
d_ff3_sh_y_out[6]), .Y(n450) );
AO22XLTS U1536 ( .A0(n1072), .A1(d_ff2_X[2]), .B0(n1126), .B1(
d_ff3_sh_x_out[2]), .Y(n394) );
CLKBUFX3TS U1537 ( .A(n1101), .Y(n1073) );
AO22XLTS U1538 ( .A0(n1148), .A1(d_ff2_X[3]), .B0(n1073), .B1(
d_ff3_sh_x_out[3]), .Y(n392) );
AO22XLTS U1539 ( .A0(n1148), .A1(d_ff2_X[4]), .B0(n1073), .B1(
d_ff3_sh_x_out[4]), .Y(n390) );
AO22XLTS U1540 ( .A0(n1069), .A1(d_ff2_Y[5]), .B0(n1110), .B1(
d_ff3_sh_y_out[5]), .Y(n452) );
AO22XLTS U1541 ( .A0(n1070), .A1(sign_inv_out[12]), .B0(n1068), .B1(
data_output[12]), .Y(n563) );
AO22XLTS U1542 ( .A0(n1072), .A1(d_ff2_X[5]), .B0(n1073), .B1(
d_ff3_sh_x_out[5]), .Y(n388) );
AO22XLTS U1543 ( .A0(n1148), .A1(d_ff2_X[6]), .B0(n1073), .B1(
d_ff3_sh_x_out[6]), .Y(n386) );
AO22XLTS U1544 ( .A0(n1111), .A1(d_ff2_Y[4]), .B0(n1110), .B1(
d_ff3_sh_y_out[4]), .Y(n454) );
AO22XLTS U1545 ( .A0(n1148), .A1(d_ff2_X[7]), .B0(n1073), .B1(
d_ff3_sh_x_out[7]), .Y(n384) );
AO22XLTS U1546 ( .A0(n1070), .A1(sign_inv_out[13]), .B0(n1068), .B1(
data_output[13]), .Y(n561) );
AO22XLTS U1547 ( .A0(n1148), .A1(d_ff2_X[8]), .B0(n1073), .B1(
d_ff3_sh_x_out[8]), .Y(n382) );
AO22XLTS U1548 ( .A0(n1069), .A1(d_ff2_Y[3]), .B0(n1110), .B1(
d_ff3_sh_y_out[3]), .Y(n456) );
AO22XLTS U1549 ( .A0(n1148), .A1(d_ff2_X[9]), .B0(n1073), .B1(
d_ff3_sh_x_out[9]), .Y(n380) );
AO22XLTS U1550 ( .A0(n1111), .A1(d_ff2_X[10]), .B0(n1073), .B1(
d_ff3_sh_x_out[10]), .Y(n378) );
AO22XLTS U1551 ( .A0(n1069), .A1(d_ff2_Y[2]), .B0(n1098), .B1(
d_ff3_sh_y_out[2]), .Y(n458) );
AO22XLTS U1552 ( .A0(n1072), .A1(d_ff2_X[11]), .B0(n1073), .B1(
d_ff3_sh_x_out[11]), .Y(n376) );
AO22XLTS U1553 ( .A0(n1070), .A1(sign_inv_out[14]), .B0(n1052), .B1(
data_output[14]), .Y(n559) );
AO22XLTS U1554 ( .A0(n1072), .A1(d_ff2_X[13]), .B0(n1071), .B1(
d_ff3_sh_x_out[13]), .Y(n372) );
AO22XLTS U1555 ( .A0(n1138), .A1(result_add_subt[28]), .B0(n1142), .B1(
d_ff_Zn[28]), .Y(n656) );
INVX2TS U1556 ( .A(n1129), .Y(n1130) );
AO22XLTS U1557 ( .A0(n1130), .A1(result_add_subt[5]), .B0(n1129), .B1(
d_ff_Xn[5]), .Y(n615) );
AO22XLTS U1558 ( .A0(n1130), .A1(result_add_subt[3]), .B0(n1129), .B1(
d_ff_Xn[3]), .Y(n617) );
AO22XLTS U1559 ( .A0(n1130), .A1(result_add_subt[2]), .B0(n1129), .B1(
d_ff_Xn[2]), .Y(n618) );
AO22XLTS U1560 ( .A0(n1130), .A1(result_add_subt[1]), .B0(n1129), .B1(
d_ff_Xn[1]), .Y(n619) );
INVX2TS U1561 ( .A(n1139), .Y(n1121) );
CLKBUFX3TS U1562 ( .A(n1149), .Y(n1122) );
AO22XLTS U1563 ( .A0(n1121), .A1(result_add_subt[22]), .B0(n1122), .B1(
d_ff_Xn[22]), .Y(n598) );
AO22XLTS U1564 ( .A0(n1148), .A1(d_ff2_X[12]), .B0(n1073), .B1(
d_ff3_sh_x_out[12]), .Y(n374) );
AO22XLTS U1565 ( .A0(n1121), .A1(result_add_subt[21]), .B0(n1122), .B1(
d_ff_Xn[21]), .Y(n599) );
NOR2X1TS U1566 ( .A(d_ff2_Y[27]), .B(n1118), .Y(n1117) );
OAI21XLTS U1567 ( .A0(n1117), .A1(n1230), .B0(n1079), .Y(n1074) );
AO22XLTS U1568 ( .A0(n1128), .A1(n1074), .B0(n1126), .B1(d_ff3_sh_y_out[28]),
.Y(n404) );
INVX2TS U1569 ( .A(n1139), .Y(n1150) );
AO22XLTS U1570 ( .A0(n1150), .A1(result_add_subt[18]), .B0(n1122), .B1(
d_ff_Xn[18]), .Y(n602) );
NOR2XLTS U1571 ( .A(d_ff2_X[27]), .B(n1076), .Y(n1075) );
AOI21X1TS U1572 ( .A0(n1076), .A1(d_ff2_X[27]), .B0(n1075), .Y(n1077) );
AOI2BB2XLTS U1573 ( .B0(n1189), .B1(n1077), .A0N(d_ff3_sh_x_out[27]), .A1N(
n1119), .Y(n341) );
AO22XLTS U1574 ( .A0(n1150), .A1(result_add_subt[15]), .B0(n1149), .B1(
d_ff_Xn[15]), .Y(n605) );
AOI21X1TS U1575 ( .A0(d_ff2_Y[29]), .A1(n1079), .B0(n1078), .Y(n1080) );
AOI2BB2XLTS U1576 ( .B0(n1189), .B1(n1080), .A0N(d_ff3_sh_y_out[29]), .A1N(
n1119), .Y(n403) );
AO22XLTS U1577 ( .A0(n1150), .A1(result_add_subt[11]), .B0(n1141), .B1(
d_ff_Xn[11]), .Y(n609) );
INVX2TS U1578 ( .A(n1081), .Y(n1087) );
AOI32X1TS U1579 ( .A0(n1085), .A1(n1084), .A2(n1083), .B0(cont_iter_out[1]),
.B1(n1084), .Y(n500) );
AO22XLTS U1580 ( .A0(n1130), .A1(result_add_subt[9]), .B0(n1139), .B1(
d_ff_Xn[9]), .Y(n611) );
AO22XLTS U1581 ( .A0(n1130), .A1(result_add_subt[8]), .B0(n1141), .B1(
d_ff_Xn[8]), .Y(n612) );
AO22XLTS U1582 ( .A0(n1130), .A1(result_add_subt[4]), .B0(n1129), .B1(
d_ff_Xn[4]), .Y(n616) );
AO22XLTS U1583 ( .A0(n1130), .A1(result_add_subt[0]), .B0(n1139), .B1(
d_ff_Xn[0]), .Y(n620) );
AO22XLTS U1584 ( .A0(n1121), .A1(result_add_subt[25]), .B0(n1122), .B1(
d_ff_Xn[25]), .Y(n595) );
AO22XLTS U1585 ( .A0(n1121), .A1(result_add_subt[23]), .B0(n1122), .B1(
d_ff_Xn[23]), .Y(n597) );
AO22XLTS U1586 ( .A0(n1130), .A1(result_add_subt[6]), .B0(n1129), .B1(
d_ff_Xn[6]), .Y(n614) );
INVX2TS U1587 ( .A(n1195), .Y(n1123) );
AO22XLTS U1588 ( .A0(d_ff_Yn[31]), .A1(n1123), .B0(d_ff2_Y[31]), .B1(n1099),
.Y(n401) );
AO22XLTS U1589 ( .A0(d_ff_Yn[22]), .A1(n1123), .B0(d_ff2_Y[22]), .B1(n1099),
.Y(n419) );
AO22XLTS U1590 ( .A0(d_ff_Yn[21]), .A1(n1123), .B0(d_ff2_Y[21]), .B1(n1099),
.Y(n421) );
AOI21X1TS U1591 ( .A0(n1087), .A1(n1189), .B0(n1086), .Y(n1184) );
NOR2X2TS U1592 ( .A(cont_iter_out[3]), .B(n1217), .Y(n1114) );
AOI22X1TS U1593 ( .A0(n1114), .A1(n1088), .B0(d_ff3_LUT_out[0]), .B1(n1203),
.Y(n1089) );
NAND2X1TS U1594 ( .A(n1184), .B(n1089), .Y(n524) );
INVX2TS U1595 ( .A(n1194), .Y(n1134) );
AO22XLTS U1596 ( .A0(d_ff_Yn[18]), .A1(n1134), .B0(d_ff2_Y[18]), .B1(n1099),
.Y(n427) );
AO22XLTS U1597 ( .A0(n1098), .A1(d_ff3_sign_out), .B0(n1119), .B1(
d_ff2_Z[31]), .Y(n464) );
AO22XLTS U1598 ( .A0(d_ff_Yn[17]), .A1(n1134), .B0(d_ff2_Y[17]), .B1(n1133),
.Y(n429) );
AO22XLTS U1599 ( .A0(d_ff_Xn[0]), .A1(n1123), .B0(d_ff2_X[0]), .B1(n1099),
.Y(n399) );
AO22XLTS U1600 ( .A0(d_ff_Xn[4]), .A1(n1123), .B0(d_ff2_X[4]), .B1(n1099),
.Y(n391) );
INVX2TS U1601 ( .A(n1090), .Y(n1091) );
AO22XLTS U1602 ( .A0(d_ff_Yn[6]), .A1(n1092), .B0(d_ff2_Y[6]), .B1(n1091),
.Y(n451) );
AO22XLTS U1603 ( .A0(d_ff_Xn[8]), .A1(n1123), .B0(d_ff2_X[8]), .B1(n1099),
.Y(n383) );
AO22XLTS U1604 ( .A0(d_ff_Yn[15]), .A1(n1134), .B0(d_ff2_Y[15]), .B1(n802),
.Y(n433) );
AO22XLTS U1605 ( .A0(d_ff_Xn[9]), .A1(n1092), .B0(d_ff2_X[9]), .B1(n801),
.Y(n381) );
AO22XLTS U1606 ( .A0(d_ff_Xn[11]), .A1(n1100), .B0(d_ff2_X[11]), .B1(n802),
.Y(n377) );
AO22XLTS U1607 ( .A0(d_ff_Yn[14]), .A1(n1134), .B0(d_ff2_Y[14]), .B1(n1133),
.Y(n435) );
AO22XLTS U1608 ( .A0(d_ff_Xn[15]), .A1(n1100), .B0(d_ff2_X[15]), .B1(n1133),
.Y(n369) );
AO22XLTS U1609 ( .A0(d_ff_Yn[13]), .A1(n1134), .B0(d_ff2_Y[13]), .B1(n1133),
.Y(n437) );
AO22XLTS U1610 ( .A0(d_ff_Xn[18]), .A1(n1100), .B0(d_ff2_X[18]), .B1(n802),
.Y(n363) );
AO22XLTS U1611 ( .A0(d_ff_Xn[21]), .A1(n1100), .B0(d_ff2_X[21]), .B1(n802),
.Y(n357) );
AO22XLTS U1612 ( .A0(d_ff_Yn[12]), .A1(n1134), .B0(d_ff2_Y[12]), .B1(n1091),
.Y(n439) );
AO22XLTS U1613 ( .A0(d_ff_Xn[22]), .A1(n1100), .B0(d_ff2_X[22]), .B1(n802),
.Y(n355) );
AO22XLTS U1614 ( .A0(d_ff_Yn[11]), .A1(n1134), .B0(d_ff2_Y[11]), .B1(n1091),
.Y(n441) );
AO22XLTS U1615 ( .A0(d_ff_Xn[31]), .A1(n1092), .B0(d_ff2_X[31]), .B1(n801),
.Y(n337) );
AO22XLTS U1616 ( .A0(d_ff_Yn[0]), .A1(n1100), .B0(d_ff2_Y[0]), .B1(n802),
.Y(n463) );
AO22XLTS U1617 ( .A0(d_ff_Yn[10]), .A1(n1123), .B0(d_ff2_Y[10]), .B1(n1091),
.Y(n443) );
AO22XLTS U1618 ( .A0(d_ff_Yn[1]), .A1(n1092), .B0(d_ff2_Y[1]), .B1(n1099),
.Y(n461) );
AO22XLTS U1619 ( .A0(d_ff_Yn[9]), .A1(n1123), .B0(d_ff2_Y[9]), .B1(n1091),
.Y(n445) );
AO22XLTS U1620 ( .A0(d_ff_Yn[2]), .A1(n1092), .B0(d_ff2_Y[2]), .B1(n802),
.Y(n459) );
AO22XLTS U1621 ( .A0(d_ff_Yn[3]), .A1(n1092), .B0(d_ff2_Y[3]), .B1(n1091),
.Y(n457) );
AO22XLTS U1622 ( .A0(d_ff_Yn[8]), .A1(n1134), .B0(d_ff2_Y[8]), .B1(n1091),
.Y(n447) );
AO22XLTS U1623 ( .A0(d_ff_Yn[7]), .A1(n1092), .B0(d_ff2_Y[7]), .B1(n1091),
.Y(n449) );
AO22XLTS U1624 ( .A0(d_ff_Yn[4]), .A1(n1134), .B0(d_ff2_Y[4]), .B1(n1091),
.Y(n455) );
AO22XLTS U1625 ( .A0(d_ff_Yn[5]), .A1(n1092), .B0(d_ff2_Y[5]), .B1(n1091),
.Y(n453) );
NAND2X1TS U1626 ( .A(n1093), .B(n1190), .Y(n1095) );
AO21XLTS U1627 ( .A0(d_ff3_LUT_out[11]), .A1(n1096), .B0(n1095), .Y(n513) );
OAI31X1TS U1628 ( .A0(cont_iter_out[0]), .A1(cont_iter_out[2]), .A2(
cont_iter_out[3]), .B0(n1188), .Y(n1109) );
NOR2X1TS U1629 ( .A(n1203), .B(n1109), .Y(n1097) );
AO21XLTS U1630 ( .A0(d_ff3_LUT_out[13]), .A1(n1108), .B0(n1097), .Y(n511) );
OAI32X1TS U1631 ( .A0(n1203), .A1(n1216), .A2(n1094), .B0(n1186), .B1(n1203),
.Y(n1102) );
AO21XLTS U1632 ( .A0(d_ff3_LUT_out[14]), .A1(n1098), .B0(n1102), .Y(n510) );
AO21XLTS U1633 ( .A0(d_ff3_LUT_out[7]), .A1(n1096), .B0(n1095), .Y(n517) );
AO21XLTS U1634 ( .A0(d_ff3_LUT_out[18]), .A1(n1098), .B0(n1097), .Y(n506) );
AO22XLTS U1635 ( .A0(d_ff_Xn[30]), .A1(n1100), .B0(d_ff2_X[30]), .B1(n802),
.Y(n346) );
AO21XLTS U1636 ( .A0(d_ff3_LUT_out[5]), .A1(n1192), .B0(n1102), .Y(n519) );
XOR2X1TS U1637 ( .A(n1103), .B(n1228), .Y(n1104) );
MXI2X1TS U1638 ( .A(n1106), .B(n1105), .S0(n1104), .Y(n1107) );
AO21XLTS U1639 ( .A0(d_ff3_sh_x_out[25]), .A1(n1108), .B0(n1107), .Y(n343)
);
AO22XLTS U1640 ( .A0(d_ff_Yn[25]), .A1(n1123), .B0(d_ff2_Y[25]), .B1(n1099),
.Y(n415) );
AO22XLTS U1641 ( .A0(n1121), .A1(result_add_subt[29]), .B0(n1141), .B1(
d_ff_Xn[29]), .Y(n591) );
AOI21X1TS U1642 ( .A0(n1114), .A1(n1216), .B0(n1185), .Y(n1116) );
AOI2BB2XLTS U1643 ( .B0(n1116), .B1(n1109), .A0N(n1183), .A1N(
d_ff3_LUT_out[21]), .Y(n503) );
AO22XLTS U1644 ( .A0(n1111), .A1(d_ff2_Y[12]), .B0(n1110), .B1(
d_ff3_sh_y_out[12]), .Y(n438) );
OAI21X1TS U1645 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .B0(n1189),
.Y(n1182) );
AOI21X1TS U1646 ( .A0(n1112), .A1(n1223), .B0(n1182), .Y(n1113) );
AOI2BB1XLTS U1647 ( .A0N(n1183), .A1N(d_ff3_LUT_out[26]), .B0(n1113), .Y(
n498) );
AO22XLTS U1648 ( .A0(n1121), .A1(result_add_subt[28]), .B0(n1141), .B1(
d_ff_Xn[28]), .Y(n592) );
INVX2TS U1649 ( .A(n1114), .Y(n1180) );
OAI21XLTS U1650 ( .A0(n814), .A1(n1180), .B0(n1188), .Y(n1115) );
AOI2BB2XLTS U1651 ( .B0(n1116), .B1(n1115), .A0N(n1183), .A1N(
d_ff3_LUT_out[9]), .Y(n515) );
AOI21X1TS U1652 ( .A0(n1118), .A1(d_ff2_Y[27]), .B0(n1117), .Y(n1120) );
AOI2BB2XLTS U1653 ( .B0(n1189), .B1(n1120), .A0N(d_ff3_sh_y_out[27]), .A1N(
n1119), .Y(n405) );
AO22XLTS U1654 ( .A0(n1121), .A1(result_add_subt[27]), .B0(n1122), .B1(
d_ff_Xn[27]), .Y(n593) );
AO22XLTS U1655 ( .A0(n1121), .A1(result_add_subt[26]), .B0(n1122), .B1(
d_ff_Xn[26]), .Y(n594) );
AO22XLTS U1656 ( .A0(n1038), .A1(sign_inv_out[28]), .B0(n1062), .B1(
data_output[28]), .Y(n531) );
AO22XLTS U1657 ( .A0(n1121), .A1(result_add_subt[24]), .B0(n1122), .B1(
d_ff_Xn[24]), .Y(n596) );
NAND2BXLTS U1658 ( .AN(d_ff3_LUT_out[27]), .B(n1185), .Y(n497) );
AO22XLTS U1659 ( .A0(n1121), .A1(result_add_subt[20]), .B0(n1122), .B1(
d_ff_Xn[20]), .Y(n600) );
AO22XLTS U1660 ( .A0(n1150), .A1(result_add_subt[19]), .B0(n1122), .B1(
d_ff_Xn[19]), .Y(n601) );
AO22XLTS U1661 ( .A0(n1150), .A1(result_add_subt[17]), .B0(n1149), .B1(
d_ff_Xn[17]), .Y(n603) );
AO22XLTS U1662 ( .A0(d_ff_Yn[26]), .A1(n1123), .B0(d_ff2_Y[26]), .B1(n801),
.Y(n414) );
AOI22X1TS U1663 ( .A0(cont_iter_out[1]), .A1(n1226), .B0(d_ff2_Y[24]), .B1(
n1217), .Y(n1124) );
XNOR2X1TS U1664 ( .A(n1125), .B(n1124), .Y(n1127) );
AO22XLTS U1665 ( .A0(n1128), .A1(n1127), .B0(n1126), .B1(d_ff3_sh_y_out[24]),
.Y(n408) );
AO22XLTS U1666 ( .A0(n1150), .A1(result_add_subt[16]), .B0(n1149), .B1(
d_ff_Xn[16]), .Y(n604) );
AO22XLTS U1667 ( .A0(n1130), .A1(result_add_subt[7]), .B0(n1129), .B1(
d_ff_Xn[7]), .Y(n613) );
AO22XLTS U1668 ( .A0(n1150), .A1(result_add_subt[12]), .B0(n1139), .B1(
d_ff_Xn[12]), .Y(n608) );
AO21XLTS U1669 ( .A0(d_ff3_LUT_out[8]), .A1(n1132), .B0(n1131), .Y(n516) );
AO22XLTS U1670 ( .A0(d_ff_Yn[16]), .A1(n1134), .B0(d_ff2_Y[16]), .B1(n1133),
.Y(n431) );
AOI31XLTS U1671 ( .A0(cordic_FSM_state_reg[0]), .A1(n1135), .A2(
beg_fsm_cordic), .B0(ack_add_subt), .Y(n1137) );
OAI211XLTS U1672 ( .A0(n1215), .A1(n800), .B0(cordic_FSM_state_reg[1]), .C0(
n1225), .Y(n1136) );
NAND3XLTS U1673 ( .A(n1137), .B(n1185), .C(n1136), .Y(
cordic_FSM_state_next_1_) );
AO22XLTS U1674 ( .A0(n1138), .A1(result_add_subt[29]), .B0(n1142), .B1(
d_ff_Zn[29]), .Y(n655) );
AO22XLTS U1675 ( .A0(n1150), .A1(result_add_subt[13]), .B0(n1139), .B1(
d_ff_Xn[13]), .Y(n607) );
INVX2TS U1676 ( .A(n1140), .Y(n1143) );
AO22XLTS U1677 ( .A0(n1143), .A1(result_add_subt[30]), .B0(n1142), .B1(
d_ff_Zn[30]), .Y(n654) );
AO22XLTS U1678 ( .A0(n1150), .A1(result_add_subt[14]), .B0(n1141), .B1(
d_ff_Xn[14]), .Y(n606) );
AO22XLTS U1679 ( .A0(n1143), .A1(result_add_subt[31]), .B0(n1142), .B1(
d_ff_Zn[31]), .Y(n653) );
OAI21XLTS U1680 ( .A0(d_ff2_X[24]), .A1(n1217), .B0(n1144), .Y(n1145) );
XOR2XLTS U1681 ( .A(n1146), .B(n1145), .Y(n1147) );
AO22XLTS U1682 ( .A0(n1148), .A1(n1147), .B0(n1185), .B1(d_ff3_sh_x_out[24]),
.Y(n344) );
AO22XLTS U1683 ( .A0(n1150), .A1(result_add_subt[10]), .B0(n1149), .B1(
d_ff_Xn[10]), .Y(n610) );
AO22XLTS U1684 ( .A0(n1012), .A1(d_ff3_sh_x_out[31]), .B0(n1152), .B1(
d_ff3_sh_y_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U1685 ( .A0(d_ff3_sh_y_out[30]), .A1(n1152), .B0(d_ff3_sh_x_out[30]), .B1(n1154), .Y(add_subt_dataB[30]) );
AOI22X1TS U1686 ( .A0(n973), .A1(d_ff3_sh_x_out[27]), .B0(n1153), .B1(
d_ff3_sh_y_out[27]), .Y(n1156) );
NAND2X1TS U1687 ( .A(d_ff3_LUT_out[27]), .B(n983), .Y(n1155) );
NAND2X1TS U1688 ( .A(n1156), .B(n1155), .Y(add_subt_dataB[27]) );
AOI2BB2XLTS U1689 ( .B0(d_ff3_sign_out), .B1(n1227), .A0N(n1227), .A1N(
d_ff3_sign_out), .Y(op_add_subt) );
AOI211XLTS U1690 ( .A0(n1159), .A1(n1215), .B0(n1158), .C0(n1157), .Y(n1162)
);
OAI211XLTS U1691 ( .A0(n1162), .A1(n800), .B0(n1161), .C0(n1160), .Y(n732)
);
OAI21XLTS U1692 ( .A0(n1218), .A1(n1164), .B0(n1185), .Y(n1163) );
AOI21X1TS U1693 ( .A0(n1218), .A1(n1164), .B0(n1163), .Y(n729) );
NAND2X1TS U1694 ( .A(n1167), .B(n1166), .Y(n1165) );
AOI22X1TS U1695 ( .A0(cont_iter_out[0]), .A1(n1165), .B0(n1166), .B1(n1216),
.Y(n728) );
NOR2X1TS U1696 ( .A(n1216), .B(n1166), .Y(n1169) );
OAI21XLTS U1697 ( .A0(cont_iter_out[1]), .A1(n1169), .B0(n1167), .Y(n1168)
);
AOI21X1TS U1698 ( .A0(cont_iter_out[1]), .A1(n1169), .B0(n1168), .Y(n727) );
OAI32X1TS U1699 ( .A0(n1173), .A1(n1172), .A2(n1231), .B0(n1171), .B1(n1170),
.Y(n686) );
CLKBUFX3TS U1700 ( .A(n1174), .Y(n1178) );
OAI2BB2XLTS U1701 ( .B0(n1175), .B1(n1243), .A0N(n1178), .A1N(
result_add_subt[5]), .Y(n647) );
OAI2BB2XLTS U1702 ( .B0(n1175), .B1(n1244), .A0N(n1178), .A1N(
result_add_subt[6]), .Y(n646) );
OAI2BB2XLTS U1703 ( .B0(n1175), .B1(n1245), .A0N(n1178), .A1N(
result_add_subt[7]), .Y(n645) );
OAI2BB2XLTS U1704 ( .B0(n1175), .B1(n1246), .A0N(n1176), .A1N(
result_add_subt[8]), .Y(n644) );
OAI2BB2XLTS U1705 ( .B0(n1175), .B1(n1247), .A0N(n1178), .A1N(
result_add_subt[9]), .Y(n643) );
OAI2BB2XLTS U1706 ( .B0(n1175), .B1(n1248), .A0N(n1176), .A1N(
result_add_subt[10]), .Y(n642) );
OAI2BB2XLTS U1707 ( .B0(n1177), .B1(n1249), .A0N(n1176), .A1N(
result_add_subt[11]), .Y(n641) );
OAI2BB2XLTS U1708 ( .B0(n1177), .B1(n1250), .A0N(n1176), .A1N(
result_add_subt[12]), .Y(n640) );
OAI2BB2XLTS U1709 ( .B0(n1177), .B1(n1251), .A0N(n1176), .A1N(
result_add_subt[13]), .Y(n639) );
OAI2BB2XLTS U1710 ( .B0(n1177), .B1(n1252), .A0N(n1176), .A1N(
result_add_subt[14]), .Y(n638) );
OAI2BB2XLTS U1711 ( .B0(n1175), .B1(n1253), .A0N(n1178), .A1N(
result_add_subt[15]), .Y(n637) );
OAI2BB2XLTS U1712 ( .B0(n1177), .B1(n1254), .A0N(n1176), .A1N(
result_add_subt[16]), .Y(n636) );
OAI2BB2XLTS U1713 ( .B0(n1177), .B1(n1255), .A0N(n1176), .A1N(
result_add_subt[17]), .Y(n635) );
OAI2BB2XLTS U1714 ( .B0(n1177), .B1(n1256), .A0N(n1178), .A1N(
result_add_subt[18]), .Y(n634) );
OAI2BB2XLTS U1715 ( .B0(n1177), .B1(n1257), .A0N(n1178), .A1N(
result_add_subt[19]), .Y(n633) );
OAI2BB2XLTS U1716 ( .B0(n1177), .B1(n1220), .A0N(n1178), .A1N(
result_add_subt[20]), .Y(n632) );
OAI2BB2XLTS U1717 ( .B0(n1179), .B1(n1221), .A0N(n1178), .A1N(
result_add_subt[22]), .Y(n630) );
OAI2BB2XLTS U1718 ( .B0(n1179), .B1(n1206), .A0N(n1178), .A1N(
result_add_subt[23]), .Y(n629) );
OAI211X1TS U1719 ( .A0(n1180), .A1(cont_iter_out[2]), .B0(n1188), .C0(n1189),
.Y(n1187) );
OAI2BB1X1TS U1720 ( .A0N(d_ff3_LUT_out[3]), .A1N(n1192), .B0(n1187), .Y(n521) );
OA22X1TS U1721 ( .A0(n1183), .A1(d_ff3_LUT_out[4]), .B0(n1182), .B1(n1181),
.Y(n520) );
OAI2BB1X1TS U1722 ( .A0N(d_ff3_LUT_out[10]), .A1N(n1192), .B0(n1184), .Y(
n514) );
AOI22X1TS U1723 ( .A0(n1205), .A1(n1186), .B0(n1235), .B1(n1185), .Y(n512)
);
OAI2BB1X1TS U1724 ( .A0N(d_ff3_LUT_out[15]), .A1N(n1192), .B0(n1190), .Y(
n509) );
OAI2BB1X1TS U1725 ( .A0N(d_ff3_LUT_out[16]), .A1N(n1192), .B0(n1187), .Y(
n508) );
OAI2BB1X1TS U1726 ( .A0N(d_ff3_LUT_out[17]), .A1N(n1192), .B0(n1190), .Y(
n507) );
NAND2X1TS U1727 ( .A(n1189), .B(n1188), .Y(n1191) );
OAI2BB1X1TS U1728 ( .A0N(d_ff3_LUT_out[19]), .A1N(n1192), .B0(n1191), .Y(
n505) );
OAI2BB1X1TS U1729 ( .A0N(d_ff3_LUT_out[20]), .A1N(n1192), .B0(n1190), .Y(
n504) );
OAI2BB1X1TS U1730 ( .A0N(d_ff3_LUT_out[22]), .A1N(n1192), .B0(n1191), .Y(
n502) );
OAI22X1TS U1731 ( .A0(n1198), .A1(n1229), .B0(n1206), .B1(n1194), .Y(n417)
);
OAI22X1TS U1732 ( .A0(n1193), .A1(n1226), .B0(n1207), .B1(n1195), .Y(n416)
);
OAI22X1TS U1733 ( .A0(n1198), .A1(n1233), .B0(n1208), .B1(n1194), .Y(n413)
);
OAI22X1TS U1734 ( .A0(n1200), .A1(n1230), .B0(n1209), .B1(n1195), .Y(n412)
);
OAI22X1TS U1735 ( .A0(n1200), .A1(n1234), .B0(n1210), .B1(n1194), .Y(n411)
);
OAI22X1TS U1736 ( .A0(n1200), .A1(n1232), .B0(n1219), .B1(n1195), .Y(n410)
);
OA22X1TS U1737 ( .A0(n1198), .A1(d_ff2_X[5]), .B0(d_ff_Xn[5]), .B1(n1196),
.Y(n389) );
OA22X1TS U1738 ( .A0(n1198), .A1(d_ff2_X[7]), .B0(d_ff_Xn[7]), .B1(n1196),
.Y(n385) );
OA22X1TS U1739 ( .A0(n1198), .A1(d_ff2_X[10]), .B0(d_ff_Xn[10]), .B1(n1196),
.Y(n379) );
OA22X1TS U1740 ( .A0(n1198), .A1(d_ff2_X[12]), .B0(d_ff_Xn[12]), .B1(n1197),
.Y(n375) );
OA22X1TS U1741 ( .A0(n1200), .A1(d_ff2_X[27]), .B0(d_ff_Xn[27]), .B1(n1199),
.Y(n349) );
AOI21X1TS U1742 ( .A0(d_ff2_X[29]), .A1(n1202), .B0(n1201), .Y(n1204) );
AOI22X1TS U1743 ( .A0(n1205), .A1(n1204), .B0(n1236), .B1(n1203), .Y(n339)
);
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_noclk.tcl_syn.sdf");
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_gtx_cpllpd_ovrd.v
// Version : 3.0
`timescale 1ns / 1ps
module pcie3_7x_0_gtx_cpllpd_ovrd (
input i_ibufds_gte2,
output o_cpllpd_ovrd,
output o_cpllreset_ovrd
);
(* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
(* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF;
always @(posedge i_ibufds_gte2)
begin
cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};
cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};
end
assign o_cpllpd_ovrd = cpllpd_wait[95];
assign o_cpllreset_ovrd = cpllreset_wait[127];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A22OI_FUNCTIONAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFINV_BLACKBOX_V
`define SKY130_FD_SC_HS__BUFINV_BLACKBOX_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__bufinv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFINV_BLACKBOX_V
|
module alu(
output reg [31:0] Z,
input [31:0] A,
input [31:0] B,
input [5:0] ALUFun,
input Sign
);
wire zero, overflow, negative;
wire [31:0] adder_out, comparer_out, logicer_out, shifter_out;
adder adder1(.Z (zero),
.V (overflow),
.N (negative),
.dout(adder_out),
.A (A),
.B (B),
.ctrl(ALUFun[0]),
.Sign(Sign));
comparer comparer1(.dout(comparer_out),
.Z (zero),
.V (overflow),
.N (negative),
.ctrl(ALUFun[3:1]));
logicer logicer1(.dout(logicer_out),
.A (A),
.B (B),
.ctrl(ALUFun[3:0]));
shifter shifter1(.dout(shifter_out),
.A (A),
.B (B),
.ctrl(ALUFun[1:0]));
always @(*) begin
case (ALUFun[5:4])
2'b00: Z = adder_out;
2'b11: Z = comparer_out;
2'b01: Z = logicer_out;
2'b10: Z = shifter_out;
default: Z = 0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O22AI_PP_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o22ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:11 11/29/2014
// Design Name:
// Module Name: FuncionActivacion
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FuncionActivacion #(parameter Width = 32, ConLimitador=0,Magnitud = 7, Precision = 24, Signo = 1, A00= 0,
A01= 1, A02 = 2, A03 = 3, A04 = 4, A05 = 5, A06 = 6, A07 = 7, A08 = 8, A09 = 9,
A10= 10, A11= 11, A12 = 12, A13 = 13, A14 = 14, A15 = 15, A16 = 16, A17 = 17, A18 = 18, A19 = 19,
A20= 20, A21= 21,A22 = 22, A23 = 23, A24 = 24, A25 = 25, A26 = 26, A27 = 27, A28 = 28, A29 = 29,
A30 = 30, M01= 1,
M02 = 2, M03 = 3, M04 = 4, M05 = 5, M06 = 6, M07 = 7, M08 = 8, M09 = 9,
M10= 10, M11= 11, M12 = 12, M13 = 13, M14 = 14, M15 = 15, M16 = 16, M17 = 17, M18 = 18, M19 = 19,
M20= 20, M21= 21,M22 = 22, M23 = 23, M24 = 24, M25 = 25, M26 = 26, M27 = 27, M28 = 28, M29 = 29,
M30 = 30,B01= 1,
B02 = 2, B03 = 3, B04 = 4, B05 = 5, B06 = 6, B07 = 7, B08 = 8, B09 = 9,
B10= 10, B11= 11, B12 = 12, B13 = 13, B14 = 14, B15 = 15, B16 = 16, B17 = 17, B18 = 18, B19 = 19,
B20= 20, B21= 21,B22 = 22, B23 = 23, B24 = 24, B25 = 25, B26 = 26, B27 = 27, B28 = 28, B29 = 29,
B30 = 30)
(Entrada,Enable,Error,Salida);
input signed [Width-1:0] Entrada;
input Enable;
output Error;
output signed [Width-1:0] Salida;
wire [4:0] SELMUX;
wire signed [Width-1:0] M,B,OutALU;
Comparador #( .Width(Width) , .A00(A00), .A01(A01),.A02(A02), .A03(A03), .A04(A04), .A05(A05),
.A06(A06), .A07(A07), .A08(A08), .A09(A09),.A10(A10), .A11(A11), .A12(A12), .A13(A13), .A14(A14),
.A15(A15), .A16(A16), .A17(A17), .A18(A18), .A19(A19),.A20(A20), .A21(A21),.A22(A22), .A23(A23),
.A24(A24), .A25(A25), .A26(A26), .A27(A27), .A28(A28), .A29(A29), .A30(A30))
COmparadorcopia (
.A(Entrada),
.OutComp(SELMUX)
);
multiplexor32a1 #(.Width(Width)) multiplexor32a1coeffPendientes (
.coeff00(32'sb00000000000000000000000000000000),
.coeff01(M01),
.coeff02(M02),
.coeff03(M03),
.coeff04(M04),
.coeff05(M05),
.coeff06(M06),
.coeff07(M07),
.coeff08(M08),
.coeff09(M09),
.coeff10(M10),
.coeff11(M11),
.coeff12(M12),
.coeff13(M13),
.coeff14(M14),
.coeff15(M15),
.coeff16(M16),
.coeff17(M17),
.coeff18(M18),
.coeff19(M19),
.coeff20(M20),
.coeff21(M21),
.coeff22(M22),
.coeff23(M23),
.coeff24(M24),
.coeff25(M25),
.coeff26(M26),
.coeff27(M27),
.coeff28(M28),
.coeff29(M29),
.coeff30(M30),
.coeff31(32'sb00000000000000000000000000000000),
.SEL(SELMUX),
.outMUX(M)
);
multiplexor32a1 #(.Width(Width)) multiplexor32a1coeffInterseccion (
.coeff00(32'sb00000000000000000000000000000000),
.coeff01(B01),
.coeff02(B02),
.coeff03(B03),
.coeff04(B04),
.coeff05(B05),
.coeff06(B06),
.coeff07(B07),
.coeff08(B08),
.coeff09(B09),
.coeff10(B10),
.coeff11(B11),
.coeff12(B12),
.coeff13(B13),
.coeff14(B14),
.coeff15(B15),
.coeff16(B16),
.coeff17(B17),
.coeff18(B18),
.coeff19(B19),
.coeff20(B20),
.coeff21(B21),
.coeff22(B22),
.coeff23(B23),
.coeff24(B24),
.coeff25(B25),
.coeff26(B26),
.coeff27(B27),
.coeff28(B28),
.coeff29(B29),
.coeff30(B30),
.coeff31(32'sb00000001000000000000000000000000),
.SEL(SELMUX),
.outMUX(B)
);
ALUfuncionActivacion #(.Width(Width), .Magnitud(Magnitud), .Precision(Precision),.Signo(Signo))
ALUfuncionActivacioncopia (
.SELMUX(SELMUX),
.Enable(Enable),
.M(M),
.B(B),
.In(Entrada),
.Out(OutALU),
.Error(Error)
);
generate
if (ConLimitador) begin: CodigoConLimitadoralaSalidaEntre0y1
LimitadorSalidaFuctActivacion #(.Width(Width)) LimitadorSalidaFuctActivacion1 (
.inData(OutALU),
.OutData(Salida)
);
end else begin: CodigoSinLimitadoralaSalidaEntre0y1
assign Salida = OutALU;
end
endgenerate
endmodule
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_valid,
F_pcb,
F_valid,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 21: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_valid;
input [ 71: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 26: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 21: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_is_opx_inst;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_op_rsv02;
wire D_op_op_rsv09;
wire D_op_op_rsv10;
wire D_op_op_rsv17;
wire D_op_op_rsv18;
wire D_op_op_rsv25;
wire D_op_op_rsv26;
wire D_op_op_rsv33;
wire D_op_op_rsv34;
wire D_op_op_rsv41;
wire D_op_op_rsv42;
wire D_op_op_rsv49;
wire D_op_op_rsv57;
wire D_op_op_rsv61;
wire D_op_op_rsv62;
wire D_op_op_rsv63;
wire D_op_opx_rsv00;
wire D_op_opx_rsv10;
wire D_op_opx_rsv15;
wire D_op_opx_rsv17;
wire D_op_opx_rsv21;
wire D_op_opx_rsv25;
wire D_op_opx_rsv33;
wire D_op_opx_rsv34;
wire D_op_opx_rsv35;
wire D_op_opx_rsv42;
wire D_op_opx_rsv43;
wire D_op_opx_rsv44;
wire D_op_opx_rsv47;
wire D_op_opx_rsv50;
wire D_op_opx_rsv51;
wire D_op_opx_rsv55;
wire D_op_opx_rsv56;
wire D_op_opx_rsv60;
wire D_op_opx_rsv63;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_op_rsv02 = D_iw_op == 2;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_op_rsv09 = D_iw_op == 9;
assign D_op_op_rsv10 = D_iw_op == 10;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_op_rsv17 = D_iw_op == 17;
assign D_op_op_rsv18 = D_iw_op == 18;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_op_rsv25 = D_iw_op == 25;
assign D_op_op_rsv26 = D_iw_op == 26;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_op_rsv33 = D_iw_op == 33;
assign D_op_op_rsv34 = D_iw_op == 34;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_op_rsv41 = D_iw_op == 41;
assign D_op_op_rsv42 = D_iw_op == 42;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_op_rsv49 = D_iw_op == 49;
assign D_op_custom = D_iw_op == 50;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_op_rsv57 = D_iw_op == 57;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_op_rsv61 = D_iw_op == 61;
assign D_op_op_rsv62 = D_iw_op == 62;
assign D_op_op_rsv63 = D_iw_op == 63;
assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
assign D_is_opx_inst = D_iw_op == 58;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: wasca_nios2_gen2_0_cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: wasca_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_random.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_random.v,v $
// Revision 1.4 2003/06/13 11:26:08 mohor
// Binary operator used instead of unary (xnor).
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
//
`include "timescale.v"
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt);
parameter Tp = 1;
input MTxClk;
input Reset;
input StateJam;
input StateJam_q;
input [3:0] RetryCnt;
input [15:0] NibCnt;
input [9:0] ByteCnt;
output RandomEq0;
output RandomEqByteCnt;
wire Feedback;
reg [9:0] x;
wire [9:0] Random;
reg [9:0] RandomLatched;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
x[9:0] <= #Tp 0;
else
x[9:0] <= #Tp {x[8:0], Feedback};
end
assign Feedback = ~(x[2] ^ x[9]);
assign Random [0] = x[0];
assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RandomLatched <= #Tp 10'h000;
else
begin
if(StateJam & StateJam_q)
RandomLatched <= #Tp Random;
end
end
// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
assign RandomEq0 = RandomLatched == 10'h0;
assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_TB_V
/**
* udp_dff$NR_pp$PKG$s: Negative edge triggered D flip-flop with
* active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_nr_pp_pkg_s.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 RESET = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 RESET = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 RESET = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 RESET = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 RESET = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__udp_dff$NR_pp$PKG$s dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O2BB2A_BEHAVIORAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND2_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_SYMBOL_V
|
/*!
* <b>Module:</b>sata_ahci_top
* @file sata_ahci_top.v
* @date 2015-07-11
* @author Alexey
*
* @brief Top of the AHCI implementation of the host adapter
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* sata_ahci_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sata_ahci_top.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
/*
* Takes commands from axi iface as a slave, transfers data with another axi iface as a master
*/
module sata_ahci_top#(
parameter PREFETCH_ALWAYS = 0,
// parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
// parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
`ifdef USE_DATASCOPE
parameter DATASCOPE_START_BIT = 14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
parameter DATASCOPE_POST_MEAS = 256, // 16, // number of measurements to perform after event
`endif
parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
parameter RESET_TO_FIRST_ACCESS = 1, // keep port reset until first R/W any register by software
parameter BITS_TO_START_XMIT = 6, // wait H2D FIFO to have 1 << BITS_TO_START_XMIT to start FIS transmission (or all FIS fits)
parameter DATA_BYTE_WIDTH = 4,
parameter ELASTIC_DEPTH = 4, // 4, //5, With 4/7 got infrequent overflows!
parameter ELASTIC_OFFSET = 7, // 5 //10
parameter FREQ_METER_WIDTH = 16
)(
output wire sata_clk,
output wire sata_rst,
input wire arst, // extrst,
// reliable clock to source drp and cpll lock det circuits
input wire reliable_clk,
input wire hclk,
/*
* Commands interface
*/
input wire ACLK, // AXI PS Master GP1 Clock , input
input wire ARESETN, // AXI PS Master GP1 Reset, output // @SuppressThisWarning VEditor unused (arst instead)
// AXI PS Master GP1: Read Address
input wire [31:0] ARADDR, // AXI PS Master GP1 ARADDR[31:0], output
input wire ARVALID, // AXI PS Master GP1 ARVALID, output
output wire ARREADY, // AXI PS Master GP1 ARREADY, input
input wire [11:0] ARID, // AXI PS Master GP1 ARID[11:0], output
input wire [3:0] ARLEN, // AXI PS Master GP1 ARLEN[3:0], output
input wire [1:0] ARSIZE, // AXI PS Master GP1 ARSIZE[1:0], output
input wire [1:0] ARBURST, // AXI PS Master GP1 ARBURST[1:0], output
// AXI PS Master GP1: Read Data
output wire [31:0] RDATA, // AXI PS Master GP1 RDATA[31:0], input
output wire RVALID, // AXI PS Master GP1 RVALID, input
input wire RREADY, // AXI PS Master GP1 RREADY, output
output wire [11:0] RID, // AXI PS Master GP1 RID[11:0], input
output wire RLAST, // AXI PS Master GP1 RLAST, input
output wire [1:0] RRESP, // AXI PS Master GP1 RRESP[1:0], input
// AXI PS Master GP1: Write Address
input wire [31:0] AWADDR, // AXI PS Master GP1 AWADDR[31:0], output
input wire AWVALID, // AXI PS Master GP1 AWVALID, output
output wire AWREADY, // AXI PS Master GP1 AWREADY, input
input wire [11:0] AWID, // AXI PS Master GP1 AWID[11:0], output
input wire [3:0] AWLEN, // AXI PS Master GP1 AWLEN[3:0], outpu:t
input wire [1:0] AWSIZE, // AXI PS Master GP1 AWSIZE[1:0], output
input wire [1:0] AWBURST, // AXI PS Master GP1 AWBURST[1:0], output
// AXI PS Master GP1: Write Data
input wire [31:0] WDATA, // AXI PS Master GP1 WDATA[31:0], output
input wire WVALID, // AXI PS Master GP1 WVALID, output
output wire WREADY, // AXI PS Master GP1 WREADY, input
input wire [11:0] WID, // AXI PS Master GP1 WID[11:0], output
input wire WLAST, // AXI PS Master GP1 WLAST, output
input wire [3:0] WSTRB, // AXI PS Master GP1 WSTRB[3:0], output
// AXI PS Master GP1: Write response
output wire BVALID, // AXI PS Master GP1 BVALID, input
input wire BREADY, // AXI PS Master GP1 BREADY, output
output wire [11:0] BID, // AXI PS Master GP1 BID[11:0], input
output wire [1:0] BRESP, // AXI PS Master GP1 BRESP[1:0], input
/*
* Data interface
*/
output wire [31:0] afi_awaddr,
output wire afi_awvalid,
input wire afi_awready,
output wire [5:0] afi_awid,
output wire [1:0] afi_awlock,
output wire [3:0] afi_awcache,
output wire [2:0] afi_awprot,
output wire [3:0] afi_awlen,
output wire [1:0] afi_awsize,
output wire [1:0] afi_awburst,
output wire [3:0] afi_awqos,
// write data
output wire [63:0] afi_wdata,
output wire afi_wvalid,
input wire afi_wready,
output wire [5:0] afi_wid,
output wire afi_wlast,
output wire [7:0] afi_wstrb,
// write response
input wire afi_bvalid,
output wire afi_bready,
input wire [5:0] afi_bid,
input wire [1:0] afi_bresp,
// PL extra (non-AXI) signals
input wire [7:0] afi_wcount,
input wire [5:0] afi_wacount,
output wire afi_wrissuecap1en,
// AXI_HP signals - read channel
// read address
output wire [31:0] afi_araddr,
output wire afi_arvalid,
input wire afi_arready,
output wire [5:0] afi_arid,
output wire [1:0] afi_arlock,
output wire [3:0] afi_arcache,
output wire [2:0] afi_arprot,
output wire [3:0] afi_arlen,
output wire [1:0] afi_arsize,
output wire [1:0] afi_arburst,
output wire [3:0] afi_arqos,
// read data
input wire [63:0] afi_rdata,
input wire afi_rvalid,
output wire afi_rready,
input wire [5:0] afi_rid,
input wire afi_rlast,
input wire [1:0] afi_rresp,
// PL extra (non-AXI) signals
input wire [7:0] afi_rcount,
input wire [2:0] afi_racount,
output wire afi_rdissuecap1en,
output wire irq,
/*
* PHY
*/
output wire TXN,
output wire TXP,
input wire RXN,
input wire RXP,
input wire EXTCLK_P,
input wire EXTCLK_N
);
// wire sata_clk;
// wire sata_rst;
wire hba_arst; // @S uppressThisWarning VEditor unused
wire port_arst; // @SuppressThisWarning VEditor unused
wire port_arst_any;
// wire exrst = port_arst_any; // now both hba_arst and port_arst are the same?
wire exrst = port_arst_any || hba_arst; // now both hba_arst and port_arst are the same (only difference in fsm)
// Data/type FIFO, host -> device
// Data System memory or FIS -> device
wire [31:0] h2d_data; // 32-bit data from the system memory to HBA (dma data)
wire [ 1:0] h2d_type; // 0 - data, 1 - FIS head, 2 - FIS END (make FIS_Last?)
wire h2d_valid; // output register full
wire h2d_ready; // send FIFO has room for data (>= 8? dwords)
// Data/type FIFO, device -> host
wire [31:0] d2h_data; // FIFO output data
wire [ 1:0] d2h_type; // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR
wire d2h_valid; // Data available from the transport layer in FIFO
wire d2h_many; // Multiple DWORDs available from the transport layer in FIFO
wire d2h_ready; // This module or DMA consumes DWORD
// communication with transport/link/phys layers
// wire phy_rst; // frome phy, as a response to hba_arst || port_arst. It is deasserted when clock is stable
wire [ 1:0] phy_speed; // 0 - not ready, 1..3 - negotiated speed
wire xmit_ok; // FIS transmission acknowledged OK
wire xmit_err; // Error during sending of a FIS
wire syncesc_recv; // These two inputs interrupt transmit
wire pcmd_st_cleared; // bit was cleared by software
wire syncesc_send; // Send sync escape
wire syncesc_send_done; // "SYNC escape until the interface is quiescent..."
wire comreset_send; // Not possible yet?
wire cominit_got;
wire set_offline; // electrically idle
wire x_rdy_collision; // X_RDY/X_RDY collision on interface
wire send_R_OK; // Should it be originated in this layer SM?
wire send_R_ERR;
// additional errors from SATA layers (single-clock pulses):
wire serr_DT; // RWC: Transport state transition error
wire serr_DS; // RWC: Link sequence error
wire serr_DH; // RWC: Handshake Error (i.e. Device got CRC error)
wire serr_DC; // RWC: CRC error in Link layer
wire serr_DB; // RWC: 10B to 8B decode error
wire serr_DW; // RWC: COMMWAKE signal was detected
wire serr_DI; // RWC: PHY Internal Error
// sirq_PRC,
wire serr_EE; // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
wire serr_EP; // RWC: Protocol Error - a violation of SATA protocol detected
wire serr_EC; // RWC: Persistent Communication or Data Integrity Error
wire serr_ET; // RWC: Transient Data Integrity Error (error not recovered by the interface)
wire serr_EM; // RWC: Communication between the device and host was lost but re-established
wire serr_EI; // RWC: Recovered Data integrity Error
// additional control signals for SATA layers
wire [3:0] sctl_ipm; // Interface power management transitions allowed
wire [3:0] sctl_spd; // Interface maximal speed
reg [2:0] nhrst_r;
wire hrst = !nhrst_r[2];
wire debug_link_send_data; // @sata clk - last symbol was data output
wire debug_link_dmatp; // @clk (sata clk) - received CODE_DMATP
wire [FREQ_METER_WIDTH-1:0] xclk_period;
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
wire datascope_clk;
wire [ADDRESS_BITS-1:0] datascope_waddr;
wire datascope_we;
wire [31:0] datascope_di;
`endif
`ifdef USE_DRP
wire drp_en;
wire drp_we;
wire [14:0] drp_addr;
wire [15:0] drp_di;
wire drp_rdy;
wire [15:0] drp_do;
`endif
wire [31:0] debug_phy;
wire [31:0] debug_link;
always @ (posedge hclk or posedge arst) begin
if (arst) nhrst_r <= 0;
else nhrst_r <= (nhrst_r << 1) | 1;
end
ahci_top #(
.PREFETCH_ALWAYS (PREFETCH_ALWAYS),
// .READ_REG_LATENCY (READ_REG_LATENCY),
// .READ_CT_LATENCY (READ_CT_LATENCY),
.ADDRESS_BITS (ADDRESS_BITS),
.HBA_RESET_BITS (HBA_RESET_BITS),
.RESET_TO_FIRST_ACCESS (RESET_TO_FIRST_ACCESS),
.FREQ_METER_WIDTH (FREQ_METER_WIDTH)
) ahci_top_i (
.aclk (ACLK), // input
.arst (arst), // input
.mclk (sata_clk), // input
.mrst (sata_rst), // input
.hba_arst (hba_arst), // output
.port_arst (port_arst), // output
.port_arst_any (port_arst_any), // port0 async set by software and by arst
.hclk (hclk), // input
.hrst (hrst), // input
.awaddr (AWADDR), // input[31:0]
.awvalid (AWVALID), // input
.awready (AWREADY), // output
.awid (AWID), // input[11:0]
.awlen (AWLEN), // input[3:0]
.awsize (AWSIZE), // input[1:0]
.awburst (AWBURST), // input[1:0]
.wdata (WDATA), // input[31:0]
.wvalid (WVALID), // input
.wready (WREADY), // output
.wid (WID), // input[11:0]
.wlast (WLAST), // input
.wstb (WSTRB), // input[3:0]
.bvalid (BVALID), // output
.bready (BREADY), // input
.bid (BID), // output[11:0]
.bresp (BRESP), // output[1:0]
.araddr (ARADDR), // input[31:0]
.arvalid (ARVALID), // input
.arready (ARREADY), // output
.arid (ARID), // input[11:0]
.arlen (ARLEN), // input[3:0]
.arsize (ARSIZE), // input[1:0]
.arburst (ARBURST), // input[1:0]
.rdata (RDATA), // output[31:0]
.rvalid (RVALID), // output
.rready (RREADY), // input
.rid (RID), // output[11:0]
.rlast (RLAST), // output
.rresp (RRESP), // output[1:0]
.afi_awaddr (afi_awaddr), // output[31:0]
.afi_awvalid (afi_awvalid), // output
.afi_awready (afi_awready), // input
.afi_awid (afi_awid), // output[5:0]
.afi_awlock (afi_awlock), // output[1:0]
.afi_awcache (afi_awcache), // output[3:0]
.afi_awprot (afi_awprot), // output[2:0]
.afi_awlen (afi_awlen), // output[3:0]
.afi_awsize (afi_awsize), // output[1:0]
.afi_awburst (afi_awburst), // output[1:0]
.afi_awqos (afi_awqos), // output[3:0]
.afi_wdata (afi_wdata), // output[63:0]
.afi_wvalid (afi_wvalid), // output
.afi_wready (afi_wready), // input
.afi_wid (afi_wid), // output[5:0]
.afi_wlast (afi_wlast), // output
.afi_wstrb (afi_wstrb), // output[7:0]
.afi_bvalid (afi_bvalid), // input
.afi_bready (afi_bready), // output
.afi_bid (afi_bid), // input[5:0]
.afi_bresp (afi_bresp), // input[1:0]
.afi_wcount (afi_wcount), // input[7:0]
.afi_wacount (afi_wacount), // input[5:0]
.afi_wrissuecap1en (afi_wrissuecap1en), // output
.afi_araddr (afi_araddr), // output[31:0]
.afi_arvalid (afi_arvalid), // output
.afi_arready (afi_arready), // input
.afi_arid (afi_arid), // output[5:0]
.afi_arlock (afi_arlock), // output[1:0]
.afi_arcache (afi_arcache), // output[3:0]
.afi_arprot (afi_arprot), // output[2:0]
.afi_arlen (afi_arlen), // output[3:0]
.afi_arsize (afi_arsize), // output[1:0]
.afi_arburst (afi_arburst), // output[1:0]
.afi_arqos (afi_arqos), // output[3:0]
.afi_rdata (afi_rdata), // input[63:0]
.afi_rvalid (afi_rvalid), // input
.afi_rready (afi_rready), // output
.afi_rid (afi_rid), // input[5:0]
.afi_rlast (afi_rlast), // input
.afi_rresp (afi_rresp), // input[1:0]
.afi_rcount (afi_rcount), // input[7:0]
.afi_racount (afi_racount), // input[2:0]
.afi_rdissuecap1en (afi_rdissuecap1en), // output
.h2d_data (h2d_data), // output[31:0]
.h2d_type (h2d_type), // output[1:0]
.h2d_valid (h2d_valid), // output
.h2d_ready (h2d_ready), // input
.d2h_data (d2h_data), // input[31:0]
.d2h_type (d2h_type), // input[1:0]
.d2h_valid (d2h_valid), // input
.d2h_many (d2h_many), // input
.d2h_ready (d2h_ready), // output
.phy_ready (phy_speed), // input[1:0]
.xmit_ok (xmit_ok), // input
.xmit_err (xmit_err), // input
.syncesc_recv (syncesc_recv), // input
.pcmd_st_cleared (pcmd_st_cleared), // output
.syncesc_send (syncesc_send), // output
.syncesc_send_done (syncesc_send_done), // input
.comreset_send (comreset_send), // output
.cominit_got (cominit_got), // input
.set_offline (set_offline), // output
.x_rdy_collision (x_rdy_collision), // input
.send_R_OK (send_R_OK), // output
.send_R_ERR (send_R_ERR), // output
.serr_DT (serr_DT), // input
.serr_DS (serr_DS), // input
.serr_DH (serr_DH), // input
.serr_DC (serr_DC), // input
.serr_DB (serr_DB), // input
.serr_DW (serr_DW), // input
.serr_DI (serr_DI), // input
.serr_EE (serr_EE), // input
.serr_EP (serr_EP), // input
.serr_EC (serr_EC), // input
.serr_ET (serr_ET), // input
.serr_EM (serr_EM), // input
.serr_EI (serr_EI), // input
.sctl_ipm (sctl_ipm), // output[3:0]
.sctl_spd (sctl_spd), // output[3:0]
.irq (irq), // output
.debug_link_send_data (debug_link_send_data), // input @posedge sata_clk - last symbol was data output (to count sent out)
.debug_link_dmatp (debug_link_dmatp), // link received DMATp from device
`ifdef USE_DATASCOPE
.datascope1_clk (datascope_clk), // input
.datascope1_waddr (datascope_waddr), // input[9:0]
.datascope1_we (datascope_we), // input
.datascope1_di (datascope_di), // input[31:0]
`endif
`ifdef USE_DRP
.drp_en (drp_en), // output reg
.drp_we (drp_we), // output reg
.drp_addr (drp_addr), // output[14:0] reg
.drp_di (drp_di), // output[15:0] reg
.drp_rdy (drp_rdy), // input
.drp_do (drp_do), // input[15:0]
`endif
.xclk_period (xclk_period), // input[11:0]
.debug_in_phy (debug_phy), // input[31:0]
.debug_in_link (debug_link) // input[31:0]
);
ahci_sata_layers #(
`ifdef USE_DATASCOPE
.ADDRESS_BITS (ADDRESS_BITS), // for datascope
.DATASCOPE_START_BIT (DATASCOPE_START_BIT), // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS), // number of measurements to perform after event
`endif
.BITS_TO_START_XMIT (BITS_TO_START_XMIT),
.DATA_BYTE_WIDTH (DATA_BYTE_WIDTH),
.ELASTIC_DEPTH (ELASTIC_DEPTH),
.ELASTIC_OFFSET (ELASTIC_OFFSET),
.FREQ_METER_WIDTH (FREQ_METER_WIDTH)
) ahci_sata_layers_i (
.exrst (exrst), // input
.reliable_clk (reliable_clk), // input
.rst (sata_rst), // output
.clk (sata_clk), // output
.h2d_data (h2d_data), // input[31:0]
.h2d_mask (2'h3), //h2d_mask), // input[1:0]
.h2d_type (h2d_type), // input[1:0]
.h2d_valid (h2d_valid), // input
.h2d_ready (h2d_ready), // output
.d2h_data (d2h_data), // output[31:0]
.d2h_mask (), // 2h_mask), // output[1:0]
.d2h_type (d2h_type), // output[1:0]
.d2h_valid (d2h_valid), // output
.d2h_many (d2h_many), // output
.d2h_ready (d2h_ready), // input
.phy_speed (phy_speed), // output[1:0]
.gtx_ready(), // output
.xmit_ok (xmit_ok), // output
.xmit_err (xmit_err), // output
.x_rdy_collision (x_rdy_collision), // output
.syncesc_recv (syncesc_recv), // output
.pcmd_st_cleared (pcmd_st_cleared), // input
.syncesc_send (syncesc_send), // input
.syncesc_send_done (syncesc_send_done), // output
.comreset_send (comreset_send), // input
.cominit_got (cominit_got), // output
.set_offline (set_offline), // input
.send_R_OK (send_R_OK), // input
.send_R_ERR (send_R_ERR), // input
.serr_DT (serr_DT), // output
.serr_DS (serr_DS), // output
.serr_DH (serr_DH), // output
.serr_DC (serr_DC), // output
.serr_DB (serr_DB), // output
.serr_DW (serr_DW), // output
.serr_DI (serr_DI), // output
.serr_EE (serr_EE), // output
.serr_EP (serr_EP), // output
.serr_EC (serr_EC), // output
.serr_ET (serr_ET), // output
.serr_EM (serr_EM), // output
.serr_EI (serr_EI), // output
.sctl_ipm (sctl_ipm), // input[3:0]
.sctl_spd (sctl_spd), // input[3:0]
.extclk_p (EXTCLK_P), // input wire
.extclk_n (EXTCLK_N), // input wire
.txp_out (TXP), // output wire
.txn_out (TXN), // output wire
.rxp_in (RXP), // input wire
.rxn_in (RXN), // input wire
.debug_is_data (debug_link_send_data), //output @clk (sata clk) - last symbol was data output
.debug_dmatp (debug_link_dmatp), // @clk (sata clk) - received CODE_DMATP
`ifdef USE_DATASCOPE
.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output
.datascope_di (datascope_di), // output[31:0]
`endif
`ifdef USE_DRP
.drp_rst (arst), // input
.drp_clk (ACLK), // input
.drp_en (drp_en), // input
.drp_we (drp_we), // input
.drp_addr (drp_addr), // input[14:0]
.drp_di (drp_di), // input[15:0]
.drp_rdy (drp_rdy), // output
.drp_do (drp_do), // output[15:0]
`endif
.xclk_period (xclk_period), // output[11:0]
.debug_phy (debug_phy), // output[31:0]
.debug_link (debug_link) // output[31:0]
,.hclk(hclk)
);
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module fmlarb #(
parameter fml_depth = 26,
parameter fml_width = 32
) (
input sys_clk,
input sys_rst,
/* Interface 0 has higher priority than the others */
input [fml_depth-1:0] m0_adr,
input m0_stb,
input m0_we,
output m0_ack,
input [fml_width/8-1:0] m0_sel,
input [fml_width-1:0] m0_di,
output [fml_width-1:0] m0_do,
input [fml_depth-1:0] m1_adr,
input m1_stb,
input m1_we,
output m1_ack,
input [fml_width/8-1:0] m1_sel,
input [fml_width-1:0] m1_di,
output [fml_width-1:0] m1_do,
input [fml_depth-1:0] m2_adr,
input m2_stb,
input m2_we,
output m2_ack,
input [fml_width/8-1:0] m2_sel,
input [fml_width-1:0] m2_di,
output [fml_width-1:0] m2_do,
input [fml_depth-1:0] m3_adr,
input m3_stb,
input m3_we,
output m3_ack,
input [fml_width/8-1:0] m3_sel,
input [fml_width-1:0] m3_di,
output [fml_width-1:0] m3_do,
input [fml_depth-1:0] m4_adr,
input m4_stb,
input m4_we,
output m4_ack,
input [fml_width/8-1:0] m4_sel,
input [fml_width-1:0] m4_di,
output [fml_width-1:0] m4_do,
input [fml_depth-1:0] m5_adr,
input m5_stb,
input m5_we,
output m5_ack,
input [fml_width/8-1:0] m5_sel,
input [fml_width-1:0] m5_di,
output [fml_width-1:0] m5_do,
output reg [fml_depth-1:0] s_adr,
output reg s_stb,
output reg s_we,
input s_eack,
output reg [fml_width/8-1:0] s_sel,
input [fml_width-1:0] s_di,
output reg [fml_width-1:0] s_do
);
assign m0_do = s_di;
assign m1_do = s_di;
assign m2_do = s_di;
assign m3_do = s_di;
assign m4_do = s_di;
assign m5_do = s_di;
wire m0_stbm;
wire m1_stbm;
wire m2_stbm;
wire m3_stbm;
wire m4_stbm;
wire m5_stbm;
reg [2:0] master;
reg [2:0] next_master;
always @(posedge sys_clk) begin
if(sys_rst)
master <= 3'd0;
else
master <= next_master;
end
/* Decide the next master */
always @(*) begin
/* By default keep our current master */
next_master = master;
case(master)
3'd0: if(~m0_stbm | s_eack) begin
if(m0_stbm | m0_stb) next_master = 3'd0;
else if(m1_stbm) next_master = 3'd1;
else if(m2_stbm) next_master = 3'd2;
else if(m3_stbm) next_master = 3'd3;
else if(m4_stbm) next_master = 3'd4;
else if(m5_stbm) next_master = 3'd5;
end
3'd1: if(~m1_stbm | s_eack) begin
if(m0_stbm) next_master = 3'd0;
else if(m3_stbm) next_master = 3'd3;
else if(m4_stbm) next_master = 3'd4;
else if(m5_stbm) next_master = 3'd5;
else if(m2_stbm) next_master = 3'd2;
end
3'd2: if(~m2_stbm | s_eack) begin
if(m0_stbm) next_master = 3'd0;
else if(m3_stbm) next_master = 3'd3;
else if(m4_stbm) next_master = 3'd4;
else if(m5_stbm) next_master = 3'd5;
else if(m1_stbm) next_master = 3'd1;
end
3'd3: if(~m3_stbm | s_eack) begin
if(m0_stbm) next_master = 3'd0;
else if(m4_stbm) next_master = 3'd4;
else if(m5_stbm) next_master = 3'd5;
else if(m1_stbm) next_master = 3'd1;
else if(m2_stbm) next_master = 3'd2;
end
3'd4: if(~m4_stbm | s_eack) begin
if(m0_stbm) next_master = 3'd0;
else if(m5_stbm) next_master = 3'd5;
else if(m1_stbm) next_master = 3'd1;
else if(m2_stbm) next_master = 3'd2;
else if(m3_stbm) next_master = 3'd3;
end
default: if(~m5_stbm | s_eack) begin // 3'd5
if(m0_stbm) next_master = 3'd0;
else if(m1_stbm) next_master = 3'd1;
else if(m2_stbm) next_master = 3'd2;
else if(m3_stbm) next_master = 3'd3;
else if(m4_stbm) next_master = 3'd4;
end
endcase
end
/* Mux control signals */
always @(*) begin
case(master)
3'd0: begin
s_adr = m0_adr;
s_stb = m0_stbm;
s_we = m0_we;
end
3'd1: begin
s_adr = m1_adr;
s_stb = m1_stbm;
s_we = m1_we;
end
3'd2: begin
s_adr = m2_adr;
s_stb = m2_stbm;
s_we = m2_we;
end
3'd3: begin
s_adr = m3_adr;
s_stb = m3_stbm;
s_we = m3_we;
end
3'd4: begin
s_adr = m4_adr;
s_stb = m4_stbm;
s_we = m4_we;
end
default: begin // 3'd5
s_adr = m5_adr;
s_stb = m5_stbm;
s_we = m5_we;
end
endcase
end
/* Generate delayed ack signals and masked strobes */
fmlarb_dack dack0(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m0_stb), .eack((master == 3'd0) & s_eack), .we(m0_we),
.stbm(m0_stbm), .ack(m0_ack));
fmlarb_dack dack1(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m1_stb), .eack((master == 3'd1) & s_eack), .we(m1_we),
.stbm(m1_stbm), .ack(m1_ack));
fmlarb_dack dack2(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m2_stb), .eack((master == 3'd2) & s_eack), .we(m2_we),
.stbm(m2_stbm), .ack(m2_ack));
fmlarb_dack dack3(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m3_stb), .eack((master == 3'd3) & s_eack), .we(m3_we),
.stbm(m3_stbm), .ack(m3_ack));
fmlarb_dack dack4(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m4_stb), .eack((master == 3'd4) & s_eack), .we(m4_we),
.stbm(m4_stbm), .ack(m4_ack));
fmlarb_dack dack5(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m5_stb), .eack((master == 3'd5) & s_eack), .we(m5_we),
.stbm(m5_stbm), .ack(m5_ack));
/* Mux data write signals */
reg [2:0] wmaster;
always @(posedge sys_clk) begin
if(sys_rst)
wmaster <= 3'd0;
else if(s_we & s_eack)
wmaster <= master;
end
always @(*) begin
case(wmaster)
3'd0: begin
s_do = m0_di;
s_sel = m0_sel;
end
3'd1: begin
s_do = m1_di;
s_sel = m1_sel;
end
3'd2: begin
s_do = m2_di;
s_sel = m2_sel;
end
3'd3: begin
s_do = m3_di;
s_sel = m3_sel;
end
3'd4: begin
s_do = m4_di;
s_sel = m4_sel;
end
default: begin // 3'd5
s_do = m5_di;
s_sel = m5_sel;
end
endcase
end
endmodule
|
module user_io(
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
input [7:0] CORE_TYPE,
output [7:0] JOY0,
output [7:0] JOY1,
output [2:0] MOUSE_BUTTONS,
output KBD_MOUSE_STROBE,
output KMS_LEVEL,
output [1:0] KBD_MOUSE_TYPE,
output [7:0] KBD_MOUSE_DATA,
output [1:0] BUTTONS,
output [1:0] SWITCHES,
output [3:0] CONF
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [5:0] cnt;
reg [7:0] joystick0;
reg [7:0] joystick1;
reg [7:0] but_sw;
reg kbd_mouse_strobe;
reg kbd_mouse_strobe_level;
reg [1:0] kbd_mouse_type;
reg [7:0] kbd_mouse_data;
reg [2:0] mouse_buttons;
assign JOY0 = joystick0;
assign JOY1 = joystick1;
assign KBD_MOUSE_DATA = kbd_mouse_data; // 8 bit movement data
assign KBD_MOUSE_TYPE = kbd_mouse_type; // 0=mouse x,1=mouse y, 2=keycode, 3=OSD kbd
assign KBD_MOUSE_STROBE = kbd_mouse_strobe; // strobe, data valid on rising edge
assign KMS_LEVEL = kbd_mouse_strobe_level; // level change of kbd_mouse_strobe
assign MOUSE_BUTTONS = mouse_buttons; // state of the two mouse buttons
assign BUTTONS = but_sw[1:0];
assign SWITCHES = but_sw[3:2];
assign CONF = but_sw[7:4];
always@(negedge SPI_CLK) begin
if(cnt < 8)
SPI_MISO <= CORE_TYPE[7-cnt];
end
always@(posedge SPI_CLK) begin
kbd_mouse_strobe_level <= #1 kbd_mouse_strobe_level ^ kbd_mouse_strobe;
if(SPI_SS_IO == 1) begin
cnt <= 0;
end else begin
sbuf[6:1] <= sbuf[5:0];
sbuf[0] <= SPI_MOSI;
cnt <= cnt + 1;
if(cnt == 7) begin
cmd[7:1] <= sbuf;
cmd[0] <= SPI_MOSI;
end
if(cnt == 8) begin
if(cmd == 4)
kbd_mouse_type <= 2'b00; // first mouse axis
else if(cmd == 5)
kbd_mouse_type <= 2'b10; // keyboard
else if(cmd == 6)
kbd_mouse_type <= 2'b11; // OSD keyboard
end
// strobe is set whenever a valid byte has been received
kbd_mouse_strobe <= 0;
// first payload byte
if(cnt == 15) begin
if(cmd == 1) begin
but_sw[7:1] <= sbuf[6:0];
but_sw[0] <= SPI_MOSI;
end
if(cmd == 2) begin
joystick0[7:1] <= sbuf[6:0];
joystick0[0] <= SPI_MOSI;
end
if(cmd == 3) begin
joystick1[7:1] <= sbuf[6:0];
joystick1[0] <= SPI_MOSI;
end
// mouse, keyboard or OSD
if((cmd == 4)||(cmd == 5)||(cmd == 6)) begin
kbd_mouse_data[7:1] <= sbuf[6:0];
kbd_mouse_data[0] <= SPI_MOSI;
kbd_mouse_strobe <= 1;
end
end
// mouse handling
if(cmd == 4) begin
// second byte contains movement data
if(cnt == 23) begin
kbd_mouse_data[7:1] <= sbuf[6:0];
kbd_mouse_data[0] <= SPI_MOSI;
kbd_mouse_strobe <= 1;
kbd_mouse_type <= 2'b01;
end
// third byte contains the buttons
if(cnt == 31) begin
mouse_buttons[2:1] <= sbuf[1:0];
mouse_buttons[0] <= SPI_MOSI;
end
end
end
end
endmodule
|
// Copyright 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Tunable ring oscillator---synthesizable (physical) version.
//
// NOTE: This netlist cannot be simulated correctly due to lack
// of accurate timing in the digital cell verilog models.
module delay_stage(in, trim, out);
input in;
input [1:0] trim;
output out;
wire d0, d1, d2;
sky130_fd_sc_hd__clkbuf_2 delaybuf0 (
.A(in),
.X(ts)
);
sky130_fd_sc_hd__clkbuf_1 delaybuf1 (
.A(ts),
.X(d0)
);
sky130_fd_sc_hd__einvp_2 delayen1 (
.A(d0),
.TE(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__einvn_4 delayenb1 (
.A(ts),
.TE_B(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__clkinv_1 delayint0 (
.A(d1),
.Y(d2)
);
sky130_fd_sc_hd__einvp_2 delayen0 (
.A(d2),
.TE(trim[0]),
.Z(out)
);
sky130_fd_sc_hd__einvn_8 delayenb0 (
.A(ts),
.TE_B(trim[0]),
.Z(out)
);
endmodule
module start_stage(in, trim, reset, out);
input in;
input [1:0] trim;
input reset;
output out;
wire d0, d1, d2, ctrl0, one;
sky130_fd_sc_hd__clkbuf_1 delaybuf0 (
.A(in),
.X(d0)
);
sky130_fd_sc_hd__einvp_2 delayen1 (
.A(d0),
.TE(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__einvn_4 delayenb1 (
.A(in),
.TE_B(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__clkinv_1 delayint0 (
.A(d1),
.Y(d2)
);
sky130_fd_sc_hd__einvp_2 delayen0 (
.A(d2),
.TE(trim[0]),
.Z(out)
);
sky130_fd_sc_hd__einvn_8 delayenb0 (
.A(in),
.TE_B(ctrl0),
.Z(out)
);
sky130_fd_sc_hd__einvp_1 reseten0 (
.A(one),
.TE(reset),
.Z(out)
);
sky130_fd_sc_hd__or2_2 ctrlen0 (
.A(reset),
.B(trim[0]),
.X(ctrl0)
);
sky130_fd_sc_hd__conb_1 const1 (
.HI(one),
.LO()
);
endmodule
// Ring oscillator with 13 stages, each with two trim bits delay
// (see above). Trim is not binary: For trim[1:0], lower bit
// trim[0] is primary trim and must be applied first; upper
// bit trim[1] is secondary trim and should only be applied
// after the primary trim is applied, or it has no effect.
//
// Total effective number of inverter stages in this oscillator
// ranges from 13 at trim 0 to 65 at trim 24. The intention is
// to cover a range greater than 2x so that the midrange can be
// reached over all PVT conditions.
//
// Frequency of this ring oscillator under SPICE simulations at
// nominal PVT is maximum 214 MHz (trim 0), minimum 90 MHz (trim 24).
module ring_osc2x13(reset, trim, clockp);
input reset;
input [25:0] trim;
output[1:0] clockp;
wire [12:0] d;
wire [1:0] clockp;
wire [1:0] c;
// Main oscillator loop stages
genvar i;
generate
for (i = 0; i < 12; i = i + 1) begin : dstage
delay_stage id (
.in(d[i]),
.trim({trim[i+13], trim[i]}),
.out(d[i+1])
);
end
endgenerate
// Reset/startup stage
start_stage iss (
.in(d[12]),
.trim({trim[25], trim[12]}),
.reset(reset),
.out(d[0])
);
// Buffered outputs a 0 and 90 degrees phase (approximately)
sky130_fd_sc_hd__clkinv_2 ibufp00 (
.A(d[0]),
.Y(c[0])
);
sky130_fd_sc_hd__clkinv_8 ibufp01 (
.A(c[0]),
.Y(clockp[0])
);
sky130_fd_sc_hd__clkinv_2 ibufp10 (
.A(d[6]),
.Y(c[1])
);
sky130_fd_sc_hd__clkinv_8 ibufp11 (
.A(c[1]),
.Y(clockp[1])
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_engine_ultrascale.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RX Engine (Ultrascale) takes a the two streams of
// AXI from the Xilinx endpoint packets and provides the request packets on the
// RXR Interface, and the completion packets on the RXC Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "ultrascale.vh"
`include "trellis.vh"
module rx_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: CQ
input M_AXIS_CQ_TVALID,
input M_AXIS_CQ_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP,
input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER,
output M_AXIS_CQ_TREADY,
// Interface: RC
input M_AXIS_RC_TVALID,
input M_AXIS_RC_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP,
input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER,
output M_AXIS_RC_TREADY,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP,
// Interface: RXR Engine
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP
);
localparam C_RX_PIPELINE_DEPTH = 3;
rxc_engine_ultrascale
#(///*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_RX_PIPELINE_DEPTH (C_RX_PIPELINE_DEPTH))
rxc_engine_inst
(/*AUTOINST*/
// Outputs
.M_AXIS_RC_TREADY (M_AXIS_RC_TREADY),
.RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_VALID (RXC_DATA_VALID),
.RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_START_FLAG (RXC_DATA_START_FLAG),
.RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (RXC_DATA_END_FLAG),
.RXC_DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
.RXC_META_FDWBE (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
.RXC_META_TAG (RXC_META_TAG[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.RXC_META_EP (RXC_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.M_AXIS_RC_TVALID (M_AXIS_RC_TVALID),
.M_AXIS_RC_TLAST (M_AXIS_RC_TLAST),
.M_AXIS_RC_TDATA (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]));
rxr_engine_ultrascale
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_RX_PIPELINE_DEPTH (C_RX_PIPELINE_DEPTH))
rxr_engine_inst
(/*AUTOINST*/
// Outputs
.M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY),
.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
.RXR_META_EP (RXR_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID),
.M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST),
.M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]));
endmodule // rx_engine_ultrascale
// Local Variables:
// verilog-library-directories:("." "./rx/")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DIODE_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DIODE_PP_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DIODE_PP_BLACKBOX_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Sat Jun 4 16:53:15 2016
// Host : Dries007-Arch running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/ClockDivider/ClockDivider_sim_netlist.v
// Design : ClockDivider
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module ClockDivider
(clk,
clk_vga,
clk_cpu,
clk_2cpu);
input clk;
output clk_vga;
output clk_cpu;
output clk_2cpu;
(* IBUF_LOW_PWR *) wire clk;
wire clk_2cpu;
wire clk_cpu;
wire clk_vga;
ClockDivider_ClockDivider_clk_wiz inst
(.clk(clk),
.clk_2cpu(clk_2cpu),
.clk_cpu(clk_cpu),
.clk_vga(clk_vga));
endmodule
(* ORIG_REF_NAME = "ClockDivider_clk_wiz" *)
module ClockDivider_ClockDivider_clk_wiz
(clk,
clk_vga,
clk_cpu,
clk_2cpu);
input clk;
output clk_vga;
output clk_cpu;
output clk_2cpu;
wire clk;
wire clk_2cpu;
wire clk_2cpu_ClockDivider;
wire clk_ClockDivider;
wire clk_cpu;
wire clk_cpu_ClockDivider;
wire clk_vga;
wire clk_vga_ClockDivider;
wire clkfbout_ClockDivider;
wire clkfbout_buf_ClockDivider;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_ClockDivider),
.O(clkfbout_buf_ClockDivider));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk),
.O(clk_ClockDivider));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_vga_ClockDivider),
.O(clk_vga));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_cpu_ClockDivider),
.O(clk_cpu));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout3_buf
(.I(clk_2cpu_ClockDivider),
.O(clk_2cpu));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(54.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(120),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(60),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_ClockDivider),
.CLKFBOUT(clkfbout_ClockDivider),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_ClockDivider),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_vga_ClockDivider),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_cpu_ClockDivider),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(clk_2cpu_ClockDivider),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__DLRTP_BEHAVIORAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTP_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_PP_SYMBOL_V
`define SKY130_FD_SC_LS__OR3B_PP_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 14 10:22:21 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_txn0, srio_txp0, s_axis_iotx_tvalid,
s_axis_iotx_tready, s_axis_iotx_tlast, s_axis_iotx_tdata, s_axis_iotx_tkeep,
s_axis_iotx_tuser, m_axis_iorx_tvalid, m_axis_iorx_tready, m_axis_iorx_tlast,
m_axis_iorx_tdata, m_axis_iorx_tkeep, m_axis_iorx_tuser, s_axi_maintr_rst,
s_axi_maintr_awvalid, s_axi_maintr_awready, s_axi_maintr_awaddr, s_axi_maintr_wvalid,
s_axi_maintr_wready, s_axi_maintr_wdata, s_axi_maintr_bvalid, s_axi_maintr_bready,
s_axi_maintr_bresp, s_axi_maintr_arvalid, s_axi_maintr_arready, s_axi_maintr_araddr,
s_axi_maintr_rvalid, s_axi_maintr_rready, s_axi_maintr_rdata, s_axi_maintr_rresp,
sim_train_en, force_reinit, phy_mce, phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset,
phy_debug, gtrx_disperr_or, gtrx_notintable_or, port_error, port_timeout, srio_host,
port_decode_error, deviceid, idle2_selected, phy_lcl_master_enable_out,
buf_lcl_response_only_out, buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out,
phy_lcl_phy_next_fm_out, phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out,
phy_lcl_phy_rcvd_buf_stat_out, phy_lcl_maint_only_out, port_initialized,
link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
output srio_txn0;
output srio_txp0;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:04:45 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, n167, n168, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196,
n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306,
n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317,
n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328,
n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350,
n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
n373, n374, n375, n376, n377, n378, n379, n380, n381,
DP_OP_36J10_126_4699_n33, DP_OP_36J10_126_4699_n22,
DP_OP_36J10_126_4699_n21, DP_OP_36J10_126_4699_n20,
DP_OP_36J10_126_4699_n19, DP_OP_36J10_126_4699_n18,
DP_OP_36J10_126_4699_n17, DP_OP_36J10_126_4699_n16,
DP_OP_36J10_126_4699_n15, DP_OP_36J10_126_4699_n9,
DP_OP_36J10_126_4699_n8, DP_OP_36J10_126_4699_n7,
DP_OP_36J10_126_4699_n6, DP_OP_36J10_126_4699_n5,
DP_OP_36J10_126_4699_n4, DP_OP_36J10_126_4699_n3,
DP_OP_36J10_126_4699_n2, DP_OP_36J10_126_4699_n1,
DP_OP_156J10_125_3370_n133, DP_OP_156J10_125_3370_n132,
DP_OP_156J10_125_3370_n131, DP_OP_156J10_125_3370_n130,
DP_OP_156J10_125_3370_n129, DP_OP_156J10_125_3370_n128,
DP_OP_156J10_125_3370_n127, DP_OP_156J10_125_3370_n126,
DP_OP_156J10_125_3370_n125, DP_OP_156J10_125_3370_n124,
DP_OP_156J10_125_3370_n123, DP_OP_156J10_125_3370_n122,
DP_OP_156J10_125_3370_n121, DP_OP_156J10_125_3370_n120,
DP_OP_156J10_125_3370_n119, DP_OP_156J10_125_3370_n118,
DP_OP_156J10_125_3370_n110, DP_OP_156J10_125_3370_n109,
DP_OP_156J10_125_3370_n108, DP_OP_156J10_125_3370_n107,
DP_OP_156J10_125_3370_n106, DP_OP_156J10_125_3370_n105,
DP_OP_156J10_125_3370_n104, DP_OP_156J10_125_3370_n103,
DP_OP_156J10_125_3370_n102, DP_OP_156J10_125_3370_n101,
DP_OP_156J10_125_3370_n100, DP_OP_156J10_125_3370_n99,
DP_OP_156J10_125_3370_n98, DP_OP_156J10_125_3370_n97,
DP_OP_156J10_125_3370_n96, DP_OP_156J10_125_3370_n95,
DP_OP_156J10_125_3370_n81, DP_OP_156J10_125_3370_n78,
DP_OP_156J10_125_3370_n77, DP_OP_156J10_125_3370_n76,
DP_OP_156J10_125_3370_n75, DP_OP_156J10_125_3370_n74,
DP_OP_156J10_125_3370_n73, DP_OP_156J10_125_3370_n72,
DP_OP_156J10_125_3370_n71, DP_OP_156J10_125_3370_n70,
DP_OP_156J10_125_3370_n69, DP_OP_156J10_125_3370_n68,
DP_OP_156J10_125_3370_n67, DP_OP_156J10_125_3370_n66,
DP_OP_156J10_125_3370_n65, DP_OP_156J10_125_3370_n64,
DP_OP_156J10_125_3370_n63, DP_OP_156J10_125_3370_n62,
DP_OP_156J10_125_3370_n61, DP_OP_156J10_125_3370_n60,
DP_OP_156J10_125_3370_n59, DP_OP_156J10_125_3370_n58,
DP_OP_156J10_125_3370_n57, DP_OP_156J10_125_3370_n56,
DP_OP_156J10_125_3370_n55, DP_OP_156J10_125_3370_n54,
DP_OP_156J10_125_3370_n53, DP_OP_156J10_125_3370_n52,
DP_OP_156J10_125_3370_n51, DP_OP_156J10_125_3370_n50,
DP_OP_156J10_125_3370_n49, DP_OP_156J10_125_3370_n48,
DP_OP_156J10_125_3370_n47, DP_OP_156J10_125_3370_n46,
DP_OP_156J10_125_3370_n45, DP_OP_156J10_125_3370_n44,
DP_OP_156J10_125_3370_n43, DP_OP_156J10_125_3370_n42,
DP_OP_156J10_125_3370_n41, DP_OP_156J10_125_3370_n40,
DP_OP_156J10_125_3370_n39, DP_OP_156J10_125_3370_n38,
DP_OP_156J10_125_3370_n37, DP_OP_156J10_125_3370_n36,
DP_OP_156J10_125_3370_n35, DP_OP_156J10_125_3370_n34,
DP_OP_156J10_125_3370_n33, DP_OP_156J10_125_3370_n32,
DP_OP_156J10_125_3370_n31, DP_OP_155J10_124_2038_n370,
DP_OP_155J10_124_2038_n365, DP_OP_155J10_124_2038_n364,
DP_OP_155J10_124_2038_n360, DP_OP_155J10_124_2038_n352,
DP_OP_155J10_124_2038_n351, DP_OP_155J10_124_2038_n346,
DP_OP_155J10_124_2038_n341, DP_OP_155J10_124_2038_n335,
DP_OP_155J10_124_2038_n332, DP_OP_155J10_124_2038_n331,
DP_OP_155J10_124_2038_n330, DP_OP_155J10_124_2038_n329,
DP_OP_155J10_124_2038_n328, DP_OP_155J10_124_2038_n327,
DP_OP_155J10_124_2038_n326, DP_OP_155J10_124_2038_n325,
DP_OP_155J10_124_2038_n324, DP_OP_155J10_124_2038_n323,
DP_OP_155J10_124_2038_n322, DP_OP_155J10_124_2038_n321,
DP_OP_155J10_124_2038_n320, DP_OP_155J10_124_2038_n319,
DP_OP_155J10_124_2038_n318, DP_OP_155J10_124_2038_n317,
DP_OP_155J10_124_2038_n316, DP_OP_155J10_124_2038_n315,
DP_OP_155J10_124_2038_n314, DP_OP_155J10_124_2038_n313,
DP_OP_155J10_124_2038_n312, DP_OP_155J10_124_2038_n311,
DP_OP_155J10_124_2038_n310, DP_OP_155J10_124_2038_n309,
DP_OP_155J10_124_2038_n308, DP_OP_155J10_124_2038_n307,
DP_OP_155J10_124_2038_n306, DP_OP_155J10_124_2038_n279,
DP_OP_155J10_124_2038_n274, DP_OP_155J10_124_2038_n273,
DP_OP_155J10_124_2038_n269, DP_OP_155J10_124_2038_n261,
DP_OP_155J10_124_2038_n260, DP_OP_155J10_124_2038_n255,
DP_OP_155J10_124_2038_n250, DP_OP_155J10_124_2038_n244,
DP_OP_155J10_124_2038_n241, DP_OP_155J10_124_2038_n240,
DP_OP_155J10_124_2038_n239, DP_OP_155J10_124_2038_n238,
DP_OP_155J10_124_2038_n237, DP_OP_155J10_124_2038_n236,
DP_OP_155J10_124_2038_n235, DP_OP_155J10_124_2038_n234,
DP_OP_155J10_124_2038_n233, DP_OP_155J10_124_2038_n232,
DP_OP_155J10_124_2038_n231, DP_OP_155J10_124_2038_n230,
DP_OP_155J10_124_2038_n229, DP_OP_155J10_124_2038_n228,
DP_OP_155J10_124_2038_n227, DP_OP_155J10_124_2038_n226,
DP_OP_155J10_124_2038_n225, DP_OP_155J10_124_2038_n224,
DP_OP_155J10_124_2038_n223, DP_OP_155J10_124_2038_n222,
DP_OP_155J10_124_2038_n221, DP_OP_155J10_124_2038_n220,
DP_OP_155J10_124_2038_n219, DP_OP_155J10_124_2038_n218,
DP_OP_155J10_124_2038_n217, DP_OP_155J10_124_2038_n216,
DP_OP_155J10_124_2038_n215, DP_OP_155J10_124_2038_n202,
DP_OP_155J10_124_2038_n201, DP_OP_155J10_124_2038_n197,
DP_OP_155J10_124_2038_n196, DP_OP_155J10_124_2038_n195,
DP_OP_155J10_124_2038_n194, DP_OP_155J10_124_2038_n193,
DP_OP_155J10_124_2038_n192, DP_OP_155J10_124_2038_n125,
DP_OP_155J10_124_2038_n124, DP_OP_155J10_124_2038_n123,
DP_OP_155J10_124_2038_n122, DP_OP_155J10_124_2038_n121,
DP_OP_155J10_124_2038_n120, DP_OP_155J10_124_2038_n119,
DP_OP_155J10_124_2038_n118, DP_OP_155J10_124_2038_n117,
DP_OP_155J10_124_2038_n116, DP_OP_155J10_124_2038_n114,
DP_OP_155J10_124_2038_n113, DP_OP_155J10_124_2038_n112,
DP_OP_155J10_124_2038_n111, DP_OP_155J10_124_2038_n110,
DP_OP_155J10_124_2038_n109, DP_OP_155J10_124_2038_n108,
DP_OP_155J10_124_2038_n107, DP_OP_155J10_124_2038_n106,
DP_OP_155J10_124_2038_n105, DP_OP_155J10_124_2038_n104,
DP_OP_155J10_124_2038_n103, DP_OP_155J10_124_2038_n101,
DP_OP_155J10_124_2038_n100, DP_OP_155J10_124_2038_n99,
DP_OP_155J10_124_2038_n98, DP_OP_155J10_124_2038_n97,
DP_OP_155J10_124_2038_n96, DP_OP_155J10_124_2038_n94,
DP_OP_155J10_124_2038_n91, DP_OP_155J10_124_2038_n90,
DP_OP_155J10_124_2038_n87, DP_OP_155J10_124_2038_n86,
DP_OP_155J10_124_2038_n83, DP_OP_155J10_124_2038_n82,
DP_OP_155J10_124_2038_n81, DP_OP_155J10_124_2038_n80,
DP_OP_155J10_124_2038_n79, DP_OP_155J10_124_2038_n78,
DP_OP_155J10_124_2038_n75, DP_OP_155J10_124_2038_n74,
DP_OP_155J10_124_2038_n73, DP_OP_155J10_124_2038_n72,
DP_OP_155J10_124_2038_n70, DP_OP_155J10_124_2038_n69,
DP_OP_155J10_124_2038_n68, DP_OP_155J10_124_2038_n67,
DP_OP_155J10_124_2038_n65, DP_OP_155J10_124_2038_n64,
DP_OP_155J10_124_2038_n63, DP_OP_155J10_124_2038_n62,
DP_OP_155J10_124_2038_n61, DP_OP_155J10_124_2038_n60,
DP_OP_155J10_124_2038_n59, DP_OP_155J10_124_2038_n58,
DP_OP_155J10_124_2038_n57, DP_OP_155J10_124_2038_n56,
DP_OP_155J10_124_2038_n55, DP_OP_155J10_124_2038_n54,
DP_OP_155J10_124_2038_n53, DP_OP_155J10_124_2038_n52,
DP_OP_155J10_124_2038_n51, DP_OP_155J10_124_2038_n50,
DP_OP_155J10_124_2038_n49, DP_OP_155J10_124_2038_n48,
DP_OP_155J10_124_2038_n47, DP_OP_155J10_124_2038_n46,
DP_OP_155J10_124_2038_n45, DP_OP_155J10_124_2038_n44,
DP_OP_155J10_124_2038_n43, DP_OP_155J10_124_2038_n42,
DP_OP_155J10_124_2038_n41, DP_OP_155J10_124_2038_n40,
DP_OP_155J10_124_2038_n39, DP_OP_155J10_124_2038_n38,
DP_OP_155J10_124_2038_n37, DP_OP_155J10_124_2038_n36,
DP_OP_155J10_124_2038_n35, DP_OP_155J10_124_2038_n34,
DP_OP_155J10_124_2038_n33, DP_OP_155J10_124_2038_n32,
DP_OP_155J10_124_2038_n31, DP_OP_155J10_124_2038_n30,
DP_OP_155J10_124_2038_n29, DP_OP_155J10_124_2038_n28,
DP_OP_155J10_124_2038_n27, DP_OP_155J10_124_2038_n26,
DP_OP_155J10_124_2038_n25, DP_OP_155J10_124_2038_n24,
DP_OP_155J10_124_2038_n23, DP_OP_155J10_124_2038_n22,
DP_OP_155J10_124_2038_n21, DP_OP_155J10_124_2038_n20,
DP_OP_155J10_124_2038_n19, DP_OP_155J10_124_2038_n18,
DP_OP_154J10_123_2038_n369, DP_OP_154J10_123_2038_n364,
DP_OP_154J10_123_2038_n359, DP_OP_154J10_123_2038_n358,
DP_OP_154J10_123_2038_n351, DP_OP_154J10_123_2038_n345,
DP_OP_154J10_123_2038_n335, DP_OP_154J10_123_2038_n332,
DP_OP_154J10_123_2038_n331, DP_OP_154J10_123_2038_n330,
DP_OP_154J10_123_2038_n329, DP_OP_154J10_123_2038_n328,
DP_OP_154J10_123_2038_n327, DP_OP_154J10_123_2038_n326,
DP_OP_154J10_123_2038_n325, DP_OP_154J10_123_2038_n324,
DP_OP_154J10_123_2038_n323, DP_OP_154J10_123_2038_n322,
DP_OP_154J10_123_2038_n321, DP_OP_154J10_123_2038_n320,
DP_OP_154J10_123_2038_n319, DP_OP_154J10_123_2038_n318,
DP_OP_154J10_123_2038_n317, DP_OP_154J10_123_2038_n316,
DP_OP_154J10_123_2038_n315, DP_OP_154J10_123_2038_n314,
DP_OP_154J10_123_2038_n313, DP_OP_154J10_123_2038_n312,
DP_OP_154J10_123_2038_n311, DP_OP_154J10_123_2038_n310,
DP_OP_154J10_123_2038_n309, DP_OP_154J10_123_2038_n308,
DP_OP_154J10_123_2038_n307, DP_OP_154J10_123_2038_n306,
DP_OP_154J10_123_2038_n279, DP_OP_154J10_123_2038_n274,
DP_OP_154J10_123_2038_n273, DP_OP_154J10_123_2038_n269,
DP_OP_154J10_123_2038_n261, DP_OP_154J10_123_2038_n260,
DP_OP_154J10_123_2038_n255, DP_OP_154J10_123_2038_n250,
DP_OP_154J10_123_2038_n244, DP_OP_154J10_123_2038_n241,
DP_OP_154J10_123_2038_n240, DP_OP_154J10_123_2038_n239,
DP_OP_154J10_123_2038_n238, DP_OP_154J10_123_2038_n237,
DP_OP_154J10_123_2038_n236, DP_OP_154J10_123_2038_n235,
DP_OP_154J10_123_2038_n234, DP_OP_154J10_123_2038_n233,
DP_OP_154J10_123_2038_n232, DP_OP_154J10_123_2038_n231,
DP_OP_154J10_123_2038_n230, DP_OP_154J10_123_2038_n229,
DP_OP_154J10_123_2038_n228, DP_OP_154J10_123_2038_n227,
DP_OP_154J10_123_2038_n226, DP_OP_154J10_123_2038_n225,
DP_OP_154J10_123_2038_n224, DP_OP_154J10_123_2038_n223,
DP_OP_154J10_123_2038_n222, DP_OP_154J10_123_2038_n221,
DP_OP_154J10_123_2038_n220, DP_OP_154J10_123_2038_n219,
DP_OP_154J10_123_2038_n218, DP_OP_154J10_123_2038_n217,
DP_OP_154J10_123_2038_n216, DP_OP_154J10_123_2038_n215,
DP_OP_154J10_123_2038_n202, DP_OP_154J10_123_2038_n201,
DP_OP_154J10_123_2038_n197, DP_OP_154J10_123_2038_n196,
DP_OP_154J10_123_2038_n195, DP_OP_154J10_123_2038_n194,
DP_OP_154J10_123_2038_n193, DP_OP_154J10_123_2038_n192,
DP_OP_154J10_123_2038_n125, DP_OP_154J10_123_2038_n124,
DP_OP_154J10_123_2038_n123, DP_OP_154J10_123_2038_n122,
DP_OP_154J10_123_2038_n121, DP_OP_154J10_123_2038_n120,
DP_OP_154J10_123_2038_n119, DP_OP_154J10_123_2038_n118,
DP_OP_154J10_123_2038_n117, DP_OP_154J10_123_2038_n116,
DP_OP_154J10_123_2038_n114, DP_OP_154J10_123_2038_n113,
DP_OP_154J10_123_2038_n112, DP_OP_154J10_123_2038_n111,
DP_OP_154J10_123_2038_n110, DP_OP_154J10_123_2038_n109,
DP_OP_154J10_123_2038_n108, DP_OP_154J10_123_2038_n107,
DP_OP_154J10_123_2038_n106, DP_OP_154J10_123_2038_n105,
DP_OP_154J10_123_2038_n104, DP_OP_154J10_123_2038_n103,
DP_OP_154J10_123_2038_n101, DP_OP_154J10_123_2038_n100,
DP_OP_154J10_123_2038_n99, DP_OP_154J10_123_2038_n98,
DP_OP_154J10_123_2038_n97, DP_OP_154J10_123_2038_n96,
DP_OP_154J10_123_2038_n94, DP_OP_154J10_123_2038_n91,
DP_OP_154J10_123_2038_n87, DP_OP_154J10_123_2038_n86,
DP_OP_154J10_123_2038_n83, DP_OP_154J10_123_2038_n82,
DP_OP_154J10_123_2038_n81, DP_OP_154J10_123_2038_n80,
DP_OP_154J10_123_2038_n79, DP_OP_154J10_123_2038_n78,
DP_OP_154J10_123_2038_n75, DP_OP_154J10_123_2038_n74,
DP_OP_154J10_123_2038_n73, DP_OP_154J10_123_2038_n72,
DP_OP_154J10_123_2038_n70, DP_OP_154J10_123_2038_n69,
DP_OP_154J10_123_2038_n68, DP_OP_154J10_123_2038_n67,
DP_OP_154J10_123_2038_n65, DP_OP_154J10_123_2038_n64,
DP_OP_154J10_123_2038_n63, DP_OP_154J10_123_2038_n62,
DP_OP_154J10_123_2038_n61, DP_OP_154J10_123_2038_n60,
DP_OP_154J10_123_2038_n59, DP_OP_154J10_123_2038_n58,
DP_OP_154J10_123_2038_n57, DP_OP_154J10_123_2038_n56,
DP_OP_154J10_123_2038_n55, DP_OP_154J10_123_2038_n54,
DP_OP_154J10_123_2038_n53, DP_OP_154J10_123_2038_n52,
DP_OP_154J10_123_2038_n51, DP_OP_154J10_123_2038_n50,
DP_OP_154J10_123_2038_n49, DP_OP_154J10_123_2038_n48,
DP_OP_154J10_123_2038_n47, DP_OP_154J10_123_2038_n46,
DP_OP_154J10_123_2038_n45, DP_OP_154J10_123_2038_n44,
DP_OP_154J10_123_2038_n43, DP_OP_154J10_123_2038_n42,
DP_OP_154J10_123_2038_n41, DP_OP_154J10_123_2038_n40,
DP_OP_154J10_123_2038_n39, DP_OP_154J10_123_2038_n38,
DP_OP_154J10_123_2038_n37, DP_OP_154J10_123_2038_n36,
DP_OP_154J10_123_2038_n35, DP_OP_154J10_123_2038_n34,
DP_OP_154J10_123_2038_n33, DP_OP_154J10_123_2038_n32,
DP_OP_154J10_123_2038_n31, DP_OP_154J10_123_2038_n30,
DP_OP_154J10_123_2038_n29, DP_OP_154J10_123_2038_n28,
DP_OP_154J10_123_2038_n27, DP_OP_154J10_123_2038_n26,
DP_OP_154J10_123_2038_n25, DP_OP_154J10_123_2038_n24,
DP_OP_154J10_123_2038_n23, DP_OP_154J10_123_2038_n22,
DP_OP_154J10_123_2038_n21, DP_OP_154J10_123_2038_n20,
DP_OP_154J10_123_2038_n19, DP_OP_154J10_123_2038_n18,
DP_OP_153J10_122_5442_n414, DP_OP_153J10_122_5442_n413,
DP_OP_153J10_122_5442_n412, DP_OP_153J10_122_5442_n407,
DP_OP_153J10_122_5442_n406, DP_OP_153J10_122_5442_n405,
DP_OP_153J10_122_5442_n404, DP_OP_153J10_122_5442_n403,
DP_OP_153J10_122_5442_n400, DP_OP_153J10_122_5442_n399,
DP_OP_153J10_122_5442_n398, DP_OP_153J10_122_5442_n397,
DP_OP_153J10_122_5442_n396, DP_OP_153J10_122_5442_n394,
DP_OP_153J10_122_5442_n393, DP_OP_153J10_122_5442_n392,
DP_OP_153J10_122_5442_n380, DP_OP_153J10_122_5442_n377,
DP_OP_153J10_122_5442_n376, DP_OP_153J10_122_5442_n375,
DP_OP_153J10_122_5442_n374, DP_OP_153J10_122_5442_n373,
DP_OP_153J10_122_5442_n372, DP_OP_153J10_122_5442_n371,
DP_OP_153J10_122_5442_n370, DP_OP_153J10_122_5442_n369,
DP_OP_153J10_122_5442_n368, DP_OP_153J10_122_5442_n367,
DP_OP_153J10_122_5442_n366, DP_OP_153J10_122_5442_n365,
DP_OP_153J10_122_5442_n364, DP_OP_153J10_122_5442_n363,
DP_OP_153J10_122_5442_n362, DP_OP_153J10_122_5442_n361,
DP_OP_153J10_122_5442_n360, DP_OP_153J10_122_5442_n359,
DP_OP_153J10_122_5442_n311, DP_OP_153J10_122_5442_n306,
DP_OP_153J10_122_5442_n305, DP_OP_153J10_122_5442_n296,
DP_OP_153J10_122_5442_n293, DP_OP_153J10_122_5442_n292,
DP_OP_153J10_122_5442_n290, DP_OP_153J10_122_5442_n289,
DP_OP_153J10_122_5442_n288, DP_OP_153J10_122_5442_n287,
DP_OP_153J10_122_5442_n282, DP_OP_153J10_122_5442_n274,
DP_OP_153J10_122_5442_n273, DP_OP_153J10_122_5442_n271,
DP_OP_153J10_122_5442_n270, DP_OP_153J10_122_5442_n269,
DP_OP_153J10_122_5442_n268, DP_OP_153J10_122_5442_n266,
DP_OP_153J10_122_5442_n265, DP_OP_153J10_122_5442_n264,
DP_OP_153J10_122_5442_n263, DP_OP_153J10_122_5442_n262,
DP_OP_153J10_122_5442_n261, DP_OP_153J10_122_5442_n259,
DP_OP_153J10_122_5442_n258, DP_OP_153J10_122_5442_n257,
DP_OP_153J10_122_5442_n256, DP_OP_153J10_122_5442_n255,
DP_OP_153J10_122_5442_n254, DP_OP_153J10_122_5442_n253,
DP_OP_153J10_122_5442_n252, DP_OP_153J10_122_5442_n251,
DP_OP_153J10_122_5442_n250, DP_OP_153J10_122_5442_n249,
DP_OP_153J10_122_5442_n248, DP_OP_153J10_122_5442_n247,
DP_OP_153J10_122_5442_n234, DP_OP_153J10_122_5442_n229,
DP_OP_153J10_122_5442_n228, DP_OP_153J10_122_5442_n227,
DP_OP_153J10_122_5442_n224, DP_OP_153J10_122_5442_n205,
DP_OP_153J10_122_5442_n204, DP_OP_153J10_122_5442_n203,
DP_OP_153J10_122_5442_n202, DP_OP_153J10_122_5442_n201,
DP_OP_153J10_122_5442_n200, DP_OP_153J10_122_5442_n196,
DP_OP_153J10_122_5442_n195, DP_OP_153J10_122_5442_n194,
DP_OP_153J10_122_5442_n193, DP_OP_153J10_122_5442_n192,
DP_OP_153J10_122_5442_n191, DP_OP_153J10_122_5442_n187,
DP_OP_153J10_122_5442_n186, DP_OP_153J10_122_5442_n185,
DP_OP_153J10_122_5442_n184, DP_OP_153J10_122_5442_n183,
DP_OP_153J10_122_5442_n182, DP_OP_153J10_122_5442_n177,
DP_OP_153J10_122_5442_n176, DP_OP_153J10_122_5442_n175,
DP_OP_153J10_122_5442_n174, DP_OP_153J10_122_5442_n173,
DP_OP_153J10_122_5442_n169, DP_OP_153J10_122_5442_n167,
DP_OP_153J10_122_5442_n166, DP_OP_153J10_122_5442_n165,
DP_OP_153J10_122_5442_n162, DP_OP_153J10_122_5442_n161,
DP_OP_153J10_122_5442_n159, DP_OP_153J10_122_5442_n158,
DP_OP_153J10_122_5442_n157, DP_OP_153J10_122_5442_n156,
DP_OP_153J10_122_5442_n155, DP_OP_153J10_122_5442_n154,
DP_OP_153J10_122_5442_n151, DP_OP_153J10_122_5442_n150,
DP_OP_153J10_122_5442_n149, DP_OP_153J10_122_5442_n148,
DP_OP_153J10_122_5442_n145, DP_OP_153J10_122_5442_n133,
DP_OP_153J10_122_5442_n128, DP_OP_153J10_122_5442_n127,
DP_OP_153J10_122_5442_n125, DP_OP_153J10_122_5442_n124,
DP_OP_153J10_122_5442_n123, DP_OP_153J10_122_5442_n122,
DP_OP_153J10_122_5442_n121, DP_OP_153J10_122_5442_n120,
DP_OP_153J10_122_5442_n119, DP_OP_153J10_122_5442_n118,
DP_OP_153J10_122_5442_n117, DP_OP_153J10_122_5442_n116,
DP_OP_153J10_122_5442_n115, DP_OP_153J10_122_5442_n113,
DP_OP_153J10_122_5442_n112, DP_OP_153J10_122_5442_n111,
DP_OP_153J10_122_5442_n110, DP_OP_153J10_122_5442_n109,
DP_OP_153J10_122_5442_n108, DP_OP_153J10_122_5442_n107,
DP_OP_153J10_122_5442_n106, DP_OP_153J10_122_5442_n105,
DP_OP_153J10_122_5442_n104, DP_OP_153J10_122_5442_n103,
DP_OP_153J10_122_5442_n102, DP_OP_153J10_122_5442_n101,
DP_OP_153J10_122_5442_n100, DP_OP_153J10_122_5442_n99,
DP_OP_153J10_122_5442_n98, DP_OP_153J10_122_5442_n97,
DP_OP_153J10_122_5442_n95, DP_OP_153J10_122_5442_n94,
DP_OP_153J10_122_5442_n93, DP_OP_153J10_122_5442_n92,
DP_OP_153J10_122_5442_n91, DP_OP_153J10_122_5442_n90,
DP_OP_153J10_122_5442_n89, DP_OP_153J10_122_5442_n88,
DP_OP_153J10_122_5442_n87, DP_OP_153J10_122_5442_n84,
DP_OP_153J10_122_5442_n83, DP_OP_153J10_122_5442_n82,
DP_OP_153J10_122_5442_n81, DP_OP_153J10_122_5442_n80,
DP_OP_153J10_122_5442_n79, DP_OP_153J10_122_5442_n78,
DP_OP_153J10_122_5442_n77, DP_OP_153J10_122_5442_n76,
DP_OP_153J10_122_5442_n75, DP_OP_153J10_122_5442_n74,
DP_OP_153J10_122_5442_n73, DP_OP_153J10_122_5442_n72,
DP_OP_153J10_122_5442_n71, DP_OP_153J10_122_5442_n70,
DP_OP_153J10_122_5442_n69, DP_OP_153J10_122_5442_n68,
DP_OP_153J10_122_5442_n67, DP_OP_153J10_122_5442_n66,
DP_OP_153J10_122_5442_n65, DP_OP_153J10_122_5442_n64,
DP_OP_153J10_122_5442_n63, DP_OP_153J10_122_5442_n62,
DP_OP_153J10_122_5442_n61, DP_OP_153J10_122_5442_n60,
DP_OP_153J10_122_5442_n59, DP_OP_153J10_122_5442_n58,
DP_OP_153J10_122_5442_n57, DP_OP_153J10_122_5442_n56,
DP_OP_153J10_122_5442_n55, DP_OP_153J10_122_5442_n54,
DP_OP_153J10_122_5442_n53, DP_OP_153J10_122_5442_n52,
DP_OP_153J10_122_5442_n51, DP_OP_153J10_122_5442_n50,
DP_OP_153J10_122_5442_n49, DP_OP_153J10_122_5442_n48,
DP_OP_153J10_122_5442_n47, DP_OP_153J10_122_5442_n46,
DP_OP_153J10_122_5442_n45, DP_OP_153J10_122_5442_n44,
DP_OP_153J10_122_5442_n43, DP_OP_153J10_122_5442_n42,
DP_OP_153J10_122_5442_n41, DP_OP_153J10_122_5442_n40,
DP_OP_153J10_122_5442_n38, DP_OP_153J10_122_5442_n37,
DP_OP_153J10_122_5442_n36, DP_OP_153J10_122_5442_n35,
DP_OP_153J10_122_5442_n34, DP_OP_153J10_122_5442_n33,
DP_OP_153J10_122_5442_n32, DP_OP_153J10_122_5442_n31,
DP_OP_153J10_122_5442_n30, DP_OP_153J10_122_5442_n29,
DP_OP_153J10_122_5442_n28, DP_OP_153J10_122_5442_n27,
DP_OP_153J10_122_5442_n26, DP_OP_153J10_122_5442_n25,
DP_OP_153J10_122_5442_n23, DP_OP_153J10_122_5442_n22,
DP_OP_153J10_122_5442_n21, n391, n392, n393, n394, n395, n396, n397,
n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408,
n409, n410, n411, n412, n413, n416, n417, n418, n419, n420, n421,
n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432,
n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443,
n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454,
n455, n456, n457, n458, n459, n460, n461, n462, n463, n464, n465,
n466, n467, n468, n469, n470, n471, n472, n473, n474, n475, n476,
n477, n478, n479, n480, n481, n482, n483, n484, n485, n486, n487,
n488, n489, n490, n491, n492, n493, n495, n496, n498, n499, n500,
n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599,
n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610,
n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621,
n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732,
n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743,
n744, n745, n746, n747, n748, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n775, n776, n777, n778,
n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789,
n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800,
n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822,
n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833,
n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844,
n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976,
n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987,
n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018,
n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329,
n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339,
n1340, n1341, n1342, n1343, n1344, n1345, n1347, n1348, n1349, n1350,
n1352, n1353, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412,
n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522,
n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532,
n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542,
n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552,
n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562,
n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572,
n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582,
n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592,
n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612,
n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622,
n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642,
n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652,
n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662,
n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672,
n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682,
n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [11:8] Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [13:8] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [9:0] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [11:8] Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(clk), .RN(
n1715), .Q(Op_MY[31]) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n1710), .Q(zero_flag), .QN(n430) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n1709), .QN(n428) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n1717), .QN(n409) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(clk), .RN(
n1709), .Q(Op_MX[14]), .QN(n417) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(clk), .RN(
n1713), .Q(Op_MX[12]), .QN(n418) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(clk), .RN(
n1715), .QN(n397) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(clk), .RN(
n1715), .QN(n394) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(clk), .RN(
n1718), .QN(n412) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n1716), .Q(Op_MX[31]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(clk), .RN(n1709),
.QN(n439) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(clk), .RN(n1708),
.QN(n448) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(clk), .RN(n393),
.QN(n438) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(clk), .RN(n393),
.QN(n447) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(clk), .RN(n1715),
.QN(n437) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(clk), .RN(n1714),
.QN(n446) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(clk), .RN(n1712),
.QN(n436) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(clk), .RN(n1713),
.QN(n445) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(clk), .RN(n1712),
.QN(n435) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(clk), .RN(n1712),
.QN(n444) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(clk), .RN(n1709),
.QN(n434) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(clk), .RN(n1718),
.QN(n443) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(clk), .RN(n1714),
.QN(n433) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(clk), .RN(n1714),
.QN(n442) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(clk), .RN(n1713),
.QN(n432) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(clk), .RN(n393),
.QN(n441) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(clk), .RN(n1710),
.QN(n431) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(clk), .RN(n393),
.QN(n451) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(clk), .RN(n1711),
.QN(n449) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(clk), .RN(n1716),
.QN(n450) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n1710),
.QN(n440) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n1709),
.Q(Add_result[0]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(clk), .RN(n1716),
.Q(Add_result[23]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n1716), .QN(n425) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n393), .QN(n426) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n1708), .QN(n408) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n1717), .QN(n398) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n1718), .QN(n407) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n1717), .QN(n396) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(clk), .RN(
n1710), .QN(n416) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(clk), .RN(
n1718), .Q(Op_MY[14]), .QN(n401) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n1709), .QN(n413) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(clk), .RN(
n1709), .QN(n399) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(clk), .RN(
n1715), .QN(n395) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(clk), .RN(
n1718), .QN(n400) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n284), .CK(clk), .RN(
n1719), .Q(P_Sgf[46]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n283), .CK(clk), .RN(
n1720), .Q(P_Sgf[45]), .QN(n1691) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n282), .CK(clk), .RN(
n167), .Q(P_Sgf[44]), .QN(n1685) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n281), .CK(clk), .RN(
n1719), .Q(P_Sgf[43]), .QN(n1692) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n280), .CK(clk), .RN(
n1720), .Q(P_Sgf[42]), .QN(n1693) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n279), .CK(clk), .RN(
n167), .Q(P_Sgf[41]), .QN(n1694) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n278), .CK(clk), .RN(
n1719), .Q(P_Sgf[40]), .QN(n1695) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n277), .CK(clk), .RN(
n1720), .Q(P_Sgf[39]), .QN(n1696) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n276), .CK(clk), .RN(
n167), .Q(P_Sgf[38]), .QN(n1697) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n275), .CK(clk), .RN(
n1719), .Q(P_Sgf[37]), .QN(n1698) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n274), .CK(clk), .RN(
n1720), .Q(P_Sgf[36]), .QN(n1699) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n273), .CK(clk), .RN(
n167), .Q(P_Sgf[35]), .QN(n1700) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n272), .CK(clk), .RN(
n1719), .Q(P_Sgf[34]), .QN(n1701) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n271), .CK(clk), .RN(
n1720), .Q(P_Sgf[33]), .QN(n1702) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n270), .CK(clk), .RN(
n167), .Q(P_Sgf[32]), .QN(n1703) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n269), .CK(clk), .RN(
n1719), .Q(P_Sgf[31]), .QN(n1704) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n268), .CK(clk), .RN(
n1720), .Q(P_Sgf[30]), .QN(n1705) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n267), .CK(clk), .RN(
n167), .Q(P_Sgf[29]), .QN(n1706) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n266), .CK(clk), .RN(
n1719), .Q(P_Sgf[28]), .QN(n1686) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n265), .CK(clk), .RN(
n1720), .Q(P_Sgf[27]), .QN(n1687) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n264), .CK(clk), .RN(
n167), .Q(P_Sgf[26]), .QN(n1688) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n263), .CK(clk), .RN(
n1719), .Q(P_Sgf[25]), .QN(n1689) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n262), .CK(clk), .RN(
n1720), .Q(P_Sgf[24]), .QN(n1690) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n261), .CK(clk), .RN(
n167), .Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n260), .CK(clk), .RN(
n1719), .Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n259), .CK(clk), .RN(
n1720), .Q(P_Sgf[21]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n258), .CK(clk), .RN(
n167), .Q(P_Sgf[20]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n257), .CK(clk), .RN(
n1719), .Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n256), .CK(clk), .RN(
n1720), .Q(P_Sgf[18]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n255), .CK(clk), .RN(
n167), .Q(P_Sgf[17]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n254), .CK(clk), .RN(
n1719), .Q(P_Sgf[16]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n253), .CK(clk), .RN(
n1720), .Q(P_Sgf[15]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n252), .CK(clk), .RN(
n167), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n251), .CK(clk), .RN(
n1719), .Q(P_Sgf[13]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n250), .CK(clk), .RN(
n1721), .Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n249), .CK(clk), .RN(
n1721), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n248), .CK(clk), .RN(
n1721), .Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n246), .CK(clk), .RN(
n1721), .Q(P_Sgf[8]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n245), .CK(clk), .RN(
n1721), .Q(P_Sgf[7]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n244), .CK(clk), .RN(
n1721), .Q(P_Sgf[6]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n243), .CK(clk), .RN(
n1721), .Q(P_Sgf[5]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n242), .CK(clk), .RN(
n1721), .Q(P_Sgf[4]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n241), .CK(clk), .RN(
n1721), .Q(P_Sgf[3]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n240), .CK(clk), .RN(
n1721), .Q(P_Sgf[2]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n239), .CK(clk), .RN(
n167), .Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n238), .CK(clk), .RN(
n167), .Q(P_Sgf[0]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n225), .CK(clk), .RN(n1714), .Q(
Exp_module_Overflow_flag_A) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(clk),
.RN(n1716), .QN(n406) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(clk),
.RN(n1718), .QN(n423) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(clk), .RN(n1710), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(clk), .RN(n1712), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(clk), .RN(n1711), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(clk), .RN(n1713), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(clk), .RN(n1715), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(clk), .RN(n1717), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(clk), .RN(n393), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(clk), .RN(n393), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(clk), .RN(n1708), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(clk), .RN(n393), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(clk), .RN(n1716), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(clk), .RN(n1708), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(clk), .RN(n1709), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(clk), .RN(n1722), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(clk), .RN(n1722), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(clk), .RN(n1722), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(clk), .RN(n1722), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(clk), .RN(n1722), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(clk), .RN(n1722), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(clk), .RN(n1722), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(clk), .RN(n1722), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(clk), .RN(n1712), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(clk), .RN(n1709), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(clk), .RN(n1717), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(clk), .RN(n1708), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(clk), .RN(n1717), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(clk), .RN(n1713), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(clk), .RN(n1711), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(clk), .RN(n1714), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(clk), .RN(n1711), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(clk), .RN(n1711), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(clk), .RN(n1709), .Q(final_result_ieee[31]), .QN(n1707) );
CMPR32X2TS DP_OP_36J10_126_4699_U9 ( .A(DP_OP_36J10_126_4699_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J10_126_4699_n9), .CO(
DP_OP_36J10_126_4699_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J10_126_4699_U8 ( .A(DP_OP_36J10_126_4699_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J10_126_4699_n8), .CO(
DP_OP_36J10_126_4699_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J10_126_4699_U7 ( .A(DP_OP_36J10_126_4699_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J10_126_4699_n7), .CO(
DP_OP_36J10_126_4699_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J10_126_4699_U6 ( .A(DP_OP_36J10_126_4699_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J10_126_4699_n6), .CO(
DP_OP_36J10_126_4699_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J10_126_4699_U5 ( .A(DP_OP_36J10_126_4699_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J10_126_4699_n5), .CO(
DP_OP_36J10_126_4699_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J10_126_4699_U4 ( .A(DP_OP_36J10_126_4699_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J10_126_4699_n4), .CO(
DP_OP_36J10_126_4699_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J10_126_4699_U3 ( .A(DP_OP_36J10_126_4699_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J10_126_4699_n3), .CO(
DP_OP_36J10_126_4699_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J10_126_4699_U2 ( .A(DP_OP_36J10_126_4699_n33), .B(
S_Oper_A_exp[8]), .C(DP_OP_36J10_126_4699_n2), .CO(
DP_OP_36J10_126_4699_n1), .S(Exp_module_Data_S[8]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n310), .CK(clk),
.RN(n1716), .Q(Sgf_normalized_result[23]), .QN(n1684) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(clk), .RN(n1711),
.Q(Add_result[2]), .QN(n1683) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n201), .CK(clk), .RN(n1718),
.Q(underflow_flag), .QN(n1682) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n224), .CK(clk),
.RN(n1712), .Q(Sgf_normalized_result[22]), .QN(n1680) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n379), .CK(clk), .RN(n1719), .Q(
FS_Module_state_reg[0]), .QN(n1679) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n393), .Q(FSM_selector_C),
.QN(n1678) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(clk),
.RN(n1708), .Q(Sgf_normalized_result[20]), .QN(n1677) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n220), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[18]), .QN(n1676) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n235), .CK(clk), .RN(n1718), .Q(
FSM_selector_B[1]), .QN(n1675) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n236), .CK(clk), .RN(n393), .Q(
FSM_selector_B[0]), .QN(n1674) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n218), .CK(clk),
.RN(n1714), .Q(Sgf_normalized_result[16]), .QN(n1673) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n216), .CK(clk),
.RN(n1713), .Q(Sgf_normalized_result[14]), .QN(n1672) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n214), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[12]), .QN(n1671) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n212), .CK(clk),
.RN(n1710), .Q(Sgf_normalized_result[10]), .QN(n1670) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(clk),
.RN(n1714), .Q(Sgf_normalized_result[6]), .QN(n1668) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(clk),
.RN(n1717), .Q(Sgf_normalized_result[4]), .QN(n1667) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(clk), .RN(n1719), .Q(
FS_Module_state_reg[2]), .QN(n1666) );
CMPR42X1TS DP_OP_156J10_125_3370_U46 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .C(
DP_OP_156J10_125_3370_n110), .D(DP_OP_156J10_125_3370_n133), .ICI(
DP_OP_156J10_125_3370_n81), .S(DP_OP_156J10_125_3370_n78), .ICO(
DP_OP_156J10_125_3370_n76), .CO(DP_OP_156J10_125_3370_n77) );
CMPR42X1TS DP_OP_156J10_125_3370_U45 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .C(
DP_OP_156J10_125_3370_n109), .D(DP_OP_156J10_125_3370_n132), .ICI(
DP_OP_156J10_125_3370_n76), .S(DP_OP_156J10_125_3370_n75), .ICO(
DP_OP_156J10_125_3370_n73), .CO(DP_OP_156J10_125_3370_n74) );
CMPR42X1TS DP_OP_156J10_125_3370_U44 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .C(
DP_OP_156J10_125_3370_n108), .D(DP_OP_156J10_125_3370_n131), .ICI(
DP_OP_156J10_125_3370_n73), .S(DP_OP_156J10_125_3370_n72), .ICO(
DP_OP_156J10_125_3370_n70), .CO(DP_OP_156J10_125_3370_n71) );
CMPR42X1TS DP_OP_156J10_125_3370_U43 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .C(
DP_OP_156J10_125_3370_n107), .D(DP_OP_156J10_125_3370_n130), .ICI(
DP_OP_156J10_125_3370_n70), .S(DP_OP_156J10_125_3370_n69), .ICO(
DP_OP_156J10_125_3370_n67), .CO(DP_OP_156J10_125_3370_n68) );
CMPR42X1TS DP_OP_156J10_125_3370_U42 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .C(
DP_OP_156J10_125_3370_n106), .D(DP_OP_156J10_125_3370_n129), .ICI(
DP_OP_156J10_125_3370_n67), .S(DP_OP_156J10_125_3370_n66), .ICO(
DP_OP_156J10_125_3370_n64), .CO(DP_OP_156J10_125_3370_n65) );
CMPR42X1TS DP_OP_156J10_125_3370_U41 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .C(
DP_OP_156J10_125_3370_n105), .D(DP_OP_156J10_125_3370_n128), .ICI(
DP_OP_156J10_125_3370_n64), .S(DP_OP_156J10_125_3370_n63), .ICO(
DP_OP_156J10_125_3370_n61), .CO(DP_OP_156J10_125_3370_n62) );
CMPR42X1TS DP_OP_156J10_125_3370_U40 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .C(
DP_OP_156J10_125_3370_n104), .D(DP_OP_156J10_125_3370_n127), .ICI(
DP_OP_156J10_125_3370_n61), .S(DP_OP_156J10_125_3370_n60), .ICO(
DP_OP_156J10_125_3370_n58), .CO(DP_OP_156J10_125_3370_n59) );
CMPR42X1TS DP_OP_156J10_125_3370_U39 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .C(
DP_OP_156J10_125_3370_n103), .D(DP_OP_156J10_125_3370_n126), .ICI(
DP_OP_156J10_125_3370_n58), .S(DP_OP_156J10_125_3370_n57), .ICO(
DP_OP_156J10_125_3370_n55), .CO(DP_OP_156J10_125_3370_n56) );
CMPR42X1TS DP_OP_156J10_125_3370_U38 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .C(
DP_OP_156J10_125_3370_n102), .D(DP_OP_156J10_125_3370_n125), .ICI(
DP_OP_156J10_125_3370_n55), .S(DP_OP_156J10_125_3370_n54), .ICO(
DP_OP_156J10_125_3370_n52), .CO(DP_OP_156J10_125_3370_n53) );
CMPR42X1TS DP_OP_156J10_125_3370_U37 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .C(
DP_OP_156J10_125_3370_n101), .D(DP_OP_156J10_125_3370_n124), .ICI(
DP_OP_156J10_125_3370_n52), .S(DP_OP_156J10_125_3370_n51), .ICO(
DP_OP_156J10_125_3370_n49), .CO(DP_OP_156J10_125_3370_n50) );
CMPR42X1TS DP_OP_156J10_125_3370_U36 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .C(
DP_OP_156J10_125_3370_n100), .D(DP_OP_156J10_125_3370_n123), .ICI(
DP_OP_156J10_125_3370_n49), .S(DP_OP_156J10_125_3370_n48), .ICO(
DP_OP_156J10_125_3370_n46), .CO(DP_OP_156J10_125_3370_n47) );
CMPR42X1TS DP_OP_156J10_125_3370_U35 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .C(
DP_OP_156J10_125_3370_n99), .D(DP_OP_156J10_125_3370_n122), .ICI(
DP_OP_156J10_125_3370_n46), .S(DP_OP_156J10_125_3370_n45), .ICO(
DP_OP_156J10_125_3370_n43), .CO(DP_OP_156J10_125_3370_n44) );
CMPR42X1TS DP_OP_156J10_125_3370_U34 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .C(
DP_OP_156J10_125_3370_n98), .D(DP_OP_156J10_125_3370_n121), .ICI(
DP_OP_156J10_125_3370_n43), .S(DP_OP_156J10_125_3370_n42), .ICO(
DP_OP_156J10_125_3370_n40), .CO(DP_OP_156J10_125_3370_n41) );
CMPR42X1TS DP_OP_156J10_125_3370_U33 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .C(
DP_OP_156J10_125_3370_n97), .D(DP_OP_156J10_125_3370_n120), .ICI(
DP_OP_156J10_125_3370_n40), .S(DP_OP_156J10_125_3370_n39), .ICO(
DP_OP_156J10_125_3370_n37), .CO(DP_OP_156J10_125_3370_n38) );
CMPR42X1TS DP_OP_156J10_125_3370_U32 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .C(
DP_OP_156J10_125_3370_n96), .D(DP_OP_156J10_125_3370_n119), .ICI(
DP_OP_156J10_125_3370_n37), .S(DP_OP_156J10_125_3370_n36), .ICO(
DP_OP_156J10_125_3370_n34), .CO(DP_OP_156J10_125_3370_n35) );
CMPR42X1TS DP_OP_156J10_125_3370_U31 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(
DP_OP_156J10_125_3370_n95), .D(DP_OP_156J10_125_3370_n118), .ICI(
DP_OP_156J10_125_3370_n34), .S(DP_OP_156J10_125_3370_n33), .ICO(
DP_OP_156J10_125_3370_n31), .CO(DP_OP_156J10_125_3370_n32) );
CMPR42X1TS DP_OP_155J10_124_2038_U253 ( .A(DP_OP_155J10_124_2038_n370), .B(
DP_OP_155J10_124_2038_n360), .C(DP_OP_155J10_124_2038_n365), .D(
DP_OP_155J10_124_2038_n335), .ICI(DP_OP_155J10_124_2038_n332), .S(
DP_OP_155J10_124_2038_n330), .ICO(DP_OP_155J10_124_2038_n328), .CO(
DP_OP_155J10_124_2038_n329) );
CMPR42X1TS DP_OP_155J10_124_2038_U250 ( .A(DP_OP_155J10_124_2038_n364), .B(
DP_OP_155J10_124_2038_n331), .C(DP_OP_155J10_124_2038_n328), .D(
DP_OP_155J10_124_2038_n327), .ICI(DP_OP_155J10_124_2038_n325), .S(
DP_OP_155J10_124_2038_n323), .ICO(DP_OP_155J10_124_2038_n321), .CO(
DP_OP_155J10_124_2038_n322) );
CMPR42X1TS DP_OP_155J10_124_2038_U247 ( .A(DP_OP_155J10_124_2038_n326), .B(
DP_OP_155J10_124_2038_n324), .C(DP_OP_155J10_124_2038_n320), .D(
DP_OP_155J10_124_2038_n318), .ICI(DP_OP_155J10_124_2038_n321), .S(
DP_OP_155J10_124_2038_n316), .ICO(DP_OP_155J10_124_2038_n314), .CO(
DP_OP_155J10_124_2038_n315) );
CMPR42X1TS DP_OP_155J10_124_2038_U245 ( .A(DP_OP_155J10_124_2038_n352), .B(
DP_OP_155J10_124_2038_n319), .C(DP_OP_155J10_124_2038_n317), .D(
DP_OP_155J10_124_2038_n313), .ICI(DP_OP_155J10_124_2038_n314), .S(
DP_OP_155J10_124_2038_n311), .ICO(DP_OP_155J10_124_2038_n309), .CO(
DP_OP_155J10_124_2038_n310) );
CMPR42X1TS DP_OP_155J10_124_2038_U244 ( .A(DP_OP_155J10_124_2038_n351), .B(
DP_OP_155J10_124_2038_n341), .C(DP_OP_155J10_124_2038_n346), .D(
DP_OP_155J10_124_2038_n312), .ICI(DP_OP_155J10_124_2038_n309), .S(
DP_OP_155J10_124_2038_n308), .ICO(DP_OP_155J10_124_2038_n306), .CO(
DP_OP_155J10_124_2038_n307) );
CMPR42X1TS DP_OP_155J10_124_2038_U180 ( .A(DP_OP_155J10_124_2038_n279), .B(
DP_OP_155J10_124_2038_n269), .C(DP_OP_155J10_124_2038_n274), .D(
DP_OP_155J10_124_2038_n244), .ICI(DP_OP_155J10_124_2038_n241), .S(
DP_OP_155J10_124_2038_n239), .ICO(DP_OP_155J10_124_2038_n237), .CO(
DP_OP_155J10_124_2038_n238) );
CMPR42X1TS DP_OP_155J10_124_2038_U177 ( .A(DP_OP_155J10_124_2038_n273), .B(
DP_OP_155J10_124_2038_n240), .C(DP_OP_155J10_124_2038_n237), .D(
DP_OP_155J10_124_2038_n236), .ICI(DP_OP_155J10_124_2038_n234), .S(
DP_OP_155J10_124_2038_n232), .ICO(DP_OP_155J10_124_2038_n230), .CO(
DP_OP_155J10_124_2038_n231) );
CMPR42X1TS DP_OP_155J10_124_2038_U174 ( .A(DP_OP_155J10_124_2038_n235), .B(
DP_OP_155J10_124_2038_n233), .C(DP_OP_155J10_124_2038_n229), .D(
DP_OP_155J10_124_2038_n227), .ICI(DP_OP_155J10_124_2038_n230), .S(
DP_OP_155J10_124_2038_n225), .ICO(DP_OP_155J10_124_2038_n223), .CO(
DP_OP_155J10_124_2038_n224) );
CMPR42X1TS DP_OP_155J10_124_2038_U172 ( .A(DP_OP_155J10_124_2038_n261), .B(
DP_OP_155J10_124_2038_n228), .C(DP_OP_155J10_124_2038_n226), .D(
DP_OP_155J10_124_2038_n222), .ICI(DP_OP_155J10_124_2038_n223), .S(
DP_OP_155J10_124_2038_n220), .ICO(DP_OP_155J10_124_2038_n218), .CO(
DP_OP_155J10_124_2038_n219) );
CMPR42X1TS DP_OP_155J10_124_2038_U171 ( .A(DP_OP_155J10_124_2038_n260), .B(
DP_OP_155J10_124_2038_n250), .C(DP_OP_155J10_124_2038_n255), .D(
DP_OP_155J10_124_2038_n221), .ICI(DP_OP_155J10_124_2038_n218), .S(
DP_OP_155J10_124_2038_n217), .ICO(DP_OP_155J10_124_2038_n215), .CO(
DP_OP_155J10_124_2038_n216) );
CMPR42X1TS DP_OP_155J10_124_2038_U39 ( .A(DP_OP_155J10_124_2038_n202), .B(
DP_OP_155J10_124_2038_n87), .C(DP_OP_155J10_124_2038_n201), .D(
DP_OP_155J10_124_2038_n118), .ICI(DP_OP_155J10_124_2038_n125), .S(
DP_OP_155J10_124_2038_n75), .ICO(DP_OP_155J10_124_2038_n73), .CO(
DP_OP_155J10_124_2038_n74) );
CMPR42X1TS DP_OP_155J10_124_2038_U37 ( .A(DP_OP_155J10_124_2038_n86), .B(
DP_OP_155J10_124_2038_n124), .C(DP_OP_155J10_124_2038_n72), .D(
DP_OP_155J10_124_2038_n117), .ICI(DP_OP_155J10_124_2038_n91), .S(
DP_OP_155J10_124_2038_n70), .ICO(DP_OP_155J10_124_2038_n68), .CO(
DP_OP_155J10_124_2038_n69) );
CMPR42X1TS DP_OP_155J10_124_2038_U35 ( .A(DP_OP_155J10_124_2038_n116), .B(
DP_OP_155J10_124_2038_n109), .C(DP_OP_155J10_124_2038_n123), .D(
DP_OP_155J10_124_2038_n68), .ICI(DP_OP_155J10_124_2038_n67), .S(
DP_OP_155J10_124_2038_n65), .ICO(DP_OP_155J10_124_2038_n63), .CO(
DP_OP_155J10_124_2038_n64) );
CMPR42X1TS DP_OP_155J10_124_2038_U32 ( .A(DP_OP_155J10_124_2038_n122), .B(
DP_OP_155J10_124_2038_n62), .C(DP_OP_155J10_124_2038_n108), .D(
DP_OP_155J10_124_2038_n90), .ICI(DP_OP_155J10_124_2038_n60), .S(
DP_OP_155J10_124_2038_n58), .ICO(DP_OP_155J10_124_2038_n56), .CO(
DP_OP_155J10_124_2038_n57) );
CMPR42X1TS DP_OP_155J10_124_2038_U31 ( .A(DP_OP_155J10_124_2038_n114), .B(
DP_OP_155J10_124_2038_n61), .C(DP_OP_155J10_124_2038_n83), .D(
DP_OP_155J10_124_2038_n197), .ICI(DP_OP_155J10_124_2038_n100), .S(
DP_OP_155J10_124_2038_n55), .ICO(DP_OP_155J10_124_2038_n53), .CO(
DP_OP_155J10_124_2038_n54) );
CMPR42X1TS DP_OP_155J10_124_2038_U30 ( .A(DP_OP_155J10_124_2038_n121), .B(
DP_OP_155J10_124_2038_n107), .C(DP_OP_155J10_124_2038_n59), .D(
DP_OP_155J10_124_2038_n56), .ICI(DP_OP_155J10_124_2038_n55), .S(
DP_OP_155J10_124_2038_n52), .ICO(DP_OP_155J10_124_2038_n50), .CO(
DP_OP_155J10_124_2038_n51) );
CMPR42X1TS DP_OP_155J10_124_2038_U29 ( .A(DP_OP_155J10_124_2038_n120), .B(
DP_OP_155J10_124_2038_n113), .C(DP_OP_155J10_124_2038_n106), .D(
DP_OP_155J10_124_2038_n99), .ICI(DP_OP_155J10_124_2038_n82), .S(
DP_OP_155J10_124_2038_n49), .ICO(DP_OP_155J10_124_2038_n47), .CO(
DP_OP_155J10_124_2038_n48) );
CMPR42X1TS DP_OP_155J10_124_2038_U28 ( .A(DP_OP_155J10_124_2038_n53), .B(
DP_OP_155J10_124_2038_n196), .C(DP_OP_155J10_124_2038_n50), .D(
DP_OP_155J10_124_2038_n54), .ICI(DP_OP_155J10_124_2038_n49), .S(
DP_OP_155J10_124_2038_n46), .ICO(DP_OP_155J10_124_2038_n44), .CO(
DP_OP_155J10_124_2038_n45) );
CMPR42X1TS DP_OP_155J10_124_2038_U27 ( .A(DP_OP_155J10_124_2038_n119), .B(
DP_OP_155J10_124_2038_n112), .C(DP_OP_155J10_124_2038_n105), .D(
DP_OP_155J10_124_2038_n98), .ICI(DP_OP_155J10_124_2038_n47), .S(
DP_OP_155J10_124_2038_n43), .ICO(DP_OP_155J10_124_2038_n41), .CO(
DP_OP_155J10_124_2038_n42) );
CMPR42X1TS DP_OP_155J10_124_2038_U26 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .B(
DP_OP_155J10_124_2038_n81), .C(DP_OP_155J10_124_2038_n48), .D(
DP_OP_155J10_124_2038_n44), .ICI(DP_OP_155J10_124_2038_n43), .S(
DP_OP_155J10_124_2038_n40), .ICO(DP_OP_155J10_124_2038_n38), .CO(
DP_OP_155J10_124_2038_n39) );
CMPR42X1TS DP_OP_155J10_124_2038_U25 ( .A(DP_OP_155J10_124_2038_n111), .B(
DP_OP_155J10_124_2038_n104), .C(DP_OP_155J10_124_2038_n97), .D(
DP_OP_155J10_124_2038_n41), .ICI(DP_OP_155J10_124_2038_n195), .S(
DP_OP_155J10_124_2038_n37), .ICO(DP_OP_155J10_124_2038_n35), .CO(
DP_OP_155J10_124_2038_n36) );
CMPR42X1TS DP_OP_155J10_124_2038_U24 ( .A(DP_OP_155J10_124_2038_n42), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .C(
DP_OP_155J10_124_2038_n80), .D(DP_OP_155J10_124_2038_n38), .ICI(
DP_OP_155J10_124_2038_n37), .S(DP_OP_155J10_124_2038_n34), .ICO(
DP_OP_155J10_124_2038_n32), .CO(DP_OP_155J10_124_2038_n33) );
CMPR42X1TS DP_OP_155J10_124_2038_U23 ( .A(DP_OP_155J10_124_2038_n110), .B(
DP_OP_155J10_124_2038_n103), .C(DP_OP_155J10_124_2038_n96), .D(
DP_OP_155J10_124_2038_n35), .ICI(DP_OP_155J10_124_2038_n194), .S(
DP_OP_155J10_124_2038_n31), .ICO(DP_OP_155J10_124_2038_n29), .CO(
DP_OP_155J10_124_2038_n30) );
CMPR42X1TS DP_OP_155J10_124_2038_U22 ( .A(DP_OP_155J10_124_2038_n36), .B(
DP_OP_155J10_124_2038_n32), .C(DP_OP_155J10_124_2038_n193), .D(
DP_OP_155J10_124_2038_n79), .ICI(DP_OP_155J10_124_2038_n31), .S(
DP_OP_155J10_124_2038_n28), .ICO(DP_OP_155J10_124_2038_n26), .CO(
DP_OP_155J10_124_2038_n27) );
CMPR42X1TS DP_OP_155J10_124_2038_U20 ( .A(DP_OP_155J10_124_2038_n25), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .C(
DP_OP_155J10_124_2038_n30), .D(DP_OP_155J10_124_2038_n78), .ICI(
DP_OP_155J10_124_2038_n26), .S(DP_OP_155J10_124_2038_n23), .ICO(
DP_OP_155J10_124_2038_n21), .CO(DP_OP_155J10_124_2038_n22) );
CMPR42X1TS DP_OP_155J10_124_2038_U19 ( .A(DP_OP_155J10_124_2038_n94), .B(
DP_OP_155J10_124_2038_n101), .C(DP_OP_155J10_124_2038_n24), .D(
DP_OP_155J10_124_2038_n192), .ICI(DP_OP_155J10_124_2038_n21), .S(
DP_OP_155J10_124_2038_n20), .ICO(DP_OP_155J10_124_2038_n18), .CO(
DP_OP_155J10_124_2038_n19) );
CMPR42X1TS DP_OP_154J10_123_2038_U254 ( .A(DP_OP_154J10_123_2038_n369), .B(
DP_OP_154J10_123_2038_n359), .C(DP_OP_154J10_123_2038_n364), .D(
DP_OP_154J10_123_2038_n335), .ICI(DP_OP_154J10_123_2038_n332), .S(
DP_OP_154J10_123_2038_n330), .ICO(DP_OP_154J10_123_2038_n328), .CO(
DP_OP_154J10_123_2038_n329) );
CMPR42X1TS DP_OP_154J10_123_2038_U251 ( .A(DP_OP_154J10_123_2038_n358), .B(
DP_OP_154J10_123_2038_n331), .C(DP_OP_154J10_123_2038_n328), .D(
DP_OP_154J10_123_2038_n327), .ICI(DP_OP_154J10_123_2038_n325), .S(
DP_OP_154J10_123_2038_n323), .ICO(DP_OP_154J10_123_2038_n321), .CO(
DP_OP_154J10_123_2038_n322) );
CMPR42X1TS DP_OP_154J10_123_2038_U248 ( .A(DP_OP_154J10_123_2038_n326), .B(
DP_OP_154J10_123_2038_n320), .C(DP_OP_154J10_123_2038_n324), .D(
DP_OP_154J10_123_2038_n318), .ICI(DP_OP_154J10_123_2038_n321), .S(
DP_OP_154J10_123_2038_n316), .ICO(DP_OP_154J10_123_2038_n314), .CO(
DP_OP_154J10_123_2038_n315) );
CMPR42X1TS DP_OP_154J10_123_2038_U246 ( .A(DP_OP_154J10_123_2038_n351), .B(
DP_OP_154J10_123_2038_n319), .C(DP_OP_154J10_123_2038_n313), .D(
DP_OP_154J10_123_2038_n317), .ICI(DP_OP_154J10_123_2038_n314), .S(
DP_OP_154J10_123_2038_n311), .ICO(DP_OP_154J10_123_2038_n309), .CO(
DP_OP_154J10_123_2038_n310) );
CMPR42X1TS DP_OP_154J10_123_2038_U245 ( .A(Op_MX[21]), .B(Op_MY[21]), .C(
DP_OP_154J10_123_2038_n345), .D(DP_OP_154J10_123_2038_n312), .ICI(
DP_OP_154J10_123_2038_n309), .S(DP_OP_154J10_123_2038_n308), .ICO(
DP_OP_154J10_123_2038_n306), .CO(DP_OP_154J10_123_2038_n307) );
CMPR42X1TS DP_OP_154J10_123_2038_U180 ( .A(DP_OP_154J10_123_2038_n279), .B(
DP_OP_154J10_123_2038_n269), .C(DP_OP_154J10_123_2038_n274), .D(
DP_OP_154J10_123_2038_n244), .ICI(DP_OP_154J10_123_2038_n241), .S(
DP_OP_154J10_123_2038_n239), .ICO(DP_OP_154J10_123_2038_n237), .CO(
DP_OP_154J10_123_2038_n238) );
CMPR42X1TS DP_OP_154J10_123_2038_U177 ( .A(DP_OP_154J10_123_2038_n273), .B(
DP_OP_154J10_123_2038_n240), .C(DP_OP_154J10_123_2038_n237), .D(
DP_OP_154J10_123_2038_n236), .ICI(DP_OP_154J10_123_2038_n234), .S(
DP_OP_154J10_123_2038_n232), .ICO(DP_OP_154J10_123_2038_n230), .CO(
DP_OP_154J10_123_2038_n231) );
CMPR42X1TS DP_OP_154J10_123_2038_U174 ( .A(DP_OP_154J10_123_2038_n235), .B(
DP_OP_154J10_123_2038_n233), .C(DP_OP_154J10_123_2038_n229), .D(
DP_OP_154J10_123_2038_n227), .ICI(DP_OP_154J10_123_2038_n230), .S(
DP_OP_154J10_123_2038_n225), .ICO(DP_OP_154J10_123_2038_n223), .CO(
DP_OP_154J10_123_2038_n224) );
CMPR42X1TS DP_OP_154J10_123_2038_U172 ( .A(DP_OP_154J10_123_2038_n261), .B(
DP_OP_154J10_123_2038_n228), .C(DP_OP_154J10_123_2038_n226), .D(
DP_OP_154J10_123_2038_n222), .ICI(DP_OP_154J10_123_2038_n223), .S(
DP_OP_154J10_123_2038_n220), .ICO(DP_OP_154J10_123_2038_n218), .CO(
DP_OP_154J10_123_2038_n219) );
CMPR42X1TS DP_OP_154J10_123_2038_U171 ( .A(DP_OP_154J10_123_2038_n260), .B(
DP_OP_154J10_123_2038_n250), .C(DP_OP_154J10_123_2038_n255), .D(
DP_OP_154J10_123_2038_n221), .ICI(DP_OP_154J10_123_2038_n218), .S(
DP_OP_154J10_123_2038_n217), .ICO(DP_OP_154J10_123_2038_n215), .CO(
DP_OP_154J10_123_2038_n216) );
CMPR42X1TS DP_OP_154J10_123_2038_U39 ( .A(DP_OP_154J10_123_2038_n202), .B(
DP_OP_154J10_123_2038_n87), .C(DP_OP_154J10_123_2038_n201), .D(
DP_OP_154J10_123_2038_n118), .ICI(DP_OP_154J10_123_2038_n125), .S(
DP_OP_154J10_123_2038_n75), .ICO(DP_OP_154J10_123_2038_n73), .CO(
DP_OP_154J10_123_2038_n74) );
CMPR42X1TS DP_OP_154J10_123_2038_U37 ( .A(DP_OP_154J10_123_2038_n86), .B(
DP_OP_154J10_123_2038_n124), .C(DP_OP_154J10_123_2038_n72), .D(
DP_OP_154J10_123_2038_n117), .ICI(DP_OP_154J10_123_2038_n91), .S(
DP_OP_154J10_123_2038_n70), .ICO(DP_OP_154J10_123_2038_n68), .CO(
DP_OP_154J10_123_2038_n69) );
CMPR42X1TS DP_OP_154J10_123_2038_U35 ( .A(DP_OP_154J10_123_2038_n116), .B(
DP_OP_154J10_123_2038_n109), .C(DP_OP_154J10_123_2038_n123), .D(
DP_OP_154J10_123_2038_n68), .ICI(DP_OP_154J10_123_2038_n67), .S(
DP_OP_154J10_123_2038_n65), .ICO(DP_OP_154J10_123_2038_n63), .CO(
DP_OP_154J10_123_2038_n64) );
CMPR42X1TS DP_OP_154J10_123_2038_U32 ( .A(DP_OP_154J10_123_2038_n62), .B(
DP_OP_154J10_123_2038_n122), .C(DP_OP_154J10_123_2038_n60), .D(
DP_OP_154J10_123_2038_n64), .ICI(DP_OP_154J10_123_2038_n108), .S(
DP_OP_154J10_123_2038_n58), .ICO(DP_OP_154J10_123_2038_n56), .CO(
DP_OP_154J10_123_2038_n57) );
CMPR42X1TS DP_OP_154J10_123_2038_U31 ( .A(DP_OP_154J10_123_2038_n114), .B(
DP_OP_154J10_123_2038_n61), .C(DP_OP_154J10_123_2038_n83), .D(
DP_OP_154J10_123_2038_n197), .ICI(DP_OP_154J10_123_2038_n100), .S(
DP_OP_154J10_123_2038_n55), .ICO(DP_OP_154J10_123_2038_n53), .CO(
DP_OP_154J10_123_2038_n54) );
CMPR42X1TS DP_OP_154J10_123_2038_U30 ( .A(DP_OP_154J10_123_2038_n121), .B(
DP_OP_154J10_123_2038_n59), .C(DP_OP_154J10_123_2038_n107), .D(
DP_OP_154J10_123_2038_n56), .ICI(DP_OP_154J10_123_2038_n55), .S(
DP_OP_154J10_123_2038_n52), .ICO(DP_OP_154J10_123_2038_n50), .CO(
DP_OP_154J10_123_2038_n51) );
CMPR42X1TS DP_OP_154J10_123_2038_U29 ( .A(DP_OP_154J10_123_2038_n120), .B(
DP_OP_154J10_123_2038_n113), .C(DP_OP_154J10_123_2038_n53), .D(
DP_OP_154J10_123_2038_n196), .ICI(DP_OP_154J10_123_2038_n82), .S(
DP_OP_154J10_123_2038_n49), .ICO(DP_OP_154J10_123_2038_n47), .CO(
DP_OP_154J10_123_2038_n48) );
CMPR42X1TS DP_OP_154J10_123_2038_U28 ( .A(DP_OP_154J10_123_2038_n99), .B(
DP_OP_154J10_123_2038_n106), .C(DP_OP_154J10_123_2038_n54), .D(
DP_OP_154J10_123_2038_n50), .ICI(DP_OP_154J10_123_2038_n49), .S(
DP_OP_154J10_123_2038_n46), .ICO(DP_OP_154J10_123_2038_n44), .CO(
DP_OP_154J10_123_2038_n45) );
CMPR42X1TS DP_OP_154J10_123_2038_U27 ( .A(DP_OP_154J10_123_2038_n119), .B(
DP_OP_154J10_123_2038_n112), .C(DP_OP_154J10_123_2038_n98), .D(
DP_OP_154J10_123_2038_n105), .ICI(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .S(
DP_OP_154J10_123_2038_n43), .ICO(DP_OP_154J10_123_2038_n41), .CO(
DP_OP_154J10_123_2038_n42) );
CMPR42X1TS DP_OP_154J10_123_2038_U26 ( .A(DP_OP_154J10_123_2038_n47), .B(
DP_OP_154J10_123_2038_n81), .C(DP_OP_154J10_123_2038_n44), .D(
DP_OP_154J10_123_2038_n48), .ICI(DP_OP_154J10_123_2038_n43), .S(
DP_OP_154J10_123_2038_n40), .ICO(DP_OP_154J10_123_2038_n38), .CO(
DP_OP_154J10_123_2038_n39) );
CMPR42X1TS DP_OP_154J10_123_2038_U25 ( .A(DP_OP_154J10_123_2038_n111), .B(
DP_OP_154J10_123_2038_n97), .C(DP_OP_154J10_123_2038_n104), .D(
DP_OP_154J10_123_2038_n195), .ICI(DP_OP_154J10_123_2038_n41), .S(
DP_OP_154J10_123_2038_n37), .ICO(DP_OP_154J10_123_2038_n35), .CO(
DP_OP_154J10_123_2038_n36) );
CMPR42X1TS DP_OP_154J10_123_2038_U24 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(
DP_OP_154J10_123_2038_n80), .C(DP_OP_154J10_123_2038_n42), .D(
DP_OP_154J10_123_2038_n38), .ICI(DP_OP_154J10_123_2038_n37), .S(
DP_OP_154J10_123_2038_n34), .ICO(DP_OP_154J10_123_2038_n32), .CO(
DP_OP_154J10_123_2038_n33) );
CMPR42X1TS DP_OP_154J10_123_2038_U23 ( .A(DP_OP_154J10_123_2038_n110), .B(
DP_OP_154J10_123_2038_n96), .C(DP_OP_154J10_123_2038_n103), .D(
DP_OP_154J10_123_2038_n35), .ICI(DP_OP_154J10_123_2038_n194), .S(
DP_OP_154J10_123_2038_n31), .ICO(DP_OP_154J10_123_2038_n29), .CO(
DP_OP_154J10_123_2038_n30) );
CMPR42X1TS DP_OP_154J10_123_2038_U22 ( .A(DP_OP_154J10_123_2038_n36), .B(
DP_OP_154J10_123_2038_n79), .C(DP_OP_154J10_123_2038_n32), .D(
DP_OP_154J10_123_2038_n31), .ICI(DP_OP_154J10_123_2038_n193), .S(
DP_OP_154J10_123_2038_n28), .ICO(DP_OP_154J10_123_2038_n26), .CO(
DP_OP_154J10_123_2038_n27) );
CMPR42X1TS DP_OP_154J10_123_2038_U20 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .B(
DP_OP_154J10_123_2038_n25), .C(DP_OP_154J10_123_2038_n78), .D(
DP_OP_154J10_123_2038_n30), .ICI(DP_OP_154J10_123_2038_n26), .S(
DP_OP_154J10_123_2038_n23), .ICO(DP_OP_154J10_123_2038_n21), .CO(
DP_OP_154J10_123_2038_n22) );
CMPR42X1TS DP_OP_154J10_123_2038_U19 ( .A(DP_OP_154J10_123_2038_n94), .B(
DP_OP_154J10_123_2038_n101), .C(DP_OP_154J10_123_2038_n24), .D(
DP_OP_154J10_123_2038_n192), .ICI(DP_OP_154J10_123_2038_n21), .S(
DP_OP_154J10_123_2038_n20), .ICO(DP_OP_154J10_123_2038_n18), .CO(
DP_OP_154J10_123_2038_n19) );
CMPR42X1TS DP_OP_153J10_122_5442_U283 ( .A(DP_OP_153J10_122_5442_n394), .B(
DP_OP_153J10_122_5442_n414), .C(DP_OP_153J10_122_5442_n407), .D(
DP_OP_153J10_122_5442_n400), .ICI(DP_OP_153J10_122_5442_n380), .S(
DP_OP_153J10_122_5442_n377), .ICO(DP_OP_153J10_122_5442_n375), .CO(
DP_OP_153J10_122_5442_n376) );
CMPR42X1TS DP_OP_153J10_122_5442_U282 ( .A(DP_OP_153J10_122_5442_n413), .B(
DP_OP_153J10_122_5442_n393), .C(DP_OP_153J10_122_5442_n399), .D(
DP_OP_153J10_122_5442_n406), .ICI(DP_OP_153J10_122_5442_n375), .S(
DP_OP_153J10_122_5442_n374), .ICO(DP_OP_153J10_122_5442_n372), .CO(
DP_OP_153J10_122_5442_n373) );
CMPR42X1TS DP_OP_153J10_122_5442_U280 ( .A(DP_OP_153J10_122_5442_n405), .B(
DP_OP_153J10_122_5442_n398), .C(DP_OP_153J10_122_5442_n412), .D(
DP_OP_153J10_122_5442_n371), .ICI(DP_OP_153J10_122_5442_n372), .S(
DP_OP_153J10_122_5442_n369), .ICO(DP_OP_153J10_122_5442_n367), .CO(
DP_OP_153J10_122_5442_n368) );
CMPR42X1TS DP_OP_153J10_122_5442_U278 ( .A(DP_OP_153J10_122_5442_n404), .B(
DP_OP_153J10_122_5442_n370), .C(DP_OP_153J10_122_5442_n397), .D(
DP_OP_153J10_122_5442_n366), .ICI(DP_OP_153J10_122_5442_n367), .S(
DP_OP_153J10_122_5442_n364), .ICO(DP_OP_153J10_122_5442_n362), .CO(
DP_OP_153J10_122_5442_n363) );
CMPR42X1TS DP_OP_153J10_122_5442_U277 ( .A(DP_OP_153J10_122_5442_n365), .B(
DP_OP_153J10_122_5442_n396), .C(DP_OP_153J10_122_5442_n392), .D(
DP_OP_153J10_122_5442_n403), .ICI(DP_OP_153J10_122_5442_n362), .S(
DP_OP_153J10_122_5442_n361), .ICO(DP_OP_153J10_122_5442_n359), .CO(
DP_OP_153J10_122_5442_n360) );
CMPR42X1TS DP_OP_153J10_122_5442_U192 ( .A(DP_OP_153J10_122_5442_n306), .B(
DP_OP_153J10_122_5442_n296), .C(DP_OP_153J10_122_5442_n274), .D(
DP_OP_153J10_122_5442_n273), .ICI(DP_OP_153J10_122_5442_n311), .S(
DP_OP_153J10_122_5442_n271), .ICO(DP_OP_153J10_122_5442_n269), .CO(
DP_OP_153J10_122_5442_n270) );
CMPR42X1TS DP_OP_153J10_122_5442_U189 ( .A(DP_OP_153J10_122_5442_n268), .B(
DP_OP_153J10_122_5442_n305), .C(DP_OP_153J10_122_5442_n290), .D(
DP_OP_153J10_122_5442_n266), .ICI(DP_OP_153J10_122_5442_n269), .S(
DP_OP_153J10_122_5442_n264), .ICO(DP_OP_153J10_122_5442_n262), .CO(
DP_OP_153J10_122_5442_n263) );
CMPR42X1TS DP_OP_153J10_122_5442_U186 ( .A(DP_OP_153J10_122_5442_n289), .B(
DP_OP_153J10_122_5442_n265), .C(DP_OP_153J10_122_5442_n261), .D(
DP_OP_153J10_122_5442_n262), .ICI(DP_OP_153J10_122_5442_n259), .S(
DP_OP_153J10_122_5442_n257), .ICO(DP_OP_153J10_122_5442_n255), .CO(
DP_OP_153J10_122_5442_n256) );
CMPR42X1TS DP_OP_153J10_122_5442_U184 ( .A(DP_OP_153J10_122_5442_n293), .B(
DP_OP_153J10_122_5442_n288), .C(DP_OP_153J10_122_5442_n254), .D(
DP_OP_153J10_122_5442_n258), .ICI(DP_OP_153J10_122_5442_n255), .S(
DP_OP_153J10_122_5442_n252), .ICO(DP_OP_153J10_122_5442_n250), .CO(
DP_OP_153J10_122_5442_n251) );
CMPR42X1TS DP_OP_153J10_122_5442_U183 ( .A(DP_OP_153J10_122_5442_n292), .B(
DP_OP_153J10_122_5442_n282), .C(DP_OP_153J10_122_5442_n287), .D(
DP_OP_153J10_122_5442_n253), .ICI(DP_OP_153J10_122_5442_n250), .S(
DP_OP_153J10_122_5442_n249), .ICO(DP_OP_153J10_122_5442_n247), .CO(
DP_OP_153J10_122_5442_n248) );
CMPR42X1TS DP_OP_153J10_122_5442_U63 ( .A(DP_OP_153J10_122_5442_n234), .B(
DP_OP_153J10_122_5442_n205), .C(DP_OP_153J10_122_5442_n191), .D(
DP_OP_153J10_122_5442_n128), .ICI(DP_OP_153J10_122_5442_n127), .S(
DP_OP_153J10_122_5442_n125), .ICO(DP_OP_153J10_122_5442_n123), .CO(
DP_OP_153J10_122_5442_n124) );
CMPR42X1TS DP_OP_153J10_122_5442_U60 ( .A(DP_OP_153J10_122_5442_n204), .B(
DP_OP_153J10_122_5442_n183), .C(DP_OP_153J10_122_5442_n122), .D(
DP_OP_153J10_122_5442_n120), .ICI(DP_OP_153J10_122_5442_n124), .S(
DP_OP_153J10_122_5442_n118), .ICO(DP_OP_153J10_122_5442_n116), .CO(
DP_OP_153J10_122_5442_n117) );
CMPR42X1TS DP_OP_153J10_122_5442_U58 ( .A(DP_OP_153J10_122_5442_n121), .B(
DP_OP_153J10_122_5442_n182), .C(DP_OP_153J10_122_5442_n196), .D(
DP_OP_153J10_122_5442_n115), .ICI(DP_OP_153J10_122_5442_n116), .S(
DP_OP_153J10_122_5442_n113), .ICO(DP_OP_153J10_122_5442_n111), .CO(
DP_OP_153J10_122_5442_n112) );
CMPR42X1TS DP_OP_153J10_122_5442_U57 ( .A(DP_OP_153J10_122_5442_n119), .B(
DP_OP_153J10_122_5442_n175), .C(DP_OP_153J10_122_5442_n203), .D(
DP_OP_153J10_122_5442_n113), .ICI(DP_OP_153J10_122_5442_n117), .S(
DP_OP_153J10_122_5442_n110), .ICO(DP_OP_153J10_122_5442_n108), .CO(
DP_OP_153J10_122_5442_n109) );
CMPR42X1TS DP_OP_153J10_122_5442_U54 ( .A(DP_OP_153J10_122_5442_n107), .B(
DP_OP_153J10_122_5442_n195), .C(DP_OP_153J10_122_5442_n174), .D(
DP_OP_153J10_122_5442_n105), .ICI(DP_OP_153J10_122_5442_n202), .S(
DP_OP_153J10_122_5442_n103), .ICO(DP_OP_153J10_122_5442_n101), .CO(
DP_OP_153J10_122_5442_n102) );
CMPR42X1TS DP_OP_153J10_122_5442_U53 ( .A(DP_OP_153J10_122_5442_n112), .B(
DP_OP_153J10_122_5442_n108), .C(DP_OP_153J10_122_5442_n167), .D(
DP_OP_153J10_122_5442_n103), .ICI(DP_OP_153J10_122_5442_n109), .S(
DP_OP_153J10_122_5442_n100), .ICO(DP_OP_153J10_122_5442_n98), .CO(
DP_OP_153J10_122_5442_n99) );
CMPR42X1TS DP_OP_153J10_122_5442_U51 ( .A(DP_OP_153J10_122_5442_n106), .B(
DP_OP_153J10_122_5442_n97), .C(DP_OP_153J10_122_5442_n173), .D(
DP_OP_153J10_122_5442_n187), .ICI(DP_OP_153J10_122_5442_n104), .S(
DP_OP_153J10_122_5442_n95), .ICO(DP_OP_153J10_122_5442_n93), .CO(
DP_OP_153J10_122_5442_n94) );
CMPR42X1TS DP_OP_153J10_122_5442_U50 ( .A(DP_OP_153J10_122_5442_n101), .B(
DP_OP_153J10_122_5442_n166), .C(DP_OP_153J10_122_5442_n194), .D(
DP_OP_153J10_122_5442_n98), .ICI(DP_OP_153J10_122_5442_n95), .S(
DP_OP_153J10_122_5442_n92), .ICO(DP_OP_153J10_122_5442_n90), .CO(
DP_OP_153J10_122_5442_n91) );
CMPR42X1TS DP_OP_153J10_122_5442_U49 ( .A(DP_OP_153J10_122_5442_n201), .B(
DP_OP_153J10_122_5442_n159), .C(DP_OP_153J10_122_5442_n102), .D(
DP_OP_153J10_122_5442_n229), .ICI(DP_OP_153J10_122_5442_n92), .S(
DP_OP_153J10_122_5442_n89), .ICO(DP_OP_153J10_122_5442_n87), .CO(
DP_OP_153J10_122_5442_n88) );
CMPR42X1TS DP_OP_153J10_122_5442_U46 ( .A(DP_OP_153J10_122_5442_n93), .B(
DP_OP_153J10_122_5442_n165), .C(DP_OP_153J10_122_5442_n186), .D(
DP_OP_153J10_122_5442_n151), .ICI(DP_OP_153J10_122_5442_n158), .S(
DP_OP_153J10_122_5442_n82), .ICO(DP_OP_153J10_122_5442_n80), .CO(
DP_OP_153J10_122_5442_n81) );
CMPR42X1TS DP_OP_153J10_122_5442_U45 ( .A(DP_OP_153J10_122_5442_n200), .B(
DP_OP_153J10_122_5442_n90), .C(DP_OP_153J10_122_5442_n94), .D(
DP_OP_153J10_122_5442_n193), .ICI(DP_OP_153J10_122_5442_n87), .S(
DP_OP_153J10_122_5442_n79), .ICO(DP_OP_153J10_122_5442_n77), .CO(
DP_OP_153J10_122_5442_n78) );
CMPR42X1TS DP_OP_153J10_122_5442_U44 ( .A(DP_OP_153J10_122_5442_n84), .B(
DP_OP_153J10_122_5442_n91), .C(DP_OP_153J10_122_5442_n82), .D(
DP_OP_153J10_122_5442_n79), .ICI(DP_OP_153J10_122_5442_n228), .S(
DP_OP_153J10_122_5442_n76), .ICO(DP_OP_153J10_122_5442_n74), .CO(
DP_OP_153J10_122_5442_n75) );
CMPR42X1TS DP_OP_153J10_122_5442_U41 ( .A(DP_OP_153J10_122_5442_n73), .B(
DP_OP_153J10_122_5442_n83), .C(DP_OP_153J10_122_5442_n192), .D(
DP_OP_153J10_122_5442_n150), .ICI(DP_OP_153J10_122_5442_n71), .S(
DP_OP_153J10_122_5442_n69), .ICO(DP_OP_153J10_122_5442_n67), .CO(
DP_OP_153J10_122_5442_n68) );
CMPR42X1TS DP_OP_153J10_122_5442_U40 ( .A(DP_OP_153J10_122_5442_n80), .B(
DP_OP_153J10_122_5442_n185), .C(DP_OP_153J10_122_5442_n157), .D(
DP_OP_153J10_122_5442_n77), .ICI(DP_OP_153J10_122_5442_n81), .S(
DP_OP_153J10_122_5442_n66), .ICO(DP_OP_153J10_122_5442_n64), .CO(
DP_OP_153J10_122_5442_n65) );
CMPR42X1TS DP_OP_153J10_122_5442_U39 ( .A(DP_OP_153J10_122_5442_n78), .B(
DP_OP_153J10_122_5442_n69), .C(DP_OP_153J10_122_5442_n74), .D(
DP_OP_153J10_122_5442_n66), .ICI(DP_OP_153J10_122_5442_n227), .S(
DP_OP_153J10_122_5442_n63), .ICO(DP_OP_153J10_122_5442_n61), .CO(
DP_OP_153J10_122_5442_n62) );
CMPR42X1TS DP_OP_153J10_122_5442_U37 ( .A(DP_OP_153J10_122_5442_n72), .B(
DP_OP_153J10_122_5442_n149), .C(DP_OP_153J10_122_5442_n184), .D(
DP_OP_153J10_122_5442_n156), .ICI(DP_OP_153J10_122_5442_n60), .S(
DP_OP_153J10_122_5442_n58), .ICO(DP_OP_153J10_122_5442_n56), .CO(
DP_OP_153J10_122_5442_n57) );
CMPR42X1TS DP_OP_153J10_122_5442_U36 ( .A(DP_OP_153J10_122_5442_n177), .B(
DP_OP_153J10_122_5442_n70), .C(DP_OP_153J10_122_5442_n67), .D(
DP_OP_153J10_122_5442_n64), .ICI(DP_OP_153J10_122_5442_n68), .S(
DP_OP_153J10_122_5442_n55), .ICO(DP_OP_153J10_122_5442_n53), .CO(
DP_OP_153J10_122_5442_n54) );
CMPR42X1TS DP_OP_153J10_122_5442_U35 ( .A(DP_OP_153J10_122_5442_n58), .B(
DP_OP_153J10_122_5442_n65), .C(DP_OP_153J10_122_5442_n55), .D(
DP_OP_153J10_122_5442_n61), .ICI(DP_OP_153J10_122_5442_n62), .S(
DP_OP_153J10_122_5442_n52), .ICO(DP_OP_153J10_122_5442_n50), .CO(
DP_OP_153J10_122_5442_n51) );
CMPR42X1TS DP_OP_153J10_122_5442_U34 ( .A(DP_OP_153J10_122_5442_n133), .B(
DP_OP_153J10_122_5442_n162), .C(DP_OP_153J10_122_5442_n148), .D(
DP_OP_153J10_122_5442_n176), .ICI(DP_OP_153J10_122_5442_n155), .S(
DP_OP_153J10_122_5442_n49), .ICO(DP_OP_153J10_122_5442_n47), .CO(
DP_OP_153J10_122_5442_n48) );
CMPR42X1TS DP_OP_153J10_122_5442_U33 ( .A(DP_OP_153J10_122_5442_n169), .B(
DP_OP_153J10_122_5442_n59), .C(DP_OP_153J10_122_5442_n56), .D(
DP_OP_153J10_122_5442_n53), .ICI(DP_OP_153J10_122_5442_n57), .S(
DP_OP_153J10_122_5442_n46), .ICO(DP_OP_153J10_122_5442_n44), .CO(
DP_OP_153J10_122_5442_n45) );
CMPR42X1TS DP_OP_153J10_122_5442_U32 ( .A(DP_OP_153J10_122_5442_n49), .B(
DP_OP_153J10_122_5442_n54), .C(DP_OP_153J10_122_5442_n46), .D(
DP_OP_153J10_122_5442_n50), .ICI(DP_OP_153J10_122_5442_n51), .S(
DP_OP_153J10_122_5442_n43), .ICO(DP_OP_153J10_122_5442_n41), .CO(
DP_OP_153J10_122_5442_n42) );
CMPR42X1TS DP_OP_153J10_122_5442_U30 ( .A(DP_OP_153J10_122_5442_n161), .B(
DP_OP_153J10_122_5442_n154), .C(DP_OP_153J10_122_5442_n47), .D(
DP_OP_153J10_122_5442_n40), .ICI(DP_OP_153J10_122_5442_n44), .S(
DP_OP_153J10_122_5442_n38), .ICO(DP_OP_153J10_122_5442_n36), .CO(
DP_OP_153J10_122_5442_n37) );
CMPR42X1TS DP_OP_153J10_122_5442_U29 ( .A(DP_OP_153J10_122_5442_n48), .B(
DP_OP_153J10_122_5442_n38), .C(DP_OP_153J10_122_5442_n45), .D(
DP_OP_153J10_122_5442_n41), .ICI(DP_OP_153J10_122_5442_n224), .S(
DP_OP_153J10_122_5442_n35), .ICO(DP_OP_153J10_122_5442_n33), .CO(
DP_OP_153J10_122_5442_n34) );
CMPR42X1TS DP_OP_153J10_122_5442_U25 ( .A(DP_OP_153J10_122_5442_n36), .B(
DP_OP_153J10_122_5442_n32), .C(DP_OP_153J10_122_5442_n30), .D(
DP_OP_153J10_122_5442_n37), .ICI(DP_OP_153J10_122_5442_n33), .S(
DP_OP_153J10_122_5442_n28), .ICO(DP_OP_153J10_122_5442_n26), .CO(
DP_OP_153J10_122_5442_n27) );
CMPR42X1TS DP_OP_153J10_122_5442_U22 ( .A(DP_OP_153J10_122_5442_n145), .B(
DP_OP_153J10_122_5442_n31), .C(DP_OP_153J10_122_5442_n29), .D(
DP_OP_153J10_122_5442_n25), .ICI(DP_OP_153J10_122_5442_n26), .S(
DP_OP_153J10_122_5442_n23), .ICO(DP_OP_153J10_122_5442_n21), .CO(
DP_OP_153J10_122_5442_n22) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n210), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[8]), .QN(n1669) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(clk), .RN(
n1712), .Q(Op_MX[11]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(clk), .RN(
n1715), .Q(Op_MY[21]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(clk), .RN(
n1710), .Q(Op_MX[0]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n1714), .Q(Op_MY[22]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(clk), .RN(
n393), .Q(Op_MX[2]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(
n1716), .Q(Op_MX[9]) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(clk), .RN(n1719), .Q(
FS_Module_state_reg[3]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(clk), .RN(
n1716), .Q(Op_MX[17]), .QN(n419) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(clk),
.RN(n1713), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(clk), .RN(
n393), .Q(Op_MY[12]), .QN(n405) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(clk), .RN(
n1715), .Q(Op_MY[17]), .QN(n402) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(clk),
.RN(n1711), .Q(Sgf_normalized_result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n207), .CK(clk),
.RN(n1713), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n209), .CK(clk),
.RN(n1718), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n211), .CK(clk),
.RN(n1710), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n213), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n215), .CK(clk),
.RN(n1713), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n217), .CK(clk),
.RN(n1710), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n219), .CK(clk),
.RN(n1713), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n221), .CK(clk),
.RN(n1714), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n223), .CK(clk),
.RN(n1710), .Q(Sgf_normalized_result[21]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n1716), .Q(Op_MY[11]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n237), .CK(clk), .RN(
n167), .Q(P_Sgf[47]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n227), .CK(clk), .RN(n1715),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n228), .CK(clk), .RN(n393),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(clk), .RN(n1716),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(clk), .RN(n1714),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(clk), .RN(n1715),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(clk), .RN(n1712),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(clk), .RN(n1712),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(clk), .RN(n1708),
.Q(exp_oper_result[0]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(clk), .RN(
n1718), .Q(FSM_add_overflow_flag) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n226), .CK(clk), .RN(n1712),
.Q(exp_oper_result[8]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(clk), .RN(
n1718), .Q(Op_MY[2]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n1717), .Q(Op_MX[23]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n393), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n1716), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n1711), .Q(Op_MX[25]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n247), .CK(clk), .RN(
n1721), .Q(P_Sgf[9]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(clk), .RN(
n1716), .Q(Op_MY[18]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(clk), .RN(
n1715), .Q(Op_MX[21]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(clk), .RN(
n1710), .Q(Op_MX[20]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(clk), .RN(
n1718), .Q(Op_MX[19]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(clk), .RN(
n1708), .Q(Op_MX[22]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(clk), .RN(
n1717), .Q(Op_MY[0]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(clk), .RN(
n1712), .Q(Op_MY[20]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(clk), .RN(
n1714), .Q(Op_MX[18]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(clk), .RN(
n1717), .Q(Op_MX[10]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(clk), .RN(
n1708), .Q(Op_MY[19]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(clk), .RN(
n1713), .Q(Op_MX[7]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(clk), .RN(
n1711), .Q(Op_MX[3]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(clk), .RN(
n393), .Q(Op_MX[5]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(clk), .RN(
n1711), .Q(Op_MY[7]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(clk), .RN(
n1718), .Q(Op_MX[13]), .QN(n420) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(clk), .RN(
n1708), .Q(Op_MY[13]), .QN(n403) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(clk), .RN(
n1716), .Q(Op_MX[15]), .QN(n422) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(clk), .RN(
n393), .Q(Op_MX[16]), .QN(n421) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(clk), .RN(
n1717), .Q(Op_MY[16]), .QN(n404) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n1718), .Q(Op_MY[23]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n1708), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n1716), .Q(Op_MX[24]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n1711), .Q(Op_MY[27]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(clk), .RN(
n393), .Q(Op_MY[3]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(clk), .RN(
n1718), .Q(n392) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(clk), .RN(
n1718), .Q(Op_MY[4]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(clk), .RN(
n393), .Q(Op_MY[5]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(clk), .RN(
n1709), .Q(n391) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(clk), .RN(n167), .Q(
FS_Module_state_reg[1]) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n376), .CK(clk), .RN(n1716), .Q(FSM_selector_A),
.QN(n1681) );
CMPR32X2TS DP_OP_36J10_126_4699_U10 ( .A(S_Oper_A_exp[0]), .B(
DP_OP_36J10_126_4699_n33), .C(DP_OP_36J10_126_4699_n22), .CO(
DP_OP_36J10_126_4699_n9), .S(Exp_module_Data_S[0]) );
OR2X6TS U406 ( .A(n1389), .B(FSM_selector_C), .Y(n1306) );
NAND2X4TS U407 ( .A(n1340), .B(n1339), .Y(n1352) );
CMPR32X2TS U408 ( .A(n632), .B(n572), .C(n631), .CO(n610), .S(n708) );
CMPR32X2TS U409 ( .A(n1197), .B(n1196), .C(n1195), .CO(n1192), .S(n1635) );
CMPR32X2TS U410 ( .A(Op_MX[10]), .B(Op_MX[22]), .C(n522), .CO(n515), .S(n637) );
CMPR32X2TS U411 ( .A(n391), .B(Op_MY[22]), .C(n525), .CO(n514), .S(n643) );
CMPR32X2TS U412 ( .A(n495), .B(Op_MY[21]), .C(n521), .CO(n525), .S(n657) );
CMPR32X2TS U413 ( .A(Op_MX[9]), .B(Op_MX[21]), .C(n517), .CO(n522), .S(n661)
);
CMPR32X2TS U414 ( .A(n496), .B(Op_MX[20]), .C(n518), .CO(n517), .S(n604) );
CMPR32X2TS U415 ( .A(n492), .B(Op_MY[20]), .C(n519), .CO(n521), .S(n606) );
CMPR32X2TS U416 ( .A(Op_MX[7]), .B(Op_MX[19]), .C(n520), .CO(n518), .S(n551)
);
CMPR32X2TS U417 ( .A(Op_MY[7]), .B(Op_MY[19]), .C(n516), .CO(n519), .S(n546)
);
CMPR32X2TS U418 ( .A(n499), .B(Op_MX[18]), .C(n579), .CO(n520), .S(n611) );
CMPR32X2TS U419 ( .A(n498), .B(Op_MY[18]), .C(n577), .CO(n516), .S(n750) );
CMPR32X2TS U420 ( .A(Op_MY[16]), .B(Op_MY[22]), .C(n848), .CO(n847), .S(n872) );
CMPR32X2TS U421 ( .A(n483), .B(Op_MY[21]), .C(n850), .CO(n848), .S(n874) );
CMPR32X2TS U422 ( .A(Op_MY[5]), .B(Op_MY[17]), .C(n578), .CO(n577), .S(n752)
);
CMPR32X4TS U423 ( .A(Op_MX[5]), .B(Op_MX[17]), .C(n571), .CO(n579), .S(n572)
);
CMPR32X2TS U424 ( .A(Op_MX[16]), .B(Op_MX[22]), .C(n844), .CO(n876), .S(n846) );
CMPR32X2TS U425 ( .A(n485), .B(Op_MY[20]), .C(n852), .CO(n850), .S(n883) );
CMPR32X2TS U426 ( .A(Op_MY[4]), .B(Op_MY[16]), .C(n580), .CO(n578), .S(n730)
);
CMPR32X2TS U427 ( .A(Op_MY[13]), .B(Op_MY[19]), .C(n854), .CO(n852), .S(
n1129) );
CMPR32X2TS U428 ( .A(n487), .B(Op_MX[20]), .C(n859), .CO(n842), .S(n861) );
CMPR32X4TS U429 ( .A(Op_MX[3]), .B(Op_MX[15]), .C(n573), .CO(n575), .S(n574)
);
CMPR32X4TS U430 ( .A(n493), .B(Op_MX[13]), .C(n528), .CO(n582), .S(n529) );
CMPR32X2TS U431 ( .A(n1097), .B(n1196), .C(n1096), .CO(n1114), .S(n1116) );
CMPR32X2TS U432 ( .A(n392), .B(Op_MX[10]), .C(n962), .CO(n993), .S(n963) );
NOR2XLTS U433 ( .A(n773), .B(n763), .Y(n809) );
NOR2XLTS U434 ( .A(n402), .B(n420), .Y(n834) );
NOR2XLTS U435 ( .A(n402), .B(n486), .Y(n831) );
NOR2XLTS U436 ( .A(n747), .B(n736), .Y(n794) );
AO22X1TS U437 ( .A0(n1661), .A1(P_Sgf[47]), .B0(n1660), .B1(n1659), .Y(n237)
);
AO22X1TS U438 ( .A0(n1629), .A1(P_Sgf[46]), .B0(n1660), .B1(n1511), .Y(n284)
);
AO22X1TS U439 ( .A0(n1661), .A1(P_Sgf[45]), .B0(n1612), .B1(n1514), .Y(n283)
);
AO22X1TS U440 ( .A0(n1629), .A1(P_Sgf[44]), .B0(n1643), .B1(n1517), .Y(n282)
);
AO22X1TS U441 ( .A0(n1661), .A1(P_Sgf[43]), .B0(n1643), .B1(n1520), .Y(n281)
);
AO22X1TS U442 ( .A0(n1629), .A1(P_Sgf[42]), .B0(n1612), .B1(n1523), .Y(n280)
);
AO22X1TS U443 ( .A0(n1661), .A1(P_Sgf[41]), .B0(n1612), .B1(n1526), .Y(n279)
);
AO22X1TS U444 ( .A0(n1629), .A1(P_Sgf[40]), .B0(n1612), .B1(n1529), .Y(n278)
);
AO22X1TS U445 ( .A0(n1661), .A1(P_Sgf[39]), .B0(n1612), .B1(n1532), .Y(n277)
);
AO22X1TS U446 ( .A0(n1629), .A1(P_Sgf[38]), .B0(n1612), .B1(n1535), .Y(n276)
);
AO22X1TS U447 ( .A0(n1661), .A1(P_Sgf[37]), .B0(n1612), .B1(n1539), .Y(n275)
);
ADDFX1TS U448 ( .A(n1586), .B(n1585), .CI(n1584), .CO(n1580), .S(n1587) );
OAI21X1TS U449 ( .A0(n1141), .A1(n1140), .B0(n1142), .Y(n1139) );
OAI21X1TS U450 ( .A0(n1101), .A1(n1100), .B0(n1102), .Y(n1099) );
OAI21X1TS U451 ( .A0(n748), .A1(n712), .B0(n700), .Y(n699) );
NOR2X1TS U452 ( .A(n754), .B(n770), .Y(n626) );
NOR2X1TS U453 ( .A(n754), .B(n790), .Y(DP_OP_153J10_122_5442_n155) );
NOR2X1TS U454 ( .A(n771), .B(n790), .Y(n629) );
NOR2X1TS U455 ( .A(n760), .B(n790), .Y(n635) );
NOR2X1TS U456 ( .A(n755), .B(n789), .Y(n627) );
NOR2X1TS U457 ( .A(n759), .B(n789), .Y(n633) );
NOR2X1TS U458 ( .A(n755), .B(n757), .Y(DP_OP_153J10_122_5442_n176) );
NOR2X1TS U459 ( .A(n790), .B(n789), .Y(n791) );
NOR2X1TS U460 ( .A(n773), .B(n765), .Y(n674) );
NOR2X1TS U461 ( .A(n773), .B(n743), .Y(n767) );
NOR2X1TS U462 ( .A(n772), .B(n769), .Y(n810) );
NOR2X1TS U463 ( .A(n773), .B(n812), .Y(n540) );
NOR2X1TS U464 ( .A(n765), .B(n769), .Y(n808) );
ADDFX1TS U465 ( .A(n614), .B(n752), .CI(n613), .CO(n619), .S(n615) );
NOR2X1TS U466 ( .A(n743), .B(n680), .Y(n675) );
NOR2X1TS U467 ( .A(n772), .B(n680), .Y(n807) );
CLKBUFX3TS U468 ( .A(n860), .Y(n937) );
NAND2X2TS U469 ( .A(n876), .B(Op_MX[17]), .Y(n1140) );
INVX3TS U470 ( .A(n574), .Y(n729) );
INVX3TS U471 ( .A(n914), .Y(n917) );
OR3X2TS U472 ( .A(underflow_flag), .B(overflow_flag), .C(n1662), .Y(n1664)
);
ADDFX1TS U473 ( .A(n392), .B(Op_MX[16]), .CI(n575), .CO(n571), .S(n621) );
INVX3TS U474 ( .A(n1035), .Y(n1039) );
NOR2X4TS U475 ( .A(n1385), .B(n1654), .Y(n1345) );
INVX6TS U476 ( .A(n1665), .Y(n1662) );
BUFX6TS U477 ( .A(n1722), .Y(n393) );
NAND2BX4TS U478 ( .AN(n1344), .B(n1343), .Y(n1660) );
ADDHX2TS U479 ( .A(Op_MX[18]), .B(n489), .CO(n858), .S(n1123) );
ADDHX2TS U480 ( .A(n489), .B(Op_MX[0]), .CO(n528), .S(n753) );
OA21X2TS U481 ( .A0(n1253), .A1(n1342), .B0(FS_Module_state_reg[1]), .Y(
n1254) );
ADDHX2TS U482 ( .A(n498), .B(Op_MY[0]), .CO(n971), .S(n1095) );
ADDHX2TS U483 ( .A(n499), .B(Op_MX[0]), .CO(n975), .S(n1086) );
INVX3TS U484 ( .A(n413), .Y(n495) );
INVX3TS U485 ( .A(n399), .Y(n492) );
INVX3TS U486 ( .A(n397), .Y(n496) );
ADDHX2TS U487 ( .A(Op_MY[12]), .B(Op_MY[0]), .CO(n547), .S(n600) );
INVX3TS U488 ( .A(n394), .Y(n499) );
ADDHX2TS U489 ( .A(Op_MY[18]), .B(Op_MY[12]), .CO(n854), .S(n1136) );
INVX3TS U490 ( .A(n412), .Y(n493) );
INVX2TS U491 ( .A(n400), .Y(n491) );
INVX3TS U492 ( .A(n395), .Y(n498) );
NOR2XLTS U493 ( .A(n756), .B(n783), .Y(n787) );
NOR2XLTS U494 ( .A(n784), .B(n783), .Y(n785) );
NOR2XLTS U495 ( .A(n756), .B(n757), .Y(n663) );
NOR2XLTS U496 ( .A(n771), .B(n758), .Y(DP_OP_153J10_122_5442_n151) );
NOR2XLTS U497 ( .A(n790), .B(n783), .Y(DP_OP_153J10_122_5442_n187) );
NOR2XLTS U498 ( .A(n760), .B(n784), .Y(n645) );
NOR2XLTS U499 ( .A(n759), .B(n757), .Y(n647) );
NOR2XLTS U500 ( .A(n797), .B(n783), .Y(n666) );
NOR2XLTS U501 ( .A(n759), .B(n761), .Y(DP_OP_153J10_122_5442_n202) );
NOR2XLTS U502 ( .A(n754), .B(n797), .Y(DP_OP_153J10_122_5442_n158) );
NOR2XLTS U503 ( .A(n784), .B(n789), .Y(n652) );
NOR2XLTS U504 ( .A(n790), .B(n757), .Y(n651) );
NOR2XLTS U505 ( .A(n770), .B(n796), .Y(DP_OP_153J10_122_5442_n193) );
NOR2XLTS U506 ( .A(n771), .B(n797), .Y(DP_OP_153J10_122_5442_n150) );
NOR2XLTS U507 ( .A(n754), .B(n784), .Y(DP_OP_153J10_122_5442_n156) );
NOR2XLTS U508 ( .A(n765), .B(n680), .Y(n806) );
NOR2XLTS U509 ( .A(n743), .B(n764), .Y(n684) );
NOR2XLTS U510 ( .A(n743), .B(n762), .Y(n677) );
NOR2XLTS U511 ( .A(n726), .B(n747), .Y(n593) );
CLKAND2X2TS U512 ( .A(Op_MY[7]), .B(Op_MX[9]), .Y(n1075) );
CLKAND2X2TS U513 ( .A(n498), .B(Op_MX[10]), .Y(n1074) );
CLKAND2X2TS U514 ( .A(Op_MY[7]), .B(Op_MX[10]), .Y(n1085) );
CLKAND2X2TS U515 ( .A(Op_MX[11]), .B(n498), .Y(n1084) );
CLKAND2X2TS U516 ( .A(n495), .B(n496), .Y(n1055) );
CLKAND2X2TS U517 ( .A(n492), .B(Op_MX[9]), .Y(n1057) );
CLKAND2X2TS U518 ( .A(Op_MY[11]), .B(n499), .Y(n1056) );
CLKAND2X2TS U519 ( .A(Op_MX[11]), .B(Op_MY[7]), .Y(n1080) );
CLKAND2X2TS U520 ( .A(n492), .B(Op_MX[10]), .Y(n1081) );
CLKAND2X2TS U521 ( .A(Op_MY[11]), .B(Op_MX[7]), .Y(n1059) );
CLKAND2X2TS U522 ( .A(n391), .B(n496), .Y(n1058) );
CLKAND2X2TS U523 ( .A(n495), .B(Op_MX[9]), .Y(n1060) );
NOR2XLTS U524 ( .A(n758), .B(n796), .Y(n667) );
NOR2XLTS U525 ( .A(n797), .B(n761), .Y(n669) );
NOR2XLTS U526 ( .A(n758), .B(n761), .Y(n1439) );
CLKAND2X2TS U527 ( .A(n495), .B(Op_MX[10]), .Y(n1064) );
CLKAND2X2TS U528 ( .A(Op_MX[11]), .B(n492), .Y(n1066) );
CLKAND2X2TS U529 ( .A(Op_MY[11]), .B(n496), .Y(n1065) );
NOR2XLTS U530 ( .A(n763), .B(n762), .Y(n524) );
NOR2XLTS U531 ( .A(n763), .B(n680), .Y(n682) );
NOR2XLTS U532 ( .A(n765), .B(n762), .Y(n681) );
NOR2XLTS U533 ( .A(n772), .B(n764), .Y(n686) );
NOR2XLTS U534 ( .A(n679), .B(n769), .Y(n688) );
NOR2XLTS U535 ( .A(n404), .B(n486), .Y(n833) );
NOR2XLTS U536 ( .A(n419), .B(n403), .Y(n911) );
NOR2XLTS U537 ( .A(n484), .B(n421), .Y(n912) );
NOR2XLTS U538 ( .A(n812), .B(n764), .Y(DP_OP_153J10_122_5442_n311) );
NOR2XLTS U539 ( .A(n419), .B(n484), .Y(n832) );
NOR2XLTS U540 ( .A(n913), .B(n421), .Y(n830) );
NOR2XLTS U541 ( .A(n921), .B(n1124), .Y(DP_OP_154J10_123_2038_n100) );
CLKAND2X2TS U542 ( .A(Op_MX[22]), .B(Op_MY[18]), .Y(n941) );
CLKAND2X2TS U543 ( .A(Op_MY[19]), .B(Op_MX[21]), .Y(n942) );
CLKAND2X2TS U544 ( .A(Op_MY[20]), .B(Op_MX[21]), .Y(n926) );
CLKAND2X2TS U545 ( .A(Op_MX[22]), .B(Op_MY[19]), .Y(n928) );
CLKAND2X2TS U546 ( .A(Op_MY[22]), .B(Op_MX[19]), .Y(n927) );
CLKAND2X2TS U547 ( .A(Op_MY[22]), .B(Op_MX[20]), .Y(n929) );
CLKAND2X2TS U548 ( .A(Op_MY[21]), .B(Op_MX[21]), .Y(n931) );
CLKAND2X2TS U549 ( .A(Op_MX[22]), .B(Op_MY[20]), .Y(n930) );
CLKAND2X2TS U550 ( .A(Op_MX[22]), .B(Op_MY[21]), .Y(n841) );
CLKAND2X2TS U551 ( .A(Op_MX[5]), .B(n491), .Y(n1082) );
CLKAND2X2TS U552 ( .A(Op_MY[2]), .B(n392), .Y(n1083) );
CLKAND2X2TS U553 ( .A(Op_MY[4]), .B(Op_MX[2]), .Y(n1061) );
CLKAND2X2TS U554 ( .A(Op_MY[3]), .B(Op_MX[3]), .Y(n1063) );
CLKAND2X2TS U555 ( .A(Op_MY[5]), .B(n493), .Y(n1062) );
CLKAND2X2TS U556 ( .A(Op_MX[5]), .B(Op_MY[2]), .Y(n1045) );
CLKAND2X2TS U557 ( .A(Op_MY[5]), .B(Op_MX[2]), .Y(n1044) );
CLKAND2X2TS U558 ( .A(Op_MY[3]), .B(n392), .Y(n1043) );
CLKAND2X2TS U559 ( .A(Op_MY[7]), .B(Op_MX[7]), .Y(n511) );
CLKAND2X2TS U560 ( .A(n492), .B(n499), .Y(n512) );
CLKAND2X2TS U561 ( .A(n498), .B(Op_MX[9]), .Y(n1072) );
CLKAND2X2TS U562 ( .A(Op_MY[7]), .B(n496), .Y(n1073) );
CLKAND2X2TS U563 ( .A(n492), .B(Op_MX[7]), .Y(n510) );
CLKAND2X2TS U564 ( .A(n495), .B(n499), .Y(n509) );
CLKAND2X2TS U565 ( .A(n495), .B(Op_MX[7]), .Y(DP_OP_155J10_124_2038_n365) );
CLKAND2X2TS U566 ( .A(n492), .B(n496), .Y(DP_OP_155J10_124_2038_n360) );
CLKAND2X2TS U567 ( .A(n391), .B(n499), .Y(DP_OP_155J10_124_2038_n370) );
CLKAND2X2TS U568 ( .A(n391), .B(Op_MX[7]), .Y(DP_OP_155J10_124_2038_n364) );
CLKAND2X2TS U569 ( .A(n391), .B(Op_MX[9]), .Y(DP_OP_155J10_124_2038_n352) );
CLKAND2X2TS U570 ( .A(Op_MY[11]), .B(Op_MX[9]), .Y(
DP_OP_155J10_124_2038_n351) );
CLKAND2X2TS U571 ( .A(n391), .B(Op_MX[10]), .Y(DP_OP_155J10_124_2038_n346)
);
CLKAND2X2TS U572 ( .A(Op_MX[11]), .B(n495), .Y(DP_OP_155J10_124_2038_n341)
);
CLKAND2X2TS U573 ( .A(Op_MY[11]), .B(Op_MX[10]), .Y(n1020) );
CLKAND2X2TS U574 ( .A(Op_MX[11]), .B(n391), .Y(n1021) );
NOR2XLTS U575 ( .A(n405), .B(n421), .Y(n903) );
NOR2XLTS U576 ( .A(n403), .B(n422), .Y(n904) );
NOR2XLTS U577 ( .A(n913), .B(n486), .Y(n836) );
NOR2XLTS U578 ( .A(n419), .B(n405), .Y(n839) );
NOR2XLTS U579 ( .A(n403), .B(n421), .Y(n840) );
NOR2XLTS U580 ( .A(n679), .B(n680), .Y(n532) );
AOI2BB2XLTS U581 ( .B0(n876), .B1(Op_MX[17]), .A0N(Op_MX[17]), .A1N(n876),
.Y(n845) );
NOR2XLTS U582 ( .A(n419), .B(n404), .Y(n899) );
CLKAND2X2TS U583 ( .A(Op_MY[19]), .B(Op_MX[19]), .Y(n503) );
CLKAND2X2TS U584 ( .A(Op_MY[20]), .B(Op_MX[18]), .Y(n504) );
CLKAND2X2TS U585 ( .A(Op_MY[19]), .B(Op_MX[20]), .Y(n933) );
CLKAND2X2TS U586 ( .A(Op_MY[18]), .B(Op_MX[21]), .Y(n932) );
CLKAND2X2TS U587 ( .A(Op_MY[20]), .B(Op_MX[19]), .Y(n502) );
CLKAND2X2TS U588 ( .A(Op_MY[21]), .B(Op_MX[18]), .Y(n501) );
CLKAND2X2TS U589 ( .A(Op_MY[21]), .B(Op_MX[19]), .Y(
DP_OP_154J10_123_2038_n364) );
CLKAND2X2TS U590 ( .A(Op_MY[20]), .B(Op_MX[20]), .Y(
DP_OP_154J10_123_2038_n359) );
CLKAND2X2TS U591 ( .A(Op_MY[22]), .B(Op_MX[18]), .Y(
DP_OP_154J10_123_2038_n369) );
CLKAND2X2TS U592 ( .A(Op_MY[21]), .B(Op_MX[20]), .Y(
DP_OP_154J10_123_2038_n358) );
CLKAND2X2TS U593 ( .A(Op_MY[22]), .B(Op_MX[21]), .Y(
DP_OP_154J10_123_2038_n351) );
CLKAND2X2TS U594 ( .A(Op_MY[22]), .B(Op_MX[22]), .Y(
DP_OP_154J10_123_2038_n345) );
CLKAND2X2TS U595 ( .A(Op_MY[0]), .B(n392), .Y(n1076) );
CLKAND2X2TS U596 ( .A(n491), .B(Op_MX[3]), .Y(n1077) );
CLKAND2X2TS U597 ( .A(Op_MX[5]), .B(Op_MY[0]), .Y(n1078) );
CLKAND2X2TS U598 ( .A(n491), .B(n392), .Y(n1079) );
CLKAND2X2TS U599 ( .A(Op_MY[3]), .B(Op_MX[2]), .Y(n1069) );
CLKAND2X2TS U600 ( .A(Op_MY[2]), .B(Op_MX[3]), .Y(n1071) );
CLKAND2X2TS U601 ( .A(Op_MY[5]), .B(Op_MX[0]), .Y(n1070) );
CLKAND2X2TS U602 ( .A(Op_MY[4]), .B(Op_MX[3]), .Y(DP_OP_155J10_124_2038_n261) );
CLKAND2X2TS U603 ( .A(Op_MX[5]), .B(Op_MY[3]), .Y(DP_OP_155J10_124_2038_n250) );
CLKAND2X2TS U604 ( .A(Op_MY[5]), .B(Op_MX[3]), .Y(DP_OP_155J10_124_2038_n260) );
CLKAND2X2TS U605 ( .A(Op_MY[4]), .B(n392), .Y(DP_OP_155J10_124_2038_n255) );
CLKAND2X2TS U606 ( .A(Op_MX[5]), .B(Op_MY[4]), .Y(n1029) );
CLKAND2X2TS U607 ( .A(Op_MY[5]), .B(n392), .Y(n1028) );
CLKAND2X2TS U608 ( .A(n498), .B(Op_MX[7]), .Y(n1005) );
CLKAND2X2TS U609 ( .A(Op_MY[7]), .B(n499), .Y(n1004) );
CLKAND2X2TS U610 ( .A(n498), .B(n496), .Y(n1010) );
CLKAND2X2TS U611 ( .A(Op_MY[11]), .B(Op_MX[11]), .Y(n1025) );
NOR2XLTS U612 ( .A(n403), .B(n420), .Y(n821) );
NOR2XLTS U613 ( .A(n401), .B(n418), .Y(n822) );
NOR2XLTS U614 ( .A(n405), .B(n422), .Y(n924) );
NOR2XLTS U615 ( .A(n403), .B(n417), .Y(n925) );
NOR2XLTS U616 ( .A(n484), .B(n420), .Y(n820) );
NOR2XLTS U617 ( .A(n913), .B(n488), .Y(n819) );
NOR2XLTS U618 ( .A(n1124), .B(n867), .Y(n1160) );
NOR2XLTS U619 ( .A(n419), .B(n402), .Y(n909) );
CLKAND2X2TS U620 ( .A(Op_MY[18]), .B(Op_MX[19]), .Y(n886) );
CLKAND2X2TS U621 ( .A(Op_MY[19]), .B(Op_MX[18]), .Y(n885) );
CLKAND2X2TS U622 ( .A(Op_MY[18]), .B(Op_MX[20]), .Y(n888) );
CLKAND2X2TS U623 ( .A(Op_MY[2]), .B(Op_MX[0]), .Y(n952) );
CLKAND2X2TS U624 ( .A(n491), .B(n493), .Y(n951) );
CLKAND2X2TS U625 ( .A(Op_MY[0]), .B(Op_MX[3]), .Y(n1067) );
CLKAND2X2TS U626 ( .A(n491), .B(Op_MX[2]), .Y(n1068) );
CLKAND2X2TS U627 ( .A(Op_MY[3]), .B(Op_MX[0]), .Y(n949) );
CLKAND2X2TS U628 ( .A(Op_MY[2]), .B(n493), .Y(n950) );
CLKAND2X2TS U629 ( .A(Op_MY[2]), .B(Op_MX[2]), .Y(DP_OP_155J10_124_2038_n269) );
CLKAND2X2TS U630 ( .A(Op_MY[4]), .B(Op_MX[0]), .Y(DP_OP_155J10_124_2038_n279) );
CLKAND2X2TS U631 ( .A(Op_MY[3]), .B(n493), .Y(DP_OP_155J10_124_2038_n274) );
CLKAND2X2TS U632 ( .A(Op_MY[4]), .B(n493), .Y(DP_OP_155J10_124_2038_n273) );
CLKAND2X2TS U633 ( .A(Op_MY[5]), .B(Op_MX[5]), .Y(n1033) );
NOR2XLTS U634 ( .A(n405), .B(n486), .Y(n892) );
NAND3XLTS U635 ( .A(FS_Module_state_reg[1]), .B(FSM_add_overflow_flag), .C(
n1342), .Y(n1343) );
CLKAND2X2TS U636 ( .A(n491), .B(Op_MX[0]), .Y(n1088) );
CLKAND2X2TS U637 ( .A(Op_MY[0]), .B(n493), .Y(n1089) );
CLKAND2X2TS U638 ( .A(Op_MY[0]), .B(Op_MX[2]), .Y(n1007) );
AO22XLTS U639 ( .A0(Data_MY[27]), .A1(n1341), .B0(n1359), .B1(Op_MY[27]),
.Y(n339) );
AO22XLTS U640 ( .A0(Data_MX[24]), .A1(n1361), .B0(n1359), .B1(Op_MX[24]),
.Y(n368) );
AO22XLTS U641 ( .A0(Data_MX[28]), .A1(n1361), .B0(n1359), .B1(Op_MX[28]),
.Y(n372) );
AO22XLTS U642 ( .A0(n1341), .A1(Data_MY[16]), .B0(n1358), .B1(Op_MY[16]),
.Y(n328) );
AO22XLTS U643 ( .A0(n1361), .A1(Data_MX[16]), .B0(n1362), .B1(Op_MX[16]),
.Y(n360) );
AO22XLTS U644 ( .A0(n1361), .A1(Data_MX[15]), .B0(n1362), .B1(Op_MX[15]),
.Y(n359) );
AO22XLTS U645 ( .A0(n1341), .A1(Data_MY[13]), .B0(n1360), .B1(Op_MY[13]),
.Y(n325) );
AO22XLTS U646 ( .A0(n1361), .A1(Data_MX[13]), .B0(n1362), .B1(Op_MX[13]),
.Y(n357) );
AO22XLTS U647 ( .A0(n1363), .A1(Data_MY[7]), .B0(n1360), .B1(Op_MY[7]), .Y(
n319) );
AO22XLTS U648 ( .A0(n1361), .A1(Data_MX[5]), .B0(n1358), .B1(Op_MX[5]), .Y(
n349) );
AO22XLTS U649 ( .A0(n1363), .A1(Data_MX[3]), .B0(n1358), .B1(Op_MX[3]), .Y(
n347) );
AO22XLTS U650 ( .A0(n1363), .A1(Data_MX[7]), .B0(n1358), .B1(Op_MX[7]), .Y(
n351) );
AO22XLTS U651 ( .A0(n1363), .A1(Data_MY[19]), .B0(n1359), .B1(Op_MY[19]),
.Y(n331) );
AO22XLTS U652 ( .A0(n1361), .A1(Data_MX[10]), .B0(n1358), .B1(Op_MX[10]),
.Y(n354) );
AO22XLTS U653 ( .A0(n1361), .A1(Data_MX[18]), .B0(n1362), .B1(Op_MX[18]),
.Y(n362) );
AO22XLTS U654 ( .A0(n1363), .A1(Data_MY[20]), .B0(n1359), .B1(Op_MY[20]),
.Y(n332) );
AO22XLTS U655 ( .A0(n1363), .A1(Data_MY[0]), .B0(n1362), .B1(Op_MY[0]), .Y(
n312) );
AO22XLTS U656 ( .A0(n1363), .A1(Data_MX[22]), .B0(n1362), .B1(Op_MX[22]),
.Y(n366) );
AO22XLTS U657 ( .A0(n1361), .A1(Data_MX[19]), .B0(n1362), .B1(Op_MX[19]),
.Y(n363) );
AO22XLTS U658 ( .A0(n1361), .A1(Data_MX[20]), .B0(n1362), .B1(Op_MX[20]),
.Y(n364) );
AO22XLTS U659 ( .A0(n1361), .A1(Data_MX[21]), .B0(n1362), .B1(Op_MX[21]),
.Y(n365) );
AO22XLTS U660 ( .A0(n1363), .A1(Data_MY[18]), .B0(n1359), .B1(Op_MY[18]),
.Y(n330) );
AO22XLTS U661 ( .A0(Data_MX[25]), .A1(n1341), .B0(n1359), .B1(Op_MX[25]),
.Y(n369) );
AO22XLTS U662 ( .A0(Data_MX[27]), .A1(n1341), .B0(n1359), .B1(Op_MX[27]),
.Y(n371) );
AO22XLTS U663 ( .A0(Data_MX[26]), .A1(n1341), .B0(n1359), .B1(Op_MX[26]),
.Y(n370) );
AO22XLTS U664 ( .A0(Data_MX[23]), .A1(n1341), .B0(n1359), .B1(Op_MX[23]),
.Y(n367) );
AO22XLTS U665 ( .A0(n1363), .A1(Data_MY[4]), .B0(n1360), .B1(Op_MY[4]), .Y(
n316) );
AO22XLTS U666 ( .A0(n1361), .A1(Data_MY[5]), .B0(n1360), .B1(Op_MY[5]), .Y(
n317) );
AO22XLTS U667 ( .A0(n1363), .A1(Data_MY[2]), .B0(n1362), .B1(Op_MY[2]), .Y(
n314) );
AO22XLTS U668 ( .A0(n1361), .A1(Data_MY[3]), .B0(n1360), .B1(Op_MY[3]), .Y(
n315) );
AO22XLTS U669 ( .A0(n1361), .A1(Data_MY[11]), .B0(n1360), .B1(Op_MY[11]),
.Y(n323) );
AO22XLTS U670 ( .A0(n1341), .A1(Data_MY[17]), .B0(n1360), .B1(Op_MY[17]),
.Y(n329) );
AO22XLTS U671 ( .A0(n1361), .A1(Data_MY[12]), .B0(n1360), .B1(Op_MY[12]),
.Y(n324) );
AO22XLTS U672 ( .A0(n1361), .A1(Data_MX[17]), .B0(n1362), .B1(Op_MX[17]),
.Y(n361) );
AO22XLTS U673 ( .A0(n1361), .A1(Data_MX[9]), .B0(n1358), .B1(Op_MX[9]), .Y(
n353) );
AO22XLTS U674 ( .A0(n1363), .A1(Data_MX[2]), .B0(n1358), .B1(Op_MX[2]), .Y(
n346) );
AO22XLTS U675 ( .A0(n1363), .A1(Data_MY[22]), .B0(n1358), .B1(Op_MY[22]),
.Y(n334) );
AO22XLTS U676 ( .A0(n1363), .A1(Data_MX[0]), .B0(n1359), .B1(Op_MX[0]), .Y(
n344) );
AO22XLTS U677 ( .A0(n1363), .A1(Data_MY[21]), .B0(n1360), .B1(Op_MY[21]),
.Y(n333) );
AO22XLTS U678 ( .A0(n1361), .A1(Data_MX[11]), .B0(n1358), .B1(Op_MX[11]),
.Y(n355) );
AO22XLTS U679 ( .A0(n1661), .A1(P_Sgf[1]), .B0(n1654), .B1(n1652), .Y(n239)
);
AO22XLTS U680 ( .A0(n1629), .A1(P_Sgf[24]), .B0(n1643), .B1(n1591), .Y(n262)
);
AO22XLTS U681 ( .A0(n1629), .A1(P_Sgf[25]), .B0(n1643), .B1(n1587), .Y(n263)
);
AO22XLTS U682 ( .A0(n1629), .A1(P_Sgf[26]), .B0(n1643), .B1(n1583), .Y(n264)
);
AO22XLTS U683 ( .A0(n1629), .A1(P_Sgf[27]), .B0(n1643), .B1(n1579), .Y(n265)
);
AO22XLTS U684 ( .A0(n1629), .A1(P_Sgf[28]), .B0(n1643), .B1(n1575), .Y(n266)
);
AO22XLTS U685 ( .A0(n1629), .A1(P_Sgf[29]), .B0(n1643), .B1(n1571), .Y(n267)
);
AO22XLTS U686 ( .A0(n1629), .A1(P_Sgf[30]), .B0(n1643), .B1(n1567), .Y(n268)
);
AO22XLTS U687 ( .A0(n1629), .A1(P_Sgf[31]), .B0(n1612), .B1(n1563), .Y(n269)
);
AO22XLTS U688 ( .A0(n1629), .A1(P_Sgf[32]), .B0(n1612), .B1(n1559), .Y(n270)
);
AO22XLTS U689 ( .A0(n1661), .A1(P_Sgf[33]), .B0(n1612), .B1(n1555), .Y(n271)
);
AO22XLTS U690 ( .A0(n1629), .A1(P_Sgf[34]), .B0(n1612), .B1(n1551), .Y(n272)
);
AO22XLTS U691 ( .A0(n1661), .A1(P_Sgf[35]), .B0(n1612), .B1(n1547), .Y(n273)
);
AO22XLTS U692 ( .A0(n1629), .A1(P_Sgf[36]), .B0(n1612), .B1(n1543), .Y(n274)
);
AO22XLTS U693 ( .A0(n1341), .A1(Data_MY[1]), .B0(n1362), .B1(n491), .Y(n313)
);
AO22XLTS U694 ( .A0(n1361), .A1(Data_MY[6]), .B0(n1360), .B1(n498), .Y(n318)
);
AO22XLTS U695 ( .A0(n1361), .A1(Data_MY[8]), .B0(n1360), .B1(n492), .Y(n320)
);
AO22XLTS U696 ( .A0(n1341), .A1(Data_MY[9]), .B0(n1360), .B1(n495), .Y(n321)
);
AO22XLTS U697 ( .A0(n1361), .A1(Data_MY[10]), .B0(n1360), .B1(n391), .Y(n322) );
AO22XLTS U698 ( .A0(n1361), .A1(Data_MY[14]), .B0(n1359), .B1(n485), .Y(n326) );
AO22XLTS U699 ( .A0(n1341), .A1(Data_MY[15]), .B0(n1360), .B1(n483), .Y(n327) );
OAI211XLTS U700 ( .A0(Sgf_normalized_result[3]), .A1(n1393), .B0(n1438),
.C0(n1395), .Y(n1394) );
AO22XLTS U701 ( .A0(n1438), .A1(n1396), .B0(n1433), .B1(n463), .Y(n305) );
OAI211XLTS U702 ( .A0(Sgf_normalized_result[5]), .A1(n1397), .B0(n1428),
.C0(n1399), .Y(n1398) );
AO22XLTS U703 ( .A0(n1438), .A1(n1400), .B0(n1433), .B1(n474), .Y(n303) );
AO22XLTS U704 ( .A0(n1438), .A1(n1404), .B0(n1433), .B1(n475), .Y(n301) );
AO22XLTS U705 ( .A0(n1438), .A1(n1407), .B0(n1433), .B1(n476), .Y(n299) );
AO22XLTS U706 ( .A0(n1438), .A1(n1411), .B0(n1433), .B1(n477), .Y(n297) );
AO22XLTS U707 ( .A0(n1438), .A1(n1415), .B0(n1433), .B1(n478), .Y(n295) );
AO22XLTS U708 ( .A0(n1438), .A1(n1419), .B0(n1433), .B1(n479), .Y(n293) );
AO22XLTS U709 ( .A0(n1438), .A1(n1423), .B0(n1433), .B1(n480), .Y(n291) );
AO22XLTS U710 ( .A0(n1438), .A1(n1427), .B0(n1433), .B1(n481), .Y(n289) );
AO22XLTS U711 ( .A0(n1341), .A1(Data_MX[1]), .B0(n1358), .B1(n493), .Y(n345)
);
AO22XLTS U712 ( .A0(n1341), .A1(Data_MX[4]), .B0(n1358), .B1(n392), .Y(n348)
);
AO22XLTS U713 ( .A0(n1341), .A1(Data_MX[6]), .B0(n1358), .B1(n499), .Y(n350)
);
AO22XLTS U714 ( .A0(n1361), .A1(Data_MX[8]), .B0(n1358), .B1(n496), .Y(n352)
);
AO22XLTS U715 ( .A0(n1361), .A1(Data_MX[12]), .B0(n1362), .B1(n489), .Y(n356) );
AO22XLTS U716 ( .A0(n1361), .A1(Data_MX[14]), .B0(n1362), .B1(n487), .Y(n358) );
AO22XLTS U717 ( .A0(Data_MX[29]), .A1(n1341), .B0(n1359), .B1(n457), .Y(n373) );
AO22XLTS U718 ( .A0(Data_MX[30]), .A1(n1341), .B0(n1359), .B1(n456), .Y(n374) );
OR2X1TS U719 ( .A(Op_MX[27]), .B(Op_MX[26]), .Y(n410) );
OR2X1TS U720 ( .A(Op_MY[2]), .B(Op_MY[3]), .Y(n411) );
OR2X1TS U721 ( .A(n1669), .B(n1403), .Y(n424) );
OR2X1TS U722 ( .A(Op_MX[23]), .B(Op_MX[25]), .Y(n427) );
OR2X1TS U723 ( .A(Op_MY[4]), .B(Op_MY[5]), .Y(n429) );
CLKINVX6TS U724 ( .A(rst), .Y(n167) );
ADDHX1TS U725 ( .A(n779), .B(n778), .CO(n648), .S(DP_OP_153J10_122_5442_n97)
);
ADDHX1TS U726 ( .A(Op_MY[19]), .B(Op_MX[19]), .CO(DP_OP_154J10_123_2038_n319), .S(DP_OP_154J10_123_2038_n320) );
ADDHX1TS U727 ( .A(n1052), .B(n1051), .CO(DP_OP_155J10_124_2038_n61), .S(
DP_OP_155J10_124_2038_n62) );
NOR2X1TS U728 ( .A(n743), .B(n769), .Y(DP_OP_153J10_122_5442_n292) );
NOR2X2TS U729 ( .A(n1680), .B(n1431), .Y(n1434) );
NOR2X2TS U730 ( .A(n1668), .B(n1399), .Y(n1401) );
INVX2TS U731 ( .A(n424), .Y(n452) );
NOR2X2TS U732 ( .A(n1670), .B(n1406), .Y(n1408) );
NOR2X2TS U733 ( .A(n1671), .B(n1410), .Y(n1412) );
NOR2X2TS U734 ( .A(n1672), .B(n1414), .Y(n1416) );
NOR2X2TS U735 ( .A(n1673), .B(n1418), .Y(n1420) );
NOR2X2TS U736 ( .A(n1676), .B(n1422), .Y(n1424) );
NOR2X2TS U737 ( .A(n1677), .B(n1426), .Y(n1429) );
NOR4X1TS U738 ( .A(n499), .B(Op_MX[7]), .C(n496), .D(Op_MX[9]), .Y(n1376) );
NOR4X1TS U739 ( .A(n498), .B(Op_MY[7]), .C(n492), .D(n495), .Y(n1368) );
NOR4X1TS U740 ( .A(Op_MX[2]), .B(Op_MX[3]), .C(n392), .D(Op_MX[5]), .Y(n1379) );
NOR4X1TS U741 ( .A(Op_MY[18]), .B(Op_MY[19]), .C(Op_MY[20]), .D(Op_MY[21]),
.Y(n1367) );
OAI22X2TS U742 ( .A0(beg_FSM), .A1(n1709), .B0(ack_FSM), .B1(n1322), .Y(
n1353) );
OAI2BB2X4TS U743 ( .B0(n402), .B1(n847), .A0N(n847), .A1N(n402), .Y(n919) );
BUFX4TS U744 ( .A(n1722), .Y(n1716) );
BUFX4TS U745 ( .A(n1722), .Y(n1718) );
BUFX4TS U746 ( .A(n1722), .Y(n1709) );
INVX6TS U747 ( .A(n1352), .Y(n1361) );
ADDHX1TS U748 ( .A(n1089), .B(n1088), .CO(n1008), .S(n1652) );
ADDHX1TS U749 ( .A(n1172), .B(n1171), .CO(n1173), .S(n1656) );
ADDHX1TS U750 ( .A(n611), .B(n610), .CO(n612), .S(n703) );
INVX2TS U751 ( .A(n426), .Y(n453) );
INVX2TS U752 ( .A(n408), .Y(n454) );
NOR4X1TS U753 ( .A(Op_MY[22]), .B(n453), .C(n454), .D(Op_MY[27]), .Y(n1364)
);
NOR3XLTS U754 ( .A(Op_MX[24]), .B(Op_MX[0]), .C(n493), .Y(n1378) );
INVX2TS U755 ( .A(n396), .Y(n455) );
INVX2TS U756 ( .A(n428), .Y(n456) );
INVX2TS U757 ( .A(n409), .Y(n457) );
NOR4X1TS U758 ( .A(Op_MX[22]), .B(n456), .C(n457), .D(Op_MX[28]), .Y(n1372)
);
INVX2TS U759 ( .A(n407), .Y(n458) );
NOR3XLTS U760 ( .A(Op_MY[23]), .B(Op_MY[0]), .C(n491), .Y(n1370) );
INVX2TS U761 ( .A(n398), .Y(n459) );
INVX2TS U762 ( .A(n425), .Y(n460) );
INVX2TS U763 ( .A(n450), .Y(n461) );
INVX2TS U764 ( .A(n451), .Y(n462) );
INVX2TS U765 ( .A(n449), .Y(n463) );
INVX2TS U766 ( .A(n441), .Y(n464) );
INVX2TS U767 ( .A(n442), .Y(n465) );
INVX2TS U768 ( .A(n443), .Y(n466) );
INVX2TS U769 ( .A(n444), .Y(n467) );
INVX2TS U770 ( .A(n445), .Y(n468) );
INVX2TS U771 ( .A(n446), .Y(n469) );
INVX2TS U772 ( .A(n447), .Y(n470) );
INVX2TS U773 ( .A(n448), .Y(n471) );
INVX2TS U774 ( .A(n440), .Y(n472) );
INVX2TS U775 ( .A(n439), .Y(n473) );
INVX2TS U776 ( .A(n431), .Y(n474) );
INVX2TS U777 ( .A(n432), .Y(n475) );
INVX2TS U778 ( .A(n433), .Y(n476) );
INVX2TS U779 ( .A(n434), .Y(n477) );
INVX2TS U780 ( .A(n435), .Y(n478) );
INVX2TS U781 ( .A(n436), .Y(n479) );
INVX2TS U782 ( .A(n437), .Y(n480) );
INVX2TS U783 ( .A(n438), .Y(n481) );
CLKBUFX3TS U784 ( .A(n1246), .Y(n1436) );
NOR2XLTS U785 ( .A(n773), .B(n679), .Y(n685) );
NOR2X4TS U786 ( .A(Op_MX[11]), .B(n515), .Y(n773) );
BUFX6TS U787 ( .A(n1255), .Y(n1302) );
CLKINVX3TS U788 ( .A(n1436), .Y(n1428) );
INVX3TS U789 ( .A(n1436), .Y(n1438) );
ADDHX1TS U790 ( .A(n1005), .B(n1004), .CO(n1011), .S(n1196) );
INVX3TS U791 ( .A(n1254), .Y(n1387) );
INVX3TS U792 ( .A(n1254), .Y(n1303) );
CLKINVX6TS U793 ( .A(n1664), .Y(n1663) );
BUFX6TS U794 ( .A(n1256), .Y(n1308) );
INVX2TS U795 ( .A(n406), .Y(n482) );
ADDHX1TS U796 ( .A(n1126), .B(n1125), .CO(n893), .S(n1585) );
NOR4X1TS U797 ( .A(n485), .B(n483), .C(Op_MY[16]), .D(Op_MY[17]), .Y(n1366)
);
NOR4X1TS U798 ( .A(n487), .B(Op_MX[15]), .C(Op_MX[16]), .D(Op_MX[17]), .Y(
n1374) );
INVX2TS U799 ( .A(n416), .Y(n483) );
CMPR32X4TS U800 ( .A(Op_MX[15]), .B(Op_MX[21]), .C(n842), .CO(n844), .S(n914) );
ADDFX2TS U801 ( .A(n491), .B(Op_MY[13]), .CI(n547), .CO(n585), .S(n607) );
NOR4X1TS U802 ( .A(n391), .B(Op_MY[11]), .C(Op_MY[12]), .D(Op_MY[13]), .Y(
n1369) );
NOR4X1TS U803 ( .A(Op_MX[10]), .B(Op_MX[11]), .C(n489), .D(Op_MX[13]), .Y(
n1377) );
INVX2TS U804 ( .A(Op_MY[14]), .Y(n484) );
INVX2TS U805 ( .A(n484), .Y(n485) );
INVX2TS U806 ( .A(Op_MX[14]), .Y(n486) );
INVX2TS U807 ( .A(n486), .Y(n487) );
INVX2TS U808 ( .A(Op_MX[12]), .Y(n488) );
INVX2TS U809 ( .A(n488), .Y(n489) );
INVX2TS U810 ( .A(n423), .Y(n490) );
ADDFX2TS U811 ( .A(n491), .B(Op_MY[7]), .CI(n971), .CO(n969), .S(n1092) );
CMPR32X4TS U812 ( .A(Op_MX[5]), .B(Op_MX[11]), .C(n993), .CO(n994), .S(n1037) );
CMPR32X4TS U813 ( .A(Op_MX[3]), .B(Op_MX[9]), .C(n960), .CO(n962), .S(n1035)
);
ADDFX2TS U814 ( .A(n493), .B(Op_MX[7]), .CI(n975), .CO(n976), .S(n1091) );
ADDFX2TS U815 ( .A(Op_MX[13]), .B(Op_MX[19]), .CI(n858), .CO(n859), .S(n1128) );
NOR4X1TS U816 ( .A(P_Sgf[6]), .B(P_Sgf[7]), .C(P_Sgf[8]), .D(P_Sgf[9]), .Y(
n1311) );
NOR2XLTS U817 ( .A(n410), .B(n427), .Y(n1373) );
NOR2XLTS U818 ( .A(n411), .B(n429), .Y(n1371) );
BUFX4TS U819 ( .A(n167), .Y(n1719) );
ADDHX1TS U820 ( .A(n750), .B(n619), .CO(n709), .S(n609) );
INVX6TS U821 ( .A(n1660), .Y(n1629) );
NOR2X4TS U822 ( .A(Op_MY[11]), .B(n514), .Y(n743) );
CLKAND2X4TS U823 ( .A(n1344), .B(n1249), .Y(DP_OP_36J10_126_4699_n33) );
INVX4TS U824 ( .A(n1352), .Y(n1341) );
BUFX6TS U825 ( .A(n1258), .Y(n1307) );
CLKINVX6TS U826 ( .A(n1244), .Y(n1722) );
NOR2X4TS U827 ( .A(Op_MY[17]), .B(n847), .Y(n1141) );
NOR3X2TS U828 ( .A(n1666), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[3]), .Y(n1344) );
NOR2XLTS U829 ( .A(n797), .B(n796), .Y(n801) );
NOR2XLTS U830 ( .A(n756), .B(n796), .Y(n665) );
NOR2XLTS U831 ( .A(n1087), .B(n1054), .Y(DP_OP_155J10_124_2038_n100) );
NOR2XLTS U832 ( .A(n765), .B(n764), .Y(n523) );
NOR2XLTS U833 ( .A(n913), .B(n422), .Y(n835) );
INVX2TS U834 ( .A(n1086), .Y(n984) );
NOR2XLTS U835 ( .A(n401), .B(n422), .Y(n838) );
NOR2XLTS U836 ( .A(n1124), .B(n937), .Y(DP_OP_154J10_123_2038_n118) );
NOR2XLTS U837 ( .A(n1087), .B(n1049), .Y(DP_OP_155J10_124_2038_n118) );
NOR2XLTS U838 ( .A(n1087), .B(n984), .Y(n1119) );
OAI211XLTS U839 ( .A0(Sgf_normalized_result[15]), .A1(n1416), .B0(n1428),
.C0(n1418), .Y(n1417) );
OAI211XLTS U840 ( .A0(n1248), .A1(n1674), .B0(n1436), .C0(n1386), .Y(n236)
);
OAI211XLTS U841 ( .A0(n1306), .A1(n1689), .B0(n1268), .C0(n1267), .Y(n203)
);
CMPR32X2TS U842 ( .A(Op_MY[22]), .B(Op_MX[22]), .C(
DP_OP_154J10_123_2038_n306), .CO(n881), .S(n506) );
CMPR32X2TS U843 ( .A(n502), .B(n501), .C(n500), .CO(n814), .S(n817) );
ADDHXLTS U844 ( .A(n504), .B(n503), .CO(n500), .S(n887) );
NOR2X1TS U845 ( .A(n881), .B(n880), .Y(DP_OP_154J10_123_2038_n192) );
INVX2TS U846 ( .A(DP_OP_154J10_123_2038_n192), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]) );
CMPR32X2TS U847 ( .A(DP_OP_154J10_123_2038_n307), .B(n506), .C(n505), .CO(
n880), .S(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]) );
CMPR32X2TS U848 ( .A(DP_OP_154J10_123_2038_n308), .B(
DP_OP_154J10_123_2038_n310), .C(n507), .CO(n505), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]) );
CMPR32X2TS U849 ( .A(n510), .B(n509), .C(n508), .CO(n944), .S(n947) );
ADDHXLTS U850 ( .A(n512), .B(n511), .CO(n508), .S(n1009) );
CMPR32X2TS U851 ( .A(DP_OP_155J10_124_2038_n308), .B(
DP_OP_155J10_124_2038_n310), .C(n513), .CO(n1022), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]) );
CLKXOR2X2TS U852 ( .A(Op_MY[11]), .B(n514), .Y(n812) );
CLKXOR2X2TS U853 ( .A(Op_MX[11]), .B(n515), .Y(n811) );
NOR2X1TS U854 ( .A(n743), .B(n811), .Y(n539) );
INVX2TS U855 ( .A(n546), .Y(n679) );
INVX2TS U856 ( .A(n661), .Y(n680) );
INVX2TS U857 ( .A(n604), .Y(n762) );
NOR2X1TS U858 ( .A(n679), .B(n762), .Y(n527) );
INVX2TS U859 ( .A(n606), .Y(n763) );
INVX2TS U860 ( .A(n551), .Y(n764) );
NOR2X1TS U861 ( .A(n763), .B(n764), .Y(n526) );
INVX2TS U862 ( .A(n657), .Y(n765) );
INVX2TS U863 ( .A(n637), .Y(n769) );
ADDHXLTS U864 ( .A(n524), .B(n523), .CO(n687), .S(n530) );
INVX2TS U865 ( .A(n643), .Y(n772) );
NOR2X1TS U866 ( .A(n811), .B(n679), .Y(n536) );
ADDHX1TS U867 ( .A(n527), .B(n526), .CO(n531), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
NOR2X1TS U868 ( .A(n679), .B(n764), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
INVX4TS U869 ( .A(n529), .Y(DP_OP_153J10_122_5442_n412) );
CMPR32X2TS U870 ( .A(n532), .B(n531), .C(n530), .CO(n535), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
CMPR32X2TS U871 ( .A(n535), .B(n534), .C(n533), .CO(n537), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
CMPR32X2TS U872 ( .A(n537), .B(n536), .C(DP_OP_153J10_122_5442_n271), .CO(
n538), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
CMPR32X2TS U873 ( .A(DP_OP_153J10_122_5442_n264), .B(
DP_OP_153J10_122_5442_n270), .C(n538), .CO(n672), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
CMPR32X2TS U874 ( .A(n540), .B(n539), .C(DP_OP_153J10_122_5442_n247), .CO(
n768), .S(n542) );
CMPR32X2TS U875 ( .A(DP_OP_153J10_122_5442_n248), .B(n542), .C(n541), .CO(
n766), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
INVX2TS U876 ( .A(n1466), .Y(n555) );
INVX2TS U877 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .Y(
n557) );
INVX2TS U878 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(
n1441) );
INVX2TS U879 ( .A(n600), .Y(n747) );
INVX2TS U880 ( .A(n753), .Y(n543) );
NOR2X1TS U881 ( .A(n747), .B(n543), .Y(n1510) );
INVX2TS U882 ( .A(n1510), .Y(n1440) );
INVX2TS U883 ( .A(n544), .Y(n758) );
INVX2TS U884 ( .A(n545), .Y(n761) );
ADDHXLTS U885 ( .A(n600), .B(n546), .CO(n608), .S(n544) );
INVX2TS U886 ( .A(n548), .Y(n797) );
AOI21X1TS U887 ( .A0(n600), .A1(n753), .B0(DP_OP_153J10_122_5442_n412), .Y(
n603) );
NAND2X1TS U888 ( .A(n529), .B(n543), .Y(n550) );
INVX2TS U889 ( .A(n607), .Y(n711) );
AOI22X1TS U890 ( .A0(n529), .A1(n711), .B0(n607), .B1(
DP_OP_153J10_122_5442_n412), .Y(n549) );
OAI22X1TS U891 ( .A0(n600), .A1(n550), .B0(n549), .B1(n543), .Y(n602) );
INVX2TS U892 ( .A(n1465), .Y(n668) );
ADDHXLTS U893 ( .A(n753), .B(n551), .CO(n605), .S(n545) );
INVX2TS U894 ( .A(n552), .Y(n796) );
INVX2TS U895 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .Y(
n567) );
INVX2TS U896 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .Y(
n565) );
INVX2TS U897 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .Y(
n563) );
INVX2TS U898 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .Y(
n561) );
CMPR32X2TS U899 ( .A(DP_OP_153J10_122_5442_n35), .B(
DP_OP_153J10_122_5442_n42), .C(n553), .CO(n737), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
CMPR32X2TS U900 ( .A(DP_OP_153J10_122_5442_n43), .B(n555), .C(n554), .CO(
n553), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
CMPR32X2TS U901 ( .A(DP_OP_153J10_122_5442_n52), .B(n557), .C(n556), .CO(
n554), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
CMPR32X2TS U902 ( .A(DP_OP_153J10_122_5442_n63), .B(
DP_OP_153J10_122_5442_n75), .C(n558), .CO(n556), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
CMPR32X2TS U903 ( .A(DP_OP_153J10_122_5442_n76), .B(
DP_OP_153J10_122_5442_n88), .C(n559), .CO(n558), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
CMPR32X2TS U904 ( .A(n560), .B(DP_OP_153J10_122_5442_n99), .C(
DP_OP_153J10_122_5442_n89), .CO(n559), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
CMPR32X2TS U905 ( .A(n562), .B(n561), .C(DP_OP_153J10_122_5442_n100), .CO(
n560), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
CMPR32X2TS U906 ( .A(n564), .B(n563), .C(DP_OP_153J10_122_5442_n110), .CO(
n562), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
CMPR32X2TS U907 ( .A(n566), .B(n565), .C(DP_OP_153J10_122_5442_n118), .CO(
n564), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
CMPR32X2TS U908 ( .A(n568), .B(n567), .C(DP_OP_153J10_122_5442_n125), .CO(
n566), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
CMPR32X2TS U909 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]),
.B(n570), .C(n569), .CO(n568), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]) );
INVX4TS U910 ( .A(n572), .Y(n718) );
INVX2TS U911 ( .A(n621), .Y(n691) );
AOI22X1TS U912 ( .A0(n574), .A1(n691), .B0(n621), .B1(n729), .Y(n576) );
BUFX3TS U913 ( .A(n576), .Y(n726) );
OAI221X4TS U914 ( .A0(n621), .A1(n572), .B0(n691), .B1(n718), .C0(n726), .Y(
n724) );
INVX2TS U915 ( .A(n750), .Y(n748) );
AOI22X1TS U916 ( .A0(n572), .A1(n748), .B0(n750), .B1(n718), .Y(n713) );
OAI22X1TS U917 ( .A0(n718), .A1(n726), .B0(n724), .B1(n713), .Y(n695) );
INVX2TS U918 ( .A(n695), .Y(n693) );
INVX2TS U919 ( .A(n752), .Y(n727) );
AOI2BB2X4TS U920 ( .B0(n611), .B1(n718), .A0N(n718), .A1N(n611), .Y(n746) );
INVX2TS U921 ( .A(n730), .Y(n731) );
NAND2X2TS U922 ( .A(n572), .B(n611), .Y(n712) );
OAI22X1TS U923 ( .A0(n727), .A1(n746), .B0(n731), .B1(n712), .Y(n692) );
AOI22X1TS U924 ( .A0(n572), .A1(n711), .B0(n607), .B1(n718), .Y(n723) );
AOI22X1TS U925 ( .A0(n572), .A1(n747), .B0(n600), .B1(n718), .Y(n581) );
OAI22X1TS U926 ( .A0(n726), .A1(n723), .B0(n724), .B1(n581), .Y(n590) );
CMPR32X2TS U927 ( .A(Op_MX[2]), .B(n487), .C(n582), .CO(n573), .S(n660) );
INVX2TS U928 ( .A(n660), .Y(n775) );
AOI22X1TS U929 ( .A0(n529), .A1(n775), .B0(n660), .B1(
DP_OP_153J10_122_5442_n412), .Y(n583) );
BUFX3TS U930 ( .A(n583), .Y(n736) );
CMPR32X2TS U931 ( .A(Op_MY[3]), .B(n483), .C(n584), .CO(n580), .S(n715) );
INVX2TS U932 ( .A(n715), .Y(n716) );
AOI22X1TS U933 ( .A0(n574), .A1(n716), .B0(n715), .B1(n729), .Y(n733) );
OAI221X4TS U934 ( .A0(n660), .A1(n574), .B0(n775), .B1(n729), .C0(n736), .Y(
n734) );
CMPR32X2TS U935 ( .A(Op_MY[2]), .B(n485), .C(n585), .CO(n584), .S(n719) );
INVX2TS U936 ( .A(n719), .Y(n720) );
AOI22X1TS U937 ( .A0(n574), .A1(n720), .B0(n719), .B1(n729), .Y(n587) );
OAI22X1TS U938 ( .A0(n736), .A1(n733), .B0(n734), .B1(n587), .Y(n589) );
AOI22X1TS U939 ( .A0(n529), .A1(n731), .B0(n730), .B1(
DP_OP_153J10_122_5442_n412), .Y(n586) );
OAI32X1TS U940 ( .A0(n753), .A1(n715), .A2(DP_OP_153J10_122_5442_n412), .B0(
n586), .B1(n543), .Y(n594) );
AOI22X1TS U941 ( .A0(n574), .A1(n711), .B0(n607), .B1(n729), .Y(n597) );
OAI22X1TS U942 ( .A0(n736), .A1(n587), .B0(n734), .B1(n597), .Y(n592) );
CMPR32X2TS U943 ( .A(n590), .B(n589), .C(n588), .CO(n641), .S(n782) );
AOI22X1TS U944 ( .A0(n529), .A1(n727), .B0(n752), .B1(
DP_OP_153J10_122_5442_n412), .Y(n591) );
OAI32X1TS U945 ( .A0(n753), .A1(n730), .A2(DP_OP_153J10_122_5442_n412), .B0(
n591), .B1(n543), .Y(n777) );
OAI32X1TS U946 ( .A0(n718), .A1(n600), .A2(n726), .B0(n724), .B1(n718), .Y(
n776) );
CMPR32X2TS U947 ( .A(n594), .B(n593), .C(n592), .CO(n588), .S(n655) );
AOI22X1TS U948 ( .A0(n529), .A1(n716), .B0(n715), .B1(
DP_OP_153J10_122_5442_n412), .Y(n595) );
OAI32X1TS U949 ( .A0(n753), .A1(n719), .A2(DP_OP_153J10_122_5442_n412), .B0(
n595), .B1(n543), .Y(n599) );
AOI22X1TS U950 ( .A0(n574), .A1(n747), .B0(n600), .B1(n729), .Y(n596) );
OAI22X1TS U951 ( .A0(n736), .A1(n597), .B0(n734), .B1(n596), .Y(n598) );
ADDHXLTS U952 ( .A(n599), .B(n598), .CO(n654), .S(n800) );
OAI32X1TS U953 ( .A0(n729), .A1(n600), .A2(n736), .B0(n734), .B1(n729), .Y(
n799) );
AOI22X1TS U954 ( .A0(n529), .A1(n720), .B0(n719), .B1(
DP_OP_153J10_122_5442_n412), .Y(n601) );
OAI32X1TS U955 ( .A0(n753), .A1(n607), .A2(DP_OP_153J10_122_5442_n412), .B0(
n601), .B1(n543), .Y(n795) );
ADDHX1TS U956 ( .A(n603), .B(n602), .CO(n793), .S(n1465) );
INVX2TS U957 ( .A(n773), .Y(n632) );
CMPR32X2TS U958 ( .A(n605), .B(n529), .C(n604), .CO(n659), .S(n552) );
INVX2TS U959 ( .A(n811), .Y(n620) );
INVX2TS U960 ( .A(n703), .Y(n754) );
INVX2TS U961 ( .A(n743), .Y(n614) );
CMPR32X2TS U962 ( .A(n608), .B(n607), .C(n606), .CO(n656), .S(n548) );
INVX2TS U963 ( .A(n812), .Y(n616) );
INVX2TS U964 ( .A(n609), .Y(n770) );
INVX2TS U965 ( .A(n612), .Y(n771) );
INVX2TS U966 ( .A(n615), .Y(n759) );
NOR2X1TS U967 ( .A(n771), .B(n759), .Y(n625) );
CMPR32X2TS U968 ( .A(n617), .B(n730), .C(n616), .CO(n613), .S(n618) );
INVX2TS U969 ( .A(n618), .Y(n790) );
INVX2TS U970 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]),
.Y(n628) );
INVX2TS U971 ( .A(n709), .Y(n755) );
CMPR32X2TS U972 ( .A(n622), .B(n621), .C(n620), .CO(n631), .S(n623) );
INVX2TS U973 ( .A(n623), .Y(n789) );
CMPR32X2TS U974 ( .A(n626), .B(n625), .C(n624), .CO(
DP_OP_153J10_122_5442_n29), .S(DP_OP_153J10_122_5442_n30) );
CMPR32X2TS U975 ( .A(n629), .B(n628), .C(n627), .CO(n624), .S(
DP_OP_153J10_122_5442_n40) );
CMPR32X2TS U976 ( .A(DP_OP_153J10_122_5442_n364), .B(
DP_OP_153J10_122_5442_n368), .C(n630), .CO(n689), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
INVX2TS U977 ( .A(n708), .Y(n760) );
INVX2TS U978 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .Y(
n634) );
CMPR32X2TS U979 ( .A(n635), .B(n634), .C(n633), .CO(
DP_OP_153J10_122_5442_n59), .S(DP_OP_153J10_122_5442_n60) );
CMPR32X2TS U980 ( .A(n637), .B(n574), .C(n636), .CO(n622), .S(n638) );
INVX2TS U981 ( .A(n638), .Y(n757) );
CMPR32X2TS U982 ( .A(DP_OP_153J10_122_5442_n374), .B(
DP_OP_153J10_122_5442_n376), .C(n639), .CO(n690), .S(n1449) );
INVX2TS U983 ( .A(n1449), .Y(n649) );
CMPR32X2TS U984 ( .A(DP_OP_153J10_122_5442_n377), .B(n641), .C(n640), .CO(
n639), .S(n1458) );
INVX2TS U985 ( .A(n1458), .Y(n779) );
CMPR32X2TS U986 ( .A(n643), .B(n715), .C(n642), .CO(n617), .S(n644) );
INVX2TS U987 ( .A(n644), .Y(n784) );
NOR2X1TS U988 ( .A(n784), .B(n757), .Y(n778) );
CMPR32X2TS U989 ( .A(n647), .B(n646), .C(n645), .CO(
DP_OP_153J10_122_5442_n70), .S(DP_OP_153J10_122_5442_n71) );
ADDHXLTS U990 ( .A(n649), .B(n648), .CO(n646), .S(n650) );
CMPR32X2TS U991 ( .A(n652), .B(n651), .C(n650), .CO(
DP_OP_153J10_122_5442_n83), .S(DP_OP_153J10_122_5442_n84) );
CMPR32X2TS U992 ( .A(n655), .B(n654), .C(n653), .CO(n780), .S(n1461) );
INVX2TS U993 ( .A(n1461), .Y(n788) );
CMPR32X2TS U994 ( .A(n657), .B(n719), .C(n656), .CO(n642), .S(n658) );
INVX2TS U995 ( .A(n658), .Y(n756) );
CMPR32X2TS U996 ( .A(n661), .B(n660), .C(n659), .CO(n636), .S(n662) );
INVX2TS U997 ( .A(n662), .Y(n783) );
CMPR32X2TS U998 ( .A(n664), .B(n663), .C(DP_OP_153J10_122_5442_n111), .CO(
DP_OP_153J10_122_5442_n104), .S(DP_OP_153J10_122_5442_n105) );
CMPR32X2TS U999 ( .A(n666), .B(n665), .C(DP_OP_153J10_122_5442_n123), .CO(
DP_OP_153J10_122_5442_n119), .S(DP_OP_153J10_122_5442_n120) );
CMPR32X2TS U1000 ( .A(n669), .B(n668), .C(n667), .CO(
DP_OP_153J10_122_5442_n128), .S(n569) );
CMPR32X2TS U1001 ( .A(DP_OP_153J10_122_5442_n249), .B(
DP_OP_153J10_122_5442_n251), .C(n670), .CO(n541), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
CMPR32X2TS U1002 ( .A(DP_OP_153J10_122_5442_n252), .B(
DP_OP_153J10_122_5442_n256), .C(n671), .CO(n670), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
CMPR32X2TS U1003 ( .A(DP_OP_153J10_122_5442_n257), .B(
DP_OP_153J10_122_5442_n263), .C(n672), .CO(n671), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
CMPR32X2TS U1004 ( .A(n675), .B(n674), .C(n673), .CO(
DP_OP_153J10_122_5442_n253), .S(DP_OP_153J10_122_5442_n254) );
NOR2X1TS U1005 ( .A(n812), .B(n680), .Y(n676) );
CMPR32X2TS U1006 ( .A(n678), .B(n677), .C(n676), .CO(
DP_OP_153J10_122_5442_n258), .S(DP_OP_153J10_122_5442_n259) );
ADDHXLTS U1007 ( .A(n682), .B(n681), .CO(n805), .S(n534) );
CMPR32X2TS U1008 ( .A(n685), .B(n684), .C(n683), .CO(
DP_OP_153J10_122_5442_n265), .S(DP_OP_153J10_122_5442_n266) );
CMPR32X2TS U1009 ( .A(n688), .B(n687), .C(n686), .CO(
DP_OP_153J10_122_5442_n274), .S(n533) );
CMPR32X2TS U1010 ( .A(DP_OP_153J10_122_5442_n361), .B(
DP_OP_153J10_122_5442_n363), .C(n689), .CO(n697), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]) );
CMPR32X2TS U1011 ( .A(DP_OP_153J10_122_5442_n369), .B(
DP_OP_153J10_122_5442_n373), .C(n690), .CO(n630), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
OAI22X1TS U1012 ( .A0(n748), .A1(n746), .B0(n727), .B1(n712), .Y(n696) );
OAI21X1TS U1013 ( .A0(n729), .A1(n691), .B0(n572), .Y(n694) );
CMPR32X2TS U1014 ( .A(n693), .B(n692), .C(DP_OP_153J10_122_5442_n359), .CO(
n707), .S(n698) );
CMPR32X2TS U1015 ( .A(n696), .B(n695), .C(n694), .CO(n702), .S(n706) );
CMPR32X2TS U1016 ( .A(DP_OP_153J10_122_5442_n360), .B(n698), .C(n697), .CO(
n705), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]) );
OAI31X1TS U1017 ( .A0(n748), .A1(n700), .A2(n712), .B0(n699), .Y(n701) );
XNOR2X2TS U1018 ( .A(n702), .B(n701), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]) );
NAND2X1TS U1019 ( .A(n709), .B(n703), .Y(n704) );
XNOR2X1TS U1020 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]),
.B(n704), .Y(DP_OP_153J10_122_5442_n25) );
CMPR32X2TS U1021 ( .A(n707), .B(n706), .C(n705), .CO(n700), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]) );
NAND2X1TS U1022 ( .A(n709), .B(n708), .Y(n710) );
XNOR2X1TS U1023 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]),
.B(n710), .Y(DP_OP_153J10_122_5442_n32) );
OAI22X1TS U1024 ( .A0(n716), .A1(n746), .B0(n720), .B1(n712), .Y(
DP_OP_153J10_122_5442_n365) );
OAI22X1TS U1025 ( .A0(n720), .A1(n746), .B0(n711), .B1(n712), .Y(
DP_OP_153J10_122_5442_n370) );
OAI22X1TS U1026 ( .A0(n731), .A1(n746), .B0(n716), .B1(n712), .Y(
DP_OP_153J10_122_5442_n392) );
OAI22X1TS U1027 ( .A0(n747), .A1(n712), .B0(n711), .B1(n746), .Y(
DP_OP_153J10_122_5442_n393) );
AOI22X1TS U1028 ( .A0(n572), .A1(n727), .B0(n752), .B1(n718), .Y(n714) );
OAI22X1TS U1029 ( .A0(n726), .A1(n713), .B0(n724), .B1(n714), .Y(
DP_OP_153J10_122_5442_n396) );
AOI22X1TS U1030 ( .A0(n572), .A1(n731), .B0(n730), .B1(n718), .Y(n717) );
OAI22X1TS U1031 ( .A0(n726), .A1(n714), .B0(n724), .B1(n717), .Y(
DP_OP_153J10_122_5442_n397) );
AOI22X1TS U1032 ( .A0(n572), .A1(n716), .B0(n715), .B1(n718), .Y(n722) );
OAI22X1TS U1033 ( .A0(n726), .A1(n717), .B0(n724), .B1(n722), .Y(
DP_OP_153J10_122_5442_n398) );
AOI22X1TS U1034 ( .A0(n572), .A1(n720), .B0(n719), .B1(n718), .Y(n725) );
OAI22X1TS U1035 ( .A0(n726), .A1(n722), .B0(n724), .B1(n725), .Y(
DP_OP_153J10_122_5442_n399) );
OAI22X1TS U1036 ( .A0(n726), .A1(n725), .B0(n724), .B1(n723), .Y(
DP_OP_153J10_122_5442_n400) );
AOI22X1TS U1037 ( .A0(n574), .A1(n748), .B0(n750), .B1(n729), .Y(n728) );
OAI22X1TS U1038 ( .A0(n729), .A1(n736), .B0(n734), .B1(n728), .Y(
DP_OP_153J10_122_5442_n404) );
AOI22X1TS U1039 ( .A0(n574), .A1(n727), .B0(n752), .B1(n729), .Y(n732) );
OAI22X1TS U1040 ( .A0(n736), .A1(n728), .B0(n734), .B1(n732), .Y(
DP_OP_153J10_122_5442_n405) );
AOI22X1TS U1041 ( .A0(n574), .A1(n731), .B0(n730), .B1(n729), .Y(n735) );
OAI22X1TS U1042 ( .A0(n736), .A1(n732), .B0(n734), .B1(n735), .Y(
DP_OP_153J10_122_5442_n406) );
OAI22X1TS U1043 ( .A0(n736), .A1(n735), .B0(n734), .B1(n733), .Y(
DP_OP_153J10_122_5442_n407) );
AOI21X1TS U1044 ( .A0(n750), .A1(n543), .B0(DP_OP_153J10_122_5442_n412), .Y(
DP_OP_153J10_122_5442_n413) );
CMPR32X2TS U1045 ( .A(DP_OP_153J10_122_5442_n34), .B(
DP_OP_153J10_122_5442_n28), .C(n737), .CO(n740), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
OAI21X1TS U1046 ( .A0(n755), .A1(n754), .B0(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(n739) );
NOR2X1TS U1047 ( .A(n755), .B(n771), .Y(n738) );
CMPR32X2TS U1048 ( .A(n739), .B(n738), .C(DP_OP_153J10_122_5442_n21), .CO(
n745), .S(n742) );
CMPR32X2TS U1049 ( .A(DP_OP_153J10_122_5442_n27), .B(
DP_OP_153J10_122_5442_n23), .C(n740), .CO(n741), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
XNOR2X1TS U1050 ( .A(n745), .B(n744), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]) );
CMPR32X2TS U1051 ( .A(n742), .B(DP_OP_153J10_122_5442_n22), .C(n741), .CO(
n744), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
NOR2X1TS U1052 ( .A(n745), .B(n744), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]) );
INVX2TS U1053 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]),
.Y(DP_OP_153J10_122_5442_n133) );
NOR2X1TS U1054 ( .A(n754), .B(n758), .Y(DP_OP_153J10_122_5442_n159) );
NOR2X1TS U1055 ( .A(n754), .B(n756), .Y(DP_OP_153J10_122_5442_n157) );
NOR2X1TS U1056 ( .A(n755), .B(n761), .Y(DP_OP_153J10_122_5442_n200) );
NOR2X1TS U1057 ( .A(n760), .B(n797), .Y(DP_OP_153J10_122_5442_n166) );
OAI21X1TS U1058 ( .A0(n755), .A1(n760), .B0(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
DP_OP_153J10_122_5442_n31) );
NOR2X1TS U1059 ( .A(n790), .B(n796), .Y(DP_OP_153J10_122_5442_n195) );
NOR2X1TS U1060 ( .A(n770), .B(n761), .Y(DP_OP_153J10_122_5442_n201) );
NOR2X1TS U1061 ( .A(n759), .B(n796), .Y(DP_OP_153J10_122_5442_n194) );
NOR2X1TS U1062 ( .A(n760), .B(n758), .Y(DP_OP_153J10_122_5442_n167) );
NOR2X1TS U1063 ( .A(n797), .B(n789), .Y(DP_OP_153J10_122_5442_n174) );
NOR2X1TS U1064 ( .A(n756), .B(n789), .Y(DP_OP_153J10_122_5442_n173) );
NOR2X1TS U1065 ( .A(n770), .B(n783), .Y(DP_OP_153J10_122_5442_n185) );
NOR2X1TS U1066 ( .A(n760), .B(n756), .Y(DP_OP_153J10_122_5442_n165) );
NOR2X1TS U1067 ( .A(n747), .B(n746), .Y(DP_OP_153J10_122_5442_n394) );
NOR2X1TS U1068 ( .A(n790), .B(n761), .Y(DP_OP_153J10_122_5442_n203) );
NOR2X1TS U1069 ( .A(n758), .B(n789), .Y(DP_OP_153J10_122_5442_n175) );
NOR2X1TS U1070 ( .A(n755), .B(n796), .Y(DP_OP_153J10_122_5442_n192) );
NOR2X1TS U1071 ( .A(n759), .B(n783), .Y(DP_OP_153J10_122_5442_n186) );
NOR2X1TS U1072 ( .A(n770), .B(n757), .Y(DP_OP_153J10_122_5442_n177) );
NOR2X1TS U1073 ( .A(n755), .B(n783), .Y(DP_OP_153J10_122_5442_n184) );
INVX2TS U1074 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(
DP_OP_153J10_122_5442_n234) );
NOR2X1TS U1075 ( .A(n754), .B(n759), .Y(DP_OP_153J10_122_5442_n154) );
INVX2TS U1076 ( .A(DP_OP_153J10_122_5442_n370), .Y(
DP_OP_153J10_122_5442_n371) );
NOR2X1TS U1077 ( .A(n771), .B(n756), .Y(DP_OP_153J10_122_5442_n149) );
AOI22X1TS U1078 ( .A0(n750), .A1(DP_OP_153J10_122_5442_n412), .B0(n529),
.B1(n748), .Y(n751) );
OAI32X1TS U1079 ( .A0(n753), .A1(n752), .A2(DP_OP_153J10_122_5442_n412),
.B0(n751), .B1(n543), .Y(DP_OP_153J10_122_5442_n414) );
NOR2X1TS U1080 ( .A(n770), .B(n789), .Y(DP_OP_153J10_122_5442_n169) );
NOR2X1TS U1081 ( .A(n797), .B(n757), .Y(DP_OP_153J10_122_5442_n182) );
NOR2X1TS U1082 ( .A(n784), .B(n796), .Y(DP_OP_153J10_122_5442_n196) );
NOR2X1TS U1083 ( .A(n756), .B(n761), .Y(DP_OP_153J10_122_5442_n205) );
NOR2X1TS U1084 ( .A(n758), .B(n783), .Y(DP_OP_153J10_122_5442_n191) );
INVX2TS U1085 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .Y(
DP_OP_153J10_122_5442_n229) );
NOR2X1TS U1086 ( .A(n760), .B(n770), .Y(DP_OP_153J10_122_5442_n161) );
INVX2TS U1087 ( .A(DP_OP_153J10_122_5442_n365), .Y(
DP_OP_153J10_122_5442_n366) );
NOR2X1TS U1088 ( .A(n758), .B(n757), .Y(DP_OP_153J10_122_5442_n183) );
NOR2X1TS U1089 ( .A(n760), .B(n759), .Y(DP_OP_153J10_122_5442_n162) );
NOR2X1TS U1090 ( .A(n784), .B(n761), .Y(DP_OP_153J10_122_5442_n204) );
NOR2X1TS U1091 ( .A(n771), .B(n784), .Y(DP_OP_153J10_122_5442_n148) );
INVX2TS U1092 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(
DP_OP_153J10_122_5442_n228) );
INVX2TS U1093 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(
DP_OP_153J10_122_5442_n227) );
NOR2X1TS U1094 ( .A(n812), .B(n762), .Y(DP_OP_153J10_122_5442_n305) );
NOR2X1TS U1095 ( .A(n811), .B(n763), .Y(DP_OP_153J10_122_5442_n290) );
NOR2X1TS U1096 ( .A(n772), .B(n762), .Y(DP_OP_153J10_122_5442_n306) );
NOR2X1TS U1097 ( .A(n763), .B(n769), .Y(DP_OP_153J10_122_5442_n296) );
NOR2X1TS U1098 ( .A(n811), .B(n765), .Y(DP_OP_153J10_122_5442_n289) );
CMPR32X2TS U1099 ( .A(n768), .B(n767), .C(n766), .CO(n1470), .S(n1466) );
INVX2TS U1100 ( .A(n1470), .Y(DP_OP_153J10_122_5442_n224) );
NOR2X1TS U1101 ( .A(n812), .B(n769), .Y(DP_OP_153J10_122_5442_n293) );
NOR2X1TS U1102 ( .A(n811), .B(n772), .Y(DP_OP_153J10_122_5442_n288) );
NOR2X1TS U1103 ( .A(n771), .B(n770), .Y(DP_OP_153J10_122_5442_n145) );
NOR2X1TS U1104 ( .A(n773), .B(n772), .Y(DP_OP_153J10_122_5442_n282) );
OAI21X1TS U1105 ( .A0(DP_OP_153J10_122_5442_n412), .A1(n775), .B0(n574), .Y(
DP_OP_153J10_122_5442_n403) );
ADDHXLTS U1106 ( .A(n777), .B(n776), .CO(DP_OP_153J10_122_5442_n380), .S(
n781) );
CMPR32X2TS U1107 ( .A(n782), .B(n781), .C(n780), .CO(n640), .S(n1460) );
INVX2TS U1108 ( .A(n1460), .Y(n786) );
ADDHXLTS U1109 ( .A(n786), .B(n785), .CO(DP_OP_153J10_122_5442_n106), .S(
DP_OP_153J10_122_5442_n107) );
ADDHXLTS U1110 ( .A(n788), .B(n787), .CO(n664), .S(
DP_OP_153J10_122_5442_n115) );
INVX2TS U1111 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]),
.Y(n792) );
ADDHXLTS U1112 ( .A(n792), .B(n791), .CO(DP_OP_153J10_122_5442_n72), .S(
DP_OP_153J10_122_5442_n73) );
CMPR32X2TS U1113 ( .A(n795), .B(n794), .C(n793), .CO(n798), .S(n1463) );
INVX2TS U1114 ( .A(n1463), .Y(n802) );
CMPR32X2TS U1115 ( .A(n800), .B(n799), .C(n798), .CO(n653), .S(n1462) );
INVX2TS U1116 ( .A(n1462), .Y(n804) );
ADDHXLTS U1117 ( .A(n802), .B(n801), .CO(n803), .S(
DP_OP_153J10_122_5442_n127) );
ADDHXLTS U1118 ( .A(n804), .B(n803), .CO(DP_OP_153J10_122_5442_n121), .S(
DP_OP_153J10_122_5442_n122) );
ADDHXLTS U1119 ( .A(n806), .B(n805), .CO(n683), .S(
DP_OP_153J10_122_5442_n273) );
ADDHXLTS U1120 ( .A(n808), .B(n807), .CO(n678), .S(
DP_OP_153J10_122_5442_n268) );
ADDHXLTS U1121 ( .A(n810), .B(n809), .CO(n673), .S(
DP_OP_153J10_122_5442_n261) );
NOR2X1TS U1122 ( .A(n812), .B(n811), .Y(DP_OP_153J10_122_5442_n287) );
CMPR32X2TS U1123 ( .A(DP_OP_154J10_123_2038_n330), .B(n814), .C(n813), .CO(
n938), .S(n1217) );
INVX2TS U1124 ( .A(n1217), .Y(n829) );
CMPR32X2TS U1125 ( .A(n817), .B(n816), .C(n815), .CO(n813), .S(n1211) );
INVX2TS U1126 ( .A(n1211), .Y(n916) );
INVX2TS U1127 ( .A(n483), .Y(n913) );
CMPR32X2TS U1128 ( .A(n820), .B(n819), .C(n818), .CO(n824), .S(n907) );
NOR2X1TS U1129 ( .A(n405), .B(n420), .Y(n1126) );
NOR2X1TS U1130 ( .A(n403), .B(n418), .Y(n1125) );
ADDHXLTS U1131 ( .A(n822), .B(n821), .CO(n818), .S(n891) );
INVX2TS U1132 ( .A(n1573), .Y(n827) );
CMPR32X2TS U1133 ( .A(DP_OP_154J10_123_2038_n239), .B(n824), .C(n823), .CO(
n890), .S(n1573) );
INVX2TS U1134 ( .A(n1569), .Y(n825) );
CMPR32X2TS U1135 ( .A(n826), .B(n825), .C(DP_OP_154J10_123_2038_n63), .CO(
DP_OP_154J10_123_2038_n59), .S(DP_OP_154J10_123_2038_n60) );
CMPR32X2TS U1136 ( .A(n829), .B(n828), .C(n827), .CO(n826), .S(
DP_OP_154J10_123_2038_n67) );
CMPR32X2TS U1137 ( .A(n832), .B(n831), .C(n830), .CO(
DP_OP_154J10_123_2038_n221), .S(DP_OP_154J10_123_2038_n222) );
CMPR32X2TS U1138 ( .A(n835), .B(n834), .C(n833), .CO(
DP_OP_154J10_123_2038_n226), .S(DP_OP_154J10_123_2038_n227) );
NOR2X1TS U1139 ( .A(n402), .B(n488), .Y(n837) );
CMPR32X2TS U1140 ( .A(n838), .B(n837), .C(n836), .CO(
DP_OP_154J10_123_2038_n233), .S(DP_OP_154J10_123_2038_n234) );
ADDHXLTS U1141 ( .A(n840), .B(n839), .CO(DP_OP_154J10_123_2038_n235), .S(
DP_OP_154J10_123_2038_n236) );
CMPR32X2TS U1142 ( .A(Op_MY[20]), .B(Op_MX[20]), .C(n841), .CO(
DP_OP_154J10_123_2038_n312), .S(DP_OP_154J10_123_2038_n313) );
ADDHXLTS U1143 ( .A(Op_MY[18]), .B(Op_MX[18]), .CO(
DP_OP_154J10_123_2038_n326), .S(DP_OP_154J10_123_2038_n327) );
INVX2TS U1144 ( .A(n846), .Y(n879) );
AOI22X1TS U1145 ( .A0(n914), .A1(n879), .B0(n846), .B1(n917), .Y(n843) );
BUFX3TS U1146 ( .A(n843), .Y(n1135) );
BUFX3TS U1147 ( .A(n845), .Y(n1137) );
INVX2TS U1148 ( .A(n1141), .Y(n868) );
INVX2TS U1149 ( .A(n1137), .Y(n878) );
AOI22X1TS U1150 ( .A0(n1137), .A1(n868), .B0(n1141), .B1(n878), .Y(n918) );
OAI221X4TS U1151 ( .A0(n846), .A1(n878), .B0(n879), .B1(n1137), .C0(n1135),
.Y(n1134) );
INVX2TS U1152 ( .A(n919), .Y(n870) );
AOI22X1TS U1153 ( .A0(n1137), .A1(n870), .B0(n919), .B1(n878), .Y(n849) );
OAI22X1TS U1154 ( .A0(n1135), .A1(n918), .B0(n1134), .B1(n849), .Y(
DP_OP_154J10_123_2038_n103) );
INVX2TS U1155 ( .A(n872), .Y(n920) );
AOI22X1TS U1156 ( .A0(n1137), .A1(n872), .B0(n920), .B1(n878), .Y(n851) );
OAI22X1TS U1157 ( .A0(n851), .A1(n1134), .B0(n1135), .B1(n849), .Y(
DP_OP_154J10_123_2038_n104) );
INVX2TS U1158 ( .A(n874), .Y(n877) );
AOI22X1TS U1159 ( .A0(n1137), .A1(n874), .B0(n877), .B1(n878), .Y(n853) );
OAI22X1TS U1160 ( .A0(n851), .A1(n1135), .B0(n853), .B1(n1134), .Y(
DP_OP_154J10_123_2038_n105) );
INVX2TS U1161 ( .A(n883), .Y(n882) );
AOI22X1TS U1162 ( .A0(n1137), .A1(n883), .B0(n882), .B1(n878), .Y(n855) );
OAI22X1TS U1163 ( .A0(n853), .A1(n1135), .B0(n855), .B1(n1134), .Y(
DP_OP_154J10_123_2038_n106) );
INVX2TS U1164 ( .A(n1129), .Y(n1127) );
AOI22X1TS U1165 ( .A0(n1137), .A1(n1129), .B0(n1127), .B1(n878), .Y(n857) );
OAI22X1TS U1166 ( .A0(n855), .A1(n1135), .B0(n857), .B1(n1134), .Y(
DP_OP_154J10_123_2038_n107) );
INVX2TS U1167 ( .A(n1136), .Y(n1124) );
AOI22X1TS U1168 ( .A0(n1137), .A1(n1136), .B0(n1124), .B1(n878), .Y(n856) );
OAI22X1TS U1169 ( .A0(n857), .A1(n1135), .B0(n1134), .B1(n856), .Y(
DP_OP_154J10_123_2038_n108) );
INVX4TS U1170 ( .A(n1128), .Y(DP_OP_154J10_123_2038_n119) );
AOI22X1TS U1171 ( .A0(n914), .A1(n1141), .B0(n868), .B1(n917), .Y(n862) );
INVX2TS U1172 ( .A(n861), .Y(n915) );
AOI22X1TS U1173 ( .A0(n1128), .A1(n915), .B0(n861), .B1(
DP_OP_154J10_123_2038_n119), .Y(n860) );
OAI221X4TS U1174 ( .A0(n861), .A1(n914), .B0(n915), .B1(n917), .C0(n937),
.Y(n935) );
OAI22X1TS U1175 ( .A0(n862), .A1(n935), .B0(n917), .B1(n937), .Y(
DP_OP_154J10_123_2038_n111) );
AOI22X1TS U1176 ( .A0(n914), .A1(n919), .B0(n870), .B1(n917), .Y(n863) );
OAI22X1TS U1177 ( .A0(n862), .A1(n937), .B0(n863), .B1(n935), .Y(
DP_OP_154J10_123_2038_n112) );
AOI22X1TS U1178 ( .A0(n914), .A1(n920), .B0(n872), .B1(n917), .Y(n864) );
OAI22X1TS U1179 ( .A0(n863), .A1(n937), .B0(n935), .B1(n864), .Y(
DP_OP_154J10_123_2038_n113) );
AOI22X1TS U1180 ( .A0(n914), .A1(n877), .B0(n874), .B1(n917), .Y(n936) );
OAI22X1TS U1181 ( .A0(n937), .A1(n864), .B0(n935), .B1(n936), .Y(
DP_OP_154J10_123_2038_n114) );
AOI22X1TS U1182 ( .A0(n914), .A1(n882), .B0(n883), .B1(n917), .Y(n934) );
AOI22X1TS U1183 ( .A0(n914), .A1(n1127), .B0(n1129), .B1(n917), .Y(n866) );
OAI22X1TS U1184 ( .A0(n937), .A1(n934), .B0(n935), .B1(n866), .Y(
DP_OP_154J10_123_2038_n116) );
AOI22X1TS U1185 ( .A0(n914), .A1(n1124), .B0(n1136), .B1(n917), .Y(n865) );
OAI22X1TS U1186 ( .A0(n937), .A1(n866), .B0(n935), .B1(n865), .Y(
DP_OP_154J10_123_2038_n117) );
INVX2TS U1187 ( .A(n1123), .Y(n867) );
AOI21X1TS U1188 ( .A0(n868), .A1(n867), .B0(DP_OP_154J10_123_2038_n119), .Y(
DP_OP_154J10_123_2038_n120) );
AOI22X1TS U1189 ( .A0(n1141), .A1(n1128), .B0(DP_OP_154J10_123_2038_n119),
.B1(n868), .Y(n869) );
OAI32X1TS U1190 ( .A0(n1123), .A1(n870), .A2(DP_OP_154J10_123_2038_n119),
.B0(n869), .B1(n867), .Y(DP_OP_154J10_123_2038_n121) );
AOI22X1TS U1191 ( .A0(n919), .A1(n1128), .B0(DP_OP_154J10_123_2038_n119),
.B1(n870), .Y(n871) );
OAI32X1TS U1192 ( .A0(n1123), .A1(n872), .A2(DP_OP_154J10_123_2038_n119),
.B0(n871), .B1(n867), .Y(DP_OP_154J10_123_2038_n122) );
AOI22X1TS U1193 ( .A0(n872), .A1(DP_OP_154J10_123_2038_n119), .B0(n1128),
.B1(n920), .Y(n873) );
OAI32X1TS U1194 ( .A0(n1123), .A1(n874), .A2(DP_OP_154J10_123_2038_n119),
.B0(n873), .B1(n867), .Y(DP_OP_154J10_123_2038_n123) );
AOI22X1TS U1195 ( .A0(n874), .A1(DP_OP_154J10_123_2038_n119), .B0(n1128),
.B1(n877), .Y(n875) );
OAI32X1TS U1196 ( .A0(n1123), .A1(n883), .A2(DP_OP_154J10_123_2038_n119),
.B0(n875), .B1(n867), .Y(DP_OP_154J10_123_2038_n124) );
INVX2TS U1197 ( .A(n1140), .Y(n921) );
AOI22X1TS U1198 ( .A0(n921), .A1(n919), .B0(n1141), .B1(n1140), .Y(
DP_OP_154J10_123_2038_n94) );
AOI22X1TS U1199 ( .A0(n921), .A1(n877), .B0(n920), .B1(n1140), .Y(
DP_OP_154J10_123_2038_n96) );
AOI22X1TS U1200 ( .A0(n921), .A1(n882), .B0(n877), .B1(n1140), .Y(
DP_OP_154J10_123_2038_n97) );
AOI22X1TS U1201 ( .A0(n921), .A1(n1127), .B0(n882), .B1(n1140), .Y(
DP_OP_154J10_123_2038_n98) );
AOI22X1TS U1202 ( .A0(n921), .A1(n1124), .B0(n1127), .B1(n1140), .Y(
DP_OP_154J10_123_2038_n99) );
OAI21X1TS U1203 ( .A0(n917), .A1(n879), .B0(n878), .Y(
DP_OP_154J10_123_2038_n101) );
XOR2X1TS U1204 ( .A(n881), .B(n880), .Y(DP_OP_154J10_123_2038_n193) );
NOR2X1TS U1205 ( .A(n1135), .B(n1124), .Y(DP_OP_154J10_123_2038_n109) );
AOI22X1TS U1206 ( .A0(n883), .A1(DP_OP_154J10_123_2038_n119), .B0(n1128),
.B1(n882), .Y(n884) );
OAI32X1TS U1207 ( .A0(n1123), .A1(n1129), .A2(DP_OP_154J10_123_2038_n119),
.B0(n884), .B1(n867), .Y(DP_OP_154J10_123_2038_n125) );
ADDHX1TS U1208 ( .A(n886), .B(n885), .CO(n889), .S(n1205) );
INVX2TS U1209 ( .A(n1205), .Y(DP_OP_154J10_123_2038_n202) );
CMPR32X2TS U1210 ( .A(n889), .B(n888), .C(n887), .CO(n815), .S(n1214) );
INVX2TS U1211 ( .A(n1214), .Y(DP_OP_154J10_123_2038_n201) );
CMPR32X2TS U1212 ( .A(DP_OP_154J10_123_2038_n232), .B(
DP_OP_154J10_123_2038_n238), .C(n890), .CO(n896), .S(n1569) );
INVX2TS U1213 ( .A(n1454), .Y(DP_OP_154J10_123_2038_n83) );
CMPR32X2TS U1214 ( .A(n893), .B(n892), .C(n891), .CO(n905), .S(n1581) );
INVX2TS U1215 ( .A(n1581), .Y(DP_OP_154J10_123_2038_n87) );
CMPR32X2TS U1216 ( .A(DP_OP_154J10_123_2038_n311), .B(
DP_OP_154J10_123_2038_n315), .C(n894), .CO(n507), .S(n1175) );
INVX2TS U1217 ( .A(n1175), .Y(DP_OP_154J10_123_2038_n196) );
CMPR32X2TS U1218 ( .A(DP_OP_154J10_123_2038_n316), .B(
DP_OP_154J10_123_2038_n322), .C(n895), .CO(n894), .S(n1223) );
INVX2TS U1219 ( .A(n1223), .Y(DP_OP_154J10_123_2038_n197) );
CMPR32X2TS U1220 ( .A(DP_OP_154J10_123_2038_n225), .B(
DP_OP_154J10_123_2038_n231), .C(n896), .CO(n902), .S(n1454) );
INVX2TS U1221 ( .A(n1241), .Y(DP_OP_154J10_123_2038_n81) );
NOR2X1TS U1222 ( .A(n402), .B(n421), .Y(n898) );
CMPR32X2TS U1223 ( .A(DP_OP_154J10_123_2038_n217), .B(
DP_OP_154J10_123_2038_n219), .C(n897), .CO(n900), .S(n1241) );
INVX2TS U1224 ( .A(n1232), .Y(DP_OP_154J10_123_2038_n80) );
CMPR32X2TS U1225 ( .A(n899), .B(n898), .C(DP_OP_154J10_123_2038_n215), .CO(
n910), .S(n901) );
CMPR32X2TS U1226 ( .A(DP_OP_154J10_123_2038_n216), .B(n901), .C(n900), .CO(
n908), .S(n1232) );
INVX2TS U1227 ( .A(n1235), .Y(DP_OP_154J10_123_2038_n79) );
CMPR32X2TS U1228 ( .A(DP_OP_154J10_123_2038_n220), .B(
DP_OP_154J10_123_2038_n224), .C(n902), .CO(n897), .S(n1446) );
INVX2TS U1229 ( .A(n1446), .Y(DP_OP_154J10_123_2038_n82) );
INVX2TS U1230 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(
DP_OP_154J10_123_2038_n195) );
INVX2TS U1231 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(
DP_OP_154J10_123_2038_n194) );
NOR2X1TS U1232 ( .A(n484), .B(n417), .Y(DP_OP_154J10_123_2038_n269) );
ADDHXLTS U1233 ( .A(n904), .B(n903), .CO(DP_OP_154J10_123_2038_n240), .S(
DP_OP_154J10_123_2038_n241) );
CMPR32X2TS U1234 ( .A(n907), .B(n906), .C(n905), .CO(n823), .S(n1577) );
INVX2TS U1235 ( .A(n1577), .Y(DP_OP_154J10_123_2038_n86) );
NOR2X1TS U1236 ( .A(n913), .B(n420), .Y(DP_OP_154J10_123_2038_n274) );
CMPR32X2TS U1237 ( .A(n910), .B(n909), .C(n908), .CO(n1202), .S(n1235) );
INVX2TS U1238 ( .A(n1202), .Y(DP_OP_154J10_123_2038_n78) );
NOR2X1TS U1239 ( .A(n404), .B(n420), .Y(DP_OP_154J10_123_2038_n273) );
ADDHXLTS U1240 ( .A(n912), .B(n911), .CO(DP_OP_154J10_123_2038_n228), .S(
DP_OP_154J10_123_2038_n229) );
NOR2X1TS U1241 ( .A(n419), .B(n913), .Y(DP_OP_154J10_123_2038_n250) );
OAI21X1TS U1242 ( .A0(DP_OP_154J10_123_2038_n119), .A1(n915), .B0(n914), .Y(
DP_OP_154J10_123_2038_n110) );
NOR2X1TS U1243 ( .A(n404), .B(n422), .Y(DP_OP_154J10_123_2038_n261) );
NOR2X1TS U1244 ( .A(n404), .B(n421), .Y(DP_OP_154J10_123_2038_n255) );
ADDHXLTS U1245 ( .A(DP_OP_154J10_123_2038_n73), .B(n916), .CO(n828), .S(
DP_OP_154J10_123_2038_n72) );
OAI32X1TS U1246 ( .A0(n917), .A1(n1136), .A2(n937), .B0(n935), .B1(n917),
.Y(DP_OP_154J10_123_2038_n91) );
OAI22X1TS U1247 ( .A0(n1137), .A1(n1135), .B0(n918), .B1(n1134), .Y(n923) );
AOI22X1TS U1248 ( .A0(n921), .A1(n920), .B0(n919), .B1(n1140), .Y(n922) );
CMPR32X2TS U1249 ( .A(n923), .B(n922), .C(DP_OP_154J10_123_2038_n29), .CO(
DP_OP_154J10_123_2038_n24), .S(DP_OP_154J10_123_2038_n25) );
ADDHXLTS U1250 ( .A(n925), .B(n924), .CO(DP_OP_154J10_123_2038_n244), .S(
n906) );
NOR2X1TS U1251 ( .A(n404), .B(n488), .Y(DP_OP_154J10_123_2038_n279) );
CMPR32X2TS U1252 ( .A(n928), .B(n927), .C(n926), .CO(
DP_OP_154J10_123_2038_n324), .S(DP_OP_154J10_123_2038_n325) );
CMPR32X2TS U1253 ( .A(n931), .B(n930), .C(n929), .CO(
DP_OP_154J10_123_2038_n317), .S(DP_OP_154J10_123_2038_n318) );
ADDHXLTS U1254 ( .A(n933), .B(n932), .CO(DP_OP_154J10_123_2038_n335), .S(
n816) );
OAI22X1TS U1255 ( .A0(n937), .A1(n936), .B0(n935), .B1(n934), .Y(n940) );
CMPR32X2TS U1256 ( .A(DP_OP_154J10_123_2038_n323), .B(
DP_OP_154J10_123_2038_n329), .C(n938), .CO(n895), .S(n1220) );
INVX2TS U1257 ( .A(n1220), .Y(n939) );
ADDHXLTS U1258 ( .A(n940), .B(n939), .CO(DP_OP_154J10_123_2038_n61), .S(
DP_OP_154J10_123_2038_n62) );
NOR2X1TS U1259 ( .A(n402), .B(n422), .Y(DP_OP_154J10_123_2038_n260) );
ADDHXLTS U1260 ( .A(n942), .B(n941), .CO(DP_OP_154J10_123_2038_n331), .S(
DP_OP_154J10_123_2038_n332) );
CMPR32X2TS U1261 ( .A(DP_OP_155J10_124_2038_n330), .B(n944), .C(n943), .CO(
n1050), .S(n1190) );
INVX2TS U1262 ( .A(n1190), .Y(n959) );
CMPR32X2TS U1263 ( .A(n947), .B(n946), .C(n945), .CO(n943), .S(n1181) );
INVX2TS U1264 ( .A(n1181), .Y(n1053) );
CMPR32X2TS U1265 ( .A(n950), .B(n949), .C(n948), .CO(n954), .S(n1016) );
ADDHXLTS U1266 ( .A(n952), .B(n951), .CO(n948), .S(n1006) );
INVX2TS U1267 ( .A(n1649), .Y(n957) );
CMPR32X2TS U1268 ( .A(DP_OP_155J10_124_2038_n239), .B(n954), .C(n953), .CO(
n1012), .S(n1649) );
INVX2TS U1269 ( .A(n1648), .Y(n955) );
CMPR32X2TS U1270 ( .A(n956), .B(n955), .C(DP_OP_155J10_124_2038_n63), .CO(
DP_OP_155J10_124_2038_n59), .S(DP_OP_155J10_124_2038_n60) );
CMPR32X2TS U1271 ( .A(n959), .B(n958), .C(n957), .CO(n956), .S(
DP_OP_155J10_124_2038_n67) );
INVX2TS U1272 ( .A(n963), .Y(n1038) );
AOI22X1TS U1273 ( .A0(n1035), .A1(n1038), .B0(n963), .B1(n1039), .Y(n961) );
BUFX3TS U1274 ( .A(n961), .Y(n1041) );
INVX2TS U1275 ( .A(n985), .Y(n1100) );
INVX4TS U1276 ( .A(n1037), .Y(n1042) );
AOI22X1TS U1277 ( .A0(n1037), .A1(n1100), .B0(n985), .B1(n1042), .Y(n998) );
OAI221X4TS U1278 ( .A0(n963), .A1(n1037), .B0(n1038), .B1(n1042), .C0(n1041),
.Y(n1040) );
CMPR32X2TS U1279 ( .A(Op_MY[5]), .B(Op_MY[11]), .C(n964), .CO(n985), .S(n987) );
INVX2TS U1280 ( .A(n987), .Y(n997) );
AOI22X1TS U1281 ( .A0(n1037), .A1(n997), .B0(n987), .B1(n1042), .Y(n966) );
OAI22X1TS U1282 ( .A0(n1041), .A1(n998), .B0(n1040), .B1(n966), .Y(
DP_OP_155J10_124_2038_n103) );
CMPR32X2TS U1283 ( .A(Op_MY[4]), .B(n391), .C(n965), .CO(n964), .S(n989) );
INVX2TS U1284 ( .A(n989), .Y(n996) );
AOI22X1TS U1285 ( .A0(n1037), .A1(n996), .B0(n989), .B1(n1042), .Y(n968) );
OAI22X1TS U1286 ( .A0(n1041), .A1(n966), .B0(n1040), .B1(n968), .Y(
DP_OP_155J10_124_2038_n104) );
CMPR32X2TS U1287 ( .A(Op_MY[3]), .B(n495), .C(n967), .CO(n965), .S(n991) );
INVX2TS U1288 ( .A(n991), .Y(n995) );
AOI22X1TS U1289 ( .A0(n1037), .A1(n995), .B0(n991), .B1(n1042), .Y(n970) );
OAI22X1TS U1290 ( .A0(n1041), .A1(n968), .B0(n1040), .B1(n970), .Y(
DP_OP_155J10_124_2038_n105) );
CMPR32X2TS U1291 ( .A(Op_MY[2]), .B(n492), .C(n969), .CO(n967), .S(n1002) );
INVX2TS U1292 ( .A(n1002), .Y(n1001) );
AOI22X1TS U1293 ( .A0(n1037), .A1(n1001), .B0(n1002), .B1(n1042), .Y(n972)
);
OAI22X1TS U1294 ( .A0(n1041), .A1(n970), .B0(n1040), .B1(n972), .Y(
DP_OP_155J10_124_2038_n106) );
INVX2TS U1295 ( .A(n1092), .Y(n1090) );
AOI22X1TS U1296 ( .A0(n1037), .A1(n1090), .B0(n1092), .B1(n1042), .Y(n974)
);
OAI22X1TS U1297 ( .A0(n1041), .A1(n972), .B0(n1040), .B1(n974), .Y(
DP_OP_155J10_124_2038_n107) );
INVX2TS U1298 ( .A(n1095), .Y(n1087) );
AOI22X1TS U1299 ( .A0(n1037), .A1(n1087), .B0(n1095), .B1(n1042), .Y(n973)
);
OAI22X1TS U1300 ( .A0(n1041), .A1(n974), .B0(n1040), .B1(n973), .Y(
DP_OP_155J10_124_2038_n108) );
INVX4TS U1301 ( .A(n1091), .Y(DP_OP_155J10_124_2038_n119) );
CMPR32X2TS U1302 ( .A(Op_MX[2]), .B(n496), .C(n976), .CO(n960), .S(n978) );
INVX2TS U1303 ( .A(n978), .Y(n1036) );
AOI22X1TS U1304 ( .A0(n1091), .A1(n1036), .B0(n978), .B1(
DP_OP_155J10_124_2038_n119), .Y(n977) );
BUFX3TS U1305 ( .A(n977), .Y(n1049) );
OAI221X4TS U1306 ( .A0(n978), .A1(n1035), .B0(n1036), .B1(n1039), .C0(n1049),
.Y(n1047) );
AOI22X1TS U1307 ( .A0(n1035), .A1(n1100), .B0(n985), .B1(n1039), .Y(n979) );
OAI22X1TS U1308 ( .A0(n1039), .A1(n1049), .B0(n1047), .B1(n979), .Y(
DP_OP_155J10_124_2038_n111) );
AOI22X1TS U1309 ( .A0(n1035), .A1(n997), .B0(n987), .B1(n1039), .Y(n980) );
OAI22X1TS U1310 ( .A0(n1049), .A1(n979), .B0(n1047), .B1(n980), .Y(
DP_OP_155J10_124_2038_n112) );
AOI22X1TS U1311 ( .A0(n1035), .A1(n996), .B0(n989), .B1(n1039), .Y(n981) );
OAI22X1TS U1312 ( .A0(n1049), .A1(n980), .B0(n1047), .B1(n981), .Y(
DP_OP_155J10_124_2038_n113) );
AOI22X1TS U1313 ( .A0(n1035), .A1(n995), .B0(n991), .B1(n1039), .Y(n1048) );
OAI22X1TS U1314 ( .A0(n1049), .A1(n981), .B0(n1047), .B1(n1048), .Y(
DP_OP_155J10_124_2038_n114) );
AOI22X1TS U1315 ( .A0(n1035), .A1(n1001), .B0(n1002), .B1(n1039), .Y(n1046)
);
AOI22X1TS U1316 ( .A0(n1035), .A1(n1090), .B0(n1092), .B1(n1039), .Y(n983)
);
OAI22X1TS U1317 ( .A0(n1049), .A1(n1046), .B0(n1047), .B1(n983), .Y(
DP_OP_155J10_124_2038_n116) );
AOI22X1TS U1318 ( .A0(n1035), .A1(n1087), .B0(n1095), .B1(n1039), .Y(n982)
);
OAI22X1TS U1319 ( .A0(n1049), .A1(n983), .B0(n1047), .B1(n982), .Y(
DP_OP_155J10_124_2038_n117) );
AOI21X1TS U1320 ( .A0(n985), .A1(n984), .B0(DP_OP_155J10_124_2038_n119), .Y(
DP_OP_155J10_124_2038_n120) );
AOI22X1TS U1321 ( .A0(n985), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n1100), .Y(n986) );
OAI32X1TS U1322 ( .A0(n1086), .A1(n987), .A2(DP_OP_155J10_124_2038_n119),
.B0(n986), .B1(n984), .Y(DP_OP_155J10_124_2038_n121) );
AOI22X1TS U1323 ( .A0(n987), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n997), .Y(n988) );
OAI32X1TS U1324 ( .A0(n1086), .A1(n989), .A2(DP_OP_155J10_124_2038_n119),
.B0(n988), .B1(n984), .Y(DP_OP_155J10_124_2038_n122) );
AOI22X1TS U1325 ( .A0(n989), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n996), .Y(n990) );
OAI32X1TS U1326 ( .A0(n1086), .A1(n991), .A2(DP_OP_155J10_124_2038_n119),
.B0(n990), .B1(n984), .Y(DP_OP_155J10_124_2038_n123) );
AOI22X1TS U1327 ( .A0(n991), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n995), .Y(n992) );
OAI32X1TS U1328 ( .A0(n1086), .A1(n1002), .A2(DP_OP_155J10_124_2038_n119),
.B0(n992), .B1(n984), .Y(DP_OP_155J10_124_2038_n124) );
AOI2BB2X4TS U1329 ( .B0(n994), .B1(n1042), .A0N(n1042), .A1N(n994), .Y(n1054) );
NAND2X2TS U1330 ( .A(n1037), .B(n994), .Y(n1101) );
OAI22X1TS U1331 ( .A0(n1100), .A1(n1054), .B0(n997), .B1(n1101), .Y(
DP_OP_155J10_124_2038_n94) );
OAI22X1TS U1332 ( .A0(n996), .A1(n1054), .B0(n995), .B1(n1101), .Y(
DP_OP_155J10_124_2038_n96) );
OAI22X1TS U1333 ( .A0(n995), .A1(n1054), .B0(n1001), .B1(n1101), .Y(
DP_OP_155J10_124_2038_n97) );
OAI22X1TS U1334 ( .A0(n1001), .A1(n1054), .B0(n1090), .B1(n1101), .Y(
DP_OP_155J10_124_2038_n98) );
OAI22X1TS U1335 ( .A0(n1090), .A1(n1054), .B0(n1087), .B1(n1101), .Y(
DP_OP_155J10_124_2038_n99) );
OAI22X1TS U1336 ( .A0(n997), .A1(n1054), .B0(n996), .B1(n1101), .Y(n1000) );
OAI22X1TS U1337 ( .A0(n1042), .A1(n1041), .B0(n1040), .B1(n998), .Y(n999) );
CMPR32X2TS U1338 ( .A(n1000), .B(n999), .C(DP_OP_155J10_124_2038_n29), .CO(
DP_OP_155J10_124_2038_n24), .S(DP_OP_155J10_124_2038_n25) );
NOR2X1TS U1339 ( .A(n1041), .B(n1087), .Y(DP_OP_155J10_124_2038_n109) );
AOI22X1TS U1340 ( .A0(n1002), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n1001), .Y(n1003) );
OAI32X1TS U1341 ( .A0(n1086), .A1(n1092), .A2(DP_OP_155J10_124_2038_n119),
.B0(n1003), .B1(n984), .Y(DP_OP_155J10_124_2038_n125) );
INVX2TS U1342 ( .A(n1196), .Y(DP_OP_155J10_124_2038_n202) );
CMPR32X2TS U1343 ( .A(n1008), .B(n1007), .C(n1006), .CO(n1014), .S(n1651) );
INVX2TS U1344 ( .A(n1651), .Y(DP_OP_155J10_124_2038_n87) );
CMPR32X2TS U1345 ( .A(n1011), .B(n1010), .C(n1009), .CO(n945), .S(n1193) );
INVX2TS U1346 ( .A(n1193), .Y(DP_OP_155J10_124_2038_n201) );
CMPR32X2TS U1347 ( .A(DP_OP_155J10_124_2038_n232), .B(
DP_OP_155J10_124_2038_n238), .C(n1012), .CO(n1017), .S(n1648) );
INVX2TS U1348 ( .A(n1456), .Y(DP_OP_155J10_124_2038_n83) );
CMPR32X2TS U1349 ( .A(DP_OP_155J10_124_2038_n316), .B(
DP_OP_155J10_124_2038_n322), .C(n1013), .CO(n1018), .S(n1187) );
INVX2TS U1350 ( .A(n1187), .Y(DP_OP_155J10_124_2038_n197) );
CMPR32X2TS U1351 ( .A(n1016), .B(n1015), .C(n1014), .CO(n953), .S(n1650) );
INVX2TS U1352 ( .A(n1650), .Y(DP_OP_155J10_124_2038_n86) );
CMPR32X2TS U1353 ( .A(DP_OP_155J10_124_2038_n225), .B(
DP_OP_155J10_124_2038_n231), .C(n1017), .CO(n1027), .S(n1456) );
INVX2TS U1354 ( .A(n1238), .Y(DP_OP_155J10_124_2038_n81) );
CMPR32X2TS U1355 ( .A(DP_OP_155J10_124_2038_n311), .B(
DP_OP_155J10_124_2038_n315), .C(n1018), .CO(n513), .S(n1169) );
INVX2TS U1356 ( .A(n1169), .Y(DP_OP_155J10_124_2038_n196) );
CMPR32X2TS U1357 ( .A(DP_OP_155J10_124_2038_n217), .B(
DP_OP_155J10_124_2038_n219), .C(n1019), .CO(n1030), .S(n1238) );
INVX2TS U1358 ( .A(n1226), .Y(DP_OP_155J10_124_2038_n80) );
CMPR32X2TS U1359 ( .A(n1021), .B(n1020), .C(DP_OP_155J10_124_2038_n306),
.CO(n1026), .S(n1023) );
CMPR32X2TS U1360 ( .A(DP_OP_155J10_124_2038_n307), .B(n1023), .C(n1022),
.CO(n1024), .S(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]) );
CMPR32X2TS U1361 ( .A(n1026), .B(n1025), .C(n1024), .CO(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .S(n1166) );
INVX2TS U1362 ( .A(n1166), .Y(DP_OP_155J10_124_2038_n193) );
CMPR32X2TS U1363 ( .A(DP_OP_155J10_124_2038_n220), .B(
DP_OP_155J10_124_2038_n224), .C(n1027), .CO(n1019), .S(n1443) );
INVX2TS U1364 ( .A(n1443), .Y(DP_OP_155J10_124_2038_n82) );
CMPR32X2TS U1365 ( .A(n1029), .B(n1028), .C(DP_OP_155J10_124_2038_n215),
.CO(n1034), .S(n1031) );
CMPR32X2TS U1366 ( .A(DP_OP_155J10_124_2038_n216), .B(n1031), .C(n1030),
.CO(n1032), .S(n1226) );
INVX2TS U1367 ( .A(n1229), .Y(DP_OP_155J10_124_2038_n79) );
INVX2TS U1368 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(
DP_OP_155J10_124_2038_n195) );
INVX2TS U1369 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(
DP_OP_155J10_124_2038_n194) );
CMPR32X2TS U1370 ( .A(n1034), .B(n1033), .C(n1032), .CO(n1178), .S(n1229) );
INVX2TS U1371 ( .A(n1178), .Y(DP_OP_155J10_124_2038_n78) );
INVX2TS U1372 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]),
.Y(DP_OP_155J10_124_2038_n192) );
OAI21X1TS U1373 ( .A0(DP_OP_155J10_124_2038_n119), .A1(n1036), .B0(n1035),
.Y(DP_OP_155J10_124_2038_n110) );
OAI21X1TS U1374 ( .A0(n1039), .A1(n1038), .B0(n1037), .Y(
DP_OP_155J10_124_2038_n101) );
OAI32X1TS U1375 ( .A0(n1039), .A1(n1095), .A2(n1049), .B0(n1047), .B1(n1039),
.Y(DP_OP_155J10_124_2038_n91) );
OAI32X1TS U1376 ( .A0(n1042), .A1(n1095), .A2(n1041), .B0(n1040), .B1(n1042),
.Y(DP_OP_155J10_124_2038_n90) );
CMPR32X2TS U1377 ( .A(n1045), .B(n1044), .C(n1043), .CO(
DP_OP_155J10_124_2038_n221), .S(DP_OP_155J10_124_2038_n222) );
OAI22X1TS U1378 ( .A0(n1049), .A1(n1048), .B0(n1047), .B1(n1046), .Y(n1052)
);
CMPR32X2TS U1379 ( .A(DP_OP_155J10_124_2038_n323), .B(
DP_OP_155J10_124_2038_n329), .C(n1050), .CO(n1013), .S(n1184) );
INVX2TS U1380 ( .A(n1184), .Y(n1051) );
ADDHXLTS U1381 ( .A(DP_OP_155J10_124_2038_n73), .B(n1053), .CO(n958), .S(
DP_OP_155J10_124_2038_n72) );
CMPR32X2TS U1382 ( .A(n1057), .B(n1056), .C(n1055), .CO(
DP_OP_155J10_124_2038_n324), .S(DP_OP_155J10_124_2038_n325) );
CMPR32X2TS U1383 ( .A(n1060), .B(n1059), .C(n1058), .CO(
DP_OP_155J10_124_2038_n317), .S(DP_OP_155J10_124_2038_n318) );
CMPR32X2TS U1384 ( .A(n1063), .B(n1062), .C(n1061), .CO(
DP_OP_155J10_124_2038_n226), .S(DP_OP_155J10_124_2038_n227) );
CMPR32X2TS U1385 ( .A(n1066), .B(n1065), .C(n1064), .CO(
DP_OP_155J10_124_2038_n312), .S(DP_OP_155J10_124_2038_n313) );
ADDHXLTS U1386 ( .A(n1068), .B(n1067), .CO(DP_OP_155J10_124_2038_n244), .S(
n1015) );
CMPR32X2TS U1387 ( .A(n1071), .B(n1070), .C(n1069), .CO(
DP_OP_155J10_124_2038_n233), .S(DP_OP_155J10_124_2038_n234) );
ADDHXLTS U1388 ( .A(n1073), .B(n1072), .CO(DP_OP_155J10_124_2038_n335), .S(
n946) );
ADDHXLTS U1389 ( .A(n1075), .B(n1074), .CO(DP_OP_155J10_124_2038_n331), .S(
DP_OP_155J10_124_2038_n332) );
ADDHXLTS U1390 ( .A(n1077), .B(n1076), .CO(DP_OP_155J10_124_2038_n240), .S(
DP_OP_155J10_124_2038_n241) );
ADDHXLTS U1391 ( .A(n1079), .B(n1078), .CO(DP_OP_155J10_124_2038_n235), .S(
DP_OP_155J10_124_2038_n236) );
ADDHXLTS U1392 ( .A(n1081), .B(n1080), .CO(DP_OP_155J10_124_2038_n319), .S(
DP_OP_155J10_124_2038_n320) );
ADDHXLTS U1393 ( .A(n1083), .B(n1082), .CO(DP_OP_155J10_124_2038_n228), .S(
DP_OP_155J10_124_2038_n229) );
ADDHXLTS U1394 ( .A(n1085), .B(n1084), .CO(DP_OP_155J10_124_2038_n326), .S(
DP_OP_155J10_124_2038_n327) );
AOI21X1TS U1395 ( .A0(n1095), .A1(n1086), .B0(DP_OP_155J10_124_2038_n119),
.Y(n1118) );
NAND2X1TS U1396 ( .A(n498), .B(n499), .Y(n1120) );
NAND2X1TS U1397 ( .A(Op_MY[0]), .B(Op_MX[0]), .Y(n1464) );
INVX2TS U1398 ( .A(n1652), .Y(n1097) );
NAND2X1TS U1399 ( .A(n1091), .B(n984), .Y(n1094) );
AOI22X1TS U1400 ( .A0(n1092), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n1090), .Y(n1093) );
OAI22X1TS U1401 ( .A0(n1095), .A1(n1094), .B0(n1093), .B1(n984), .Y(n1096)
);
XOR2X1TS U1402 ( .A(n1098), .B(DP_OP_155J10_124_2038_n19), .Y(n1102) );
OAI31X1TS U1403 ( .A0(n1102), .A1(n1101), .A2(n1100), .B0(n1099), .Y(n1103)
);
XOR2X1TS U1404 ( .A(DP_OP_155J10_124_2038_n18), .B(n1103), .Y(n1170) );
CMPR32X2TS U1405 ( .A(DP_OP_155J10_124_2038_n20), .B(
DP_OP_155J10_124_2038_n22), .C(n1104), .CO(n1098), .S(n1188) );
CMPR32X2TS U1406 ( .A(DP_OP_155J10_124_2038_n23), .B(
DP_OP_155J10_124_2038_n27), .C(n1105), .CO(n1104), .S(n1185) );
CMPR32X2TS U1407 ( .A(DP_OP_155J10_124_2038_n28), .B(
DP_OP_155J10_124_2038_n33), .C(n1106), .CO(n1105), .S(n1191) );
CMPR32X2TS U1408 ( .A(DP_OP_155J10_124_2038_n34), .B(
DP_OP_155J10_124_2038_n39), .C(n1107), .CO(n1106), .S(n1182) );
CMPR32X2TS U1409 ( .A(DP_OP_155J10_124_2038_n40), .B(
DP_OP_155J10_124_2038_n45), .C(n1108), .CO(n1107), .S(n1194) );
CMPR32X2TS U1410 ( .A(DP_OP_155J10_124_2038_n46), .B(
DP_OP_155J10_124_2038_n51), .C(n1109), .CO(n1108), .S(n1197) );
CMPR32X2TS U1411 ( .A(DP_OP_155J10_124_2038_n52), .B(
DP_OP_155J10_124_2038_n57), .C(n1110), .CO(n1109), .S(n1200) );
INVX2TS U1412 ( .A(n1120), .Y(n1199) );
CMPR32X2TS U1413 ( .A(n1111), .B(DP_OP_155J10_124_2038_n64), .C(
DP_OP_155J10_124_2038_n58), .CO(n1110), .S(n1179) );
CMPR32X2TS U1414 ( .A(DP_OP_155J10_124_2038_n65), .B(
DP_OP_155J10_124_2038_n69), .C(n1112), .CO(n1111), .S(n1230) );
CMPR32X2TS U1415 ( .A(n1113), .B(DP_OP_155J10_124_2038_n74), .C(
DP_OP_155J10_124_2038_n70), .CO(n1112), .S(n1227) );
CMPR32X2TS U1416 ( .A(n1115), .B(n1114), .C(DP_OP_155J10_124_2038_n75), .CO(
n1113), .S(n1239) );
CMPR32X2TS U1417 ( .A(n1118), .B(n1117), .C(n1116), .CO(n1115), .S(n1444) );
CMPR32X2TS U1418 ( .A(n1120), .B(n1464), .C(n1119), .CO(n1117), .S(n1455) );
INVX2TS U1419 ( .A(n1605), .Y(DP_OP_156J10_125_3370_n98) );
ADDHX1TS U1420 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]),
.B(n1121), .CO(n1122), .S(n1605) );
INVX2TS U1421 ( .A(n1601), .Y(DP_OP_156J10_125_3370_n97) );
ADDHX1TS U1422 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]),
.B(n1122), .CO(n1165), .S(n1601) );
INVX2TS U1423 ( .A(n1597), .Y(DP_OP_156J10_125_3370_n96) );
AOI21X1TS U1424 ( .A0(n1136), .A1(n1123), .B0(DP_OP_154J10_123_2038_n119),
.Y(n1159) );
NAND2X1TS U1425 ( .A(Op_MY[18]), .B(Op_MX[18]), .Y(n1162) );
NOR2X1TS U1426 ( .A(n405), .B(n488), .Y(n1589) );
INVX2TS U1427 ( .A(n1589), .Y(n1161) );
INVX2TS U1428 ( .A(n1585), .Y(n1133) );
NAND2X1TS U1429 ( .A(n1128), .B(n867), .Y(n1131) );
AOI22X1TS U1430 ( .A0(n1129), .A1(DP_OP_154J10_123_2038_n119), .B0(n1128),
.B1(n1127), .Y(n1130) );
OAI22X1TS U1431 ( .A0(n1136), .A1(n1131), .B0(n1130), .B1(n867), .Y(n1132)
);
CMPR32X2TS U1432 ( .A(n1133), .B(n1205), .C(n1132), .CO(n1155), .S(n1157) );
OAI32X1TS U1433 ( .A0(n1137), .A1(n1136), .A2(n1135), .B0(n1134), .B1(n1137),
.Y(n1151) );
XOR2X1TS U1434 ( .A(n1138), .B(DP_OP_154J10_123_2038_n19), .Y(n1142) );
OAI31X1TS U1435 ( .A0(n1142), .A1(n1141), .A2(n1140), .B0(n1139), .Y(n1143)
);
XOR2X1TS U1436 ( .A(DP_OP_154J10_123_2038_n18), .B(n1143), .Y(n1176) );
CMPR32X2TS U1437 ( .A(DP_OP_154J10_123_2038_n22), .B(
DP_OP_154J10_123_2038_n20), .C(n1144), .CO(n1138), .S(n1224) );
CMPR32X2TS U1438 ( .A(DP_OP_154J10_123_2038_n23), .B(
DP_OP_154J10_123_2038_n27), .C(n1145), .CO(n1144), .S(n1221) );
CMPR32X2TS U1439 ( .A(DP_OP_154J10_123_2038_n28), .B(
DP_OP_154J10_123_2038_n33), .C(n1146), .CO(n1145), .S(n1218) );
CMPR32X2TS U1440 ( .A(DP_OP_154J10_123_2038_n34), .B(
DP_OP_154J10_123_2038_n39), .C(n1147), .CO(n1146), .S(n1212) );
CMPR32X2TS U1441 ( .A(DP_OP_154J10_123_2038_n40), .B(
DP_OP_154J10_123_2038_n45), .C(n1148), .CO(n1147), .S(n1215) );
CMPR32X2TS U1442 ( .A(DP_OP_154J10_123_2038_n46), .B(
DP_OP_154J10_123_2038_n51), .C(n1149), .CO(n1148), .S(n1206) );
CMPR32X2TS U1443 ( .A(DP_OP_154J10_123_2038_n52), .B(
DP_OP_154J10_123_2038_n57), .C(n1150), .CO(n1149), .S(n1209) );
INVX2TS U1444 ( .A(n1162), .Y(n1208) );
CMPR32X2TS U1445 ( .A(n1152), .B(n1151), .C(DP_OP_154J10_123_2038_n58), .CO(
n1150), .S(n1203) );
CMPR32X2TS U1446 ( .A(DP_OP_154J10_123_2038_n65), .B(
DP_OP_154J10_123_2038_n69), .C(n1153), .CO(n1152), .S(n1236) );
CMPR32X2TS U1447 ( .A(n1154), .B(DP_OP_154J10_123_2038_n74), .C(
DP_OP_154J10_123_2038_n70), .CO(n1153), .S(n1233) );
CMPR32X2TS U1448 ( .A(n1156), .B(n1155), .C(DP_OP_154J10_123_2038_n75), .CO(
n1154), .S(n1242) );
CMPR32X2TS U1449 ( .A(n1159), .B(n1158), .C(n1157), .CO(n1156), .S(n1447) );
CMPR32X2TS U1450 ( .A(n1162), .B(n1161), .C(n1160), .CO(n1158), .S(n1453) );
INVX2TS U1451 ( .A(n1516), .Y(DP_OP_156J10_125_3370_n121) );
ADDHX1TS U1452 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .B(
n1163), .CO(n1164), .S(n1516) );
INVX2TS U1453 ( .A(n1513), .Y(DP_OP_156J10_125_3370_n120) );
INVX2TS U1454 ( .A(DP_OP_154J10_123_2038_n193), .Y(n1172) );
ADDHX1TS U1455 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(
n1164), .CO(n1171), .S(n1513) );
INVX2TS U1456 ( .A(n1656), .Y(DP_OP_156J10_125_3370_n119) );
ADDHX1TS U1457 ( .A(n1166), .B(n1165), .CO(n1167), .S(n1597) );
XOR2X1TS U1458 ( .A(n1167), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(n1593) );
INVX2TS U1459 ( .A(n1593), .Y(DP_OP_156J10_125_3370_n95) );
CMPR32X2TS U1460 ( .A(n1170), .B(n1169), .C(n1168), .CO(n1121), .S(n1609) );
INVX2TS U1461 ( .A(n1609), .Y(DP_OP_156J10_125_3370_n99) );
XOR2X1TS U1462 ( .A(n1173), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(n1657) );
INVX2TS U1463 ( .A(n1657), .Y(DP_OP_156J10_125_3370_n118) );
CMPR32X2TS U1464 ( .A(n1176), .B(n1175), .C(n1174), .CO(n1163), .S(n1519) );
INVX2TS U1465 ( .A(n1519), .Y(DP_OP_156J10_125_3370_n122) );
CMPR32X2TS U1466 ( .A(n1179), .B(n1178), .C(n1177), .CO(n1198), .S(n1641) );
INVX2TS U1467 ( .A(n1641), .Y(DP_OP_156J10_125_3370_n107) );
CMPR32X2TS U1468 ( .A(n1182), .B(n1181), .C(n1180), .CO(n1189), .S(n1626) );
INVX2TS U1469 ( .A(n1626), .Y(DP_OP_156J10_125_3370_n103) );
CMPR32X2TS U1470 ( .A(n1185), .B(n1184), .C(n1183), .CO(n1186), .S(n1618) );
INVX2TS U1471 ( .A(n1618), .Y(DP_OP_156J10_125_3370_n101) );
CMPR32X2TS U1472 ( .A(n1188), .B(n1187), .C(n1186), .CO(n1168), .S(n1614) );
INVX2TS U1473 ( .A(n1614), .Y(DP_OP_156J10_125_3370_n100) );
CMPR32X2TS U1474 ( .A(n1191), .B(n1190), .C(n1189), .CO(n1183), .S(n1622) );
INVX2TS U1475 ( .A(n1622), .Y(DP_OP_156J10_125_3370_n102) );
CMPR32X2TS U1476 ( .A(n1194), .B(n1193), .C(n1192), .CO(n1180), .S(n1631) );
INVX2TS U1477 ( .A(n1631), .Y(DP_OP_156J10_125_3370_n104) );
INVX2TS U1478 ( .A(n1635), .Y(DP_OP_156J10_125_3370_n105) );
CMPR32X2TS U1479 ( .A(n1200), .B(n1199), .C(n1198), .CO(n1195), .S(n1639) );
INVX2TS U1480 ( .A(n1639), .Y(DP_OP_156J10_125_3370_n106) );
CMPR32X2TS U1481 ( .A(n1203), .B(n1202), .C(n1201), .CO(n1207), .S(n1545) );
INVX2TS U1482 ( .A(n1545), .Y(DP_OP_156J10_125_3370_n130) );
CMPR32X2TS U1483 ( .A(n1206), .B(n1205), .C(n1204), .CO(n1213), .S(n1537) );
INVX2TS U1484 ( .A(n1537), .Y(DP_OP_156J10_125_3370_n128) );
CMPR32X2TS U1485 ( .A(n1209), .B(n1208), .C(n1207), .CO(n1204), .S(n1541) );
INVX2TS U1486 ( .A(n1541), .Y(DP_OP_156J10_125_3370_n129) );
CMPR32X2TS U1487 ( .A(n1212), .B(n1211), .C(n1210), .CO(n1216), .S(n1531) );
INVX2TS U1488 ( .A(n1531), .Y(DP_OP_156J10_125_3370_n126) );
CMPR32X2TS U1489 ( .A(n1215), .B(n1214), .C(n1213), .CO(n1210), .S(n1534) );
INVX2TS U1490 ( .A(n1534), .Y(DP_OP_156J10_125_3370_n127) );
CMPR32X2TS U1491 ( .A(n1218), .B(n1217), .C(n1216), .CO(n1219), .S(n1528) );
INVX2TS U1492 ( .A(n1528), .Y(DP_OP_156J10_125_3370_n125) );
CMPR32X2TS U1493 ( .A(n1221), .B(n1220), .C(n1219), .CO(n1222), .S(n1525) );
INVX2TS U1494 ( .A(n1525), .Y(DP_OP_156J10_125_3370_n124) );
CMPR32X2TS U1495 ( .A(n1224), .B(n1223), .C(n1222), .CO(n1174), .S(n1522) );
INVX2TS U1496 ( .A(n1522), .Y(DP_OP_156J10_125_3370_n123) );
CMPR32X2TS U1497 ( .A(n1227), .B(n1226), .C(n1225), .CO(n1228), .S(n1644) );
INVX2TS U1498 ( .A(n1644), .Y(DP_OP_156J10_125_3370_n109) );
CMPR32X2TS U1499 ( .A(n1230), .B(n1229), .C(n1228), .CO(n1177), .S(n1642) );
INVX2TS U1500 ( .A(n1642), .Y(DP_OP_156J10_125_3370_n108) );
CMPR32X2TS U1501 ( .A(n1233), .B(n1232), .C(n1231), .CO(n1234), .S(n1553) );
INVX2TS U1502 ( .A(n1553), .Y(DP_OP_156J10_125_3370_n132) );
CMPR32X2TS U1503 ( .A(n1236), .B(n1235), .C(n1234), .CO(n1201), .S(n1549) );
INVX2TS U1504 ( .A(n1549), .Y(DP_OP_156J10_125_3370_n131) );
CMPR32X2TS U1505 ( .A(n1239), .B(n1238), .C(n1237), .CO(n1225), .S(n1645) );
INVX2TS U1506 ( .A(n1645), .Y(DP_OP_156J10_125_3370_n110) );
CMPR32X2TS U1507 ( .A(n1242), .B(n1241), .C(n1240), .CO(n1231), .S(n1557) );
INVX2TS U1508 ( .A(n1557), .Y(DP_OP_156J10_125_3370_n133) );
INVX2TS U1509 ( .A(FS_Module_state_reg[1]), .Y(n1249) );
NOR2X1TS U1510 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n1339) );
NAND2X1TS U1511 ( .A(n1679), .B(n1339), .Y(n1243) );
NOR2X1TS U1512 ( .A(FS_Module_state_reg[1]), .B(n1243), .Y(n1244) );
OR2X1TS U1513 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
BUFX3TS U1514 ( .A(n167), .Y(n1720) );
BUFX3TS U1515 ( .A(n167), .Y(n1721) );
BUFX3TS U1516 ( .A(n1722), .Y(n1712) );
BUFX3TS U1517 ( .A(n1722), .Y(n1711) );
BUFX3TS U1518 ( .A(n1722), .Y(n1710) );
BUFX3TS U1519 ( .A(n1722), .Y(n1713) );
BUFX3TS U1520 ( .A(n1722), .Y(n1708) );
BUFX3TS U1521 ( .A(n1722), .Y(n1717) );
BUFX3TS U1522 ( .A(n1722), .Y(n1715) );
BUFX3TS U1523 ( .A(n1722), .Y(n1714) );
NOR2X1TS U1524 ( .A(n1249), .B(FS_Module_state_reg[2]), .Y(n1338) );
NOR2XLTS U1525 ( .A(FS_Module_state_reg[3]), .B(n1679), .Y(n1245) );
NAND2X1TS U1526 ( .A(n1338), .B(n1245), .Y(n1386) );
INVX2TS U1527 ( .A(n1386), .Y(n1385) );
NOR2X2TS U1528 ( .A(FS_Module_state_reg[1]), .B(n1679), .Y(n1340) );
NAND3XLTS U1529 ( .A(FS_Module_state_reg[3]), .B(n1340), .C(n1666), .Y(n1246) );
NOR2X1TS U1530 ( .A(FS_Module_state_reg[3]), .B(n1666), .Y(n1253) );
NAND2X1TS U1531 ( .A(n1340), .B(n1253), .Y(n1355) );
NOR2BX1TS U1532 ( .AN(P_Sgf[47]), .B(n1355), .Y(n1248) );
INVX2TS U1533 ( .A(n1248), .Y(n1247) );
OAI31X1TS U1534 ( .A0(n1385), .A1(n1438), .A2(n1675), .B0(n1247), .Y(n235)
);
NAND2X1TS U1535 ( .A(FS_Module_state_reg[3]), .B(n1666), .Y(n1252) );
NOR3XLTS U1536 ( .A(n1252), .B(n1249), .C(n1679), .Y(n1250) );
CLKBUFX3TS U1537 ( .A(n1250), .Y(n1665) );
XOR2X1TS U1538 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n1318) );
NOR2XLTS U1539 ( .A(n1318), .B(underflow_flag), .Y(n1251) );
OAI32X1TS U1540 ( .A0(n1662), .A1(n1251), .A2(overflow_flag), .B0(n1665),
.B1(n1707), .Y(n168) );
NOR2X2TS U1541 ( .A(FS_Module_state_reg[0]), .B(n1252), .Y(n1342) );
AOI32X2TS U1542 ( .A0(FSM_add_overflow_flag), .A1(FS_Module_state_reg[1]),
.A2(n1342), .B0(n1344), .B1(FS_Module_state_reg[1]), .Y(n1389) );
NOR2XLTS U1543 ( .A(n1389), .B(n1678), .Y(n1255) );
AOI22X1TS U1544 ( .A0(n482), .A1(n1387), .B0(n1302), .B1(n461), .Y(n1260) );
NAND2X1TS U1545 ( .A(n1254), .B(n1389), .Y(n1257) );
NOR2XLTS U1546 ( .A(FSM_selector_C), .B(n1257), .Y(n1256) );
NOR2XLTS U1547 ( .A(n1678), .B(n1257), .Y(n1258) );
AOI22X1TS U1548 ( .A0(n1308), .A1(P_Sgf[25]), .B0(n1307), .B1(Add_result[2]),
.Y(n1259) );
OAI211XLTS U1549 ( .A0(n1306), .A1(n1688), .B0(n1260), .C0(n1259), .Y(n204)
);
AOI22X1TS U1550 ( .A0(Sgf_normalized_result[0]), .A1(n1303), .B0(n1302),
.B1(n472), .Y(n1262) );
AOI22X1TS U1551 ( .A0(n1308), .A1(P_Sgf[23]), .B0(n1307), .B1(Add_result[0]),
.Y(n1261) );
OAI211XLTS U1552 ( .A0(n1306), .A1(n1690), .B0(n1262), .C0(n1261), .Y(n202)
);
AOI22X1TS U1553 ( .A0(Sgf_normalized_result[3]), .A1(n1387), .B0(n1302),
.B1(n463), .Y(n1264) );
AOI22X1TS U1554 ( .A0(n1308), .A1(P_Sgf[26]), .B0(n1307), .B1(n461), .Y(
n1263) );
OAI211XLTS U1555 ( .A0(n1306), .A1(n1687), .B0(n1264), .C0(n1263), .Y(n205)
);
AOI22X1TS U1556 ( .A0(Sgf_normalized_result[5]), .A1(n1387), .B0(n474), .B1(
n1302), .Y(n1266) );
AOI22X1TS U1557 ( .A0(n1308), .A1(P_Sgf[28]), .B0(n1307), .B1(n462), .Y(
n1265) );
OAI211XLTS U1558 ( .A0(n1306), .A1(n1706), .B0(n1266), .C0(n1265), .Y(n207)
);
AOI22X1TS U1559 ( .A0(n490), .A1(n1387), .B0(n1302), .B1(Add_result[2]), .Y(
n1268) );
AOI22X1TS U1560 ( .A0(n1308), .A1(P_Sgf[24]), .B0(n1307), .B1(n472), .Y(
n1267) );
AOI22X1TS U1561 ( .A0(Sgf_normalized_result[4]), .A1(n1387), .B0(n1302),
.B1(n462), .Y(n1270) );
AOI22X1TS U1562 ( .A0(n1308), .A1(P_Sgf[27]), .B0(n1307), .B1(n463), .Y(
n1269) );
OAI211XLTS U1563 ( .A0(n1306), .A1(n1686), .B0(n1270), .C0(n1269), .Y(n206)
);
AOI22X1TS U1564 ( .A0(Sgf_normalized_result[17]), .A1(n1387), .B0(n480),
.B1(n1302), .Y(n1272) );
AOI22X1TS U1565 ( .A0(n469), .A1(n1307), .B0(n1308), .B1(P_Sgf[40]), .Y(
n1271) );
OAI211XLTS U1566 ( .A0(n1306), .A1(n1694), .B0(n1272), .C0(n1271), .Y(n219)
);
AOI22X1TS U1567 ( .A0(Sgf_normalized_result[7]), .A1(n1387), .B0(n475), .B1(
n1302), .Y(n1274) );
AOI22X1TS U1568 ( .A0(n464), .A1(n1307), .B0(n1308), .B1(P_Sgf[30]), .Y(
n1273) );
OAI211XLTS U1569 ( .A0(n1306), .A1(n1704), .B0(n1274), .C0(n1273), .Y(n209)
);
AOI22X1TS U1570 ( .A0(Sgf_normalized_result[21]), .A1(n1303), .B0(n473),
.B1(n1302), .Y(n1276) );
AOI22X1TS U1571 ( .A0(n471), .A1(n1307), .B0(n1308), .B1(P_Sgf[44]), .Y(
n1275) );
OAI211XLTS U1572 ( .A0(n1691), .A1(n1306), .B0(n1276), .C0(n1275), .Y(n223)
);
AOI22X1TS U1573 ( .A0(Sgf_normalized_result[19]), .A1(n1303), .B0(n481),
.B1(n1302), .Y(n1278) );
AOI22X1TS U1574 ( .A0(n470), .A1(n1307), .B0(n1308), .B1(P_Sgf[42]), .Y(
n1277) );
OAI211XLTS U1575 ( .A0(n1306), .A1(n1692), .B0(n1278), .C0(n1277), .Y(n221)
);
AOI22X1TS U1576 ( .A0(Sgf_normalized_result[9]), .A1(n1387), .B0(n476), .B1(
n1302), .Y(n1280) );
AOI22X1TS U1577 ( .A0(n465), .A1(n1307), .B0(n1308), .B1(P_Sgf[32]), .Y(
n1279) );
OAI211XLTS U1578 ( .A0(n1306), .A1(n1702), .B0(n1280), .C0(n1279), .Y(n211)
);
AOI22X1TS U1579 ( .A0(Sgf_normalized_result[11]), .A1(n1303), .B0(n477),
.B1(n1302), .Y(n1282) );
AOI22X1TS U1580 ( .A0(n466), .A1(n1307), .B0(n1308), .B1(P_Sgf[34]), .Y(
n1281) );
OAI211XLTS U1581 ( .A0(n1306), .A1(n1700), .B0(n1282), .C0(n1281), .Y(n213)
);
AOI22X1TS U1582 ( .A0(Sgf_normalized_result[15]), .A1(n1303), .B0(n479),
.B1(n1302), .Y(n1284) );
AOI22X1TS U1583 ( .A0(n468), .A1(n1307), .B0(n1308), .B1(P_Sgf[38]), .Y(
n1283) );
OAI211XLTS U1584 ( .A0(n1306), .A1(n1696), .B0(n1284), .C0(n1283), .Y(n217)
);
AOI22X1TS U1585 ( .A0(Sgf_normalized_result[13]), .A1(n1303), .B0(n478),
.B1(n1302), .Y(n1286) );
AOI22X1TS U1586 ( .A0(n467), .A1(n1307), .B0(n1308), .B1(P_Sgf[36]), .Y(
n1285) );
OAI211XLTS U1587 ( .A0(n1306), .A1(n1698), .B0(n1286), .C0(n1285), .Y(n215)
);
AOI22X1TS U1588 ( .A0(Sgf_normalized_result[10]), .A1(n1387), .B0(n466),
.B1(n1302), .Y(n1288) );
AOI22X1TS U1589 ( .A0(n476), .A1(n1307), .B0(n1308), .B1(P_Sgf[33]), .Y(
n1287) );
OAI211XLTS U1590 ( .A0(n1306), .A1(n1701), .B0(n1288), .C0(n1287), .Y(n212)
);
AOI22X1TS U1591 ( .A0(Sgf_normalized_result[6]), .A1(n1387), .B0(n464), .B1(
n1302), .Y(n1290) );
AOI22X1TS U1592 ( .A0(n474), .A1(n1307), .B0(n1308), .B1(P_Sgf[29]), .Y(
n1289) );
OAI211XLTS U1593 ( .A0(n1306), .A1(n1705), .B0(n1290), .C0(n1289), .Y(n208)
);
AOI22X1TS U1594 ( .A0(Sgf_normalized_result[20]), .A1(n1303), .B0(n471),
.B1(n1302), .Y(n1292) );
AOI22X1TS U1595 ( .A0(n481), .A1(n1307), .B0(n1308), .B1(P_Sgf[43]), .Y(
n1291) );
OAI211XLTS U1596 ( .A0(n1685), .A1(n1306), .B0(n1292), .C0(n1291), .Y(n222)
);
AOI22X1TS U1597 ( .A0(Sgf_normalized_result[12]), .A1(n1303), .B0(n467),
.B1(n1302), .Y(n1294) );
AOI22X1TS U1598 ( .A0(n477), .A1(n1307), .B0(n1308), .B1(P_Sgf[35]), .Y(
n1293) );
OAI211XLTS U1599 ( .A0(n1306), .A1(n1699), .B0(n1294), .C0(n1293), .Y(n214)
);
AOI22X1TS U1600 ( .A0(Sgf_normalized_result[8]), .A1(n1387), .B0(n465), .B1(
n1302), .Y(n1296) );
AOI22X1TS U1601 ( .A0(n475), .A1(n1307), .B0(n1308), .B1(P_Sgf[31]), .Y(
n1295) );
OAI211XLTS U1602 ( .A0(n1306), .A1(n1703), .B0(n1296), .C0(n1295), .Y(n210)
);
AOI22X1TS U1603 ( .A0(Sgf_normalized_result[16]), .A1(n1303), .B0(n469),
.B1(n1302), .Y(n1299) );
AOI22X1TS U1604 ( .A0(n479), .A1(n1307), .B0(n1308), .B1(P_Sgf[39]), .Y(
n1298) );
OAI211XLTS U1605 ( .A0(n1306), .A1(n1695), .B0(n1299), .C0(n1298), .Y(n218)
);
AOI22X1TS U1606 ( .A0(Sgf_normalized_result[14]), .A1(n1303), .B0(n468),
.B1(n1302), .Y(n1301) );
AOI22X1TS U1607 ( .A0(n478), .A1(n1307), .B0(n1308), .B1(P_Sgf[37]), .Y(
n1300) );
OAI211XLTS U1608 ( .A0(n1306), .A1(n1697), .B0(n1301), .C0(n1300), .Y(n216)
);
AOI22X1TS U1609 ( .A0(Sgf_normalized_result[18]), .A1(n1303), .B0(n470),
.B1(n1302), .Y(n1305) );
AOI22X1TS U1610 ( .A0(n480), .A1(n1307), .B0(n1308), .B1(P_Sgf[41]), .Y(
n1304) );
OAI211XLTS U1611 ( .A0(n1306), .A1(n1693), .B0(n1305), .C0(n1304), .Y(n220)
);
AOI22X1TS U1612 ( .A0(FSM_selector_C), .A1(Add_result[23]), .B0(P_Sgf[46]),
.B1(n1678), .Y(n1388) );
AOI22X1TS U1613 ( .A0(Sgf_normalized_result[22]), .A1(n1387), .B0(n473),
.B1(n1307), .Y(n1310) );
NAND2X1TS U1614 ( .A(n1308), .B(P_Sgf[45]), .Y(n1309) );
OAI211XLTS U1615 ( .A0(n1389), .A1(n1388), .B0(n1310), .C0(n1309), .Y(n224)
);
INVX2TS U1616 ( .A(n1342), .Y(n1321) );
NOR4X1TS U1617 ( .A(P_Sgf[14]), .B(P_Sgf[15]), .C(P_Sgf[16]), .D(P_Sgf[17]),
.Y(n1317) );
NOR4X1TS U1618 ( .A(P_Sgf[18]), .B(P_Sgf[19]), .C(P_Sgf[20]), .D(P_Sgf[21]),
.Y(n1316) );
NOR4X1TS U1619 ( .A(P_Sgf[2]), .B(P_Sgf[3]), .C(P_Sgf[4]), .D(P_Sgf[5]), .Y(
n1314) );
NOR3XLTS U1620 ( .A(P_Sgf[22]), .B(P_Sgf[0]), .C(P_Sgf[1]), .Y(n1313) );
NOR4X1TS U1621 ( .A(P_Sgf[10]), .B(P_Sgf[11]), .C(P_Sgf[12]), .D(P_Sgf[13]),
.Y(n1312) );
AND4X1TS U1622 ( .A(n1314), .B(n1313), .C(n1312), .D(n1311), .Y(n1315) );
NAND3XLTS U1623 ( .A(n1317), .B(n1316), .C(n1315), .Y(n1320) );
MXI2X1TS U1624 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n1318), .Y(n1319)
);
OAI211X1TS U1625 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n1320), .C0(
n1319), .Y(n1335) );
OAI31X1TS U1626 ( .A0(FS_Module_state_reg[1]), .A1(n1321), .A2(n1335), .B0(
n1678), .Y(n375) );
NAND2X1TS U1627 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n1336) );
NOR3X1TS U1628 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1336), .Y(ready) );
AOI22X1TS U1629 ( .A0(DP_OP_36J10_126_4699_n33), .A1(n430), .B0(n1666), .B1(
n1679), .Y(n1323) );
INVX2TS U1630 ( .A(ready), .Y(n1322) );
OAI22X1TS U1631 ( .A0(n1323), .A1(n1353), .B0(P_Sgf[47]), .B1(n1355), .Y(
n379) );
INVX2TS U1632 ( .A(DP_OP_36J10_126_4699_n33), .Y(n1356) );
OAI21XLTS U1633 ( .A0(n1666), .A1(n1353), .B0(FS_Module_state_reg[3]), .Y(
n1324) );
OAI211XLTS U1634 ( .A0(n430), .A1(n1356), .B0(n1303), .C0(n1324), .Y(n380)
);
NOR3BX1TS U1635 ( .AN(n460), .B(FSM_selector_B[0]), .C(FSM_selector_B[1]),
.Y(n1325) );
XOR2X1TS U1636 ( .A(DP_OP_36J10_126_4699_n33), .B(n1325), .Y(
DP_OP_36J10_126_4699_n15) );
OR2X2TS U1637 ( .A(FSM_selector_B[1]), .B(n1674), .Y(n1332) );
OAI2BB1X1TS U1638 ( .A0N(n453), .A1N(n1675), .B0(n1332), .Y(n1326) );
XOR2X1TS U1639 ( .A(DP_OP_36J10_126_4699_n33), .B(n1326), .Y(
DP_OP_36J10_126_4699_n16) );
OAI2BB1X1TS U1640 ( .A0N(n454), .A1N(n1675), .B0(n1332), .Y(n1327) );
XOR2X1TS U1641 ( .A(DP_OP_36J10_126_4699_n33), .B(n1327), .Y(
DP_OP_36J10_126_4699_n17) );
OAI2BB1X1TS U1642 ( .A0N(Op_MY[27]), .A1N(n1675), .B0(n1332), .Y(n1328) );
XOR2X1TS U1643 ( .A(DP_OP_36J10_126_4699_n33), .B(n1328), .Y(
DP_OP_36J10_126_4699_n18) );
OAI2BB1X1TS U1644 ( .A0N(n459), .A1N(n1675), .B0(n1332), .Y(n1329) );
XOR2X1TS U1645 ( .A(DP_OP_36J10_126_4699_n33), .B(n1329), .Y(
DP_OP_36J10_126_4699_n19) );
OAI2BB1X1TS U1646 ( .A0N(n458), .A1N(n1675), .B0(n1332), .Y(n1330) );
XOR2X1TS U1647 ( .A(DP_OP_36J10_126_4699_n33), .B(n1330), .Y(
DP_OP_36J10_126_4699_n20) );
OAI2BB1X1TS U1648 ( .A0N(n455), .A1N(n1675), .B0(n1332), .Y(n1331) );
XOR2X1TS U1649 ( .A(DP_OP_36J10_126_4699_n33), .B(n1331), .Y(
DP_OP_36J10_126_4699_n21) );
NOR2XLTS U1650 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1333) );
OAI21XLTS U1651 ( .A0(FSM_selector_B[0]), .A1(n1333), .B0(n1332), .Y(n1334)
);
XOR2X1TS U1652 ( .A(DP_OP_36J10_126_4699_n33), .B(n1334), .Y(
DP_OP_36J10_126_4699_n22) );
AOI22X1TS U1653 ( .A0(n1340), .A1(n1336), .B0(n1342), .B1(n1335), .Y(n1337)
);
OAI2BB1X1TS U1654 ( .A0N(n1338), .A1N(n1679), .B0(n1337), .Y(n378) );
AO22XLTS U1655 ( .A0(Data_MY[26]), .A1(n1363), .B0(n1352), .B1(n459), .Y(
n338) );
AO22XLTS U1656 ( .A0(Data_MY[25]), .A1(n1363), .B0(n1352), .B1(n458), .Y(
n337) );
AO22XLTS U1657 ( .A0(Data_MY[30]), .A1(n1363), .B0(n1352), .B1(n460), .Y(
n342) );
AO22XLTS U1658 ( .A0(Data_MY[24]), .A1(n1363), .B0(n1352), .B1(n455), .Y(
n336) );
AO22XLTS U1659 ( .A0(Data_MY[29]), .A1(n1363), .B0(n1352), .B1(n453), .Y(
n341) );
AO22XLTS U1660 ( .A0(Data_MY[28]), .A1(n1341), .B0(n1352), .B1(n454), .Y(
n340) );
BUFX3TS U1661 ( .A(n1352), .Y(n1359) );
MX2X1TS U1662 ( .A(Op_MY[23]), .B(Data_MY[23]), .S0(n1363), .Y(n335) );
NAND2X1TS U1663 ( .A(n1386), .B(n1681), .Y(n376) );
NOR2BX1TS U1664 ( .AN(exp_oper_result[8]), .B(n1681), .Y(S_Oper_A_exp[8]) );
BUFX3TS U1665 ( .A(n1660), .Y(n1654) );
MX2X1TS U1666 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n1345),
.Y(n227) );
MX2X1TS U1667 ( .A(n456), .B(exp_oper_result[7]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[7]) );
MX2X1TS U1668 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n1345),
.Y(n228) );
MX2X1TS U1669 ( .A(n457), .B(exp_oper_result[6]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[6]) );
MX2X1TS U1670 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n1345),
.Y(n229) );
MX2X1TS U1671 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
MX2X1TS U1672 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n1345),
.Y(n230) );
MX2X1TS U1673 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
MX2X1TS U1674 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n1345),
.Y(n231) );
MX2X1TS U1675 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U1676 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n1345),
.Y(n232) );
MX2X1TS U1677 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
MX2X1TS U1678 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n1345),
.Y(n233) );
MX2X1TS U1679 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
MX2X1TS U1680 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n1345),
.Y(n234) );
MX2X1TS U1681 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
MX2X1TS U1682 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n1345),
.Y(n226) );
XNOR2X1TS U1683 ( .A(DP_OP_36J10_126_4699_n1), .B(n1356), .Y(n1347) );
CLKINVX6TS U1684 ( .A(n1660), .Y(n1661) );
MX2X1TS U1685 ( .A(n1347), .B(Exp_module_Overflow_flag_A), .S0(n1661), .Y(
n225) );
NAND4XLTS U1686 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n1348) );
NAND4BXLTS U1687 ( .AN(n1348), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n1349) );
NAND3BXLTS U1688 ( .AN(Exp_module_Data_S[7]), .B(n1385), .C(n1349), .Y(n1350) );
OAI22X1TS U1689 ( .A0(Exp_module_Data_S[8]), .A1(n1350), .B0(n1385), .B1(
n1682), .Y(n201) );
CLKINVX6TS U1690 ( .A(n1352), .Y(n1363) );
AO22XLTS U1691 ( .A0(n1363), .A1(Data_MY[31]), .B0(n1352), .B1(Op_MY[31]),
.Y(n381) );
AOI32X1TS U1692 ( .A0(FS_Module_state_reg[1]), .A1(n1666), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n1353), .Y(
n1357) );
NAND3XLTS U1693 ( .A(n1357), .B(n1356), .C(n1355), .Y(n377) );
BUFX3TS U1694 ( .A(n1352), .Y(n1362) );
BUFX3TS U1695 ( .A(n1352), .Y(n1358) );
AO22XLTS U1696 ( .A0(n1363), .A1(Data_MX[31]), .B0(n1358), .B1(Op_MX[31]),
.Y(n343) );
BUFX3TS U1697 ( .A(n1352), .Y(n1360) );
NOR4X1TS U1698 ( .A(n459), .B(n458), .C(n460), .D(n455), .Y(n1365) );
NAND4XLTS U1699 ( .A(n1367), .B(n1366), .C(n1365), .D(n1364), .Y(n1383) );
NAND4XLTS U1700 ( .A(n1371), .B(n1370), .C(n1369), .D(n1368), .Y(n1382) );
NOR4X1TS U1701 ( .A(Op_MX[18]), .B(Op_MX[19]), .C(Op_MX[20]), .D(Op_MX[21]),
.Y(n1375) );
NAND4XLTS U1702 ( .A(n1375), .B(n1374), .C(n1373), .D(n1372), .Y(n1381) );
NAND4XLTS U1703 ( .A(n1379), .B(n1378), .C(n1377), .D(n1376), .Y(n1380) );
OAI22X1TS U1704 ( .A0(n1383), .A1(n1382), .B0(n1381), .B1(n1380), .Y(n1384)
);
AO22XLTS U1705 ( .A0(n1386), .A1(zero_flag), .B0(n1385), .B1(n1384), .Y(n311) );
AOI32X1TS U1706 ( .A0(n1389), .A1(n1254), .A2(n1388), .B0(n1684), .B1(n1303),
.Y(n310) );
AOI2BB2XLTS U1707 ( .B0(n1438), .B1(Sgf_normalized_result[0]), .A0N(
Add_result[0]), .A1N(n1428), .Y(n309) );
NOR2XLTS U1708 ( .A(n490), .B(Sgf_normalized_result[0]), .Y(n1390) );
AOI21X1TS U1709 ( .A0(Sgf_normalized_result[0]), .A1(n490), .B0(n1390), .Y(
n1391) );
AOI2BB2XLTS U1710 ( .B0(n1438), .B1(n1391), .A0N(n472), .A1N(n1428), .Y(n308) );
OR3X1TS U1711 ( .A(n482), .B(n490), .C(Sgf_normalized_result[0]), .Y(n1393)
);
OAI21XLTS U1712 ( .A0(n490), .A1(Sgf_normalized_result[0]), .B0(n482), .Y(
n1392) );
AOI32X1TS U1713 ( .A0(n1393), .A1(n1438), .A2(n1392), .B0(n1683), .B1(n1436),
.Y(n307) );
BUFX4TS U1714 ( .A(n1436), .Y(n1433) );
NAND2X1TS U1715 ( .A(Sgf_normalized_result[3]), .B(n1393), .Y(n1395) );
OAI2BB1X1TS U1716 ( .A0N(n461), .A1N(n1433), .B0(n1394), .Y(n306) );
NAND2X1TS U1717 ( .A(n1667), .B(n1395), .Y(n1397) );
OAI21XLTS U1718 ( .A0(n1395), .A1(n1667), .B0(n1397), .Y(n1396) );
NAND2X1TS U1719 ( .A(Sgf_normalized_result[5]), .B(n1397), .Y(n1399) );
OAI2BB1X1TS U1720 ( .A0N(n462), .A1N(n1433), .B0(n1398), .Y(n304) );
AOI21X1TS U1721 ( .A0(n1668), .A1(n1399), .B0(n1401), .Y(n1400) );
NAND2X1TS U1722 ( .A(Sgf_normalized_result[7]), .B(n1401), .Y(n1403) );
OAI211XLTS U1723 ( .A0(Sgf_normalized_result[7]), .A1(n1401), .B0(n1428),
.C0(n1403), .Y(n1402) );
OAI2BB1X1TS U1724 ( .A0N(n464), .A1N(n1433), .B0(n1402), .Y(n302) );
AOI21X1TS U1725 ( .A0(n1669), .A1(n1403), .B0(n452), .Y(n1404) );
NAND2X1TS U1726 ( .A(Sgf_normalized_result[9]), .B(n452), .Y(n1406) );
OAI211XLTS U1727 ( .A0(Sgf_normalized_result[9]), .A1(n452), .B0(n1428),
.C0(n1406), .Y(n1405) );
OAI2BB1X1TS U1728 ( .A0N(n465), .A1N(n1433), .B0(n1405), .Y(n300) );
AOI21X1TS U1729 ( .A0(n1670), .A1(n1406), .B0(n1408), .Y(n1407) );
NAND2X1TS U1730 ( .A(Sgf_normalized_result[11]), .B(n1408), .Y(n1410) );
OAI211XLTS U1731 ( .A0(Sgf_normalized_result[11]), .A1(n1408), .B0(n1428),
.C0(n1410), .Y(n1409) );
OAI2BB1X1TS U1732 ( .A0N(n466), .A1N(n1433), .B0(n1409), .Y(n298) );
AOI21X1TS U1733 ( .A0(n1671), .A1(n1410), .B0(n1412), .Y(n1411) );
NAND2X1TS U1734 ( .A(Sgf_normalized_result[13]), .B(n1412), .Y(n1414) );
OAI211XLTS U1735 ( .A0(Sgf_normalized_result[13]), .A1(n1412), .B0(n1428),
.C0(n1414), .Y(n1413) );
OAI2BB1X1TS U1736 ( .A0N(n467), .A1N(n1433), .B0(n1413), .Y(n296) );
AOI21X1TS U1737 ( .A0(n1672), .A1(n1414), .B0(n1416), .Y(n1415) );
NAND2X1TS U1738 ( .A(Sgf_normalized_result[15]), .B(n1416), .Y(n1418) );
OAI2BB1X1TS U1739 ( .A0N(n468), .A1N(n1433), .B0(n1417), .Y(n294) );
AOI21X1TS U1740 ( .A0(n1673), .A1(n1418), .B0(n1420), .Y(n1419) );
NAND2X1TS U1741 ( .A(Sgf_normalized_result[17]), .B(n1420), .Y(n1422) );
OAI211XLTS U1742 ( .A0(Sgf_normalized_result[17]), .A1(n1420), .B0(n1428),
.C0(n1422), .Y(n1421) );
OAI2BB1X1TS U1743 ( .A0N(n469), .A1N(n1433), .B0(n1421), .Y(n292) );
AOI21X1TS U1744 ( .A0(n1676), .A1(n1422), .B0(n1424), .Y(n1423) );
NAND2X1TS U1745 ( .A(Sgf_normalized_result[19]), .B(n1424), .Y(n1426) );
OAI211XLTS U1746 ( .A0(Sgf_normalized_result[19]), .A1(n1424), .B0(n1428),
.C0(n1426), .Y(n1425) );
OAI2BB1X1TS U1747 ( .A0N(n470), .A1N(n1433), .B0(n1425), .Y(n290) );
AOI21X1TS U1748 ( .A0(n1677), .A1(n1426), .B0(n1429), .Y(n1427) );
NAND2X1TS U1749 ( .A(Sgf_normalized_result[21]), .B(n1429), .Y(n1431) );
OAI211XLTS U1750 ( .A0(Sgf_normalized_result[21]), .A1(n1429), .B0(n1428),
.C0(n1431), .Y(n1430) );
OAI2BB1X1TS U1751 ( .A0N(n471), .A1N(n1433), .B0(n1430), .Y(n288) );
AOI211XLTS U1752 ( .A0(n1680), .A1(n1431), .B0(n1434), .C0(n1436), .Y(n1432)
);
AO21XLTS U1753 ( .A0(n473), .A1(n1433), .B0(n1432), .Y(n287) );
AOI21X1TS U1754 ( .A0(n1434), .A1(Sgf_normalized_result[23]), .B0(n1436),
.Y(n1437) );
OAI21XLTS U1755 ( .A0(n1434), .A1(Sgf_normalized_result[23]), .B0(n1437),
.Y(n1435) );
OAI2BB1X1TS U1756 ( .A0N(Add_result[23]), .A1N(n1436), .B0(n1435), .Y(n286)
);
AOI2BB1XLTS U1757 ( .A0N(n1428), .A1N(FSM_add_overflow_flag), .B0(n1437),
.Y(n285) );
CMPR32X2TS U1758 ( .A(n1441), .B(n1440), .C(n1439), .CO(n570), .S(n1448) );
CMPR32X2TS U1759 ( .A(n1444), .B(n1443), .C(n1442), .CO(n1237), .S(n1646) );
INVX2TS U1760 ( .A(n1646), .Y(n1452) );
CMPR32X2TS U1761 ( .A(n1447), .B(n1446), .C(n1445), .CO(n1240), .S(n1561) );
INVX2TS U1762 ( .A(n1561), .Y(n1451) );
ADDHXLTS U1763 ( .A(n1449), .B(n1448), .CO(DP_OP_156J10_125_3370_n81), .S(
n1450) );
CMPR32X2TS U1764 ( .A(n1452), .B(n1451), .C(n1450), .CO(n1489), .S(n1492) );
ADDHX1TS U1765 ( .A(n1454), .B(n1453), .CO(n1445), .S(n1565) );
INVX2TS U1766 ( .A(n1565), .Y(n1459) );
ADDHX1TS U1767 ( .A(n1456), .B(n1455), .CO(n1442), .S(n1647) );
INVX2TS U1768 ( .A(n1647), .Y(n1457) );
CMPR32X2TS U1769 ( .A(n1459), .B(n1458), .C(n1457), .CO(n1491), .S(n1495) );
CMPR32X2TS U1770 ( .A(n825), .B(n1460), .C(n955), .CO(n1494), .S(n1498) );
CMPR32X2TS U1771 ( .A(n827), .B(n1461), .C(n957), .CO(n1497), .S(n1501) );
CMPR32X2TS U1772 ( .A(DP_OP_154J10_123_2038_n86), .B(n1462), .C(
DP_OP_155J10_124_2038_n86), .CO(n1500), .S(n1504) );
CMPR32X2TS U1773 ( .A(DP_OP_154J10_123_2038_n87), .B(n1463), .C(
DP_OP_155J10_124_2038_n87), .CO(n1503), .S(n1507) );
NAND2BXLTS U1774 ( .AN(n1465), .B(n1585), .Y(n1506) );
INVX2TS U1775 ( .A(n1464), .Y(n1653) );
XOR2X1TS U1776 ( .A(n1465), .B(n1585), .Y(n1508) );
ADDHXLTS U1777 ( .A(n1466), .B(DP_OP_156J10_125_3370_n31), .CO(n1467), .S(
n1472) );
XNOR2X1TS U1778 ( .A(n1468), .B(n1467), .Y(n1469) );
XOR2X1TS U1779 ( .A(n1470), .B(n1469), .Y(n1538) );
CMPR32X2TS U1780 ( .A(n1472), .B(DP_OP_156J10_125_3370_n32), .C(n1471), .CO(
n1468), .S(n1542) );
CMPR32X2TS U1781 ( .A(DP_OP_156J10_125_3370_n33), .B(
DP_OP_156J10_125_3370_n35), .C(n1473), .CO(n1471), .S(n1546) );
CMPR32X2TS U1782 ( .A(DP_OP_156J10_125_3370_n36), .B(
DP_OP_156J10_125_3370_n38), .C(n1474), .CO(n1473), .S(n1550) );
CMPR32X2TS U1783 ( .A(DP_OP_156J10_125_3370_n39), .B(
DP_OP_156J10_125_3370_n41), .C(n1475), .CO(n1474), .S(n1554) );
CMPR32X2TS U1784 ( .A(DP_OP_156J10_125_3370_n42), .B(
DP_OP_156J10_125_3370_n44), .C(n1476), .CO(n1475), .S(n1558) );
CMPR32X2TS U1785 ( .A(DP_OP_156J10_125_3370_n45), .B(
DP_OP_156J10_125_3370_n47), .C(n1477), .CO(n1476), .S(n1562) );
CMPR32X2TS U1786 ( .A(DP_OP_156J10_125_3370_n48), .B(
DP_OP_156J10_125_3370_n50), .C(n1478), .CO(n1477), .S(n1566) );
CMPR32X2TS U1787 ( .A(DP_OP_156J10_125_3370_n51), .B(
DP_OP_156J10_125_3370_n53), .C(n1479), .CO(n1478), .S(n1570) );
CMPR32X2TS U1788 ( .A(DP_OP_156J10_125_3370_n54), .B(
DP_OP_156J10_125_3370_n56), .C(n1480), .CO(n1479), .S(n1574) );
CMPR32X2TS U1789 ( .A(DP_OP_156J10_125_3370_n57), .B(
DP_OP_156J10_125_3370_n59), .C(n1481), .CO(n1480), .S(n1578) );
CMPR32X2TS U1790 ( .A(DP_OP_156J10_125_3370_n60), .B(
DP_OP_156J10_125_3370_n62), .C(n1482), .CO(n1481), .S(n1582) );
CMPR32X2TS U1791 ( .A(DP_OP_156J10_125_3370_n63), .B(
DP_OP_156J10_125_3370_n65), .C(n1483), .CO(n1482), .S(n1586) );
CMPR32X2TS U1792 ( .A(DP_OP_156J10_125_3370_n66), .B(
DP_OP_156J10_125_3370_n68), .C(n1484), .CO(n1483), .S(n1590) );
CMPR32X2TS U1793 ( .A(DP_OP_156J10_125_3370_n69), .B(
DP_OP_156J10_125_3370_n71), .C(n1485), .CO(n1484), .S(n1594) );
CMPR32X2TS U1794 ( .A(DP_OP_156J10_125_3370_n72), .B(
DP_OP_156J10_125_3370_n74), .C(n1486), .CO(n1485), .S(n1598) );
CMPR32X2TS U1795 ( .A(DP_OP_156J10_125_3370_n75), .B(
DP_OP_156J10_125_3370_n77), .C(n1487), .CO(n1486), .S(n1602) );
CMPR32X2TS U1796 ( .A(DP_OP_156J10_125_3370_n78), .B(n1489), .C(n1488), .CO(
n1487), .S(n1606) );
CMPR32X2TS U1797 ( .A(n1492), .B(n1491), .C(n1490), .CO(n1488), .S(n1610) );
CMPR32X2TS U1798 ( .A(n1495), .B(n1494), .C(n1493), .CO(n1490), .S(n1615) );
CMPR32X2TS U1799 ( .A(n1498), .B(n1497), .C(n1496), .CO(n1493), .S(n1619) );
CMPR32X2TS U1800 ( .A(n1501), .B(n1500), .C(n1499), .CO(n1496), .S(n1623) );
CMPR32X2TS U1801 ( .A(n1504), .B(n1503), .C(n1502), .CO(n1499), .S(n1627) );
CMPR32X2TS U1802 ( .A(n1507), .B(n1506), .C(n1505), .CO(n1502), .S(n1632) );
CMPR32X2TS U1803 ( .A(n1509), .B(n1097), .C(n1508), .CO(n1505), .S(n1636) );
CMPR32X2TS U1804 ( .A(n1161), .B(n1510), .C(n1464), .CO(n1509), .S(n1638) );
BUFX3TS U1805 ( .A(n1660), .Y(n1612) );
ADDHXLTS U1806 ( .A(n1513), .B(n1512), .CO(n1655), .S(n1514) );
BUFX3TS U1807 ( .A(n1660), .Y(n1643) );
ADDHXLTS U1808 ( .A(n1516), .B(n1515), .CO(n1512), .S(n1517) );
ADDHXLTS U1809 ( .A(n1519), .B(n1518), .CO(n1515), .S(n1520) );
ADDHXLTS U1810 ( .A(n1522), .B(n1521), .CO(n1518), .S(n1523) );
ADDHXLTS U1811 ( .A(n1525), .B(n1524), .CO(n1521), .S(n1526) );
ADDHXLTS U1812 ( .A(n1528), .B(n1527), .CO(n1524), .S(n1529) );
ADDHXLTS U1813 ( .A(n1531), .B(n1530), .CO(n1527), .S(n1532) );
ADDHXLTS U1814 ( .A(n1534), .B(n1533), .CO(n1530), .S(n1535) );
CMPR32X2TS U1815 ( .A(n1538), .B(n1537), .C(n1536), .CO(n1533), .S(n1539) );
CMPR32X2TS U1816 ( .A(n1542), .B(n1541), .C(n1540), .CO(n1536), .S(n1543) );
CMPR32X2TS U1817 ( .A(n1546), .B(n1545), .C(n1544), .CO(n1540), .S(n1547) );
CMPR32X2TS U1818 ( .A(n1550), .B(n1549), .C(n1548), .CO(n1544), .S(n1551) );
CMPR32X2TS U1819 ( .A(n1554), .B(n1553), .C(n1552), .CO(n1548), .S(n1555) );
CMPR32X2TS U1820 ( .A(n1558), .B(n1557), .C(n1556), .CO(n1552), .S(n1559) );
CMPR32X2TS U1821 ( .A(n1562), .B(n1561), .C(n1560), .CO(n1556), .S(n1563) );
CMPR32X2TS U1822 ( .A(n1566), .B(n1565), .C(n1564), .CO(n1560), .S(n1567) );
CMPR32X2TS U1823 ( .A(n1570), .B(n1569), .C(n1568), .CO(n1564), .S(n1571) );
CMPR32X2TS U1824 ( .A(n1574), .B(n1573), .C(n1572), .CO(n1568), .S(n1575) );
CMPR32X2TS U1825 ( .A(n1578), .B(n1577), .C(n1576), .CO(n1572), .S(n1579) );
CMPR32X2TS U1826 ( .A(n1582), .B(n1581), .C(n1580), .CO(n1576), .S(n1583) );
CMPR32X2TS U1827 ( .A(n1590), .B(n1589), .C(n1588), .CO(n1584), .S(n1591) );
CMPR32X2TS U1828 ( .A(n1594), .B(n1593), .C(n1592), .CO(n1588), .S(n1595) );
AO22XLTS U1829 ( .A0(n1629), .A1(P_Sgf[23]), .B0(n1643), .B1(n1595), .Y(n261) );
CMPR32X2TS U1830 ( .A(n1598), .B(n1597), .C(n1596), .CO(n1592), .S(n1599) );
AO22XLTS U1831 ( .A0(n1629), .A1(P_Sgf[22]), .B0(n1643), .B1(n1599), .Y(n260) );
CMPR32X2TS U1832 ( .A(n1602), .B(n1601), .C(n1600), .CO(n1596), .S(n1603) );
AO22XLTS U1833 ( .A0(n1629), .A1(P_Sgf[21]), .B0(n1643), .B1(n1603), .Y(n259) );
CMPR32X2TS U1834 ( .A(n1606), .B(n1605), .C(n1604), .CO(n1600), .S(n1607) );
AO22XLTS U1835 ( .A0(n1629), .A1(P_Sgf[20]), .B0(n1643), .B1(n1607), .Y(n258) );
CMPR32X2TS U1836 ( .A(n1610), .B(n1609), .C(n1608), .CO(n1604), .S(n1611) );
AO22XLTS U1837 ( .A0(n1629), .A1(P_Sgf[19]), .B0(n1612), .B1(n1611), .Y(n257) );
CMPR32X2TS U1838 ( .A(n1615), .B(n1614), .C(n1613), .CO(n1608), .S(n1616) );
AO22XLTS U1839 ( .A0(n1629), .A1(P_Sgf[18]), .B0(n1660), .B1(n1616), .Y(n256) );
CMPR32X2TS U1840 ( .A(n1619), .B(n1618), .C(n1617), .CO(n1613), .S(n1620) );
AO22XLTS U1841 ( .A0(n1629), .A1(P_Sgf[17]), .B0(n1660), .B1(n1620), .Y(n255) );
CMPR32X2TS U1842 ( .A(n1623), .B(n1622), .C(n1621), .CO(n1617), .S(n1624) );
AO22XLTS U1843 ( .A0(n1629), .A1(P_Sgf[16]), .B0(n1660), .B1(n1624), .Y(n254) );
CMPR32X2TS U1844 ( .A(n1627), .B(n1626), .C(n1625), .CO(n1621), .S(n1628) );
AO22XLTS U1845 ( .A0(n1629), .A1(P_Sgf[15]), .B0(n1660), .B1(n1628), .Y(n253) );
CMPR32X2TS U1846 ( .A(n1632), .B(n1631), .C(n1630), .CO(n1625), .S(n1633) );
AO22XLTS U1847 ( .A0(n1661), .A1(P_Sgf[14]), .B0(n1660), .B1(n1633), .Y(n252) );
CMPR32X2TS U1848 ( .A(n1636), .B(n1635), .C(n1634), .CO(n1630), .S(n1637) );
AO22XLTS U1849 ( .A0(n1661), .A1(P_Sgf[13]), .B0(n1654), .B1(n1637), .Y(n251) );
ADDHXLTS U1850 ( .A(n1639), .B(n1638), .CO(n1634), .S(n1640) );
AO22XLTS U1851 ( .A0(n1661), .A1(P_Sgf[12]), .B0(n1660), .B1(n1640), .Y(n250) );
AO22XLTS U1852 ( .A0(n1661), .A1(P_Sgf[11]), .B0(n1654), .B1(n1641), .Y(n249) );
AO22XLTS U1853 ( .A0(n1661), .A1(P_Sgf[10]), .B0(n1643), .B1(n1642), .Y(n248) );
AO22XLTS U1854 ( .A0(n1661), .A1(P_Sgf[9]), .B0(n1654), .B1(n1644), .Y(n247)
);
AO22XLTS U1855 ( .A0(n1661), .A1(P_Sgf[8]), .B0(n1654), .B1(n1645), .Y(n246)
);
AO22XLTS U1856 ( .A0(n1661), .A1(P_Sgf[7]), .B0(n1654), .B1(n1646), .Y(n245)
);
AO22XLTS U1857 ( .A0(n1661), .A1(P_Sgf[6]), .B0(n1654), .B1(n1647), .Y(n244)
);
AO22XLTS U1858 ( .A0(n1661), .A1(P_Sgf[5]), .B0(n1654), .B1(n1648), .Y(n243)
);
AO22XLTS U1859 ( .A0(n1661), .A1(P_Sgf[4]), .B0(n1654), .B1(n1649), .Y(n242)
);
AO22XLTS U1860 ( .A0(n1661), .A1(P_Sgf[3]), .B0(n1654), .B1(n1650), .Y(n241)
);
AO22XLTS U1861 ( .A0(n1661), .A1(P_Sgf[2]), .B0(n1654), .B1(n1651), .Y(n240)
);
AO22XLTS U1862 ( .A0(n1661), .A1(P_Sgf[0]), .B0(n1654), .B1(n1653), .Y(n238)
);
ADDHXLTS U1863 ( .A(n1656), .B(n1655), .CO(n1658), .S(n1511) );
XOR2X1TS U1864 ( .A(n1658), .B(n1657), .Y(n1659) );
AO22XLTS U1865 ( .A0(Sgf_normalized_result[0]), .A1(n1663), .B0(
final_result_ieee[0]), .B1(n1662), .Y(n200) );
AO22XLTS U1866 ( .A0(n490), .A1(n1663), .B0(final_result_ieee[1]), .B1(n1662), .Y(n199) );
AO22XLTS U1867 ( .A0(n482), .A1(n1663), .B0(final_result_ieee[2]), .B1(n1662), .Y(n198) );
AO22XLTS U1868 ( .A0(Sgf_normalized_result[3]), .A1(n1663), .B0(
final_result_ieee[3]), .B1(n1662), .Y(n197) );
AO22XLTS U1869 ( .A0(Sgf_normalized_result[4]), .A1(n1663), .B0(
final_result_ieee[4]), .B1(n1662), .Y(n196) );
AO22XLTS U1870 ( .A0(Sgf_normalized_result[5]), .A1(n1663), .B0(
final_result_ieee[5]), .B1(n1662), .Y(n195) );
AO22XLTS U1871 ( .A0(Sgf_normalized_result[6]), .A1(n1663), .B0(
final_result_ieee[6]), .B1(n1662), .Y(n194) );
AO22XLTS U1872 ( .A0(Sgf_normalized_result[7]), .A1(n1663), .B0(
final_result_ieee[7]), .B1(n1662), .Y(n193) );
AO22XLTS U1873 ( .A0(Sgf_normalized_result[8]), .A1(n1663), .B0(
final_result_ieee[8]), .B1(n1662), .Y(n192) );
AO22XLTS U1874 ( .A0(Sgf_normalized_result[9]), .A1(n1663), .B0(
final_result_ieee[9]), .B1(n1662), .Y(n191) );
AO22XLTS U1875 ( .A0(Sgf_normalized_result[10]), .A1(n1663), .B0(
final_result_ieee[10]), .B1(n1662), .Y(n190) );
AO22XLTS U1876 ( .A0(Sgf_normalized_result[11]), .A1(n1663), .B0(
final_result_ieee[11]), .B1(n1662), .Y(n189) );
AO22XLTS U1877 ( .A0(Sgf_normalized_result[12]), .A1(n1663), .B0(
final_result_ieee[12]), .B1(n1662), .Y(n188) );
AO22XLTS U1878 ( .A0(Sgf_normalized_result[13]), .A1(n1663), .B0(
final_result_ieee[13]), .B1(n1662), .Y(n187) );
AO22XLTS U1879 ( .A0(Sgf_normalized_result[14]), .A1(n1663), .B0(
final_result_ieee[14]), .B1(n1662), .Y(n186) );
AO22XLTS U1880 ( .A0(Sgf_normalized_result[15]), .A1(n1663), .B0(
final_result_ieee[15]), .B1(n1662), .Y(n185) );
AO22XLTS U1881 ( .A0(Sgf_normalized_result[16]), .A1(n1663), .B0(
final_result_ieee[16]), .B1(n1662), .Y(n184) );
AO22XLTS U1882 ( .A0(Sgf_normalized_result[17]), .A1(n1663), .B0(
final_result_ieee[17]), .B1(n1662), .Y(n183) );
AO22XLTS U1883 ( .A0(Sgf_normalized_result[18]), .A1(n1663), .B0(
final_result_ieee[18]), .B1(n1662), .Y(n182) );
AO22XLTS U1884 ( .A0(Sgf_normalized_result[19]), .A1(n1663), .B0(
final_result_ieee[19]), .B1(n1662), .Y(n181) );
AO22XLTS U1885 ( .A0(Sgf_normalized_result[20]), .A1(n1663), .B0(
final_result_ieee[20]), .B1(n1662), .Y(n180) );
AO22XLTS U1886 ( .A0(Sgf_normalized_result[21]), .A1(n1663), .B0(
final_result_ieee[21]), .B1(n1662), .Y(n179) );
AO22XLTS U1887 ( .A0(Sgf_normalized_result[22]), .A1(n1663), .B0(
final_result_ieee[22]), .B1(n1662), .Y(n178) );
OA22X1TS U1888 ( .A0(n1665), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n1664), .Y(n177) );
OA22X1TS U1889 ( .A0(n1665), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n1664), .Y(n176) );
OA22X1TS U1890 ( .A0(n1665), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n1664), .Y(n175) );
OA22X1TS U1891 ( .A0(n1665), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n1664), .Y(n174) );
OA22X1TS U1892 ( .A0(n1665), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n1664), .Y(n173) );
OA22X1TS U1893 ( .A0(n1665), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n1664), .Y(n172) );
OA22X1TS U1894 ( .A0(n1665), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n1664), .Y(n171) );
OA22X1TS U1895 ( .A0(n1665), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n1664), .Y(n170) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk40.tcl_RKOA_1STAGE_syn.sdf");
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
module inport #(parameter X_LOCAL = 2, parameter Y_LOCAL = 2)
(
input wire clka,
input wire rsta,
input wire [1:0] diff_pair_din,
input wire [47:0] channel_din,
output wire request_dout,
output wire x_hit_dout,
output wire y_hit_dout,
output wire [47:0] packet_dout
);
//---- Signal declaration
// Port flow_handler
wire request_unreg;
// Segmentation Registers
reg [47:0] input_pipe_reg = 48'b0;
// Register for arbitration request
reg request_reg;
// Port flow_handler
input_flow_handler inport_flow_handler
(
.clka (clka),
.rsta (rsta),
.diff_pair_p(diff_pair_din[1]),
.diff_pair_n(diff_pair_din[0]),
.pipe_en (request_unreg)
); // flow_handler
// Registered outputs
assign packet_dout = input_pipe_reg[47:0];
assign request_dout = request_reg;
// Derived outputs
assign x_hit_dout = (input_pipe_reg[47:44] == X_LOCAL) ? 1'b1 : 1'b0;
assign y_hit_dout = (input_pipe_reg[43:40] == Y_LOCAL) ? 1'b1 : 1'b0;
//---- Memory Elements
// Segmentation Registers
always @(posedge clka)
if (request_unreg)
input_pipe_reg <= channel_din;
// Register for arbitration request
always @(posedge clka)
request_reg <= request_unreg;
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_sequencer_ram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../altera_mem_if_ddr3_phy_0001_qsys_sequencer_sequencer_ram.hex";
output [ 31: 0] readdata;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 512,
the_altsyncram.numwords_a = 512,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 9;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "UNUSED",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 512,
// the_altsyncram.numwords_a = 512,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 9;
//
//synthesis read_comments_as_HDL off
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Comultiplierany:
// Engineer:
//
// Create Date: 00:38:22 02/18/2016
// Design Name:
// Module Name: boothMultiplier
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module boothMultiplier(
input [3:0] multiplicand,
input [3:0] multiplier,
output [7:0] product,
input clock,
input reset
);
reg [3:0] A, Q, M;
reg Q_1;
reg [3:0] count;
wire [3:0] sum, difference;
always @(posedge clock)
begin
if (reset) begin
A <= 4'b0;
M <= multiplicand;
Q <= multiplier;
Q_1 <= 1'b0;
count <= 3'b0;
end
else begin
case ({Q[0], Q_1})
2'b01 : {A, Q, Q_1} <= {sum[3], sum, Q};
2'b10 : {A, Q, Q_1} <= {difference[3], difference, Q};
default: {A, Q, Q_1} <= {A[3], A, Q};
endcase
count <= count + 1;
end
end
alu adder (A, M, 0,sum);
alu subtracter (A, ~M, 1,difference);
assign product = {A, Q};
endmodule
module alu(a,b,cin,out);
input [3:0] a;
input [3:0] b;
input cin;
output [3:0] out;
assign out = a + b + cin;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_TB_V
`define SKY130_FD_SC_LP__A41O_TB_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 A4 = 1'b1;
#280 B1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 A4 = 1'b0;
#460 B1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B1 = 1'b1;
#660 A4 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B1 = 1'bx;
#840 A4 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a41o dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_TB_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module RAMB16_S1_S9 (
CLKA, CLKB, ENB, WEA, WEB, ENA, SSRA, SSRB, DIPB, ADDRA, ADDRB, DIA, DIB, DOA, DOB, DOPB
);
input wire CLKA;
input wire CLKB;
output reg [7 : 0] DOB;
output reg [0 : 0] DOA;
input wire [0 : 0] WEA;
input wire [0 : 0] WEB;
input wire [10 : 0] ADDRB;
input wire [13 : 0] ADDRA;
input wire [7 : 0] DIB;
input wire [0 : 0] DIA;
input wire ENB;
input wire ENA;
input wire SSRA;
input wire SSRB;
input wire DIPB;
output wire DOPB;
parameter WIDTHA = 1;
parameter SIZEA = 16384;
parameter ADDRWIDTHA = 14;
parameter WIDTHB = 8;
parameter SIZEB = 2048;
parameter ADDRWIDTHB = 11;
`define max(a,b) (a) > (b) ? (a) : (b)
`define min(a,b) (a) < (b) ? (a) : (b)
`include "../includes/log2func.v"
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = `CLOG2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
always @(posedge CLKA)
if (WEA)
RAM[ADDRA] <= DIA;
else
DOA <= RAM[ADDRA];
genvar i;
generate for (i = 0; i < RATIO; i = i+1)
begin: portA
localparam [log2RATIO-1:0] lsbaddr = i;
always @(posedge CLKB)
if (WEB)
RAM[{ADDRB, lsbaddr}] <= DIB[(i+1)*minWIDTH-1:i*minWIDTH];
else
DOB[(i+1)*minWIDTH-1:i*minWIDTH] <= RAM[{ADDRB, lsbaddr}];
end
endgenerate
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// mv_read O 64
// mav_write O 64
// mv_sie_read O 64
// mav_sie_write O 64
// CLK I 1 clock
// RST_N I 1 reset
// mav_write_misa I 28
// mav_write_wordxl I 64
// mav_sie_write_misa I 28
// mav_sie_write_wordxl I 64
// EN_reset I 1
// EN_mav_write I 1
// EN_mav_sie_write I 1
//
// Combinational paths from inputs to outputs:
// (mav_write_misa, mav_write_wordxl) -> mav_write
// (mav_sie_write_misa, mav_sie_write_wordxl) -> mav_sie_write
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_MIE(CLK,
RST_N,
EN_reset,
mv_read,
mav_write_misa,
mav_write_wordxl,
EN_mav_write,
mav_write,
mv_sie_read,
mav_sie_write_misa,
mav_sie_write_wordxl,
EN_mav_sie_write,
mav_sie_write);
input CLK;
input RST_N;
// action method reset
input EN_reset;
// value method mv_read
output [63 : 0] mv_read;
// actionvalue method mav_write
input [27 : 0] mav_write_misa;
input [63 : 0] mav_write_wordxl;
input EN_mav_write;
output [63 : 0] mav_write;
// value method mv_sie_read
output [63 : 0] mv_sie_read;
// actionvalue method mav_sie_write
input [27 : 0] mav_sie_write_misa;
input [63 : 0] mav_sie_write_wordxl;
input EN_mav_sie_write;
output [63 : 0] mav_sie_write;
// signals for module outputs
wire [63 : 0] mav_sie_write, mav_write, mv_read, mv_sie_read;
// register rg_mie
reg [11 : 0] rg_mie;
reg [11 : 0] rg_mie$D_IN;
wire rg_mie$EN;
// rule scheduling signals
wire CAN_FIRE_mav_sie_write,
CAN_FIRE_mav_write,
CAN_FIRE_reset,
WILL_FIRE_mav_sie_write,
WILL_FIRE_mav_write,
WILL_FIRE_reset;
// inputs to muxes for submodule ports
wire [11 : 0] MUX_rg_mie$write_1__VAL_3;
// remaining internal signals
wire [11 : 0] mie__h92, x__h467, x__h901;
wire seie__h132,
seie__h562,
ssie__h126,
ssie__h556,
stie__h129,
stie__h559,
ueie__h131,
ueie__h561,
usie__h125,
usie__h555,
utie__h128,
utie__h558;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 52'd0, rg_mie } ;
// actionvalue method mav_write
assign mav_write = { 52'd0, mie__h92 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// value method mv_sie_read
assign mv_sie_read = { 52'd0, x__h467 } ;
// actionvalue method mav_sie_write
assign mav_sie_write = { 52'd0, x__h901 } ;
assign CAN_FIRE_mav_sie_write = 1'd1 ;
assign WILL_FIRE_mav_sie_write = EN_mav_sie_write ;
// inputs to muxes for submodule ports
assign MUX_rg_mie$write_1__VAL_3 =
{ rg_mie[11],
1'b0,
seie__h562,
ueie__h561,
rg_mie[7],
1'b0,
stie__h559,
utie__h558,
rg_mie[3],
1'b0,
ssie__h556,
usie__h555 } ;
// register rg_mie
always@(EN_mav_write or
mie__h92 or
EN_reset or EN_mav_sie_write or MUX_rg_mie$write_1__VAL_3)
case (1'b1)
EN_mav_write: rg_mie$D_IN = mie__h92;
EN_reset: rg_mie$D_IN = 12'd0;
EN_mav_sie_write: rg_mie$D_IN = MUX_rg_mie$write_1__VAL_3;
default: rg_mie$D_IN = 12'b101010101010 /* unspecified value */ ;
endcase
assign rg_mie$EN = EN_mav_write || EN_mav_sie_write || EN_reset ;
// remaining internal signals
assign mie__h92 =
{ mav_write_wordxl[11],
1'b0,
seie__h132,
ueie__h131,
mav_write_wordxl[7],
1'b0,
stie__h129,
utie__h128,
mav_write_wordxl[3],
1'b0,
ssie__h126,
usie__h125 } ;
assign seie__h132 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign seie__h562 = mav_sie_write_misa[18] && mav_sie_write_wordxl[9] ;
assign ssie__h126 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign ssie__h556 = mav_sie_write_misa[18] && mav_sie_write_wordxl[1] ;
assign stie__h129 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign stie__h559 = mav_sie_write_misa[18] && mav_sie_write_wordxl[5] ;
assign ueie__h131 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign ueie__h561 = mav_sie_write_misa[13] && mav_sie_write_wordxl[8] ;
assign usie__h125 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign usie__h555 = mav_sie_write_misa[13] && mav_sie_write_wordxl[0] ;
assign utie__h128 = mav_write_misa[13] && mav_write_wordxl[4] ;
assign utie__h558 = mav_sie_write_misa[13] && mav_sie_write_wordxl[4] ;
assign x__h467 =
{ 2'd0, rg_mie[9:8], 2'd0, rg_mie[5:4], 2'd0, rg_mie[1:0] } ;
assign x__h901 =
{ 2'd0,
seie__h562,
ueie__h561,
2'd0,
stie__h559,
utie__h558,
2'd0,
ssie__h556,
usie__h555 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0;
end
else
begin
if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_mie = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCSR_MIE
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 23:00:38 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_timer_0_1/zqynq_lab_1_design_axi_timer_0_1_stub.v
// Design : zqynq_lab_1_design_axi_timer_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_timer,Vivado 2017.2" *)
module zqynq_lab_1_design_axi_timer_0_1(capturetrig0, capturetrig1, generateout0,
generateout1, pwm0, interrupt, freeze, s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awvalid,
s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp,
s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, s_axi_rdata,
s_axi_rresp, s_axi_rvalid, s_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="capturetrig0,capturetrig1,generateout0,generateout1,pwm0,interrupt,freeze,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[4:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[4:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready" */;
input capturetrig0;
input capturetrig1;
output generateout0;
output generateout1;
output pwm0;
output interrupt;
input freeze;
input s_axi_aclk;
input s_axi_aresetn;
input [4:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [4:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
endmodule
|
/*!
* <b>Module:</b>oob
* @file oob.v
* @date 2015-07-11
* @author Alexey
*
* @brief sata oob unit implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* oob.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* oob.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
/*
* For now both device and host shall be set up to SATA2 speeds.
* Need to think how to change speed grades on fly (either to broaden
* data iface width or to change RXRATE/TXRATE)
*/
// All references to doc = to SerialATA_Revision_2_6_Gold.pdf
module oob #(
parameter DATA_BYTE_WIDTH = 4,
parameter CLK_SPEED_GRADE = 1 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
)
(
output reg [11:0] debug,
input wire clk, // sata clk = usrclk2
input wire rst, // reset oob
// oob responses
input wire rxcominitdet_in,
input wire rxcomwakedet_in,
input wire rxelecidle_in,
// oob issues
output wire txcominit,
output wire txcomwake,
output wire txelecidle,
output wire txpcsreset_req, // partial tx reset
input wire recal_tx_done,
output wire rxreset_req, // rx reset (after rxelecidle -> 0)
input wire rxreset_ack,
// Andrey: adding new signal and state - after RX is operational try re-align clock
output wire clk_phase_align_req, // Request GTX to align SIPO parallel clock and user- provided RXUSRCLK
input wire clk_phase_align_ack, // GTX aligned clock phase (DEBUG - not always clear when it works or not)
input wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_in, // input data stream (if any data during OOB setting => ignored)
input wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in,
output wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_out, // output data stream to gtx
output wire [DATA_BYTE_WIDTH - 1:0] txcharisk_out,
input wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in, // input data from gtx
input wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_in,
output wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_out, // bypassed data from gtx
output wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out,
input wire oob_start, // oob sequence needs to be issued
output wire oob_done, // connection established, all further data is valid
output wire oob_busy, // oob can't handle new start request
output wire link_up, // doc p265, link is established after 3back-to-back non-ALIGNp
output wire link_down, // link goes down - if rxelecidle
output wire cominit_req, // the device itself sends cominit
input wire cominit_allow, // allow to respond to cominit
// status information to handle by a control block if any exists
output wire oob_incompatible, // incompatible host-device speed grades (host cannot lock to alignp)
output wire oob_error, // timeout in an unexpected place
output wire oob_silence // noone responds to our cominits
,output debug_detected_alignp
`ifdef OOB_MULTISPEED
//TODO
// !!Implement it later on, ref to gen.adjustment fsm in the notebook!!
// speed grade control
,
// current speed grade, dynamic instead of static parameter
input wire [2:0] speed_grade,
// clock to be adjusted to best speed
input wire adj_clk,
// ask for slower protocol clock
output wire speed_down_req,
input wire speed_down_ack,
// reset speedgrade to the fastest one
output wire speed_rst_req,
input wire speed_rst_ack
`endif //OOB_MULTISPEED
);
assign debug_detected_alignp = detected_alignp;
`ifdef SIMULATION
reg [639:0] HOST_OOB_TITLE ='bz; // to show human-readable state in the GTKWave
`endif
// 873.8 us error timer
// = 2621400 SATA2 serial ticks (period = 0.000333 us)
// = 131070 ticks @ 150Mhz
// = 65535 ticks @ 75Mhz
localparam [19:0] CLK_TO_TIMER_CONTRIB = CLK_SPEED_GRADE == 1 ? 20'h4 :
CLK_SPEED_GRADE == 2 ? 20'h2 :
CLK_SPEED_GRADE == 4 ? 20'h1 : 20'h1;
localparam RXDLYSRESET_CYCLES = 5; // minimum - 50ns
reg [RXDLYSRESET_CYCLES-1:0] rxdlysreset_r;
assign clk_phase_align_req = rxdlysreset_r[RXDLYSRESET_CYCLES-1];
`ifdef SIMULATION
localparam [19:0] TIMER_LIMIT = 19'd20000;
`else
localparam [19:0] TIMER_LIMIT = 19'd262140;
`endif
reg [19:0] timer;
wire timer_clr;
wire timer_fin;
// latching inputs from gtx
reg rxcominitdet;
reg rxcomwakedet;
reg rxelecidle;
reg [DATA_BYTE_WIDTH*8 - 1:0] rxdata;
reg [DATA_BYTE_WIDTH - 1:0] rxcharisk;
// primitives detection
wire detected_alignp;
localparam NUM_CON_ALIGNS = 2; // just for debugging 1024;
reg [1:0] detected_alignp_cntr; // count detected ALIGNp - do not respond yet
///localparam NUM_CON_ALIGNS = 1024; // just for debugging 1024;
///reg [12:0] detected_alignp_cntr; // count detected ALIGNp - do not respond yet
reg detected_alignp_r; // debugging - N-th ALIGNp primitive
wire detected_syncp;
// wait until device's cominit is done
reg cominit_req_l;
reg rxcominitdet_l;
reg rxcomwakedet_l;
wire rxcominit_done;
wire rxcomwake_done;
reg [9:0] rxcom_timer;
// for 75MHz : period of cominit = 426.7 ns = 32 ticks => need to wait x6 pulses + 1 as an insurance => 224 clock cycles. Same thoughts for comwake
localparam COMINIT_DONE_TIME = 896; // 300Mhz cycles
localparam COMWAKE_DONE_TIME = 448; // 300Mhz cycles
// wait until rxelecidle is not stable (more or less) deasserted
// let's say, if rxelecidle = 0 longer, than 2 comwake burst duration (2 * 106.7 ns), elecidle is stable and we're receiving some data
// 2 * 106.7ns = 64 clock cycles @ 300 MHz, 32 @ 150, 16 @ 75
// rxelecidle is synchronous to sata host clk, sooo some idle raises can occur insensibly. Still, it means line issues,
// not affecting the fact, oob was done and a stage when device sends alignps started
reg [7:0] eidle_timer;
wire eidle_timer_done;
// fsm, doc p265,266
wire state_idle;
reg state_wait_cominit;
reg state_wait_comwake;
reg state_recal_tx;
reg state_wait_eidle;
reg state_wait_rxrst;
reg state_wait_align;
reg state_wait_clk_align;
reg state_wait_align2; // after clocks aligned
reg state_wait_synp;
reg state_wait_linkup;
reg state_error;
wire set_wait_cominit;
wire set_wait_comwake;
wire set_recal_tx;
wire set_wait_eidle;
wire set_wait_rxrst;
wire set_wait_align;
wire set_wait_clk_align;
wire set_wait_align2;
wire set_wait_synp;
wire set_wait_linkup;
wire set_error;
wire clr_wait_cominit;
wire clr_wait_comwake;
wire clr_recal_tx;
wire clr_wait_eidle;
wire clr_wait_rxrst;
wire clr_wait_align;
wire clr_wait_clk_align;
wire clr_wait_align2;
wire clr_wait_synp;
wire clr_wait_linkup;
wire clr_error;
always @ (posedge clk) begin
if (rst || rxelecidle) rxdlysreset_r <= 0;
else if (set_wait_clk_align) rxdlysreset_r <= ~0;
else rxdlysreset_r <= rxdlysreset_r << 1;
end
reg was_rxelecidle_waiting_reset;
always @ (posedge clk) begin
if (rst || set_wait_eidle) was_rxelecidle_waiting_reset <= 0;
else if (state_wait_rxrst && rxelecidle) was_rxelecidle_waiting_reset <= 1;
end
assign state_idle = ~state_wait_cominit &
~state_wait_comwake &
~state_wait_align &
~state_wait_clk_align &
~state_wait_align2 &
~state_wait_synp &
~state_wait_linkup &
~state_error &
~state_recal_tx &
~state_wait_rxrst &
~state_wait_eidle;
always @ (posedge clk)
begin
state_wait_cominit <= (state_wait_cominit | set_wait_cominit ) & ~clr_wait_cominit & ~rst;
state_wait_comwake <= (state_wait_comwake | set_wait_comwake ) & ~clr_wait_comwake & ~rst;
state_recal_tx <= (state_recal_tx | set_recal_tx ) & ~clr_recal_tx & ~rst;
state_wait_eidle <= (state_wait_eidle | set_wait_eidle ) & ~clr_wait_eidle & ~rst;
state_wait_rxrst <= (state_wait_rxrst | set_wait_rxrst ) & ~clr_wait_rxrst & ~rst;
state_wait_align <= (state_wait_align | set_wait_align ) & ~clr_wait_align & ~rst;
state_wait_clk_align <= (state_wait_clk_align | set_wait_clk_align) & ~clr_wait_clk_align & ~rst;
state_wait_align2 <= (state_wait_align2 | set_wait_align2 ) & ~clr_wait_align2 & ~rst;
state_wait_synp <= (state_wait_synp | set_wait_synp ) & ~clr_wait_synp & ~rst;
state_wait_linkup <= (state_wait_linkup | set_wait_linkup ) & ~clr_wait_linkup & ~rst;
state_error <= (state_error | set_error ) & ~clr_error & ~rst;
end
assign set_wait_cominit = state_idle & oob_start & ~cominit_req;
assign set_wait_comwake = state_idle & cominit_req_l & cominit_allow & rxcominit_done | state_wait_cominit & rxcominitdet_l & rxcominit_done;
assign set_recal_tx = state_wait_comwake & rxcomwakedet_l & rxcomwake_done;
///assign set_wait_eidle = state_recal_tx & recal_tx_done;
assign set_wait_eidle = (state_recal_tx & recal_tx_done) |
(rxelecidle &
(state_wait_align | state_wait_clk_align | state_wait_align2 | (state_wait_rxrst & rxreset_ack & was_rxelecidle_waiting_reset) ));
assign set_wait_rxrst = state_wait_eidle & eidle_timer_done;
///assign set_wait_align = state_wait_rxrst & rxreset_ack;
///assign set_wait_clk_align = state_wait_align & (detected_alignp_r);
///assign set_wait_align2 = state_wait_clk_align & clk_phase_align_ack;
assign set_wait_align = state_wait_rxrst & rxreset_ack & ~rxelecidle;
assign set_wait_clk_align = state_wait_align & (detected_alignp_r) & ~rxelecidle;
assign set_wait_align2 = state_wait_clk_align & clk_phase_align_ack & ~rxelecidle;
//assign set_wait_synp = state_wait_align & detected_alignp;
assign set_wait_synp = state_wait_align2 & (detected_alignp_r); // N previous were both ALIGNp
assign set_wait_linkup = state_wait_synp & detected_syncp;
assign set_error = timer_fin & (state_wait_cominit |
state_wait_comwake |
state_recal_tx |
state_wait_eidle |
state_wait_rxrst |
state_wait_align |
state_wait_clk_align |
state_wait_align2 |
state_wait_synp/* | state_wait_linkup*/);
assign clr_wait_cominit = set_wait_comwake | set_error;
assign clr_wait_comwake = set_recal_tx | set_error;
assign clr_recal_tx = set_wait_eidle | set_error;
assign clr_wait_eidle = set_wait_rxrst | set_error;
///assign clr_wait_rxrst = set_wait_align | set_error;
assign clr_wait_rxrst = state_wait_rxrst & rxreset_ack;
///assign clr_wait_align = set_wait_clk_align | set_error;
///assign clr_wait_clk_align = set_wait_align2 | set_error;
///assign clr_wait_align2 = set_wait_synp | set_error;
assign clr_wait_align = set_wait_clk_align | set_error | rxelecidle;
assign clr_wait_clk_align = set_wait_align2 | set_error | rxelecidle;
assign clr_wait_align2 = set_wait_synp | set_error | rxelecidle;
assign clr_wait_synp = set_wait_linkup | set_error;
assign clr_wait_linkup = state_wait_linkup; //TODO not so important, but still have to trace 3 back-to-back non alignp primitives
assign clr_error = state_error;
// waiting timeout timer
assign timer_fin = timer == TIMER_LIMIT;
assign timer_clr = set_error | state_error | state_idle;
always @ (posedge clk)
timer <= rst | timer_clr ? 20'h0 : timer + CLK_TO_TIMER_CONTRIB;
// something is wrong with speed grades if the host cannot lock to device's alignp stream
assign oob_incompatible = state_wait_align & set_error;
// oob sequence is done, everything is okay
assign oob_done = set_wait_linkup;
// noone responds to cominits
assign oob_silence = set_error & state_wait_cominit;
// other timeouts
assign oob_error = set_error & ~oob_silence & ~oob_incompatible;
// obvioud
assign oob_busy = ~state_idle;
// ask for recalibration
assign txpcsreset_req = state_recal_tx;
// ask for rxreset
assign rxreset_req = state_wait_rxrst;
// set gtx controls
reg txelecidle_r;
always @ (posedge clk)
txelecidle_r <= rst ? 1'b1 : /*clr_wait_cominit */ clr_wait_comwake ? 1'b0 : set_wait_cominit ? 1'b1 : txelecidle_r;
assign txcominit = set_wait_cominit;
assign txcomwake = set_wait_comwake;
assign txelecidle = set_wait_cominit | txelecidle_r;
// indicate if link up condition was made
assign link_up = clr_wait_linkup;
// link goes down when line is idle
reg rxelecidle_r;
reg rxelecidle_rr;
always @ (posedge clk)
begin
rxelecidle_rr <= rxelecidle_r;
rxelecidle_r <= rxelecidle;
end
assign link_down = rxelecidle_rr;
// indicate that device is requesting for oob
reg cominit_req_r;
wire cominit_req_set;
assign cominit_req_set = state_idle & rxcominitdet;
always @ (posedge clk)
cominit_req_r <= (cominit_req_r | cominit_req_set) & ~(cominit_allow & cominit_req) & ~rst;
assign cominit_req = cominit_req_set | cominit_req_r;
// primitives
wire [63:0] alignp = {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100, 8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100};
wire [63:0] syncp = {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100, 8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100};
// detect which primitives sends the device after comwake was done
generate
if (DATA_BYTE_WIDTH == 2)
begin
reg detected_alignp_f;
always @ (posedge clk)
detected_alignp_f <= rst | ~state_wait_align ? 1'b0 :
~|(rxdata[15:0] ^ alignp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D10.2, K28.5}
assign detected_alignp = detected_alignp_f & ~|(rxdata[15:0] ^ alignp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D27.3, D10.2} // S uppressThisWarning VEditor -warning would be fixed in future releases
reg detected_syncp_f;
always @ (posedge clk)
detected_syncp_f <= rst | ~state_wait_synp ? 1'b0 :
~|(rxdata[15:0] ^ syncp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D21.4, K28.3}
assign detected_syncp = detected_syncp_f & ~|(rxdata[15:0] ^ syncp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D21.5, D21.5} // S uppressThisWarning VEditor -warning would be fixed in future releases
end
else
if (DATA_BYTE_WIDTH == 4)
begin
assign detected_alignp = ~|(rxdata[31:0] ^ alignp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5} // S uppressThisWarning VEditor -warning would be fixed in future releases
assign detected_syncp = ~|(rxdata[31:0] ^ syncp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3} // S uppressThisWarning VEditor -warning would be fixed in future releases
end
else
if (DATA_BYTE_WIDTH == 8)
begin
assign detected_alignp = ~|(rxdata[63:0] ^ alignp[63:0]) & ~|(rxcharisk[7:0] ^ 8'h11); // {D27.3, D10.2, D10.2, K28.5} // SuppressThisWarning VEditor -warning would be fixed in future releases
assign detected_syncp = ~|(rxdata[63:0] ^ syncp[63:0]) & ~|(rxcharisk[7:0] ^ 8'h11); // {D21.5, D21.5, D21.4, K28.3} // SuppressThisWarning VEditor -warning would be fixed in future releases
end
else
begin
always @ (posedge clk)
begin
$display("%m oob module works only with 16/32/64 gtx input data width");
$finish;
end
end
endgenerate
// calculate an aproximate time when oob burst shall be done
assign rxcominit_done = rxcom_timer == COMINIT_DONE_TIME & state_wait_cominit;
assign rxcomwake_done = rxcom_timer == COMWAKE_DONE_TIME & state_wait_comwake;
always @ (posedge clk) begin
cominit_req_l <= rst | rxcominit_done | ~state_idle ? 1'b0 : cominit_req ? 1'b1 : cominit_req_l;
rxcominitdet_l <= rst | rxcominit_done | ~state_wait_cominit ? 1'b0 : rxcominitdet ? 1'b1 : rxcominitdet_l;
rxcomwakedet_l <= rst | rxcomwake_done | ~state_wait_comwake ? 1'b0 : rxcomwakedet ? 1'b1 : rxcomwakedet_l;
end
// buf inputs from gtx
always @ (posedge clk)
begin
rxcominitdet <= rxcominitdet_in;
rxcomwakedet <= rxcomwakedet_in;
rxelecidle <= rxelecidle_in;
rxdata <= rxdata_in;
rxcharisk <= rxcharisk_in;
end
// set data outputs to upper levels
assign rxdata_out = rxdata;
assign rxcharisk_out = rxcharisk;
// as depicted @ doc, p264, figure 163, have to insert D10.2 and align primitives after
// getting comwake from device
reg [DATA_BYTE_WIDTH*8 - 1:0] txdata;
reg [DATA_BYTE_WIDTH - 1:0] txcharisk;
wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_d102;
wire [DATA_BYTE_WIDTH - 1:0] txcharisk_d102;
wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_align;
wire [DATA_BYTE_WIDTH - 1:0] txcharisk_align;
always @ (posedge clk)
begin
txdata <= state_wait_align ? txdata_d102 :
state_wait_rxrst ? txdata_d102 :
state_wait_synp ? txdata_align : txdata_in;
txcharisk <= state_wait_align ? txcharisk_d102 :
state_wait_rxrst ? txcharisk_d102 :
state_wait_synp ? txcharisk_align : txcharisk_in;
end
// Continious D10.2 primitive
assign txcharisk_d102 = {DATA_BYTE_WIDTH{1'b0}};
assign txdata_d102 = {DATA_BYTE_WIDTH{8'b01001010}}; // SuppressThisWarning VEditor -warning would be fixed in future releases
// Align primitive: K28.5 + D10.2 + D10.2 + D27.3
generate
if (DATA_BYTE_WIDTH == 2)
begin
reg align_odd;
always @ (posedge clk)
align_odd <= rst | ~state_wait_synp ? 1'b0 : ~align_odd;
assign txcharisk_align[DATA_BYTE_WIDTH - 1:0] = align_odd ? 2'b01 : 2'b00; // SuppressThisWarning VEditor -warning would be fixed in future releases
assign txdata_align[DATA_BYTE_WIDTH*8 - 1:0] = align_odd ? alignp[15:0] : // {D10.2, K28.5} // SuppressThisWarning VEditor -warning would be fixed in future releases
alignp[31:16]; // {D27.3, D10.2} // SuppressThisWarning VEditor -warning would be fixed in future releases
end
else
if (DATA_BYTE_WIDTH == 4)
begin
assign txcharisk_align[DATA_BYTE_WIDTH - 1:0] = 4'h1;
assign txdata_align[DATA_BYTE_WIDTH*8 - 1:0] = alignp[DATA_BYTE_WIDTH*8 - 1:0]; // {D27.3, D10.2, D10.2, K28.5}
end
else
if (DATA_BYTE_WIDTH == 8)
begin
assign txcharisk_align[DATA_BYTE_WIDTH - 1:0] = 8'h11; // SuppressThisWarning VEditor -warning would be fixed in future releases
assign txdata_align[DATA_BYTE_WIDTH*8 - 1:0] = alignp[DATA_BYTE_WIDTH*8 - 1:0]; // 2x{D27.3, D10.2, D10.2, K28.5}
end
else
always @ (posedge clk)
begin
$display("%m oob module works only with 16/32/64 gtx input data width");
$finish;
end
endgenerate
`ifdef SIMULATION
// info msgs
always @ (posedge clk)
begin
if (txcominit) begin
HOST_OOB_TITLE = "Issued cominit";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
if (txcomwake) begin
HOST_OOB_TITLE = "Issued comwake";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
if (state_wait_linkup) begin
HOST_OOB_TITLE = "Link is up";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
if (set_wait_synp) begin
HOST_OOB_TITLE = "Started continious align sending";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
end
`endif
always @ (posedge clk)
rxcom_timer <= rst | rxcominit_done & state_wait_cominit | rxcomwake_done & state_wait_comwake | rxcominitdet & state_wait_cominit | rxcomwakedet & state_wait_comwake ? 10'h0 : cominit_req_l & state_idle | rxcominitdet_l & state_wait_cominit | rxcomwakedet_l & state_wait_comwake ? rxcom_timer + CLK_TO_TIMER_CONTRIB[9:0] : 10'h0;
// set data outputs to gtx
assign txdata_out = txdata;
assign txcharisk_out = txcharisk;
// rxelectidle timer logic
assign eidle_timer_done = eidle_timer == 64;
always @ (posedge clk)
eidle_timer <= rst | rxelecidle | ~state_wait_eidle ? 8'b0 : eidle_timer + CLK_TO_TIMER_CONTRIB[7:0];
always @ (posedge clk) begin
if (rst || !detected_alignp) detected_alignp_cntr <= NUM_CON_ALIGNS;
else if (|detected_alignp_cntr) detected_alignp_cntr <= detected_alignp_cntr -1;
detected_alignp_r <= detected_alignp_cntr == 0;
end
always @ (posedge clk)
debug <= rst ? 12'h000 : {
state_idle,
state_wait_cominit,
state_wait_comwake,
state_recal_tx,
state_wait_eidle,
state_wait_rxrst,
state_wait_align,
state_wait_synp,
state_wait_linkup,
state_error,
oob_start,
oob_error} | debug;
endmodule
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <[email protected]>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
module tb_sim;
`include "bch_params.vh"
parameter T = 3;
parameter OPTION = "SERIAL";
parameter DATA_BITS = 5;
parameter BITS = 1;
parameter REG_RATIO = 1;
parameter SEED = 0;
localparam BCH_PARAMS = bch_params(DATA_BITS, T);
reg [31:0] seed = SEED;
initial begin
$dumpfile("test.vcd");
$dumpvars(0);
end
localparam TCQ = 1;
reg clk = 0;
reg reset = 0;
reg [DATA_BITS-1:0] din = 0;
reg [$clog2(T+2)-1:0] nerr = 0;
reg [`BCH_CODE_BITS(BCH_PARAMS)-1:0] error = 0;
function [DATA_BITS-1:0] randk;
input [31:0] useless;
integer i;
begin
for (i = 0; i < (31 + DATA_BITS) / 32; i = i + 1)
if (i * 32 > DATA_BITS) begin
if (DATA_BITS % 32)
/* Placate isim */
randk[i*32+:(DATA_BITS%32) ? (DATA_BITS%32) : 1] = $random(seed);
end else
randk[i*32+:32] = $random(seed);
end
endfunction
function integer n_errors;
input [31:0] useless;
integer i;
begin
n_errors = (32'h7fff_ffff & $random(seed)) % (T + 1);
end
endfunction
function [`BCH_CODE_BITS(BCH_PARAMS)-1:0] rande;
input [31:0] nerr;
integer i;
begin
rande = 0;
while (nerr) begin
i = (32'h7fff_ffff & $random(seed)) % (`BCH_CODE_BITS(BCH_PARAMS));
if (!((1 << i) & rande)) begin
rande = rande | (1 << i);
nerr = nerr - 1;
end
end
end
endfunction
reg encode_start = 0;
wire wrong;
wire ready;
reg active = 0;
sim #(BCH_PARAMS, OPTION, BITS, REG_RATIO) u_sim(
.clk(clk),
.reset(1'b0),
.data_in(din),
.error(error),
.ready(ready),
.encode_start(active),
.wrong(wrong)
);
always
#5 clk = ~clk;
always @(posedge wrong)
#10 $finish;
reg [31:0] s;
always @(posedge clk) begin
if (ready) begin
s = seed;
#1;
din <= randk(0);
#1;
nerr <= n_errors(0);
#1;
error <= rande(nerr);
#1;
active <= 1;
$display("%b %d flips - %b (seed = %d)", din, nerr, error, s);
end
end
initial begin
$display("GF(2^%1d) (%1d, %1d/%1d, %1d) %s",
`BCH_M(BCH_PARAMS), `BCH_N(BCH_PARAMS), `BCH_K(BCH_PARAMS),
DATA_BITS, `BCH_T(BCH_PARAMS), OPTION);
@(posedge clk);
@(posedge clk);
reset <= #1 1;
@(posedge clk);
@(posedge clk);
reset <= #1 0;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_rx_FF.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2008/08/17 11:41:30 maverickist
// no message
//
// Revision 1.5 2006/06/25 04:58:56 maverickist
// no message
//
// Revision 1.4 2006/05/28 05:09:20 maverickist
// no message
//
// Revision 1.3 2006/01/19 14:07:54 maverickist
// verification is complete.
//
// Revision 1.3 2005/12/16 06:44:16 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.2 2005/12/13 12:15:37 Administrator
// no message
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module MAC_rx_FF (
Reset ,
Clk_MAC ,
Clk_SYS ,
//MAC_rx_ctrl interface
Fifo_data ,
Fifo_data_en ,
Fifo_full ,
Fifo_data_err ,
Fifo_data_end ,
//CPU
Rx_Hwmark,
Rx_Lwmark,
RX_APPEND_CRC,
//user interface
Rx_mac_ra ,
Rx_mac_rd ,
Rx_mac_data ,
Rx_mac_BE ,
Rx_mac_sop ,
Rx_mac_pa,
Rx_mac_eop
);
input Reset ;
input Clk_MAC ;
input Clk_SYS ;
//MAC_rx_ctrl interface
input [7:0] Fifo_data ;
input Fifo_data_en ;
output Fifo_full ;
input Fifo_data_err ;
input Fifo_data_end ;
//CPU
input RX_APPEND_CRC ;
input [4:0] Rx_Hwmark ;
input [4:0] Rx_Lwmark ;
//user interface
output Rx_mac_ra ;//
input Rx_mac_rd ;
output [31:0] Rx_mac_data ;
output [1:0] Rx_mac_BE ;
output Rx_mac_pa ;
output Rx_mac_sop ;
output Rx_mac_eop ;
//******************************************************************************
//internal signals
//******************************************************************************
parameter State_byte3 =4'd0;
parameter State_byte2 =4'd1;
parameter State_byte1 =4'd2;
parameter State_byte0 =4'd3;
parameter State_be0 =4'd4;
parameter State_be3 =4'd5;
parameter State_be2 =4'd6;
parameter State_be1 =4'd7;
parameter State_err_end =4'd8;
parameter State_idle =4'd9;
parameter SYS_read =3'd0;
parameter SYS_pause =3'd1;
parameter SYS_wait_end =3'd2;
parameter SYS_idle =3'd3;
parameter FF_emtpy_err =3'd4;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_reg;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_pl1;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray;
reg [35:0] Din;
reg [35:0] Din_tmp;
reg [35:0] Din_tmp_reg;
wire[35:0] Dout;
reg Wr_en;
reg Wr_en_tmp;
reg Wr_en_ptr;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2;
reg Full;
reg Almost_full;
reg Empty /* synthesis syn_keep=1 */;
reg [3:0] Current_state /* synthesis syn_keep=1 */;
reg [3:0] Next_state;
reg [7:0] Fifo_data_byte0;
reg [7:0] Fifo_data_byte1;
reg [7:0] Fifo_data_byte2;
reg [7:0] Fifo_data_byte3;
reg Fifo_data_en_dl1;
reg [7:0] Fifo_data_dl1;
reg Rx_mac_sop_tmp ;
reg Rx_mac_sop ;
reg Rx_mac_ra ;
reg Rx_mac_pa ;
reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;
reg [2:0] Next_state_SYS ;
reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;
reg Packet_number_sub ;
wire Packet_number_add_edge;
reg Packet_number_add_dl1;
reg Packet_number_add_dl2;
reg Packet_number_add ;
reg Packet_number_add_tmp ;
reg Packet_number_add_tmp_dl1;
reg Packet_number_add_tmp_dl2;
reg Rx_mac_sop_tmp_dl1;
reg [35:0] Dout_dl1;
reg [4:0] Fifo_data_count;
reg Rx_mac_pa_tmp ;
reg Add_wr_jump_tmp ;
reg Add_wr_jump_tmp_pl1 ;
reg Add_wr_jump ;
reg Add_wr_jump_rd_pl1 ;
reg [4:0] Rx_Hwmark_pl ;
reg [4:0] Rx_Lwmark_pl ;
reg Addr_freshed_ptr ;
integer i ;
//******************************************************************************
//domain Clk_MAC,write data to dprom.a-port for write
//******************************************************************************
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Current_state <=State_idle;
else
Current_state <=Next_state;
always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
case (Current_state)
State_idle:
if (Fifo_data_en)
Next_state =State_byte3;
else
Next_state =Current_state;
State_byte3:
if (Fifo_data_en)
Next_state =State_byte2;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be1;
else
Next_state =Current_state;
State_byte2:
if (Fifo_data_en)
Next_state =State_byte1;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be2;
else
Next_state =Current_state;
State_byte1:
if (Fifo_data_en)
Next_state =State_byte0;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be3;
else
Next_state =Current_state;
State_byte0:
if (Fifo_data_en)
Next_state =State_byte3;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be0;
else
Next_state =Current_state;
State_be1:
Next_state =State_idle;
State_be2:
Next_state =State_idle;
State_be3:
Next_state =State_idle;
State_be0:
Next_state =State_idle;
State_err_end:
Next_state =State_idle;
default:
Next_state =State_idle;
endcase
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_reg <=0;
else if (Current_state==State_idle)
Add_wr_reg <=Add_wr;
//
always @ (posedge Reset or posedge Clk_MAC)
if (Reset)
Add_wr_gray <=0;
else
begin
Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
end
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd_gray_dl1 <=0;
else
Add_rd_gray_dl1 <=Add_rd_gray;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd_ungray =0;
else
begin
Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
end
assign Add_wr_pluse=Add_wr+1;
assign Add_wr_pluse4=Add_wr+4;
assign Add_wr_pluse3=Add_wr+3;
assign Add_wr_pluse2=Add_wr+2;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Full <=0;
else if (Add_wr_pluse==Add_rd_ungray)
Full <=1;
else
Full <=0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Almost_full <=0;
else if (Add_wr_pluse4==Add_rd_ungray||
Add_wr_pluse3==Add_rd_ungray||
Add_wr_pluse2==Add_rd_ungray||
Add_wr_pluse==Add_rd_ungray
)
Almost_full <=1;
else
Almost_full <=0;
assign Fifo_full =Almost_full;
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr <=0;
else if (Current_state==State_err_end)
Add_wr <=Add_wr_reg;
else if (Wr_en&&!Full)
Add_wr <=Add_wr +1;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_jump_tmp <=0;
else if (Current_state==State_err_end)
Add_wr_jump_tmp <=1;
else
Add_wr_jump_tmp <=0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_jump_tmp_pl1 <=0;
else
Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_jump <=0;
else if (Current_state==State_err_end)
Add_wr_jump <=1;
else if (Add_wr_jump_tmp_pl1)
Add_wr_jump <=0;
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_en_dl1 <=0;
else
Fifo_data_en_dl1 <=Fifo_data_en;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_dl1 <=0;
else
Fifo_data_dl1 <=Fifo_data;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte3 <=0;
else if (Current_state==State_byte3&&Fifo_data_en_dl1)
Fifo_data_byte3 <=Fifo_data_dl1;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte2 <=0;
else if (Current_state==State_byte2&&Fifo_data_en_dl1)
Fifo_data_byte2 <=Fifo_data_dl1;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte1 <=0;
else if (Current_state==State_byte1&&Fifo_data_en_dl1)
Fifo_data_byte1 <=Fifo_data_dl1;
always @ (* )
case (Current_state)
State_be0:
Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
State_be1:
Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
State_be2:
Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
State_be3:
Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
default:
Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
endcase
always @ (*)
if (Current_state==State_be0||Current_state==State_be1||
Current_state==State_be2||Current_state==State_be3||
(Current_state==State_byte0&&Fifo_data_en))
Wr_en_tmp =1;
else
Wr_en_tmp =0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Din_tmp_reg <=0;
else if(Wr_en_tmp)
Din_tmp_reg <=Din_tmp;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Wr_en_ptr <=0;
else if(Current_state==State_idle)
Wr_en_ptr <=0;
else if(Wr_en_tmp)
Wr_en_ptr <=1;
//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
begin
Wr_en <=0;
Din <=0;
end
else if(RX_APPEND_CRC)
begin
Wr_en <=Wr_en_tmp;
Din <=Din_tmp;
end
else
begin
Wr_en <=Wr_en_tmp&&Wr_en_ptr;
Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};
end
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Packet_number_add_tmp <=0;
else if (Current_state==State_be0||Current_state==State_be1||
Current_state==State_be2||Current_state==State_be3)
Packet_number_add_tmp <=1;
else
Packet_number_add_tmp <=0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
begin
Packet_number_add_tmp_dl1 <=0;
Packet_number_add_tmp_dl2 <=0;
end
else
begin
Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;
Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;
end
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.
//expand to two cycles long almost=16 ns
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Packet_number_add <=0;
else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
Packet_number_add <=1;
else
Packet_number_add <=0;
//******************************************************************************
//domain Clk_SYS,read data from dprom.b-port for read
//******************************************************************************
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Current_state_SYS <=SYS_idle;
else
Current_state_SYS <=Next_state_SYS;
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
case (Current_state_SYS)
SYS_idle:
if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
Next_state_SYS =SYS_read;
else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
Next_state_SYS =FF_emtpy_err;
else
Next_state_SYS =Current_state_SYS;
SYS_read:
if (Dout[35])
Next_state_SYS =SYS_wait_end;
else if (!Rx_mac_rd)
Next_state_SYS =SYS_pause;
else if (Empty)
Next_state_SYS =FF_emtpy_err;
else
Next_state_SYS =Current_state_SYS;
SYS_pause:
if (Rx_mac_rd)
Next_state_SYS =SYS_read;
else
Next_state_SYS =Current_state_SYS;
FF_emtpy_err:
if (!Empty)
Next_state_SYS =SYS_read;
else
Next_state_SYS =Current_state_SYS;
SYS_wait_end:
if (!Rx_mac_rd)
Next_state_SYS =SYS_idle;
else
Next_state_SYS =Current_state_SYS;
default:
Next_state_SYS =SYS_idle;
endcase
//gen Rx_mac_ra
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Packet_number_add_dl1 <=0;
Packet_number_add_dl2 <=0;
end
else
begin
Packet_number_add_dl1 <=Packet_number_add;
Packet_number_add_dl2 <=Packet_number_add_dl1;
end
assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
always @ (Current_state_SYS or Next_state_SYS)
if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
Packet_number_sub =1;
else
Packet_number_sub =0;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Packet_number_inFF <=0;
else if (Packet_number_add_edge&&!Packet_number_sub)
Packet_number_inFF <=Packet_number_inFF + 1;
else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
Packet_number_inFF <=Packet_number_inFF - 1;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Fifo_data_count <=0;
else
Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Rx_Hwmark_pl <=0;
Rx_Lwmark_pl <=0;
end
else
begin
Rx_Hwmark_pl <=Rx_Hwmark;
Rx_Lwmark_pl <=Rx_Lwmark;
end
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_ra <=0;
else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
Rx_mac_ra <=0;
else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
Rx_mac_ra <=1;
//control Add_rd signal;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_rd <=0;
else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
Add_rd <=Add_rd + 1;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_rd_pl1 <=0;
else
Add_rd_pl1 <=Add_rd;
always @ (*)
if (Add_rd_pl1==Add_rd)
Addr_freshed_ptr =0;
else
Addr_freshed_ptr =1;
//
always @ (posedge Reset or posedge Clk_SYS)
if (Reset)
Add_rd_gray <=0;
else
begin
Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
end
//
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr_gray_dl1 <=0;
else
Add_wr_gray_dl1 <=Add_wr_gray;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr_jump_rd_pl1 <=0;
else
Add_wr_jump_rd_pl1 <=Add_wr_jump;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr_ungray =0;
else if (!Add_wr_jump_rd_pl1)
begin
Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
end
//empty signal gen
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Empty <=1;
else if (Add_rd==Add_wr_ungray)
Empty <=1;
else
Empty <=0;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Dout_dl1 <=0;
else
Dout_dl1 <=Dout;
assign Rx_mac_data =Dout_dl1[31:0];
assign Rx_mac_BE =Dout_dl1[33:32];
assign Rx_mac_eop =Dout_dl1[35];
//aligned to Addr_rd
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_pa_tmp <=0;
else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
Rx_mac_pa_tmp <=1;
else
Rx_mac_pa_tmp <=0;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_pa <=0;
else
Rx_mac_pa <=Rx_mac_pa_tmp;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_sop_tmp <=0;
else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
Rx_mac_sop_tmp <=1;
else
Rx_mac_sop_tmp <=0;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Rx_mac_sop_tmp_dl1 <=0;
Rx_mac_sop <=0;
end
else
begin
Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;
Rx_mac_sop <=Rx_mac_sop_tmp_dl1;
end
//******************************************************************************
duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
.data_a (Din ),
.wren_a (Wr_en ),
.address_a (Add_wr ),
.address_b (Add_rd ),
.clock_a (Clk_MAC ),
.clock_b (Clk_SYS ),
.q_b (Dout ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD3_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD3_SYMBOL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv3sd3 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD3_SYMBOL_V
|
// system_acl_iface_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.26.20:39:58
`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_1 (
input wire pll_outclk0_clk, // pll_outclk0.clk
input wire clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset, // clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset.reset
input wire [29:0] clock_cross_kernel_mem1_m0_address, // clock_cross_kernel_mem1_m0.address
output wire clock_cross_kernel_mem1_m0_waitrequest, // .waitrequest
input wire [4:0] clock_cross_kernel_mem1_m0_burstcount, // .burstcount
input wire [31:0] clock_cross_kernel_mem1_m0_byteenable, // .byteenable
input wire clock_cross_kernel_mem1_m0_read, // .read
output wire [255:0] clock_cross_kernel_mem1_m0_readdata, // .readdata
output wire clock_cross_kernel_mem1_m0_readdatavalid, // .readdatavalid
input wire clock_cross_kernel_mem1_m0_write, // .write
input wire [255:0] clock_cross_kernel_mem1_m0_writedata, // .writedata
input wire clock_cross_kernel_mem1_m0_debugaccess, // .debugaccess
output wire [24:0] address_span_extender_kernel_windowed_slave_address, // address_span_extender_kernel_windowed_slave.address
output wire address_span_extender_kernel_windowed_slave_write, // .write
output wire address_span_extender_kernel_windowed_slave_read, // .read
input wire [255:0] address_span_extender_kernel_windowed_slave_readdata, // .readdata
output wire [255:0] address_span_extender_kernel_windowed_slave_writedata, // .writedata
output wire [4:0] address_span_extender_kernel_windowed_slave_burstcount, // .burstcount
output wire [31:0] address_span_extender_kernel_windowed_slave_byteenable, // .byteenable
input wire address_span_extender_kernel_windowed_slave_readdatavalid, // .readdatavalid
input wire address_span_extender_kernel_windowed_slave_waitrequest // .waitrequest
);
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_waitrequest; // address_span_extender_kernel_windowed_slave_translator:uav_waitrequest -> clock_cross_kernel_mem1_m0_translator:uav_waitrequest
wire [9:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_burstcount; // clock_cross_kernel_mem1_m0_translator:uav_burstcount -> address_span_extender_kernel_windowed_slave_translator:uav_burstcount
wire [255:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_writedata; // clock_cross_kernel_mem1_m0_translator:uav_writedata -> address_span_extender_kernel_windowed_slave_translator:uav_writedata
wire [29:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_address; // clock_cross_kernel_mem1_m0_translator:uav_address -> address_span_extender_kernel_windowed_slave_translator:uav_address
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_lock; // clock_cross_kernel_mem1_m0_translator:uav_lock -> address_span_extender_kernel_windowed_slave_translator:uav_lock
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_write; // clock_cross_kernel_mem1_m0_translator:uav_write -> address_span_extender_kernel_windowed_slave_translator:uav_write
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_read; // clock_cross_kernel_mem1_m0_translator:uav_read -> address_span_extender_kernel_windowed_slave_translator:uav_read
wire [255:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdata; // address_span_extender_kernel_windowed_slave_translator:uav_readdata -> clock_cross_kernel_mem1_m0_translator:uav_readdata
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_debugaccess; // clock_cross_kernel_mem1_m0_translator:uav_debugaccess -> address_span_extender_kernel_windowed_slave_translator:uav_debugaccess
wire [31:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_byteenable; // clock_cross_kernel_mem1_m0_translator:uav_byteenable -> address_span_extender_kernel_windowed_slave_translator:uav_byteenable
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_kernel_windowed_slave_translator:uav_readdatavalid -> clock_cross_kernel_mem1_m0_translator:uav_readdatavalid
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (1),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) clock_cross_kernel_mem1_m0_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (clock_cross_kernel_mem1_m0_address), // avalon_anti_master_0.address
.av_waitrequest (clock_cross_kernel_mem1_m0_waitrequest), // .waitrequest
.av_burstcount (clock_cross_kernel_mem1_m0_burstcount), // .burstcount
.av_byteenable (clock_cross_kernel_mem1_m0_byteenable), // .byteenable
.av_read (clock_cross_kernel_mem1_m0_read), // .read
.av_readdata (clock_cross_kernel_mem1_m0_readdata), // .readdata
.av_readdatavalid (clock_cross_kernel_mem1_m0_readdatavalid), // .readdatavalid
.av_write (clock_cross_kernel_mem1_m0_write), // .write
.av_writedata (clock_cross_kernel_mem1_m0_writedata), // .writedata
.av_debugaccess (clock_cross_kernel_mem1_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (256),
.UAV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_kernel_windowed_slave_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_kernel_windowed_slave_address), // avalon_anti_slave_0.address
.av_write (address_span_extender_kernel_windowed_slave_write), // .write
.av_read (address_span_extender_kernel_windowed_slave_read), // .read
.av_readdata (address_span_extender_kernel_windowed_slave_readdata), // .readdata
.av_writedata (address_span_extender_kernel_windowed_slave_writedata), // .writedata
.av_burstcount (address_span_extender_kernel_windowed_slave_burstcount), // .burstcount
.av_byteenable (address_span_extender_kernel_windowed_slave_byteenable), // .byteenable
.av_readdatavalid (address_span_extender_kernel_windowed_slave_readdatavalid), // .readdatavalid
.av_waitrequest (address_span_extender_kernel_windowed_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule
|
`timescale 1 ns / 1 ps
`include "Speck_Block_Cipher_Multirate_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module Speck_Block_Cipher_Multirate_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
// zhiyang ong
// andrew mattheisen
// This version includes:
// HZ1 Detection and data forwarding for HZ1
// HZ2 detection was not necessary
// HZ3 Detection and data forwarding for HZ3
// Current bugs (...they're features, actually)
// No none current bugs!
/*
// this statement is for ncverilog only
`include "control.h"
`include "alu.v"
`include "control.v"
`include "mux128.v"
`include "pipe1.v"
`include "pipe2.v"
`include "pipe3.v"
`include "prog_counter2.v"
`include "regfileww.v"
`include "hazard_detect.v"
*/
// Synthesis include statements
`include "/home/scf-07/zhiyango/ee577b/projs/final/src/control.h"
`include "/home/scf-07/zhiyango/ee577b/projs/final/src/alu.v"
`include "/home/scf-07/zhiyango/ee577b/projs/final/src/control.v"
`include "/home/scf-07/zhiyango/ee577b/projs/final/src/mux128.v"
`include "/home/scf-07/zhiyango/ee577b/projs/final/src/pipe1.v"
`include "/home/scf-07/zhiyango/ee577b/projs/final/src/pipe2.v"
`include "/home/scf-07/zhiyango/ee577b/projs/final/src/pipe3.v"
`include "/home/scf-07/zhiyango/ee577b/projs/final/src/prog_counter2.v"
`include "/home/scf-07/zhiyango/ee577b/projs/final/src/regfileww.v"
`include "/home/scf-07/zhiyango/ee577b/projs/final/src/hazard_detect.v"
//Note that the following two lines were removed because the cpu.tb file integrates datamem
//`include datamem.v
//data_mem datamem1(data_out,data_in,mem_ctrl_addr,clk,dm_ctrl_sig);
module cpu(
clk,
reset,
instruction, // 32 bit instruction
pc, // 32 bit program counter
dataIn, // 128 bit data from dmem
dataOut, // 128 bit data to dmem
memAddr, // 21 bit immediate address, only 8 bits are used
memWrEn, // dmem write enable
memEn // dmem enable (to avoid spurious reads)
);
//INPUTS
input clk, reset;
input [0:31] instruction; // 32 bit instruction
input [0:127] dataIn; // 128 bit data from dmem
//OUTPUTS
output [0:31] pc; // 32 bit program counter
output [0:127] dataOut; // 128 bit data to dmem
output [0:21] memAddr; // 21 bit immediate address, only 8 bits are used
output memWrEn, // dmem write enable
memEn; // dmem enable (to avoid spurious reads)
// WIRES
wire [0:31] pc;
wire [0:31] instruction1, instruction2, instruction3;
wire [0:4] aluop, aluop2;
wire [0:1] ww, ww2;
wire [0:1] memop;
wire [0:20] memAddr_pre, memAddr;
wire [0:15] wbyteen, wbyteen2, wbyteen3;
wire [0:2] regop;
wire regwren2, regwren3;
wire [0:4] rrdaddra, rrdaddrb;
wire [0:4] rwraddrd, rwraddrd2, rwraddrd3;
wire [0:127] rd1data, rd1data2;
wire [0:127] rd2data, rd2data2, dataOut, dataIn, dataIn3;
wire reginmuxop, reginmuxop2, reginmuxop3;
wire aluinmuxop;
wire [0:127] immediate, immediate2;
wire [0:127] aluOut, aluOut3, wrdata;
wire memEn_pre, memWrEn_pre;
// Wires for data forwarding
wire hz1_a_or_d, hz1_b, hz3;
wire [0:127] rd2data_immediate, rega, hz1data;
wire hz3_a_or_d, hz3_b;
wire [0:127] regahz1, regbhz1;
// ------------- Stage 1 IF -----------------------
// modules for sturctural verilog
prog_counter2 programcounter(pc, reset, clk);
// imem is integrated in the testbench
pipe1 pipe1_1(instruction, instruction1, clk, reset);
// ------------- Stage 2 ID/RF ---------------------
control control1(instruction1, aluop, ww, memEn_pre, memWrEn_pre, memAddr_pre, wbyteen,
regop, rrdaddra, rrdaddrb, rwraddrd, reginmuxop, aluinmuxop, immediate);
regfileww regfile1(rd1data,rd2data,wrdata,rrdaddra,rrdaddrb,rwraddrd3,
regop[0],regop[1],regwren3,wbyteen3,clk);
mux128 aluinmux(rd2data, immediate2, rd2data_immediate, aluinmuxop2);
// HZ1 Data Forwarding Muxes
mux128 regb_df1_mux(rd2data_immediate, hz1data, regbhz1, hz1_b);
mux128 rega_df1_mux(rd1data, hz1data, regahz1, hz1_a_or_d);
// HZ3 Data Forwarding Muxes
mux128 regb_df3_mux(regbhz1, wrdata, dataOut, hz3_b);
mux128 rega_df3_mux(regahz1, wrdata, rega, hz3_a_or_d);
pipe2 pipe2_1(aluop, aluop2,
ww, ww2,
memEn_pre, memEn,
memWrEn_pre, memWrEn,
memAddr_pre, memAddr,
wbyteen, wbyteen2,
regop[2], regwren2,
rwraddrd, rwraddrd2,
reginmuxop, reginmuxop2,
aluinmuxop, aluinmuxop2,
immediate, immediate2,
wrdata, hz1data,
instruction1, instruction2,
clk,
reset);
// ------------- Stage 3 MEM/EX ---------------------
alu alu1(rega, dataOut, ww2, aluop2, aluOut);
//datamem - seperate module, integrated by testbench
pipe3 pipe3_1( dataIn, dataIn3,
wbyteen2, wbyteen3,
regwren2, regwren3,
rwraddrd2, rwraddrd3,
reginmuxop2, reginmuxop3,
aluOut, aluOut3,
instruction2, instruction3,
clk,
reset);
// ------------- Stage 4 WB ---------------------
mux128 reginmux(aluOut3,
dataIn,
wrdata,
reginmuxop3 );
// WR inputs of previously instantiated regfile used
// ------------- Hazard Detection -----------------
hazard_detect hazard_detect1(instruction1, instruction2, instruction3,
hz1_a_or_d, hz1_b, hz3_a_or_d, hz3_b);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cmp_top.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////
`include "sys_paths.h"
`include "sys.h"
`include "iop.h"
module cmp_top ();
wire rst_l ;
wire pwrok ;
wire [2:0] j_pack2 ;
wire [2:0] j_pack3 ;
wire [2:0] j_pack6 ;
wire [5:0] j_req_out_l_0 ;
wire [5:0] j_req_out_l_1 ;
wire [5:0] j_req_out_l_2 ;
wire [5:0] j_req_out_l_3 ;
wire [5:0] j_req_out_l_4 ;
wire [5:0] j_req_out_l_5 ;
wire [5:0] j_req_out_l_6 ;
wire [5:0] j_req_in_l_0 ;
wire [5:0] j_req_in_l_1 ;
wire [5:0] j_req_in_l_2 ;
wire [5:0] j_req_in_l_3 ;
wire [5:0] j_req_in_l_4 ;
wire [5:0] j_req_in_l_5 ;
wire [5:0] j_req_in_l_6 ;
reg [2:0] j_pack0_d1 ;
reg [2:0] j_pack0_d2 ;
reg [2:0] j_pack0_d3 ;
reg [2:0] j_pack1_d1 ;
reg [2:0] j_pack1_d2 ;
reg [2:0] j_pack1_d3 ;
reg j_fatal_error_l ;
reg [2:0] j_pack0_d ;
reg [2:0] j_pack1_d ;
reg [2:0] j_pack2_d ;
reg [2:0] j_pack3_d ;
reg [2:0] j_pack4_d ;
reg [2:0] j_pack5_d ;
reg [2:0] j_pack6_d ;
reg j_par_d1 ;
reg j_par_d2 ;
reg jbus_j_por_l_reg ;
reg jbi_io_j_ad_en_d ;
reg jbi_io_j_adp_en_d ;
reg jbi_io_j_adtype_en_d ;
reg jbi_io_j_pack0_en_d ;
reg jbi_io_j_pack1_en_d ;
reg [1:0] sjm_4_status ;
reg [1:0] sjm_5_status ;
reg trigger_sjm_4 ;
reg trigger_sjm_5 ;
reg reset_handler_done ;
integer sjm_init_status ;
wire start_sjm ;
wire jbus_j_por_l ;
wire j_change_l ;
wire j_clk ;
wire pwron_rst_l ;
wire j_rst_l ;
wire j_err_5 ;
wire xir_l ;
wire valid0 ;
wire valid1 ;
wire p_trdy ;
wire p_int_arb ;
wire g_int_arb ;
wire pci_master_rst_l ;
wire [7:0] pci_int1_l ;
wire [7:0] pci_int2_l ;
wire [7:0] pci_int3_l ;
wire [7:0] pci_int4_l ;
wire [5:0] pci_int5_l ;
wire [3:0] pci_int6_l ;
wire [3:0] pci_int7_l ;
wire [3:0] pci_int8_l ;
wire [7:4] pci_int4;
wire [5:0] int_in_l ;
wire p_clk ;
wire g_clk ;
wire g_rd_clk, g_rd_clk_l ;
wire g_upa_refclk, g_upa_refclk_l ;
wire upa_clk ;
wire p_bpclk ;
wire ichip_clk ;
wire p_rst_l ;
wire g_rst_l ;
wire [7:0] stub_done ;
wire [7:0] stub_pass ;
wire cken_off_done ;
wire warm_rst_l ;
wire warm_rst_trig_l ;
wire [7:0] pll_byp_offset ;
reg do_bist_warm_rst_trig_l ;
reg pwron_seq_done ;
reg trig_tap_cmd;
reg tap_end_cmd;
reg in_pll_byp;
integer delay;
wire [2:0] DBG_CK_P;
wire [2:0] DBG_CK_N;
wire [39:0] DBG_DQ;
wire DBG_VREF;
wire BURNIN;
wire [1:0] CLKOBS; // From iop of iop.v
wire [2:0] DIODE_TOP; // From iop of iop.v
wire MDC; // From iop of iop.v
wire SSI_MOSI; // From iop of iop.v
wire SSI_SCK; // From iop of iop.v
wire TDO; // From iop of iop.v
wire DO_BIST; // To iop of iop.v
wire DRAM01_N_REF_RES; // To iop of iop.v
wire DRAM01_P_REF_RES; // To iop of iop.v
wire DRAM02_SCL; // To cmp_dram of cmp_dram.v
wire DRAM13_SCL; // To cmp_dram of cmp_dram.v
wire DRAM23_N_REF_RES; // To iop of iop.v
wire DRAM23_P_REF_RES; // To iop of iop.v
wire DRAM_FAIL_OVER; // To cmp_dram of cmp_dram.v
wire [5:0] DRAM_FAIL_PART; // To cmp_dram of cmp_dram.v
wire EXT_INT_L; // To iop of iop.v
wire HSTL_VREF; // To iop of iop.v
wire JBUS_N_REF_RES; // To iop of iop.v
wire JBUS_P_REF_RES; // To iop of iop.v
wire [1:0] J_CLK; // To iop of iop.v
wire PGRM_EN; // To iop of iop.v
wire PWRON_RST_L; // To iop of iop.v
wire SSI_MISO; // To iop of iop.v
wire TCK; // To iop of iop.v
wire TCK2; // To iop of iop.v
wire TDI; // To iop of iop.v
wire TEMP_TRIG; // To iop of iop.v
wire TEST_MODE; // To iop of iop.v
wire TMS; // To iop of iop.v
wire TRIGIN; // To iop of iop.v
wire TRST_L; // To iop of iop.v
wire VDD_PLL; // To iop of iop.v
wire VDD_TSR; // To iop of iop.v
wire [2:0] XXSA; // To cmp_dram of cmp_dram.v
wire XXWP; // To cmp_dram of cmp_dram.v
wire DRAM02_SDA; // To/From cmp_dram of cmp_dram.v
wire [14:0] DRAM0_ADDR; // From iop of iop.v
wire [2:0] DRAM0_BA; // From iop of iop.v
wire DRAM0_CAS_L; // From iop of iop.v
wire [15:0] DRAM0_CB; // To/From iop of iop.v, ...
wire DRAM0_CKE; // From iop of iop.v
wire [3:0] DRAM0_CK_N; // From iop of iop.v
wire [3:0] DRAM0_CK_P; // From iop of iop.v
wire [3:0] DRAM0_CS_L; // From iop of iop.v
wire [127:0] DRAM0_DQ; // To/From iop of iop.v, ...
wire [35:0] DRAM0_DQS; // To/From iop of iop.v, ...
wire DRAM0_RAS_L; // From iop of iop.v
wire DRAM0_WE_L; // From iop of iop.v
wire DRAM13_SDA; // To/From cmp_dram of cmp_dram.v
wire [14:0] DRAM1_ADDR; // From iop of iop.v
wire [2:0] DRAM1_BA; // From iop of iop.v
wire DRAM1_CAS_L; // From iop of iop.v
wire [15:0] DRAM1_CB; // To/From iop of iop.v, ...
wire DRAM1_CKE; // From iop of iop.v
wire [3:0] DRAM1_CK_N; // From iop of iop.v
wire [3:0] DRAM1_CK_P; // From iop of iop.v
wire [3:0] DRAM1_CS_L; // From iop of iop.v
wire [127:0] DRAM1_DQ; // To/From iop of iop.v, ...
wire [35:0] DRAM1_DQS; // To/From iop of iop.v, ...
wire DRAM1_RAS_L; // From iop of iop.v
wire DRAM1_WE_L; // From iop of iop.v
wire [14:0] DRAM2_ADDR; // From iop of iop.v
wire [2:0] DRAM2_BA; // From iop of iop.v
wire DRAM2_CAS_L; // From iop of iop.v
wire [15:0] DRAM2_CB; // To/From iop of iop.v, ...
wire DRAM2_CKE; // From iop of iop.v
wire [3:0] DRAM2_CK_N; // From iop of iop.v
wire [3:0] DRAM2_CK_P; // From iop of iop.v
wire [3:0] DRAM2_CS_L; // From iop of iop.v
wire [127:0] DRAM2_DQ; // To/From iop of iop.v, ...
wire [35:0] DRAM2_DQS; // To/From iop of iop.v, ...
wire DRAM2_RAS_L; // From iop of iop.v
wire DRAM2_WE_L; // From iop of iop.v
wire [14:0] DRAM3_ADDR; // From iop of iop.v
wire [2:0] DRAM3_BA; // From iop of iop.v
wire DRAM3_CAS_L; // From iop of iop.v
wire [15:0] DRAM3_CB; // To/From iop of iop.v, ...
wire DRAM3_CKE; // From iop of iop.v
wire [3:0] DRAM3_CK_N; // From iop of iop.v
wire [3:0] DRAM3_CK_P; // From iop of iop.v
wire [3:0] DRAM3_CS_L; // From iop of iop.v
wire [127:0] DRAM3_DQ; // To/From iop of iop.v, ...
wire [35:0] DRAM3_DQS; // To/From iop of iop.v, ...
wire DRAM3_RAS_L; // From iop of iop.v
wire DRAM3_WE_L; // From iop of iop.v
wire [127:0] J_AD; // To/From iop of iop.v
wire [3:0] J_ADP; // To/From iop of iop.v
wire [7:0] J_ADTYPE; // To/From iop of iop.v
wire [2:0] J_PACK0; // To/From iop of iop.v
wire [2:0] J_PACK1; // To/From iop of iop.v
wire [2:0] J_PACK4; // To/From iop of iop.v
wire [2:0] J_PACK5; // To/From iop of iop.v
wire J_PAR; // To/From iop of iop.v
wire J_REQ0_OUT_L; // To/From iop of iop.v
wire J_REQ1_OUT_L; // To/From iop of iop.v
wire J_REQ4_IN_L; // To/From iop of iop.v
wire J_REQ5_IN_L; // To/From iop of iop.v
wire J_RST_L; // To/From iop of iop.v
wire SPARE_DDR0_PIN; // To/From iop of iop.v
wire [2:0] SPARE_DDR1_PIN;
wire [2:0] SPARE_DDR2_PIN; // To/From iop of iop.v
wire [2:0] SPARE_DDR3_PIN; // To/From iop of iop.v
wire SPARE_MISC_PIN; // To/From iop of iop.v
wire DTL_L_VREF; // To/From iop of iop.v
wire DTL_R_VREF; // To/From iop of iop.v
wire CLK_STRETCH; // To/From iop of iop.v
wire PMI; // To/From iop of iop.v
wire PLL_CHAR_IN; // To/From iop of iop.v
wire VREG_SELBG_L; // To/From iop of iop.v
wire SPARE_JBUSR_PIN; // To/From iop of iop.v
wire [1:0] TSR_TESTIO; // To/From iop of iop.v
wire [2:0] DIODE_BOT; // To/From iop of iop.v
reg [2048:0] filename;
// dummy wire used only by coreccx_coverage
wire [11:0] coreccx_pcx_retry_req_cov;
//wire for tap testing.
wire cmp_tck;
wire tclk;
`ifdef DRAM_SAT
wire clk_ddr_slfrsh ;
wire cmp_gclk ;
wire cmp_grst_l ;
wire cmp_grst ;
wire cmp_arst_l ;
wire cmp_gdbginit_l ;
wire cmp_adbginit_l ;
wire jbus_j_clk ;
//wire jbus_gclk = jbus_j_clk ;
wire jbus_gclk;
wire jbus_grst_l ;
wire jbus_arst_l ;
wire jbus_gdbginit_l ;
wire jbus_adbginit_l ;
wire dram_gclk ;
wire free_dram_gclk ;
wire dram_grst_l ;
wire dram_arst_l ;
wire dram_gdbginit_l ;
wire dram_adbginit_l ;
assign j_clk = jbus_j_clk;
assign cmp_top.iop.dram_gdbginit_l = dram_gdbginit_l ;
assign cmp_top.iop.dram_adbginit_l = dram_adbginit_l ;
assign cmp_top.iop.jbus_gdbginit_l = jbus_gdbginit_l ;
assign cmp_top.iop.jbus_adbginit_l = jbus_adbginit_l ;
assign cmp_top.iop.cmp_gdbginit_out_l = cmp_gdbginit_l ;
assign cmp_top.iop.cmp_adbginit_l = cmp_adbginit_l ;
assign cmp_top.iop.ccx_rclk = cmp_gclk; // ccx_rclk is the clock for L2-DRAM buffers.
assign cmp_top.iop.cmp_gclk = cmp_gclk ;
assign cmp_top.iop.dram_gclk = dram_gclk ;
assign cmp_top.iop.jbus_gclk = jbus_gclk ;
//assign cmp_top.iop.bscan_clock_dr_in = tck ;
assign cmp_top.iop.jbus_grst_l = jbus_grst_l ;
assign cmp_top.iop.dram_grst_l = dram_grst_l ;
assign cmp_top.iop.cmp_grst_out_l = cmp_grst_l ;
assign cmp_top.iop.jbus_arst_l = jbus_arst_l ;
assign cmp_top.iop.dram_arst_l = dram_arst_l ;
assign cmp_top.iop.cmp_arst_l = cmp_arst_l ;
assign cmp_grst = ~cmp_grst_l ;
`else
`ifdef MSS_SAT
// wires used by MSS coverage only
wire l2_iq_cas12_cov_0 = 0;
wire l2_iq_cas12_cov_1 = 0;
wire l2_iq_cas12_cov_2 = 0;
wire l2_iq_cas12_cov_3 = 0;
wire [13:0] l2_atomic_store_cov_0 = 0;
wire [13:0] l2_atomic_store_cov_1 = 0;
wire [13:0] l2_atomic_store_cov_2 = 0;
wire [13:0] l2_atomic_store_cov_3 = 0;
wire [2:0] l2_pst1_dataerr_pst2_tagerr_cov_0 = 0;
wire [2:0] l2_pst1_dataerr_pst2_tagerr_cov_1 = 0;
wire [2:0] l2_pst1_dataerr_pst2_tagerr_cov_2 = 0;
wire [2:0] l2_pst1_dataerr_pst2_tagerr_cov_3 = 0;
reg ctu_tst_pre_grst_l;
wire clk_ddr_slfrsh ;
wire cmp_gclk ;
wire cmp_rclk = cmp_top.iop.ccx.rclk ;
wire cmp_grst_l ;
wire cmp_grst ;
wire cmp_arst_l ;
wire cmp_gdbginit_l ;
wire cmp_adbginit_l ;
wire jbus_j_clk ;
//wire jbus_gclk = jbus_j_clk ;
wire jbus_gclk;
wire jbus_grst_l ;
wire jbus_arst_l ;
wire jbus_gdbginit_l ;
wire jbus_adbginit_l ;
wire dram_gclk ;
wire free_dram_gclk ;
wire dram_grst_l ;
wire dram_arst_l ;
wire dram_gdbginit_l ;
wire dram_adbginit_l ;
assign j_clk = jbus_j_clk;
assign cmp_top.iop.dram_gdbginit_l = dram_gdbginit_l ;
assign cmp_top.iop.dram_adbginit_l = dram_adbginit_l ;
assign cmp_top.iop.jbus_gdbginit_l = jbus_gdbginit_l ;
assign cmp_top.iop.jbus_adbginit_l = jbus_adbginit_l ;
assign cmp_top.iop.cmp_gdbginit_out_l = cmp_gdbginit_l ;
assign cmp_top.iop.cmp_adbginit_l = cmp_adbginit_l ;
assign cmp_top.iop.cmp_gclk = cmp_gclk ;
assign cmp_top.iop.dram_gclk = dram_gclk ;
assign cmp_top.iop.jbus_gclk = jbus_gclk ;
assign cmp_top.iop.jbus_grst_l = jbus_grst_l ;
assign cmp_top.iop.dram_grst_l = dram_grst_l ;
assign cmp_top.iop.cmp_grst_out_l = cmp_grst_l ;
assign cmp_top.iop.jbus_arst_l = jbus_arst_l ;
assign cmp_top.iop.dram_arst_l = dram_arst_l ;
assign cmp_top.iop.cmp_arst_l = cmp_arst_l ;
assign cmp_grst = ~cmp_grst_l ;
`else
wire clk_ddr_slfrsh ;
wire cmp_grst_l = cmp_top.iop.cmp_grst_out_l ;
wire cmp_grst = ~cmp_top.iop.cmp_grst_out_l ;
wire jbus_gclk = cmp_top.iop.jbus_gclk ;
wire cmp_gclk = cmp_top.iop.cmp_gclk ;
wire cmp_rclk = cmp_top.iop.sparc0.rclk ;
wire dram_gclk = cmp_top.iop.dram_gclk ;
wire jbus_j_clk = j_clk ;
wire jbus_j_clk_l = ~jbus_j_clk;
`endif // ifdef MSS_SAT
`endif // ifdef DRAM_SAT
////////////////////////////////////////////////////////
// jtag interface
////////////////////////////////////////////////////////
`ifdef DRAM_SAT
assign cmp_top.iop.ctu_misc_mode_ctl = 1'b0 ;
assign cmp_top.iop.ctu_misc_shift_dr = 1'b0 ;
assign cmp_top.iop.ctu_misc_hiz_l = 1'b0 ;
assign cmp_top.iop.ctu_misc_update_dr = 1'b0 ;
assign cmp_top.iop.ctu_misc_clock_dr = 1'b0 ;
assign cmp_top.iop.io_test_mode = 1'b0 ;
assign cmp_top.iop.ctu_ddr1_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr1_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr2_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr2_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr3_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr3_hiz_l = 0 ;
assign cmp_top.iop.ctu_dram02_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_dram13_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_ddr0_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr1_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr2_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr3_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram02_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram13_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram02_jbus_cken = 1 ;
assign cmp_top.iop.ctu_dram13_jbus_cken = 1 ;
assign cmp_top.iop.global_shift_enable = 1'b0 ;
assign cmp_top.iop.ctu_dram_selfrsh = clk_ddr_slfrsh;
assign cmp_top.iop.ctu_ddr0_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr0_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr_testmode_l = 1'b1;
assign cmp_top.iop.ctu_tst_scanmode = 0 ;
assign cmp_top.iop.ctu_tst_macrotest = 0 ;
assign cmp_top.iop.ctu_tst_pre_grst_l = 1 ;
assign cmp_top.iop.ctu_tst_scan_disable = 0 ;
`endif
`ifdef MSS_SAT
assign cmp_top.iop.ctu_misc_mode_ctl = 1'b0 ;
assign cmp_top.iop.ctu_misc_shift_dr = 1'b0 ;
assign cmp_top.iop.ctu_misc_hiz_l = 1'b0 ;
assign cmp_top.iop.ctu_misc_update_dr = 1'b0 ;
assign cmp_top.iop.ctu_misc_clock_dr = 1'b0 ;
assign cmp_top.iop.ctu_ddr0_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr1_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr2_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr3_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr0_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr1_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr2_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr3_mode_ctl = 0 ;
assign cmp_top.iop.ctu_scdata0_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_scdata1_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_scdata2_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_scdata3_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_sctag0_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_sctag1_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_sctag2_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_sctag3_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_ccx_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_ddr0_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr1_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr2_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr3_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram02_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_dram13_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_dram02_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram13_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram02_jbus_cken = 1 ;
assign cmp_top.iop.ctu_dram13_jbus_cken = 1 ;
assign cmp_top.iop.io_test_mode = 1'b0 ;
assign cmp_top.iop.global_shift_enable = 1'b0 ;
assign cmp_top.iop.ctu_dram_selfrsh = clk_ddr_slfrsh;
assign cmp_top.iop.ctu_ddr_testmode_l = 1'b1;
assign cmp_top.iop.ctu_tst_scanmode = 0 ;
assign cmp_top.iop.ctu_tst_macrotest = 0 ;
assign cmp_top.iop.ctu_tst_scan_disable = 0 ;
assign cmp_top.iop.ctu_sctag0_mbisten = 0;
assign cmp_top.iop.ctu_sctag1_mbisten = 0;
assign cmp_top.iop.ctu_sctag2_mbisten = 0;
assign cmp_top.iop.ctu_sctag3_mbisten = 0;
assign cmp_top.iop.ctu_tst_pre_grst_l = ctu_tst_pre_grst_l;
initial begin
ctu_tst_pre_grst_l = 0;
repeat(120) @(posedge cmp_gclk);
ctu_tst_pre_grst_l = 1;
end
`endif
////////////////////////////////////////////////////////
// OpenSPARCT1 instantiation
////////////////////////////////////////////////////////
OpenSPARCT1 iop(/*AUTOINST*/
// Outputs
.DRAM0_RAS_L (DRAM0_RAS_L),
.DRAM0_CAS_L (DRAM0_CAS_L),
.DRAM0_WE_L (DRAM0_WE_L),
.DRAM0_CS_L (DRAM0_CS_L[3:0]),
.DRAM0_CKE (DRAM0_CKE),
.DRAM0_ADDR (DRAM0_ADDR[14:0]),
.DRAM0_BA (DRAM0_BA[2:0]),
.DRAM0_CK_P (DRAM0_CK_P[3:0]),
.DRAM0_CK_N (DRAM0_CK_N[3:0]),
.DRAM1_RAS_L (DRAM1_RAS_L),
.DRAM1_CAS_L (DRAM1_CAS_L),
.DRAM1_WE_L (DRAM1_WE_L),
.DRAM1_CS_L (DRAM1_CS_L[3:0]),
.DRAM1_CKE (DRAM1_CKE),
.DRAM1_ADDR (DRAM1_ADDR[14:0]),
.DRAM1_BA (DRAM1_BA[2:0]),
.DRAM1_CK_P (DRAM1_CK_P[3:0]),
.DRAM1_CK_N (DRAM1_CK_N[3:0]),
.CLKOBS (CLKOBS[1:0]),
.DRAM2_RAS_L (DRAM2_RAS_L),
.DRAM2_CAS_L (DRAM2_CAS_L),
.DRAM2_WE_L (DRAM2_WE_L),
.DRAM2_CS_L (DRAM2_CS_L[3:0]),
.DRAM2_CKE (DRAM2_CKE),
.DRAM2_ADDR (DRAM2_ADDR[14:0]),
.DRAM2_BA (DRAM2_BA[2:0]),
.DRAM2_CK_P (DRAM2_CK_P[3:0]),
.DRAM2_CK_N (DRAM2_CK_N[3:0]),
.DRAM3_RAS_L (DRAM3_RAS_L),
.DRAM3_CAS_L (DRAM3_CAS_L),
.DRAM3_WE_L (DRAM3_WE_L),
.DRAM3_CS_L (DRAM3_CS_L[3:0]),
.DRAM3_CKE (DRAM3_CKE),
.DRAM3_ADDR (DRAM3_ADDR[14:0]),
.DRAM3_BA (DRAM3_BA[2:0]),
.DRAM3_CK_P (DRAM3_CK_P[3:0]),
.DRAM3_CK_N (DRAM3_CK_N[3:0]),
.J_PACK0 (J_PACK0[2:0]),
.J_PACK1 (J_PACK1[2:0]),
.J_REQ0_OUT_L (J_REQ0_OUT_L),
.J_REQ1_OUT_L (J_REQ1_OUT_L),
.J_ERR (J_ERR),
.TSR_TESTIO (TSR_TESTIO[1:0]),
.DIODE_TOP (DIODE_TOP[2:0]),
.DIODE_BOT (DIODE_BOT[2:0]),
.TDO (TDO),
.SSI_MOSI (SSI_MOSI),
.SSI_SCK (SSI_SCK),
.PMO (PMO),
.VDD_SENSE (VDD_SENSE),
.VSS_SENSE (VSS_SENSE),
// Inouts
.DBG_DQ (DBG_DQ[39:0]),
.DBG_CK_P (DBG_CK_P[2:0]),
.DBG_CK_N (DBG_CK_N[2:0]),
.DBG_VREF (DBG_VREF),
.DRAM0_DQ (DRAM0_DQ[127:0]),
.DRAM0_CB (DRAM0_CB[15:0]),
.DRAM0_DQS (DRAM0_DQS[35:0]),
.SPARE_DDR0_PIN (SPARE_DDR0_PIN),
.DRAM1_DQ (DRAM1_DQ[127:0]),
.DRAM1_CB (DRAM1_CB[15:0]),
.DRAM1_DQS (DRAM1_DQS[35:0]),
.SPARE_DDR1_PIN (SPARE_DDR1_PIN[2:0]),
.DRAM2_DQ (DRAM2_DQ[127:0]),
.DRAM2_CB (DRAM2_CB[15:0]),
.DRAM2_DQS (DRAM2_DQS[35:0]),
.SPARE_DDR2_PIN (SPARE_DDR2_PIN[2:0]),
.DRAM3_DQ (DRAM3_DQ[127:0]),
.DRAM3_CB (DRAM3_CB[15:0]),
.DRAM3_DQS (DRAM3_DQS[35:0]),
.SPARE_DDR3_PIN (SPARE_DDR3_PIN[2:0]),
.J_AD (J_AD[127:0]),
.J_ADP (J_ADP[3:0]),
.J_ADTYPE (J_ADTYPE[7:0]),
.J_PAR (J_PAR),
.SPARE_JBUSR_PIN (SPARE_JBUSR_PIN),
.VDDA (VDDA),
.VPP (VPP),
.SPARE_MISC_PIN (SPARE_MISC_PIN),
// Inputs
.BURNIN (BURNIN),
.DRAM01_P_REF_RES (DRAM01_P_REF_RES),
.DRAM01_N_REF_RES (DRAM01_N_REF_RES),
.DRAM23_P_REF_RES (DRAM23_P_REF_RES),
.DRAM23_N_REF_RES (DRAM23_N_REF_RES),
.J_PACK4 (J_PACK4[2:0]),
.J_PACK5 (J_PACK5[2:0]),
.J_REQ4_IN_L (J_REQ4_IN_L),
.J_REQ5_IN_L (J_REQ5_IN_L),
.J_RST_L (J_RST_L),
.DTL_L_VREF (DTL_L_VREF),
.DTL_R_VREF (DTL_R_VREF),
.JBUS_P_REF_RES (JBUS_P_REF_RES),
.JBUS_N_REF_RES (JBUS_N_REF_RES),
.J_CLK (J_CLK[1:0]),
.TCK (TCK),
.TCK2 (TCK2),
.TRST_L (TRST_L),
.TDI (TDI),
.TMS (TMS),
.TEST_MODE (TEST_MODE),
.PWRON_RST_L (PWRON_RST_L),
.SSI_MISO (SSI_MISO),
.CLK_STRETCH (CLK_STRETCH),
.DO_BIST (DO_BIST),
.EXT_INT_L (EXT_INT_L),
.PMI (PMI),
.PGRM_EN (PGRM_EN),
.PLL_CHAR_IN (PLL_CHAR_IN),
.VREG_SELBG_L (VREG_SELBG_L),
.TEMP_TRIG (TEMP_TRIG),
.TRIGIN (TRIGIN),
.HSTL_VREF (HSTL_VREF));
// .VDD_PLL (VDD_PLL),
// .VDD_TSR (VDD_TSR));
`ifdef RTL_DRAM02
// instantiate dram modules
cmp_dram cmp_dram(/*AUTOINST*/
// Inouts
.DRAM0_CB (DRAM0_CB[15:0]),
.DRAM0_DQ (DRAM0_DQ[127:0]),
.DRAM0_DQS (DRAM0_DQS[35:0]),
.DRAM1_CB (DRAM1_CB[15:0]),
.DRAM1_DQ (DRAM1_DQ[127:0]),
.DRAM1_DQS (DRAM1_DQS[35:0]),
.DRAM2_CB (DRAM2_CB[15:0]),
.DRAM2_DQ (DRAM2_DQ[127:0]),
.DRAM2_DQS (DRAM2_DQS[35:0]),
.DRAM3_CB (DRAM3_CB[15:0]),
.DRAM3_DQ (DRAM3_DQ[127:0]),
.DRAM3_DQS (DRAM3_DQS[35:0]),
.DRAM02_SDA (DRAM02_SDA),
.DRAM13_SDA (DRAM13_SDA),
// Inputs
.DRAM02_SCL (DRAM02_SCL),
.DRAM13_SCL (DRAM13_SCL),
.DRAM0_ADDR (DRAM0_ADDR[14:0]),
.DRAM0_BA (DRAM0_BA[2:0]),
.DRAM0_CAS_L (DRAM0_CAS_L),
.DRAM0_CKE (DRAM0_CKE),
.DRAM0_CK_N (DRAM0_CK_N[3:0]),
.DRAM0_CK_P (DRAM0_CK_P[3:0]),
.DRAM0_CS_L (DRAM0_CS_L[3:0]),
.DRAM0_RAS_L (DRAM0_RAS_L),
.DRAM0_RST_L (cmp_top.iop.cmp_grst_out_l), // Templated
.DRAM0_WE_L (DRAM0_WE_L),
.DRAM1_ADDR (DRAM1_ADDR[14:0]),
.DRAM1_BA (DRAM1_BA[2:0]),
.DRAM1_CAS_L (DRAM1_CAS_L),
.DRAM1_CKE (DRAM1_CKE),
.DRAM1_CK_N (DRAM1_CK_N[3:0]),
.DRAM1_CK_P (DRAM1_CK_P[3:0]),
.DRAM1_CS_L (DRAM1_CS_L[3:0]),
.DRAM1_RAS_L (DRAM1_RAS_L),
.DRAM1_RST_L (cmp_top.iop.cmp_grst_out_l), // Templated
.DRAM1_WE_L (DRAM1_WE_L),
.DRAM2_ADDR (DRAM2_ADDR[14:0]),
.DRAM2_BA (DRAM2_BA[2:0]),
.DRAM2_CAS_L (DRAM2_CAS_L),
.DRAM2_CKE (DRAM2_CKE),
.DRAM2_CK_N (DRAM2_CK_N[3:0]),
.DRAM2_CK_P (DRAM2_CK_P[3:0]),
.DRAM2_CS_L (DRAM2_CS_L[3:0]),
.DRAM2_RAS_L (DRAM2_RAS_L),
.DRAM2_RST_L (cmp_top.iop.cmp_grst_out_l), // Templated
.DRAM2_WE_L (DRAM2_WE_L),
.DRAM3_ADDR (DRAM3_ADDR[14:0]),
.DRAM3_BA (DRAM3_BA[2:0]),
.DRAM3_CAS_L (DRAM3_CAS_L),
.DRAM3_CKE (DRAM3_CKE),
.DRAM3_CK_N (DRAM3_CK_N[3:0]),
.DRAM3_CK_P (DRAM3_CK_P[3:0]),
.DRAM3_CS_L (DRAM3_CS_L[3:0]),
.DRAM3_RAS_L (DRAM3_RAS_L),
.DRAM3_RST_L (cmp_top.iop.cmp_grst_out_l), // Templated
.DRAM3_WE_L (DRAM3_WE_L),
.DRAM_FAIL_OVER (DRAM_FAIL_OVER),
.DRAM_FAIL_PART (DRAM_FAIL_PART[5:0]),
.XXSA (XXSA[2:0]),
.XXWP (XXWP),
.cmp_grst (cmp_grst),
.dram_gclk (cmp_top.iop.dram_gclk));
`endif
/*monitor AUTO_TEMPLATE
(
.rst_l(cmp_grst_l),
.clk(cmp_gclk),
);
*/
monitor monitor(/*AUTOINST*/
// Inputs
.clk (cmp_rclk), // Templated
.cmp_gclk (cmp_gclk), // Templated
.rst_l (cmp_grst_l)); // Templated
`ifdef RTL_IOBDG
dbg_port_chk dbg_port_chk () ;
`endif
cmp_mem cmp_mem();
`ifdef GATE_SIM
`else
`ifdef MSS_SAT
`else
`ifdef DRAM_SAT
err_inject err_inject();
`else
err_inject err_inject();
one_hot_mux_mon one_hot_mux_mon();
`endif // ifdef DRAM_SAT
`endif // ifdef MSS_SAT
`endif // ifdef GATE_SIM
`ifdef DRAM_SAT
`else
`ifdef MSS_SAT
slam_init slam_init();
pcx_stall pcx_stall();
cpx_stall cpx_stall();
`else
`ifdef GATE_SIM
`else
// randomly asserts sctag_pcx_stall_pq to exercise protocol adherence of Core
pcx_stall pcx_stall();
// randomly asserts CPX stall signal to make CPX packets arrive at the Cores in bursts
cpx_stall cpx_stall();
`endif // ifdef GATE_SIM
////////////////////////////////////////////////////////
// system interfaces - boot rom, external interrupts
////////////////////////////////////////////////////////
initial begin
$init_jbus_model("mem.image");
end
bw_sys bw_sys(/*AUTOINST*/
// Outputs
.ssi_miso (SSI_MISO),
.ext_int_l (EXT_INT_L),
.warm_rst_l (warm_rst_trig_l),
.temp_trig (TEMP_TRIG),
.clk_stretch (CLK_STRETCH),
// Inputs
.j_rst_l (j_rst_l),
.jbus_gclk (jbus_j_clk),
.ssi_sck (SSI_SCK),
.ssi_mosi (SSI_MOSI));
////////////////////////////////////////////////////////
// slam initial values into model
////////////////////////////////////////////////////////
slam_init slam_init () ;
////////////////////////////////////////////////////////
// efuse stub
////////////////////////////////////////////////////////
assign PGRM_EN = 0 ;
// efuse_stub efuse_stub (
// .efc_iob_coreavail_dshift (`TOP_MOD.iop.efc_iob_coreavail_dshift),
// .efc_iob_fuse_clk1 (`TOP_MOD.iop.efc_iob_fuse_clk1),
// .efc_iob_fuse_data (`TOP_MOD.iop.efc_iob_fuse_data),
// .efc_iob_fusestat_dshift (`TOP_MOD.iop.efc_iob_fusestat_dshift),
// .efc_iob_sernum0_dshift (`TOP_MOD.iop.efc_iob_sernum0_dshift),
// .efc_iob_sernum1_dshift (`TOP_MOD.iop.efc_iob_sernum1_dshift),
// .efc_iob_sernum2_dshift (`TOP_MOD.iop.efc_iob_sernum2_dshift),
// .jbus_arst_l (cmp_top.iop.jbus_arst_l),
// .jbus_gclk (jbus_j_clk)
// );
`endif // ifdef MSS_SAT
`endif // ifdef DRAM_SAT
////////////////////////////////////////////////////////
// clock generator stub
////////////////////////////////////////////////////////
`ifdef MSS_SAT
`define DRAM_OR_MSS_SAT
`else
`ifdef DRAM_SAT
`define DRAM_OR_MSS_SAT
`endif
`endif
`ifdef DRAM_OR_MSS_SAT
assign TCK = 1'b0 ;
assign TCK2 = 1'b0 ;
assign TEST_MODE = 1'b0 ;
sys_clk sys_clk (
// InOuts
.pwron_rst_l (pwron_rst_l),
.j_rst_l (j_rst_l),
.free_jbus_gclk (jbus_j_clk),
//.jbus_gclk (j_clk),
.jbus_gclk (jbus_gclk),
.free_clk (free_clk),
.dram_gclk (dram_gclk),
.free_dram_gclk (free_dram_gclk),
.cmp_gclk (cmp_gclk),
.pci_gclk (pci_gclk),
.io_gb_clkref (io_gb_clkref),
.jbus_grst_l (jbus_grst_l),
.cmp_grst_l (cmp_grst_l),
.dram_grst_l (dram_grst_l),
.jbus_arst_l (jbus_arst_l),
.cmp_arst_l (cmp_arst_l),
.dram_arst_l (dram_arst_l),
// .ctu_jbi_fst_rst_l (`TOP_MOD.iop.ctu_jbi_fst_rst_l),
.ctu_jbi_ssiclk (`TOP_MOD.iop.ctu_jbi_ssiclk),
.jbus_gdbginit_l (jbus_gdbginit_l),
.cmp_gdbginit_l (cmp_gdbginit_l),
.dram_gdbginit_l (dram_gdbginit_l),
.jbus_adbginit_l (jbus_adbginit_l),
.cmp_adbginit_l (cmp_adbginit_l),
.dram_adbginit_l (dram_adbginit_l),
.clspine_jbus_tx_sync (`TOP_MOD.iop.ctu_jbus_tx_sync_out),
.clspine_jbus_rx_sync (`TOP_MOD.iop.ctu_jbus_rx_sync_out),
.clspine_dram_tx_sync (`TOP_MOD.iop.ctu_dram_tx_sync_out),
.clspine_dram_rx_sync (`TOP_MOD.iop.ctu_dram_rx_sync_out),
// Inputs
.rst_l (rst_l));
`else
assign stub_pass[3] = 1'b1 ;
assign stub_done[3] = cken_off_done ;
assign TCK2 = TCK ;
// this part determines when to trigger a warm reset so that do_bist sequence can be driven
initial begin
pwron_seq_done = 1'b0 ;
do_bist_warm_rst_trig_l = 1'b1;
// wait for pwron_rst_l deassertion
@(posedge pwron_rst_l);
// wait for first deassertion of j_rst_l, cold pwron
@(posedge j_rst_l);
pwron_seq_done = 1'b1;
if ($test$plusargs("do_bist")) begin
// wait for wake thread to determine when efc array readout is done
// @(posedge cmp_top.iop.ctu_iob_wake_thr);
// need to be more deterministic, and since efc readout is deterministic, can hard set a wait time
// 22 cyles from deassertion of J_RST_L to efc_read_start, 8K to wake_thr
repeat (8022 * pll_byp_offset) @(posedge j_clk);
// trigger a warm reset
do_bist_warm_rst_trig_l = 1'b0;
@(posedge j_clk);
do_bist_warm_rst_trig_l = 1'b1;
end
end
assign warm_rst_l = j_fatal_error_l & warm_rst_trig_l & do_bist_warm_rst_trig_l;
cmp_clk cmp_clk (
.warm_rst_l (warm_rst_l), // input
.in_pll_byp (in_pll_byp), // input
.test_mode (TEST_MODE),
.cken_off_done (cken_off_done), // output
.tck (cmp_tck), // output
.pwron_rst_l (pwron_rst_l), // output
.j_rst_l (j_rst_l), // output
.xir_l (xir_l), // output
.pwrok (pwrok), // output
.j_clk (j_clk), // output
.pll_char_in (PLL_CHAR_IN), // output
.do_bist (DO_BIST), // output
.g_rd_clk (g_rd_clk), // output
.g_upa_refclk (g_upa_refclk), // output
.p_clk (p_clk), // output
.ichip_clk (ichip_clk)) ; // output
`endif // ifdef DRAM_OR_MSS_SAT
`ifdef DRAM_SAT
`else
`ifdef MSS_SAT
`else
////////////////////////////////////////////////////////
// iobridge rtl/stub
////////////////////////////////////////////////////////
`ifdef RTL_IOBDG
`else
ciop_iob ciop_iob(
// Outputs
.iob_clk_l2_tr (`TOP_MOD.iop.iob_ctu_l2_tr),
.iob_clk_tr (`TOP_MOD.iop.iob_ctu_tr),
.iob_cpx_data_ca (`TOP_MOD.iop.iob_cpx_data_ca[`CPX_WIDTH-1:0]),
.iob_cpx_req_cq (`TOP_MOD.iop.iob_cpx_req_cq[`IOB_CPU_WIDTH-1:0]),
.iob_ctu_coreavail (`TOP_MOD.iop.iob_ctu_coreavail[`IOB_CPU_WIDTH-1:0]),
.iob_io_dbg_data (`TOP_MOD.iop.iob_io_dbg_data[39:0]),
.iob_io_dbg_en (`TOP_MOD.iop.iob_io_dbg_en),
.iob_jbi_dbg_hi_data(`TOP_MOD.iop.iob_jbi_dbg_hi_data[47:0]),
.iob_jbi_dbg_hi_vld(`TOP_MOD.iop.iob_jbi_dbg_hi_vld),
.iob_jbi_dbg_lo_data(`TOP_MOD.iop.iob_jbi_dbg_lo_data[47:0]),
.iob_jbi_dbg_lo_vld(`TOP_MOD.iop.iob_jbi_dbg_lo_vld),
.iob_jbi_mondo_ack (`TOP_MOD.iop.iob_jbi_mondo_ack),
.iob_jbi_mondo_nack(`TOP_MOD.iop.iob_jbi_mondo_nack),
.iob_pcx_stall_pq (`TOP_MOD.iop.iob_pcx_stall_pq),
.iob_clk_data (`TOP_MOD.iop.iob_clsp_data[`IOB_CLK_WIDTH-1:0]),
.iob_clk_stall (`TOP_MOD.iop.iob_clsp_stall),
.iob_clk_vld (`TOP_MOD.iop.iob_clsp_vld),
.iob_dram02_data (`TOP_MOD.iop.iob_dram02_data[`IOB_DRAM_WIDTH-1:0]),
.iob_dram02_stall (`TOP_MOD.iop.iob_dram02_stall),
.iob_dram02_vld (`TOP_MOD.iop.iob_dram02_vld),
.iob_dram13_data (`TOP_MOD.iop.iob_dram13_data[`IOB_DRAM_WIDTH-1:0]),
.iob_dram13_stall (`TOP_MOD.iop.iob_dram13_stall),
.iob_dram13_vld (`TOP_MOD.iop.iob_dram13_vld),
.iob_jbi_pio_data (`TOP_MOD.iop.iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),
.iob_jbi_pio_stall (`TOP_MOD.iop.iob_jbi_pio_stall),
.iob_jbi_pio_vld (`TOP_MOD.iop.iob_jbi_pio_vld),
.iob_jbi_spi_data (`TOP_MOD.iop.iob_jbi_spi_data[`IOB_SPI_WIDTH-1:0]),
.iob_jbi_spi_stall (`TOP_MOD.iop.iob_jbi_spi_stall),
.iob_jbi_spi_vld (`TOP_MOD.iop.iob_jbi_spi_vld),
.iob_tap_data (`TOP_MOD.iop.iob_tap_data[`IOB_TAP_WIDTH-1:0]),
.iob_tap_stall (`TOP_MOD.iop.iob_tap_stall),
.iob_tap_vld (`TOP_MOD.iop.iob_tap_vld),
.iob_scanout (`TOP_MOD.iop.par_scan_tail[30]),
.iob_io_dbg_ck_p (`TOP_MOD.iop.iob_io_dbg_ck_p[2:0]),
.iob_io_dbg_ck_n (`TOP_MOD.iop.iob_io_dbg_ck_n[2:0]),
// Inputs
.clk_iob_cken (`TOP_MOD.iop.ctu_iob_jbus_cken),
.clspine_iob_resetstat (`TOP_MOD.iop.ctu_iob_resetstat[`IOB_RESET_STAT_WIDTH-1:0]),
.clspine_iob_resetstat_wr (`TOP_MOD.iop.ctu_iob_resetstat_wr),
.clspine_jbus_rx_sync (`TOP_MOD.iop.ctu_jbus_rx_sync_out),
.clspine_jbus_tx_sync (`TOP_MOD.iop.ctu_jbus_tx_sync_out),
.cpx_iob_grant_cx2 (`TOP_MOD.iop.cpx_iob_grant_cx2[`IOB_CPU_WIDTH-1:0]),
.ctu_iob_wake_thr (`TOP_MOD.iop.ctu_iob_wake_thr),
.jbi_iob_mondo_data(`TOP_MOD.iop.jbi_iob_mondo_data[`JBI_IOB_MONDO_BUS_WIDTH-1:0]),
.jbi_iob_mondo_vld (`TOP_MOD.iop.jbi_iob_mondo_vld),
.jbus_gclk (`TOP_MOD.iop.jbi.jbus_rclk),
.jbus_grst_l (`TOP_MOD.iop.jbi.jbus_grst_l),
.pcx_iob_data_px2 (`TOP_MOD.iop.pcx_iob_data_px2[`PCX_WIDTH-1:0]),
.pcx_iob_data_rdy_px2(`TOP_MOD.iop.pcx_iob_data_rdy_px2),
.dram02_iob_data (`TOP_MOD.iop.dram02_iob_data[`DRAM_IOB_WIDTH-1:0]),
.dram02_iob_stall (`TOP_MOD.iop.dram02_iob_stall),
.dram02_iob_vld (`TOP_MOD.iop.dram02_iob_vld),
.dram13_iob_data (`TOP_MOD.iop.dram13_iob_data[`DRAM_IOB_WIDTH-1:0]),
.dram13_iob_stall (`TOP_MOD.iop.dram13_iob_stall),
.dram13_iob_vld (`TOP_MOD.iop.dram13_iob_vld),
.jbi_iob_pio_data (`TOP_MOD.iop.jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),
.jbi_iob_pio_stall (`TOP_MOD.iop.jbi_iob_pio_stall),
.jbi_iob_pio_vld (`TOP_MOD.iop.jbi_iob_pio_vld),
.jbi_iob_spi_data (`TOP_MOD.iop.jbi_iob_spi_data[`SPI_IOB_WIDTH-1:0]),
.jbi_iob_spi_stall (`TOP_MOD.iop.jbi_iob_spi_stall),
.jbi_iob_spi_vld (`TOP_MOD.iop.jbi_iob_spi_vld),
`ifdef GATE_SIM_SPARC
.spc0_inst_done (`TOP_MOD.monitor.pc_cmp.spc0_inst_done),
.pc_w0 (`PCPATH0.ifu_fdp.pc_w),
`else
`ifdef RTL_SPARC0
.spc0_inst_done (`TOP_MOD.monitor.pc_cmp.spc0_inst_done),
.pc_w0 (`PCPATH0.fdp.pc_w),
`else
.spc0_inst_done (1'b0),
.pc_w0 (49'h0),
`endif
`endif // ifdef GATE_SIM_SPARC
`ifdef RTL_SPARC1
.spc1_inst_done (`TOP_MOD.monitor.pc_cmp.spc1_inst_done),
.pc_w1 (`PCPATH1.fdp.pc_w),
`else
.spc1_inst_done (1'b0),
.pc_w1 (49'h0),
`endif
`ifdef RTL_SPARC2
.spc2_inst_done (`TOP_MOD.monitor.pc_cmp.spc2_inst_done),
.pc_w2 (`PCPATH2.fdp.pc_w),
`else
.spc2_inst_done (1'b0),
.pc_w2 (49'h0),
`endif
`ifdef RTL_SPARC3
.spc3_inst_done (`TOP_MOD.monitor.pc_cmp.spc3_inst_done),
.pc_w3 (`PCPATH3.fdp.pc_w),
`else
.spc3_inst_done (1'b0),
.pc_w3 (49'h0),
`endif
`ifdef RTL_SPARC4
.spc4_inst_done (`TOP_MOD.monitor.pc_cmp.spc4_inst_done),
.pc_w4 (`PCPATH4.fdp.pc_w),
`else
.spc4_inst_done (1'b0),
.pc_w4 (49'h0),
`endif
`ifdef RTL_SPARC5
.spc5_inst_done (`TOP_MOD.monitor.pc_cmp.spc5_inst_done),
.pc_w5 (`PCPATH5.fdp.pc_w),
`else
.spc5_inst_done (1'b0),
.pc_w5 (49'h0),
`endif
`ifdef RTL_SPARC6
.spc6_inst_done (`TOP_MOD.monitor.pc_cmp.spc6_inst_done),
.pc_w6 (`PCPATH6.fdp.pc_w),
`else
.spc6_inst_done (1'b0),
.pc_w6 (49'h0),
`endif
`ifdef RTL_SPARC7
.spc7_inst_done (`TOP_MOD.monitor.pc_cmp.spc7_inst_done),
.pc_w7 (`PCPATH7.fdp.pc_w),
`else
.spc7_inst_done (1'b0),
.pc_w7 (49'h0),
`endif
.cmp_gclk (`TOP_MOD.iop.ccx.rclk));
`endif // ifdef RTL_IOBDG
`endif // ifdef MSS_SAT
`endif // ifdef DRAM_SAT
////////////////////////////////////////////////////////
// dft stuff
////////////////////////////////////////////////////////
// assign DO_BIST = 1'b0;
// assign CLK_STRETCH = 1'b0;
assign VREG_SELBG_L = 1'b0 ;
// assign PLL_CHAR_IN = 1'b0 ;
assign VDD_PLL = 1'b1 ;
assign VDD_TSR = 1'b1 ;
// flags for verification environment
reg fail_flag, diag_done;
initial begin
fail_flag = 0;
diag_done =0;
end // initial begin
// parse command line for monitors
initial begin
$monInit();
$monErrorDisable() ;
while (cmp_top.iop.jbus_grst_l !== 1'b0) @(posedge j_clk) ;
@(posedge cmp_top.iop.jbus_grst_l) ;
$monErrorEnable() ;
end
`ifdef DRAM_SAT
`else
`ifdef MSS_SAT
assign J_RST_L = j_rst_l ;
`else
////////////////////////////////////////////////////////
// jbus proper
////////////////////////////////////////////////////////
assign (weak0,weak1) J_AD = 128'hffffffffffffffffffffffffffffffff ;
assign (weak0,weak1) J_ADP = 4'b1111 ;
assign (weak0,weak1) J_ADTYPE = 8'b11111111 ;
assign (weak0,weak1) J_PACK0 = 3'b111 ;
assign (weak0,weak1) J_PACK1 = 3'b111 ;
assign (weak0,weak1) j_pack2 = 3'b111 ;
assign (weak0,weak1) j_pack3 = 3'b111 ;
assign (weak0,weak1) J_PACK4 = 3'b111 ;
assign (weak0,weak1) J_PACK5 = 3'b111 ;
assign (weak0,weak1) j_pack6 = 3'b111 ;
// for pll bypass case, to ensure repeatability we mask out the clock until
// entering bypass mode
reg j_clk_mask;
initial begin
j_clk_mask = 1'b1;
if ($test$plusargs("tap_pll_byp")) begin
if ($test$plusargs("mask_j_clk")) begin
$display("cmp_top.v: %0d masking j_clk", $time);
j_clk_mask = 1'b0;
@(posedge cmp_top.iop.ctu.pll_bypass);
repeat (4) @(posedge j_clk);
j_clk_mask = 1'b1;
$display("cmp_top.v: %0d unmasking j_clk", $time);
end
end
end
assign J_CLK [0] = j_clk & j_clk_mask;
assign J_CLK [1] = ~j_clk & j_clk_mask;
assign (weak0,weak1) j_req_out_l_0 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_1 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_2 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_3 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_4 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_5 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_6 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_0 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_1 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_2 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_3 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_4 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_5 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_6 = 6'b111111 ;
assign (weak0,weak1) j_change_l = 1'b1 ;
// bw pins
assign j_req_out_l_0 = {3{J_REQ1_OUT_L,J_REQ0_OUT_L}} ;
assign J_REQ4_IN_L = j_req_in_l_0 [3] ;
assign J_REQ5_IN_L = j_req_in_l_0 [4] ;
// bw
assign j_req_in_l_0 [3] = j_req_out_l_4 [0] ;
assign j_req_in_l_0 [4] = j_req_out_l_5 [0] ;
// sjm 4
assign j_req_in_l_4 [0] = j_req_out_l_5 [0] ;
assign j_req_in_l_4 [2] = j_req_out_l_0 [0] ;
assign j_req_in_l_4 [3] = j_req_out_l_1 [0] ;
// sjm 5
assign j_req_in_l_5 [1] = j_req_out_l_0 [1] ;
assign j_req_in_l_5 [2] = j_req_out_l_1 [0] ;
assign j_req_in_l_5 [5] = j_req_out_l_4 [0] ;
////////////////////////////////////////////////////////
// sjm
////////////////////////////////////////////////////////
initial begin
jbus_j_por_l_reg = 1'b0 ;
repeat (15) @(posedge jbus_j_clk) ;
jbus_j_por_l_reg = 1'b1 ;
end
assign jbus_j_por_l = jbus_j_por_l_reg ;
initial begin
$disable_errwarnmon();
end
// disable_errwarnmon is used to disable the dispmon error messages during reset
always @(negedge J_RST_L) begin
$dispmon("reset", 0, "Detected reset assertion. Will disable errwarnmon") ;
$disable_errwarnmon() ;
end
// enable_errwarnmon is used to enable the dispmon error messages after reset
always @(posedge J_RST_L) begin
if (pwron_seq_done == 1'b1) begin
$dispmon("reset", 0, "Detected reset deassertion. Will enable errwarnmon") ;
$enable_errwarnmon() ;
end
end
`ifdef NO_SJM
`else
// { start ifndef NO_SJM, SJM code segment
initial begin
// Trigger sjm stubs
trigger_sjm_4 = 1'b0;
trigger_sjm_5 = 1'b0;
// Drive reset to pci master stubs
reset_handler_done = 1'b0;
sjm_init_status = $sjm_init ;
end
always @(posedge j_clk) begin
while (cmp_top.iop.jbus_grst_l !== 1'b0) @(posedge j_clk) ;
// added to start sjms after second reset for tester runs
if ($test$plusargs("tester_rst_seq")) begin
repeat (2) @(posedge cmp_top.iop.jbus_grst_l) ;
end else
@(posedge cmp_top.iop.jbus_grst_l) ;
repeat (8) @(posedge j_clk) ;
trigger_sjm_4 = 1'b1;
trigger_sjm_5 = 1'b1;
reset_handler_done = 1'b1;
end
// } end ifndef NO_SJM, SJM code segment
`endif
assign stub_pass[1] = 1'b1 ; // sjm will die before getting here if a failure occurs
assign stub_done[1] = (sjm_4_status === 2'b11) ? 1'b1 : 1'b0 ;
`ifdef NO_SJM
`else
// { start ifndef NO_SJM, SJM code segment
////////////////////////////////////////////////////////
// sjm 4
////////////////////////////////////////////////////////
always @(posedge j_clk) begin
cmp_top.j_sjm_4.sjm_status (sjm_4_status) ;
// $info (0, "sjm 4 status %d", sjm_4_status);
end
always @ (posedge trigger_sjm_4) begin
$info (0, "Starting sjm_4 master devices");
cmp_top.j_sjm_4.sjm_start_executing;
end
jp_sjm j_sjm_4 (
.j_id (3'b100),
.j_req_in_l (j_req_in_l_4),
.j_req_out_l (j_req_out_l_4), //output
.j_ad (J_AD), //inout
.j_adp (J_ADP), //inout
.j_adtype (J_ADTYPE), //inout
.j_pack0 (J_PACK0), //inout
.j_pack1 (J_PACK1), //inout
.j_pack2 (j_pack2), //inout
.j_pack3 (j_pack3), //inout
.j_pack4 (J_PACK4), //inout
.j_pack5 (J_PACK5), //inout
.j_pack6 (j_pack6), //inout
.j_change_l (j_change_l), //inout
.j_rst_l (j_rst_l), //inout
.j_por_l (jbus_j_por_l), //inout
.j_clk (jbus_j_clk),
.pwr_ok (pwrok)
);
// } end ifndef NO_SJM, SJM code segment
`endif
assign stub_pass[2] = 1'b1 ; // sjm will die before getting here if a failure occurs
assign stub_done[2] = (sjm_5_status === 2'b11) ? 1'b1 : 1'b0 ;
// { start SJM_5 code segment
// These signals are driven by I/O Bridge when it is present
// in the system.
assign j_err_5 = 1'b0;
assign J_PAR = j_par_d2 ;
assign J_RST_L = j_rst_l ;
assign PWRON_RST_L = pwron_rst_l ;
assign p_rst_l = 1'b1;
assign g_rst_l = 1'b1;
////////////////////////////////////////////////////////
// jbus fatal error detection
////////////////////////////////////////////////////////
// DOK ON for 4 consecutive cycles indicates a fatal error. I/O Bridge
// should recognize this and assert j_rst_l.
always @(posedge jbus_j_clk) begin
j_pack0_d1 <= J_PACK0 ;
j_pack0_d2 <= j_pack0_d1 ;
j_pack0_d3 <= j_pack0_d2 ;
j_pack1_d1 <= J_PACK1 ;
j_pack1_d2 <= j_pack1_d1 ;
j_pack1_d3 <= j_pack1_d2 ;
j_fatal_error_l <= ((J_PACK0 === 3'h7) &&
(j_pack0_d1 === 3'h7) &&
(j_pack0_d2 === 3'h7) &&
(j_pack0_d3 === 3'h7)) ||
((J_PACK1 === 3'h7) &&
(j_pack1_d1 === 3'h7) &&
(j_pack1_d2 === 3'h7) &&
(j_pack1_d3 === 3'h7)) ? 1'b0 : 1'b1 ;
end
`ifdef NO_SJM
`else
// { start ifndef NO_SJM, SJM code segment
////////////////////////////////////////////////////////
// sjm 5
////////////////////////////////////////////////////////
always @(posedge j_clk) begin
cmp_top.j_sjm_5.sjm_status (sjm_5_status) ;
// $info (0, "sjm 5 status %d", sjm_5_status);
end
always @ (posedge trigger_sjm_5) begin
$info (0, "Starting sjm_5 master devices");
cmp_top.j_sjm_5.sjm_start_executing;
end
jp_sjm j_sjm_5 (
.j_id (3'b101),
.j_req_in_l (j_req_in_l_5),
.j_req_out_l (j_req_out_l_5), //output
.j_ad (J_AD), //inout
.j_adp (J_ADP), //inout
.j_adtype (J_ADTYPE), //inout
.j_pack0 (J_PACK0), //inout
.j_pack1 (J_PACK1), //inout
.j_pack2 (j_pack2), //inout
.j_pack3 (j_pack3), //inout
.j_pack4 (J_PACK4), //inout
.j_pack5 (J_PACK5), //inout
.j_pack6 (j_pack6), //inout
.j_change_l (j_change_l), //inout
.j_rst_l (j_rst_l), //inout
.j_por_l (jbus_j_por_l), //inout
.j_clk (jbus_j_clk),
.pwr_ok (pwrok)
);
// } end ifndef NO_SJM, SJM code segment
`endif
// } end SJM_5 code segment
////////////////////////////////////////////////////////
// parity generation
////////////////////////////////////////////////////////
always @(posedge jbus_j_clk) begin
j_pack0_d <= J_PACK0 ;
j_pack1_d <= J_PACK1 ;
j_pack2_d <= j_pack2 ;
j_pack3_d <= j_pack3 ;
j_pack4_d <= J_PACK4 ;
j_pack5_d <= J_PACK5 ;
j_pack6_d <= j_pack6 ;
j_par_d1 <= ~ ((j_req_out_l_0 [0]) ^
(j_req_out_l_1 [0]) ^
(j_req_out_l_2 [0]) ^
(j_req_out_l_3 [0]) ^
(j_req_out_l_4 [0]) ^
(j_req_out_l_5 [0]) ^
(j_req_out_l_6 [0]) ^
(^ j_pack0_d) ^
(^ j_pack1_d) ^
(^ j_pack2_d) ^
(^ j_pack3_d) ^
(^ j_pack4_d) ^
(^ j_pack5_d) ^
(^ j_pack6_d)) ;
j_par_d2 <= j_par_d1 ;
end
`ifdef NO_JBUS_MON
`else
////////////////////////////////////////////////////////
// jbus monitor
////////////////////////////////////////////////////////
always @(posedge diag_done) begin
$jbus_mon_finish;
end
jbus_monitor jbus_monitor (
.jbus_j_req_out_l_0 (j_req_out_l_0),
.jbus_j_req_out_l_1 (j_req_out_l_1),
.jbus_j_req_out_l_2 (j_req_out_l_2),
.jbus_j_req_out_l_3 (j_req_out_l_3),
.jbus_j_req_out_l_4 (j_req_out_l_4),
.jbus_j_req_out_l_5 (j_req_out_l_5),
.jbus_j_req_out_l_6 (j_req_out_l_6),
.jbus_j_ad (J_AD),
.jbus_j_adtype (J_ADTYPE),
.jbus_j_adp (J_ADP),
.jbus_j_pack0 (J_PACK0),
.jbus_j_pack1 (J_PACK1),
.jbus_j_pack2 (j_pack2),
.jbus_j_pack3 (j_pack3),
.jbus_j_pack4 (J_PACK4),
.jbus_j_pack5 (J_PACK5),
.jbus_j_pack6 (j_pack6),
.jbus_j_par (J_PAR),
.jbus_j_rst (j_rst_l),
.jbus_j_por (jbus_j_por_l),
.jbus_j_clk (jbus_j_clk),
.local_ports (7'h33),
.jbus_j_err ({1'b0, j_err_5, 5'h0}),
.jbus_j_change_l (j_change_l)
);
`endif // NO_JBUS_MON
`endif // ifdef MSS_SAT
`endif // ifdef DRAM_SAT
`ifdef INCLUDE_SAS_TASKS
// turn on sas interface after a delay
reg need_sas_sparc_intf_update;
initial begin
need_sas_sparc_intf_update = 0;
#12500;
need_sas_sparc_intf_update = 1;
end // initial begin
sas_intf sas_intf(/*AUTOINST*/
// Inputs
.clk (cmp_rclk), // Templated
.rst_l (cmp_grst_l)); // Templated
// create sas tasks
sas_tasks sas_tasks(/*AUTOINST*/
// Inputs
.clk (cmp_rclk), // Templated
.rst_l (cmp_grst_l)); // Templated
// sparc pipe flow monitor
sparc_pipe_flow sparc_pipe_flow(/*AUTOINST*/
// Inputs
.clk (cmp_rclk)); // Templated
// initialize client to communicate with ref model through socket
integer vsocket, i, list_handle;
initial begin
//list_handle = $bw_list(list_handle, 0);chin's change
//if not use sas, list should not be called
if($test$plusargs("use_sas_tasks"))begin
list_handle = $bw_list(list_handle, 0);
$bw_socket_init();
end
end
`endif // ifdef INCLUDE_SAS_TASKS
`ifdef GATE_SIM
initial $sdf_annotate ("cmp_top.sdf") ;
`endif
// This code is needed for production vector generation
// please do not remove it
`ifdef RTL_PAD_JBUSR
always @(posedge cmp_top.iop.pad_jbusr.clk) begin
jbi_io_j_ad_en_d = cmp_top.iop.pad_jbusr.jbi_io_j_ad_en ;
jbi_io_j_adp_en_d = cmp_top.iop.pad_jbusr.jbi_io_j_adp_en ;
jbi_io_j_adtype_en_d = cmp_top.iop.pad_jbusr.jbi_io_j_adtype_en ;
jbi_io_j_pack0_en_d = cmp_top.iop.pad_jbusr.jbi_io_j_pack0_en ;
jbi_io_j_pack1_en_d = cmp_top.iop.pad_jbusr.jbi_io_j_pack1_en ;
end
`endif
`ifdef NO_VERA
// { start of NO_VERA
// Sniper is not present when vera is missing ... tie the sparc
// ports off here
`ifdef RTL_SPARC0
`else
assign cmp_top.iop.spc0_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc0_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc0_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC1
`else
assign cmp_top.iop.spc1_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc1_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc1_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC2
`else
assign cmp_top.iop.spc2_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc2_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc2_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC3
`else
assign cmp_top.iop.spc3_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc3_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc3_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC4
`else
assign cmp_top.iop.spc4_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc4_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc4_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC5
`else
assign cmp_top.iop.spc5_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc5_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc5_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC6
`else
assign cmp_top.iop.spc6_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc6_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc6_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC7
`else
assign cmp_top.iop.spc7_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc7_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc7_pcx_atom_pq = 1'b0 ;
`endif
// } endif of NO_VERA
`endif
`ifdef MSS_SAT
`else
//tcl interface
`ifdef TCL_TAP_TEST
assign TCK = tclk;
tap tap( // Outputs
.stub_done (stub_done[0]),
.stub_pass(stub_pass[0]),
.trst_n (TRST_L),
.tms (TMS),
.tdi (TDI),
.trigin(TRIGIN),
.tclk(tclk),
// Inputs
.tdo (TDO),
.tck(cmp_tck)
);
`else
assign TCK = cmp_tck;
task send_tap_cmd;
begin
tap_end_cmd = 1'b1; // this will enable the final tap command that goes back to rst state
@(posedge j_clk);
trig_tap_cmd = 1'b1;
@(posedge j_clk);
trig_tap_cmd = 1'b0;
end
endtask
// all tap related commands
initial begin
trig_tap_cmd = 1'b0;
tap_end_cmd = 1'b0;
in_pll_byp = 1'b0;
if ($test$plusargs("tester_tap_seq")) begin
// pll bypass
if ($test$plusargs("tap_pll_byp")) begin
@(negedge cmp_top.tap_stub.stub_done); // wait for tap_stub to get ready
repeat (2) @(posedge TCK); // addition wait required for tap_stub
$display("cmp_top.v: %0d sending pll_bypass command thru tap", $time);
send_tap_cmd;
in_pll_byp = 1'b1;
end
// wait for first j_rst_l deassertion, warm reset
@(posedge pwron_seq_done);
// clock divider programming
if ($test$plusargs("tap_wr_clk_div")) begin
$display("cmp_top.v: %0d programming clk divs thru tap", $time);
repeat (200) @(posedge j_clk);
send_tap_cmd;
delay = 7350 - 200;
end
else begin
// 22 cycles, then efc_read_start issued, efc array readout will take 8K cycles
// inside the efc, the word addr count == 6'h3f at 7322 cycles, starting from pwron_seq_done
// question is to count 7350 or sync on the word addr count in the efc?
// why 7350? no particular reason. multiply by 4 during pll bypass mode
delay = 7350 * pll_byp_offset;
end
$display("cmp_top.v: %0d waiting %d jbus cycles for efc array readout", $time, delay);
repeat (delay) @(posedge j_clk);
// send efc_byp_data and efc_byp command
if ($test$plusargs("tap_efc_byp")) begin
$display("cmp_top.v: %0d sending efc_bypass_data and efc_bypass_cmd thru tap", $time);
send_tap_cmd;
end
// toggle out of pll_bypass
if ($test$plusargs("tap_clr_pll_bypass")) begin
send_tap_cmd;
end
// wait for start of warm rst, where bisi will started on do_bist pin
$display("cmp_top.v: %0d syncing on start of warm reset", $time);
@(negedge j_rst_l);
$display("cmp_top.v: %0d warm reset started", $time);
@(posedge j_clk);
// wait for end of warm_rst, when do_bist happens, then wait to issue bist_abort
$display("cmp_top.v: %0d syncing on end of warm reset", $time);
@(posedge j_rst_l);
$display("cmp_top.v: %0d end of warm reset detected", $time);
// bist_abort
if ($test$plusargs("tap_bist_abort")) begin
// bist_abort after 10K cpu cycles, in bypass mode cpu clk is same as j_clk
// in normal mode at 4:16 ratio, that comes to 2500 j_clk cycles
delay = 2500 * pll_byp_offset;
$display("cmp_top.v: %0d waiting %d jbus cycles before issuing bist_abort", $time, delay);
repeat (delay) @(posedge j_clk);
$display("cmp_top.v: %0d sending bist_abort thru tap", $time);
send_tap_cmd;
end
// the final tap command, go to reset state
if (tap_end_cmd == 1'b1) begin
$display("cmp_top.v: %0d sending tap end command", $time);
send_tap_cmd;
end
end
end
assign pll_byp_offset = 1 + (3 * in_pll_byp);
tap_stub tap_stub (
// Outputs
.stub_done (stub_done[0]),
.stub_pass (stub_pass[0]),
.trst_n (TRST_L),
.tms (TMS),
.tdi (TDI),
.trigin(TRIGIN),
// Inputs
.tdo (TDO),
.tck (TCK),
.diag_done (diag_done),
.trig_tap_cmd(trig_tap_cmd)
) ;
`endif
`endif
`ifdef FSDB_OFF
`else
// control dumping of debussy waveform
integer limitInMegaBytes;
initial begin
if ($test$plusargs("debussy")) begin
// the following must be specified before any other fsdb command
// [Viranjit 04/13/04]
if ($value$plusargs ("fsdbDumplimit=%d", limitInMegaBytes)) begin
$fsdbDumplimit(limitInMegaBytes);
end
if ($value$plusargs ("fsdbfile=%s", filename)) begin
$fsdbDumpfile(filename);
end
if ($test$plusargs("gate_sim")) begin
$fsdbDumpvars(1, cmp_top.iop);
`ifdef RTL_SPARC0
$fsdbDumpvars(1, cmp_top.iop.sparc0);
`endif
`ifdef RTL_SPARC1
$fsdbDumpvars(1, cmp_top.iop.sparc1);
`endif
`ifdef RTL_SPARC2
$fsdbDumpvars(1, cmp_top.iop.sparc2);
`endif
`ifdef RTL_SPARC3
$fsdbDumpvars(1, cmp_top.iop.sparc3);
`endif
`ifdef RTL_SPARC4
$fsdbDumpvars(1, cmp_top.iop.sparc4);
`endif
`ifdef RTL_SPARC5
$fsdbDumpvars(1, cmp_top.iop.sparc5);
`endif
`ifdef RTL_SPARC6
$fsdbDumpvars(1, cmp_top.iop.sparc6);
`endif
`ifdef RTL_SPARC7
$fsdbDumpvars(1, cmp_top.iop.sparc7);
`endif
end
else if ($test$plusargs("pinonly")) begin
$fsdbDumpvars(1, cmp_top.cmp_gclk);
$fsdbDumpvars(1, cmp_top.dram_gclk);
$fsdbDumpvars(1, cmp_top.jbus_gclk);
$fsdbDumpvars(1, cmp_top.iop.ctu_dram_rx_sync_out);
$fsdbDumpvars(1, cmp_top.iop.ctu_dram_tx_sync_out);
$fsdbDumpvars(1, cmp_top.iop.ctu_jbus_rx_sync_out);
$fsdbDumpvars(1, cmp_top.iop.ctu_jbus_tx_sync_out);
`ifdef GATE_SIM
`else
$fsdbDumpvars(1, cmp_top.iop.ctu.ctu_clsp.u_ctu_clsp_ctrl.text);
`endif
$fsdbDumpvars(1, cmp_top.DBG_CK_P);
$fsdbDumpvars(1, cmp_top.DBG_CK_N);
$fsdbDumpvars(1, cmp_top.DBG_DQ);
$fsdbDumpvars(1, cmp_top.DRAM0_RAS_L);
$fsdbDumpvars(1, cmp_top.DRAM0_CAS_L);
$fsdbDumpvars(1, cmp_top.DRAM0_WE_L);
$fsdbDumpvars(1, cmp_top.DRAM0_CS_L);
$fsdbDumpvars(1, cmp_top.DRAM0_CKE);
$fsdbDumpvars(1, cmp_top.DRAM0_ADDR);
$fsdbDumpvars(1, cmp_top.DRAM0_BA);
$fsdbDumpvars(1, cmp_top.ddr0_dq);
$fsdbDumpvars(1, cmp_top.ddr0_cb);
$fsdbDumpvars(1, cmp_top.DRAM0_DQS);
$fsdbDumpvars(1, cmp_top.DRAM0_CK_P);
$fsdbDumpvars(1, cmp_top.DRAM0_CK_N);
$fsdbDumpvars(1, cmp_top.SPARE_DDR0_PIN);
`ifdef RTL_PAD_DDR0
$fsdbDumpvars(1, cmp_top.ddr0_pad_dq_oe);
$fsdbDumpvars(1, cmp_top.ddr0_pad_dqs_oe);
`endif
$fsdbDumpvars(1, cmp_top.DRAM1_RAS_L);
$fsdbDumpvars(1, cmp_top.DRAM1_CAS_L);
$fsdbDumpvars(1, cmp_top.DRAM1_WE_L);
$fsdbDumpvars(1, cmp_top.DRAM1_CS_L);
$fsdbDumpvars(1, cmp_top.DRAM1_CKE);
$fsdbDumpvars(1, cmp_top.DRAM1_ADDR);
$fsdbDumpvars(1, cmp_top.DRAM1_BA);
$fsdbDumpvars(1, cmp_top.ddr1_dq);
$fsdbDumpvars(1, cmp_top.ddr1_cb);
$fsdbDumpvars(1, cmp_top.DRAM1_DQS);
$fsdbDumpvars(1, cmp_top.DRAM1_CK_P);
$fsdbDumpvars(1, cmp_top.DRAM1_CK_N);
$fsdbDumpvars(1, cmp_top.SPARE_DDR1_PIN);
`ifdef RTL_PAD_DDR1
$fsdbDumpvars(1, cmp_top.ddr1_pad_dq_oe);
$fsdbDumpvars(1, cmp_top.ddr1_pad_dqs_oe);
`endif
$fsdbDumpvars(1, cmp_top.CLKOBS);
$fsdbDumpvars(1, cmp_top.DRAM2_RAS_L);
$fsdbDumpvars(1, cmp_top.DRAM2_CAS_L);
$fsdbDumpvars(1, cmp_top.DRAM2_WE_L);
$fsdbDumpvars(1, cmp_top.DRAM2_CS_L);
$fsdbDumpvars(1, cmp_top.DRAM2_CKE);
$fsdbDumpvars(1, cmp_top.DRAM2_ADDR);
$fsdbDumpvars(1, cmp_top.DRAM2_BA);
$fsdbDumpvars(1, cmp_top.ddr2_dq);
$fsdbDumpvars(1, cmp_top.ddr2_cb);
$fsdbDumpvars(1, cmp_top.DRAM2_DQS);
$fsdbDumpvars(1, cmp_top.DRAM2_CK_P);
$fsdbDumpvars(1, cmp_top.DRAM2_CK_N);
$fsdbDumpvars(1, cmp_top.SPARE_DDR2_PIN);
`ifdef RTL_PAD_DDR2
$fsdbDumpvars(1, cmp_top.ddr2_pad_dq_oe);
$fsdbDumpvars(1, cmp_top.ddr2_pad_dqs_oe);
`endif
$fsdbDumpvars(1, cmp_top.DRAM3_RAS_L);
$fsdbDumpvars(1, cmp_top.DRAM3_CAS_L);
$fsdbDumpvars(1, cmp_top.DRAM3_WE_L);
$fsdbDumpvars(1, cmp_top.DRAM3_CS_L);
$fsdbDumpvars(1, cmp_top.DRAM3_CKE);
$fsdbDumpvars(1, cmp_top.DRAM3_ADDR);
$fsdbDumpvars(1, cmp_top.DRAM3_BA);
$fsdbDumpvars(1, cmp_top.ddr3_dq);
$fsdbDumpvars(1, cmp_top.ddr3_cb);
$fsdbDumpvars(1, cmp_top.DRAM3_DQS);
$fsdbDumpvars(1, cmp_top.DRAM3_CK_P);
$fsdbDumpvars(1, cmp_top.DRAM3_CK_N);
$fsdbDumpvars(1, cmp_top.SPARE_DDR3_PIN);
`ifdef RTL_PAD_DDR3
$fsdbDumpvars(1, cmp_top.ddr3_pad_dq_oe);
$fsdbDumpvars(1, cmp_top.ddr3_pad_dqs_oe);
`endif
$fsdbDumpvars(1, cmp_top.J_CLK);
$fsdbDumpvars(1, cmp_top.J_REQ4_IN_L);
$fsdbDumpvars(1, cmp_top.J_REQ5_IN_L);
$fsdbDumpvars(1, cmp_top.J_REQ0_OUT_L);
$fsdbDumpvars(1, cmp_top.J_REQ1_OUT_L);
$fsdbDumpvars(1, cmp_top.J_AD);
$fsdbDumpvars(1, cmp_top.J_ADP);
$fsdbDumpvars(1, cmp_top.J_ADTYPE);
$fsdbDumpvars(1, cmp_top.J_PACK0);
$fsdbDumpvars(1, cmp_top.J_PACK1);
$fsdbDumpvars(1, cmp_top.jbi_io_j_ad_en_d);
$fsdbDumpvars(1, cmp_top.jbi_io_j_adp_en_d);
$fsdbDumpvars(1, cmp_top.jbi_io_j_adtype_en_d);
$fsdbDumpvars(1, cmp_top.jbi_io_j_pack0_en_d);
$fsdbDumpvars(1, cmp_top.jbi_io_j_pack1_en_d);
$fsdbDumpvars(1, cmp_top.J_PACK4);
$fsdbDumpvars(1, cmp_top.J_PACK5);
$fsdbDumpvars(1, cmp_top.J_PAR);
$fsdbDumpvars(1, cmp_top.J_ERR);
$fsdbDumpvars(1, cmp_top.J_RST_L);
$fsdbDumpvars(1, cmp_top.SPARE_JBUSR_PIN);
$fsdbDumpvars(1, cmp_top.SPARE_MISC_PIN);
$fsdbDumpvars(1, cmp_top.BURNIN);
$fsdbDumpvars(1, cmp_top.TEMP_TRIG);
$fsdbDumpvars(1, cmp_top.PWRON_RST_L);
$fsdbDumpvars(1, cmp_top.TDI);
$fsdbDumpvars(1, cmp_top.TDO);
$fsdbDumpvars(1, cmp_top.TCK);
$fsdbDumpvars(1, cmp_top.TCK2);
$fsdbDumpvars(1, cmp_top.TRST_L);
$fsdbDumpvars(1, cmp_top.TMS);
$fsdbDumpvars(1, cmp_top.PLL_CHAR_IN);
$fsdbDumpvars(1, cmp_top.DO_BIST);
$fsdbDumpvars(1, cmp_top.TRIGIN);
$fsdbDumpvars(1, cmp_top.SSI_MOSI);
$fsdbDumpvars(1, cmp_top.SSI_MISO);
$fsdbDumpvars(1, cmp_top.SSI_SCK);
$fsdbDumpvars(1, cmp_top.EXT_INT_L);
$fsdbDumpvars(1, cmp_top.TEST_MODE);
$fsdbDumpvars(1, cmp_top.PGRM_EN);
$fsdbDumpvars(1, cmp_top.PMI);
$fsdbDumpvars(1, cmp_top.PMO);
$fsdbDumpvars(1, cmp_top.CLK_STRETCH);
$fsdbDumpvars(1, cmp_top.VREG_SELBG_L);
$fsdbDumpvars(1, cmp_top.iop.ctu_iob_wake_thr);
`ifdef RTL_IOBDG
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a4i0) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i0) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i1) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i2) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i3) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i6) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i7) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a3i7) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a3i6) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a3i3) ;
`endif
end
else if ($test$plusargs("gate_top"))
begin
$fsdbDumpvars(1,cmp_top.iop);
end
else begin
$fsdbDumpvars(0, cmp_top);
end
end
end
`endif
///////////////////////////////////////////////
// Generate fake OE for DQ and CB pads at DDR0.
///////////////////////////////////////////////
`ifdef RTL_PAD_DDR0
`ifdef GATE_SIM_DRAM
wire ddr0_pad_dqs_oe = cmp_top.iop.pad_ddr0.ddr0_ddr_ch_I0_I0_ddr_6sig0_dqs_pad0_dqs_edgelogic_oe_n ;
`else
wire ddr0_pad_dqs_oe = cmp_top.iop.pad_ddr0.ddr0_ddr_ch.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.oe ;
wire ddr0_drive_dqs_q = cmp_top.iop.pad_ddr0.ddr0_ddr_ch.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.drive_dqs_q;
wire ddr0_dqs_read = cmp_top.iop.pad_ddr0.ddr0_ddr_ch.I0.I0.ddr_6sig0.dq_pad0.dq_edgelogic.dqs_read;
`endif
dffrl_async #(1) flop_ddr0_oe(
.din(ddr0_drive_dqs_q),
.q(ddr0_pad_dq_oe),
.rst_l(pwron_rst_l),
.clk(~ddr0_dqs_read), .si(), .so(), .se(1'b0));
wire [127:0] ddr0_dq = ddr0_pad_dqs_oe & ddr0_pad_dq_oe ? cmp_top.DRAM0_DQ :
ddr0_pad_dqs_oe ? 128'hz :
cmp_top.DRAM0_DQ ;
wire [15:0] ddr0_cb = ddr0_pad_dqs_oe & ddr0_pad_dq_oe ? cmp_top.DRAM0_CB :
ddr0_pad_dqs_oe ? 16'hz :
cmp_top.DRAM0_CB;
`endif
///////////////////////////////////////////////
// FOR DDR1
///////////////////////////////////////////////
`ifdef RTL_PAD_DDR1
`ifdef GATE_SIM_DRAM
wire ddr1_pad_dqs_oe = cmp_top.iop.pad_ddr1.ddr1_ddr_ch_b_I0_I0_ddr_6sig0_dqs_pad0_dqs_edgelogic_oe_n ;
`else
wire ddr1_pad_dqs_oe = cmp_top.iop.pad_ddr1.ddr1_ddr_ch_b.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.oe ;
wire ddr1_drive_dqs_q = cmp_top.iop.pad_ddr1.ddr1_ddr_ch_b.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.drive_dqs_q;
wire ddr1_dqs_read = cmp_top.iop.pad_ddr1.ddr1_ddr_ch_b.I0.I0.ddr_6sig0.dq_pad0.dq_edgelogic.dqs_read;
`endif
dffrl_async #(1) flop_ddr1_oe(
.din(ddr1_drive_dqs_q),
.q(ddr1_pad_dq_oe),
.rst_l(pwron_rst_l),
.clk(~ddr1_dqs_read), .si(), .so(), .se(1'b0));
wire [127:0] ddr1_dq = ddr1_pad_dqs_oe & ddr1_pad_dq_oe ? cmp_top.DRAM1_DQ :
ddr1_pad_dqs_oe ? 128'hz :
cmp_top.DRAM1_DQ ;
wire [15:0] ddr1_cb = ddr1_pad_dqs_oe & ddr1_pad_dq_oe ? cmp_top.DRAM1_CB :
ddr1_pad_dqs_oe ? 16'hz :
cmp_top.DRAM1_CB;
`endif
///////////////////////////////////////////////
// FOR DDR2
///////////////////////////////////////////////
`ifdef RTL_PAD_DDR2
`ifdef GATE_SIM_DRAM
wire ddr2_pad_dqs_oe = cmp_top.iop.pad_ddr2.ddr2_ddr_ch_I0_I0_ddr_6sig0_dqs_pad0_dqs_edgelogic_oe_n ;
`else
wire ddr2_pad_dqs_oe = cmp_top.iop.pad_ddr2.ddr2_ddr_ch.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.oe ;
wire ddr2_drive_dqs_q = cmp_top.iop.pad_ddr2.ddr2_ddr_ch.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.drive_dqs_q;
wire ddr2_dqs_read = cmp_top.iop.pad_ddr2.ddr2_ddr_ch.I0.I0.ddr_6sig0.dq_pad0.dq_edgelogic.dqs_read;
`endif
dffrl_async #(1) flop_ddr2_oe(
.din(ddr2_drive_dqs_q),
.q(ddr2_pad_dq_oe),
.rst_l(pwron_rst_l),
.clk(~ddr2_dqs_read), .si(), .so(), .se(1'b0));
wire [127:0] ddr2_dq = ddr2_pad_dqs_oe & ddr2_pad_dq_oe ? cmp_top.DRAM2_DQ :
ddr2_pad_dqs_oe ? 128'hz :
cmp_top.DRAM2_DQ ;
wire [15:0] ddr2_cb = ddr2_pad_dqs_oe & ddr2_pad_dq_oe ? cmp_top.DRAM2_CB :
ddr2_pad_dqs_oe ? 16'hz :
cmp_top.DRAM2_CB;
`endif
///////////////////////////////////////////////
// FOR DDR3
///////////////////////////////////////////////
`ifdef RTL_PAD_DDR3
`ifdef GATE_SIM_DRAM
wire ddr3_pad_dqs_oe = cmp_top.iop.pad_ddr3.ddr3_ddr_ch_b_I0_I0_ddr_6sig2_dqs_pad0_dqs_edgelogic_oe_n ;
`else
wire ddr3_pad_dqs_oe = cmp_top.iop.pad_ddr3.ddr3_ddr_ch_b.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.oe ;
wire ddr3_drive_dqs_q = cmp_top.iop.pad_ddr3.ddr3_ddr_ch_b.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.drive_dqs_q;
wire ddr3_dqs_read = cmp_top.iop.pad_ddr3.ddr3_ddr_ch_b.I0.I0.ddr_6sig0.dq_pad0.dq_edgelogic.dqs_read;
`endif
dffrl_async #(1) flop_ddr3_oe(
.din(ddr3_drive_dqs_q),
.q(ddr3_pad_dq_oe),
.rst_l(pwron_rst_l),
.clk(~ddr3_dqs_read), .si(), .so(), .se(1'b0));
wire [127:0] ddr3_dq = ddr3_pad_dqs_oe & ddr3_pad_dq_oe ? cmp_top.DRAM3_DQ :
ddr3_pad_dqs_oe ? 128'hz :
cmp_top.DRAM3_DQ ;
wire [15:0] ddr3_cb = ddr3_pad_dqs_oe & ddr3_pad_dq_oe ? cmp_top.DRAM3_CB :
ddr3_pad_dqs_oe ? 16'hz :
cmp_top.DRAM3_CB;
`endif
endmodule // cmp_top
|
/**************************************************************************
*
* File Name: MT48LC8M16A2.V
* Version: 2.1
* Date: June 6th, 2002
* Model: BUS Functional
* Simulator: Model Technology
*
* Dependencies: None
*
* Email: [email protected]
* Company: Micron Technology, Inc.
* Model: MT48LC8M16A2 (2Meg x 16 x 4 Banks)
*
* Description: Micron 128Mb SDRAM Verilog model
*
* Limitation: - Doesn't check for 8192 cycle refresh
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
* Copyright © 2001 Micron Semiconductor Products, Inc.
* All rights researved
*
* Rev Author Date Changes
* --- -------------------------- ---------------------------------------
* 2.1 SH 06/06/2002 - Typo in bank multiplex
* Micron Technology Inc.
*
* 2.0 SH 04/30/2002 - Second release
* Micron Technology Inc.
*
**************************************************************************/
`timescale 1ns / 1ps
module mt48lc8m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
parameter addr_bits = 12;
parameter data_bits = 16;
parameter col_bits = 9;
parameter mem_sizes = 2097151;
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [1 : 0] Dqm;
reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
reg [addr_bits - 1 : 0] Mode_reg;
reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
reg [col_bits - 1 : 0] Col_temp, Burst_counter;
reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank)
reg Read_precharge [0 : 3]; // R Auto Precharge
reg Write_precharge [0 : 3]; // W Auto Precharge
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank
integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter
integer Count_precharge [0 : 3]; // RW Auto Precharge Counter
reg Data_in_enable;
reg Data_out_enable;
reg [1 : 0] Bank, Prev_bank;
reg [addr_bits - 1 : 0] Row;
reg [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
reg CkeZ, Sys_clk;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
// CAS Latency Decode
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
// wire Debug = 1'b1; // Debug messages : 1 = On
wire Debug = 1'b0; // Debug messages : 1 = On
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
assign Dq = Dq_reg; // DQ buffer
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define WRITE 3
`define PRECH 4
`define A_REF 5
`define BST 6
`define LMR 7
// Timing Parameters for -7E PC133 CL2
parameter tAC = 5.4;
parameter tHZ = 5.4;
parameter tOH = 3.0;
parameter tMRD = 2.0; // 2 Clk Cycles
parameter tRAS = 37.0;
parameter tRC = 60.0;
parameter tRCD = 15.0;
parameter tRFC = 66.0;
parameter tRP = 15.0;
parameter tRRD = 14.0;
parameter tWRa = 7.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns)
parameter tWRm = 14.0; // A2 Version - Manual precharge mode (14 ns)
// Timing Check variable
time MRD_chk;
time WR_chkm [0 : 3];
time RFC_chk, RRD_chk;
time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
initial begin
Dq_reg = {data_bits{1'bz}};
Data_in_enable = 0; Data_out_enable = 0;
Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0;
RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
MRD_chk = 0; RFC_chk = 0; RRD_chk = 0;
RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
$timeformat (-9, 1, " ns", 12);
end
// System clock generator
always begin
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge Clk) begin
Sys_clk = 1'b0;
end
end
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {col_bits{1'b0}};
Bank_addr[0] = Bank_addr[1];
Bank_addr[1] = Bank_addr[2];
Bank_addr[2] = Bank_addr[3];
Bank_addr[3] = 2'b0;
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = 2'b0;
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1'b0;
// Dqm pipeline for Read
Dqm_reg0 = Dqm_reg1;
Dqm_reg1 = Dqm;
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] === 1'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] === 1'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] === 1'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] === 1'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
// Read or Write Interrupt Counter
if (RW_interrupt_write[0] === 1'b1) begin
RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
end
if (RW_interrupt_write[1] === 1'b1) begin
RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
end
if (RW_interrupt_write[2] === 1'b1) begin
RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
end
if (RW_interrupt_write[3] === 1'b1) begin
RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
end
// tMRD Counter
MRD_chk = MRD_chk + 1;
// Auto Refresh
if (Aref_enable === 1'b1) begin
if (Debug) begin
$display ("%m : at time %t AREF : Auto Refresh", $time);
end
// Auto Refresh to Auto Refresh
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Load Mode Register to Auto Refresh
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time);
end
// Record Current tRFC time
RFC_chk = $time;
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
// Register Mode
Mode_reg = Addr;
// Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
if (Debug) begin
$display ("%m : at time %t LMR : Load Mode Register", $time);
// CAS Latency
case (Addr[6 : 4])
3'b010 : $display ("%m : CAS Latency = 2");
3'b011 : $display ("%m : CAS Latency = 3");
default : $display ("%m : CAS Latency = Reserved");
endcase
// Burst Length
case (Addr[2 : 0])
3'b000 : $display ("%m : Burst Length = 1");
3'b001 : $display ("%m : Burst Length = 2");
3'b010 : $display ("%m : Burst Length = 4");
3'b011 : $display ("%m : Burst Length = 8");
3'b111 : $display ("%m : Burst Length = Full");
default : $display ("%m : Burst Length = Reserved");
endcase
// Burst Type
if (Addr[3] === 1'b0) begin
$display ("%m : Burst Type = Sequential");
end else if (Addr[3] === 1'b1) begin
$display ("%m : Burst Type = Interleaved");
end else begin
$display ("%m : Burst Type = Reserved");
end
// Write Burst Mode
if (Addr[9] === 1'b0) begin
$display ("%m : Write Burst Mode = Programmed Burst Length");
end else if (Addr[9] === 1'b1) begin
$display ("%m : Write Burst Mode = Single Location Access");
end else begin
$display ("%m : Write Burst Mode = Reserved");
end
end
// Precharge to Load Mode Register
if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// Precharge to Load Mode Register
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time);
end
// Auto Refresh to Load Mode Register
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time);
end
// Load Mode Register to Load Mode Register
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
// Reset MRD Counter
MRD_chk = 0;
end
// Active Block (Latch Bank Address and Row Address)
if (Active_enable === 1'b1) begin
// Activate an open bank can corrupt data
if ((Ba === 2'b00 && Act_b0 === 1'b1) || (Ba === 2'b01 && Act_b1 === 1'b1) ||
(Ba === 2'b10 && Act_b2 === 1'b1) || (Ba === 2'b11 && Act_b3 === 1'b1)) begin
$display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time);
$stop; // JEA debug
end
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 0 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk0 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time);
end
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time);
end
// Record variables
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk0 = $time;
RC_chk0 = $time;
RCD_chk0 = $time;
end
if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 1 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk1 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time);
end
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time);
end
// Record variables
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk1 = $time;
RC_chk1 = $time;
RCD_chk1 = $time;
end
if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 2 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk2 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time);
end
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time);
end
// Record variables
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk2 = $time;
RC_chk2 = $time;
RCD_chk2 = $time;
end
if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 3 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk3 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time);
end
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time);
end
// Record variables
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk3 = $time;
RC_chk3 = $time;
RCD_chk3 = $time;
end
// Active Bank A to Active Bank B
if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
end
// Auto Refresh to Activate
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $time, Ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
$display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
end
// Record variables for checking violation
RRD_chk = $time;
Prev_bank = Ba;
end
// Precharge Block
if (Prech_enable == 1'b1) begin
// Load Mode Register to Precharge
if ($time - MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time);
end
// Precharge Bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $time;
// Activate to Precharge
if ($time - RAS_chk0 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[0] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $time;
// Activate to Precharge
if ($time - RAS_chk1 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[1] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $time;
// Activate to Precharge
if ($time - RAS_chk2 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[2] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $time;
// Activate to Precharge
if ($time - RAS_chk3 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[3] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin
Data_in_enable = 1'b0;
end
// Precharge Command Pipeline for Read
if (Cas_latency_3 === 1'b1) begin
Command[2] = `PRECH;
Bank_precharge[2] = Ba;
A10_precharge[2] = Addr[10];
end else if (Cas_latency_2 === 1'b1) begin
Command[1] = `PRECH;
Bank_precharge[1] = Ba;
A10_precharge[1] = Addr[10];
end
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 === 1'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `BST;
end
// Display debug message
if (Debug) begin
$display ("%m : at time %t BST : Burst Terminate",$time);
end
end
// Read, Write, Column Latch
if (Read_enable === 1'b1) begin
// Check to see if bank is open (ACT)
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Read", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// CAS Latency pipeline
if (Cas_latency_3 == 1'b1) begin
Command[2] = `READ;
Col_addr[2] = Addr;
Bank_addr[2] = Ba;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `READ;
Col_addr[1] = Addr;
Bank_addr[1] = Ba;
end
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
RW_interrupt_counter[RW_interrupt_bank] = 0;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time);
end
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Read_precharge[Ba] = 1'b1;
end
end
// Write Command
if (Write_enable == 1'b1) begin
// Activate to Write
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Write", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// Latch Write command, Bank, and Column
Command[0] = `WRITE;
Col_addr[0] = Addr;
Bank_addr[0] = Ba;
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Read Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
end
end
end
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
// Interrupting a Read with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_read[RW_interrupt_bank] = 1'b1;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
end
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Write_precharge[Ba] = 1'b1;
end
end
/*
Write with Auto Precharge Calculation
The device start internal precharge when:
1. Meet minimum tRAS requirement
and 2. tWR cycle(s) after last valid data
or 3. Interrupt by a Read or Write (with or without Auto Precharge)
Note: Model is starting the internal precharge 1 cycle after they meet all the
requirement but tRP will be compensate for the time after the 1 cycle.
*/
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3
Auto_precharge[0] = 1'b0;
Write_precharge[0] = 1'b0;
RW_interrupt_write[0] = 1'b0;
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3
Auto_precharge[1] = 1'b0;
Write_precharge[1] = 1'b0;
RW_interrupt_write[1] = 1'b0;
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3
Auto_precharge[2] = 1'b0;
Write_precharge[2] = 1'b0;
RW_interrupt_write[2] = 1'b0;
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3
Auto_precharge[3] = 1'b0;
Write_precharge[3] = 1'b0;
RW_interrupt_write[3] = 1'b0;
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. Meet minimum tRAS requirement
// and 2. CAS Latency - 1 cycles before last burst
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 1
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1'b1)) begin // Case 3
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Auto_precharge[0] = 1'b0;
Read_precharge[0] = 1'b0;
RW_interrupt_read[0] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1'b1)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Auto_precharge[1] = 1'b0;
Read_precharge[1] = 1'b0;
RW_interrupt_read[1] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1'b1)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Auto_precharge[2] = 1'b0;
Read_precharge[2] = 1'b0;
RW_interrupt_read[2] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1'b1)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Auto_precharge[3] = 1'b0;
Read_precharge[3] = 1'b0;
RW_interrupt_read[3] = 1'b0;
if (Debug) begin
$display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
if (Data_out_enable == 1'b0) begin
Dq_reg <= #tOH {data_bits{1'bz}};
end
// Detect Read or Write command
if (Command[0] == `READ) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b0;
Data_out_enable = 1'b1;
end else if (Command[0] == `WRITE) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b1;
Data_out_enable = 1'b0;
end
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1'b1) begin // Writing Data to Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0 [{Row, Col}];
2'b01 : Dq_dqm = Bank1 [{Row, Col}];
2'b10 : Dq_dqm = Bank2 [{Row, Col}];
2'b11 : Dq_dqm = Bank3 [{Row, Col}];
endcase
// Dqm operation
if (Dqm[0] == 1'b0) begin
Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
end
if (Dqm[1] == 1'b0) begin
Dq_dqm [15 : 8] = Dq [15 : 8];
end
// Write to memory
case (Bank)
2'b00 : Bank0 [{Row, Col}] = Dq_dqm;
2'b01 : Bank1 [{Row, Col}] = Dq_dqm;
2'b10 : Bank2 [{Row, Col}] = Dq_dqm;
2'b11 : Bank3 [{Row, Col}] = Dq_dqm;
endcase
// Display debug message
if (Dqm !== 2'b11) begin
// Record tWR for manual precharge
WR_chkm [Bank] = $time;
if (Debug) begin
$display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_dqm);
end
end else begin
if (Debug) begin
$display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end
end
// Advance burst counter subroutine
#tHZ Burst_decode;
end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0[{Row, Col}];
2'b01 : Dq_dqm = Bank1[{Row, Col}];
2'b10 : Dq_dqm = Bank2[{Row, Col}];
2'b11 : Dq_dqm = Bank3[{Row, Col}];
endcase
// Dqm operation
if (Dqm_reg0 [0] == 1'b1) begin
Dq_dqm [ 7 : 0] = 8'bz;
end
if (Dqm_reg0 [1] == 1'b1) begin
Dq_dqm [15 : 8] = 8'bz;
end
// Display debug message
if (Dqm_reg0 !== 2'b11) begin
Dq_reg = #tAC Dq_dqm;
if (Debug) begin
$display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_reg);
end
end else begin
Dq_reg = #tHZ {data_bits{1'bz}};
if (Debug) begin
$display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end
end
// Advance burst counter subroutine
Burst_decode;
end
end
// Burst counter decode
task Burst_decode;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
// Burst Type
if (Mode_reg[3] == 1'b0) begin // Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
// Burst Length
if (Burst_length_2) begin // Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin // Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin // Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin // Burst Length = FULL
Col = Col_temp;
end
// Burst Read Single Write
if (Write_burst_mode == 1'b1) begin
Data_in_enable = 1'b0;
end
// Data Counter
if (Burst_length_1 == 1'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_2 == 1'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_4 == 1'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_8 == 1'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end
end
endtask
// // Timing Parameters for -7E (133 MHz @ CL2)
// specify
// specparam
// tAH = 0.8, // Addr, Ba Hold Time
// tAS = 1.5, // Addr, Ba Setup Time
// tCH = 2.5, // Clock High-Level Width
// tCL = 2.5, // Clock Low-Level Width
// tCK = 7.0, // Clock Cycle Time
// tDH = 0.8, // Data-in Hold Time
// tDS = 1.5, // Data-in Setup Time
// tCKH = 0.8, // CKE Hold Time
// tCKS = 1.5, // CKE Setup Time
// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
// $width (posedge Clk, tCH);
// $width (negedge Clk, tCL);
// $period (negedge Clk, tCK);
// $period (posedge Clk, tCK);
// $setuphold(posedge Clk, Cke, tCKS, tCKH);
// $setuphold(posedge Clk, Cs_n, tCMS, tCMH);
// $setuphold(posedge Clk, Cas_n, tCMS, tCMH);
// $setuphold(posedge Clk, Ras_n, tCMS, tCMH);
// $setuphold(posedge Clk, We_n, tCMS, tCMH);
// $setuphold(posedge Clk, Addr, tAS, tAH);
// $setuphold(posedge Clk, Ba, tAS, tAH);
// $setuphold(posedge Clk, Dqm, tCMS, tCMH);
// $setuphold(posedge Dq_chk, Dq, tDS, tDH);
// endspecify
endmodule
|
// This tests SystemVerilog casting support
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
// Extended by Maciej Suminski
// Copied and modified by Martin Whitaker
// Copied and modified again by Lars-Peter Clausen
module test();
typedef logic [7:0] pa08;
typedef pa08 [1:0] pa16;
typedef pa16 [1:0] pa32;
typedef pa32 [1:0] pa64;
// variables used in casting
pa08 var_08;
pa16 var_16;
pa32 var_32;
pa64 var_64;
real var_real;
// error counter
bit err = 0;
initial begin
var_08 = pa08'(4'h5); if (var_08 !== 8'h05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end
var_16 = pa16'(var_08); if (var_16 !== 16'h05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end
var_32 = pa32'(var_16); if (var_32 !== 32'h05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end
var_64 = pa64'(var_32); if (var_64 !== 64'h05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end
var_real = 13.4; var_08 = pa08'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end
var_real = 14.5; var_16 = pa16'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end
var_real = 15.6; var_32 = pa32'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end
var_real = -15.6; var_64 = pa64'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end
var_08 = pa08'(4'hf); if (var_08 !== 8'h0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end
var_16 = pa08'(16'h0f0f); if (var_16 !== 16'h0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Encoder Unit ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_encoder.v,v 1.3 2002/10/31 12:51:44 rherveille Exp $
//
// $Date: 2002/10/31 12:51:44 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_encoder.v,v $
// Revision 1.3 2002/10/31 12:51:44 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 18:58:51 rherveille
// Fixed a bug in the zero-run (run-length-coder)
//
// Revision 1.1 2002/10/23 09:07:01 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_encoder(
clk,
ena,
dstrb,
din,
qnt_val,
qnt_cnt,
size,
rlen,
amp,
douten,
SE,
SI,
SO
);
//
// parameters
//
////////////////////////////////////////////////////////////////////
// //
// ITU-T.81, ITU-T.83 & Coefficient resolution notes //
// //
////////////////////////////////////////////////////////////////////
// //
// Worst case error (all input values -128) is //
// zero (i.e. no errors) when using 15bit coefficients //
// //
// Using less bits for the coefficients produces a biterror //
// approx. equal to (15 - used_coefficient-bits). //
// i.e. 14bit coefficients, errors in dout-bit[0] only //
// 13bit coefficients, errors in dout-bits[1:0] //
// 12bit coefficients, errors in dout-bits[2:0] etc. //
// Tests with real non-continous tone image data have shown that //
// even when using 13bit coefficients errors remain in the lsb //
// only (i.e. dout-bit[0] //
// //
// The amount of coefficient-bits needed is dependent on the //
// desired quality. //
// The JPEG-standard compliance specs.(ITU-T.83) prescribe //
// that the output of the combined DCT AND Quantization unit //
// shall not exceed 1 for the desired quality. //
// //
// This means for high quantization levels, lesser bits //
// for the DCT unit can be used. //
// //
// Looking at the recommended "quantization tables for generic //
// compliance testing of DCT-based processes" (ITU-T.83 annex B) //
// it can be noticed that relatively large quantization values //
// are being used. Errors in the lower-order bits should //
// therefore not be visible. //
// Tests with real continuous and non-continous tone image data //
// have shown that when using the examples quantization tables //
// from ITU-T.81 annex K 10bit coefficients are sufficient to //
// comply to the ITU-T.83 specs. Compliance tests have been met //
// using as little as 9bit coefficients. //
// For certain applications some of the lower-order bits could //
// actually be discarded. When looking at the luminance and //
// chrominance example quantization tables (ITU-T.81 annex K) //
// it can be seen that the smallest quantization value is ten //
// (qnt_val_min = 10). This means that the lowest 2bits can be //
// discarded (set to zero '0') without having any effect on the //
// final result. In this example 11 bit or 12 bit coefficients //
// would be sufficient. //
// //
////////////////////////////////////////////////////////////////////
parameter coef_width = 11;
parameter di_width = 8; // no function yet
//
// inputs & outputs
//
input SE;
input SI;
output SO;
input clk; // system clock
input ena; // clock enable
input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
input [di_width-1:0] din;
input [7:0] qnt_val; // quantization value
output [ 5:0] qnt_cnt; // quantization value address
output [ 3:0] size; // size
output [ 3:0] rlen; // run-length
output [11:0] amp; // amplitude
output douten; // data output enable
//
// variables
//
wire rst = 1'b1; // active low asynchronous reset
wire fdct_doe, qnr_doe;
wire [11:0] fdct_dout;
reg [11:0] dfdct_dout;
wire [10:0] qnr_dout;
reg dqnr_doe;
//
// module body
//
// Hookup FDCT & ZigZag module
fdct #(coef_width, di_width, 12)
fdct_zigzag(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dstrb),
.din(din),
.dout(fdct_dout),
.douten(fdct_doe)
);
// delay 'fdct_dout' => wait for synchronous quantization RAM/ROM
always @(posedge clk)
if(ena)
dfdct_dout <= #1 fdct_dout;
// Hookup QNR (Quantization and Rounding) unit
jpeg_qnr
qnr(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(fdct_doe),
.din(dfdct_dout),
.qnt_val(qnt_val),
.qnt_cnt(qnt_cnt),
.dout(qnr_dout),
.douten(qnr_doe)
);
// delay douten 1 clk_cycle => account for delayed fdct_res & qnt_val
always @(posedge clk)
if(ena)
dqnr_doe <= #1 qnr_doe;
//
// TODO: Insert DC differential generator here.
//
wire [11:0] dc_diff_dout = {qnr_dout[10], qnr_dout};
wire dc_diff_doe = dqnr_doe;
// Hookup Run Length Encoder
jpeg_rle
rle(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dc_diff_doe),
.din(dc_diff_dout),
.size(size),
.rlen(rlen),
.amp(amp),
.douten(douten),
.bstart()
);
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Forward Discrete Cosine Transform and ZigZag unit ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: fdct.v,v 1.3 2002/10/31 12:50:03 rherveille Exp $
//
// $Date: 2002/10/31 12:50:03 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: fdct.v,v $
// Revision 1.3 2002/10/31 12:50:03 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:06:59 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module fdct(clk, ena, rst, dstrb, din, dout, douten);
//
// parameters
//
////////////////////////////////////////////////////////////////////
// //
// ITU-T.81, ITU-T.83 & Coefficient resolution notes //
// //
////////////////////////////////////////////////////////////////////
// //
// Worst case error (all input values -128) is //
// zero (i.e. no errors) when using 15bit coefficients //
// //
// Using less bits for the coefficients produces a biterror //
// approx. equal to (15 - used_coefficient-bits). //
// i.e. 14bit coefficients, errors in dout-bit[0] only //
// 13bit coefficients, errors in dout-bits[1:0] //
// 12bit coefficients, errors in dout-bits[2:0] etc. //
// Tests with real non-continous tone image data have shown that //
// even when using 13bit coefficients errors remain in the lsb //
// only (i.e. dout-bit[0] //
// //
// The amount of coefficient-bits needed is dependent on the //
// desired quality. //
// The JPEG-standard compliance specs.(ITU-T.83) prescribe //
// that the output of the combined DCT AND Quantization unit //
// shall not exceed 1 for the desired quality. //
// //
// This means for high quantization levels, lesser bits //
// for the DCT unit can be used. //
// //
// Looking at the recommended "quantization tables for generic //
// compliance testing of DCT-based processes" (ITU-T.83 annex B) //
// it can be noticed that relatively large quantization values //
// are being used. Errors in the lower-order bits should //
// therefore not be visible. //
// For certain applications some of the lower-order bits could //
// actually be discarded. When looking at the luminance and //
// chrominance example quantization tables (ITU-T.81 annex K) //
// it can be seen that the smallest quantization value is ten //
// (qnt_val_min = 10). This means that the lowest 2bits can be //
// discarded (set to zero '0') without having any effect on the //
// final result. In this example 11 bit or 12 bit coefficients //
// would be sufficient. //
// //
////////////////////////////////////////////////////////////////////
parameter coef_width = 11;
parameter di_width = 8;
parameter do_width = 12;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input rst; // active low asynchronous reset
input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
input [di_width-1:0] din;
output [do_width-1:0] dout;
output douten; // data-out enable
//
// variables
//
wire doe;
wire [do_width -1:0] // results from DCT module
res00, res01, res02, res03, res04, res05, res06, res07,
res10, res11, res12, res13, res14, res15, res16, res17,
res20, res21, res22, res23, res24, res25, res26, res27,
res30, res31, res32, res33, res34, res35, res36, res37,
res40, res41, res42, res43, res44, res45, res46, res47,
res50, res51, res52, res53, res54, res55, res56, res57,
res60, res61, res62, res63, res64, res65, res66, res67,
res70, res71, res72, res73, res74, res75, res76, res77;
//
// module body
//
// Hookup DCT module
dct #(coef_width, di_width, do_width)
dct_mod(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dstrb),
.din(din),
.dout_00(res00),
.dout_01(res01),
.dout_02(res02),
.dout_03(res03),
.dout_04(res04),
.dout_05(res05),
.dout_06(res06),
.dout_07(res07),
.dout_10(res10),
.dout_11(res11),
.dout_12(res12),
.dout_13(res13),
.dout_14(res14),
.dout_15(res15),
.dout_16(res16),
.dout_17(res17),
.dout_20(res20),
.dout_21(res21),
.dout_22(res22),
.dout_23(res23),
.dout_24(res24),
.dout_25(res25),
.dout_26(res26),
.dout_27(res27),
.dout_30(res30),
.dout_31(res31),
.dout_32(res32),
.dout_33(res33),
.dout_34(res34),
.dout_35(res35),
.dout_36(res36),
.dout_37(res37),
.dout_40(res40),
.dout_41(res41),
.dout_42(res42),
.dout_43(res43),
.dout_44(res44),
.dout_45(res45),
.dout_46(res46),
.dout_47(res47),
.dout_50(res50),
.dout_51(res51),
.dout_52(res52),
.dout_53(res53),
.dout_54(res54),
.dout_55(res55),
.dout_56(res56),
.dout_57(res57),
.dout_60(res60),
.dout_61(res61),
.dout_62(res62),
.dout_63(res63),
.dout_64(res64),
.dout_65(res65),
.dout_66(res66),
.dout_67(res67),
.dout_70(res70),
.dout_71(res71),
.dout_72(res72),
.dout_73(res73),
.dout_74(res74),
.dout_75(res75),
.dout_76(res76),
.dout_77(res77),
.douten(doe)
);
// Hookup ZigZag unit
zigzag zigzag_mod(
.clk(clk),
.ena(ena),
.dstrb(doe),
.din_00(res00),
.din_01(res01),
.din_02(res02),
.din_03(res03),
.din_04(res04),
.din_05(res05),
.din_06(res06),
.din_07(res07),
.din_10(res10),
.din_11(res11),
.din_12(res12),
.din_13(res13),
.din_14(res14),
.din_15(res15),
.din_16(res16),
.din_17(res17),
.din_20(res20),
.din_21(res21),
.din_22(res22),
.din_23(res23),
.din_24(res24),
.din_25(res25),
.din_26(res26),
.din_27(res27),
.din_30(res30),
.din_31(res31),
.din_32(res32),
.din_33(res33),
.din_34(res34),
.din_35(res35),
.din_36(res36),
.din_37(res37),
.din_40(res40),
.din_41(res41),
.din_42(res42),
.din_43(res43),
.din_44(res44),
.din_45(res45),
.din_46(res46),
.din_47(res47),
.din_50(res50),
.din_51(res51),
.din_52(res52),
.din_53(res53),
.din_54(res54),
.din_55(res55),
.din_56(res56),
.din_57(res57),
.din_60(res60),
.din_61(res61),
.din_62(res62),
.din_63(res63),
.din_64(res64),
.din_65(res65),
.din_66(res66),
.din_67(res67),
.din_70(res70),
.din_71(res71),
.din_72(res72),
.din_73(res73),
.din_74(res74),
.din_75(res75),
.din_76(res76),
.din_77(res77),
.dout(dout),
.douten(douten)
);
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Discrete Cosine Transform, Parallel implementation ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: dct.v,v 1.3 2002/10/31 12:50:03 rherveille Exp $
//
// $Date: 2002/10/31 12:50:03 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: dct.v,v $
// Revision 1.3 2002/10/31 12:50:03 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:06:59 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module dct(
clk,
ena,
rst,
dstrb,
din,
dout_00, dout_01, dout_02, dout_03, dout_04, dout_05, dout_06, dout_07,
dout_10, dout_11, dout_12, dout_13, dout_14, dout_15, dout_16, dout_17,
dout_20, dout_21, dout_22, dout_23, dout_24, dout_25, dout_26, dout_27,
dout_30, dout_31, dout_32, dout_33, dout_34, dout_35, dout_36, dout_37,
dout_40, dout_41, dout_42, dout_43, dout_44, dout_45, dout_46, dout_47,
dout_50, dout_51, dout_52, dout_53, dout_54, dout_55, dout_56, dout_57,
dout_60, dout_61, dout_62, dout_63, dout_64, dout_65, dout_66, dout_67,
dout_70, dout_71, dout_72, dout_73, dout_74, dout_75, dout_76, dout_77,
douten
);
//
// parameters
//
// Worst case errors (Din = 64* -128) remain in decimal bit
// when using 13bit coefficients
//
// For ultra-high
parameter coef_width = 11;
parameter di_width = 8;
parameter do_width = 12;
//
// inputs & outputs
//
input clk;
input ena;
input rst; // active low asynchronous reset
input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
input [di_width:1] din;
output [do_width:1]
dout_00, dout_01, dout_02, dout_03, dout_04, dout_05, dout_06, dout_07,
dout_10, dout_11, dout_12, dout_13, dout_14, dout_15, dout_16, dout_17,
dout_20, dout_21, dout_22, dout_23, dout_24, dout_25, dout_26, dout_27,
dout_30, dout_31, dout_32, dout_33, dout_34, dout_35, dout_36, dout_37,
dout_40, dout_41, dout_42, dout_43, dout_44, dout_45, dout_46, dout_47,
dout_50, dout_51, dout_52, dout_53, dout_54, dout_55, dout_56, dout_57,
dout_60, dout_61, dout_62, dout_63, dout_64, dout_65, dout_66, dout_67,
dout_70, dout_71, dout_72, dout_73, dout_74, dout_75, dout_76, dout_77;
output douten; // data-out enable
reg douten;
//
// variables
//
reg go, dgo, ddgo, ddcnt, dddcnt;
reg [di_width:1] ddin;
//
// module body
//
// generate sample counter
reg [5:0] sample_cnt;
wire dcnt = &sample_cnt;
always @(posedge clk or negedge rst)
if (~rst)
sample_cnt <= #1 6'h0;
else if (ena)
if(dstrb)
sample_cnt <= #1 6'h0;
else if(~dcnt)
sample_cnt <= #1 sample_cnt + 6'h1;
// internal signals
always @(posedge clk or negedge rst)
if (~rst)
begin
go <= #1 1'b0;
dgo <= #1 1'b0;
ddgo <= #1 1'b0;
ddin <= #1 0;
douten <= #1 1'b0;
ddcnt <= #1 1'b1;
dddcnt <= #1 1'b1;
end
else if (ena)
begin
go <= #1 dstrb;
dgo <= #1 go;
ddgo <= #1 dgo;
ddin <= #1 din;
ddcnt <= #1 dcnt;
dddcnt <= #1 ddcnt;
douten <= #1 ddcnt & ~dddcnt;
end
// Hookup DCT units
// V = 0
dctub #(coef_width, di_width, 3'h0)
dct_block_0 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_00), // (U,V) = (0,0)
.dout1(dout_01), // (U,V) = (0,1)
.dout2(dout_02), // (U,V) = (0,2)
.dout3(dout_03), // (U,V) = (0,3)
.dout4(dout_04), // (U,V) = (0,4)
.dout5(dout_05), // (U,V) = (0,5)
.dout6(dout_06), // (U,V) = (0,6)
.dout7(dout_07) // (U,V) = (0,7)
);
// V = 1
dctub #(coef_width, di_width, 3'h1)
dct_block_1 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_10), // (U,V) = (1,0)
.dout1(dout_11), // (U,V) = (1,1)
.dout2(dout_12), // (U,V) = (1,2)
.dout3(dout_13), // (U,V) = (1,3)
.dout4(dout_14), // (U,V) = (1,4)
.dout5(dout_15), // (U,V) = (1,5)
.dout6(dout_16), // (U,V) = (1,6)
.dout7(dout_17) // (U,V) = (1,7)
);
// V = 2
dctub #(coef_width, di_width, 3'h2)
dct_block_2 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_20), // (U,V) = (2,0)
.dout1(dout_21), // (U,V) = (2,1)
.dout2(dout_22), // (U,V) = (2,2)
.dout3(dout_23), // (U,V) = (2,3)
.dout4(dout_24), // (U,V) = (2,4)
.dout5(dout_25), // (U,V) = (2,5)
.dout6(dout_26), // (U,V) = (2,6)
.dout7(dout_27) // (U,V) = (2,7)
);
// V = 3
dctub #(coef_width, di_width, 3'h3)
dct_block_3 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_30), // (U,V) = (3,0)
.dout1(dout_31), // (U,V) = (3,1)
.dout2(dout_32), // (U,V) = (3,2)
.dout3(dout_33), // (U,V) = (3,3)
.dout4(dout_34), // (U,V) = (3,4)
.dout5(dout_35), // (U,V) = (3,5)
.dout6(dout_36), // (U,V) = (3,6)
.dout7(dout_37) // (U,V) = (3,7)
);
// V = 4
dctub #(coef_width, di_width, 3'h4)
dct_block_4 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_40), // (U,V) = (4,0)
.dout1(dout_41), // (U,V) = (4,1)
.dout2(dout_42), // (U,V) = (4,2)
.dout3(dout_43), // (U,V) = (4,3)
.dout4(dout_44), // (U,V) = (4,4)
.dout5(dout_45), // (U,V) = (4,5)
.dout6(dout_46), // (U,V) = (4,6)
.dout7(dout_47) // (U,V) = (4,7)
);
// V = 5
dctub #(coef_width, di_width, 3'h5)
dct_block_5 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_50), // (U,V) = (5,0)
.dout1(dout_51), // (U,V) = (5,1)
.dout2(dout_52), // (U,V) = (5,2)
.dout3(dout_53), // (U,V) = (5,3)
.dout4(dout_54), // (U,V) = (5,4)
.dout5(dout_55), // (U,V) = (5,5)
.dout6(dout_56), // (U,V) = (5,6)
.dout7(dout_57) // (U,V) = (5,7)
);
// V = 6
dctub #(coef_width, di_width, 3'h6)
dct_block_6 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_60), // (U,V) = (6,0)
.dout1(dout_61), // (U,V) = (6,1)
.dout2(dout_62), // (U,V) = (6,2)
.dout3(dout_63), // (U,V) = (6,3)
.dout4(dout_64), // (U,V) = (6,4)
.dout5(dout_65), // (U,V) = (6,5)
.dout6(dout_66), // (U,V) = (6,6)
.dout7(dout_67) // (U,V) = (6,7)
);
// V = 7
dctub #(coef_width, di_width, 3'h7)
dct_block_7 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_70), // (U,V) = (7,0)
.dout1(dout_71), // (U,V) = (7,1)
.dout2(dout_72), // (U,V) = (7,2)
.dout3(dout_73), // (U,V) = (7,3)
.dout4(dout_74), // (U,V) = (7,4)
.dout5(dout_75), // (U,V) = (7,5)
.dout6(dout_76), // (U,V) = (7,6)
.dout7(dout_77) // (U,V) = (7,7)
);
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Discrete Cosine Transform, DCT unit block ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: dctub.v,v 1.3 2002/10/31 12:50:03 rherveille Exp $
//
// $Date: 2002/10/31 12:50:03 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: dctub.v,v $
// Revision 1.3 2002/10/31 12:50:03 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:06:59 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module dctub(clk, ena, ddgo, x, y, ddin,
dout0, dout1, dout2, dout3, dout4, dout5, dout6, dout7);
parameter coef_width = 16;
parameter di_width = 8;
parameter [2:0] v = 3'h0;
//
// inputs & outputs
//
input clk;
input ena;
input ddgo; // double delayed go strobe
input [2:0] x, y;
input [di_width:1] ddin; // delayed data input
output [11:0] dout0, dout1, dout2, dout3, dout4, dout5, dout6, dout7;
//
// module body
//
// Hookup DCT units
dctu #(coef_width, di_width, v, 3'h0)
dct_unit_0 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout0)
);
dctu #(coef_width, di_width, v, 3'h1)
dct_unit_1 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout1)
);
dctu #(coef_width, di_width, v, 3'h2)
dct_unit_2 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout2)
);
dctu #(coef_width, di_width, v, 3'h3)
dct_unit_3 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout3)
);
dctu #(coef_width, di_width, v, 3'h4)
dct_unit_4 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout4)
);
dctu #(coef_width, di_width, v, 3'h5)
dct_unit_5 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout5)
);
dctu #(coef_width, di_width, v, 3'h6)
dct_unit_6 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout6)
);
dctu #(coef_width, di_width, v, 3'h7)
dct_unit_7 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout7)
);
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Quantization & Rounding Core ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_qnr.v,v 1.3 2002/10/31 12:52:55 rherveille Exp $
//
// $Date: 2002/10/31 12:52:55 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_qnr.v,v $
// Revision 1.3 2002/10/31 12:52:55 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:07:03 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_qnr(clk, ena, rst, dstrb, din, qnt_val, qnt_cnt, dout, douten);
//
// parameters
//
parameter d_width = 12;
parameter z_width = 2 * d_width;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input rst; // asynchronous active low reset
input dstrb; // present dstrb 1clk cycle before din
input [d_width-1:0] din; // data input
input [ 7:0] qnt_val; // quantization value
output [ 5:0] qnt_cnt; // sample number (get quantization value qnt_cnt)
output [10:0] dout; // data output
output douten;
//
// variables
//
wire [z_width-1:0] iz; // intermediate divident value
wire [d_width-1:0] id; // intermediate dividor value
wire [d_width :0] iq; // intermediate result divider
reg [d_width :0] rq; // rounded q-value
reg [d_width+3:0] dep;// data enable pipeline
// generate sample counter
reg [5:0] qnt_cnt;
wire dcnt = &qnt_cnt;
always @(posedge clk or negedge rst)
if (~rst)
qnt_cnt <= #1 6'h0;
else if (dstrb)
qnt_cnt <= #1 6'h0;
else if (ena)
qnt_cnt <= #1 qnt_cnt + 6'h1;
// generate intermediate dividor/divident values
assign id = { {(d_width - 8){1'b0}}, qnt_val};
assign iz = { {(z_width - d_width){din[d_width-1]}}, din};
// hookup division unit
div_su #(z_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(),
.div0(),
.ovf()
);
// round result to the nearest integer
always @(posedge clk)
if (ena)
if (iq[0])
if (iq[d_width])
rq <= #1 iq - 1'h1;
else
rq <= #1 iq + 1'h1;
else
rq <= #1 iq;
// assign dout signal
assign dout = rq[d_width -1: d_width-11];
// generate data-out enable signal
// This is a pipeline, data is not dependant on sample-count
integer n;
always @(posedge clk or negedge rst)
if (!rst)
dep <= #1 0;
else if(ena)
begin
dep[0] <= #1 dstrb;
for (n=1; n <= d_width +3; n = n +1)
dep[n] <= #1 dep[n-1];
end
assign douten = dep[d_width +3];
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Run-Length encoder ////
//// ////
//// 1) Retreive zig-zag-ed samples (starting with DC coeff.) ////
//// 2) Translate DC-coeff. into 11bit-size and amplitude ////
//// 3) Translate AC-coeff. into zero-runs, size and amplitude ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_rle.v,v 1.4 2002/10/31 12:53:39 rherveille Exp $
//
// $Date: 2002/10/31 12:53:39 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_rle.v,v $
// Revision 1.4 2002/10/31 12:53:39 rherveille
// *** empty log message ***
//
// Revision 1.3 2002/10/23 18:58:54 rherveille
// Fixed a bug in the zero-run (run-length-coder)
//
// Revision 1.2 2002/10/23 09:07:04 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_rle(clk, rst, ena, dstrb, din, size, rlen, amp, douten, bstart);
//
// parameters
//
//
// inputs & outputs
//
input clk; // system clock
input rst; // asynchronous reset
input ena; // clock enable
input dstrb;
input [11:0] din; // data input
output [ 3:0] size; // size
output [ 3:0] rlen; // run-length
output [11:0] amp; // amplitude
output douten; // data output enable
output bstart; // block start
//
// variables
//
wire [ 3:0] rle_rlen, rz1_rlen, rz2_rlen, rz3_rlen, rz4_rlen;
wire [ 3:0] rle_size, rz1_size, rz2_size, rz3_size, rz4_size;
wire [11:0] rle_amp, rz1_amp, rz2_amp, rz3_amp, rz4_amp;
wire rle_den, rz1_den, rz2_den, rz3_den, rz4_den;
wire rle_dc, rz1_dc, rz2_dc, rz3_dc, rz4_dc;
//
// module body
//
reg ddstrb;
always @(posedge clk)
ddstrb <= #1 dstrb;
// generate run-length encoded signals
jpeg_rle1 rle(
.clk(clk),
.rst(rst),
.ena(ena),
.go(ddstrb),
.din(din),
.rlen(rle_rlen),
.size(rle_size),
.amp(rle_amp),
.den(rle_den),
.dcterm(rle_dc)
);
// Find (15,0) (0,0) sequences and replace by (0,0)
// There can be max. 4 (15,0) sequences in a row
// step1
jpeg_rzs rz1(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rle_rlen),
.sizei(rle_size),
.ampi(rle_amp),
.deni(rle_den),
.dci(rle_dc),
.rleno(rz1_rlen),
.sizeo(rz1_size),
.ampo(rz1_amp),
.deno(rz1_den),
.dco(rz1_dc)
);
// step2
jpeg_rzs rz2(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz1_rlen),
.sizei(rz1_size),
.ampi(rz1_amp),
.deni(rz1_den),
.dci(rz1_dc),
.rleno(rz2_rlen),
.sizeo(rz2_size),
.ampo(rz2_amp),
.deno(rz2_den),
.dco(rz2_dc)
);
// step3
jpeg_rzs rz3(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz2_rlen),
.sizei(rz2_size),
.ampi(rz2_amp),
.deni(rz2_den),
.dci(rz2_dc),
.rleno(rz3_rlen),
.sizeo(rz3_size),
.ampo(rz3_amp),
.deno(rz3_den),
.dco(rz3_dc)
);
// step4
jpeg_rzs rz4(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz3_rlen),
.sizei(rz3_size),
.ampi(rz3_amp),
.deni(rz3_den),
.dci(rz3_dc),
.rleno(rz4_rlen),
.sizeo(rz4_size),
.ampo(rz4_amp),
.deno(rz4_den),
.dco(rz4_dc)
);
// assign outputs
assign rlen = rz4_rlen;
assign size = rz4_size;
assign amp = rz4_amp;
assign douten = rz4_den;
assign bstart = rz4_dc;
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Discrete Cosine Transform Unit ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: dctu.v,v 1.3 2002/10/31 12:50:03 rherveille Exp $
//
// $Date: 2002/10/31 12:50:03 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: dctu.v,v $
// Revision 1.3 2002/10/31 12:50:03 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:06:59 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module dctu(clk, ena, ddgo, x, y, ddin, dout);
parameter coef_width = 16;
parameter di_width = 8;
parameter [2:0] v = 0;
parameter [2:0] u = 0;
//
// inputs & outputs
//
input clk;
input ena;
input ddgo; // double delayed go signal
input [2:0] x, y;
input [di_width:1] ddin; // delayed data input
output [11:0] dout;
//
// variables
//
reg [ 31:0] coef;
wire [coef_width +10:0] result;
`include "dct_cos_table.v"
//
// module body
//
// hookup cosine-table
always @(posedge clk)
if(ena)
coef <= #1 dct_cos_table(x, y, u, v);
// hookup dct-mac unit
dct_mac #(8, coef_width)
macu (
.clk(clk),
.ena(ena),
.dclr(ddgo),
.din(ddin),
.coef( coef[31:31 -coef_width +1] ),
.result(result)
);
assign dout = result[coef_width +10: coef_width -1];
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Run-Length Encoder, remove zero sequences ////
//// ////
//// - Detect (15,0) (0,0) seqence ////
//// - Replace them by (0,0) ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_rzs.v,v 1.4 2002/10/31 12:53:39 rherveille Exp $
//
// $Date: 2002/10/31 12:53:39 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_rzs.v,v $
// Revision 1.4 2002/10/31 12:53:39 rherveille
// *** empty log message ***
//
// Revision 1.3 2002/10/23 18:58:54 rherveille
// Fixed a bug in the zero-run (run-length-coder)
//
// Revision 1.2 2002/10/23 09:07:04 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_rzs(clk, ena, rst, deni, dci, rleni, sizei, ampi, deno, dco, rleno, sizeo, ampo);
//
// inputs & outputs
//
input clk;
input ena;
input rst;
input deni;
input dci;
input [ 3:0] sizei;
input [ 3:0] rleni;
input [11:0] ampi;
output deno;
output dco;
output [ 3:0] sizeo;
output [ 3:0] rleno;
output [11:0] ampo;
reg deno, dco;
reg [ 3:0] sizeo, rleno;
reg [11:0] ampo;
//
// variables
//
reg [ 3:0] size;
reg [ 3:0] rlen;
reg [11:0] amp;
reg den;
reg dc;
wire eob;
wire zerobl;
reg state;
//
// module body
//
always @(posedge clk)
if(ena & deni)
begin
size <= #1 sizei;
rlen <= #1 rleni;
amp <= #1 ampi;
end
always @(posedge clk)
if(ena)
begin
sizeo <= #1 size;
rleno <= #1 rlen;
ampo <= #1 amp;
dc <= #1 dci;
dco <= #1 dc;
end
assign zerobl = &rleni & ~|sizei & deni;
assign eob = ~|{rleni, sizei} & deni & ~dci;
always @(posedge clk or negedge rst)
if (!rst)
begin
state <= #1 1'b0;
den <= #1 1'b0;
deno <= #1 1'b0;
end
else
if(ena)
case (state) // synopsys full_case parallel_case
1'b0:
begin
if (zerobl)
begin
state <= #1 1'b1; // go to zero-detection state
den <= #1 1'b0; // do not yet set data output enable
deno <= #1 den; // output previous data
end
else
begin
state <= #1 1'b0; // stay in 'normal' state
den <= #1 deni; // set data output enable
deno <= #1 den; // output previous data
end
end
1'b1:
begin
deno <= #1 1'b0;
if (deni)
if (zerobl)
begin
state <= #1 1'b1; // stay in zero-detection state
den <= #1 1'b0; // hold current zer-block
deno <= #1 1'b1; // output previous zero-block
end
else if (eob)
begin
state <= #1 1'b0; // go to 'normal' state
den <= #1 1'b1; // set output enable for EOB
deno <= #1 1'b0; // (was already zero), maybe optimize ??
end
else
begin
state <= #1 1'b0; // go to normal state
den <= #1 1'b1; // set data output enable
deno <= #1 1'b1; // oops, zero-block should have been output
end
end
endcase
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Discrete Cosine Transform, MAC unit ////
//// ////
//// Virtex-II: Block-Multiplier is used ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: dct_mac.v,v 1.3 2002/10/31 12:50:03 rherveille Exp $
//
// $Date: 2002/10/31 12:50:03 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: dct_mac.v,v $
// Revision 1.3 2002/10/31 12:50:03 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:06:59 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module dct_mac(clk, ena, dclr, din, coef, result);
//
// parameters
//
parameter dwidth = 8;
parameter cwidth = 16;
parameter mwidth = dwidth + cwidth; // multiplier result
parameter rwidth = mwidth +3; // add 3 bits for growth
//
// inputs & outputs
//
input clk; // clock input
input ena; // clock enable
input dclr; // start new mac (delayed 1 cycle)
input [dwidth-1:0] din; // data input
input [cwidth-1:0] coef; // coefficient input
output [rwidth-1:0] result; // mac-result
reg [rwidth -1:0] result;
//
// variables
//
wire [mwidth-1:0] idin;
wire [mwidth-1:0] icoef;
reg [mwidth -1:0] mult_res /* synthesis syn_multstyle="block_mult" syn_pipeline=1*/ ;
wire [rwidth -1:0] ext_mult_res;
//
// module body
//
assign icoef = { {(mwidth-cwidth){coef[cwidth-1]}}, coef};
assign idin = { {(mwidth-dwidth){din[dwidth-1]}}, din};
// generate multiplier structure
always @(posedge clk)
if(ena)
mult_res <= #1 icoef * idin;
assign ext_mult_res = { {3{mult_res[mwidth-1]}}, mult_res};
// generate adder structure
always @(posedge clk)
if(ena)
if(dclr)
result <= #1 ext_mult_res;
else
result <= #1 ext_mult_res + result;
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring unsinged divider ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_uu.v,v 1.3 2002/10/31 12:52:55 rherveille Exp $
//
// $Date: 2002/10/31 12:52:55 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: div_uu.v,v $
// Revision 1.3 2002/10/31 12:52:55 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:07:03 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module div_uu(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width -1:0] z; // divident
input [d_width -1:0] d; // divisor
output [d_width -1:0] q; // quotient
reg [d_width-1:0] q;
output [d_width -1:0] s; // remainder
reg [d_width-1:0] s;
output div0;
reg div0;
output ovf;
reg ovf;
//
// functions
//
function [z_width:0] gen_s;
input [z_width:0] si;
input [z_width:0] di;
begin
if(si[z_width])
gen_s = {si[z_width-1:0], 1'b0} + di;
else
gen_s = {si[z_width-1:0], 1'b0} - di;
end
endfunction
function [d_width-1:0] gen_q;
input [d_width-1:0] qi;
input [z_width:0] si;
begin
gen_q = {qi[d_width-2:0], ~si[z_width]};
end
endfunction
function [d_width-1:0] assign_s;
input [z_width:0] si;
input [z_width:0] di;
reg [z_width:0] tmp;
begin
if(si[z_width])
tmp = si + di;
else
tmp = si;
assign_s = tmp[z_width-1:z_width-4];
end
endfunction
//
// variables
//
reg [d_width-1:0] q_pipe [d_width-1:0];
reg [z_width:0] s_pipe [d_width:0];
reg [z_width:0] d_pipe [d_width:0];
reg [d_width:0] div0_pipe, ovf_pipe;
//
// perform parameter checks
//
// synopsys translate_off
initial
begin
if(d_width !== z_width / 2)
$display("div.v parameter error (d_width != z_width/2).");
end
// synopsys translate_on
integer n0, n1, n2, n3;
// generate divisor (d) pipe
always @(d)
d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
always @(posedge clk)
if(ena)
for(n0=1; n0 <= d_width; n0=n0+1)
d_pipe[n0] <= #1 d_pipe[n0-1];
// generate internal remainder pipe
always @(z)
s_pipe[0] <= z;
always @(posedge clk)
if(ena)
for(n1=1; n1 <= d_width; n1=n1+1)
s_pipe[n1] <= #1 gen_s(s_pipe[n1-1], d_pipe[n1-1]);
// generate quotient pipe
always @(posedge clk)
q_pipe[0] <= #1 0;
always @(posedge clk)
if(ena)
for(n2=1; n2 < d_width; n2=n2+1)
q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]);
// flags (divide_by_zero, overflow)
always @(z or d)
begin
ovf_pipe[0] <= !(z[z_width-1:d_width] < d);
div0_pipe[0] <= ~|d;
end
always @(posedge clk)
if(ena)
for(n3=1; n3 <= d_width; n3=n3+1)
begin
ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
div0_pipe[n3] <= #1 div0_pipe[n3-1];
end
// assign outputs
always @(posedge clk)
if(ena)
ovf <= #1 ovf_pipe[d_width];
always @(posedge clk)
if(ena)
div0 <= #1 div0_pipe[d_width];
always @(posedge clk)
if(ena)
q <= #1 gen_q(q_pipe[d_width-1], s_pipe[d_width]);
always @(posedge clk)
if(ena)
s <= #1 assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring signed by unsigned divider ////
//// Uses the non-restoring unsigned by unsigned divider ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_su.v,v 1.3 2002/10/31 12:52:54 rherveille Exp $
//
// $Date: 2002/10/31 12:52:54 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: div_su.v,v $
// Revision 1.3 2002/10/31 12:52:54 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:07:03 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module div_su(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width-1:0] z; // divident
input [d_width-1:0] d; // divisor
output [d_width :0] q; // quotient
output [d_width-1:0] s; // remainder
output div0;
output ovf;
reg [d_width :0] q;
reg [d_width-1:0] s;
reg div0;
reg ovf;
//
// variables
//
reg [z_width -1:0] iz;
reg [d_width -1:0] id;
reg [d_width +1:0] spipe;
wire [d_width -1:0] iq, is;
wire idiv0, iovf;
//
// module body
//
// delay d
always @(posedge clk)
if (ena)
id <= #1 d;
// check z, take abs value
always @(posedge clk)
if (ena)
if (z[z_width-1])
iz <= #1 ~z +1'h1;
else
iz <= #1 z;
// generate spipe (sign bit pipe)
integer n;
always @(posedge clk)
if(ena)
begin
spipe[0] <= #1 z[z_width-1];
for(n=1; n <= d_width+1; n=n+1)
spipe[n] <= #1 spipe[n-1];
end
// hookup non-restoring divider
div_uu #(z_width, d_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(is),
.div0(idiv0),
.ovf(iovf)
);
// correct divider results if 'd' was negative
always @(posedge clk)
if(ena)
if(spipe[d_width+1])
begin
q <= #1 (~iq) + 1'h1;
s <= #1 (~is) + 1'h1;
end
else
begin
q <= #1 {1'b0, iq};
s <= #1 {1'b0, is};
end
// delay flags same as results
always @(posedge clk)
if(ena)
begin
div0 <= #1 idiv0;
ovf <= #1 iovf;
end
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Run-Length Encoder, intermediate results ////
//// ////
//// - Translate DC and AC coeff. into: ////
//// 1) zero-run-length ////
//// 2) bit-size for amplitude ////
//// 3) amplitude ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_rle1.v,v 1.4 2002/10/31 12:53:39 rherveille Exp $
//
// $Date: 2002/10/31 12:53:39 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_rle1.v,v $
// Revision 1.4 2002/10/31 12:53:39 rherveille
// *** empty log message ***
//
// Revision 1.3 2002/10/23 18:58:54 rherveille
// Fixed a bug in the zero-run (run-length-coder)
//
// Revision 1.2 2002/10/23 09:07:04 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_rle1(clk, rst, ena, go, din, rlen, size, amp, den, dcterm);
//
// parameters
//
//
// inputs & outputs
//
input clk; // system clock
input rst; // asynchronous reset
input ena; // clock enable
input go;
input [11:0] din; // data input
output [ 3:0] rlen; // run-length
output [ 3:0] size; // size (or category)
output [11:0] amp; // amplitude
output den; // data output enable
output dcterm; // DC-term (start of new block)
reg [ 3:0] rlen, size;
reg [11:0] amp;
reg den, dcterm;
//
// variables
//
reg [5:0] sample_cnt;
reg [3:0] zero_cnt;
wire is_zero;
reg state;
parameter dc = 1'b0;
parameter ac = 1'b1;
//
// module body
//
//
// function declarations
//
// Function abs; absolute value
function [10:0] abs;
input [11:0] a;
begin
if (a[11])
abs = (~a[10:0]) +11'h1;
else
abs = a[10:0];
end
endfunction
// Function cat, calculates category for Din
function [3:0] cat;
input [11:0] a;
reg [10:0] tmp;
begin
// get absolute value
tmp = abs(a);
// determine category
casex(tmp) // synopsys full_case parallel_case
11'b1??_????_???? : cat = 4'hb; // 1024..2047
11'b01?_????_???? : cat = 4'ha; // 512..1023
11'b001_????_???? : cat = 4'h9; // 256.. 511
11'b000_1???_???? : cat = 4'h8; // 128.. 255
11'b000_01??_???? : cat = 4'h7; // 64.. 127
11'b000_001?_???? : cat = 4'h6; // 32.. 63
11'b000_0001_???? : cat = 4'h5; // 16.. 31
11'b000_0000_1??? : cat = 4'h4; // 8.. 15
11'b000_0000_01?? : cat = 4'h3; // 4.. 7
11'b000_0000_001? : cat = 4'h2; // 2.. 3
11'b000_0000_0001 : cat = 4'h1; // 1
11'b000_0000_0000 : cat = 4'h0; // 0 (DC only)
endcase
end
endfunction
// Function modamp, calculate additional bits per category
function [10:0] rem;
input [11:0] a;
reg [10:0] tmp, tmp_rem;
begin
tmp_rem = a[11] ? (a[10:0] - 10'h1) : a[10:0];
if(0)
begin
// get absolute value
tmp = abs(a);
casex(tmp) // synopsys full_case parallel_case
11'b1??_????_???? : rem = tmp_rem & 11'b111_1111_1111;
11'b01?_????_???? : rem = tmp_rem & 11'b011_1111_1111;
11'b001_????_???? : rem = tmp_rem & 11'b001_1111_1111;
11'b000_1???_???? : rem = tmp_rem & 11'b000_1111_1111;
11'b000_01??_???? : rem = tmp_rem & 11'b000_0111_1111;
11'b000_001?_???? : rem = tmp_rem & 11'b000_0011_1111;
11'b000_0001_???? : rem = tmp_rem & 11'b000_0001_1111;
11'b000_0000_1??? : rem = tmp_rem & 11'b000_0000_1111;
11'b000_0000_01?? : rem = tmp_rem & 11'b000_0000_0111;
11'b000_0000_001? : rem = tmp_rem & 11'b000_0000_0011;
11'b000_0000_0001 : rem = tmp_rem & 11'b000_0000_0001;
11'b000_0000_0000 : rem = tmp_rem & 11'b000_0000_0000;
endcase
end
else
rem = tmp_rem;
end
endfunction
// detect zero
assign is_zero = ~|din;
// assign dout
always @(posedge clk)
if (ena)
amp <= #1 rem(din);
// generate sample counter
always @(posedge clk)
if (ena)
if (go)
sample_cnt <= #1 1; // count AC-terms, 'go=1' is sample-zero
else
sample_cnt <= #1 sample_cnt +1;
// generate zero counter
always @(posedge clk)
if (ena)
if (is_zero)
zero_cnt <= #1 zero_cnt +1;
else
zero_cnt <= #1 0;
// statemachine, create intermediate results
always @(posedge clk or negedge rst)
if(!rst)
begin
state <= #1 dc;
rlen <= #1 0;
size <= #1 0;
den <= #1 1'b0;
dcterm <= #1 1'b0;
end
else if (ena)
case (state) // synopsys full_case parallel_case
dc:
begin
rlen <= #1 0;
size <= #1 cat(din);
if(go)
begin
state <= #1 ac;
den <= #1 1'b1;
dcterm <= #1 1'b1;
end
else
begin
state <= #1 dc;
den <= #1 1'b0;
dcterm <= #1 1'b0;
end
end
ac:
if(&sample_cnt) // finished current block
begin
state <= #1 dc;
if (is_zero) // last sample zero? send EOB
begin
rlen <= #1 0;
size <= #1 0;
den <= #1 1'b1;
dcterm <= #1 1'b0;
end
else
begin
rlen <= #1 zero_cnt;
size <= #1 cat(din);
den <= #1 1'b1;
dcterm <= #1 1'b0;
end
end
else
begin
state <= #1 ac;
rlen <= #1 zero_cnt;
dcterm <= #1 1'b0;
if (is_zero)
begin
size <= #1 0;
den <= #1 &zero_cnt;
end
else
begin
size <= #1 cat(din);
den <= #1 1'b1;
end
end
endcase
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Zig-Zag Unit ////
//// Performs zigzag-ing, as used by many DCT based encoders ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: zigzag.v,v 1.2 2002/10/23 09:06:59 rherveille Exp $
//
// $Date: 2002/10/23 09:06:59 $
// $Revision: 1.2 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: zigzag.v,v $
// Revision 1.2 2002/10/23 09:06:59 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
module zigzag(
clk,
ena,
dstrb,
din_00, din_01, din_02, din_03, din_04, din_05, din_06, din_07,
din_10, din_11, din_12, din_13, din_14, din_15, din_16, din_17,
din_20, din_21, din_22, din_23, din_24, din_25, din_26, din_27,
din_30, din_31, din_32, din_33, din_34, din_35, din_36, din_37,
din_40, din_41, din_42, din_43, din_44, din_45, din_46, din_47,
din_50, din_51, din_52, din_53, din_54, din_55, din_56, din_57,
din_60, din_61, din_62, din_63, din_64, din_65, din_66, din_67,
din_70, din_71, din_72, din_73, din_74, din_75, din_76, din_77,
dout,
douten
);
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
input [11:0]
din_00, din_01, din_02, din_03, din_04, din_05, din_06, din_07,
din_10, din_11, din_12, din_13, din_14, din_15, din_16, din_17,
din_20, din_21, din_22, din_23, din_24, din_25, din_26, din_27,
din_30, din_31, din_32, din_33, din_34, din_35, din_36, din_37,
din_40, din_41, din_42, din_43, din_44, din_45, din_46, din_47,
din_50, din_51, din_52, din_53, din_54, din_55, din_56, din_57,
din_60, din_61, din_62, din_63, din_64, din_65, din_66, din_67,
din_70, din_71, din_72, din_73, din_74, din_75, din_76, din_77;
output [11:0] dout;
output douten; // data-out enable
//
// variables
//
reg ld_zigzag;
reg [11:0] sresult [63:0]; // store results for zig-zagging
//
// module body
//
always @(posedge clk)
if(ena)
ld_zigzag <= #1 dstrb;
assign douten = ld_zigzag;
//
// Generate zig-zag structure
//
// This implicates that the quantization step be performed after
// the zig-zagging.
//
// 0: 1: 2: 3: 4: 5: 6: 7: 0: 1: 2: 3: 4: 5: 6: 7:
// 0: 63 62 58 57 49 48 36 35 3f 3e 3a 39 31 30 24 23
// 1: 61 59 56 50 47 37 34 21 3d 3b 38 32 2f 25 22 15
// 2: 60 55 51 46 38 33 22 20 3c 37 33 2e 26 21 16 14
// 3: 54 52 45 39 32 23 19 10 36 34 2d 27 20 17 13 0a
// 4: 53 44 40 31 24 18 11 09 35 2c 28 1f 18 12 0b 09
// 5: 43 41 30 25 17 12 08 03 2b 29 1e 19 11 0c 08 03
// 6: 42 29 26 16 13 07 04 02 2a 1d 1a 10 0d 07 04 02
// 7: 28 27 15 14 06 05 01 00 1c 1b 0f 0e 06 05 01 00
//
// zig-zag the DCT results
integer n;
always @(posedge clk)
if(ena)
if(ld_zigzag) // reload results-register file
begin
sresult[63] <= #1 din_00;
sresult[62] <= #1 din_01;
sresult[61] <= #1 din_10;
sresult[60] <= #1 din_20;
sresult[59] <= #1 din_11;
sresult[58] <= #1 din_02;
sresult[57] <= #1 din_03;
sresult[56] <= #1 din_12;
sresult[55] <= #1 din_21;
sresult[54] <= #1 din_30;
sresult[53] <= #1 din_40;
sresult[52] <= #1 din_31;
sresult[51] <= #1 din_22;
sresult[50] <= #1 din_13;
sresult[49] <= #1 din_04;
sresult[48] <= #1 din_05;
sresult[47] <= #1 din_14;
sresult[46] <= #1 din_23;
sresult[45] <= #1 din_32;
sresult[44] <= #1 din_41;
sresult[43] <= #1 din_50;
sresult[42] <= #1 din_60;
sresult[41] <= #1 din_51;
sresult[40] <= #1 din_42;
sresult[39] <= #1 din_33;
sresult[38] <= #1 din_24;
sresult[37] <= #1 din_15;
sresult[36] <= #1 din_06;
sresult[35] <= #1 din_07;
sresult[34] <= #1 din_16;
sresult[33] <= #1 din_25;
sresult[32] <= #1 din_34;
sresult[31] <= #1 din_43;
sresult[30] <= #1 din_52;
sresult[29] <= #1 din_61;
sresult[28] <= #1 din_70;
sresult[27] <= #1 din_71;
sresult[26] <= #1 din_62;
sresult[25] <= #1 din_53;
sresult[24] <= #1 din_44;
sresult[23] <= #1 din_35;
sresult[22] <= #1 din_26;
sresult[21] <= #1 din_17;
sresult[20] <= #1 din_27;
sresult[19] <= #1 din_36;
sresult[18] <= #1 din_45;
sresult[17] <= #1 din_54;
sresult[16] <= #1 din_63;
sresult[15] <= #1 din_72;
sresult[14] <= #1 din_73;
sresult[13] <= #1 din_64;
sresult[12] <= #1 din_55;
sresult[11] <= #1 din_46;
sresult[10] <= #1 din_37;
sresult[09] <= #1 din_47;
sresult[08] <= #1 din_56;
sresult[07] <= #1 din_65;
sresult[06] <= #1 din_74;
sresult[05] <= #1 din_75;
sresult[04] <= #1 din_66;
sresult[03] <= #1 din_57;
sresult[02] <= #1 din_67;
sresult[01] <= #1 din_76;
sresult[00] <= #1 din_77;
end
else // shift results out
for (n=1; n<=63; n=n+1) // do not change sresult[0]
sresult[n] <= #1 sresult[n -1];
assign dout = sresult[63];
endmodule
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module memory_mux (
input select,
input enable_0,
input command_0,
input [31:0] address_0,
input [31:0] write_data_0,
input [3:0] write_mask_0,
output [31:0] read_data_0,
output valid_0,
input enable_1,
input command_1,
input [31:0] address_1,
input [31:0] write_data_1,
input [3:0] write_mask_1,
output [31:0] read_data_1,
output valid_1,
output enable,
output command,
output [31:0] address,
output [31:0] write_data,
output [3:0] write_mask,
input [31:0] read_data,
input valid
);
assign enable = select ? enable_1 : enable_0;
assign command = select ? command_1 : command_0;
assign address = select ? address_1 : address_0;
assign write_data = select ? write_data_1 : write_data_0;
assign write_mask = select ? write_mask_1 : write_mask_0;
assign read_data_1 = read_data;
assign read_data_0 = read_data;
assign valid_1 = select ? valid : 1'b0;
assign valid_0 = !select ? valid : 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A311O_PP_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_PP_SYMBOL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:12:05 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132,
n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154,
n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165,
n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176,
n177, n178, n179, n180, n181, n182, n183, n184;
OA21XLTS U74 ( .A0(n181), .A1(n183), .B0(n161), .Y(n131) );
NAND2X1TS U75 ( .A(n64), .B(n63), .Y(n182) );
NAND2X1TS U76 ( .A(n117), .B(in1[3]), .Y(n161) );
XNOR2X2TS U77 ( .A(n69), .B(in2[15]), .Y(n112) );
NAND2X1TS U78 ( .A(n100), .B(in1[10]), .Y(n136) );
NAND2X1TS U79 ( .A(n70), .B(add_sub), .Y(n71) );
NAND2X1TS U80 ( .A(in1[2]), .B(n59), .Y(n181) );
CMPR32X2TS U81 ( .A(n157), .B(in1[7]), .C(n156), .CO(n170), .S(res[7]) );
XOR2X2TS U82 ( .A(n73), .B(in2[13]), .Y(n107) );
NOR2X1TS U83 ( .A(n72), .B(n101), .Y(n73) );
NAND2XLTS U84 ( .A(n98), .B(add_sub), .Y(n99) );
NOR2XLTS U85 ( .A(n102), .B(n101), .Y(n103) );
XOR2X2TS U86 ( .A(n91), .B(in2[9]), .Y(n95) );
NOR2X1TS U87 ( .A(n90), .B(n101), .Y(n91) );
INVX2TS U88 ( .A(add_sub), .Y(n101) );
NOR2XLTS U89 ( .A(n101), .B(n60), .Y(n61) );
XOR2X1TS U90 ( .A(n103), .B(in2[11]), .Y(n104) );
NAND2X1TS U91 ( .A(n106), .B(in1[12]), .Y(n145) );
NOR2X6TS U92 ( .A(n92), .B(in2[8]), .Y(n90) );
NAND2X2TS U93 ( .A(n79), .B(add_sub), .Y(n80) );
NAND2X2TS U94 ( .A(n177), .B(n176), .Y(n178) );
XNOR2X2TS U95 ( .A(n75), .B(in2[12]), .Y(n106) );
NAND2X2TS U96 ( .A(n74), .B(add_sub), .Y(n75) );
NOR2X6TS U97 ( .A(n79), .B(in2[6]), .Y(n77) );
AO21X2TS U98 ( .A0(n114), .A1(n174), .B0(n113), .Y(res[16]) );
XOR2X1TS U99 ( .A(n155), .B(n154), .Y(res[13]) );
AOI21X2TS U100 ( .A0(n151), .A1(n150), .B0(n149), .Y(n155) );
NAND2X2TS U101 ( .A(n107), .B(in1[13]), .Y(n152) );
XOR2X1TS U102 ( .A(n129), .B(n128), .Y(res[9]) );
XNOR2X2TS U103 ( .A(n99), .B(in2[10]), .Y(n100) );
XOR2X1TS U104 ( .A(n166), .B(n165), .Y(res[6]) );
XNOR2X2TS U105 ( .A(n93), .B(in2[8]), .Y(n94) );
XOR2X1TS U106 ( .A(n121), .B(n158), .Y(res[5]) );
NOR2X1TS U107 ( .A(n164), .B(n163), .Y(n165) );
AND2X2TS U108 ( .A(n88), .B(in1[6]), .Y(n163) );
OA21XLTS U109 ( .A0(n64), .A1(n63), .B0(n182), .Y(res[2]) );
INVX1TS U110 ( .A(n158), .Y(n162) );
XOR2XLTS U111 ( .A(n180), .B(n122), .Y(res[1]) );
XOR2X1TS U112 ( .A(n130), .B(in1[1]), .Y(n122) );
OAI21X1TS U113 ( .A0(n180), .A1(in1[1]), .B0(n130), .Y(n62) );
AOI2BB1XLTS U114 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n180), .Y(res[0]) );
OAI21X1TS U115 ( .A0(in2[1]), .A1(in2[0]), .B0(add_sub), .Y(n58) );
OAI21X1TS U116 ( .A0(n131), .A1(n160), .B0(n119), .Y(n121) );
NAND2X4TS U117 ( .A(n118), .B(in1[4]), .Y(n119) );
XNOR2X2TS U118 ( .A(n116), .B(in2[3]), .Y(n117) );
NAND2BX4TS U119 ( .AN(in2[7]), .B(n77), .Y(n92) );
XNOR2X2TS U120 ( .A(n82), .B(in2[4]), .Y(n118) );
NAND2X1TS U121 ( .A(n81), .B(add_sub), .Y(n82) );
XNOR2X2TS U122 ( .A(n84), .B(in2[5]), .Y(n120) );
NAND2X2TS U123 ( .A(n92), .B(add_sub), .Y(n93) );
NOR2BX2TS U124 ( .AN(in1[0]), .B(n60), .Y(n180) );
OAI21X2TS U125 ( .A0(n118), .A1(in1[4]), .B0(n119), .Y(n160) );
INVX2TS U126 ( .A(n167), .Y(n124) );
NAND2BX2TS U127 ( .AN(in2[13]), .B(n72), .Y(n70) );
INVX2TS U128 ( .A(n163), .Y(n89) );
NAND2X1TS U129 ( .A(n168), .B(n167), .Y(n169) );
XOR2XLTS U130 ( .A(n139), .B(n138), .Y(res[10]) );
NAND2X1TS U131 ( .A(n150), .B(n145), .Y(n146) );
NOR2X4TS U132 ( .A(n95), .B(in1[9]), .Y(n125) );
AOI21X2TS U133 ( .A0(n89), .A1(n159), .B0(n164), .Y(n156) );
NOR2X4TS U134 ( .A(n112), .B(in1[15]), .Y(n175) );
OAI21X4TS U135 ( .A0(n110), .A1(n144), .B0(n109), .Y(n174) );
AOI21X4TS U136 ( .A0(n143), .A1(n141), .B0(n105), .Y(n144) );
AOI21X2TS U137 ( .A0(n153), .A1(n149), .B0(n108), .Y(n109) );
NAND2BX4TS U138 ( .AN(in2[9]), .B(n90), .Y(n98) );
XNOR2X4TS U139 ( .A(n71), .B(in2[14]), .Y(n111) );
OAI21X4TS U140 ( .A0(n119), .A1(n85), .B0(n120), .Y(n86) );
XNOR2X4TS U141 ( .A(n80), .B(in2[6]), .Y(n88) );
XNOR2X1TS U142 ( .A(n58), .B(in2[2]), .Y(n59) );
OAI21X1TS U143 ( .A0(in1[2]), .A1(n59), .B0(n181), .Y(n133) );
INVX2TS U144 ( .A(n133), .Y(n64) );
INVX4TS U145 ( .A(in2[0]), .Y(n60) );
CLKXOR2X2TS U146 ( .A(n61), .B(in2[1]), .Y(n130) );
OAI2BB1X1TS U147 ( .A0N(n180), .A1N(in1[1]), .B0(n62), .Y(n63) );
INVX2TS U148 ( .A(in2[1]), .Y(n67) );
INVX2TS U149 ( .A(in2[2]), .Y(n66) );
INVX2TS U150 ( .A(in2[3]), .Y(n65) );
NAND4X4TS U151 ( .A(n60), .B(n67), .C(n66), .D(n65), .Y(n81) );
NOR2X4TS U152 ( .A(n81), .B(in2[4]), .Y(n83) );
INVX2TS U153 ( .A(in2[5]), .Y(n68) );
NAND2X4TS U154 ( .A(n83), .B(n68), .Y(n79) );
NOR2X4TS U155 ( .A(n98), .B(in2[10]), .Y(n102) );
NAND2BX4TS U156 ( .AN(in2[11]), .B(n102), .Y(n74) );
NOR2X4TS U157 ( .A(n74), .B(in2[12]), .Y(n72) );
OAI21X1TS U158 ( .A0(n70), .A1(in2[14]), .B0(add_sub), .Y(n69) );
NOR2X2TS U159 ( .A(n111), .B(in1[14]), .Y(n147) );
NOR2X1TS U160 ( .A(n175), .B(n147), .Y(n114) );
OR2X2TS U161 ( .A(n107), .B(in1[13]), .Y(n153) );
NOR2X1TS U162 ( .A(n106), .B(in1[12]), .Y(n76) );
INVX2TS U163 ( .A(n76), .Y(n150) );
NAND2X2TS U164 ( .A(n153), .B(n150), .Y(n110) );
NOR2X1TS U165 ( .A(n77), .B(n101), .Y(n78) );
XOR2X1TS U166 ( .A(n78), .B(in2[7]), .Y(n157) );
INVX2TS U167 ( .A(n119), .Y(n87) );
INVX2TS U168 ( .A(in1[5]), .Y(n85) );
NOR2X1TS U169 ( .A(n83), .B(n101), .Y(n84) );
OAI21X4TS U170 ( .A0(n87), .A1(in1[5]), .B0(n86), .Y(n159) );
NOR2X2TS U171 ( .A(n88), .B(in1[6]), .Y(n164) );
NOR2X2TS U172 ( .A(n94), .B(in1[8]), .Y(n123) );
NOR2X1TS U173 ( .A(n125), .B(n123), .Y(n97) );
NAND2X2TS U174 ( .A(n94), .B(in1[8]), .Y(n167) );
NAND2X2TS U175 ( .A(n95), .B(in1[9]), .Y(n126) );
OAI21X1TS U176 ( .A0(n125), .A1(n167), .B0(n126), .Y(n96) );
AOI21X4TS U177 ( .A0(n170), .A1(n97), .B0(n96), .Y(n139) );
NOR2X2TS U178 ( .A(n100), .B(in1[10]), .Y(n135) );
OAI21X4TS U179 ( .A0(n139), .A1(n135), .B0(n136), .Y(n143) );
OR2X2TS U180 ( .A(n104), .B(in1[11]), .Y(n141) );
NAND2X2TS U181 ( .A(n104), .B(in1[11]), .Y(n140) );
INVX2TS U182 ( .A(n140), .Y(n105) );
INVX2TS U183 ( .A(n145), .Y(n149) );
INVX2TS U184 ( .A(n152), .Y(n108) );
NAND2X2TS U185 ( .A(n111), .B(in1[14]), .Y(n171) );
NAND2X2TS U186 ( .A(n112), .B(in1[15]), .Y(n176) );
OAI21X1TS U187 ( .A0(n175), .A1(n171), .B0(n176), .Y(n113) );
OR3X1TS U188 ( .A(in2[2]), .B(in2[1]), .C(in2[0]), .Y(n115) );
NAND2X1TS U189 ( .A(add_sub), .B(n115), .Y(n116) );
OAI21X2TS U190 ( .A0(n117), .A1(in1[3]), .B0(n161), .Y(n183) );
XNOR2X1TS U191 ( .A(n120), .B(in1[5]), .Y(n158) );
INVX2TS U192 ( .A(n123), .Y(n168) );
AOI21X1TS U193 ( .A0(n170), .A1(n168), .B0(n124), .Y(n129) );
INVX2TS U194 ( .A(n125), .Y(n127) );
NAND2X1TS U195 ( .A(n127), .B(n126), .Y(n128) );
NAND2X1TS U196 ( .A(n130), .B(in1[1]), .Y(n132) );
OAI31X1TS U197 ( .A0(n133), .A1(n183), .A2(n132), .B0(n131), .Y(n134) );
XNOR2X1TS U198 ( .A(n134), .B(n160), .Y(res[4]) );
INVX2TS U199 ( .A(n135), .Y(n137) );
NAND2X1TS U200 ( .A(n137), .B(n136), .Y(n138) );
NAND2X1TS U201 ( .A(n141), .B(n140), .Y(n142) );
XNOR2X1TS U202 ( .A(n143), .B(n142), .Y(res[11]) );
INVX2TS U203 ( .A(n144), .Y(n151) );
XNOR2X1TS U204 ( .A(n151), .B(n146), .Y(res[12]) );
INVX2TS U205 ( .A(n147), .Y(n173) );
NAND2X1TS U206 ( .A(n173), .B(n171), .Y(n148) );
XNOR2X1TS U207 ( .A(n174), .B(n148), .Y(res[14]) );
NAND2X1TS U208 ( .A(n153), .B(n152), .Y(n154) );
OAI31X1TS U209 ( .A0(n162), .A1(n161), .A2(n160), .B0(n159), .Y(n166) );
XNOR2X1TS U210 ( .A(n170), .B(n169), .Y(res[8]) );
INVX2TS U211 ( .A(n171), .Y(n172) );
AOI21X4TS U212 ( .A0(n174), .A1(n173), .B0(n172), .Y(n179) );
INVX2TS U213 ( .A(n175), .Y(n177) );
XOR2X1TS U214 ( .A(n179), .B(n178), .Y(res[15]) );
NAND2X1TS U215 ( .A(n182), .B(n181), .Y(n184) );
XNOR2X1TS U216 ( .A(n184), .B(n183), .Y(res[3]) );
initial $sdf_annotate("Approx_adder_GDAN8M8P3_syn.sdf");
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.4
// \ \ Application :
// / / Filename : xil_9032_39
// /___/ /\ Timestamp : 07/03/2015 00:57:55
// \ \ / \
// \___\/\___\
//
//Command:
//Design Name:
//
`timescale 1ns / 1ps
module SSeg_map(input[63:0]Disp_num,
output[63:0]Seg_map
);
assign Seg_map = {Disp_num[0], Disp_num[4], Disp_num[16], Disp_num[25], Disp_num[17], Disp_num[5], Disp_num[12], Disp_num[24],
Disp_num[1], Disp_num[6], Disp_num[18], Disp_num[27], Disp_num[19], Disp_num[7], Disp_num[13], Disp_num[26],
Disp_num[2], Disp_num[8], Disp_num[20], Disp_num[29], Disp_num[21], Disp_num[9], Disp_num[14], Disp_num[28],
Disp_num[3], Disp_num[10], Disp_num[22], Disp_num[31], Disp_num[23], Disp_num[11], Disp_num[15], Disp_num[30],
Disp_num[0], Disp_num[4], Disp_num[16], Disp_num[25], Disp_num[17], Disp_num[5], Disp_num[12], Disp_num[24],
Disp_num[1], Disp_num[6], Disp_num[18], Disp_num[27], Disp_num[19], Disp_num[7], Disp_num[13], Disp_num[26],
Disp_num[2], Disp_num[8], Disp_num[20], Disp_num[29], Disp_num[21], Disp_num[9], Disp_num[14], Disp_num[28],
Disp_num[3], Disp_num[10], Disp_num[22], Disp_num[31], Disp_num[23], Disp_num[11], Disp_num[15], Disp_num[30]};
endmodule |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:18:00 11/19/2013
// Design Name: i2s_out
// Module Name: C:/Users/Fabian/Desktop/Respaldo taller/taller-diseno-digital-master/Proyecto Final/tec-drums/i2s_test.v
// Project Name: tec-drums
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: i2s_out
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module i2s_test;
// Inputs
reg clock;
reg reset;
reg [15:0] left_data;
reg [15:0] right_data;
// Outputs
wire mclk;
wire lrck;
wire sclk;
wire sdin;
// Instantiate the Unit Under Test (UUT)
i2s_out uut (
.clock(clock),
.reset(reset),
.left_data(left_data),
.right_data(right_data),
.mclk(mclk),
.lrck(lrck),
.sclk(sclk),
.sdin(sdin)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
left_data = 0;
right_data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
// This is a component of pluto_servo_spi, a PWM servo driver and quadrature
// counter for linuxcnc and the RaspberryPi over SPI.
// based on the servo.v from Jeff Epler <[email protected]>
// Copyright 2013 by Matsche <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//**********************************************************************
/* Open-Drain buffer
module OC_Buff(in, out);
input in;
output out;
assign out = in ? 1'bz : 1'b0;
endmodule
*/
//**********************************************************************
module pluto_spi_rspi(clk, SCK, MOSI, MISO, SSEL, LED, nConfig, nRESET, nPE, quadA, quadB, quadZ, up, down, dout, din);
parameter QW=14;
input clk;
input SCK, SSEL, MOSI, nRESET;
output MISO, nConfig, nPE;
output LED;
//output [3:0] down = 4'bZZZZ;
//output [3:0] up = 4'bZZZZ;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire do_tristate;
assign nConfig = nRESET;
//assign nConfig = 1'b1;
assign nPE = 1'b1;
reg[9:0] real_dout;
output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
wire[3:0] real_up;
output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down;
output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
//**********************************************************************
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
wire pwm_at_top;
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2047;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt; // pwm0[14] = pdm/pwm bit
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
//**********************************************************************
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire qr0, qr1, qr2, qr3;
//quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q0(clk, quadA[0], quadB[0], quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
//**********************************************************************
// SPI zeugs
// synchronizing the handshakes
//
reg [2:0] SCKr;
always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
wire SCK_fallingedge = (SCKr[2:1]==2'b10); // and falling edges
wire SCK_high = SCKr[1]; // SCK is high
// same thing for SSEL
reg [2:0] SSELr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
wire MOSI_data = MOSI;
// we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
reg [2:0] bitcnt;
reg byte_received; // high when 8 bit has been received
reg [4:0] spibytecnt;
reg [7:0] data_recvd;
reg [7:0] data_sent;
reg [7:0] data_outbuf;
always @(posedge clk) begin
if(SSEL_startmessage) begin
//data_sent <= data_outbuf;
bitcnt <= 3'b000;
spibytecnt <= 5'b00000;
end
if(SSEL_active) begin
if(SCK_risingedge) begin
data_recvd <= {data_recvd[6:0], MOSI_data};
bitcnt <= bitcnt + 3'b001;
if(bitcnt==3'b000)
data_sent <= data_outbuf;
end
else if(SCK_fallingedge) begin
data_sent <= {data_sent[6:0], 1'b0};
if(bitcnt==3'b000) begin
spibytecnt <= spibytecnt + 5'b00001;
end
end
byte_received <= SCK_risingedge && (bitcnt==3'b111);
end
end
assign MISO = data_sent[7]; // send MSB first
// we assume that there is only one slave on the SPI bus
// so we don't bother with a tri-state buffer for MISO
// otherwise we would need to tri-state MISO when SSEL is inactive
reg [7:0] data_inbuf;
always @(posedge clk) begin
if(SSEL_active) begin
//------------------------------------------------- word 0
if(spibytecnt == 5'b00000) begin // 0
data_outbuf <= quad0[7:0];
if(byte_received)
data_inbuf <= data_recvd; //pwm0[7:0]
end
else if(spibytecnt == 5'b00001) begin // 1
data_outbuf <= quad0[15:8];
if(byte_received)
pwm0 <= {data_recvd,data_inbuf}; //pwm0
end
else if(spibytecnt == 5'b00010) begin // 2
data_outbuf <= quad0[23:16];
if(byte_received)
data_inbuf <= data_recvd; //pwm1[7:0]
end
else if(spibytecnt == 5'b00011) begin // 3
data_outbuf <= {4'b0, quad0[27:24]};
if(byte_received)
pwm1 <= {data_recvd,data_inbuf}; //pwm1
end
//------------------------------------------------- word 1
else if(spibytecnt == 5'b00100) begin // 4
data_outbuf <= quad1[7:0];
if(byte_received)
data_inbuf <= data_recvd; //pwm2[7:0]
end
else if(spibytecnt == 5'b00101) begin // 5
data_outbuf <= quad1[15:8];
if(byte_received)
pwm2 <= {data_recvd,data_inbuf}; //pwm2
end
else if(spibytecnt == 5'b00110) begin // 6
data_outbuf <= quad1[23:16];
if(byte_received)
data_inbuf <= data_recvd; //pwm3[7:0]
end
else if(spibytecnt == 5'b00111) begin // 7
data_outbuf <= {4'b0, quad1[27:24]};
if(byte_received)
pwm3 <= {data_recvd,data_inbuf}; //pwm3
end
//------------------------------------------------- word 2
else if(spibytecnt == 5'b01000) begin // 8
data_outbuf <= quad2[7:0];
if(byte_received)
data_inbuf <= data_recvd; //real_dout[7:0]
end
else if(spibytecnt == 5'b01001) begin // 9
data_outbuf <= quad2[15:8];
if(byte_received) begin
real_dout <= {data_recvd[1:0],data_inbuf}; //real_dout[9:8]
Zpolarity <= data_recvd[7]; //Zpolarity
qtest <= data_recvd[5]; //qtest
end
end
else if(spibytecnt == 5'b01010) data_outbuf <= quad2[23:16]; // 10
else if(spibytecnt == 5'b01011) data_outbuf <= {4'b0, quad2[27:24]}; // 11
//------------------------------------------------- word 3
else if(spibytecnt == 5'b01100) data_outbuf <= quad3[7:0];
else if(spibytecnt == 5'b01101) data_outbuf <= quad3[15:8];
else if(spibytecnt == 5'b01110) data_outbuf <= quad3[23:16];
else if(spibytecnt == 5'b01111) data_outbuf <= {4'b0, quad3[27:24]};
//------------------------------------------------- word 4
else if(spibytecnt == 5'b10000) data_outbuf <= din;
else if(spibytecnt == 5'b10001) data_outbuf <= {quadB, quadZ};
else if(spibytecnt == 5'b10010) data_outbuf <= {4'b0, quadA};
else if(spibytecnt == 5'b10011) data_outbuf <= 8'b0;
else data_outbuf <= spibytecnt;
end
end
assign LED = (real_up[0] ^ real_down[0]);
endmodule
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.1 (lin64) Build 1215546 Mon Apr 27 19:07:21 MDT 2015
//Date : Sat Aug 8 13:34:20 2015
//Host : edinburgh running 64-bit Ubuntu 15.04
//Command : generate_target opl3_cpu_wrapper.bd
//Design : opl3_cpu_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module opl3_cpu_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
ac_mclk,
ac_mute_n,
clk125,
i2s_sclk,
i2s_sd,
i2s_ws,
iic_0_scl_io,
iic_0_sda_io,
led);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output ac_mclk;
output ac_mute_n;
input clk125;
output i2s_sclk;
output i2s_sd;
output i2s_ws;
inout iic_0_scl_io;
inout iic_0_sda_io;
output [3:0]led;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire ac_mclk;
wire ac_mute_n;
wire clk125;
wire i2s_sclk;
wire i2s_sd;
wire i2s_ws;
wire iic_0_scl_i;
wire iic_0_scl_io;
wire iic_0_scl_o;
wire iic_0_scl_t;
wire iic_0_sda_i;
wire iic_0_sda_io;
wire iic_0_sda_o;
wire iic_0_sda_t;
wire [3:0]led;
IOBUF iic_0_scl_iobuf
(.I(iic_0_scl_o),
.IO(iic_0_scl_io),
.O(iic_0_scl_i),
.T(iic_0_scl_t));
IOBUF iic_0_sda_iobuf
(.I(iic_0_sda_o),
.IO(iic_0_sda_io),
.O(iic_0_sda_i),
.T(iic_0_sda_t));
opl3_cpu opl3_cpu_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.IIC_0_scl_i(iic_0_scl_i),
.IIC_0_scl_o(iic_0_scl_o),
.IIC_0_scl_t(iic_0_scl_t),
.IIC_0_sda_i(iic_0_sda_i),
.IIC_0_sda_o(iic_0_sda_o),
.IIC_0_sda_t(iic_0_sda_t),
.ac_mclk(ac_mclk),
.ac_mute_n(ac_mute_n),
.clk125(clk125),
.i2s_sclk(i2s_sclk),
.i2s_sd(i2s_sd),
.i2s_ws(i2s_ws),
.led(led));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_P_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_P_BLACKBOX_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dlatch$P (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_P_BLACKBOX_V
|
`timescale 1ns / 1ps
/* This file is part of JT51.
JT51 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-4-2017
*/
module jt51_phrom
(
input [4:0] addr,
input clk,
output reg [45:0] ph
);
reg [45:0] sinetable[31:0];
initial
begin
sinetable[5'd0 ] = 46'b0001100000100100010001000010101010101001010010;
sinetable[5'd1 ] = 46'b0001100000110100000100000010010001001101000001;
sinetable[5'd2 ] = 46'b0001100000110100000100110010001011001101100000;
sinetable[5'd3 ] = 46'b0001110000010000000000110010110001001101110010;
sinetable[5'd4 ] = 46'b0001110000010000001100000010111010001101101001;
sinetable[5'd5 ] = 46'b0001110000010100001001100010000000101101111010;
sinetable[5'd6 ] = 46'b0001110000010100001101100010010011001101011010;
sinetable[5'd7 ] = 46'b0001110000011100000101010010111000101111111100;
sinetable[5'd8 ] = 46'b0001110000111000000001110010101110001101110111;
sinetable[5'd9 ] = 46'b0001110000111000010100111000011101011010100110;
sinetable[5'd10] = 46'b0001110000111100011000011000111100001001111010;
sinetable[5'd11] = 46'b0001110000111100011100111001101011001001110111;
sinetable[5'd12] = 46'b0100100001010000010001011001001000111010110111;
sinetable[5'd13] = 46'b0100100001010100010001001001110001111100101010;
sinetable[5'd14] = 46'b0100100001010100010101101101111110100101000110;
sinetable[5'd15] = 46'b0100100011100000001000011001010110101101111001;
sinetable[5'd16] = 46'b0100100011100100001000101011100101001011101111;
sinetable[5'd17] = 46'b0100100011101100000111011010000001011010110001;
sinetable[5'd18] = 46'b0100110011001000000111101010000010111010111111;
sinetable[5'd19] = 46'b0100110011001100001011011110101110110110000001;
sinetable[5'd20] = 46'b0100110011101000011010111011001010001101110001;
sinetable[5'd21] = 46'b0100110011101101011010110101111001010100001111;
sinetable[5'd22] = 46'b0111000010000001010111000101010101010110010111;
sinetable[5'd23] = 46'b0111000010000101010111110111110101010010111011;
sinetable[5'd24] = 46'b0111000010110101101000101100001000010000011001;
sinetable[5'd25] = 46'b0111010010011001100100011110100100010010010010;
sinetable[5'd26] = 46'b0111010010111010100101100101000000110100100011;
sinetable[5'd27] = 46'b1010000010011010101101011101100001110010011010;
sinetable[5'd28] = 46'b1010000010111111111100100111010100010000111001;
sinetable[5'd29] = 46'b1010010111110100110010001100111001010110100000;
sinetable[5'd30] = 46'b1011010111010011111011011110000100110010100001;
sinetable[5'd31] = 46'b1110011011110001111011100111100001110110100111;
end
always @ (posedge clk)
ph <= sinetable[addr];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_SYMBOL_V
`define SKY130_FD_SC_HD__TAPVGND2_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_SYMBOL_V
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module output_queues
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter OP_LUT_STAGE_NUM = 4,
parameter NUM_OUTPUT_QUEUES = 8,
parameter STAGE_NUM = 6,
parameter SRAM_ADDR_WIDTH = 13
)
(// --- data path interface
out_data_0,
out_ctrl_0,
out_rdy_0,
out_wr_0,
out_data_1,
out_ctrl_1,
out_rdy_1,
out_wr_1,
out_data_2,
out_ctrl_2,
out_rdy_2,
out_wr_2,
out_data_3,
out_ctrl_3,
out_rdy_3,
out_wr_3,
out_data_4,
out_ctrl_4,
out_rdy_4,
out_wr_4,
out_data_5,
out_ctrl_5,
out_wr_5,
out_rdy_5,
out_data_6,
out_ctrl_6,
out_wr_6,
out_rdy_6,
out_data_7,
out_ctrl_7,
out_wr_7,
out_rdy_7,
// --- Interface to the previous module
in_data,
in_ctrl,
in_rdy,
in_wr,
// --- Register interface
reg_req_in,
reg_ack_in,
reg_rd_wr_L_in,
reg_addr_in,
reg_data_in,
reg_src_in,
reg_req_out,
reg_ack_out,
reg_rd_wr_L_out,
reg_addr_out,
reg_data_out,
reg_src_out,
// --- SRAM sm interface
wr_0_addr,
wr_0_req,
wr_0_ack,
wr_0_data,
rd_0_ack,
rd_0_data,
rd_0_vld,
rd_0_addr,
rd_0_req,
// --- Misc
clk,
reset
);
output [DATA_WIDTH-1:0] out_data_0;
output [CTRL_WIDTH-1:0] out_ctrl_0;
input out_rdy_0;
output out_wr_0;
output [DATA_WIDTH-1:0] out_data_1;
output [CTRL_WIDTH-1:0] out_ctrl_1;
input out_rdy_1;
output out_wr_1;
output [DATA_WIDTH-1:0] out_data_2;
output [CTRL_WIDTH-1:0] out_ctrl_2;
input out_rdy_2;
output out_wr_2;
output [DATA_WIDTH-1:0] out_data_3;
output [CTRL_WIDTH-1:0] out_ctrl_3;
input out_rdy_3;
output out_wr_3;
output [DATA_WIDTH-1:0] out_data_4;
output [CTRL_WIDTH-1:0] out_ctrl_4;
input out_rdy_4;
output out_wr_4;
output [DATA_WIDTH-1:0] out_data_5;
output [CTRL_WIDTH-1:0] out_ctrl_5;
output out_wr_5;
input out_rdy_5;
output [DATA_WIDTH-1:0] out_data_6;
output [CTRL_WIDTH-1:0] out_ctrl_6;
output out_wr_6;
input out_rdy_6;
output [DATA_WIDTH-1:0] out_data_7;
output [CTRL_WIDTH-1:0] out_ctrl_7;
output out_wr_7;
input out_rdy_7;
// --- Interface to the previous module
input [DATA_WIDTH-1:0] in_data;
input [CTRL_WIDTH-1:0] in_ctrl;
output in_rdy;
input in_wr;
// --- Register interface
input reg_req_in;
input reg_ack_in;
input reg_rd_wr_L_in;
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in;
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in;
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in;
output reg_req_out;
output reg_ack_out;
output reg_rd_wr_L_out;
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out;
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out;
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out;
// --- SRAM sm interface
output [SRAM_ADDR_WIDTH-1:0] wr_0_addr;
output wr_0_req;
input wr_0_ack;
output [DATA_WIDTH+CTRL_WIDTH-1:0] wr_0_data;
input rd_0_ack;
input [DATA_WIDTH+CTRL_WIDTH-1:0] rd_0_data;
input rd_0_vld;
output [SRAM_ADDR_WIDTH-1:0] rd_0_addr;
output rd_0_req;
// --- Misc
input clk;
input reset;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//------------- Internal Parameters ---------------
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES);
parameter PKT_LEN_WIDTH = 11;
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH);
parameter MAX_PKT = 2048; // allow for 2K bytes
parameter PKT_BYTE_CNT_WIDTH = log2(MAX_PKT);
parameter PKT_WORD_CNT_WIDTH = log2(MAX_PKT/CTRL_WIDTH);
//--------------- Regs/Wires ----------------------
wire [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr;
wire [SRAM_ADDR_WIDTH-1:0] src_oq_high_addr;
wire [SRAM_ADDR_WIDTH-1:0] src_oq_low_addr;
wire [NUM_OUTPUT_QUEUES-1:0]src_oq_empty;
wire [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr_new;
wire pkt_removed;
wire [PKT_LEN_WIDTH-1:0] removed_pkt_data_length;
wire [CTRL_WIDTH-1:0] removed_pkt_overhead_length;
wire [PKT_WORDS_WIDTH-1:0] removed_pkt_total_word_length;
wire [NUM_OQ_WIDTH-1:0] src_oq;
wire [NUM_OQ_WIDTH-1:0] removed_oq;
wire rd_src_addr;
wire [NUM_OUTPUT_QUEUES-1:0] enable_send_pkt;
wire dst_oq_avail;
wire [NUM_OQ_WIDTH-1:0] parsed_dst_oq;
wire [PKT_BYTE_CNT_WIDTH-1:0] parsed_pkt_byte_len;
wire [PKT_WORD_CNT_WIDTH-1:0] parsed_pkt_word_len;
wire rd_dst_oq;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr_new;
wire pkt_stored;
wire pkt_dropped;
wire [PKT_LEN_WIDTH-1:0] stored_pkt_data_length;
wire [CTRL_WIDTH-1:0] stored_pkt_overhead_length;
wire [PKT_WORDS_WIDTH-1:0] stored_pkt_total_word_length;
wire [NUM_OQ_WIDTH-1:0] dst_oq;
wire rd_dst_addr;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_high_addr;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_low_addr;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr;
wire [NUM_OUTPUT_QUEUES-1:0]dst_oq_full;
wire input_fifo_rd_en;
wire input_fifo_empty;
wire [DATA_WIDTH-1:0] input_fifo_data_out;
wire [CTRL_WIDTH-1:0] input_fifo_ctrl_out;
wire input_fifo_nearly_full;
//---------------- Modules ------------------------
oq_header_parser
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.OP_LUT_STAGE_NUM(OP_LUT_STAGE_NUM),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES))
oq_header_parser
(
.parsed_dst_oq (parsed_dst_oq),
.parsed_pkt_byte_len (parsed_pkt_byte_len),
.parsed_pkt_word_len (parsed_pkt_word_len),
.header_parser_rdy (header_parser_rdy),
.dst_oq_avail (dst_oq_avail),
.rd_dst_oq (rd_dst_oq),
.in_wr (in_wr),
.in_ctrl (in_ctrl),
.in_data (in_data),
.clk (clk),
.reset (reset));
fallthrough_small_fifo
#(.WIDTH(DATA_WIDTH+CTRL_WIDTH),
.MAX_DEPTH_BITS(3))
input_fifo
(.dout({input_fifo_ctrl_out, input_fifo_data_out}),
.full(),
.prog_full (),
.nearly_full(input_fifo_nearly_full),
.empty(input_fifo_empty),
.din({in_ctrl, in_data}),
.wr_en(in_wr),
.rd_en(input_fifo_rd_en),
.reset(reset),
.clk(clk));
store_pkt
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
.SRAM_ADDR_WIDTH(SRAM_ADDR_WIDTH),
.OQ_STAGE_NUM (STAGE_NUM),
.PKT_LEN_WIDTH(PKT_LEN_WIDTH))
store_pkt
( // --- Interface to header_parser
.dst_oq_avail (dst_oq_avail),
.parsed_dst_oq (parsed_dst_oq),
.parsed_pkt_byte_len (parsed_pkt_byte_len),
.parsed_pkt_word_len (parsed_pkt_word_len),
.rd_dst_oq (rd_dst_oq),
// --- Interface to registers
.dst_oq_wr_addr_new (dst_oq_wr_addr_new),
.pkt_stored (pkt_stored),
.pkt_dropped (pkt_dropped),
.stored_pkt_data_length (stored_pkt_data_length),
.stored_pkt_overhead_length (stored_pkt_overhead_length),
.stored_pkt_total_word_length (stored_pkt_total_word_length),
.dst_oq (dst_oq),
.rd_dst_addr (rd_dst_addr),
.dst_oq_high_addr (dst_oq_high_addr),
.dst_oq_low_addr (dst_oq_low_addr),
.dst_oq_wr_addr (dst_oq_wr_addr),
.dst_oq_full (dst_oq_full),
// --- Interface to SRAM
.wr_0_addr (wr_0_addr),
.wr_0_req (wr_0_req),
.wr_0_ack (wr_0_ack),
.wr_0_data (wr_0_data),
// --- Interface to input fifo
.input_fifo_rd_en (input_fifo_rd_en),
.input_fifo_empty (input_fifo_empty),
.input_fifo_data_out (input_fifo_data_out),
.input_fifo_ctrl_out (input_fifo_ctrl_out),
// --- misc
.clk (clk),
.reset (reset));
remove_pkt
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
.SRAM_ADDR_WIDTH(SRAM_ADDR_WIDTH),
.OQ_STAGE_NUM (STAGE_NUM),
.OP_LUT_STAGE_NUM(OP_LUT_STAGE_NUM),
.PKT_LEN_WIDTH(PKT_LEN_WIDTH))
remove_pkt
(// --- Interface to SRAM
.rd_0_ack (rd_0_ack),
.rd_0_data (rd_0_data),
.rd_0_vld (rd_0_vld),
.rd_0_addr (rd_0_addr),
.rd_0_req (rd_0_req),
// --- Interface to regs
.src_oq_rd_addr (src_oq_rd_addr),
.src_oq_high_addr (src_oq_high_addr),
.src_oq_low_addr (src_oq_low_addr),
.src_oq_empty (src_oq_empty),
.src_oq_rd_addr_new (src_oq_rd_addr_new),
.pkt_removed (pkt_removed),
.removed_pkt_data_length (removed_pkt_data_length),
.removed_pkt_overhead_length (removed_pkt_overhead_length),
.removed_pkt_total_word_length (removed_pkt_total_word_length),
.src_oq (src_oq),
.removed_oq (removed_oq),
.rd_src_addr (rd_src_addr),
.enable_send_pkt (enable_send_pkt),
// --- Interface to datapath
.out_data_0 (out_data_0),
.out_ctrl_0 (out_ctrl_0),
.out_wr_0 (out_wr_0),
.out_rdy_0 (out_rdy_0),
.out_data_1 (out_data_1),
.out_ctrl_1 (out_ctrl_1),
.out_wr_1 (out_wr_1),
.out_rdy_1 (out_rdy_1),
.out_data_2 (out_data_2),
.out_ctrl_2 (out_ctrl_2),
.out_wr_2 (out_wr_2),
.out_rdy_2 (out_rdy_2),
.out_data_3 (out_data_3),
.out_ctrl_3 (out_ctrl_3),
.out_wr_3 (out_wr_3),
.out_rdy_3 (out_rdy_3),
.out_data_4 (out_data_4),
.out_ctrl_4 (out_ctrl_4),
.out_wr_4 (out_wr_4),
.out_rdy_4 (out_rdy_4),
.out_data_5 (out_data_5),
.out_ctrl_5 (out_ctrl_5),
.out_wr_5 (out_wr_5),
.out_rdy_5 (out_rdy_5),
.out_data_6 (out_data_6),
.out_ctrl_6 (out_ctrl_6),
.out_wr_6 (out_wr_6),
.out_rdy_6 (out_rdy_6),
.out_data_7 (out_data_7),
.out_ctrl_7 (out_ctrl_7),
.out_wr_7 (out_wr_7),
.out_rdy_7 (out_rdy_7),
// --- Misc
.clk (clk),
.reset (reset));
oq_regs
#(
.SRAM_ADDR_WIDTH(SRAM_ADDR_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
.PKT_LEN_WIDTH(PKT_LEN_WIDTH))
oq_regs
(// --- interface to udp_reg_grp
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
// --- interface to remove_pkt
.src_oq_rd_addr (src_oq_rd_addr),
.src_oq_high_addr (src_oq_high_addr),
.src_oq_low_addr (src_oq_low_addr),
.src_oq_empty (src_oq_empty),
.src_oq_rd_addr_new (src_oq_rd_addr_new),
.pkt_removed (pkt_removed),
.removed_pkt_data_length (removed_pkt_data_length),
.removed_pkt_overhead_length (removed_pkt_overhead_length),
.removed_pkt_total_word_length (removed_pkt_total_word_length),
.src_oq (src_oq),
.removed_oq (removed_oq),
.rd_src_addr (rd_src_addr),
.enable_send_pkt (enable_send_pkt),
// --- interface to store_pkt
.dst_oq_wr_addr_new (dst_oq_wr_addr_new),
.pkt_stored (pkt_stored),
.stored_pkt_data_length (stored_pkt_data_length),
.stored_pkt_overhead_length (stored_pkt_overhead_length),
.stored_pkt_total_word_length (stored_pkt_total_word_length),
.pkt_dropped (pkt_dropped),
.dst_oq (dst_oq),
.rd_dst_addr (rd_dst_addr),
.dst_oq_high_addr (dst_oq_high_addr),
.dst_oq_low_addr (dst_oq_low_addr),
.dst_oq_wr_addr (dst_oq_wr_addr),
.dst_oq_full (dst_oq_full),
// --- Misc
.clk (clk),
.reset (reset));
//------------------ Logic ------------------------
assign in_rdy = header_parser_rdy && !input_fifo_nearly_full;
endmodule // output_queues
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_8_V
`define SKY130_FD_SC_HS__INV_8_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__inv_8 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_8_V
|
/* ****************************************************************************
-- (C) Copyright 2016 Kevin M. Hubbard - All rights reserved.
-- Source file: sump2.v
-- Date: July 2016
-- Author: khubbard
-- Description: SUMP2 is a fast and simple logic analyzer.
-- It captures N/2 samples before and after a specified
-- positive edged trigger event where N is length of BRAM.
-- It is designed to be really small and simple for places where
-- SUMP-RLE is either too big or overly complicated. It also
-- runs much faster and wider than SUMP-RLE.
-- SUMP2 is NOT software compatible with SUMP-RLE.
-- Language: Verilog-2001
-- Simulation: Mentor-Modelsim
-- Synthesis: Xilint-XST,Xilinx-Vivado,Lattice-Synplify
-- License: This project is licensed with the CERN Open Hardware Licence
-- v1.2. You may redistribute and modify this project under the
-- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
-- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED
-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL
-- v.1.2 for applicable Conditions.
--
-- Design Instance Parameters with examples:
-- depth_len = 1024 : Depth of RAM in number of cell, example 1024,4096
-- depth_bits = 10 : Number of RAM address lines, example 10,12
-- event_bytes = 4 : Number of event bytes 1,2,3 or 4
-- data_dwords = 16 : Number of DWORDs for Data 0,4,8,12 or 16
--
-- nonrle_en = 1 : If 0, removes Event RAM (for small RLE only designs)
-- rle_en = 1 : Adds logic for Event RLE captures.
-- pattern_en = 1 : Adds logic for 32bit event pattern triggers
-- trigger_nth_en = 1 : Adds logic for triggering on Nth trigger event
-- trigger_dly_en = 1 : Adds logic for triggering after a delay from trigger
--
-- freq_mhz = 16'd80 : Freq integer 0 MHz up to 65 GHz ( 16bit )
-- freq_fracts = 16'h0000 : Freq fraction bits, example C000 = 0.75 MHz
-- sump_id = 16'hABBA : Don't Change
-- sump_rev = 8'h02 : Don't Change
--
-- LocalBus 2 DWORD Register Interface
-- lb_cs_ctrl : PCI addr sel for Control
-- lb_cs_data : PCI addr sel for Data transfers. +0x4 offset from lb_cs_ctrl
--
-- clk_lb _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_
-- lb_cs_ctrl _____/ \___/ \___________________________________________
-- lb_cs_data _________________________/ \_______________________________
-- lb_wr _____/ \__/ \___________________________________________
-- lb_rd _________________________/ \______________________________
-- lb_wr_d -----< >--< >-------------------------------------------
-- lb_rd_dy _________________________________________/ \______________
-- lb_rd_d -----------------------------------------< >--------------
-- |---------------| variable distance
--
-- Software Interface
-- 6bit Control Commands:
-- 0x00 : Idle + Read Status
-- 0x01 : ARM + Read Status
-- 0x02 : Reset
--
-- 0x04 : Load Trigger Type ( AND,OR,Ext )
-- 0x05 : Load Trigger Field ( AND/OR bits )
-- 0x06 : Load Trigger Delay & nth
-- 0x07 : Load Trigger Position ( Num Post Trigger Samples to capture ).
--
-- 0x08 : Load RLE Event Enable
-- 0x09 : Load Read Pointer
-- 0x0a : Load Read Page
--
-- 0x0b : Read HW ID + Revision
-- 0x0c : Read HW Config RAM Width+Length
-- 0x0d : Read HW Config Sample Clock Frequency
-- 0x0e : Read Trigger Location
-- 0x0f : Read RAM Data ( address auto incrementing )
--
-- 0x10 : Load User Controls
-- 0x11 : Load User Pattern0
-- 0x12 : Load User Pattern1
-- 0x13 : Load Data Enable Field
--
-- 0x18 : Read Deep-RAM Width+Length
-- 0x19 : Read Deep-RAM Trigger Location + Status
-- 0x1a : Read Deep-RAM Data ( address auto incrementing )
-- 0x1b : Load Deep-RAM Read Pointer
-- 0x1c : Load Deep-RAM Read Page
-- 0x1d : Load Deep-Sump User Control
-- 0x1e : Load Deep-Sump User Mask
-- 0x1f : Load Deep-Sump User Cfg
--
-- 0x20 - 0x3F : Reserved for future use
--
-- Trigger Types:
-- AND Rising = 0x00;
-- AND Falling = 0x01;
-- OR Rising = 0x02;
-- OR Falling = 0x03;
-- Pattern Rising = 0x04;
-- Pattern Falling = 0x05;
-- Input Trigger Rising = 0x06;
-- Input Trigger Falling = 0x07;
--
-- Revision History:
-- Ver# When Who What
-- ---- -------- -------- --------------------------------------------------
-- 0.1 07.01.16 khubbard Creation. Rev01
-- 0.2 05.14.18 khubbard Rev02 DeepSump support added. Ctrl from 5 to 6bits
-- ***************************************************************************/
`default_nettype none // Strictly enforce all nets to be declared
module sump2 #
(
parameter depth_len = 1024,
parameter depth_bits = 10,
parameter event_bytes = 4,
parameter data_dwords = 16,
parameter nonrle_en = 1,
parameter rle_en = 1,
parameter data_en = 1,
parameter pattern_en = 1,
parameter trigger_nth_en = 1,
parameter trigger_dly_en = 1,
parameter trigger_wd_en = 1,
parameter deep_sump_en = 0,
parameter freq_mhz = 16'd80,
parameter freq_fracts = 16'h0000,
parameter sump_id = 16'hABBA,
parameter sump_rev = 8'h02
)
(
input wire reset,
input wire clk_cap,
input wire clk_lb,
input wire lb_cs_ctrl,
input wire lb_cs_data,
input wire lb_wr,
input wire lb_rd,
input wire [31:0] lb_wr_d,
output reg [31:0] lb_rd_d,
output reg lb_rd_rdy,
output reg active,
output wire [31:0] user_ctrl,
output wire [31:0] user_pat0,
output wire [31:0] user_pat1,
input wire trigger_in,
output reg trigger_out,
output reg ds_trigger,
output reg [31:0] ds_events,
output wire [31:0] ds_user_ctrl,
output reg [5:0] ds_cmd_lb,
output reg [5:0] ds_cmd_cap,
output reg ds_rd_req,
output reg ds_wr_req,
output reg [31:0] ds_wr_d,
input wire [31:0] ds_rd_d,
input wire ds_rd_rdy,
input wire ds_rle_pre_done,
input wire ds_rle_post_done,
input wire [31:0] events_din,
input wire [127:0] dwords_3_0,
input wire [127:0] dwords_7_4,
input wire [127:0] dwords_11_8,
input wire [127:0] dwords_15_12
);
wire reset_loc;
wire [15:0] zeros;
wire [15:0] ones;
wire [7:0] cap_status;
wire [5:0] ctrl_cmd;
reg [5:0] ctrl_cmd_loc;
reg ctrl_cmd_xfer;
wire [4:0] ctrl_rd_page;
wire [15:0] ctrl_rd_ptr;
reg [5:0] ctrl_reg;
reg [31:0] events_loc;
reg trigger_loc;
reg trigger_or;
reg trigger_or_p1;
reg trigger_and;
reg trigger_and_p1;
reg trigger_pat;
reg trigger_pat_p1;
reg xfer_clr;
reg rd_inc;
reg armed_jk;
reg triggered_jk;
reg acquired_jk;
reg complete_jk;
reg [31:0] ctrl_04_reg;
reg [31:0] ctrl_05_reg;
reg [31:0] ctrl_06_reg;
reg [31:0] ctrl_07_reg;
reg [31:0] ctrl_08_reg;
reg [31:0] ctrl_09_reg;
reg [31:0] ctrl_0a_reg;
reg [31:0] ctrl_0b_reg;
reg [31:0] ctrl_10_reg;
reg [31:0] ctrl_11_reg;
reg [31:0] ctrl_12_reg;
reg [31:0] ctrl_13_reg;
reg [31:0] ctrl_14_reg;
reg [31:0] ctrl_1d_reg;
wire [31:0] watchdog_reg;
reg [31:0] watchdog_cnt;
reg wd_armed_jk;
reg trigger_wd;
wire [31:0] trigger_bits;
wire [3:0] trigger_type;
wire [31:0] trigger_pos;
wire [15:0] trigger_nth;
wire [15:0] trigger_delay;
reg [15:0] trigger_dly_cnt;
wire [31:0] rle_event_en;
reg [15:0] trigger_cnt;
reg [31:0] ram_rd_d;
reg [depth_bits-1:0] post_trig_cnt;
reg [depth_bits-1:0] trigger_ptr;
reg trigger_in_meta;
reg trigger_in_p1;
reg trigger_in_p2;
wire [31:0] pat0;
wire [31:0] pat1;
// Variable Size Capture BRAM
reg [31:0] event_ram_array[depth_len-1:0];
reg [127:0] dwords_3_0_ram_array[depth_len-1:0];
reg [127:0] dwords_7_4_ram_array[depth_len-1:0];
reg [127:0] dwords_11_8_ram_array[depth_len-1:0];
reg [127:0] dwords_15_12_ram_array[depth_len-1:0];
reg [127:0] dwords_3_0_p1;
reg [127:0] dwords_7_4_p1;
reg [127:0] dwords_11_8_p1;
reg [127:0] dwords_15_12_p1;
reg [127:0] dwords_3_0_p2;
reg [127:0] dwords_7_4_p2;
reg [127:0] dwords_11_8_p2;
reg [127:0] dwords_15_12_p2;
reg [127:0] dwords_3_0_do;
reg [127:0] dwords_7_4_do;
reg [127:0] dwords_11_8_do;
reg [127:0] dwords_15_12_do;
reg [depth_bits-1:0] c_addr;
reg [depth_bits-1:0] c_addr_p1;
reg c_we;
reg c_we_p1;
wire [31:0] c_di;
reg [31:0] c_di_p1;
reg [depth_bits-1:0] d_addr;
reg [31:0] d_do;
reg [63:0] rle_ram_array[depth_len-1:0];
reg [depth_bits-1:0] a_addr;
reg [depth_bits-1:0] a_addr_p1;
reg a_we;
reg a_we_p1;
reg [63:0] a_di;
reg [63:0] a_di_p1;
reg [depth_bits-1:0] b_addr;
reg [63:0] b_do;
wire [31:0] data_en_bits;
reg data_en_loc;
reg data_en_loc_p1;
reg [31:0] events_pre;
reg [31:0] events_p1;
reg [31:0] events_p2;
reg [31:0] rle_time;
reg [31:0] rle_time_p1;
reg rle_wd_sample;
reg rle_pre_jk;
reg rle_done_jk;
reg rle_done_loc;
reg rle_pre_done_loc;
wire [7:0] data_4x_dwords;
assign zeros = 16'd0;
assign ones = 16'hFFFF;
assign reset_loc = reset;
//assign cap_status = { rle_en, 1'b0, rle_done_loc, ~rle_pre_jk,
assign cap_status = { rle_en, 1'b0, rle_done_loc, rle_pre_done_loc,
complete_jk, acquired_jk, triggered_jk, armed_jk };
//-----------------------------------------------------------------------------
// Flop the input events and support reduction for much smaller designs.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_done
rle_done_loc <= rle_done_jk && ( deep_sump_en==0 || ds_rle_post_done==1);
rle_pre_done_loc <= ~rle_pre_jk && ( deep_sump_en==0 || ds_rle_pre_done==1);
end // proc_din
//-----------------------------------------------------------------------------
// Flop the input events and support reduction for much smaller designs.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_din
if ( event_bytes == 1 ) begin
events_loc <= { 24'd0, events_din[7:0] };
end else if ( event_bytes == 2 ) begin
events_loc <= { 16'd0, events_din[15:0] };
end else if ( event_bytes == 3 ) begin
events_loc <= { 8'd0, events_din[23:0] };
end else begin
events_loc <= { events_din[31:0] };
end
if ( rle_en == 1 ) begin
events_pre <= events_loc[31:0] & rle_event_en[31:0];
events_p1 <= events_pre[31:0];
events_p2 <= events_p1[31:0];
end
end // proc_din
//-----------------------------------------------------------------------------
// Capture Logic. When armed, capture in a continuous loop until trigger is
// detected and then capture N/2 samples more.
// Note: Software Must go from Idle to Arm to clear the JKs.
//-----------------------------------------------------------------------------
always @ ( * ) begin : proc_data_en
if ( data_en_bits == 32'h00000000 || data_en == 0 ||
( data_en_bits[31:0] & events_din[31:0] ) != 32'h00000000 ) begin
data_en_loc <= 1;// Capture sample in time
end else begin
data_en_loc <= 0;// Prevent sample capture
end
end // proc_data_en
//-----------------------------------------------------------------------------
// Capture Logic. When armed, capture in a continuous loop until trigger is
// detected and then capture N/2 samples more.
// Note: Software Must go from Idle to Arm to clear the JKs.
//-----------------------------------------------------------------------------
integer i;
always @ ( posedge clk_cap ) begin : proc_trig
trigger_in_meta <= trigger_in;
trigger_in_p1 <= trigger_in_meta;
trigger_in_p2 <= trigger_in_p1;
trigger_or <= 0;
trigger_and <= 0;
trigger_pat <= 0;
trigger_or_p1 <= trigger_or;
trigger_and_p1 <= trigger_and;
trigger_pat_p1 <= trigger_pat;
data_en_loc_p1 <= data_en_loc;
for ( i = 0; i <= 31; i=i+1 ) begin
if ( trigger_bits[i] == 1 && events_loc[i] == 1 ) begin
trigger_or <= 1;// This is a 32bit OR
end
end
if ( ( events_loc[31:0] & trigger_bits[31:0] ) == trigger_bits[31:0] ) begin
trigger_and <= 1;
end
if (
(( events_loc[31:0] & pat0[31:0] ) ^
( pat1[31:0] & pat0[31:0] ) ) == 32'h00000000 ) begin
if ( pattern_en == 1 ) begin
trigger_pat <= 1;// Exact 32bit Pattern Match
end
end
end // proc_trig
//-----------------------------------------------------------------------------
// Capture Logic. When armed, capture in a continuous loop until trigger is
// detected and then capture N/2 samples more.
// Note: Software Must go from Idle to Arm to clear the JKs.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_cap
c_we <= 0;
trigger_out <= 0;
trigger_loc <= 0;
trigger_wd <= 0;
active <= 0;
ds_trigger <= 0;
ds_events <= events_p1[31:0];
// CMD_ARM
if ( ctrl_cmd_loc == 6'h01 ) begin
active <= 1;
// Watchdog gets armed on 1st kick. Every kick after clears count.
// If count expires, assert trigger_wd.
if ( trigger_wd_en == 1 && ( trigger_or != trigger_or_p1 ) ) begin
wd_armed_jk <= 1;
end
if ( wd_armed_jk == 0 || ( trigger_or != trigger_or_p1 ) ) begin
watchdog_cnt <= 32'd0;
trigger_wd <= 0;
end else begin
watchdog_cnt <= watchdog_cnt[31:0] + 1;
if ( watchdog_cnt == watchdog_reg[31:0] ) begin
trigger_wd <= 1;
wd_armed_jk <= 0;
end
end
if ( triggered_jk == 0 && acquired_jk == 0 ) begin
// PreTrigger Acquire
armed_jk <= 1;
if ( data_en_loc == 1 || data_en_loc_p1 == 1 ) begin
c_we <= 1;
c_addr <= c_addr + 1;
end
if ( trigger_dly_cnt != 16'hFFFF ) begin
trigger_dly_cnt <= trigger_dly_cnt + 1;
end
if ( ( trigger_type==4'h0 && trigger_and==1 && trigger_and_p1==0 ) ||
( trigger_type==4'h1 && trigger_and==0 && trigger_and_p1==1 ) ||
( trigger_type==4'h2 && trigger_or ==1 && trigger_or_p1 ==0 ) ||
( trigger_type==4'h3 && trigger_or ==0 && trigger_or_p1 ==1 ) ||
( trigger_type==4'h4 && trigger_pat==1 && trigger_pat_p1==0 ) ||
( trigger_type==4'h5 && trigger_pat==0 && trigger_pat_p1==1 ) ||
( trigger_type==4'h6 && trigger_in_p1 ==1 && trigger_in_p2 ==0 ) ||
( trigger_type==4'h7 && trigger_in_p1 ==0 && trigger_in_p2 ==1 ) ||
( trigger_type==4'h8 && trigger_wd == 1 )
) begin
if ( trigger_dly_cnt == 16'hFFFF || trigger_dly_en==0 ) begin
trigger_dly_cnt <= 16'd0;
trigger_loc <= 1;// Only used if trigger delay is removed
c_we <= 1;// Store Trigger even if data_en_loc == 0
c_addr <= c_addr + 1;
end
end
// Don't allow trigger until pre-trig buffer is full
// If there is a deep_sump block, wait for it as well.
// if ( complete_jk == 1 ) begin
if ( complete_jk == 1 && ( deep_sump_en==0 || ds_rle_pre_done==1) ) begin
if ( ( trigger_dly_cnt == trigger_delay[15:0] ) ||
( trigger_dly_en==0 && trigger_loc == 1 ) ) begin
trigger_dly_cnt <= 16'hFFFF;
if ( trigger_cnt == trigger_nth[15:0] || trigger_nth_en==0 ) begin
armed_jk <= 0;
trigger_ptr <= c_addr[depth_bits-1:0];
trigger_out <= 1;
triggered_jk <= 1;
ds_trigger <= 1;
end
trigger_cnt <= trigger_cnt + 1;
end
end
end else if ( triggered_jk == 1 && acquired_jk == 0 ) begin
// PostTrigger Acquire
trigger_out <= 1;
if ( data_en_loc == 1 || data_en_loc_p1 == 1 ) begin
c_we <= 1;
c_addr <= c_addr + 1;
post_trig_cnt <= post_trig_cnt + 1;
end
if ( post_trig_cnt == trigger_pos[depth_bits-1:0] ) begin
acquired_jk <= 1;
c_we <= 0;
end
end
// If RAM has rolled, then pre-trigger buffer is full. Assert status bit.
// If RAM hasn't rolled, then pre-trigger samples start at 0x0.
if ( c_addr[depth_bits-1] == 0 && c_addr_p1[depth_bits-1] == 1 ) begin
complete_jk <= 1;
end
// CMD_RESET
end else if ( ctrl_cmd_loc == 6'h02 ) begin
c_addr <= zeros[depth_bits-1:0];
post_trig_cnt <= zeros[depth_bits-1:0];
post_trig_cnt[1:0] <= 2'b11;// Subtracts 3 from trigger_pos for alignment
trigger_cnt <= 16'd1;
trigger_dly_cnt <= 16'hFFFF;
armed_jk <= 0;
triggered_jk <= 0;
acquired_jk <= 0;
complete_jk <= 0;
wd_armed_jk <= 0;
end
// Cleanly xfer clock domains
xfer_clr <= 0;
if ( ctrl_cmd_xfer == 1 ) begin
ctrl_cmd_loc <= ctrl_cmd[5:0];
xfer_clr <= 1;
end
ds_cmd_cap <= ctrl_cmd_loc[5:0];
end // proc_cap
assign c_di = events_loc[31:0];
//-----------------------------------------------------------------------------
// RLE Capture Logic. This captures and stores event changes along with
// time stamps to a x64 BRAM. 1st half of RAM is any pre-trigger activity.
// 2nd half of RAM is post-trigger activity. Pre-trig is circular and must
// be unrolled by software in correct order. Enabling RLE block is optional.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_rle
a_we <= 0;
rle_time_p1 <= rle_time[31:0];
// Prevent RLE from hanging in cases where no activity happens after the
// trigger event by storing a non-changing sample periodically every
// 2^24 clock cycles ( about 100ms at 100 MHz )
rle_wd_sample <= rle_time[15] & ~ rle_time_p1[15];
// CMD_ARM
if ( ctrl_cmd_loc == 6'h01 ) begin
rle_time <= rle_time[31:0] + 1;
if ( triggered_jk == 0 ) begin
a_addr[depth_bits-1] <= 0;// Pre-Trigger Half
// If the prebuffer is invalid, store everything, change or no change
// as to immediately fill up RAM with valid samples
// Once prebuffer is valid, only store event deltas ( RLE )
if ( rle_pre_jk == 1 || rle_wd_sample == 1 ||
( events_p1 != events_p2[31:0] ) ) begin
a_we <= 1;
a_addr[depth_bits-2:0] <= a_addr[depth_bits-2:0] + 1;
if ( a_addr[depth_bits-2:0] == ones[depth_bits-2:0] ) begin
rle_pre_jk <= 0;// PreBuffer is completely valid - and rolling
end
end
end else if ( triggered_jk == 1 && rle_done_jk == 0 ) begin
if ( ( events_p1 != events_p2[31:0] ) || ( rle_wd_sample == 1) ) begin
a_we <= 1;
a_addr[depth_bits-2:0] <= a_addr[depth_bits-2:0] + 1;
// If previous write was to last address in RAM, then call it quits
if ( a_addr[depth_bits-2:0] == ones[depth_bits-2:0] ) begin
rle_done_jk <= 1;// Post-Trig RAM is full
a_we <= 0;
a_addr[depth_bits-2:0] <= a_addr[depth_bits-2:0];
end
// If previous cycle was pre-trig, set address to start of post trig
if ( a_addr[depth_bits-1] == 0 ) begin
a_addr[depth_bits-1] <= 1;// Post-Trigger Half
a_addr[depth_bits-2:0] <= zeros[depth_bits-2:0];
end
end
end
// CMD_RESET
end else if ( ctrl_cmd_loc == 6'h02 ) begin
rle_time <= 32'd0;// 43 seconds at 100 MHz
a_addr <= zeros[depth_bits-1:0];
rle_pre_jk <= 1;
rle_done_jk <= 0;
end
a_di[31:0] <= events_p1[31:0];
a_di[63:32] <= rle_time[31:0];
end // proc_rle
//-----------------------------------------------------------------------------
// Create write/read bus interface to the sump2_deep block
// 0x18 : Read Deep-RAM Width+Length
// 0x19 : Read Deep-RAM Trigger Location + Status
// 0x1a : Read Deep-RAM Data ( address auto incrementing )
// 0x1b : Load Deep-RAM Read Pointer
// 0x1c : Load Deep-RAM Read Page
// 0x1d : Load Deep-Sump User Control
// 0x1e : Load Deep-Sump User Mask
// 0x1f : Load Deep-Sump User Config
// Note: ds_user_ctrl is decoded locally here as it may be used to switch
// between multiple deep_sump.v instances, for example one may use fast
// on chip BRAM and another might use slower external DRAM. A user may
// decide to mux between the two with a ds_user_ctrl bit.
//-----------------------------------------------------------------------------
always @ ( posedge clk_lb ) begin : proc_lb_ds
ds_wr_req <= 0;
ds_rd_req <= 0;
if ( lb_wr == 1 && lb_cs_data == 1 ) begin
if ( ctrl_cmd[5:0] == 6'h1b ||
ctrl_cmd[5:0] == 6'h1c ||
ctrl_cmd[5:0] == 6'h1e ||
ctrl_cmd[5:0] == 6'h1f ) begin
ds_wr_req <= 1;
ds_wr_d <= lb_wr_d[31:0];
end
end
if ( lb_rd == 1 && lb_cs_data == 1 ) begin
if ( ctrl_cmd[5:0] == 6'h18 ||
ctrl_cmd[5:0] == 6'h19 ||
ctrl_cmd[5:0] == 6'h1a ) begin
ds_rd_req <= 1;
end
end
end
//-----------------------------------------------------------------------------
// LocalBus Write Ctrl register
//-----------------------------------------------------------------------------
always @ ( posedge clk_lb ) begin : proc_lb_wr
ds_cmd_lb <= ctrl_reg[5:0];
if ( lb_wr == 1 && lb_cs_ctrl == 1 ) begin
ctrl_reg[5:0] <= lb_wr_d[5:0];
ctrl_cmd_xfer <= 1;
end
if ( lb_wr == 1 && lb_cs_data == 1 ) begin
case( ctrl_cmd[5:0] )
6'h04 : ctrl_04_reg <= lb_wr_d[31:0];
6'h05 : ctrl_05_reg <= lb_wr_d[31:0];
6'h06 : ctrl_06_reg <= lb_wr_d[31:0];
6'h07 : ctrl_07_reg <= lb_wr_d[31:0];
6'h08 : ctrl_08_reg <= lb_wr_d[31:0];
6'h09 : ctrl_09_reg <= lb_wr_d[31:0];
6'h0A : ctrl_0a_reg <= lb_wr_d[31:0];
6'h0B : ctrl_0b_reg <= lb_wr_d[31:0];
6'h10 : ctrl_10_reg <= lb_wr_d[31:0];
6'h11 : ctrl_11_reg <= lb_wr_d[31:0];
6'h12 : ctrl_12_reg <= lb_wr_d[31:0];
6'h13 : ctrl_13_reg <= lb_wr_d[31:0];
6'h14 : ctrl_14_reg <= lb_wr_d[31:0];
6'h1d : ctrl_1d_reg <= lb_wr_d[31:0];
endcase
end
if ( xfer_clr == 1 ) begin
ctrl_cmd_xfer <= 0;
end
if ( ctrl_cmd == 6'h01 ) begin
d_addr <= c_addr[depth_bits-1:0];// When Acq stops, d_addr will be last
end
if ( lb_wr == 1 && lb_cs_data == 1 && ctrl_cmd == 6'h09 ) begin
d_addr <= lb_wr_d[depth_bits-1:0];// Load user specified address
end
if ( rd_inc == 1 ) begin
d_addr <= d_addr[depth_bits-1:0] + 1;// Auto Increment on each read
end
if ( reset_loc == 1 ) begin
ctrl_reg[5:0] <= 6'd0;
ctrl_cmd_xfer <= 1;// Flag to xfer ctrl_reg into other clock domain
end
end
assign ctrl_cmd[5:0] = ctrl_reg[5:0];
assign trigger_type = ctrl_04_reg[3:0];
assign trigger_bits = ctrl_05_reg[31:0];
assign trigger_nth = ctrl_06_reg[15:0];
assign trigger_delay = ctrl_06_reg[31:16];
assign trigger_pos = ctrl_07_reg[31:0];
assign rle_event_en = ctrl_08_reg[31:0];
assign user_ctrl[31:0] = ctrl_10_reg[31:0];
assign user_pat0[31:0] = ctrl_11_reg[31:0];
assign user_pat1[31:0] = ctrl_12_reg[31:0];
assign pat0[31:0] = ctrl_11_reg[31:0];
assign pat1[31:0] = ctrl_12_reg[31:0];
assign data_en_bits[31:0] = ctrl_13_reg[31:0];
assign watchdog_reg[31:0] = ctrl_14_reg[31:0];
assign ds_user_ctrl[31:0] = ctrl_1d_reg[31:0];
assign ctrl_rd_ptr[15:0] = ctrl_09_reg[15:0];
assign ctrl_rd_page[4:0] = ctrl_0a_reg[4:0];
assign data_4x_dwords = data_dwords;
//-----------------------------------------------------------------------------
// LocalBus readback of ctrl_reg and data_reg
//-----------------------------------------------------------------------------
always @ ( posedge clk_lb ) begin : proc_lb_rd
lb_rd_d <= 32'd0;
lb_rd_rdy <= 0;
rd_inc <= 0;
if ( lb_rd == 1 && lb_cs_ctrl == 1 ) begin
lb_rd_d[5:0] <= ctrl_reg[5:0];
lb_rd_rdy <= 1;
end
if ( ds_rd_rdy == 1 && deep_sump_en == 1 ) begin
lb_rd_d <= ds_rd_d[31:0];
lb_rd_rdy <= 1;
end
if ( lb_rd == 1 && lb_cs_data == 1 ) begin
if ( ctrl_cmd == 6'h00 ||
ctrl_cmd == 6'h01
) begin
lb_rd_d[7:0] <= cap_status[7:0];
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0b ) begin
lb_rd_d[31:16] <= sump_id;// Identification
lb_rd_d[15:8] <= sump_rev;// Revision
lb_rd_d[7] <= deep_sump_en;
lb_rd_d[6] <= data_en;
lb_rd_d[5] <= trigger_wd_en;
lb_rd_d[4] <= ~ nonrle_en;// Invert to disable backwards SW comptbl
lb_rd_d[3] <= rle_en;
lb_rd_d[2] <= pattern_en;
lb_rd_d[1] <= trigger_nth_en;
lb_rd_d[0] <= trigger_dly_en;
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0c ) begin
lb_rd_d[31:28] <= rle_en ;// 1 if RLE RAM exists
lb_rd_d[27:24] <= event_bytes;// How Many Event Bytes 1-4
lb_rd_d[23:16] <= data_4x_dwords[5:2];// How Many 32bit BRAMs data 4x
lb_rd_d[15:0] <= depth_len; // How deep RAMs are
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0d ) begin
lb_rd_d[15:0] <= freq_fracts;// Fractional MHz bits 1/2,1/4,etc.
lb_rd_d[31:16] <= freq_mhz ;// Integer MHz
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0e ) begin
lb_rd_d[depth_bits-1:0] <= trigger_ptr[depth_bits-1:0];// Where Trig Is
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0f ) begin
lb_rd_d <= ram_rd_d[31:0];
rd_inc <= 1;// Auto Increment RAM Address
lb_rd_rdy <= 1;
end
end
// Mux between the BRAMs
case( ctrl_rd_page[4:0] )
5'H02 : ram_rd_d <= b_do[31:0]; // RLE Data
5'H03 : ram_rd_d <= b_do[63:32]; // RLE Time
5'H10 : ram_rd_d <= dwords_3_0_do[31:0];
5'H11 : ram_rd_d <= dwords_3_0_do[63:32];
5'H12 : ram_rd_d <= dwords_3_0_do[95:64];
5'H13 : ram_rd_d <= dwords_3_0_do[127:96];
5'H14 : ram_rd_d <= dwords_7_4_do[31:0];
5'H15 : ram_rd_d <= dwords_7_4_do[63:32];
5'H16 : ram_rd_d <= dwords_7_4_do[95:64];
5'H17 : ram_rd_d <= dwords_7_4_do[127:96];
5'H18 : ram_rd_d <= dwords_11_8_do[31:0];
5'H19 : ram_rd_d <= dwords_11_8_do[63:32];
5'H1a : ram_rd_d <= dwords_11_8_do[95:64];
5'H1b : ram_rd_d <= dwords_11_8_do[127:96];
5'H1c : ram_rd_d <= dwords_15_12_do[31:0];
5'H1d : ram_rd_d <= dwords_15_12_do[63:32];
5'H1e : ram_rd_d <= dwords_15_12_do[95:64];
5'H1f : ram_rd_d <= dwords_15_12_do[127:96];
default : ram_rd_d <= d_do[31:0]; // Events
endcase
end // proc_lb_rd
//-----------------------------------------------------------------------------
// Data Dual Port RAM - Infer RAM here to make easy to change depth on the fly
//-----------------------------------------------------------------------------
always @( posedge clk_cap )
begin
c_we_p1 <= c_we;
c_addr_p1 <= c_addr;
c_di_p1 <= c_di;
if ( c_we_p1 ) begin
if ( nonrle_en == 1 ) begin
event_ram_array[c_addr_p1] <= c_di_p1;
end
end // if ( c_we )
dwords_3_0_p1 <= dwords_3_0[127:0];
dwords_7_4_p1 <= dwords_7_4[127:0];
dwords_11_8_p1 <= dwords_11_8[127:0];
dwords_15_12_p1 <= dwords_15_12[127:0];
dwords_3_0_p2 <= dwords_3_0_p1[127:0];
dwords_7_4_p2 <= dwords_7_4_p1[127:0];
dwords_11_8_p2 <= dwords_11_8_p1[127:0];
dwords_15_12_p2 <= dwords_15_12_p1[127:0];
if ( c_we_p1 ) begin
if ( data_dwords >= 4 ) begin
dwords_3_0_ram_array[ c_addr_p1 ] <= dwords_3_0_p2[127:0];
end
if ( data_dwords >= 8 ) begin
dwords_7_4_ram_array[ c_addr_p1 ] <= dwords_7_4_p2[127:0];
end
if ( data_dwords >= 12 ) begin
dwords_11_8_ram_array[ c_addr_p1 ] <= dwords_11_8_p2[127:0];
end
if ( data_dwords >= 16 ) begin
dwords_15_12_ram_array[ c_addr_p1 ] <= dwords_15_12_p2[127:0];
end
end // if ( c_we )
end // always
//-----------------------------------------------------------------------------
// 2nd Port of RAM is clocked from local bus
//-----------------------------------------------------------------------------
always @( posedge clk_lb )
begin
if ( nonrle_en == 1 ) begin
d_do <= event_ram_array[d_addr] ;
end
if ( data_dwords >= 4 ) begin
dwords_3_0_do <= dwords_3_0_ram_array[ d_addr ];
end
if ( data_dwords >= 8 ) begin
dwords_7_4_do <= dwords_7_4_ram_array[ d_addr ];
end
if ( data_dwords >= 12 ) begin
dwords_11_8_do <= dwords_11_8_ram_array[ d_addr ];
end
if ( data_dwords >= 16 ) begin
dwords_15_12_do <= dwords_15_12_ram_array[ d_addr ];
end
end // always
//-----------------------------------------------------------------------------
// RLE Dual Port RAM - Infer RAM here to make easy to change depth on the fly
//-----------------------------------------------------------------------------
always @( posedge clk_cap )
begin
if ( rle_en == 1 ) begin
a_we_p1 <= a_we;
a_addr_p1 <= a_addr;
a_we_p1 <= a_we;
a_addr_p1 <= a_addr;
a_di_p1 <= a_di;
if ( a_we_p1 ) begin
rle_ram_array[a_addr_p1] <= a_di_p1;
end // if ( a_we )
end
end // always
//-----------------------------------------------------------------------------
// 2nd Port of RAM is clocked from local bus
//-----------------------------------------------------------------------------
always @( posedge clk_lb )
begin
if ( rle_en == 1 ) begin
b_do <= rle_ram_array[d_addr];
end
end // always
endmodule // sump2
|
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_top.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2006/01/19 14:07:52 maverickist
// verification is complete.
//
// Revision 1.2 2005/12/16 06:44:13 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
module MAC_top(
//system signals
input Reset ,
input Clk_125M ,
input Clk_user ,
input Clk_reg ,
output [2:0] Speed ,
//user interface
output Rx_mac_ra ,
input Rx_mac_rd ,
output [31:0] Rx_mac_data ,
output [1:0] Rx_mac_BE ,
output Rx_mac_pa ,
output Rx_mac_sop ,
output Rx_mac_eop ,
//user interface
output Tx_mac_wa ,
input Tx_mac_wr ,
input [31:0] Tx_mac_data ,
input [1:0] Tx_mac_BE ,//big endian
input Tx_mac_sop ,
input Tx_mac_eop ,
//pkg_lgth fifo
input Pkg_lgth_fifo_rd ,
output Pkg_lgth_fifo_ra ,
output [15:0] Pkg_lgth_fifo_data ,
//Phy interface
//Phy interface
output Gtx_clk ,//used only in GMII mode
input Rx_clk ,
input Tx_clk ,//used only in MII mode
output Tx_er ,
output Tx_en ,
output [7:0] Txd ,
input Rx_er ,
input Rx_dv ,
input [7:0] Rxd ,
input Crs ,
input Col ,
//host interface
input CSB ,
input WRB ,
input [15:0] CD_in ,
output [15:0] CD_out ,
input [7:0] CA ,
//mdx
output Mdo, // MII Management Data Output
output MdoEn, // MII Management Data Output Enable
input Mdi,
output Mdc // MII Management Data Clock
);
//******************************************************************************
//internal signals
//******************************************************************************
//RMON interface
wire [15:0] Rx_pkt_length_rmon ;
wire Rx_apply_rmon ;
wire [2:0] Rx_pkt_err_type_rmon ;
wire [2:0] Rx_pkt_type_rmon ;
wire [2:0] Tx_pkt_type_rmon ;
wire [15:0] Tx_pkt_length_rmon ;
wire Tx_apply_rmon ;
wire [2:0] Tx_pkt_err_type_rmon ;
//PHY interface
wire MCrs_dv ;
wire [7:0] MRxD ;
wire MRxErr ;
//flow_control signals
wire [15:0] pause_quanta ;
wire pause_quanta_val ;
//PHY interface
wire [7:0] MTxD ;
wire MTxEn ;
wire MCRS ;
//interface clk signals
wire MAC_tx_clk ;
wire MAC_rx_clk ;
wire MAC_tx_clk_div ;
wire MAC_rx_clk_div ;
//reg signals
wire [4:0] Tx_Hwmark ;
wire [4:0] Tx_Lwmark ;
wire pause_frame_send_en ;
wire [15:0] pause_quanta_set ;
wire MAC_tx_add_en ;
wire FullDuplex ;
wire [3:0] MaxRetry ;
wire [5:0] IFGset ;
wire [7:0] MAC_tx_add_prom_data ;
wire [2:0] MAC_tx_add_prom_add ;
wire MAC_tx_add_prom_wr ;
wire tx_pause_en ;
wire xoff_cpu ;
wire xon_cpu ;
//Rx host interface
wire MAC_rx_add_chk_en ;
wire [7:0] MAC_rx_add_prom_data ;
wire [2:0] MAC_rx_add_prom_add ;
wire MAC_rx_add_prom_wr ;
wire broadcast_filter_en ;
wire [15:0] broadcast_MAX ;
wire RX_APPEND_CRC ;
wire [4:0] Rx_Hwmark ;
wire [4:0] Rx_Lwmark ;
wire CRC_chk_en ;
wire [5:0] RX_IFG_SET ;
wire [15:0] RX_MAX_LENGTH ;
wire [6:0] RX_MIN_LENGTH ;
//RMON host interface
wire [5:0] CPU_rd_addr ;
wire CPU_rd_apply ;
wire CPU_rd_grant ;
wire [31:0] CPU_rd_dout ;
//Phy int host interface
wire Line_loop_en ;
//MII to CPU
wire [7:0] Divider ;
wire [15:0] CtrlData ;
wire [4:0] Rgad ;
wire [4:0] Fiad ;
wire NoPre ;
wire WCtrlData ;
wire RStat ;
wire ScanStat ;
wire Busy ;
wire LinkFail ;
wire Nvalid ;
wire [15:0] Prsd ;
wire WCtrlDataStart ;
wire RStatStart ;
wire UpdateMIIRX_DATAReg ;
wire [15:0] broadcast_bucket_depth ;
wire [15:0] broadcast_bucket_interval ;
wire Pkg_lgth_fifo_empty;
reg rx_pkg_lgth_fifo_wr_tmp;
reg rx_pkg_lgth_fifo_wr_tmp_pl1;
reg rx_pkg_lgth_fifo_wr;
//******************************************************************************
//internal signals
//******************************************************************************
MAC_rx U_MAC_rx(
.Reset (Reset ),
.Clk_user (Clk_user ),
.Clk (MAC_rx_clk_div ),
//RMII interface (//PHY interface ),
.MCrs_dv (MCrs_dv ),
.MRxD (MRxD ),
.MRxErr (MRxErr ),
//flow_control signals (//flow_control signals ),
.pause_quanta (pause_quanta ),
.pause_quanta_val (pause_quanta_val ),
//user interface (//user interface ),
.Rx_mac_ra (Rx_mac_ra ),
.Rx_mac_rd (Rx_mac_rd ),
.Rx_mac_data (Rx_mac_data ),
.Rx_mac_BE (Rx_mac_BE ),
.Rx_mac_pa (Rx_mac_pa ),
.Rx_mac_sop (Rx_mac_sop ),
.Rx_mac_eop (Rx_mac_eop ),
//CPU (//CPU ),
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
.MAC_add_prom_data (MAC_rx_add_prom_data ),
.MAC_add_prom_add (MAC_rx_add_prom_add ),
.MAC_add_prom_wr (MAC_rx_add_prom_wr ),
.broadcast_filter_en (broadcast_filter_en ),
.broadcast_bucket_depth (broadcast_bucket_depth ),
.broadcast_bucket_interval (broadcast_bucket_interval ),
.RX_APPEND_CRC (RX_APPEND_CRC ),
.Rx_Hwmark (Rx_Hwmark ),
.Rx_Lwmark (Rx_Lwmark ),
.CRC_chk_en (CRC_chk_en ),
.RX_IFG_SET (RX_IFG_SET ),
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
//RMON interface (//RMON interface ),
.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),
.Rx_apply_rmon (Rx_apply_rmon ),
.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
.Rx_pkt_type_rmon (Rx_pkt_type_rmon )
);
MAC_tx U_MAC_tx(
.Reset (Reset ),
.Clk (MAC_tx_clk_div ),
.Clk_user (Clk_user ),
//PHY interface (//PHY interface ),
.TxD (MTxD ),
.TxEn (MTxEn ),
.CRS (MCRS ),
//RMON (//RMON ),
.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),
.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),
.Tx_apply_rmon (Tx_apply_rmon ),
.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
//user interface (//user interface ),
.Tx_mac_wa (Tx_mac_wa ),
.Tx_mac_wr (Tx_mac_wr ),
.Tx_mac_data (Tx_mac_data ),
.Tx_mac_BE (Tx_mac_BE ),
.Tx_mac_sop (Tx_mac_sop ),
.Tx_mac_eop (Tx_mac_eop ),
//host interface (//host interface ),
.Tx_Hwmark (Tx_Hwmark ),
.Tx_Lwmark (Tx_Lwmark ),
.pause_frame_send_en (pause_frame_send_en ),
.pause_quanta_set (pause_quanta_set ),
.MAC_tx_add_en (MAC_tx_add_en ),
.FullDuplex (FullDuplex ),
.MaxRetry (MaxRetry ),
.IFGset (IFGset ),
.MAC_add_prom_data (MAC_tx_add_prom_data ),
.MAC_add_prom_add (MAC_tx_add_prom_add ),
.MAC_add_prom_wr (MAC_tx_add_prom_wr ),
.tx_pause_en (tx_pause_en ),
.xoff_cpu (xoff_cpu ),
.xon_cpu (xon_cpu ),
//MAC_rx_flow (//MAC_rx_flow ),
.pause_quanta (pause_quanta ),
.pause_quanta_val (pause_quanta_val )
);
assign Pkg_lgth_fifo_ra=!Pkg_lgth_fifo_empty;
always @ (posedge Reset or posedge MAC_rx_clk_div)
if (Reset)
rx_pkg_lgth_fifo_wr_tmp <=0;
else if(Rx_apply_rmon&&Rx_pkt_err_type_rmon==3'b100)
rx_pkg_lgth_fifo_wr_tmp <=1;
else
rx_pkg_lgth_fifo_wr_tmp <=0;
always @ (posedge Reset or posedge MAC_rx_clk_div)
if (Reset)
rx_pkg_lgth_fifo_wr_tmp_pl1 <=0;
else
rx_pkg_lgth_fifo_wr_tmp_pl1 <=rx_pkg_lgth_fifo_wr_tmp;
always @ (posedge Reset or posedge MAC_rx_clk_div)
if (Reset)
rx_pkg_lgth_fifo_wr <=0;
else if(rx_pkg_lgth_fifo_wr_tmp&!rx_pkg_lgth_fifo_wr_tmp_pl1)
rx_pkg_lgth_fifo_wr <=1;
else
rx_pkg_lgth_fifo_wr <=0;
afifo U_rx_pkg_lgth_fifo (
.din (RX_APPEND_CRC?Rx_pkt_length_rmon:Rx_pkt_length_rmon-4),
.wr_en (rx_pkg_lgth_fifo_wr ),
.wr_clk (MAC_rx_clk_div ),
.rd_en (Pkg_lgth_fifo_rd ),
.rd_clk (Clk_user ),
.ainit (Reset ),
.dout (Pkg_lgth_fifo_data ),
.full ( ),
.almost_full ( ),
.empty (Pkg_lgth_fifo_empty ),
.wr_count ( ),
.rd_count ( ),
.rd_ack ( ),
.wr_ack ( ));
RMON U_RMON(
.Clk (Clk_reg ),
.Reset (Reset ),
//Tx_RMON (//Tx_RMON ),
.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),
.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),
.Tx_apply_rmon (Tx_apply_rmon ),
.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
//Tx_RMON (//Tx_RMON ),
.Rx_pkt_type_rmon (Rx_pkt_type_rmon ),
.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),
.Rx_apply_rmon (Rx_apply_rmon ),
.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
//CPU (//CPU ),
.CPU_rd_addr (CPU_rd_addr ),
.CPU_rd_apply (CPU_rd_apply ),
.CPU_rd_grant (CPU_rd_grant ),
.CPU_rd_dout (CPU_rd_dout )
);
Phy_int U_Phy_int(
.Reset (Reset ),
.MAC_rx_clk (MAC_rx_clk ),
.MAC_tx_clk (MAC_tx_clk ),
//Rx interface (//Rx interface ),
.MCrs_dv (MCrs_dv ),
.MRxD (MRxD ),
.MRxErr (MRxErr ),
//Tx interface (//Tx interface ),
.MTxD (MTxD ),
.MTxEn (MTxEn ),
.MCRS (MCRS ),
//Phy interface (//Phy interface ),
.Tx_er (Tx_er ),
.Tx_en (Tx_en ),
.Txd (Txd ),
.Rx_er (Rx_er ),
.Rx_dv (Rx_dv ),
.Rxd (Rxd ),
.Crs (Crs ),
.Col (Col ),
//host interface (//host interface ),
.Line_loop_en (Line_loop_en ),
.Speed (Speed )
);
Clk_ctrl U_Clk_ctrl(
.Reset (Reset ),
.Clk_125M (Clk_125M ),
//host interface (//host interface ),
.Speed (Speed ),
//Phy interface (//Phy interface ),
.Gtx_clk (Gtx_clk ),
.Rx_clk (Rx_clk ),
.Tx_clk (Tx_clk ),
//interface clk (//interface clk ),
.MAC_tx_clk (MAC_tx_clk ),
.MAC_rx_clk (MAC_rx_clk ),
.MAC_tx_clk_div (MAC_tx_clk_div ),
.MAC_rx_clk_div (MAC_rx_clk_div )
);
eth_miim U_eth_miim(
.Clk (Clk_reg ),
.Reset (Reset ),
.Divider (Divider ),
.NoPre (NoPre ),
.CtrlData (CtrlData ),
.Rgad (Rgad ),
.Fiad (Fiad ),
.WCtrlData (WCtrlData ),
.RStat (RStat ),
.ScanStat (ScanStat ),
.Mdo (Mdo ),
.MdoEn (MdoEn ),
.Mdi (Mdi ),
.Mdc (Mdc ),
.Busy (Busy ),
.Prsd (Prsd ),
.LinkFail (LinkFail ),
.Nvalid (Nvalid ),
.WCtrlDataStart (WCtrlDataStart ),
.RStatStart (RStatStart ),
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ));
Reg_int U_Reg_int(
.Reset (Reset ),
.Clk_reg (Clk_reg ),
.CSB (CSB ),
.WRB (WRB ),
.CD_in (CD_in ),
.CD_out (CD_out ),
.CA (CA ),
//Tx host interface (//Tx host interface ),
.Tx_Hwmark (Tx_Hwmark ),
.Tx_Lwmark (Tx_Lwmark ),
.pause_frame_send_en (pause_frame_send_en ),
.pause_quanta_set (pause_quanta_set ),
.MAC_tx_add_en (MAC_tx_add_en ),
.FullDuplex (FullDuplex ),
.MaxRetry (MaxRetry ),
.IFGset (IFGset ),
.MAC_tx_add_prom_data (MAC_tx_add_prom_data ),
.MAC_tx_add_prom_add (MAC_tx_add_prom_add ),
.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ),
.tx_pause_en (tx_pause_en ),
.xoff_cpu (xoff_cpu ),
.xon_cpu (xon_cpu ),
//Rx host interface (//Rx host interface ),
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ),
.broadcast_filter_en (broadcast_filter_en ),
.broadcast_bucket_depth (broadcast_bucket_depth ),
.broadcast_bucket_interval (broadcast_bucket_interval ),
.RX_APPEND_CRC (RX_APPEND_CRC ),
.Rx_Hwmark (Rx_Hwmark ),
.Rx_Lwmark (Rx_Lwmark ),
.CRC_chk_en (CRC_chk_en ),
.RX_IFG_SET (RX_IFG_SET ),
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
//RMON host interface (//RMON host interface ),
.CPU_rd_addr (CPU_rd_addr ),
.CPU_rd_apply (CPU_rd_apply ),
.CPU_rd_grant (CPU_rd_grant ),
.CPU_rd_dout (CPU_rd_dout ),
//Phy int host interface (//Phy int host interface ),
.Line_loop_en (Line_loop_en ),
.Speed (Speed ),
//MII to CPU (//MII to CPU ),
.Divider (Divider ),
.CtrlData (CtrlData ),
.Rgad (Rgad ),
.Fiad (Fiad ),
.NoPre (NoPre ),
.WCtrlData (WCtrlData ),
.RStat (RStat ),
.ScanStat (ScanStat ),
.Busy (Busy ),
.LinkFail (LinkFail ),
.Nvalid (Nvalid ),
.Prsd (Prsd ),
.WCtrlDataStart (WCtrlDataStart ),
.RStatStart (RStatStart ),
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg )
);
endmodule
|
module fifo_formalbench;
wire reset = 1'b0;
wire clock;
wire enque, deque;
wire [3:0] enque_data, deque_data, data0, data1, data2, data3;
wire is_full, is_empty;
fifo f0
( .reset
, .clock
, .enque
, .deque
, .enque_data
, .deque_data
, .enqued
, .dequed
, .is_full
, .is_empty
);
// psl default clock = (posedge clock);
// psl assmue always stable(data0);
// psl assmue always stable(data1);
// psl assmue always stable(data2);
// psl assmue always stable(data3);
// psl what_goes_in_may_come_out : assert always
// {! is_full && enque && enque_data == data0; enqued} |=>
// {(! is_empty)[*]; deque; (! dequed)[*]; dequed && deque_data == data0};
// psl what_goes_in_can_be_forced_out : assert always ((always deque) -> (
// {! is_full && enque && enque_data == data0; enqued} |=>
// {[*]; dequed && deque_data == data0} !));
// psl single_in_single_out : assert always
// {is_empty && enque && enque_data == data0; enqued; (! deque)[*]; deque; dequed} |->
// (deque_data == data0);
// psl empty_to_full_to_empty : cover
// { is_empty && enque && enque_data == data0
// ; (! enqued)[*]
// ; enqued && enque && enque_data == data1
// ; (! enqued)[*]
// ; enqued && enque && enque_data == data2
// ; (! enqued)[*]
// ; enqued && enque && enque_data == data3
// ; (! enqued)[*]
// ; enqued && is_full
// ; deque
// ; (! dequed)[*]
// ; dequed && deque_data == data0 && deque
// ; (! dequed)[*]
// ; dequed && deque_data == data1 && deque
// ; (! dequed)[*]
// ; dequed && deque_data == data2 && deque
// ; (! dequed)[*]
// ; dequed && deque_data == data3 && is_empty
// };
// psl immediate_enque : assert always {! is_full && enque} |=> enqued;
// psl immediate_deque : assert always {! is_empty && deque} |=> dequed;
// psl concurrent_enque_deque : assert always {! is_empty && enque && deque} |=> (enqued && dequed);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_SYMBOL_V
`define SKY130_FD_SC_LP__O32A_SYMBOL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o32a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:39:37 03/24/2011
// Design Name: jace_en_fpga
// Module Name: C:/proyectos_xilinx/fpga_ace/test_ace.v
// Project Name: fpga_ace
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: jace_en_fpga
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_ace;
// Inputs
reg clk50mhz;
reg reset;
reg ear;
// Outputs
wire spk;
wire mic;
wire video;
wire sync;
// Instantiate the Unit Under Test (UUT)
jace_en_fpga uut (
.clk50mhz(clk50mhz),
.reset(reset),
.ear(ear),
.spk(spk),
.mic(mic),
.video(video),
.sync(sync)
);
initial begin
// Initialize Inputs
clk50mhz = 0;
reset = 1;
ear = 0;
// Wait 100 ns for global reset to finish
#1000;
reset = 0;
// Add stimulus here
end
always
#77 clk50mhz = !clk50mhz;
endmodule
|
//*****************************************************************************
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : infrastructure.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:09 $
// \ \ / \ Date Created : Mon Mar 2 2009
// \___\/\___\
//
//Device : Spartan-6
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : Clock generation/distribution and reset synchronization
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ns/1ps
module infrastructure #
(
parameter C_INCLK_PERIOD = 2500,
parameter C_RST_ACT_LOW = 1,
parameter C_INPUT_CLK_TYPE = "DIFFERENTIAL",
parameter C_CLKOUT0_DIVIDE = 1,
parameter C_CLKOUT1_DIVIDE = 1,
parameter C_CLKOUT2_DIVIDE = 16,
parameter C_CLKOUT3_DIVIDE = 8,
parameter C_CLKFBOUT_MULT = 2,
parameter C_DIVCLK_DIVIDE = 1
)
(
input sys_clk_p,
input sys_clk_n,
input sys_clk,
input sys_rst_i,
output clk0,
output rst0,
output async_rst,
output sysclk_2x,
output sysclk_2x_180,
output mcb_drp_clk,
output pll_ce_0,
output pll_ce_90,
output pll_lock
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on PLL/DCM lock status)
localparam RST_SYNC_NUM = 25;
localparam CLK_PERIOD_NS = C_INCLK_PERIOD / 1000.0;
localparam CLK_PERIOD_INT = C_INCLK_PERIOD/1000;
wire clk_2x_0;
wire clk_2x_180;
wire clk0_bufg;
wire clk0_bufg_in;
wire mcb_drp_clk_bufg_in;
wire clkfbout_clkfbin;
wire locked;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
reg powerup_pll_locked;
reg syn_clk0_powerup_pll_locked;
wire sys_rst;
wire bufpll_mcb_locked;
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
assign sys_rst = C_RST_ACT_LOW ? ~sys_rst_i: sys_rst_i;
assign clk0 = clk0_bufg;
assign pll_lock = bufpll_mcb_locked;
generate
if (C_INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM ("TRUE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (C_INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG u_ibufg_sys_clk
(
.I (sys_clk),
.O (sys_clk_ibufg)
);
end
endgenerate
//***************************************************************************
// Global clock generation and distribution
//***************************************************************************
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (CLK_PERIOD_NS),
.CLKIN2_PERIOD (CLK_PERIOD_NS),
.CLKOUT0_DIVIDE (C_CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (C_CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (C_CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (C_CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (180.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.SIM_DEVICE ("SPARTAN6"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (C_DIVCLK_DIVIDE),
.CLKFBOUT_MULT (C_CLKFBOUT_MULT),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.005000)
)
u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (sys_rst),
.CLKFBDCM (),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (clk_2x_0),
.CLKOUT1 (clk_2x_180),
.CLKOUT2 (clk0_bufg_in),
.CLKOUT3 (mcb_drp_clk_bufg_in),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (locked)
);
BUFG U_BUFG_CLK0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);
BUFGCE U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in),
.CE (locked)
);
always @(posedge mcb_drp_clk , posedge sys_rst)
if(sys_rst)
powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
powerup_pll_locked <= 1'b1;
always @(posedge clk0_bufg , posedge sys_rst)
if(sys_rst)
syn_clk0_powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
syn_clk0_powerup_pll_locked <= 1'b1;
//***************************************************************************
// Reset synchronization
// NOTES:
// 1. shut down the whole operation if the PLL hasn't yet locked (and
// by inference, this means that external SYS_RST_IN has been asserted -
// PLL deasserts LOCKED as soon as SYS_RST_IN asserted)
// 2. asynchronously assert reset. This was we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers).
// reset deassertion is synchronous.
// 3. asynchronous reset only look at pll_lock from PLL during power up. After
// power up and pll_lock is asserted, the powerup_pll_locked will be asserted
// forever until sys_rst is asserted again. PLL will lose lock when FPGA
// enters suspend mode. We don't want reset to MCB get
// asserted in the application that needs suspend feature.
//***************************************************************************
assign async_rst = sys_rst | ~powerup_pll_locked;
// synthesis attribute max_fanout of rst0_sync_r is 10
assign rst_tmp = sys_rst | ~syn_clk0_powerup_pll_locked;
always @(posedge clk0_bufg or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
BUFPLL_MCB BUFPLL_MCB1
( .IOCLK0 (sysclk_2x),
.IOCLK1 (sysclk_2x_180),
.LOCKED (locked),
.GCLK (mcb_drp_clk),
.SERDESSTROBE0 (pll_ce_0),
.SERDESSTROBE1 (pll_ce_90),
.PLLIN0 (clk_2x_0),
.PLLIN1 (clk_2x_180),
.LOCK (bufpll_mcb_locked)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp_macc_l.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of PCX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp_macc_l(/*AUTOARG*/
// Outputs
data_out_px_l, scan_out, shiftenable_buf,
// Inputs
arb_pcxdp_qsel1_pa, arb_pcxdp_qsel0_pa, arb_pcxdp_grant_pa,
arb_pcxdp_shift_px, arb_pcxdp_q0_hold_pa, src_pcx_data_pa,
data_crit_px_l, data_ncrit_px_l, rclk, scan_in, shiftenable
);
output [129:0] data_out_px_l; // pcx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_pcxdp_qsel1_pa; // queue write sel
input arb_pcxdp_qsel0_pa; // queue write sel
input arb_pcxdp_grant_pa;//grant signal
input arb_pcxdp_shift_px;//grant signal
input arb_pcxdp_q0_hold_pa;//grant signal
input [129:0] src_pcx_data_pa; // spache to pcx data
input [129:0] data_crit_px_l;
input [129:0] data_ncrit_px_l;
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_px;
wire [129:0] q0_datain_pa;
wire [129:0] q1_dataout, q0_dataout;
wire [129:0] data_px_l;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_pcxdp_q0_hold_pa),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_pcxdp_qsel1_pa),
.tmb_l(se_l));
// Latch and drive grant signal
// Generate write selects
dff_s #(1) dff_pcx_grin_r(
.din (arb_pcxdp_grant_pa),
.q (grant_px),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(130) dff_pcx_datain_q1(
.din (src_pcx_data_pa[129:0]),
.q (q1_dataout[129:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
/*
mux2ds #(`PCX_WIDTH) mx2ds_pcx_datain_q0(
.dout (q0_datain_pa[`PCX_WIDTH-1:0]),
.in0 (q1_dataout[`PCX_WIDTH-1:0]),
.in1 (src_pcx_data_pa[`PCX_WIDTH-1:0]),
.sel0 (arb_pcxdp_shift_px),
.sel1 (arb_pcxdp_qsel0_pa));
*/
assign q0_datain_pa[129:0] =
(arb_pcxdp_qsel0_pa ? src_pcx_data_pa[129:0] : 130'd0) |
(arb_pcxdp_shift_px ? q1_dataout[129:0] : 130'd0) ;
dff_s #(130) dff_pcx_datain_q0(
.din (q0_datain_pa[129:0]),
.q (q0_dataout[129:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_px_l[129:0] = ~(grant_px ? q0_dataout[129:0]:130'd0);
assign data_out_px_l[129:0] = data_px_l[129:0] & data_crit_px_l[129:0] & data_ncrit_px_l[129:0];
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_iqctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////////////
module sctag_iqctl
(/*AUTOARG*/
// Outputs
so, iq_array_wr_en, iq_array_wr_wl, iq_array_rd_en,
iq_array_rd_wl, sctag_pcx_stall_pq, iq_arbctl_vld_px2,
pcx_sctag_atm_px2_p, iqctl_sel_pcx, iqctl_sel_c1, iqctl_hold_rd,
sel_c1reg_over_iqarray,
// Inputs
rclk, arst_l, grst_l, se, si, pcx_sctag_data_rdy_px1,
pcx_sctag_atm_px1, sehold, arbctl_iqsel_px2
) ;
input rclk;
input arst_l;
input grst_l;
input se;
input si;
input pcx_sctag_data_rdy_px1;
input pcx_sctag_atm_px1;
input sehold; // NEW_PIN post 4.2
input arbctl_iqsel_px2;
output so;
output iq_array_wr_en;
output [3:0] iq_array_wr_wl;
output iq_array_rd_en;
output [3:0] iq_array_rd_wl;
output sctag_pcx_stall_pq;
output iq_arbctl_vld_px2;
output pcx_sctag_atm_px2_p;
output iqctl_sel_pcx;
output iqctl_sel_c1;
output iqctl_hold_rd;
output sel_c1reg_over_iqarray;
////////////////////////////////////////////////////////////////////////////////
// Local Wires declaration
////////////////////////////////////////////////////////////////////////////////
wire pcx_sctag_data_rdy_px2 ;
wire pcx_sctag_data_rdy_px2_d1 ;
wire arbctl_iqsel_px2_d1 ;
wire set_c1_reg_inst_vld ;
wire c1_reg_inst_vld ;
wire inc_wr_ptr_px2 ;
wire inc_wr_ptr_c1 ;
wire sel_wrptr_same, sel_wrptr_plus1 ;
wire [3:0] wrptr, wrptr_plus1 ;
wire [3:0] wrptr_d1, wrptr_plus1_d1 ;
wire inc_rd_ptr_px2 ;
wire [3:0] rdptr, rdptr_plus1 ;
wire [3:0] rdptr_d1 ;
wire sel_qcount_plus1 ;
wire sel_qcount_minus1 ;
wire sel_qcount_same ;
wire [4:0] que_cnt, que_cnt_plus1, que_cnt_minus1 ;
wire [4:0] next_que_cnt ;
wire que_cnt_0, que_cnt_0_p, que_cnt_0_n ;
wire que_cnt_1, que_cnt_1_p, que_cnt_1_n ;
wire que_cnt_1_plus, que_cnt_1_plus_p, que_cnt_1_plus_n ;
wire que_cnt_2, que_cnt_2_p, que_cnt_2_n ;
wire que_cnt_2_plus_p ;
wire que_cnt_3_p ;
wire que_cnt_11_p ;
wire que_cnt_12, que_cnt_12_p, que_cnt_12_n ;
wire que_cnt_12_plus, que_cnt_12_plus_p, que_cnt_12_plus_n ;
wire que_cnt_13_p ;
wire que_cnt_13_plus_p ;
wire set_iqctl_sel_iq ;
wire set_iqctl_sel_pcx ;
wire iqctl_sel_iq;
wire iqctl_sel_iq_d1;
wire iqctl_sel_iq_fe;
wire dbb_rst_l;
///////////////////////////////////////////////////////////////////
// Reset flop
///////////////////////////////////////////////////////////////////
dffrl_async #(1) reset_flop (.q(dbb_rst_l),
.clk(rclk),
.rst_l(arst_l),
.din(grst_l),
.se(se), .si(), .so());
////////////////////////////////////////////////////////////////////////////////
dff_s #(1) ff_pcx_sctag_data_rdy_px2
(.q (pcx_sctag_data_rdy_px2),
.din (pcx_sctag_data_rdy_px1),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_pcx_sctag_data_rdy_px2_d1
(.q (pcx_sctag_data_rdy_px2_d1),
.din (pcx_sctag_data_rdy_px2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_pcx_sctag_atm_px2_p
(.q (pcx_sctag_atm_px2_p),
.din (pcx_sctag_atm_px1),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_arbctl_iqsel_px2_d1
(.q (arbctl_iqsel_px2_d1),
.din (arbctl_iqsel_px2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// "c1_reg_inst_vld" signal will be used to indicate that there is a valid
// instructon in the C1 Flop. C1 flop instruction is only valid if the queue is
// empty and the instruction issued by the pcx is not selected in the same cycle
// by the arbiter. C1 flop is used to store the instruction for only one cycle
// in the case queue is empty and instruction issued by pcx is not selected by
// arbiter in the same cycle.
////////////////////////////////////////////////////////////////////////////////
assign set_c1_reg_inst_vld = ((que_cnt_0 | (que_cnt_1 & sel_qcount_minus1)) &
~c1_reg_inst_vld & pcx_sctag_data_rdy_px2 & ~arbctl_iqsel_px2) |
(((c1_reg_inst_vld) |
(que_cnt_1 & ~sel_qcount_minus1 & ~sel_qcount_plus1) |
(que_cnt_2 & sel_qcount_minus1)) &
pcx_sctag_data_rdy_px2 & arbctl_iqsel_px2) ;
dff_s #(1) ff_pcx_inst_vld_c1
(.q (c1_reg_inst_vld),
.din (set_c1_reg_inst_vld),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// Pipeline for Write Enable and Write Pointer generation for PH2 write
//
//===================================================
// PX2 | C1 |
//===================================================
// write into | write into |
// IQ array | IQ array |
// | |
// gen wrt en | gen wrt en |
// | |
// gen inc wrt | Mux select new gen inc wrt |
// ptr signal | wrt pointer ptr signal |
// | |
// gen wrt ptr | gen wrt ptr |
// plus 1 | plus 1 |
//===================================================
////////////////////////////////////////////////////////////////////////////////
assign inc_wr_ptr_px2 = pcx_sctag_data_rdy_px2 & (~arbctl_iqsel_px2 |
((~que_cnt_0 & ~(que_cnt_1 & sel_qcount_minus1)) |
c1_reg_inst_vld)) ;
dff_s #(1) ff_inc_wr_ptr_c1
(.q (inc_wr_ptr_c1),
.din (inc_wr_ptr_px2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign sel_wrptr_plus1 = dbb_rst_l & inc_wr_ptr_c1 ;
assign sel_wrptr_same = dbb_rst_l & ~inc_wr_ptr_c1 ;
assign wrptr_plus1 = wrptr + 4'b1 ;
mux3ds #(4) mux_wrptr
(.dout (wrptr[3:0]),
.in0 (4'b0), .sel0 (~dbb_rst_l),
.in1 (wrptr_plus1_d1[3:0]), .sel1 (sel_wrptr_plus1),
.in2 (wrptr_d1[3:0]), .sel2 (sel_wrptr_same)
) ;
dff_s #(4) ff_array_wr_ptr_plus1
(.q (wrptr_plus1_d1[3:0]),
.din (wrptr_plus1[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(4) ff_array_wr_ptr
(.q (wrptr_d1[3:0]),
.din (wrptr[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign iq_array_wr_en = pcx_sctag_data_rdy_px2 ;
assign iq_array_wr_wl = wrptr ;
////////////////////////////////////////////////////////////////////////////////
//==================================================
// PX2 | C1 |
//==================================================
// gen rd en | gen rd en |
// | |
// mux slect new | gen rd ptr mux slect new |
// rd ptr | plus 1 rd ptr |
//==================================================
//
// Generation of Mux select for selecting between Read Pointer and it's
// Incremented value depends on the 'arbctl_iqsel_px2' signal. New value of
// write pointer is selected and transmitted to the IQ array for reading the
// array. Since 'arbctl_iqsel_px2' signal arrives late in the cycle this may
// create timing problem.
//
////////////////////////////////////////////////////////////////////////////////
assign iq_array_rd_en = iq_arbctl_vld_px2 ;
assign iq_array_rd_wl = rdptr ;
assign inc_rd_ptr_px2 = c1_reg_inst_vld |
(que_cnt_1 & sel_qcount_plus1 & arbctl_iqsel_px2) |
(que_cnt_1_plus & ~(que_cnt_2 & sel_qcount_minus1) &
arbctl_iqsel_px2) ;
assign rdptr_plus1 = rdptr_d1 + 4'b1 ;
mux2ds #(4) mux_rdptr
(.dout (rdptr[3:0]),
.in0 (rdptr_d1[3:0]), .sel0 (~inc_rd_ptr_px2),
.in1 (rdptr_plus1[3:0]), .sel1 (inc_rd_ptr_px2)
) ;
dffrl_s #(4) ff_array_rd_ptr
(.q (rdptr_d1[3:0]),
.din (rdptr[3:0]),
.clk (rclk), .rst_l(dbb_rst_l),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
//==============================================================================
// PX2 | C1 | C2
//==============================================================================
// latch pcx rdy | gen qcount inc, dec or | new Qcount vlue
// & iqsel signals | same sig. |
// | |
// | gen next compare values | new compare values
// | based on current qcount |
// | & inc, dec or same signal |
// | |
// | latch pcx rdy | gen qcount inc, dec or
// | & iqsel signals | same sig.
// | |
// | | gen next compare values
// | | based on current qcount
// | | & inc, dec or same signal
// | |
// | | latch pcx rdy
// | | & iqsel signals
////////////////////////////////////////////////////////////////////////////////
assign sel_qcount_plus1 = pcx_sctag_data_rdy_px2_d1 & ~arbctl_iqsel_px2_d1 ;
assign sel_qcount_minus1 = ~pcx_sctag_data_rdy_px2_d1 & arbctl_iqsel_px2_d1 ;
assign sel_qcount_same = ~(sel_qcount_plus1 | sel_qcount_minus1) ;
assign que_cnt_plus1 = que_cnt + 5'b1 ;
assign que_cnt_minus1 = que_cnt - 5'b1 ;
mux3ds #(5) mux_que_cnt
(.dout (next_que_cnt[4:0]),
.in0 (que_cnt_plus1[4:0]), .sel0 (sel_qcount_plus1),
.in1 (que_cnt_minus1[4:0]), .sel1 (sel_qcount_minus1),
.in2 (que_cnt[4:0]), .sel2 (sel_qcount_same)
) ;
dffrl_s #(5) ff_que_cnt
(.q (que_cnt[4:0]),
.din (next_que_cnt[4:0]),
.clk (rclk), .rst_l (dbb_rst_l),
.se(se), .si (), .so ()
) ;
assign que_cnt_0_p = ~(|que_cnt[4:0]) ;
assign que_cnt_1_p = (~que_cnt_1_plus & que_cnt[0]) ;
assign que_cnt_1_plus_p = |(que_cnt[4:1]) ;
assign que_cnt_2_p = ~(|que_cnt[4:2] | que_cnt[0]) & que_cnt[1] ;
assign que_cnt_2_plus_p = (|que_cnt[4:2]) | (&que_cnt[1:0]) ;
assign que_cnt_3_p = ~(|que_cnt[4:2]) & (&que_cnt[1:0]) ;
assign que_cnt_11_p = (que_cnt == 5'd11) ;
assign que_cnt_12_p = (que_cnt == 5'd12) ;
assign que_cnt_12_plus_p = (que_cnt > 5'd12) ;
assign que_cnt_13_p = (que_cnt == 5'd13) ;
assign que_cnt_13_plus_p = (que_cnt > 5'd13) ;
assign que_cnt_0_n = (que_cnt_0_p & sel_qcount_same) |
(que_cnt_1_p & sel_qcount_minus1) ;
assign que_cnt_1_n = (que_cnt_1_p & sel_qcount_same) |
(que_cnt_0_p & sel_qcount_plus1) |
(que_cnt_2_p & sel_qcount_minus1) ;
assign que_cnt_1_plus_n = (que_cnt_1_plus_p & (sel_qcount_same | sel_qcount_plus1)) |
(que_cnt_1_p & sel_qcount_plus1) |
(que_cnt_2_plus_p & sel_qcount_minus1) ;
assign que_cnt_2_n = (que_cnt_2_p & sel_qcount_same) |
(que_cnt_1_p & sel_qcount_plus1) |
(que_cnt_3_p & sel_qcount_minus1) ;
assign que_cnt_12_n = (que_cnt_12_p & sel_qcount_same) |
(que_cnt_11_p & sel_qcount_plus1) |
(que_cnt_13_p & sel_qcount_minus1) ;
assign que_cnt_12_plus_n = (que_cnt_12_plus_p & (sel_qcount_same | sel_qcount_plus1)) |
(que_cnt_12_p & sel_qcount_plus1) |
(que_cnt_13_plus_p & sel_qcount_minus1) ;
dff_s #(1) ff_que_cnt_0
(.q (que_cnt_0),
.din (que_cnt_0_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_que_cnt_1
(.q (que_cnt_1),
.din (que_cnt_1_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_que_cnt_1_plus
(.q (que_cnt_1_plus),
.din (que_cnt_1_plus_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_que_cnt_2
(.q (que_cnt_2),
.din (que_cnt_2_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_que_cnt_12
(.q (que_cnt_12),
.din (que_cnt_12_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_que_cnt_12_plus
(.q (que_cnt_12_plus),
.din (que_cnt_12_plus_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// ----\/ FIX for macrotest \/---------
// sehold is high during macrotest. This will ensure that the array
// data is always chosen over the c1reg data during macrotest.
////////////////////////////////////////////////////////////////////////////////
assign sel_c1reg_over_iqarray = (wrptr_d1 == rdptr_d1) & ~sehold ;
////////////////////////////////////////////////////////////////////////////////
// MUX sel generation for IQ dp.
////////////////////////////////////////////////////////////////////////////////
//assign iqctl_sel_iq = ~c1_reg_inst_vld &
// (que_cnt_1_plus | (que_cnt_1 & ~arbctl_iqsel_px2_d1)) ;
assign set_iqctl_sel_iq = ~set_c1_reg_inst_vld &
(que_cnt_1_plus_n | (que_cnt_1_n & ~arbctl_iqsel_px2)) ;
dff_s #(1) ff_iqctl_sel_iq
(.q (iqctl_sel_iq),
.din (set_iqctl_sel_iq),
.clk (rclk),
.se (se), .si (), .so ()
) ;
//assign iqctl_sel_c1 = c1_reg_inst_vld ;
dff_s #(1) ff_iqctl_sel_c1
(.q (iqctl_sel_c1),
.din (set_c1_reg_inst_vld),
.clk (rclk),
.se (se), .si (), .so ()
) ;
//assign iqctl_sel_pcx = ~iqctl_sel_iq & ~iqctl_sel_c1 ;
assign set_iqctl_sel_pcx = ~set_iqctl_sel_iq & ~set_c1_reg_inst_vld ;
dff_s #(1) ff_iqctl_sel_pcx
(.q (iqctl_sel_pcx),
.din (set_iqctl_sel_pcx),
.clk (rclk),
.se (se), .si (), .so ()
) ;
dff_s #(1) ff_iqctl_sel_iq_d1
(.q (iqctl_sel_iq_d1),
.din (iqctl_sel_iq),
.clk (rclk),
.se (se), .si (), .so ()
) ;
assign iqctl_sel_iq_fe = iqctl_sel_iq_d1 & ~iqctl_sel_iq ;
assign iqctl_hold_rd = iqctl_sel_iq & ~arbctl_iqsel_px2 & ~iqctl_sel_iq_fe ;
////////////////////////////////////////////////////////////////////////////////
// IQ COUNT
//
// MUX here
// PQ PA PX1 PX2 C1 C2(counter update for pckt in PX2)
// PQ PA PX1 PX2 C1 C2
// PQ PA PX1 PX2 C1 C2
// PQ PA PX1 PX2 C1
// PQ PA PX1 PX2 C1 C2
// PQ PA PX1 PX2 C1
//
// When the stall is signalled, there can potentially be 5 packets in C1,
// PX2, Px1, PA and PQ that need to be queued in the IQ. The packet in PQ may
// be an atomic hence, the high water mark is 11.
////////////////////////////////////////////////////////////////////////////////
assign sctag_pcx_stall_pq = que_cnt_12_plus |
(que_cnt_12 & (pcx_sctag_data_rdy_px2_d1 &
~arbctl_iqsel_px2_d1)) ;
assign iq_arbctl_vld_px2 = pcx_sctag_data_rdy_px2 | c1_reg_inst_vld |
(que_cnt_1_plus | (que_cnt_1 & ~sel_qcount_minus1)) ;
endmodule
|
`timescale 1ns/10ps
module RegBankS2Sim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [7:0] out;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`RegBankS2_LD0,8'hAE};
inst_en = 1;
#4 inst = {`RegBankS2_RDO,8'bxxxxxxx0};
inst_en = 1;
#4 inst = {`RegBankS2_LD1,8'hAB};
inst_en = 1;
#4 inst = {`RegBankS2_RDO,8'bxxxxxxx1};
inst_en = 1;
#4 inst = {`RegBankS2_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`RegBankS2_LD1,8'h87};
inst_en = 0;
#4 inst = {`RegBankS2_LD0,8'hAE};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'hAB};
inst_en = 1;
#4 inst = {`RegBankS2_LD1,8'h27};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`RegBankS2_LD0,8'h1A};
inst_en = 1;
#4 inst = {`RegBankS2_NOP,8'bxxxxxxxx};
inst_en = 1;
end
RegBankS2
rbs2 (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.out(out));
endmodule // RegBankS2Sim
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_SYMBOL_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND3_BLACKBOX_V
/**
* nand3: 3-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_TB_V
/**
* udp_dff$PE_pp$PG: Positive edge triggered enabled D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_pe_pp_pg.v"
module top();
// Inputs are registered
reg D;
reg DATA_EN;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DATA_EN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DATA_EN = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 DATA_EN = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 DATA_EN = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 DATA_EN = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 DATA_EN = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PE_pp$PG dut (.D(D), .DATA_EN(DATA_EN), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD2_SYMBOL_V
`define SKY130_FD_SC_MS__DLYGATE4SD2_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD2_SYMBOL_V
|
// Library - static, Cell - th24, View - schematic
// LAST TIME SAVED: May 23 16:39:19 2014
// NETLIST TIME: May 23 16:39:23 2014
`timescale 1ns / 1ns
module th24 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th24";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N13 ( .d(net61), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N12 ( .d(net41), .g(d), .s(net61), .b(cds_globals.gnd_));
nfet_b N11 ( .d(net50), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N9 ( .d(net50), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N8 ( .d(net41), .g(c), .s(net50), .b(cds_globals.gnd_));
nfet_b N7 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N6 ( .d(net41), .g(b), .s(net44), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net44), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net41), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net41), .g(a), .s(net66), .b(cds_globals.gnd_));
nfet_b N0 ( .d(net66), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
pfet_b P11 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net49));
pfet_b P10 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
pfet_b P9 ( .b(cds_globals.vdd_), .g(c), .s(net49), .d(net62));
pfet_b P8 ( .b(cds_globals.vdd_), .g(d), .s(net62), .d(net63));
pfet_b P7 ( .b(cds_globals.vdd_), .g(y), .s(net63), .d(net41));
pfet_b P6 ( .b(cds_globals.vdd_), .g(d), .s(net36), .d(net64));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(net64), .d(net41));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(net35), .d(net41));
pfet_b P3 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net65));
pfet_b P2 ( .b(cds_globals.vdd_), .g(b), .s(net65), .d(net36));
pfet_b P1 ( .b(cds_globals.vdd_), .g(c), .s(net36), .d(net35));
pfet_b P0 ( .b(cds_globals.vdd_), .g(d), .s(net35), .d(net41));
inv I11 ( y, net41);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MAJ3_1_V
`define SKY130_FD_SC_LS__MAJ3_1_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__maj3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__maj3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__MAJ3_1_V
|
// ddr3_s4_uniphy_example.v
// This file was auto-generated from alt_mem_if_ddr3_tg_ed_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using SOPC Builder version 11.0sp1 208 at 2011.09.28.12:48:43
`timescale 1 ps / 1 ps
module ddr3_s4_uniphy_example (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire [1:0] mem_dm, // .mem_dm
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [15:0] mem_dq, // .mem_dq
inout wire [1:0] mem_dqs, // .mem_dqs
inout wire [1:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire local_init_done, // emif_status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire oct_rdn, // oct.rdn
input wire oct_rup, // .rup
output wire drv_status_pass, // drv_status.pass
output wire drv_status_fail, // .fail
output wire drv_status_test_complete, // .test_complete
output wire local_powerdn_ack, // local_powerdown.local_powerdn_ack
input wire local_powerdn_req // .local_powerdn_req
);
wire if0_afi_clk_clk; // if0:afi_clk -> [d0:clk, d0_avl_translator:clk, if0_avl_translator:clk, rst_controller:clk]
wire if0_afi_reset_reset; // if0:afi_reset_n -> [d0:reset_n, rst_controller:reset_in0]
wire [2:0] d0_avl_burstcount; // d0:avl_size -> d0_avl_translator:av_burstcount
wire d0_avl_waitrequest; // d0_avl_translator:av_waitrequest -> d0:avl_ready
wire [63:0] d0_avl_writedata; // d0:avl_wdata -> d0_avl_translator:av_writedata
wire [26:0] d0_avl_address; // d0:avl_addr -> d0_avl_translator:av_address
wire d0_avl_write; // d0:avl_write_req -> d0_avl_translator:av_write
wire d0_avl_beginbursttransfer; // d0:avl_burstbegin -> d0_avl_translator:av_beginbursttransfer
wire d0_avl_read; // d0:avl_read_req -> d0_avl_translator:av_read
wire [63:0] d0_avl_readdata; // d0_avl_translator:av_readdata -> d0:avl_rdata
wire [7:0] d0_avl_byteenable; // d0:avl_be -> d0_avl_translator:av_byteenable
wire d0_avl_readdatavalid; // d0_avl_translator:av_readdatavalid -> d0:avl_rdata_valid
wire d0_avl_translator_avalon_universal_master_0_waitrequest; // if0_avl_translator:uav_waitrequest -> d0_avl_translator:uav_waitrequest
wire [5:0] d0_avl_translator_avalon_universal_master_0_burstcount; // d0_avl_translator:uav_burstcount -> if0_avl_translator:uav_burstcount
wire [63:0] d0_avl_translator_avalon_universal_master_0_writedata; // d0_avl_translator:uav_writedata -> if0_avl_translator:uav_writedata
wire [26:0] d0_avl_translator_avalon_universal_master_0_address; // d0_avl_translator:uav_address -> if0_avl_translator:uav_address
wire d0_avl_translator_avalon_universal_master_0_lock; // d0_avl_translator:uav_lock -> if0_avl_translator:uav_lock
wire d0_avl_translator_avalon_universal_master_0_write; // d0_avl_translator:uav_write -> if0_avl_translator:uav_write
wire d0_avl_translator_avalon_universal_master_0_read; // d0_avl_translator:uav_read -> if0_avl_translator:uav_read
wire [63:0] d0_avl_translator_avalon_universal_master_0_readdata; // if0_avl_translator:uav_readdata -> d0_avl_translator:uav_readdata
wire d0_avl_translator_avalon_universal_master_0_debugaccess; // d0_avl_translator:uav_debugaccess -> if0_avl_translator:uav_debugaccess
wire [7:0] d0_avl_translator_avalon_universal_master_0_byteenable; // d0_avl_translator:uav_byteenable -> if0_avl_translator:uav_byteenable
wire d0_avl_translator_avalon_universal_master_0_readdatavalid; // if0_avl_translator:uav_readdatavalid -> d0_avl_translator:uav_readdatavalid
wire if0_avl_translator_avalon_anti_slave_0_waitrequest; // if0:avl_ready -> if0_avl_translator:av_waitrequest
wire [2:0] if0_avl_translator_avalon_anti_slave_0_burstcount; // if0_avl_translator:av_burstcount -> if0:avl_size
wire [63:0] if0_avl_translator_avalon_anti_slave_0_writedata; // if0_avl_translator:av_writedata -> if0:avl_wdata
wire [23:0] if0_avl_translator_avalon_anti_slave_0_address; // if0_avl_translator:av_address -> if0:avl_addr
wire if0_avl_translator_avalon_anti_slave_0_write; // if0_avl_translator:av_write -> if0:avl_write_req
wire if0_avl_translator_avalon_anti_slave_0_beginbursttransfer; // if0_avl_translator:av_beginbursttransfer -> if0:avl_burstbegin
wire if0_avl_translator_avalon_anti_slave_0_read; // if0_avl_translator:av_read -> if0:avl_read_req
wire [63:0] if0_avl_translator_avalon_anti_slave_0_readdata; // if0:avl_rdata -> if0_avl_translator:av_readdata
wire if0_avl_translator_avalon_anti_slave_0_readdatavalid; // if0:avl_rdata_valid -> if0_avl_translator:av_readdatavalid
wire [7:0] if0_avl_translator_avalon_anti_slave_0_byteenable; // if0_avl_translator:av_byteenable -> if0:avl_be
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [d0_avl_translator:reset, if0_avl_translator:reset]
ddr3_s4_uniphy_example_if0 if0 (
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_clk (if0_afi_clk_clk), // afi_clk.clk
.afi_half_clk (), // afi_half_clk.clk
.afi_reset_n (if0_afi_reset_reset), // afi_reset.reset_n
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.avl_ready (if0_avl_translator_avalon_anti_slave_0_waitrequest), // avl.waitrequest_n
.avl_burstbegin (if0_avl_translator_avalon_anti_slave_0_beginbursttransfer), // .beginbursttransfer
.avl_addr (if0_avl_translator_avalon_anti_slave_0_address), // .address
.avl_rdata_valid (if0_avl_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.avl_rdata (if0_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_wdata (if0_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_be (if0_avl_translator_avalon_anti_slave_0_byteenable), // .byteenable
.avl_read_req (if0_avl_translator_avalon_anti_slave_0_read), // .read
.avl_write_req (if0_avl_translator_avalon_anti_slave_0_write), // .write
.avl_size (if0_avl_translator_avalon_anti_slave_0_burstcount), // .burstcount
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.oct_rdn (oct_rdn), // oct.rdn
.oct_rup (oct_rup), // .rup
.local_powerdn_ack (local_powerdn_ack), // local_powerdown.local_powerdn_ack
.local_powerdn_req (local_powerdn_req) // .local_powerdn_req
);
ddr3_s4_uniphy_example_d0 #(
.DEVICE_FAMILY ("Stratix IV"),
.TG_AVL_DATA_WIDTH (64),
.TG_AVL_ADDR_WIDTH (27),
.TG_AVL_WORD_ADDR_WIDTH (24),
.TG_AVL_SIZE_WIDTH (3),
.TG_AVL_BE_WIDTH (8),
.TG_GEN_BYTE_ADDR (1),
.TG_NUM_DRIVER_LOOP (1),
.TG_RANDOM_BYTE_ENABLE (1),
.TG_ENABLE_READ_COMPARE (1),
.TG_POWER_OF_TWO_BURSTS_ONLY (0),
.TG_BURST_ON_BURST_BOUNDARY (0),
.TG_TIMEOUT_COUNTER_WIDTH (30),
.TG_MAX_READ_LATENCY (20),
.TG_SINGLE_RW_SEQ_ADDR_COUNT (32),
.TG_SINGLE_RW_RAND_ADDR_COUNT (32),
.TG_SINGLE_RW_RAND_SEQ_ADDR_COUNT (32),
.TG_BLOCK_RW_SEQ_ADDR_COUNT (8),
.TG_BLOCK_RW_RAND_ADDR_COUNT (8),
.TG_BLOCK_RW_RAND_SEQ_ADDR_COUNT (8),
.TG_BLOCK_RW_BLOCK_SIZE (8),
.TG_TEMPLATE_STAGE_COUNT (4),
.TG_SEQ_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_SEQ_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_RAND_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_SEQ_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_RAND_SEQ_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_SEQ_ADDR_GEN_RAND_ADDR_PERCENT (50)
) d0 (
.clk (if0_afi_clk_clk), // avl_clock.clk
.reset_n (if0_afi_reset_reset), // avl_reset.reset_n
.pass (drv_status_pass), // status.pass
.fail (drv_status_fail), // .fail
.test_complete (drv_status_test_complete), // .test_complete
.avl_ready (~d0_avl_waitrequest), // avl.waitrequest_n
.avl_addr (d0_avl_address), // .address
.avl_size (d0_avl_burstcount), // .burstcount
.avl_wdata (d0_avl_writedata), // .writedata
.avl_rdata (d0_avl_readdata), // .readdata
.avl_write_req (d0_avl_write), // .write
.avl_read_req (d0_avl_read), // .read
.avl_rdata_valid (d0_avl_readdatavalid), // .readdatavalid
.avl_be (d0_avl_byteenable), // .byteenable
.avl_burstbegin (d0_avl_beginbursttransfer) // .beginbursttransfer
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (64),
.AV_BURSTCOUNT_W (3),
.AV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (6),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (1),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) d0_avl_translator (
.clk (if0_afi_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (d0_avl_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (d0_avl_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (d0_avl_translator_avalon_universal_master_0_read), // .read
.uav_write (d0_avl_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (d0_avl_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (d0_avl_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (d0_avl_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (d0_avl_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (d0_avl_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (d0_avl_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (d0_avl_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (d0_avl_address), // avalon_anti_master_0.address
.av_waitrequest (d0_avl_waitrequest), // .waitrequest
.av_burstcount (d0_avl_burstcount), // .burstcount
.av_byteenable (d0_avl_byteenable), // .byteenable
.av_beginbursttransfer (d0_avl_beginbursttransfer), // .beginbursttransfer
.av_read (d0_avl_read), // .read
.av_readdata (d0_avl_readdata), // .readdata
.av_readdatavalid (d0_avl_readdatavalid), // .readdatavalid
.av_write (d0_avl_write), // .write
.av_writedata (d0_avl_writedata), // .writedata
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (24),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (3),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (6),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) if0_avl_translator (
.clk (if0_afi_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (d0_avl_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (d0_avl_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (d0_avl_translator_avalon_universal_master_0_read), // .read
.uav_write (d0_avl_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (d0_avl_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (d0_avl_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (d0_avl_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (d0_avl_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (d0_avl_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (d0_avl_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (d0_avl_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (if0_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (if0_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (if0_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (if0_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (if0_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_beginbursttransfer (if0_avl_translator_avalon_anti_slave_0_beginbursttransfer), // .beginbursttransfer
.av_burstcount (if0_avl_translator_avalon_anti_slave_0_burstcount), // .burstcount
.av_byteenable (if0_avl_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (if0_avl_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (~if0_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~if0_afi_reset_reset), // reset_in0.reset
.clk (if0_afi_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
//included for synthesis
`include "~/ee577b/syn/src/control.h"
/*
*ALU Functions Included (in order coded below):
* mules
* mulos
* muleu
* mulou
*/
module alu_mult(reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
// Input signals
input [0:127] reg_A;
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
input [0:4] alu_op;
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
// Declare "reg" signals:
reg [0:127] result;
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
integer sgn;
integer i;
integer j;
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// !!TROY PART 2 START!!
// ======================================================
// Signed Multiplication - even subfields
`aluwmules:
begin
case(ctrl_ww)
(`w8+2'b1): // aluwmules AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[0:7];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[0:7];
if(reg_B[0]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[0:7];
end
else
begin
p_pdt8a2[8:15]=reg_B[0:7];
end
end
else
begin
p_pdt8a[8:15]=reg_A[0:7];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]<=1+~p_pdt[0:15];
end
else
begin
result[0:15]<=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[16:23];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[16:23];
if(reg_B[16]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[16:23];
end
else
begin
p_pdt8b2[8:15]=reg_B[16:23];
end
end
else
begin
p_pdt8b[8:15]=reg_A[16:23];
end
p_pdt8b[0:7]=8'd0;
$display("p_pdt8b[0:15]",p_pdt8b[0:15]);
$display("p_pdt8b2[0:15]",p_pdt8b2[0:15]);
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
$display("p_pdt[16:31]",p_pdt[16:31]);
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
$display("MINUSp_pdt[16:31]",p_pdt[16:31]);
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
$display("ADDp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
$display("ZEROp_pdt[16:31]",p_pdt[16:31]);
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]<=1+~p_pdt[16:31];
$display("INVp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
result[16:31]<=p_pdt[16:31];
$display("RESp_pdt[16:31]",p_pdt[16:31]);
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[32:39];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[32:39];
if(reg_B[32]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[32:39];
end
else
begin
p_pdt8c2[8:15]=reg_B[32:39];
end
end
else
begin
p_pdt8c[8:15]=reg_A[32:39];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]<=1+~p_pdt[32:47];
end
else
begin
result[32:47]<=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[48:55];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[48:55];
if(reg_B[48]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[48:55];
end
else
begin
p_pdt8d2[8:15]=reg_B[48:55];
end
end
else
begin
p_pdt8d[8:15]=reg_A[48:55];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]<=1+~p_pdt[48:63];
end
else
begin
result[48:63]<=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[64:71];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[64:71];
if(reg_B[64]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[64:71];
end
else
begin
p_pdt8e2[8:15]=reg_B[64:71];
end
end
else
begin
p_pdt8e[8:15]=reg_A[64:71];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]<=1+~p_pdt[64:79];
end
else
begin
result[64:79]<=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[80:87];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[80:87];
if(reg_B[80]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[80:87];
end
else
begin
p_pdt8f2[8:15]=reg_B[80:87];
end
end
else
begin
p_pdt8f[8:15]=reg_A[80:87];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]<=1+~p_pdt[80:95];
end
else
begin
result[80:95]<=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[96:103];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[96:103];
if(reg_B[96]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[96:103];
end
else
begin
p_pdt8g2[8:15]=reg_B[96:103];
end
end
else
begin
p_pdt8g[8:15]=reg_A[96:103];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]<=1+~p_pdt[96:111];
end
else
begin
result[96:111]<=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[112:119];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[112:119];
if(reg_B[112]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[112:119];
end
else
begin
p_pdt8h2[8:15]=reg_B[112:119];
end
end
else
begin
p_pdt8h[8:15]=reg_A[112:119];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]<=1+~p_pdt[112:127];
end
else
begin
result[112:127]<=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
end
(`w16+2'b1): // aluwmules AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[0:15];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[0:15];
if(reg_B[0]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[0:15];
end
else
begin
p_pdt16a2[16:31]=reg_B[0:15];
end
end
else
begin
p_pdt16a[16:31]=reg_A[0:15];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]<=1+~p_pdt[0:31];
end
else
begin
result[0:31]<=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[32:47];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[32:47];
if(reg_B[32]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[32:47];
end
else
begin
p_pdt16b2[16:31]=reg_B[32:47];
end
end
else
begin
p_pdt16b[16:31]=reg_A[0:15];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]<=1+~p_pdt[32:63];
end
else
begin
result[32:63]<=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[64:79];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[64:79];
if(reg_B[64]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[64:79];
end
else
begin
p_pdt16c2[16:31]=reg_B[64:79];
end
end
else
begin
p_pdt16c[16:31]=reg_A[64:79];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]<=1+~p_pdt[64:95];
end
else
begin
result[64:95]<=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[96:111];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[96:111];
if(reg_B[96]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[96:111];
end
else
begin
p_pdt16d2[16:31]=reg_B[96:111];
end
end
else
begin
p_pdt16d[16:31]=reg_A[96:111];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]<=1+~p_pdt[96:127];
end
else
begin
result[96:127]<=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// Signed Multiplication - odd subfields
`aluwmulos:
begin
case(ctrl_ww)
(`w8+2'b1): // aluwmulos AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[8:15];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[8]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[8:15];
if(reg_B[8]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[8:15];
end
else
begin
p_pdt8a2[8:15]=reg_B[8:15];
end
end
else
begin
p_pdt8a[8:15]=reg_A[8:15];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]<=1+~p_pdt[0:15];
end
else
begin
result[0:15]<=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[24:31];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[24]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[24:31];
if(reg_B[24]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[24:31];
end
else
begin
p_pdt8b2[8:15]=reg_B[24:31];
end
end
else
begin
p_pdt8b[8:15]=reg_A[24:31];
end
p_pdt8b[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]<=1+~p_pdt[16:31];
end
else
begin
result[16:31]<=p_pdt[16:31];
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[40:47];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[40]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[40:47];
if(reg_B[40]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[40:47];
end
else
begin
p_pdt8c2[8:15]=reg_B[40:47];
end
end
else
begin
p_pdt8c[8:15]=reg_A[40:47];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]<=1+~p_pdt[32:47];
end
else
begin
result[32:47]<=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[56:63];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[56]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[56:63];
if(reg_B[56]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[56:63];
end
else
begin
p_pdt8d2[8:15]=reg_B[56:63];
end
end
else
begin
p_pdt8d[8:15]=reg_A[56:63];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]<=1+~p_pdt[48:63];
end
else
begin
result[48:63]<=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[72:79];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[72]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[72:79];
if(reg_B[72]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[72:79];
end
else
begin
p_pdt8e2[8:15]=reg_B[72:79];
end
end
else
begin
p_pdt8e[8:15]=reg_A[72:79];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]<=1+~p_pdt[64:79];
end
else
begin
result[64:79]<=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[88:95];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[88]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[88:95];
if(reg_B[88]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[88:95];
end
else
begin
p_pdt8f2[8:15]=reg_B[88:95];
end
end
else
begin
p_pdt8f[8:15]=reg_A[88:95];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]<=1+~p_pdt[80:95];
end
else
begin
result[80:95]<=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[104:111];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[104]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[104:111];
if(reg_B[104]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[104:111];
end
else
begin
p_pdt8g2[8:15]=reg_B[104:111];
end
end
else
begin
p_pdt8g[8:15]=reg_A[104:111];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]<=1+~p_pdt[96:111];
end
else
begin
result[96:111]<=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[120:127];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[120]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[120:127];
if(reg_B[120]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[120:127];
end
else
begin
p_pdt8h2[8:15]=reg_B[120:127];
end
end
else
begin
p_pdt8h[8:15]=reg_A[120:127];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]<=1+~p_pdt[112:127];
end
else
begin
result[112:127]<=p_pdt[112:127];
end
// ---------------------------------------
end
(`w16+2'b1): // aluwmulos AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[16:31];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[16:31];
if(reg_B[16]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[16:31];
end
else
begin
p_pdt16a2[16:31]=reg_B[16:31];
end
end
else
begin
p_pdt16a[16:31]=reg_A[16:31];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]<=1+~p_pdt[0:31];
end
else
begin
result[0:31]<=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[48:63];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[48:63];
if(reg_B[48]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[48:63];
end
else
begin
p_pdt16b2[16:31]=reg_B[48:63];
end
end
else
begin
p_pdt16b[16:31]=reg_A[48:63];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]<=1+~p_pdt[32:63];
end
else
begin
result[32:63]<=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[80:95];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[80:95];
if(reg_B[80]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[80:95];
end
else
begin
p_pdt16c2[16:31]=reg_B[80:95];
end
end
else
begin
p_pdt16c[16:31]=reg_A[80:95];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]<=1+~p_pdt[64:95];
end
else
begin
result[64:95]<=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[112:127];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[112:127];
if(reg_B[112]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[112:127];
end
else
begin
p_pdt16d2[16:31]=reg_B[112:127];
end
end
else
begin
p_pdt16d[16:31]=reg_A[112:127];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]<=1+~p_pdt[96:127];
end
else
begin
result[96:127]<=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result<=128'd0;
end
endcase
end
// ===========================================
// Unsigned Multiplication - even subfields
`aluwmuleu:
begin
case(ctrl_ww)
(`w8+2'b1):
begin
// 1st even byte
// extend operand B
p_pdt8a2={{8{1'b0}},reg_B[0+(16*0):7+(16*0)]};
// extend operand A
p_pdt8a={{8{1'b0}},reg_A[0+(16*0):7+(16*0)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*0):15+(16*0)]=p_pdt[0+(16*0):15+(16*0)]
+ (p_pdt8a[i]?(p_pdt8a2<<(8'd15-i)):16'b0);
// 2nd even byte
// extend operand B
p_pdt8b2={{8{1'b0}},reg_B[0+(16*1):7+(16*1)]};
// extend operand A
p_pdt8b={{8{1'b0}},reg_A[0+(16*1):7+(16*1)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*1):15+(16*1)]=p_pdt[0+(16*1):15+(16*1)]
+ (p_pdt8b[i]?(p_pdt8b2<<(8'd15-i)):16'b0);
// 3rd even byte
// extend operand B
p_pdt8c2={{8{1'b0}},reg_B[0+(16*2):7+(16*2)]};
// extend operand A
p_pdt8c={{8{1'b0}},reg_A[0+(16*2):7+(16*2)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*2):15+(16*2)]=p_pdt[0+(16*2):15+(16*2)]
+ (p_pdt8c[i]?(p_pdt8c2<<(8'd15-i)):16'b0);
// 4th even byte
// extend operand B
p_pdt8d2={{8{1'b0}},reg_B[0+(16*3):7+(16*3)]};
// extend operand A
p_pdt8d={{8{1'b0}},reg_A[0+(16*3):7+(16*3)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*3):15+(16*3)]=p_pdt[0+(16*3):15+(16*3)]
+ (p_pdt8d[i]?(p_pdt8d2<<(8'd15-i)):16'b0);
// 5th even byte
// extend operand B
p_pdt8e2={{8{1'b0}},reg_B[0+(16*4):7+(16*4)]};
// extend operand A
p_pdt8e={{8{1'b0}},reg_A[0+(16*4):7+(16*4)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*4):15+(16*4)]=p_pdt[0+(16*4):15+(16*4)]
+ (p_pdt8e[i]?(p_pdt8e2<<(8'd15-i)):16'b0);
// 6th even byte
// extend operand B
p_pdt8f2={{8{1'b0}},reg_B[0+(16*5):7+(16*5)]};
// extend operand A
p_pdt8f={{8{1'b0}},reg_A[0+(16*5):7+(16*5)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*5):15+(16*5)]=p_pdt[0+(16*5):15+(16*5)]
+ (p_pdt8f[i]?(p_pdt8f2<<(8'd15-i)):16'b0);
// 7th even byte
// extend operand B
p_pdt8g2={{8{1'b0}},reg_B[0+(16*6):7+(16*6)]};
// extend operand A
p_pdt8g={{8{1'b0}},reg_A[0+(16*6):7+(16*6)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*6):15+(16*6)]=p_pdt[0+(16*6):15+(16*6)]
+ (p_pdt8g[i]?(p_pdt8g2<<(8'd15-i)):16'b0);
// 8th even byte
// extend operand B
p_pdt8h2={{8{1'b0}},reg_B[0+(16*7):7+(16*7)]};
// extend operand A
p_pdt8h={{8{1'b0}},reg_A[0+(16*7):7+(16*7)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*7):15+(16*7)]=p_pdt[0+(16*7):15+(16*7)]
+ (p_pdt8h[i]?(p_pdt8h2<<(8'd15-i)):16'b0);
result<=p_pdt;
end // case (`w8+2'b1)
(`w16+2'b1):
begin
// 1st word
// extend operand B
p_pdt16a2={{16{1'b0}},reg_B[0+(32*0):15+(32*0)]};
// extend operand A
p_pdt16a={{16{1'b0}},reg_A[0+(32*0):15+(32*0)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*0):31+(32*0)]=p_pdt[0+(32*0):31+(32*0)]
+ (p_pdt16a[i]?(p_pdt16a2<<(8'd31-i)):32'b0);
// 2nd word
// extend operand B
p_pdt16b2={{16{1'b0}},reg_B[0+(32*1):15+(32*1)]};
// extend operand A
p_pdt16b={{16{1'b0}},reg_A[0+(32*1):15+(32*1)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*1):31+(32*1)]=p_pdt[0+(32*1):31+(32*1)]
+ (p_pdt16b[i]?(p_pdt16b2<<(8'd31-i)):32'b0);
// 3rd word
// extend operand B
p_pdt16c2={{16{1'b0}},reg_B[0+(32*2):15+(32*2)]};
// extend operand A
p_pdt16c={{16{1'b0}},reg_A[0+(32*2):15+(32*2)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*2):31+(32*2)]=p_pdt[0+(32*2):31+(32*2)]
+ (p_pdt16c[i]?(p_pdt16c2<<(8'd31-i)):32'b0);
// 4th word
// extend operand B
p_pdt16d2={{16{1'b0}},reg_B[0+(32*3):15+(32*3)]};
// extend operand A
p_pdt16d={{16{1'b0}},reg_A[0+(32*3):15+(32*3)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*3):31+(32*3)]=p_pdt[0+(32*3):31+(32*3)]
+ (p_pdt16d[i]?(p_pdt16d2<<(8'd31-i)):32'b0);
result<=p_pdt;
end // case (`w16+2'b1)
default:
begin
result<=128'd0;
end
endcase // case(ctrl_ww)
end
// ===================================
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
(`w8+2'd1): // aluwmulou AND `w8
begin
p_pdt8a[8:15]=reg_A[8:15];
p_pdt8a[0:7]=8'd0;
p_pdt8a2[0:15]={{8{1'b0}},reg_B[8:15]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[0:15]=p_pdt[0:15]+((p_pdt8a[sgn]==1'd1)?(p_pdt8a2<<(8'd15-sgn)):16'b0);
end
p_pdt8b[8:15]=reg_A[24:31];
p_pdt8b[0:7]=8'd0;
p_pdt8b2[0:15]={{8{1'b0}},reg_B[24:31]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[16:31]=p_pdt[16:31]+((p_pdt8b[sgn]==1'd1)?(p_pdt8b2<<(8'd15-sgn)):16'b0);
end
p_pdt8c[8:15]=reg_A[40:47];
p_pdt8c[0:7]=8'd0;
p_pdt8c2[0:15]={{8{1'b0}},reg_B[40:47]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[32:47]=p_pdt[32:47]+((p_pdt8c[sgn]==1'd1)?(p_pdt8c2<<(8'd15-sgn)):16'b0);
end
p_pdt8d[8:15]=reg_A[56:63];
p_pdt8d[0:7]=8'd0;
p_pdt8d2[0:15]={{8{1'b0}},reg_B[56:63]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[48:63]=p_pdt[48:63]+((p_pdt8d[sgn]==1'd1)?(p_pdt8d2<<(8'd15-sgn)):16'b0);
end
p_pdt8e[8:15]=reg_A[72:79];
p_pdt8e[0:7]=8'd0;
p_pdt8e2[0:15]={{8{1'b0}},reg_B[72:79]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[64:79]=p_pdt[64:79]+((p_pdt8e[sgn]==1'd1)?(p_pdt8e2<<(8'd15-sgn)):16'b0);
end
p_pdt8f[8:15]=reg_A[88:95];
p_pdt8f[0:7]=8'd0;
p_pdt8f2[0:15]={{8{1'b0}},reg_B[88:95]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[80:95]=p_pdt[80:95]+((p_pdt8f[sgn]==1'd1)?(p_pdt8f2<<(8'd15-sgn)):16'b0);
end
p_pdt8g[8:15]=reg_A[104:111];
p_pdt8g[0:7]=8'd0;
p_pdt8g2[0:15]={{8{1'b0}},reg_B[104:111]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[96:111]=p_pdt[96:111]+((p_pdt8g[sgn]==1'd1)?(p_pdt8g2<<(8'd15-sgn)):16'b0);
end
p_pdt8h[8:15]=reg_A[120:127];
p_pdt8h[0:7]=8'd0;
p_pdt8h2[0:15]={{8{1'b0}},reg_B[120:127]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[112:127]=p_pdt[112:127]+((p_pdt8h[sgn]==1'd1)?(p_pdt8h2<<(8'd15-sgn)):16'b0);
end
result<=p_pdt;
end
(`w16+2'b01): // aluwmulou AND `w16
begin
p_pdt16a[0:31]={{16{1'b0}},reg_B[16:31]};
p_pdt16a2[0:31]={{16{1'b0}},reg_A[16:31]};
p_pdt16b[0:31]={{16{1'b0}},reg_B[48:63]};
p_pdt16b2[0:31]={{16{1'b0}},reg_A[48:63]};
p_pdt16c[0:31]={{16{1'b0}},reg_B[80:95]};
p_pdt16c2[0:31]={{16{1'b0}},reg_A[80:95]};
p_pdt16d[0:31]={{16{1'b0}},reg_B[112:127]};
p_pdt16d2[0:31]={{16{1'b0}},reg_A[112:127]};
for(sgn=31; sgn>=16; sgn=sgn-1)
begin
p_pdt[0:31]=p_pdt[0:31]+((p_pdt16a[sgn]==1'd1)?(p_pdt16a2<<(16'd31-sgn)):32'd0);
p_pdt[32:63]=p_pdt[32:63]+((p_pdt16b[sgn]==1'd1)?(p_pdt16b2<<(16'd31-sgn)):32'd0);
p_pdt[64:95]=p_pdt[64:95]+((p_pdt16c[sgn]==1'd1)?(p_pdt16c2<<(16'd31-sgn)):32'd0);
p_pdt[96:127]=p_pdt[96:127]+((p_pdt16d[sgn]==1'd1)?(p_pdt16d2<<(16'd31-sgn)):32'd0);
end
result<=p_pdt;
end
default: // aluwmulou AND Default
begin
result<=128'd0;
end
endcase
end
// !!TROY PART 2 END!!
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:45:02 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_prog_rom_0_0/RAT_prog_rom_0_0_sim_netlist.v
// Design : RAT_prog_rom_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_prog_rom_0_0,prog_rom,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "prog_rom,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_prog_rom_0_0
(ADDRESS,
INSTRUCTION,
CLK);
input [9:0]ADDRESS;
output [17:0]INSTRUCTION;
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;
wire [9:0]ADDRESS;
wire CLK;
wire [17:0]INSTRUCTION;
RAT_prog_rom_0_0_prog_rom U0
(.ADDRESS(ADDRESS),
.CLK(CLK),
.INSTRUCTION(INSTRUCTION));
endmodule
(* ORIG_REF_NAME = "prog_rom" *)
module RAT_prog_rom_0_0_prog_rom
(INSTRUCTION,
CLK,
ADDRESS);
output [17:0]INSTRUCTION;
input CLK;
input [9:0]ADDRESS;
wire [9:0]ADDRESS;
wire CLK;
wire [17:0]INSTRUCTION;
wire [15:0]NLW_ram_1024_x_18_DIBDI_UNCONNECTED;
wire [1:0]NLW_ram_1024_x_18_DIPBDIP_UNCONNECTED;
wire [15:0]NLW_ram_1024_x_18_DOBDO_UNCONNECTED;
wire [1:0]NLW_ram_1024_x_18_DOPBDOP_UNCONNECTED;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* XILINX_LEGACY_PRIM = "RAMB16_S18" *)
(* XILINX_TRANSFORM_PINMAP = "ADDR[0]:ADDRARDADDR[4] ADDR[1]:ADDRARDADDR[5] ADDR[2]:ADDRARDADDR[6] ADDR[3]:ADDRARDADDR[7] ADDR[4]:ADDRARDADDR[8] ADDR[5]:ADDRARDADDR[9] ADDR[6]:ADDRARDADDR[10] ADDR[7]:ADDRARDADDR[11] ADDR[8]:ADDRARDADDR[12] ADDR[9]:ADDRARDADDR[13] CLK:CLKARDCLK DI[0]:DIADI[0] DI[10]:DIADI[10] DI[11]:DIADI[11] DI[12]:DIADI[12] DI[13]:DIADI[13] DI[14]:DIADI[14] DI[15]:DIADI[15] DI[1]:DIADI[1] DI[2]:DIADI[2] DI[3]:DIADI[3] DI[4]:DIADI[4] DI[5]:DIADI[5] DI[6]:DIADI[6] DI[7]:DIADI[7] DI[8]:DIADI[8] DI[9]:DIADI[9] DIP[0]:DIPADIP[0] DIP[1]:DIPADIP[1] DO[0]:DOADO[0] DO[10]:DOADO[10] DO[11]:DOADO[11] DO[12]:DOADO[12] DO[13]:DOADO[13] DO[14]:DOADO[14] DO[15]:DOADO[15] DO[1]:DOADO[1] DO[2]:DOADO[2] DO[3]:DOADO[3] DO[4]:DOADO[4] DO[5]:DOADO[5] DO[6]:DOADO[6] DO[7]:DOADO[7] DO[8]:DOADO[8] DO[9]:DOADO[9] DOP[0]:DOPADOP[0] DOP[1]:DOPADOP[1] EN:ENARDEN SSR:RSTRAMARSTRAM WE:WEA[1],WEA[0]" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h000000000000000000000000000000000000000000000000000000CF00000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000080804A400A5A6BFF2A20),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.READ_WIDTH_A(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_WIDTH_A(18))
ram_1024_x_18
(.ADDRARDADDR({ADDRESS,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(CLK),
.CLKBWRCLK(1'b0),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI(NLW_ram_1024_x_18_DIBDI_UNCONNECTED[15:0]),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP(NLW_ram_1024_x_18_DIPBDIP_UNCONNECTED[1:0]),
.DOADO(INSTRUCTION[15:0]),
.DOBDO(NLW_ram_1024_x_18_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(INSTRUCTION[17:16]),
.DOPBDOP(NLW_ram_1024_x_18_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCIN_BEHAVIORAL_V
`define SKY130_FD_SC_HS__FAHCIN_BEHAVIORAL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire u_vpwr_vgnd1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , u_vpwr_vgnd1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCIN_BEHAVIORAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ffu_ctl_visctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ffu_ctl_visctl
// Description: This is the ffu vis control block.
*/
module sparc_ffu_ctl_visctl (/*AUTOARG*/
// Outputs
ctl_vis_sel_add, ctl_vis_sel_log, ctl_vis_sel_align,
ctl_vis_add32, ctl_vis_subtract, ctl_vis_cin, ctl_vis_align0,
ctl_vis_align2, ctl_vis_align4, ctl_vis_align6, ctl_vis_align_odd,
ctl_vis_log_sel_pass, ctl_vis_log_sel_nand, ctl_vis_log_sel_nor,
ctl_vis_log_sel_xor, ctl_vis_log_invert_rs1,
ctl_vis_log_invert_rs2, ctl_vis_log_constant,
ctl_vis_log_pass_const, ctl_vis_log_pass_rs1,
ctl_vis_log_pass_rs2, vis_result, illegal_vis_e, vis_nofrf_e,
visop_m, visop_w_vld, vis_wen_next, fpu_rnd,
ffu_exu_rsr_data_hi_m, ffu_exu_rsr_data_mid_m,
ffu_exu_rsr_data_lo_m, ctl_dp_wsr_data_w2, ctl_dp_gsr_wsr_w2,
ctl_dp_thr_e,
// Inputs
clk, se, reset, opf, tid_w2, tid_e, tid, visop_e, kill_w,
ifu_tlu_sraddr_d, exu_ffu_wsr_inst_e, exu_ffu_gsr_align_m,
exu_ffu_gsr_rnd_m, exu_ffu_gsr_mask_m, exu_ffu_gsr_scale_m,
ifu_ffu_rnd_e, dp_ctl_fsr_rnd, flush_w2, thr_match_mw2,
thr_match_ww2, ifu_tlu_inst_vld_w, ue_trap_w3, frs1_e, frs2_e,
frd_e, rollback_c3, rollback_rs2_w2, visop, rollback_rs1_w3,
dp_ctl_gsr_mask_e, dp_ctl_gsr_scale_e
) ;
input clk;
input se;
input reset;
input [8:0] opf;
input [1:0] tid_w2;
input [1:0] tid_e;
input [1:0] tid;
input visop_e;
input kill_w;
input [6:0] ifu_tlu_sraddr_d;
input exu_ffu_wsr_inst_e;
input [2:0] exu_ffu_gsr_align_m;
input [2:0] exu_ffu_gsr_rnd_m;
input [31:0] exu_ffu_gsr_mask_m;
input [4:0] exu_ffu_gsr_scale_m;
input [2:0] ifu_ffu_rnd_e;
input [1:0] dp_ctl_fsr_rnd;
input flush_w2;
input thr_match_mw2;
input thr_match_ww2;
input ifu_tlu_inst_vld_w;
input ue_trap_w3;
input [4:0] frs1_e;
input [4:0] frs2_e;
input [4:0] frd_e;
input rollback_c3;
input rollback_rs2_w2;
input visop;
input rollback_rs1_w3;
input [31:0] dp_ctl_gsr_mask_e;
input [4:0] dp_ctl_gsr_scale_e;
output ctl_vis_sel_add;
output ctl_vis_sel_log;
output ctl_vis_sel_align;
output ctl_vis_add32;
output ctl_vis_subtract;
output ctl_vis_cin;
output ctl_vis_align0;
output ctl_vis_align2;
output ctl_vis_align4;
output ctl_vis_align6;
output ctl_vis_align_odd;
output ctl_vis_log_sel_pass;
output ctl_vis_log_sel_nand;
output ctl_vis_log_sel_nor;
output ctl_vis_log_sel_xor;
output ctl_vis_log_invert_rs1;
output ctl_vis_log_invert_rs2;
output ctl_vis_log_constant;
output ctl_vis_log_pass_const;
output ctl_vis_log_pass_rs1;
output ctl_vis_log_pass_rs2;
output vis_result;
output illegal_vis_e;
output vis_nofrf_e;
output visop_m;
output visop_w_vld;
output vis_wen_next;
output [1:0] fpu_rnd;
output [31:0] ffu_exu_rsr_data_hi_m;
output [2:0] ffu_exu_rsr_data_mid_m;
output [7:0] ffu_exu_rsr_data_lo_m;
output [36:0] ctl_dp_wsr_data_w2;
output [3:0] ctl_dp_gsr_wsr_w2;
output [3:0] ctl_dp_thr_e;
wire illegal_rs1_e;
wire illegal_rs2_e;
wire illegal_siam_e;
wire rs2_check_nonzero_e;
wire rs1_check_nonzero_e;
wire visop_e;
wire issue_visop_e;
wire visop_m;
wire visop_w;
wire visop_w_vld;
wire visop_w2_vld;
wire visop_w2;
wire visop_w3;
wire visop_w3_vld;
wire add;
wire align;
wire logic;
wire siam;
wire alignaddr;
wire opf_log_zero;
wire opf_log_one;
wire opf_log_src1;
wire opf_log_src2;
wire opf_log_not1;
wire opf_log_not2;
wire opf_log_or;
wire opf_log_nor;
wire opf_log_and;
wire opf_log_nand;
wire opf_log_xor;
wire opf_log_xnor;
wire opf_log_ornot1;
wire opf_log_ornot2;
wire opf_log_andnot1;
wire opf_log_andnot2;
wire invert_rs1_next;
wire invert_rs2_next;
wire log_pass_rs1_next;
wire log_pass_rs2_next;
wire log_pass_rs1;
wire log_pass_rs2;
wire [2:0] t0_gsr_rnd;
wire [2:0] t1_gsr_rnd;
wire [2:0] t2_gsr_rnd;
wire [2:0] t3_gsr_rnd;
wire [2:0] t0_gsr_align;
wire [2:0] t1_gsr_align;
wire [2:0] t2_gsr_align;
wire [2:0] t3_gsr_align;
wire [2:0] t0_gsr_rnd_next;
wire [2:0] t1_gsr_rnd_next;
wire [2:0] t2_gsr_rnd_next;
wire [2:0] t3_gsr_rnd_next;
wire [2:0] t0_gsr_align_next;
wire [2:0] t1_gsr_align_next;
wire [2:0] t2_gsr_align_next;
wire [2:0] t3_gsr_align_next;
wire [2:0] gsr_rnd_e;
wire [2:0] gsr_align_e;
wire t0_rnd_wen_l;
wire t0_gsr_wsr_w2;
wire t0_siam_w2;
wire t0_align_wen_l;
wire t0_alignaddr_w2;
wire t1_rnd_wen_l;
wire t1_gsr_wsr_w2;
wire t1_siam_w2;
wire t1_align_wen_l;
wire t1_alignaddr_w2;
wire t2_rnd_wen_l;
wire t2_gsr_wsr_w2;
wire t2_siam_w2;
wire t2_align_wen_l;
wire t2_alignaddr_w2;
wire t3_rnd_wen_l;
wire t3_gsr_wsr_w2;
wire t3_siam_w2;
wire t3_align_wen_l;
wire t3_alignaddr_w2;
wire [2:0] siam_rnd;
wire [3:0] thr_w2;
wire [3:0] ctl_dp_thr_e;
wire [3:0] thr_fp;
wire gsr_addr_d;
wire gsr_addr_e;
wire wgsr_e;
wire wgsr_m;
wire wgsr_w;
wire wgsr_vld_m;
wire wgsr_vld_w;
wire wgsr_vld_w2;
wire wgsr_w2;
wire [2:0] gsr_rnd;
wire [1:0] fpu_rnd_next;
wire [2:0] gsr_align;
wire [2:0] gsr_align_d1;
wire [2:0] align_addr_data_w2;
wire [2:0] wgsr_align_offset_w;
wire [2:0] wgsr_rnd_w;
wire [2:0] wgsr_align_offset_w2;
wire [2:0] wgsr_rnd_w2;
wire [36:0] wsr_data_m;
wire [36:0] wsr_data_w;
//////////////////////////////////////
// VIS PIPELINE
//------------------------------------
// Note: rs2_ce, rs2_ue, rs1_ue will kill vis instruction
// in addition to any traps, etc.
// These are incorporated into the "kill" signals
// E: ren rs2
// M: ren rs1
// W: rs2 data ready, check rs2 ecc
// W2: rs1 data ready, check rs1 ecc
// W3: execute vis operation (result written to rs2/rd flop)
// W4: gen ecc and write to frf
dff_s visop_e2m(.din(issue_visop_e), .clk(clk), .q(visop_m), .si(), .so(), .se(se));
dff_s visop_m2w(.din(visop_m), .clk(clk), .q(visop_w), .si(), .so(), .se(se));
dff_s visop_w2w2(.din(visop_w_vld), .clk(clk), .q(visop_w2), .si(), .so(), .se(se));
dff_s visop_w22w3(.din(visop_w2_vld), .clk(clk), .q(visop_w3), .si(), .so(), .se(se));
assign issue_visop_e = visop_e | visop & rollback_c3;
// only check kills in w since they are accumulated into kill_w
assign visop_w_vld = visop_w & ~kill_w;
assign visop_w2_vld = visop_w2 & ~flush_w2 & ~rollback_rs2_w2;
assign visop_w3_vld = visop_w3 & ~ue_trap_w3 & ~rollback_rs1_w3;
assign vis_result = visop_w3_vld;
assign vis_wen_next = vis_result & ~siam & ~alignaddr;
////////////////////////////////////
// Decode opf
////////////////////////////////////
assign add = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & opf[4] & ~opf[3];
assign align = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & ~opf[4] & opf[3] & ~opf[2] & ~opf[1] & ~opf[0];
assign logic = ~opf[8] & ~opf[7] & opf[6] & opf[5];
assign siam = ~opf[8] & opf[7] & ~opf[6] & ~opf[5] & ~opf[4] & ~opf[3] & ~opf[2] & ~opf[1] & opf[0];
assign alignaddr = ~opf[8] & ~opf[7] & ~opf[6] & ~opf[5] & opf[4] & opf[3] & ~opf[2] & ~opf[0]; //alignaddress
assign illegal_vis_e = (visop_e & ~(add | align | logic | siam | alignaddr) |
illegal_rs1_e | illegal_rs2_e | illegal_siam_e);
assign rs1_check_nonzero_e = visop_e & (siam | (logic & (opf_log_zero | opf_log_one | opf_log_src2 | opf_log_not2)));
assign rs2_check_nonzero_e = visop_e & logic & (opf_log_zero | opf_log_one | opf_log_src1 | opf_log_not1);
assign illegal_rs1_e = (frs1_e[4:0] != 5'b00000) & rs1_check_nonzero_e;
assign illegal_rs2_e = (frs2_e[4:0] != 5'b00000) & rs2_check_nonzero_e;
assign illegal_siam_e = ((frd_e[4:0] != 5'b00000) | frs2_e[4] | frs2_e[3]) & siam & visop_e;
assign vis_nofrf_e = visop_e & (siam | alignaddr | opf_log_zero | opf_log_one);
// controls for add
// Make subtract come out of its own flop for loading purposes (very critical timing)
dff_s sub_dff(.din(opf[2]), .clk(clk), .q(ctl_vis_subtract), .se(se), .si(), .so());
assign ctl_vis_cin = opf[2];
assign ctl_vis_add32 = opf[1];
// controls for logic
assign opf_log_zero = ~opf[4] & ~opf[3] & ~opf[2] & ~opf[1];
assign opf_log_nor = ~opf[4] & ~opf[3] & ~opf[2] & opf[1];
assign opf_log_andnot2 = ~opf[4] & ~opf[3] & opf[2] & ~opf[1];
assign opf_log_not2 = ~opf[4] & ~opf[3] & opf[2] & opf[1];
assign opf_log_andnot1 = ~opf[4] & opf[3] & ~opf[2] & ~opf[1];
assign opf_log_not1 = ~opf[4] & opf[3] & ~opf[2] & opf[1];
assign opf_log_xor = ~opf[4] & opf[3] & opf[2] & ~opf[1];
assign opf_log_nand = ~opf[4] & opf[3] & opf[2] & opf[1];
assign opf_log_and = opf[4] & ~opf[3] & ~opf[2] & ~opf[1];
assign opf_log_xnor = opf[4] & ~opf[3] & ~opf[2] & opf[1];
assign opf_log_src1 = opf[4] & ~opf[3] & opf[2] & ~opf[1];
assign opf_log_ornot2 = opf[4] & ~opf[3] & opf[2] & opf[1];
assign opf_log_src2 = opf[4] & opf[3] & ~opf[2] & ~opf[1];
assign opf_log_ornot1 = opf[4] & opf[3] & ~opf[2] & opf[1];
assign opf_log_or = opf[4] & opf[3] & opf[2] & ~opf[1];
assign opf_log_one = opf[4] & opf[3] & opf[2] & opf[1];
// selects for logic mux
assign ctl_vis_log_sel_nand = opf_log_or | opf_log_nand | opf_log_ornot1 | opf_log_ornot2;
assign ctl_vis_log_sel_xor = opf_log_xor | opf_log_xnor;
assign ctl_vis_log_sel_nor = opf_log_and | opf_log_nor | opf_log_andnot1 | opf_log_andnot2;
assign ctl_vis_log_sel_pass = (opf_log_zero | opf_log_one | opf_log_src1 | opf_log_src2 |
opf_log_not1 | opf_log_not2);
assign invert_rs1_next = (opf_log_not1 | opf_log_or | opf_log_and |
opf_log_ornot2 | opf_log_andnot2);
assign invert_rs2_next = (opf_log_not2 | opf_log_or | opf_log_and |
opf_log_ornot1 | opf_log_andnot1 | opf_log_xnor);
dff_s invert_rs1_dff(.din(invert_rs1_next), .clk(clk), .q(ctl_vis_log_invert_rs1),
.se(se), .si(), .so());
dff_s invert_rs2_dff(.din(invert_rs2_next), .clk(clk), .q(ctl_vis_log_invert_rs2),
.se(se), .si(), .so());
// precalculate to help timing
assign log_pass_rs1_next = opf_log_src1 | opf_log_not1;
assign log_pass_rs2_next = opf_log_src2 | opf_log_not2;
dff_s #(2) log_pass_dff(.din({log_pass_rs1_next,log_pass_rs2_next}), .clk(clk),
.q({log_pass_rs1,log_pass_rs2}), .se(se), .si(), .so());
assign ctl_vis_log_pass_rs1 = log_pass_rs1;
assign ctl_vis_log_pass_rs2 = log_pass_rs2 & ~log_pass_rs1;
assign ctl_vis_log_constant = opf_log_one;
assign ctl_vis_log_pass_const = ~(ctl_vis_log_pass_rs1 | ctl_vis_log_pass_rs2);
// controls for falign
assign ctl_vis_align0 = ~gsr_align_d1[2] & ~gsr_align_d1[1];
assign ctl_vis_align2 = ~gsr_align_d1[2] & gsr_align_d1[1];
assign ctl_vis_align4 = gsr_align_d1[2] & ~gsr_align_d1[1];
assign ctl_vis_align6 = gsr_align_d1[2] & gsr_align_d1[1];
assign ctl_vis_align_odd = gsr_align_d1[0];
// controls for output mux
assign ctl_vis_sel_add = add;
assign ctl_vis_sel_align = align;
assign ctl_vis_sel_log = ~(add | align);
///////////////////////////////////////////////////////////
// GSR.alignaddr_offset, GSR.IM, GSR.IRND
///////////////////////////////////////////////////////////
mux4ds #(6) curr_gsr_mux(.dout({gsr_rnd[2:0], gsr_align[2:0]}),
.in0({t0_gsr_rnd[2:0], t0_gsr_align[2:0]}),
.in1({t1_gsr_rnd[2:0], t1_gsr_align[2:0]}),
.in2({t2_gsr_rnd[2:0], t2_gsr_align[2:0]}),
.in3({t3_gsr_rnd[2:0], t3_gsr_align[2:0]}),
.sel0(thr_fp[0]),
.sel1(thr_fp[1]),
.sel2(thr_fp[2]),
.sel3(thr_fp[3]));
mux4ds #(6) gsr_e_mux(.dout({gsr_rnd_e[2:0], gsr_align_e[2:0]}),
.in0({t0_gsr_rnd[2:0], t0_gsr_align[2:0]}),
.in1({t1_gsr_rnd[2:0], t1_gsr_align[2:0]}),
.in2({t2_gsr_rnd[2:0], t2_gsr_align[2:0]}),
.in3({t3_gsr_rnd[2:0], t3_gsr_align[2:0]}),
.sel0(ctl_dp_thr_e[0]),
.sel1(ctl_dp_thr_e[1]),
.sel2(ctl_dp_thr_e[2]),
.sel3(ctl_dp_thr_e[3]));
dff_s #(43) gsr_e2m(.din({dp_ctl_gsr_mask_e[31:0],gsr_rnd_e[2:0],
dp_ctl_gsr_scale_e[4:0],gsr_align_e[2:0]}), .clk(clk),
.q({ffu_exu_rsr_data_hi_m[31:0],ffu_exu_rsr_data_mid_m[2:0], ffu_exu_rsr_data_lo_m[7:0]}),
.se(se), .si(), .so());
dff_s #(3) gsr_align_dff(.din(gsr_align[2:0]), .clk(clk), .q(gsr_align_d1[2:0]), .se(se), .si(), .so());
// put in to help timing for sending to lsu
dff_s #(2) fpu_rnd_dff(.din(fpu_rnd_next[1:0]), .clk(clk), .q(fpu_rnd[1:0]), .si(), .so(), .se(se));
assign fpu_rnd_next[1:0] = (gsr_rnd[2])? gsr_rnd[1:0]: dp_ctl_fsr_rnd[1:0];
// if alignaddress_little then write the 2's complement
assign align_addr_data_w2[2:0] = (opf[1])? (~wgsr_align_offset_w2[2:0] + 3'b001):
wgsr_align_offset_w2[2:0];
assign gsr_addr_d = (ifu_tlu_sraddr_d[6:0] == 7'b0010011);
assign wgsr_e = exu_ffu_wsr_inst_e & gsr_addr_e;
dff_s gsr_addr_d2e(.din(gsr_addr_d), .clk(clk), .q(gsr_addr_e), .se(se), .si(), .so());
// need independent kill checks because this isn't killed by new fpop
assign wgsr_vld_m = wgsr_m & ~(thr_match_mw2 & flush_w2);
assign wgsr_vld_w = wgsr_w & ifu_tlu_inst_vld_w & ~(thr_match_ww2 & flush_w2);
assign wgsr_vld_w2 = wgsr_w2 & ~flush_w2;
dff_s wgsr_e2m(.din(wgsr_e), .clk(clk), .q(wgsr_m), .si(), .so(), .se(se));
dff_s wgsr_m2w(.din(wgsr_vld_m), .clk(clk), .q(wgsr_w), .si(), .so(), .se(se));
dff_s wgsr_w2w2(.din(wgsr_vld_w), .clk(clk), .q(wgsr_w2), .si(), .so(), .se(se));
assign thr_w2[3] = (tid_w2[1:0] == 2'b11);
assign thr_w2[2] = (tid_w2[1:0] == 2'b10);
assign thr_w2[1] = (tid_w2[1:0] == 2'b01);
assign thr_w2[0] = (tid_w2[1:0] == 2'b00);
assign ctl_dp_thr_e[3] = (tid_e[1:0] == 2'b11);
assign ctl_dp_thr_e[2] = (tid_e[1:0] == 2'b10);
assign ctl_dp_thr_e[1] = (tid_e[1:0] == 2'b01);
assign ctl_dp_thr_e[0] = (tid_e[1:0] == 2'b00);
assign thr_fp[3] = (tid[1:0] == 2'b11);
assign thr_fp[2] = (tid[1:0] == 2'b10);
assign thr_fp[1] = (tid[1:0] == 2'b01);
assign thr_fp[0] = (tid[1:0] == 2'b00);
assign t0_siam_w2 = thr_fp[0] & siam & visop_w2_vld;
assign t0_gsr_wsr_w2 = thr_w2[0] & wgsr_vld_w2;
assign t0_alignaddr_w2 = thr_fp[0] & alignaddr & visop_w2_vld;
assign t0_rnd_wen_l = ~(t0_gsr_wsr_w2 | t0_siam_w2);
assign t0_align_wen_l = ~(t0_gsr_wsr_w2 | t0_alignaddr_w2);
assign t1_siam_w2 = thr_fp[1] & siam & visop_w2_vld;
assign t1_gsr_wsr_w2 = thr_w2[1] & wgsr_vld_w2;
assign t1_alignaddr_w2 = thr_fp[1] & alignaddr & visop_w2_vld;
assign t1_rnd_wen_l = ~(t1_gsr_wsr_w2 | t1_siam_w2);
assign t1_align_wen_l = ~(t1_gsr_wsr_w2 | t1_alignaddr_w2);
assign t2_siam_w2 = thr_fp[2] & siam & visop_w2_vld;
assign t2_gsr_wsr_w2 = thr_w2[2] & wgsr_vld_w2;
assign t2_alignaddr_w2 = thr_fp[2] & alignaddr & visop_w2_vld;
assign t2_rnd_wen_l = ~(t2_gsr_wsr_w2 | t2_siam_w2);
assign t2_align_wen_l = ~(t2_gsr_wsr_w2 | t2_alignaddr_w2);
assign t3_siam_w2 = thr_fp[3] & siam & visop_w2_vld;
assign t3_gsr_wsr_w2 = thr_w2[3] & wgsr_vld_w2;
assign t3_alignaddr_w2 = thr_fp[3] & alignaddr & visop_w2_vld;
assign t3_rnd_wen_l = ~(t3_gsr_wsr_w2 | t3_siam_w2);
assign t3_align_wen_l = ~(t3_gsr_wsr_w2 | t3_alignaddr_w2);
assign ctl_dp_gsr_wsr_w2[3:0] = {t3_gsr_wsr_w2,t2_gsr_wsr_w2,t1_gsr_wsr_w2,t0_gsr_wsr_w2};
// Storage flops and muxes
mux3ds #(3) t0_rnd_mux(.dout(t0_gsr_rnd_next[2:0]),
.in0(t0_gsr_rnd[2:0]),
.in1(wgsr_rnd_w2[2:0]),
.in2(siam_rnd[2:0]),
.sel0(t0_rnd_wen_l),
.sel1(t0_gsr_wsr_w2),
.sel2(t0_siam_w2));
mux3ds #(3) t0_align_mux(.dout(t0_gsr_align_next[2:0]),
.in0(t0_gsr_align[2:0]),
.in1(wgsr_align_offset_w2[2:0]),
.in2(align_addr_data_w2[2:0]),
.sel0(t0_align_wen_l),
.sel1(t0_gsr_wsr_w2),
.sel2(t0_alignaddr_w2));
mux3ds #(3) t1_rnd_mux(.dout(t1_gsr_rnd_next[2:0]),
.in0(t1_gsr_rnd[2:0]),
.in1(wgsr_rnd_w2[2:0]),
.in2(siam_rnd[2:0]),
.sel0(t1_rnd_wen_l),
.sel1(t1_gsr_wsr_w2),
.sel2(t1_siam_w2));
mux3ds #(3) t1_align_mux(.dout(t1_gsr_align_next[2:0]),
.in0(t1_gsr_align[2:0]),
.in1(wgsr_align_offset_w2[2:0]),
.in2(align_addr_data_w2[2:0]),
.sel0(t1_align_wen_l),
.sel1(t1_gsr_wsr_w2),
.sel2(t1_alignaddr_w2));
mux3ds #(3) t2_rnd_mux(.dout(t2_gsr_rnd_next[2:0]),
.in0(t2_gsr_rnd[2:0]),
.in1(wgsr_rnd_w2[2:0]),
.in2(siam_rnd[2:0]),
.sel0(t2_rnd_wen_l),
.sel1(t2_gsr_wsr_w2),
.sel2(t2_siam_w2));
mux3ds #(3) t2_align_mux(.dout(t2_gsr_align_next[2:0]),
.in0(t2_gsr_align[2:0]),
.in1(wgsr_align_offset_w2[2:0]),
.in2(align_addr_data_w2[2:0]),
.sel0(t2_align_wen_l),
.sel1(t2_gsr_wsr_w2),
.sel2(t2_alignaddr_w2));
mux3ds #(3) t3_rnd_mux(.dout(t3_gsr_rnd_next[2:0]),
.in0(t3_gsr_rnd[2:0]),
.in1(wgsr_rnd_w2[2:0]),
.in2(siam_rnd[2:0]),
.sel0(t3_rnd_wen_l),
.sel1(t3_gsr_wsr_w2),
.sel2(t3_siam_w2));
mux3ds #(3) t3_align_mux(.dout(t3_gsr_align_next[2:0]),
.in0(t3_gsr_align[2:0]),
.in1(wgsr_align_offset_w2[2:0]),
.in2(align_addr_data_w2[2:0]),
.sel0(t3_align_wen_l),
.sel1(t3_gsr_wsr_w2),
.sel2(t3_alignaddr_w2));
dffr_s #(6) t0_gsr_dff(.din({t0_gsr_rnd_next[2:0], t0_gsr_align_next[2:0]}), .clk(clk),
.q({t0_gsr_rnd[2:0], t0_gsr_align[2:0]}), .se(se),
.si(), .so(), .rst(reset));
dffr_s #(6) t1_gsr_dff(.din({t1_gsr_rnd_next[2:0], t1_gsr_align_next[2:0]}), .clk(clk),
.q({t1_gsr_rnd[2:0], t1_gsr_align[2:0]}), .se(se),
.si(), .so(), .rst(reset));
dffr_s #(6) t2_gsr_dff(.din({t2_gsr_rnd_next[2:0], t2_gsr_align_next[2:0]}), .clk(clk),
.q({t2_gsr_rnd[2:0], t2_gsr_align[2:0]}), .se(se),
.si(), .so(), .rst(reset));
dffr_s #(6) t3_gsr_dff(.din({t3_gsr_rnd_next[2:0], t3_gsr_align_next[2:0]}), .clk(clk),
.q({t3_gsr_rnd[2:0], t3_gsr_align[2:0]}), .se(se),
.si(), .so(), .rst(reset));
dffre_s #(3) siam_rnd_dff(.din(ifu_ffu_rnd_e[2:0]), .clk(clk),
.q(siam_rnd), .se(se), .si(), .so(),
.rst(reset), .en(visop_e));
dff_s #(3) align_offset_dff1(.din(exu_ffu_gsr_align_m[2:0]), .clk(clk),
.q(wgsr_align_offset_w[2:0]), .se(se), .si(), .so());
dff_s #(3) align_offset_dff2(.din(wgsr_align_offset_w[2:0]), .clk(clk),
.q(wgsr_align_offset_w2[2:0]), .se(se), .si(), .so());
dff_s #(3) rnd_dff1(.din(exu_ffu_gsr_rnd_m[2:0]), .clk(clk),
.q(wgsr_rnd_w[2:0]), .se(se), .si(), .so());
dff_s #(3) rnd_dff2(.din(wgsr_rnd_w[2:0]), .clk(clk),
.q(wgsr_rnd_w2[2:0]), .se(se), .si(), .so());
assign wsr_data_m[36:0] = {exu_ffu_gsr_mask_m[31:0], exu_ffu_gsr_scale_m[4:0]};
dff_s #(37) wsr_data_m2w(.din(wsr_data_m[36:0]), .clk(clk), .q(wsr_data_w[36:0]),
.se(se), .si(), .so());
dff_s #(37) wsr_data_w2w2(.din(wsr_data_w[36:0]), .clk(clk), .q(ctl_dp_wsr_data_w2[36:0]),
.se(se), .si(), .so());
endmodule // sparc_ffu_ctl_visctl
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pll_100_250.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 175 10/25/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_pll_100_250 (
areset,
inclk0,
c0);
input areset;
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire2 = 1'h0;
wire [0:0] sub_wire4 = 1'h1;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire [5:0] sub_wire3 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire4};
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire2, sub_wire5};
wire [3:0] sub_wire7 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2};
altpll altpll_component (
.clkena (sub_wire3),
.inclk (sub_wire6),
.extclkena (sub_wire7),
.areset (areset),
.clk (sub_wire0)
// synopsys translate_off
,
.scanclk (),
.pllena (),
.sclkout1 (),
.sclkout0 (),
.fbin (),
.scandone (),
.clkloss (),
.extclk (),
.clkswitch (),
.pfdena (),
.scanaclr (),
.clkbad (),
.scandata (),
.enable1 (),
.scandataout (),
.enable0 (),
.scanwrite (),
.locked (),
.activeclock (),
.scanread ()
// synopsys translate_on
);
defparam
altpll_component.bandwidth = 500000,
altpll_component.bandwidth_type = "CUSTOM",
altpll_component.clk0_divide_by = 2,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 5,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Stratix GX",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "ENHANCED",
altpll_component.spread_frequency = 0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "250.000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_wave*.jpg FALSE FALSE
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL_100M.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.2 Build 222 07/20/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module PLL_100M (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 10,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 100000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=PLL_100M",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "10.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL_100M.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "100000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_100M_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
module adder_tb;
parameter N_BITS_A = 3;
parameter BIN_PT_A = 1;
parameter SIGNED_A = 1;
parameter N_BITS_B = 4;
parameter BIN_PT_B = 3;
parameter SIGNED_B = 0;
parameter N_BITS_OUT = 6;
parameter BIN_PT_OUT = 3;
reg [N_BITS_A-1:0] a;
reg [N_BITS_B-1:0] b;
wire [N_BITS_OUT-1:0] sum;
initial begin
a = 3'b0_0_0; // 0
b = 4'b0_001; // + 1/8
// 1/8
#10
a = 3'b1_1_1; // -1/2
b = 4'b0_001; // + 1/8
// -3/8
#5
a = 3'b1_1_0; // -1
b = 4'b0_100; // + 1/2
// -1/2
#5
a = 3'b0_0_1; // 1/2
b = 4'b1_000; // + 1
// 3/2
#10 ;
$finish;
end //initial
adder #(.N_BITS_A(N_BITS_A),
.BIN_PT_A(BIN_PT_A),
.SIGNED_A(SIGNED_A),
.N_BITS_B(N_BITS_B),
.BIN_PT_B(BIN_PT_B),
.SIGNED_B(SIGNED_B),
.N_BITS_OUT(N_BITS_OUT),
.BIN_PT_OUT(BIN_PT_OUT)) a0 (a, b, sum);
initial begin
$monitor("%t, a = \t(%d,%d)b'%b\t a_padded = \t(%d,%d)b'%b\n%t, b = \t(%d,%d)b'%b\t b_padded = \t(%d,%d)b'%b\n%t, sum = \t\t\t\t\t(%d,%d)b'%b", $time, N_BITS_A, BIN_PT_A, a, N_BITS_OUT, BIN_PT_OUT, a0.add0.a_padded, $time, N_BITS_B, BIN_PT_B, b, N_BITS_OUT, BIN_PT_OUT, a0.add0.b_padded, $time, N_BITS_OUT, BIN_PT_OUT, sum);
end
endmodule //add_tb
|
// megafunction wizard: %Triple-Speed Ethernet v14.0%
// GENERATION: XML
// mac_core.v
// Generated using ACDS version 14.0 200 at 2015.04.23.08:16:38
`timescale 1 ps / 1 ps
module mac_core (
input wire clk, // control_port_clock_connection.clk
input wire reset, // reset_connection.reset
input wire [7:0] reg_addr, // control_port.address
output wire [31:0] reg_data_out, // .readdata
input wire reg_rd, // .read
input wire [31:0] reg_data_in, // .writedata
input wire reg_wr, // .write
output wire reg_busy, // .waitrequest
input wire tx_clk, // pcs_mac_tx_clock_connection.clk
input wire rx_clk, // pcs_mac_rx_clock_connection.clk
input wire set_10, // mac_status_connection.set_10
input wire set_1000, // .set_1000
output wire eth_mode, // .eth_mode
output wire ena_10, // .ena_10
input wire [7:0] gm_rx_d, // mac_gmii_connection.gmii_rx_d
input wire gm_rx_dv, // .gmii_rx_dv
input wire gm_rx_err, // .gmii_rx_err
output wire [7:0] gm_tx_d, // .gmii_tx_d
output wire gm_tx_en, // .gmii_tx_en
output wire gm_tx_err, // .gmii_tx_err
input wire [3:0] m_rx_d, // mac_mii_connection.mii_rx_d
input wire m_rx_en, // .mii_rx_dv
input wire m_rx_err, // .mii_rx_err
output wire [3:0] m_tx_d, // .mii_tx_d
output wire m_tx_en, // .mii_tx_en
output wire m_tx_err, // .mii_tx_err
input wire m_rx_crs, // .mii_crs
input wire m_rx_col, // .mii_col
input wire ff_rx_clk, // receive_clock_connection.clk
input wire ff_tx_clk, // transmit_clock_connection.clk
output wire [31:0] ff_rx_data, // receive.data
output wire ff_rx_eop, // .endofpacket
output wire [5:0] rx_err, // .error
output wire [1:0] ff_rx_mod, // .empty
input wire ff_rx_rdy, // .ready
output wire ff_rx_sop, // .startofpacket
output wire ff_rx_dval, // .valid
input wire [31:0] ff_tx_data, // transmit.data
input wire ff_tx_eop, // .endofpacket
input wire ff_tx_err, // .error
input wire [1:0] ff_tx_mod, // .empty
output wire ff_tx_rdy, // .ready
input wire ff_tx_sop, // .startofpacket
input wire ff_tx_wren, // .valid
output wire magic_wakeup, // mac_misc_connection.magic_wakeup
input wire magic_sleep_n, // .magic_sleep_n
input wire ff_tx_crc_fwd, // .ff_tx_crc_fwd
output wire ff_tx_septy, // .ff_tx_septy
output wire tx_ff_uflow, // .tx_ff_uflow
output wire ff_tx_a_full, // .ff_tx_a_full
output wire ff_tx_a_empty, // .ff_tx_a_empty
output wire [17:0] rx_err_stat, // .rx_err_stat
output wire [3:0] rx_frm_type, // .rx_frm_type
output wire ff_rx_dsav, // .ff_rx_dsav
output wire ff_rx_a_full, // .ff_rx_a_full
output wire ff_rx_a_empty // .ff_rx_a_empty
);
mac_core_0002 mac_core_inst (
.clk (clk), // control_port_clock_connection.clk
.reset (reset), // reset_connection.reset
.reg_addr (reg_addr), // control_port.address
.reg_data_out (reg_data_out), // .readdata
.reg_rd (reg_rd), // .read
.reg_data_in (reg_data_in), // .writedata
.reg_wr (reg_wr), // .write
.reg_busy (reg_busy), // .waitrequest
.tx_clk (tx_clk), // pcs_mac_tx_clock_connection.clk
.rx_clk (rx_clk), // pcs_mac_rx_clock_connection.clk
.set_10 (set_10), // mac_status_connection.set_10
.set_1000 (set_1000), // .set_1000
.eth_mode (eth_mode), // .eth_mode
.ena_10 (ena_10), // .ena_10
.gm_rx_d (gm_rx_d), // mac_gmii_connection.gmii_rx_d
.gm_rx_dv (gm_rx_dv), // .gmii_rx_dv
.gm_rx_err (gm_rx_err), // .gmii_rx_err
.gm_tx_d (gm_tx_d), // .gmii_tx_d
.gm_tx_en (gm_tx_en), // .gmii_tx_en
.gm_tx_err (gm_tx_err), // .gmii_tx_err
.m_rx_d (m_rx_d), // mac_mii_connection.mii_rx_d
.m_rx_en (m_rx_en), // .mii_rx_dv
.m_rx_err (m_rx_err), // .mii_rx_err
.m_tx_d (m_tx_d), // .mii_tx_d
.m_tx_en (m_tx_en), // .mii_tx_en
.m_tx_err (m_tx_err), // .mii_tx_err
.m_rx_crs (m_rx_crs), // .mii_crs
.m_rx_col (m_rx_col), // .mii_col
.ff_rx_clk (ff_rx_clk), // receive_clock_connection.clk
.ff_tx_clk (ff_tx_clk), // transmit_clock_connection.clk
.ff_rx_data (ff_rx_data), // receive.data
.ff_rx_eop (ff_rx_eop), // .endofpacket
.rx_err (rx_err), // .error
.ff_rx_mod (ff_rx_mod), // .empty
.ff_rx_rdy (ff_rx_rdy), // .ready
.ff_rx_sop (ff_rx_sop), // .startofpacket
.ff_rx_dval (ff_rx_dval), // .valid
.ff_tx_data (ff_tx_data), // transmit.data
.ff_tx_eop (ff_tx_eop), // .endofpacket
.ff_tx_err (ff_tx_err), // .error
.ff_tx_mod (ff_tx_mod), // .empty
.ff_tx_rdy (ff_tx_rdy), // .ready
.ff_tx_sop (ff_tx_sop), // .startofpacket
.ff_tx_wren (ff_tx_wren), // .valid
.magic_wakeup (magic_wakeup), // mac_misc_connection.magic_wakeup
.magic_sleep_n (magic_sleep_n), // .magic_sleep_n
.ff_tx_crc_fwd (ff_tx_crc_fwd), // .ff_tx_crc_fwd
.ff_tx_septy (ff_tx_septy), // .ff_tx_septy
.tx_ff_uflow (tx_ff_uflow), // .tx_ff_uflow
.ff_tx_a_full (ff_tx_a_full), // .ff_tx_a_full
.ff_tx_a_empty (ff_tx_a_empty), // .ff_tx_a_empty
.rx_err_stat (rx_err_stat), // .rx_err_stat
.rx_frm_type (rx_frm_type), // .rx_frm_type
.ff_rx_dsav (ff_rx_dsav), // .ff_rx_dsav
.ff_rx_a_full (ff_rx_a_full), // .ff_rx_a_full
.ff_rx_a_empty (ff_rx_a_empty) // .ff_rx_a_empty
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2015 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_eth_tse" version="14.0" >
// Retrieval info: <generic name="deviceFamilyName" value="Stratix IV" />
// Retrieval info: <generic name="core_variation" value="MAC_ONLY" />
// Retrieval info: <generic name="ifGMII" value="MII_GMII" />
// Retrieval info: <generic name="enable_use_internal_fifo" value="true" />
// Retrieval info: <generic name="enable_ecc" value="false" />
// Retrieval info: <generic name="max_channels" value="1" />
// Retrieval info: <generic name="use_misc_ports" value="true" />
// Retrieval info: <generic name="transceiver_type" value="NONE" />
// Retrieval info: <generic name="enable_hd_logic" value="true" />
// Retrieval info: <generic name="enable_gmii_loopback" value="false" />
// Retrieval info: <generic name="enable_sup_addr" value="false" />
// Retrieval info: <generic name="stat_cnt_ena" value="true" />
// Retrieval info: <generic name="ext_stat_cnt_ena" value="false" />
// Retrieval info: <generic name="ena_hash" value="false" />
// Retrieval info: <generic name="enable_shift16" value="true" />
// Retrieval info: <generic name="enable_mac_flow_ctrl" value="false" />
// Retrieval info: <generic name="enable_mac_vlan" value="false" />
// Retrieval info: <generic name="enable_magic_detect" value="true" />
// Retrieval info: <generic name="useMDIO" value="false" />
// Retrieval info: <generic name="mdio_clk_div" value="40" />
// Retrieval info: <generic name="enable_ena" value="32" />
// Retrieval info: <generic name="eg_addr" value="11" />
// Retrieval info: <generic name="ing_addr" value="11" />
// Retrieval info: <generic name="phy_identifier" value="0" />
// Retrieval info: <generic name="enable_sgmii" value="false" />
// Retrieval info: <generic name="export_pwrdn" value="false" />
// Retrieval info: <generic name="enable_alt_reconfig" value="false" />
// Retrieval info: <generic name="starting_channel_number" value="0" />
// Retrieval info: <generic name="phyip_pll_type" value="CMU" />
// Retrieval info: <generic name="phyip_pll_base_data_rate" value="1250 Mbps" />
// Retrieval info: <generic name="phyip_en_synce_support" value="false" />
// Retrieval info: <generic name="phyip_pma_bonding_mode" value="x1" />
// Retrieval info: <generic name="nf_phyip_rcfg_enable" value="false" />
// Retrieval info: <generic name="enable_timestamping" value="false" />
// Retrieval info: <generic name="enable_ptp_1step" value="false" />
// Retrieval info: <generic name="tstamp_fp_width" value="4" />
// Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
// Retrieval info: </instance>
// IPFS_FILES : mac_core.vo
// RELATED_FILES: mac_core.v, mac_core_0002.v, altera_eth_tse_mac.v, altera_tse_clk_cntl.v, altera_tse_crc328checker.v, altera_tse_crc328generator.v, altera_tse_crc32ctl8.v, altera_tse_crc32galois8.v, altera_tse_gmii_io.v, altera_tse_lb_read_cntl.v, altera_tse_lb_wrt_cntl.v, altera_tse_hashing.v, altera_tse_host_control.v, altera_tse_host_control_small.v, altera_tse_mac_control.v, altera_tse_register_map.v, altera_tse_register_map_small.v, altera_tse_rx_counter_cntl.v, altera_tse_shared_mac_control.v, altera_tse_shared_register_map.v, altera_tse_tx_counter_cntl.v, altera_tse_lfsr_10.v, altera_tse_loopback_ff.v, altera_tse_altshifttaps.v, altera_tse_fifoless_mac_rx.v, altera_tse_mac_rx.v, altera_tse_fifoless_mac_tx.v, altera_tse_mac_tx.v, altera_tse_magic_detection.v, altera_tse_mdio.v, altera_tse_mdio_clk_gen.v, altera_tse_mdio_cntl.v, altera_tse_top_mdio.v, altera_tse_mii_rx_if.v, altera_tse_mii_tx_if.v, altera_tse_pipeline_base.v, altera_tse_pipeline_stage.sv, altera_tse_dpram_16x32.v, altera_tse_dpram_8x32.v, altera_tse_dpram_ecc_16x32.v, altera_tse_quad_16x32.v, altera_tse_quad_8x32.v, altera_tse_fifoless_retransmit_cntl.v, altera_tse_retransmit_cntl.v, altera_tse_rgmii_in1.v, altera_tse_rgmii_in4.v, altera_tse_nf_rgmii_module.v, altera_tse_rgmii_module.v, altera_tse_rgmii_out1.v, altera_tse_rgmii_out4.v, altera_tse_rx_ff.v, altera_tse_rx_min_ff.v, altera_tse_rx_ff_cntrl.v, altera_tse_rx_ff_cntrl_32.v, altera_tse_rx_ff_cntrl_32_shift16.v, altera_tse_rx_ff_length.v, altera_tse_rx_stat_extract.v, altera_tse_timing_adapter32.v, altera_tse_timing_adapter8.v, altera_tse_timing_adapter_fifo32.v, altera_tse_timing_adapter_fifo8.v, altera_tse_top_1geth.v, altera_tse_top_fifoless_1geth.v, altera_tse_top_w_fifo.v, altera_tse_top_w_fifo_10_100_1000.v, altera_tse_top_wo_fifo.v, altera_tse_top_wo_fifo_10_100_1000.v, altera_tse_top_gen_host.v, altera_tse_tx_ff.v, altera_tse_tx_min_ff.v, altera_tse_tx_ff_cntrl.v, altera_tse_tx_ff_cntrl_32.v, altera_tse_tx_ff_cntrl_32_shift16.v, altera_tse_tx_ff_length.v, altera_tse_tx_ff_read_cntl.v, altera_tse_tx_stat_extract.v, altera_tse_false_path_marker.v, altera_tse_reset_synchronizer.v, altera_tse_clock_crosser.v, altera_tse_a_fifo_13.v, altera_tse_a_fifo_24.v, altera_tse_a_fifo_34.v, altera_tse_a_fifo_opt_1246.v, altera_tse_a_fifo_opt_14_44.v, altera_tse_a_fifo_opt_36_10.v, altera_tse_gray_cnt.v, altera_tse_sdpm_altsyncram.v, altera_tse_altsyncram_dpm_fifo.v, altera_tse_bin_cnt.v, altera_tse_ph_calculator.sv, altera_tse_sdpm_gen.v, altera_tse_dc_fifo.v, altera_tse_ecc_dec_x10.v, altera_tse_ecc_enc_x10.v, altera_tse_ecc_enc_x10_wrapper.v, altera_tse_ecc_dec_x14.v, altera_tse_ecc_enc_x14.v, altera_tse_ecc_enc_x14_wrapper.v, altera_tse_ecc_dec_x2.v, altera_tse_ecc_enc_x2.v, altera_tse_ecc_enc_x2_wrapper.v, altera_tse_ecc_dec_x23.v, altera_tse_ecc_enc_x23.v, altera_tse_ecc_enc_x23_wrapper.v, altera_tse_ecc_dec_x36.v, altera_tse_ecc_enc_x36.v, altera_tse_ecc_enc_x36_wrapper.v, altera_tse_ecc_dec_x40.v, altera_tse_ecc_enc_x40.v, altera_tse_ecc_enc_x40_wrapper.v, altera_tse_ecc_dec_x30.v, altera_tse_ecc_enc_x30.v, altera_tse_ecc_enc_x30_wrapper.v, altera_tse_ecc_status_crosser.v
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__AND4B_PP_SYMBOL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4B_PP_SYMBOL_V
|
`default_nettype none
module pulse_gen(
input clk, // 12 MHz base clock
input RS232_Rx, // Receive pin for the FTDI chip
input resetn, // Reset the cycle
output RS232_Tx, // Transmit pin for the FTDI chip
output Pulse, // Output pin for the switch
output Sync, // Output pin for the SYNC pulse
// output FM, // Output pin for the FM pulse
output P2
// output P3,
// output P4,
// output J1_4,
// output J1_5,
// output J1_6,
// output J1_7,
// output J1_8,
// output J1_9,
// output J1_10,
// output J4_3,
// output J4_4,
// output J4_5,
// output J4_6,
// output J4_7,
// output J4_8,
// output J4_9
);
wire [31:0] period;
wire [15:0] p1width;
wire [15:0] delay;
wire [15:0] p2width;
wire [15:0] nut_del;
wire [7:0] nut_wid;
wire block;
wire [7:0] pulse_block;
wire [15:0] pulse_block_off;
wire [7:0] cpmg;
wire rx_done;
// wire [6:0] pre_att;
// wire [6:0] post_att;
// NOSIM_START
wire clk_pll;
wire clk_pll_gl;
wire lock;
// Setting the PLL to output a 201 MHz clock, based on code from
// https://gist.github.com/thoughtpolice/8ec923e1b3fc4bb12c11aa23b4dc53b5#file-ice40-v
// Note: These values are slightly different from those outputted by icepll
pll ecppll(
.clock_in(clk),
.clock_out(clk_pll),
.locked(lock)
);
// Setting up communications with LabView over USB
pulse_control control(
.clk(clk),
.RS232_Rx(RS232_Rx),
.RS232_Tx(RS232_Tx),
.per(period),
.p1wid(p1width),
.del(delay),
.p2wid(p2width),
.nut_d(nut_del),
.nut_w(nut_wid),
// .pr_att(pre_att),
// .po_att(post_att),
.cp(cpmg),
.p_bl(pulse_block),
.p_bl_off(pulse_block_off),
.bl(block),
.rxd(rx_done)
);
// NOSIM_END
// Generating the necessary pulses
pulses pulses(
.clk(clk),
.clk_pll(clk_pll),
.reset(resetn),
.per(period),
.p1wid(p1width),
.del(delay),
.p2wid(p2width),
.nut_d(nut_del),
.nut_w(nut_wid),
// .pr_att(pre_att),
// .po_att(post_att),
.cp(cpmg),
.p_bl(pulse_block),
.p_bl_off(pulse_block_off),
.bl(block),
.rxd(rx_done),
.sync_on(Sync),
.pulse_on(Pulse),
// .Att1({J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10}),
// .Att3({J4_9, J4_8, J4_7, J4_6, J4_5, J4_4, J4_3}),
.inhib(P2)
// .test({FM, P3, P4})
);
// NOSIM2_START
endmodule // pulse_gen
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:26:54 PM
// Design Name:
// Module Name: shift_mux_array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
localparam integer lvl = 2**(LEVEL);
localparam integer x = (SWR - 1);
generate for (j=0; j<=SWR-1 ; j=j+1) begin : MUX_ODDNORM
localparam integer sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level
case ((lvl+j)>(x))
1'b1: begin :BSHITMUX
//assign mux_out = (sel) ? din_1 : din_0;
assign Data_o[j] = (select_i) ? bit_shift_i : Data_i[j];
end
1'b0: begin : FSHITMUX
assign Data_o[j] = (select_i) ? Data_i[lvl+j] : Data_i[j];
end
endcase
end
endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cmp_pcxandcpx.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cmp_pcxandcpx (/*AUTOARG*/
// Inputs
clk, rst_l, spc_pcx_req_pq, spc_pcx_data_pa, cpx_spc_data_cx, cpu
);
input clk;
input rst_l;
//siganls
input [4:0] spc_pcx_req_pq;
input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
input [`CPX_WIDTH-1:0] cpx_spc_data_cx;
input [31:0] cpu;
reg [127:0] pcx;
reg spc_pcx_req_pq_vld;
always @(posedge clk)begin
// victorm 08/11/03
spc_pcx_req_pq_vld <= #1 |spc_pcx_req_pq[4:0];
if(spc_pcx_data_pa[`PCX_VLD] &&
(`PC_CMP.finish_mask != `PC_CMP.good) &&
(`MONITOR.bad == 0)) begin
case(spc_pcx_data_pa[`PCX_RQ_HI:`PCX_RQ_LO])
`LOAD_RQ : pcx = "LOAD_RQ";
`IMISS_RQ : pcx = "IMISS_RQ";
`STORE_RQ : pcx = "STORE_RQ";
`CAS1_RQ : pcx = "CAS1_RQ";
`CAS2_RQ : pcx = "CAS2_RQ";
`SWAP_RQ : pcx = "SWAP_RQ";
`STRLOAD_RQ: pcx = "STRLOAD_RQ";
`STRST_RQ : pcx = "STRST_RQ";
`STQ_RQ : pcx = "STQ_RQ";
`INT_RQ : pcx = "INT_RQ";
`FWD_RQ : pcx = "FWD_RQ";
`FWD_RPY : pcx = "FWD_RPY";
`RSVD_RQ : pcx = "RSVD_RQ";
5'b01010 : pcx = "FPOP1";
5'b01011 : pcx = "FPOP2";
endcase
if(spc_pcx_req_pq_vld)
$display("%0d:Info cpu(%x) pcx %0s packet received -> %b", $time, cpu[2:0], pcx, spc_pcx_data_pa);
end
if(cpx_spc_data_cx[`CPX_VLD] &&
//(`PC_CMP.finish_mask != `PC_CMP.good) &&
(`MONITOR.bad == 0))begin
case(cpx_spc_data_cx[`CPX_RQ_HI:`CPX_RQ_LO])
`LOAD_RET : pcx = "LOAD_RET";
`IFILL_RET: pcx = "IFILL_RET";
`INV_RET : pcx = "INV_RET";
`ST_ACK : pcx = "ST_ACK";
`AT_ACK : pcx = "AT_ACK";
`INT_RET : begin
pcx = "INT_RET";
if(cpx_spc_data_cx[17:16] == 3)begin
if(`PC_CMP.active_thread[cpx_spc_data_cx[12:8]])begin
`PC_CMP.back_thread[cpx_spc_data_cx[12:8]]=1;
end
end
if(cpx_spc_data_cx[17:16] != 1)begin
$display("%0d:Info cpu(%x) thread(%x) received interrupt vector -> %x Also, active_thread->%x", $time,
cpx_spc_data_cx[12:10], cpx_spc_data_cx[9:8], cpx_spc_data_cx[5:0], `PC_CMP.active_thread);
end
else if(cpx_spc_data_cx[17:16] == 1)begin
if(`PC_CMP.active_thread[cpx_spc_data_cx[12:8]])`PC_CMP.back_thread[cpx_spc_data_cx[12:8]]=1;
`PC_CMP.active_thread[cpx_spc_data_cx[12:8]] = 1'b1;
$display("%0d:Info cpu(%x) thread(%x) received interrupt vector -> %x Also, active_thread->%x", $time,
cpx_spc_data_cx[12:10], cpx_spc_data_cx[9:8], cpx_spc_data_cx[5:0], `PC_CMP.active_thread);
end
end
`TEST_RET : pcx = "TEST_RET";
`FP_RET : pcx = "FP_RET";
`EVICT_REQ: pcx = "EVICT_REQ";
`ERR_RET : pcx = "ERR_RET";
`STRLOAD_RET : pcx = "STRLOAD_RET";
`STRST_ACK: pcx = "STRST_ACK";
`FWD_RQ_RET:pcx = "FWD_RQ_RET";
`FWD_RPY_RET:pcx= "FWD_RPY_RET";
`RSVD_RET : pcx = "RSVD_RET";
endcase
$display("%0d:Info cpu(%x) cpx %0s packet received -> %b", $time, cpu[2:0], pcx, cpx_spc_data_cx);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_SYMBOL_V
`define SKY130_FD_SC_HDLL__NOR3_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_SYMBOL_V
|
/**
* Generic ROM memory
*
* (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
* GPL license
*
* Memory with the next parameters:
* - AW: Number of bits for directions
* - DW: Number of bits for data
* - ROMFILE: File to be used to load the memory
*/
module genrom #( // Parameters
parameter AW = 4, // Address width in bits
parameter DW = 8, // Data witdh in bits
parameter EXTRA = 4
)
( // Ports
input clk, // Global clock signal
input wire [ AW :0] addr, // Address
input wire [ EXTRA-1:0] extra, // Length of data to be fetch
input wire [ AW :0] lower_bound,
input wire [ AW :0] upper_bound,
output reg [2**EXTRA*DW-1:0] data=0, // Output data
output reg error=0 // none / out of limits
);
// Parameter: name of the file with the ROM content
parameter ROMFILE = "prog.list";
// Calc the number of total positions of memory
localparam NPOS = 1 << (AW+1);
// Memory
reg [DW-1: 0] rom [0: NPOS-1];
// Read the memory
always @(posedge clk) begin
error <= addr < lower_bound || addr > upper_bound;
case (extra)
0: data <= rom[addr ];
1: data <= {rom[addr ], rom[addr+ 1]};
2: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2]};
3: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3]};
4: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4]};
5: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5]};
6: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6]};
7: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7]};
8: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8]};
9: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9]};
10: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10]};
11: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11]};
12: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12]};
13: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12], rom[addr+13]};
14: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12], rom[addr+13], rom[addr+14]};
15: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12], rom[addr+13], rom[addr+14], rom[addr+15]};
endcase
end
// Load in memory the `ROMFILE` file. Values must be given in hexadecimal
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
|
//=================================================================
//
// The following code was generated from Spiral FFT IP Core Generator.
// March 2016
//
// These were the inputs to the generator:
// DFT Size = 2048
// direction = forward
// data type = 12 bit fixed point, scaled
// architecture = iterative reuse
// radix = 2
// streaming width = 2
// data ordering = natural input / natural output
// BRAM budget = 1000
// patented
//
//=================================================================
/*
* This source file contains a Verilog description of an IP core
* automatically generated by the SPIRAL HDL Generator.
*
* This product includes a hardware design developed by Carnegie Mellon University.
*
* Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project,
* Carnegie Mellon University
*
* For more information, see the SPIRAL project website at:
* http://www.spiral.net
*
* This design is provided for internal, non-commercial research use only
* and is not for redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
/* Portions of this design are protected by US Patent no. 8,321,823
* (assignee: Carnegie Mellon University).
*/
// Input/output stream: 2 complex words per cycle
// Throughput: one transform every 11287 cycles
// Latency: 12267 cycles
// Resources required:
// 4 multipliers (12 x 12 bit)
// 1 adders (11 x 11 bit)
// 6 adders (12 x 12 bit)
// 4 RAMs (2048 words, 24 bits per word)
// 2 ROMs (2048 words, 12 bits per word)
// Generated on Thu Mar 03 03:29:02 EST 2016
// Latency: 12267 clock cycles
// Throughput: 1 transform every 11287 cycles
// We use an interleaved complex data format. X0 represents the
// real portion of the first input, and X1 represents the imaginary
// portion. The X variables are system inputs and the Y variables
// are system outputs.
// The design uses a system of flag signals to indicate the
// beginning of the input and output data streams. The 'next'
// input (asserted high), is used to instruct the system that the
// input stream will begin on the following cycle.
// This system has a 'gap' of 11287 cycles. This means that
// 11287 cycles must elapse between the beginning of the input
// vectors.
// The output signal 'next_out' (also asserted high) indicates
// that the output vector will begin streaming out of the system
// on the following cycle.
// The system has a latency of 12267 cycles. This means that
// the 'next_out' will be asserted 12267 cycles after the user
// asserts 'next'.
// The simple testbench below will demonstrate the timing for loading
// and unloading data vectors.
// The system reset signal is asserted high.
// Please note: when simulating floating point code, you must include
// Xilinx's DSP slice simulation module.
/*
module dft_testbench();
reg clk, reset, next;
wire next_out;
integer i, j, k, l, m;
reg [15:0] counter;
reg [11:0] in [3:0];
wire [11:0] X0;
wire [11:0] Y0;
wire [11:0] X1;
wire [11:0] Y1;
wire [11:0] X2;
wire [11:0] Y2;
wire [11:0] X3;
wire [11:0] Y3;
reg clrCnt;
assign X0 = in[0];
assign X1 = in[1];
assign X2 = in[2];
assign X3 = in[3];
initial clk = 0;
always #10000 clk = ~clk;
// Instantiate top-level module of core 'X' signals are system inputs
// and 'Y' signals are system outputs
dft_top dft_top_instance (.clk(clk), .reset(reset), .next(next), .next_out(next_out),
.X0(X0), .Y0(Y0),
.X1(X1), .Y1(Y1),
.X2(X2), .Y2(Y2),
.X3(X3), .Y3(Y3));
// You can use this counter to verify that the gap and latency are as expected.
always @(posedge clk) begin
if (clrCnt) counter <= 0;
else counter <= counter+1;
end
initial begin
@(posedge clk);
@(posedge clk);
// On the next cycle, begin loading input vector.
next <= 1;
clrCnt <= 1;
@(posedge clk);
clrCnt <= 0;
next <= 0;
// The 2048 complex data points enter the system over 1024 cycles
for (j=0; j < 1023; j = j+1) begin
// Input: 2 complex words per cycle
for (k=0; k < 4; k = k+1) begin
in[k] <= j*4 + k;
end
@(posedge clk);
end
j = 1023;
for (k=0; k < 4; k = k+1) begin
in[k] <= j*4 + k;
end
@(posedge clk);
// Wait until the next data vector can be entered
while (counter < 11285)
@(posedge clk);
// On the next cycle, we will start the next data vector
next <= 1;
clrCnt <= 1;
@(posedge clk);
clrCnt <= 0;
next <= 0;
// Start entering next input vector
for (j=0; j < 1023; j = j+1) begin
// Input 4 words per cycle
for (k=0; k < 4; k = k+1) begin
in[k] <= 4096 + j*4 + k;
end
@(posedge clk);
end
j = 1023;
for (k=0; k < 4; k = k+1) begin
in[k] <= 4096 + j*4 + k;
end
end
initial begin
// set initial values
in[0] <= 0;
in[1] <= 0;
in[2] <= 0;
in[3] <= 0;
next <= 0;
reset <= 0;
@(posedge clk);
reset <= 1;
@(posedge clk);
reset <= 0;
@(posedge clk);
@(posedge clk);
// Wait until next_out goes high, then wait one clock cycle and begin receiving data
@(posedge next_out);
@(posedge clk); #1;
$display("--- begin output 1---");
for (m=0; m < 1023; m=m+1) begin
$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
@(posedge clk); #1;
end
$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
// Wait until next_out goes high, then wait one clock cycle and begin receiving data
@(posedge next_out);
@(posedge clk); #1;
$display("--- begin output 2---");
for (m=0; m < 1023; m=m+1) begin
$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
@(posedge clk); #1;
end
$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
$finish;
end
endmodule
*/
// Latency: 12267
// Gap: 11287
// module_name_is:dft_top
module dft_top(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
wire [11:0] t0_0;
wire [11:0] t0_1;
wire [11:0] t0_2;
wire [11:0] t0_3;
wire next_0;
wire [11:0] t1_0;
wire [11:0] t1_1;
wire [11:0] t1_2;
wire [11:0] t1_3;
wire next_1;
wire [11:0] t2_0;
wire [11:0] t2_1;
wire [11:0] t2_2;
wire [11:0] t2_3;
wire next_2;
assign t0_0 = X0;
assign Y0 = t2_0;
assign t0_1 = X1;
assign Y1 = t2_1;
assign t0_2 = X2;
assign Y2 = t2_2;
assign t0_3 = X3;
assign Y3 = t2_3;
assign next_0 = next;
assign next_out = next_2;
// latency=980, gap=1024
rc41776 stage0(.clk(clk), .reset(reset), .next(next_0), .next_out(next_1),
.X0(t0_0), .Y0(t1_0),
.X1(t0_1), .Y1(t1_1),
.X2(t0_2), .Y2(t1_2),
.X3(t0_3), .Y3(t1_3));
// latency=11287, gap=11287
ICompose_46101 IComposeInst46328(.next(next_1), .clk(clk), .reset(reset), .next_out(next_2),
.X0(t1_0), .Y0(t2_0),
.X1(t1_1), .Y1(t2_1),
.X2(t1_2), .Y2(t2_2),
.X3(t1_3), .Y3(t2_3));
endmodule
// Latency: 980
// Gap: 1024
module rc41776(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
wire [23:0] t0;
wire [23:0] s0;
assign t0 = {X0, X1};
wire [23:0] t1;
wire [23:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[23:12];
assign Y1 = s0[11:0];
assign Y2 = s1[23:12];
assign Y3 = s1[11:0];
perm41774 instPerm46329(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
// Latency: 980
// Gap: 1024
module perm41774(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 1024;
parameter logDepth = 10;
parameter width = 24;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] ybuff0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] ybuff1;
input clk, next, reset;
output next_out;
wire next0;
reg inFlip0, outFlip0;
reg inActive, outActive;
wire [logBanks-1:0] inBank0, outBank0;
wire [logDepth-1:0] inAddr0, outAddr0;
wire [logBanks-1:0] outBank_a0;
wire [logDepth-1:0] outAddr_a0;
wire [logDepth+logBanks-1:0] addr0, addr0b, addr0c;
wire [logBanks-1:0] inBank1, outBank1;
wire [logDepth-1:0] inAddr1, outAddr1;
wire [logBanks-1:0] outBank_a1;
wire [logDepth-1:0] outAddr_a1;
wire [logDepth+logBanks-1:0] addr1, addr1b, addr1c;
reg [logDepth-1:0] inCount, outCount, outCount_d, outCount_dd, outCount_for_rd_addr, outCount_for_rd_data;
assign addr0 = {inCount, 1'd0};
assign addr0b = {outCount, 1'd0};
assign addr0c = {outCount_for_rd_addr, 1'd0};
assign addr1 = {inCount, 1'd1};
assign addr1b = {outCount, 1'd1};
assign addr1c = {outCount_for_rd_addr, 1'd1};
wire [width+logDepth-1:0] w_0_0, w_0_1, w_1_0, w_1_1;
reg [width-1:0] z_0_0;
reg [width-1:0] z_0_1;
wire [width-1:0] z_1_0, z_1_1;
wire [logDepth-1:0] u_0_0, u_0_1, u_1_0, u_1_1;
always @(posedge clk) begin
end
assign inBank0[0] = addr0[10] ^ addr0[0];
assign inAddr0[0] = addr0[9];
assign inAddr0[1] = addr0[8];
assign inAddr0[2] = addr0[7];
assign inAddr0[3] = addr0[6];
assign inAddr0[4] = addr0[5];
assign inAddr0[5] = addr0[4];
assign inAddr0[6] = addr0[3];
assign inAddr0[7] = addr0[2];
assign inAddr0[8] = addr0[1];
assign inAddr0[9] = addr0[0];
assign outBank0[0] = addr0b[10] ^ addr0b[0];
assign outAddr0[0] = addr0b[1];
assign outAddr0[1] = addr0b[2];
assign outAddr0[2] = addr0b[3];
assign outAddr0[3] = addr0b[4];
assign outAddr0[4] = addr0b[5];
assign outAddr0[5] = addr0b[6];
assign outAddr0[6] = addr0b[7];
assign outAddr0[7] = addr0b[8];
assign outAddr0[8] = addr0b[9];
assign outAddr0[9] = addr0b[10];
assign outBank_a0[0] = addr0c[10] ^ addr0c[0];
assign outAddr_a0[0] = addr0c[1];
assign outAddr_a0[1] = addr0c[2];
assign outAddr_a0[2] = addr0c[3];
assign outAddr_a0[3] = addr0c[4];
assign outAddr_a0[4] = addr0c[5];
assign outAddr_a0[5] = addr0c[6];
assign outAddr_a0[6] = addr0c[7];
assign outAddr_a0[7] = addr0c[8];
assign outAddr_a0[8] = addr0c[9];
assign outAddr_a0[9] = addr0c[10];
assign inBank1[0] = addr1[10] ^ addr1[0];
assign inAddr1[0] = addr1[9];
assign inAddr1[1] = addr1[8];
assign inAddr1[2] = addr1[7];
assign inAddr1[3] = addr1[6];
assign inAddr1[4] = addr1[5];
assign inAddr1[5] = addr1[4];
assign inAddr1[6] = addr1[3];
assign inAddr1[7] = addr1[2];
assign inAddr1[8] = addr1[1];
assign inAddr1[9] = addr1[0];
assign outBank1[0] = addr1b[10] ^ addr1b[0];
assign outAddr1[0] = addr1b[1];
assign outAddr1[1] = addr1b[2];
assign outAddr1[2] = addr1b[3];
assign outAddr1[3] = addr1b[4];
assign outAddr1[4] = addr1b[5];
assign outAddr1[5] = addr1b[6];
assign outAddr1[6] = addr1b[7];
assign outAddr1[7] = addr1b[8];
assign outAddr1[8] = addr1b[9];
assign outAddr1[9] = addr1b[10];
assign outBank_a1[0] = addr1c[10] ^ addr1c[0];
assign outAddr_a1[0] = addr1c[1];
assign outAddr_a1[1] = addr1c[2];
assign outAddr_a1[2] = addr1c[3];
assign outAddr_a1[3] = addr1c[4];
assign outAddr_a1[4] = addr1c[5];
assign outAddr_a1[5] = addr1c[6];
assign outAddr_a1[6] = addr1c[7];
assign outAddr_a1[7] = addr1c[8];
assign outAddr_a1[8] = addr1c[9];
assign outAddr_a1[9] = addr1c[10];
nextReg #(978, 10) nextReg_46334(.X(next), .Y(next0), .reset(reset), .clk(clk));
shiftRegFIFO #(2, 1) shiftFIFO_46337(.X(next0), .Y(next_out), .clk(clk));
memArray2048_41774 #(numBanks, logBanks, depth, logDepth, width)
memSys(.inFlip(inFlip0), .outFlip(outFlip0), .next(next), .reset(reset),
.x0(w_1_0[width+logDepth-1:logDepth]), .y0(ybuff0),
.inAddr0(w_1_0[logDepth-1:0]),
.outAddr0(u_1_0),
.x1(w_1_1[width+logDepth-1:logDepth]), .y1(ybuff1),
.inAddr1(w_1_1[logDepth-1:0]),
.outAddr1(u_1_1),
.clk(clk));
always @(posedge clk) begin
if (reset == 1) begin
z_0_0 <= 0;
z_0_1 <= 0;
inFlip0 <= 0; outFlip0 <= 1; outCount <= 0; inCount <= 0;
outCount_for_rd_addr <= 0;
outCount_for_rd_data <= 0;
end
else begin
outCount_d <= outCount;
outCount_dd <= outCount_d;
if (inCount == 977)
outCount_for_rd_addr <= 0;
else
outCount_for_rd_addr <= outCount_for_rd_addr+1;
if (inCount == 979)
outCount_for_rd_data <= 0;
else
outCount_for_rd_data <= outCount_for_rd_data+1;
z_0_0 <= ybuff0;
z_0_1 <= ybuff1;
if (inCount == 977) begin
outFlip0 <= ~outFlip0;
outCount <= 0;
end
else
outCount <= outCount+1;
if (inCount == 1023) begin
inFlip0 <= ~inFlip0;
end
if (next == 1) begin
if (inCount >= 977)
inFlip0 <= ~inFlip0;
inCount <= 0;
end
else
inCount <= inCount + 1;
end
end
assign w_0_0 = {x0, inAddr0};
assign w_0_1 = {x1, inAddr1};
assign y0 = z_1_0;
assign y1 = z_1_1;
assign u_0_0 = outAddr_a0;
assign u_0_1 = outAddr_a1;
wire wr_ctrl_st_0;
assign wr_ctrl_st_0 = inCount[9];
switch #(logDepth+width) in_sw_0_0(.x0(w_0_0), .x1(w_0_1), .y0(w_1_0), .y1(w_1_1), .ctrl(wr_ctrl_st_0));
wire rdd_ctrl_st_0;
assign rdd_ctrl_st_0 = outCount_for_rd_data[9];
switch #(width) out_sw_0_0(.x0(z_0_0), .x1(z_0_1), .y0(z_1_0), .y1(z_1_1), .ctrl(rdd_ctrl_st_0));
wire rda_ctrl_st_0;
assign rda_ctrl_st_0 = outCount_for_rd_addr[9];
switch #(logDepth) rdaddr_sw_0_0(.x0(u_0_0), .x1(u_0_1), .y0(u_1_0), .y1(u_1_1), .ctrl(rda_ctrl_st_0));
endmodule
module memArray2048_41774(next, reset,
x0, y0,
inAddr0,
outAddr0,
x1, y1,
inAddr1,
outAddr1,
clk, inFlip, outFlip);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 1024;
parameter logDepth = 10;
parameter width = 24;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
nextReg #(1024, 10) nextReg_46342(.X(next), .Y(next0), .reset(reset), .clk(clk));
memMod #(depth*2, width, logDepth+1)
memMod0(.in(x0), .out(y0), .inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}), .writeSel(1'b1), .clk(clk));
memMod #(depth*2, width, logDepth+1)
memMod1(.in(x1), .out(y1), .inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}), .writeSel(1'b1), .clk(clk));
endmodule
module nextReg(X, Y, reset, clk);
parameter depth=2, logDepth=1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @ (posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0;
end
else if (X == 1) begin
active <= 1;
count <= 1;
end
else if (count == depth) begin
count <= 0;
active <= 0;
end
else if (active)
count <= count+1;
end
endmodule
module memMod(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is block
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module memMod_dist(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is distributed
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module switch(ctrl, x0, x1, y0, y1);
parameter width = 16;
input [width-1:0] x0, x1;
output [width-1:0] y0, y1;
input ctrl;
assign y0 = (ctrl == 0) ? x0 : x1;
assign y1 = (ctrl == 0) ? x1 : x0;
endmodule
module shiftRegFIFO(X, Y, clk);
parameter depth=1, width=1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @ (posedge clk) begin
for(index=1;index<depth;index=index+1) begin
mem[index] <= mem[index-1];
end
mem[0]<=X;
end
endmodule
// Latency: 11287
// Gap: 11287
module ICompose_46101(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
reg next_out;
input clk, reset, next;
reg [10:0] cycle_count;
reg [10:0] count;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
reg [11:0] Y0,
Y1,
Y2,
Y3;
reg int_next;
reg state;
wire [11:0] t0;
reg [11:0] s0;
wire [11:0] t1;
reg [11:0] s1;
wire [11:0] t2;
reg [11:0] s2;
wire [11:0] t3;
reg [11:0] s3;
reg [1:0] iri_state;
wire int_next_out;
reg [4:0] i1;
statementList46099 instList46347 (.clk(clk), .reset(reset), .next(int_next), .next_out(int_next_out),
.i1_in(i1),
.X0(s0), .Y0(t0),
.X1(s1), .Y1(t1),
.X2(s2), .Y2(t2),
.X3(s3), .Y3(t3));
always @(posedge clk) begin
if (reset == 1) begin
int_next <= 0;
i1 <= 10;
cycle_count <= 0;
next_out <= 0;
iri_state <= 0;
Y0 <= 0;
Y1 <= 0;
Y2 <= 0;
Y3 <= 0;
end
else begin
Y0 <= t0;
Y1 <= t1;
Y2 <= t2;
Y3 <= t3;
next_out <= 0;
case (iri_state)
0: begin
i1 <= 10;
cycle_count <= 0;
if (next == 1) begin
int_next <= 1;
iri_state <= 1;
end
else begin
int_next <= 0;
iri_state <= 0;
end
end
1: begin
int_next <= 0;
cycle_count <= cycle_count + 1;
i1 <= i1;
if (cycle_count < 1024)
iri_state <= 1;
else
iri_state <= 2;
end
2: begin
cycle_count <= 0;
i1 <= i1 - 1;
if (i1 > 0) begin
iri_state <= 1;
int_next <= 1;
end
else begin
iri_state <= 0;
next_out <= 1;
int_next <= 0;
end
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state <= 0;
count <= 0;
s0 <= 0;
s1 <= 0;
s2 <= 0;
s3 <= 0;
end
else begin
case (state)
0: begin
count <= 0;
if (next == 1) begin
state <= 1;
count <= 0;
s0 <= X0;
s1 <= X1;
s2 <= X2;
s3 <= X3;
end
else begin
state <= 0;
count <= 0;
s0 <= t0;
s1 <= t1;
s2 <= t2;
s3 <= t3;
end
end
1: begin
count <= count + 1;
if (count < 1024) begin
s0 <= X0;
s1 <= X1;
s2 <= X2;
s3 <= X3;
state <= 1;
end
else begin
s0 <= t0;
s1 <= t1;
s2 <= t2;
s3 <= t3;
state <= 0;
end
end
endcase
end
end
endmodule
// Latency: 1025
// Gap: 1024
// module_name_is:statementList46099
module statementList46099(clk, reset, next, next_out,
i1_in,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [4:0] i1_in;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
wire [11:0] t0_0;
wire [11:0] t0_1;
wire [11:0] t0_2;
wire [11:0] t0_3;
wire next_0;
wire [11:0] t1_0;
wire [11:0] t1_1;
wire [11:0] t1_2;
wire [11:0] t1_3;
wire next_1;
wire [11:0] t2_0;
wire [11:0] t2_1;
wire [11:0] t2_2;
wire [11:0] t2_3;
wire next_2;
wire [11:0] t3_0;
wire [11:0] t3_1;
wire [11:0] t3_2;
wire [11:0] t3_3;
wire next_3;
wire [4:0] i1;
wire [4:0] i1_0;
assign t0_0 = X0;
assign Y0 = t3_0;
assign t0_1 = X1;
assign Y1 = t3_1;
assign t0_2 = X2;
assign Y2 = t3_2;
assign t0_3 = X3;
assign Y3 = t3_3;
assign next_0 = next;
assign next_out = next_3;
assign i1_0 = i1_in;
// latency=11, gap=1024
DirSum_46014 DirSumInst46350(.next(next_0), .clk(clk), .reset(reset), .next_out(next_1),
.i1(i1_0),
.X0(t0_0), .Y0(t1_0),
.X1(t0_1), .Y1(t1_1),
.X2(t0_2), .Y2(t1_2),
.X3(t0_3), .Y3(t1_3));
// latency=2, gap=1024
codeBlock46016 codeBlockIsnt46351(.clk(clk), .reset(reset), .next_in(next_1), .next_out(next_2),
.X0_in(t1_0), .Y0(t2_0),
.X1_in(t1_1), .Y1(t2_1),
.X2_in(t1_2), .Y2(t2_2),
.X3_in(t1_3), .Y3(t2_3));
// latency=1012, gap=1024
rc46097 instrc46352(.clk(clk), .reset(reset), .next(next_2), .next_out(next_3),
.X0(t2_0), .Y0(t3_0),
.X1(t2_1), .Y1(t3_1),
.X2(t2_2), .Y2(t3_2),
.X3(t2_3), .Y3(t3_3));
endmodule
// Latency: 11
// Gap: 1024
module DirSum_46014(clk, reset, next, next_out,
i1,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [4:0] i1;
reg [9:0] i2;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i2 <= 0;
end
else begin
if (next == 1)
i2 <= 0;
else if (i2 == 1023)
i2 <= 0;
else
i2 <= i2 + 1;
end
end
codeBlock41778 codeBlockIsnt46353(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i2_in(i2),
.i1_in(i1),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D1_43962(addr, out, clk);
input clk;
output [11:0] out;
reg [11:0] out, out2, out3;
input [10:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 12'h400;
1: out3 <= 12'h400;
2: out3 <= 12'h400;
3: out3 <= 12'h400;
4: out3 <= 12'h400;
5: out3 <= 12'h400;
6: out3 <= 12'h400;
7: out3 <= 12'h400;
8: out3 <= 12'h400;
9: out3 <= 12'h400;
10: out3 <= 12'h400;
11: out3 <= 12'h3ff;
12: out3 <= 12'h3ff;
13: out3 <= 12'h3ff;
14: out3 <= 12'h3ff;
15: out3 <= 12'h3ff;
16: out3 <= 12'h3ff;
17: out3 <= 12'h3ff;
18: out3 <= 12'h3fe;
19: out3 <= 12'h3fe;
20: out3 <= 12'h3fe;
21: out3 <= 12'h3fe;
22: out3 <= 12'h3fe;
23: out3 <= 12'h3fd;
24: out3 <= 12'h3fd;
25: out3 <= 12'h3fd;
26: out3 <= 12'h3fd;
27: out3 <= 12'h3fc;
28: out3 <= 12'h3fc;
29: out3 <= 12'h3fc;
30: out3 <= 12'h3fc;
31: out3 <= 12'h3fb;
32: out3 <= 12'h3fb;
33: out3 <= 12'h3fb;
34: out3 <= 12'h3fa;
35: out3 <= 12'h3fa;
36: out3 <= 12'h3fa;
37: out3 <= 12'h3f9;
38: out3 <= 12'h3f9;
39: out3 <= 12'h3f9;
40: out3 <= 12'h3f8;
41: out3 <= 12'h3f8;
42: out3 <= 12'h3f8;
43: out3 <= 12'h3f7;
44: out3 <= 12'h3f7;
45: out3 <= 12'h3f6;
46: out3 <= 12'h3f6;
47: out3 <= 12'h3f5;
48: out3 <= 12'h3f5;
49: out3 <= 12'h3f4;
50: out3 <= 12'h3f4;
51: out3 <= 12'h3f3;
52: out3 <= 12'h3f3;
53: out3 <= 12'h3f2;
54: out3 <= 12'h3f2;
55: out3 <= 12'h3f1;
56: out3 <= 12'h3f1;
57: out3 <= 12'h3f0;
58: out3 <= 12'h3f0;
59: out3 <= 12'h3ef;
60: out3 <= 12'h3ef;
61: out3 <= 12'h3ee;
62: out3 <= 12'h3ee;
63: out3 <= 12'h3ed;
64: out3 <= 12'h3ec;
65: out3 <= 12'h3ec;
66: out3 <= 12'h3eb;
67: out3 <= 12'h3ea;
68: out3 <= 12'h3ea;
69: out3 <= 12'h3e9;
70: out3 <= 12'h3e8;
71: out3 <= 12'h3e8;
72: out3 <= 12'h3e7;
73: out3 <= 12'h3e6;
74: out3 <= 12'h3e6;
75: out3 <= 12'h3e5;
76: out3 <= 12'h3e4;
77: out3 <= 12'h3e4;
78: out3 <= 12'h3e3;
79: out3 <= 12'h3e2;
80: out3 <= 12'h3e1;
81: out3 <= 12'h3e1;
82: out3 <= 12'h3e0;
83: out3 <= 12'h3df;
84: out3 <= 12'h3de;
85: out3 <= 12'h3dd;
86: out3 <= 12'h3dd;
87: out3 <= 12'h3dc;
88: out3 <= 12'h3db;
89: out3 <= 12'h3da;
90: out3 <= 12'h3d9;
91: out3 <= 12'h3d8;
92: out3 <= 12'h3d7;
93: out3 <= 12'h3d7;
94: out3 <= 12'h3d6;
95: out3 <= 12'h3d5;
96: out3 <= 12'h3d4;
97: out3 <= 12'h3d3;
98: out3 <= 12'h3d2;
99: out3 <= 12'h3d1;
100: out3 <= 12'h3d0;
101: out3 <= 12'h3cf;
102: out3 <= 12'h3ce;
103: out3 <= 12'h3cd;
104: out3 <= 12'h3cc;
105: out3 <= 12'h3cb;
106: out3 <= 12'h3ca;
107: out3 <= 12'h3c9;
108: out3 <= 12'h3c8;
109: out3 <= 12'h3c7;
110: out3 <= 12'h3c6;
111: out3 <= 12'h3c5;
112: out3 <= 12'h3c4;
113: out3 <= 12'h3c3;
114: out3 <= 12'h3c2;
115: out3 <= 12'h3c1;
116: out3 <= 12'h3c0;
117: out3 <= 12'h3bf;
118: out3 <= 12'h3be;
119: out3 <= 12'h3bd;
120: out3 <= 12'h3bb;
121: out3 <= 12'h3ba;
122: out3 <= 12'h3b9;
123: out3 <= 12'h3b8;
124: out3 <= 12'h3b7;
125: out3 <= 12'h3b6;
126: out3 <= 12'h3b4;
127: out3 <= 12'h3b3;
128: out3 <= 12'h3b2;
129: out3 <= 12'h3b1;
130: out3 <= 12'h3b0;
131: out3 <= 12'h3ae;
132: out3 <= 12'h3ad;
133: out3 <= 12'h3ac;
134: out3 <= 12'h3ab;
135: out3 <= 12'h3a9;
136: out3 <= 12'h3a8;
137: out3 <= 12'h3a7;
138: out3 <= 12'h3a6;
139: out3 <= 12'h3a4;
140: out3 <= 12'h3a3;
141: out3 <= 12'h3a2;
142: out3 <= 12'h3a0;
143: out3 <= 12'h39f;
144: out3 <= 12'h39e;
145: out3 <= 12'h39c;
146: out3 <= 12'h39b;
147: out3 <= 12'h39a;
148: out3 <= 12'h398;
149: out3 <= 12'h397;
150: out3 <= 12'h395;
151: out3 <= 12'h394;
152: out3 <= 12'h393;
153: out3 <= 12'h391;
154: out3 <= 12'h390;
155: out3 <= 12'h38e;
156: out3 <= 12'h38d;
157: out3 <= 12'h38b;
158: out3 <= 12'h38a;
159: out3 <= 12'h389;
160: out3 <= 12'h387;
161: out3 <= 12'h386;
162: out3 <= 12'h384;
163: out3 <= 12'h383;
164: out3 <= 12'h381;
165: out3 <= 12'h380;
166: out3 <= 12'h37e;
167: out3 <= 12'h37d;
168: out3 <= 12'h37b;
169: out3 <= 12'h379;
170: out3 <= 12'h378;
171: out3 <= 12'h376;
172: out3 <= 12'h375;
173: out3 <= 12'h373;
174: out3 <= 12'h372;
175: out3 <= 12'h370;
176: out3 <= 12'h36e;
177: out3 <= 12'h36d;
178: out3 <= 12'h36b;
179: out3 <= 12'h369;
180: out3 <= 12'h368;
181: out3 <= 12'h366;
182: out3 <= 12'h364;
183: out3 <= 12'h363;
184: out3 <= 12'h361;
185: out3 <= 12'h35f;
186: out3 <= 12'h35e;
187: out3 <= 12'h35c;
188: out3 <= 12'h35a;
189: out3 <= 12'h359;
190: out3 <= 12'h357;
191: out3 <= 12'h355;
192: out3 <= 12'h353;
193: out3 <= 12'h352;
194: out3 <= 12'h350;
195: out3 <= 12'h34e;
196: out3 <= 12'h34c;
197: out3 <= 12'h34b;
198: out3 <= 12'h349;
199: out3 <= 12'h347;
200: out3 <= 12'h345;
201: out3 <= 12'h343;
202: out3 <= 12'h342;
203: out3 <= 12'h340;
204: out3 <= 12'h33e;
205: out3 <= 12'h33c;
206: out3 <= 12'h33a;
207: out3 <= 12'h338;
208: out3 <= 12'h336;
209: out3 <= 12'h335;
210: out3 <= 12'h333;
211: out3 <= 12'h331;
212: out3 <= 12'h32f;
213: out3 <= 12'h32d;
214: out3 <= 12'h32b;
215: out3 <= 12'h329;
216: out3 <= 12'h327;
217: out3 <= 12'h325;
218: out3 <= 12'h323;
219: out3 <= 12'h321;
220: out3 <= 12'h31f;
221: out3 <= 12'h31e;
222: out3 <= 12'h31c;
223: out3 <= 12'h31a;
224: out3 <= 12'h318;
225: out3 <= 12'h316;
226: out3 <= 12'h314;
227: out3 <= 12'h312;
228: out3 <= 12'h310;
229: out3 <= 12'h30e;
230: out3 <= 12'h30b;
231: out3 <= 12'h309;
232: out3 <= 12'h307;
233: out3 <= 12'h305;
234: out3 <= 12'h303;
235: out3 <= 12'h301;
236: out3 <= 12'h2ff;
237: out3 <= 12'h2fd;
238: out3 <= 12'h2fb;
239: out3 <= 12'h2f9;
240: out3 <= 12'h2f7;
241: out3 <= 12'h2f5;
242: out3 <= 12'h2f3;
243: out3 <= 12'h2f0;
244: out3 <= 12'h2ee;
245: out3 <= 12'h2ec;
246: out3 <= 12'h2ea;
247: out3 <= 12'h2e8;
248: out3 <= 12'h2e6;
249: out3 <= 12'h2e3;
250: out3 <= 12'h2e1;
251: out3 <= 12'h2df;
252: out3 <= 12'h2dd;
253: out3 <= 12'h2db;
254: out3 <= 12'h2d9;
255: out3 <= 12'h2d6;
256: out3 <= 12'h2d4;
257: out3 <= 12'h2d2;
258: out3 <= 12'h2d0;
259: out3 <= 12'h2cd;
260: out3 <= 12'h2cb;
261: out3 <= 12'h2c9;
262: out3 <= 12'h2c7;
263: out3 <= 12'h2c4;
264: out3 <= 12'h2c2;
265: out3 <= 12'h2c0;
266: out3 <= 12'h2be;
267: out3 <= 12'h2bb;
268: out3 <= 12'h2b9;
269: out3 <= 12'h2b7;
270: out3 <= 12'h2b4;
271: out3 <= 12'h2b2;
272: out3 <= 12'h2b0;
273: out3 <= 12'h2ad;
274: out3 <= 12'h2ab;
275: out3 <= 12'h2a9;
276: out3 <= 12'h2a6;
277: out3 <= 12'h2a4;
278: out3 <= 12'h2a2;
279: out3 <= 12'h29f;
280: out3 <= 12'h29d;
281: out3 <= 12'h29a;
282: out3 <= 12'h298;
283: out3 <= 12'h296;
284: out3 <= 12'h293;
285: out3 <= 12'h291;
286: out3 <= 12'h28e;
287: out3 <= 12'h28c;
288: out3 <= 12'h28a;
289: out3 <= 12'h287;
290: out3 <= 12'h285;
291: out3 <= 12'h282;
292: out3 <= 12'h280;
293: out3 <= 12'h27d;
294: out3 <= 12'h27b;
295: out3 <= 12'h278;
296: out3 <= 12'h276;
297: out3 <= 12'h274;
298: out3 <= 12'h271;
299: out3 <= 12'h26f;
300: out3 <= 12'h26c;
301: out3 <= 12'h26a;
302: out3 <= 12'h267;
303: out3 <= 12'h265;
304: out3 <= 12'h262;
305: out3 <= 12'h25f;
306: out3 <= 12'h25d;
307: out3 <= 12'h25a;
308: out3 <= 12'h258;
309: out3 <= 12'h255;
310: out3 <= 12'h253;
311: out3 <= 12'h250;
312: out3 <= 12'h24e;
313: out3 <= 12'h24b;
314: out3 <= 12'h248;
315: out3 <= 12'h246;
316: out3 <= 12'h243;
317: out3 <= 12'h241;
318: out3 <= 12'h23e;
319: out3 <= 12'h23c;
320: out3 <= 12'h239;
321: out3 <= 12'h236;
322: out3 <= 12'h234;
323: out3 <= 12'h231;
324: out3 <= 12'h22e;
325: out3 <= 12'h22c;
326: out3 <= 12'h229;
327: out3 <= 12'h226;
328: out3 <= 12'h224;
329: out3 <= 12'h221;
330: out3 <= 12'h21f;
331: out3 <= 12'h21c;
332: out3 <= 12'h219;
333: out3 <= 12'h217;
334: out3 <= 12'h214;
335: out3 <= 12'h211;
336: out3 <= 12'h20e;
337: out3 <= 12'h20c;
338: out3 <= 12'h209;
339: out3 <= 12'h206;
340: out3 <= 12'h204;
341: out3 <= 12'h201;
342: out3 <= 12'h1fe;
343: out3 <= 12'h1fb;
344: out3 <= 12'h1f9;
345: out3 <= 12'h1f6;
346: out3 <= 12'h1f3;
347: out3 <= 12'h1f1;
348: out3 <= 12'h1ee;
349: out3 <= 12'h1eb;
350: out3 <= 12'h1e8;
351: out3 <= 12'h1e5;
352: out3 <= 12'h1e3;
353: out3 <= 12'h1e0;
354: out3 <= 12'h1dd;
355: out3 <= 12'h1da;
356: out3 <= 12'h1d8;
357: out3 <= 12'h1d5;
358: out3 <= 12'h1d2;
359: out3 <= 12'h1cf;
360: out3 <= 12'h1cc;
361: out3 <= 12'h1ca;
362: out3 <= 12'h1c7;
363: out3 <= 12'h1c4;
364: out3 <= 12'h1c1;
365: out3 <= 12'h1be;
366: out3 <= 12'h1bb;
367: out3 <= 12'h1b9;
368: out3 <= 12'h1b6;
369: out3 <= 12'h1b3;
370: out3 <= 12'h1b0;
371: out3 <= 12'h1ad;
372: out3 <= 12'h1aa;
373: out3 <= 12'h1a8;
374: out3 <= 12'h1a5;
375: out3 <= 12'h1a2;
376: out3 <= 12'h19f;
377: out3 <= 12'h19c;
378: out3 <= 12'h199;
379: out3 <= 12'h196;
380: out3 <= 12'h193;
381: out3 <= 12'h191;
382: out3 <= 12'h18e;
383: out3 <= 12'h18b;
384: out3 <= 12'h188;
385: out3 <= 12'h185;
386: out3 <= 12'h182;
387: out3 <= 12'h17f;
388: out3 <= 12'h17c;
389: out3 <= 12'h179;
390: out3 <= 12'h176;
391: out3 <= 12'h173;
392: out3 <= 12'h171;
393: out3 <= 12'h16e;
394: out3 <= 12'h16b;
395: out3 <= 12'h168;
396: out3 <= 12'h165;
397: out3 <= 12'h162;
398: out3 <= 12'h15f;
399: out3 <= 12'h15c;
400: out3 <= 12'h159;
401: out3 <= 12'h156;
402: out3 <= 12'h153;
403: out3 <= 12'h150;
404: out3 <= 12'h14d;
405: out3 <= 12'h14a;
406: out3 <= 12'h147;
407: out3 <= 12'h144;
408: out3 <= 12'h141;
409: out3 <= 12'h13e;
410: out3 <= 12'h13b;
411: out3 <= 12'h138;
412: out3 <= 12'h135;
413: out3 <= 12'h132;
414: out3 <= 12'h12f;
415: out3 <= 12'h12c;
416: out3 <= 12'h129;
417: out3 <= 12'h126;
418: out3 <= 12'h123;
419: out3 <= 12'h120;
420: out3 <= 12'h11d;
421: out3 <= 12'h11a;
422: out3 <= 12'h117;
423: out3 <= 12'h114;
424: out3 <= 12'h111;
425: out3 <= 12'h10e;
426: out3 <= 12'h10b;
427: out3 <= 12'h108;
428: out3 <= 12'h105;
429: out3 <= 12'h102;
430: out3 <= 12'hff;
431: out3 <= 12'hfc;
432: out3 <= 12'hf9;
433: out3 <= 12'hf6;
434: out3 <= 12'hf3;
435: out3 <= 12'hf0;
436: out3 <= 12'hed;
437: out3 <= 12'hea;
438: out3 <= 12'he6;
439: out3 <= 12'he3;
440: out3 <= 12'he0;
441: out3 <= 12'hdd;
442: out3 <= 12'hda;
443: out3 <= 12'hd7;
444: out3 <= 12'hd4;
445: out3 <= 12'hd1;
446: out3 <= 12'hce;
447: out3 <= 12'hcb;
448: out3 <= 12'hc8;
449: out3 <= 12'hc5;
450: out3 <= 12'hc2;
451: out3 <= 12'hbf;
452: out3 <= 12'hbb;
453: out3 <= 12'hb8;
454: out3 <= 12'hb5;
455: out3 <= 12'hb2;
456: out3 <= 12'haf;
457: out3 <= 12'hac;
458: out3 <= 12'ha9;
459: out3 <= 12'ha6;
460: out3 <= 12'ha3;
461: out3 <= 12'ha0;
462: out3 <= 12'h9c;
463: out3 <= 12'h99;
464: out3 <= 12'h96;
465: out3 <= 12'h93;
466: out3 <= 12'h90;
467: out3 <= 12'h8d;
468: out3 <= 12'h8a;
469: out3 <= 12'h87;
470: out3 <= 12'h84;
471: out3 <= 12'h80;
472: out3 <= 12'h7d;
473: out3 <= 12'h7a;
474: out3 <= 12'h77;
475: out3 <= 12'h74;
476: out3 <= 12'h71;
477: out3 <= 12'h6e;
478: out3 <= 12'h6b;
479: out3 <= 12'h67;
480: out3 <= 12'h64;
481: out3 <= 12'h61;
482: out3 <= 12'h5e;
483: out3 <= 12'h5b;
484: out3 <= 12'h58;
485: out3 <= 12'h55;
486: out3 <= 12'h52;
487: out3 <= 12'h4e;
488: out3 <= 12'h4b;
489: out3 <= 12'h48;
490: out3 <= 12'h45;
491: out3 <= 12'h42;
492: out3 <= 12'h3f;
493: out3 <= 12'h3c;
494: out3 <= 12'h39;
495: out3 <= 12'h35;
496: out3 <= 12'h32;
497: out3 <= 12'h2f;
498: out3 <= 12'h2c;
499: out3 <= 12'h29;
500: out3 <= 12'h26;
501: out3 <= 12'h23;
502: out3 <= 12'h1f;
503: out3 <= 12'h1c;
504: out3 <= 12'h19;
505: out3 <= 12'h16;
506: out3 <= 12'h13;
507: out3 <= 12'h10;
508: out3 <= 12'hd;
509: out3 <= 12'h9;
510: out3 <= 12'h6;
511: out3 <= 12'h3;
512: out3 <= 12'h0;
513: out3 <= 12'hffd;
514: out3 <= 12'hffa;
515: out3 <= 12'hff7;
516: out3 <= 12'hff3;
517: out3 <= 12'hff0;
518: out3 <= 12'hfed;
519: out3 <= 12'hfea;
520: out3 <= 12'hfe7;
521: out3 <= 12'hfe4;
522: out3 <= 12'hfe1;
523: out3 <= 12'hfdd;
524: out3 <= 12'hfda;
525: out3 <= 12'hfd7;
526: out3 <= 12'hfd4;
527: out3 <= 12'hfd1;
528: out3 <= 12'hfce;
529: out3 <= 12'hfcb;
530: out3 <= 12'hfc7;
531: out3 <= 12'hfc4;
532: out3 <= 12'hfc1;
533: out3 <= 12'hfbe;
534: out3 <= 12'hfbb;
535: out3 <= 12'hfb8;
536: out3 <= 12'hfb5;
537: out3 <= 12'hfb2;
538: out3 <= 12'hfae;
539: out3 <= 12'hfab;
540: out3 <= 12'hfa8;
541: out3 <= 12'hfa5;
542: out3 <= 12'hfa2;
543: out3 <= 12'hf9f;
544: out3 <= 12'hf9c;
545: out3 <= 12'hf99;
546: out3 <= 12'hf95;
547: out3 <= 12'hf92;
548: out3 <= 12'hf8f;
549: out3 <= 12'hf8c;
550: out3 <= 12'hf89;
551: out3 <= 12'hf86;
552: out3 <= 12'hf83;
553: out3 <= 12'hf80;
554: out3 <= 12'hf7c;
555: out3 <= 12'hf79;
556: out3 <= 12'hf76;
557: out3 <= 12'hf73;
558: out3 <= 12'hf70;
559: out3 <= 12'hf6d;
560: out3 <= 12'hf6a;
561: out3 <= 12'hf67;
562: out3 <= 12'hf64;
563: out3 <= 12'hf60;
564: out3 <= 12'hf5d;
565: out3 <= 12'hf5a;
566: out3 <= 12'hf57;
567: out3 <= 12'hf54;
568: out3 <= 12'hf51;
569: out3 <= 12'hf4e;
570: out3 <= 12'hf4b;
571: out3 <= 12'hf48;
572: out3 <= 12'hf45;
573: out3 <= 12'hf41;
574: out3 <= 12'hf3e;
575: out3 <= 12'hf3b;
576: out3 <= 12'hf38;
577: out3 <= 12'hf35;
578: out3 <= 12'hf32;
579: out3 <= 12'hf2f;
580: out3 <= 12'hf2c;
581: out3 <= 12'hf29;
582: out3 <= 12'hf26;
583: out3 <= 12'hf23;
584: out3 <= 12'hf20;
585: out3 <= 12'hf1d;
586: out3 <= 12'hf1a;
587: out3 <= 12'hf16;
588: out3 <= 12'hf13;
589: out3 <= 12'hf10;
590: out3 <= 12'hf0d;
591: out3 <= 12'hf0a;
592: out3 <= 12'hf07;
593: out3 <= 12'hf04;
594: out3 <= 12'hf01;
595: out3 <= 12'hefe;
596: out3 <= 12'hefb;
597: out3 <= 12'hef8;
598: out3 <= 12'hef5;
599: out3 <= 12'hef2;
600: out3 <= 12'heef;
601: out3 <= 12'heec;
602: out3 <= 12'hee9;
603: out3 <= 12'hee6;
604: out3 <= 12'hee3;
605: out3 <= 12'hee0;
606: out3 <= 12'hedd;
607: out3 <= 12'heda;
608: out3 <= 12'hed7;
609: out3 <= 12'hed4;
610: out3 <= 12'hed1;
611: out3 <= 12'hece;
612: out3 <= 12'hecb;
613: out3 <= 12'hec8;
614: out3 <= 12'hec5;
615: out3 <= 12'hec2;
616: out3 <= 12'hebf;
617: out3 <= 12'hebc;
618: out3 <= 12'heb9;
619: out3 <= 12'heb6;
620: out3 <= 12'heb3;
621: out3 <= 12'heb0;
622: out3 <= 12'head;
623: out3 <= 12'heaa;
624: out3 <= 12'hea7;
625: out3 <= 12'hea4;
626: out3 <= 12'hea1;
627: out3 <= 12'he9e;
628: out3 <= 12'he9b;
629: out3 <= 12'he98;
630: out3 <= 12'he95;
631: out3 <= 12'he92;
632: out3 <= 12'he8f;
633: out3 <= 12'he8d;
634: out3 <= 12'he8a;
635: out3 <= 12'he87;
636: out3 <= 12'he84;
637: out3 <= 12'he81;
638: out3 <= 12'he7e;
639: out3 <= 12'he7b;
640: out3 <= 12'he78;
641: out3 <= 12'he75;
642: out3 <= 12'he72;
643: out3 <= 12'he6f;
644: out3 <= 12'he6d;
645: out3 <= 12'he6a;
646: out3 <= 12'he67;
647: out3 <= 12'he64;
648: out3 <= 12'he61;
649: out3 <= 12'he5e;
650: out3 <= 12'he5b;
651: out3 <= 12'he58;
652: out3 <= 12'he56;
653: out3 <= 12'he53;
654: out3 <= 12'he50;
655: out3 <= 12'he4d;
656: out3 <= 12'he4a;
657: out3 <= 12'he47;
658: out3 <= 12'he45;
659: out3 <= 12'he42;
660: out3 <= 12'he3f;
661: out3 <= 12'he3c;
662: out3 <= 12'he39;
663: out3 <= 12'he36;
664: out3 <= 12'he34;
665: out3 <= 12'he31;
666: out3 <= 12'he2e;
667: out3 <= 12'he2b;
668: out3 <= 12'he28;
669: out3 <= 12'he26;
670: out3 <= 12'he23;
671: out3 <= 12'he20;
672: out3 <= 12'he1d;
673: out3 <= 12'he1b;
674: out3 <= 12'he18;
675: out3 <= 12'he15;
676: out3 <= 12'he12;
677: out3 <= 12'he0f;
678: out3 <= 12'he0d;
679: out3 <= 12'he0a;
680: out3 <= 12'he07;
681: out3 <= 12'he05;
682: out3 <= 12'he02;
683: out3 <= 12'hdff;
684: out3 <= 12'hdfc;
685: out3 <= 12'hdfa;
686: out3 <= 12'hdf7;
687: out3 <= 12'hdf4;
688: out3 <= 12'hdf2;
689: out3 <= 12'hdef;
690: out3 <= 12'hdec;
691: out3 <= 12'hde9;
692: out3 <= 12'hde7;
693: out3 <= 12'hde4;
694: out3 <= 12'hde1;
695: out3 <= 12'hddf;
696: out3 <= 12'hddc;
697: out3 <= 12'hdda;
698: out3 <= 12'hdd7;
699: out3 <= 12'hdd4;
700: out3 <= 12'hdd2;
701: out3 <= 12'hdcf;
702: out3 <= 12'hdcc;
703: out3 <= 12'hdca;
704: out3 <= 12'hdc7;
705: out3 <= 12'hdc4;
706: out3 <= 12'hdc2;
707: out3 <= 12'hdbf;
708: out3 <= 12'hdbd;
709: out3 <= 12'hdba;
710: out3 <= 12'hdb8;
711: out3 <= 12'hdb5;
712: out3 <= 12'hdb2;
713: out3 <= 12'hdb0;
714: out3 <= 12'hdad;
715: out3 <= 12'hdab;
716: out3 <= 12'hda8;
717: out3 <= 12'hda6;
718: out3 <= 12'hda3;
719: out3 <= 12'hda1;
720: out3 <= 12'hd9e;
721: out3 <= 12'hd9b;
722: out3 <= 12'hd99;
723: out3 <= 12'hd96;
724: out3 <= 12'hd94;
725: out3 <= 12'hd91;
726: out3 <= 12'hd8f;
727: out3 <= 12'hd8c;
728: out3 <= 12'hd8a;
729: out3 <= 12'hd88;
730: out3 <= 12'hd85;
731: out3 <= 12'hd83;
732: out3 <= 12'hd80;
733: out3 <= 12'hd7e;
734: out3 <= 12'hd7b;
735: out3 <= 12'hd79;
736: out3 <= 12'hd76;
737: out3 <= 12'hd74;
738: out3 <= 12'hd72;
739: out3 <= 12'hd6f;
740: out3 <= 12'hd6d;
741: out3 <= 12'hd6a;
742: out3 <= 12'hd68;
743: out3 <= 12'hd66;
744: out3 <= 12'hd63;
745: out3 <= 12'hd61;
746: out3 <= 12'hd5e;
747: out3 <= 12'hd5c;
748: out3 <= 12'hd5a;
749: out3 <= 12'hd57;
750: out3 <= 12'hd55;
751: out3 <= 12'hd53;
752: out3 <= 12'hd50;
753: out3 <= 12'hd4e;
754: out3 <= 12'hd4c;
755: out3 <= 12'hd49;
756: out3 <= 12'hd47;
757: out3 <= 12'hd45;
758: out3 <= 12'hd42;
759: out3 <= 12'hd40;
760: out3 <= 12'hd3e;
761: out3 <= 12'hd3c;
762: out3 <= 12'hd39;
763: out3 <= 12'hd37;
764: out3 <= 12'hd35;
765: out3 <= 12'hd33;
766: out3 <= 12'hd30;
767: out3 <= 12'hd2e;
768: out3 <= 12'hd2c;
769: out3 <= 12'hd2a;
770: out3 <= 12'hd27;
771: out3 <= 12'hd25;
772: out3 <= 12'hd23;
773: out3 <= 12'hd21;
774: out3 <= 12'hd1f;
775: out3 <= 12'hd1d;
776: out3 <= 12'hd1a;
777: out3 <= 12'hd18;
778: out3 <= 12'hd16;
779: out3 <= 12'hd14;
780: out3 <= 12'hd12;
781: out3 <= 12'hd10;
782: out3 <= 12'hd0d;
783: out3 <= 12'hd0b;
784: out3 <= 12'hd09;
785: out3 <= 12'hd07;
786: out3 <= 12'hd05;
787: out3 <= 12'hd03;
788: out3 <= 12'hd01;
789: out3 <= 12'hcff;
790: out3 <= 12'hcfd;
791: out3 <= 12'hcfb;
792: out3 <= 12'hcf9;
793: out3 <= 12'hcf7;
794: out3 <= 12'hcf5;
795: out3 <= 12'hcf2;
796: out3 <= 12'hcf0;
797: out3 <= 12'hcee;
798: out3 <= 12'hcec;
799: out3 <= 12'hcea;
800: out3 <= 12'hce8;
801: out3 <= 12'hce6;
802: out3 <= 12'hce4;
803: out3 <= 12'hce2;
804: out3 <= 12'hce1;
805: out3 <= 12'hcdf;
806: out3 <= 12'hcdd;
807: out3 <= 12'hcdb;
808: out3 <= 12'hcd9;
809: out3 <= 12'hcd7;
810: out3 <= 12'hcd5;
811: out3 <= 12'hcd3;
812: out3 <= 12'hcd1;
813: out3 <= 12'hccf;
814: out3 <= 12'hccd;
815: out3 <= 12'hccb;
816: out3 <= 12'hcca;
817: out3 <= 12'hcc8;
818: out3 <= 12'hcc6;
819: out3 <= 12'hcc4;
820: out3 <= 12'hcc2;
821: out3 <= 12'hcc0;
822: out3 <= 12'hcbe;
823: out3 <= 12'hcbd;
824: out3 <= 12'hcbb;
825: out3 <= 12'hcb9;
826: out3 <= 12'hcb7;
827: out3 <= 12'hcb5;
828: out3 <= 12'hcb4;
829: out3 <= 12'hcb2;
830: out3 <= 12'hcb0;
831: out3 <= 12'hcae;
832: out3 <= 12'hcad;
833: out3 <= 12'hcab;
834: out3 <= 12'hca9;
835: out3 <= 12'hca7;
836: out3 <= 12'hca6;
837: out3 <= 12'hca4;
838: out3 <= 12'hca2;
839: out3 <= 12'hca1;
840: out3 <= 12'hc9f;
841: out3 <= 12'hc9d;
842: out3 <= 12'hc9c;
843: out3 <= 12'hc9a;
844: out3 <= 12'hc98;
845: out3 <= 12'hc97;
846: out3 <= 12'hc95;
847: out3 <= 12'hc93;
848: out3 <= 12'hc92;
849: out3 <= 12'hc90;
850: out3 <= 12'hc8e;
851: out3 <= 12'hc8d;
852: out3 <= 12'hc8b;
853: out3 <= 12'hc8a;
854: out3 <= 12'hc88;
855: out3 <= 12'hc87;
856: out3 <= 12'hc85;
857: out3 <= 12'hc83;
858: out3 <= 12'hc82;
859: out3 <= 12'hc80;
860: out3 <= 12'hc7f;
861: out3 <= 12'hc7d;
862: out3 <= 12'hc7c;
863: out3 <= 12'hc7a;
864: out3 <= 12'hc79;
865: out3 <= 12'hc77;
866: out3 <= 12'hc76;
867: out3 <= 12'hc75;
868: out3 <= 12'hc73;
869: out3 <= 12'hc72;
870: out3 <= 12'hc70;
871: out3 <= 12'hc6f;
872: out3 <= 12'hc6d;
873: out3 <= 12'hc6c;
874: out3 <= 12'hc6b;
875: out3 <= 12'hc69;
876: out3 <= 12'hc68;
877: out3 <= 12'hc66;
878: out3 <= 12'hc65;
879: out3 <= 12'hc64;
880: out3 <= 12'hc62;
881: out3 <= 12'hc61;
882: out3 <= 12'hc60;
883: out3 <= 12'hc5e;
884: out3 <= 12'hc5d;
885: out3 <= 12'hc5c;
886: out3 <= 12'hc5a;
887: out3 <= 12'hc59;
888: out3 <= 12'hc58;
889: out3 <= 12'hc57;
890: out3 <= 12'hc55;
891: out3 <= 12'hc54;
892: out3 <= 12'hc53;
893: out3 <= 12'hc52;
894: out3 <= 12'hc50;
895: out3 <= 12'hc4f;
896: out3 <= 12'hc4e;
897: out3 <= 12'hc4d;
898: out3 <= 12'hc4c;
899: out3 <= 12'hc4a;
900: out3 <= 12'hc49;
901: out3 <= 12'hc48;
902: out3 <= 12'hc47;
903: out3 <= 12'hc46;
904: out3 <= 12'hc45;
905: out3 <= 12'hc43;
906: out3 <= 12'hc42;
907: out3 <= 12'hc41;
908: out3 <= 12'hc40;
909: out3 <= 12'hc3f;
910: out3 <= 12'hc3e;
911: out3 <= 12'hc3d;
912: out3 <= 12'hc3c;
913: out3 <= 12'hc3b;
914: out3 <= 12'hc3a;
915: out3 <= 12'hc39;
916: out3 <= 12'hc38;
917: out3 <= 12'hc37;
918: out3 <= 12'hc36;
919: out3 <= 12'hc35;
920: out3 <= 12'hc34;
921: out3 <= 12'hc33;
922: out3 <= 12'hc32;
923: out3 <= 12'hc31;
924: out3 <= 12'hc30;
925: out3 <= 12'hc2f;
926: out3 <= 12'hc2e;
927: out3 <= 12'hc2d;
928: out3 <= 12'hc2c;
929: out3 <= 12'hc2b;
930: out3 <= 12'hc2a;
931: out3 <= 12'hc29;
932: out3 <= 12'hc29;
933: out3 <= 12'hc28;
934: out3 <= 12'hc27;
935: out3 <= 12'hc26;
936: out3 <= 12'hc25;
937: out3 <= 12'hc24;
938: out3 <= 12'hc23;
939: out3 <= 12'hc23;
940: out3 <= 12'hc22;
941: out3 <= 12'hc21;
942: out3 <= 12'hc20;
943: out3 <= 12'hc1f;
944: out3 <= 12'hc1f;
945: out3 <= 12'hc1e;
946: out3 <= 12'hc1d;
947: out3 <= 12'hc1c;
948: out3 <= 12'hc1c;
949: out3 <= 12'hc1b;
950: out3 <= 12'hc1a;
951: out3 <= 12'hc1a;
952: out3 <= 12'hc19;
953: out3 <= 12'hc18;
954: out3 <= 12'hc18;
955: out3 <= 12'hc17;
956: out3 <= 12'hc16;
957: out3 <= 12'hc16;
958: out3 <= 12'hc15;
959: out3 <= 12'hc14;
960: out3 <= 12'hc14;
961: out3 <= 12'hc13;
962: out3 <= 12'hc12;
963: out3 <= 12'hc12;
964: out3 <= 12'hc11;
965: out3 <= 12'hc11;
966: out3 <= 12'hc10;
967: out3 <= 12'hc10;
968: out3 <= 12'hc0f;
969: out3 <= 12'hc0f;
970: out3 <= 12'hc0e;
971: out3 <= 12'hc0e;
972: out3 <= 12'hc0d;
973: out3 <= 12'hc0d;
974: out3 <= 12'hc0c;
975: out3 <= 12'hc0c;
976: out3 <= 12'hc0b;
977: out3 <= 12'hc0b;
978: out3 <= 12'hc0a;
979: out3 <= 12'hc0a;
980: out3 <= 12'hc09;
981: out3 <= 12'hc09;
982: out3 <= 12'hc08;
983: out3 <= 12'hc08;
984: out3 <= 12'hc08;
985: out3 <= 12'hc07;
986: out3 <= 12'hc07;
987: out3 <= 12'hc07;
988: out3 <= 12'hc06;
989: out3 <= 12'hc06;
990: out3 <= 12'hc06;
991: out3 <= 12'hc05;
992: out3 <= 12'hc05;
993: out3 <= 12'hc05;
994: out3 <= 12'hc04;
995: out3 <= 12'hc04;
996: out3 <= 12'hc04;
997: out3 <= 12'hc04;
998: out3 <= 12'hc03;
999: out3 <= 12'hc03;
1000: out3 <= 12'hc03;
1001: out3 <= 12'hc03;
1002: out3 <= 12'hc02;
1003: out3 <= 12'hc02;
1004: out3 <= 12'hc02;
1005: out3 <= 12'hc02;
1006: out3 <= 12'hc02;
1007: out3 <= 12'hc01;
1008: out3 <= 12'hc01;
1009: out3 <= 12'hc01;
1010: out3 <= 12'hc01;
1011: out3 <= 12'hc01;
1012: out3 <= 12'hc01;
1013: out3 <= 12'hc01;
1014: out3 <= 12'hc00;
1015: out3 <= 12'hc00;
1016: out3 <= 12'hc00;
1017: out3 <= 12'hc00;
1018: out3 <= 12'hc00;
1019: out3 <= 12'hc00;
1020: out3 <= 12'hc00;
1021: out3 <= 12'hc00;
1022: out3 <= 12'hc00;
1023: out3 <= 12'hc00;
1024: out3 <= 12'h400;
1025: out3 <= 12'h400;
1026: out3 <= 12'h400;
1027: out3 <= 12'h400;
1028: out3 <= 12'h400;
1029: out3 <= 12'h400;
1030: out3 <= 12'h3ff;
1031: out3 <= 12'h3ff;
1032: out3 <= 12'h3ff;
1033: out3 <= 12'h3fe;
1034: out3 <= 12'h3fe;
1035: out3 <= 12'h3fe;
1036: out3 <= 12'h3fd;
1037: out3 <= 12'h3fd;
1038: out3 <= 12'h3fc;
1039: out3 <= 12'h3fc;
1040: out3 <= 12'h3fb;
1041: out3 <= 12'h3fa;
1042: out3 <= 12'h3fa;
1043: out3 <= 12'h3f9;
1044: out3 <= 12'h3f8;
1045: out3 <= 12'h3f8;
1046: out3 <= 12'h3f7;
1047: out3 <= 12'h3f6;
1048: out3 <= 12'h3f5;
1049: out3 <= 12'h3f4;
1050: out3 <= 12'h3f3;
1051: out3 <= 12'h3f2;
1052: out3 <= 12'h3f1;
1053: out3 <= 12'h3f0;
1054: out3 <= 12'h3ef;
1055: out3 <= 12'h3ee;
1056: out3 <= 12'h3ec;
1057: out3 <= 12'h3eb;
1058: out3 <= 12'h3ea;
1059: out3 <= 12'h3e8;
1060: out3 <= 12'h3e7;
1061: out3 <= 12'h3e6;
1062: out3 <= 12'h3e4;
1063: out3 <= 12'h3e3;
1064: out3 <= 12'h3e1;
1065: out3 <= 12'h3e0;
1066: out3 <= 12'h3de;
1067: out3 <= 12'h3dd;
1068: out3 <= 12'h3db;
1069: out3 <= 12'h3d9;
1070: out3 <= 12'h3d7;
1071: out3 <= 12'h3d6;
1072: out3 <= 12'h3d4;
1073: out3 <= 12'h3d2;
1074: out3 <= 12'h3d0;
1075: out3 <= 12'h3ce;
1076: out3 <= 12'h3cc;
1077: out3 <= 12'h3ca;
1078: out3 <= 12'h3c8;
1079: out3 <= 12'h3c6;
1080: out3 <= 12'h3c4;
1081: out3 <= 12'h3c2;
1082: out3 <= 12'h3c0;
1083: out3 <= 12'h3be;
1084: out3 <= 12'h3bb;
1085: out3 <= 12'h3b9;
1086: out3 <= 12'h3b7;
1087: out3 <= 12'h3b4;
1088: out3 <= 12'h3b2;
1089: out3 <= 12'h3b0;
1090: out3 <= 12'h3ad;
1091: out3 <= 12'h3ab;
1092: out3 <= 12'h3a8;
1093: out3 <= 12'h3a6;
1094: out3 <= 12'h3a3;
1095: out3 <= 12'h3a0;
1096: out3 <= 12'h39e;
1097: out3 <= 12'h39b;
1098: out3 <= 12'h398;
1099: out3 <= 12'h395;
1100: out3 <= 12'h393;
1101: out3 <= 12'h390;
1102: out3 <= 12'h38d;
1103: out3 <= 12'h38a;
1104: out3 <= 12'h387;
1105: out3 <= 12'h384;
1106: out3 <= 12'h381;
1107: out3 <= 12'h37e;
1108: out3 <= 12'h37b;
1109: out3 <= 12'h378;
1110: out3 <= 12'h375;
1111: out3 <= 12'h372;
1112: out3 <= 12'h36e;
1113: out3 <= 12'h36b;
1114: out3 <= 12'h368;
1115: out3 <= 12'h364;
1116: out3 <= 12'h361;
1117: out3 <= 12'h35e;
1118: out3 <= 12'h35a;
1119: out3 <= 12'h357;
1120: out3 <= 12'h353;
1121: out3 <= 12'h350;
1122: out3 <= 12'h34c;
1123: out3 <= 12'h349;
1124: out3 <= 12'h345;
1125: out3 <= 12'h342;
1126: out3 <= 12'h33e;
1127: out3 <= 12'h33a;
1128: out3 <= 12'h336;
1129: out3 <= 12'h333;
1130: out3 <= 12'h32f;
1131: out3 <= 12'h32b;
1132: out3 <= 12'h327;
1133: out3 <= 12'h323;
1134: out3 <= 12'h31f;
1135: out3 <= 12'h31c;
1136: out3 <= 12'h318;
1137: out3 <= 12'h314;
1138: out3 <= 12'h310;
1139: out3 <= 12'h30b;
1140: out3 <= 12'h307;
1141: out3 <= 12'h303;
1142: out3 <= 12'h2ff;
1143: out3 <= 12'h2fb;
1144: out3 <= 12'h2f7;
1145: out3 <= 12'h2f3;
1146: out3 <= 12'h2ee;
1147: out3 <= 12'h2ea;
1148: out3 <= 12'h2e6;
1149: out3 <= 12'h2e1;
1150: out3 <= 12'h2dd;
1151: out3 <= 12'h2d9;
1152: out3 <= 12'h2d4;
1153: out3 <= 12'h2d0;
1154: out3 <= 12'h2cb;
1155: out3 <= 12'h2c7;
1156: out3 <= 12'h2c2;
1157: out3 <= 12'h2be;
1158: out3 <= 12'h2b9;
1159: out3 <= 12'h2b4;
1160: out3 <= 12'h2b0;
1161: out3 <= 12'h2ab;
1162: out3 <= 12'h2a6;
1163: out3 <= 12'h2a2;
1164: out3 <= 12'h29d;
1165: out3 <= 12'h298;
1166: out3 <= 12'h293;
1167: out3 <= 12'h28e;
1168: out3 <= 12'h28a;
1169: out3 <= 12'h285;
1170: out3 <= 12'h280;
1171: out3 <= 12'h27b;
1172: out3 <= 12'h276;
1173: out3 <= 12'h271;
1174: out3 <= 12'h26c;
1175: out3 <= 12'h267;
1176: out3 <= 12'h262;
1177: out3 <= 12'h25d;
1178: out3 <= 12'h258;
1179: out3 <= 12'h253;
1180: out3 <= 12'h24e;
1181: out3 <= 12'h248;
1182: out3 <= 12'h243;
1183: out3 <= 12'h23e;
1184: out3 <= 12'h239;
1185: out3 <= 12'h234;
1186: out3 <= 12'h22e;
1187: out3 <= 12'h229;
1188: out3 <= 12'h224;
1189: out3 <= 12'h21f;
1190: out3 <= 12'h219;
1191: out3 <= 12'h214;
1192: out3 <= 12'h20e;
1193: out3 <= 12'h209;
1194: out3 <= 12'h204;
1195: out3 <= 12'h1fe;
1196: out3 <= 12'h1f9;
1197: out3 <= 12'h1f3;
1198: out3 <= 12'h1ee;
1199: out3 <= 12'h1e8;
1200: out3 <= 12'h1e3;
1201: out3 <= 12'h1dd;
1202: out3 <= 12'h1d8;
1203: out3 <= 12'h1d2;
1204: out3 <= 12'h1cc;
1205: out3 <= 12'h1c7;
1206: out3 <= 12'h1c1;
1207: out3 <= 12'h1bb;
1208: out3 <= 12'h1b6;
1209: out3 <= 12'h1b0;
1210: out3 <= 12'h1aa;
1211: out3 <= 12'h1a5;
1212: out3 <= 12'h19f;
1213: out3 <= 12'h199;
1214: out3 <= 12'h193;
1215: out3 <= 12'h18e;
1216: out3 <= 12'h188;
1217: out3 <= 12'h182;
1218: out3 <= 12'h17c;
1219: out3 <= 12'h176;
1220: out3 <= 12'h171;
1221: out3 <= 12'h16b;
1222: out3 <= 12'h165;
1223: out3 <= 12'h15f;
1224: out3 <= 12'h159;
1225: out3 <= 12'h153;
1226: out3 <= 12'h14d;
1227: out3 <= 12'h147;
1228: out3 <= 12'h141;
1229: out3 <= 12'h13b;
1230: out3 <= 12'h135;
1231: out3 <= 12'h12f;
1232: out3 <= 12'h129;
1233: out3 <= 12'h123;
1234: out3 <= 12'h11d;
1235: out3 <= 12'h117;
1236: out3 <= 12'h111;
1237: out3 <= 12'h10b;
1238: out3 <= 12'h105;
1239: out3 <= 12'hff;
1240: out3 <= 12'hf9;
1241: out3 <= 12'hf3;
1242: out3 <= 12'hed;
1243: out3 <= 12'he6;
1244: out3 <= 12'he0;
1245: out3 <= 12'hda;
1246: out3 <= 12'hd4;
1247: out3 <= 12'hce;
1248: out3 <= 12'hc8;
1249: out3 <= 12'hc2;
1250: out3 <= 12'hbb;
1251: out3 <= 12'hb5;
1252: out3 <= 12'haf;
1253: out3 <= 12'ha9;
1254: out3 <= 12'ha3;
1255: out3 <= 12'h9c;
1256: out3 <= 12'h96;
1257: out3 <= 12'h90;
1258: out3 <= 12'h8a;
1259: out3 <= 12'h84;
1260: out3 <= 12'h7d;
1261: out3 <= 12'h77;
1262: out3 <= 12'h71;
1263: out3 <= 12'h6b;
1264: out3 <= 12'h64;
1265: out3 <= 12'h5e;
1266: out3 <= 12'h58;
1267: out3 <= 12'h52;
1268: out3 <= 12'h4b;
1269: out3 <= 12'h45;
1270: out3 <= 12'h3f;
1271: out3 <= 12'h39;
1272: out3 <= 12'h32;
1273: out3 <= 12'h2c;
1274: out3 <= 12'h26;
1275: out3 <= 12'h1f;
1276: out3 <= 12'h19;
1277: out3 <= 12'h13;
1278: out3 <= 12'hd;
1279: out3 <= 12'h6;
1280: out3 <= 12'h0;
1281: out3 <= 12'hffa;
1282: out3 <= 12'hff3;
1283: out3 <= 12'hfed;
1284: out3 <= 12'hfe7;
1285: out3 <= 12'hfe1;
1286: out3 <= 12'hfda;
1287: out3 <= 12'hfd4;
1288: out3 <= 12'hfce;
1289: out3 <= 12'hfc7;
1290: out3 <= 12'hfc1;
1291: out3 <= 12'hfbb;
1292: out3 <= 12'hfb5;
1293: out3 <= 12'hfae;
1294: out3 <= 12'hfa8;
1295: out3 <= 12'hfa2;
1296: out3 <= 12'hf9c;
1297: out3 <= 12'hf95;
1298: out3 <= 12'hf8f;
1299: out3 <= 12'hf89;
1300: out3 <= 12'hf83;
1301: out3 <= 12'hf7c;
1302: out3 <= 12'hf76;
1303: out3 <= 12'hf70;
1304: out3 <= 12'hf6a;
1305: out3 <= 12'hf64;
1306: out3 <= 12'hf5d;
1307: out3 <= 12'hf57;
1308: out3 <= 12'hf51;
1309: out3 <= 12'hf4b;
1310: out3 <= 12'hf45;
1311: out3 <= 12'hf3e;
1312: out3 <= 12'hf38;
1313: out3 <= 12'hf32;
1314: out3 <= 12'hf2c;
1315: out3 <= 12'hf26;
1316: out3 <= 12'hf20;
1317: out3 <= 12'hf1a;
1318: out3 <= 12'hf13;
1319: out3 <= 12'hf0d;
1320: out3 <= 12'hf07;
1321: out3 <= 12'hf01;
1322: out3 <= 12'hefb;
1323: out3 <= 12'hef5;
1324: out3 <= 12'heef;
1325: out3 <= 12'hee9;
1326: out3 <= 12'hee3;
1327: out3 <= 12'hedd;
1328: out3 <= 12'hed7;
1329: out3 <= 12'hed1;
1330: out3 <= 12'hecb;
1331: out3 <= 12'hec5;
1332: out3 <= 12'hebf;
1333: out3 <= 12'heb9;
1334: out3 <= 12'heb3;
1335: out3 <= 12'head;
1336: out3 <= 12'hea7;
1337: out3 <= 12'hea1;
1338: out3 <= 12'he9b;
1339: out3 <= 12'he95;
1340: out3 <= 12'he8f;
1341: out3 <= 12'he8a;
1342: out3 <= 12'he84;
1343: out3 <= 12'he7e;
1344: out3 <= 12'he78;
1345: out3 <= 12'he72;
1346: out3 <= 12'he6d;
1347: out3 <= 12'he67;
1348: out3 <= 12'he61;
1349: out3 <= 12'he5b;
1350: out3 <= 12'he56;
1351: out3 <= 12'he50;
1352: out3 <= 12'he4a;
1353: out3 <= 12'he45;
1354: out3 <= 12'he3f;
1355: out3 <= 12'he39;
1356: out3 <= 12'he34;
1357: out3 <= 12'he2e;
1358: out3 <= 12'he28;
1359: out3 <= 12'he23;
1360: out3 <= 12'he1d;
1361: out3 <= 12'he18;
1362: out3 <= 12'he12;
1363: out3 <= 12'he0d;
1364: out3 <= 12'he07;
1365: out3 <= 12'he02;
1366: out3 <= 12'hdfc;
1367: out3 <= 12'hdf7;
1368: out3 <= 12'hdf2;
1369: out3 <= 12'hdec;
1370: out3 <= 12'hde7;
1371: out3 <= 12'hde1;
1372: out3 <= 12'hddc;
1373: out3 <= 12'hdd7;
1374: out3 <= 12'hdd2;
1375: out3 <= 12'hdcc;
1376: out3 <= 12'hdc7;
1377: out3 <= 12'hdc2;
1378: out3 <= 12'hdbd;
1379: out3 <= 12'hdb8;
1380: out3 <= 12'hdb2;
1381: out3 <= 12'hdad;
1382: out3 <= 12'hda8;
1383: out3 <= 12'hda3;
1384: out3 <= 12'hd9e;
1385: out3 <= 12'hd99;
1386: out3 <= 12'hd94;
1387: out3 <= 12'hd8f;
1388: out3 <= 12'hd8a;
1389: out3 <= 12'hd85;
1390: out3 <= 12'hd80;
1391: out3 <= 12'hd7b;
1392: out3 <= 12'hd76;
1393: out3 <= 12'hd72;
1394: out3 <= 12'hd6d;
1395: out3 <= 12'hd68;
1396: out3 <= 12'hd63;
1397: out3 <= 12'hd5e;
1398: out3 <= 12'hd5a;
1399: out3 <= 12'hd55;
1400: out3 <= 12'hd50;
1401: out3 <= 12'hd4c;
1402: out3 <= 12'hd47;
1403: out3 <= 12'hd42;
1404: out3 <= 12'hd3e;
1405: out3 <= 12'hd39;
1406: out3 <= 12'hd35;
1407: out3 <= 12'hd30;
1408: out3 <= 12'hd2c;
1409: out3 <= 12'hd27;
1410: out3 <= 12'hd23;
1411: out3 <= 12'hd1f;
1412: out3 <= 12'hd1a;
1413: out3 <= 12'hd16;
1414: out3 <= 12'hd12;
1415: out3 <= 12'hd0d;
1416: out3 <= 12'hd09;
1417: out3 <= 12'hd05;
1418: out3 <= 12'hd01;
1419: out3 <= 12'hcfd;
1420: out3 <= 12'hcf9;
1421: out3 <= 12'hcf5;
1422: out3 <= 12'hcf0;
1423: out3 <= 12'hcec;
1424: out3 <= 12'hce8;
1425: out3 <= 12'hce4;
1426: out3 <= 12'hce1;
1427: out3 <= 12'hcdd;
1428: out3 <= 12'hcd9;
1429: out3 <= 12'hcd5;
1430: out3 <= 12'hcd1;
1431: out3 <= 12'hccd;
1432: out3 <= 12'hcca;
1433: out3 <= 12'hcc6;
1434: out3 <= 12'hcc2;
1435: out3 <= 12'hcbe;
1436: out3 <= 12'hcbb;
1437: out3 <= 12'hcb7;
1438: out3 <= 12'hcb4;
1439: out3 <= 12'hcb0;
1440: out3 <= 12'hcad;
1441: out3 <= 12'hca9;
1442: out3 <= 12'hca6;
1443: out3 <= 12'hca2;
1444: out3 <= 12'hc9f;
1445: out3 <= 12'hc9c;
1446: out3 <= 12'hc98;
1447: out3 <= 12'hc95;
1448: out3 <= 12'hc92;
1449: out3 <= 12'hc8e;
1450: out3 <= 12'hc8b;
1451: out3 <= 12'hc88;
1452: out3 <= 12'hc85;
1453: out3 <= 12'hc82;
1454: out3 <= 12'hc7f;
1455: out3 <= 12'hc7c;
1456: out3 <= 12'hc79;
1457: out3 <= 12'hc76;
1458: out3 <= 12'hc73;
1459: out3 <= 12'hc70;
1460: out3 <= 12'hc6d;
1461: out3 <= 12'hc6b;
1462: out3 <= 12'hc68;
1463: out3 <= 12'hc65;
1464: out3 <= 12'hc62;
1465: out3 <= 12'hc60;
1466: out3 <= 12'hc5d;
1467: out3 <= 12'hc5a;
1468: out3 <= 12'hc58;
1469: out3 <= 12'hc55;
1470: out3 <= 12'hc53;
1471: out3 <= 12'hc50;
1472: out3 <= 12'hc4e;
1473: out3 <= 12'hc4c;
1474: out3 <= 12'hc49;
1475: out3 <= 12'hc47;
1476: out3 <= 12'hc45;
1477: out3 <= 12'hc42;
1478: out3 <= 12'hc40;
1479: out3 <= 12'hc3e;
1480: out3 <= 12'hc3c;
1481: out3 <= 12'hc3a;
1482: out3 <= 12'hc38;
1483: out3 <= 12'hc36;
1484: out3 <= 12'hc34;
1485: out3 <= 12'hc32;
1486: out3 <= 12'hc30;
1487: out3 <= 12'hc2e;
1488: out3 <= 12'hc2c;
1489: out3 <= 12'hc2a;
1490: out3 <= 12'hc29;
1491: out3 <= 12'hc27;
1492: out3 <= 12'hc25;
1493: out3 <= 12'hc23;
1494: out3 <= 12'hc22;
1495: out3 <= 12'hc20;
1496: out3 <= 12'hc1f;
1497: out3 <= 12'hc1d;
1498: out3 <= 12'hc1c;
1499: out3 <= 12'hc1a;
1500: out3 <= 12'hc19;
1501: out3 <= 12'hc18;
1502: out3 <= 12'hc16;
1503: out3 <= 12'hc15;
1504: out3 <= 12'hc14;
1505: out3 <= 12'hc12;
1506: out3 <= 12'hc11;
1507: out3 <= 12'hc10;
1508: out3 <= 12'hc0f;
1509: out3 <= 12'hc0e;
1510: out3 <= 12'hc0d;
1511: out3 <= 12'hc0c;
1512: out3 <= 12'hc0b;
1513: out3 <= 12'hc0a;
1514: out3 <= 12'hc09;
1515: out3 <= 12'hc08;
1516: out3 <= 12'hc08;
1517: out3 <= 12'hc07;
1518: out3 <= 12'hc06;
1519: out3 <= 12'hc06;
1520: out3 <= 12'hc05;
1521: out3 <= 12'hc04;
1522: out3 <= 12'hc04;
1523: out3 <= 12'hc03;
1524: out3 <= 12'hc03;
1525: out3 <= 12'hc02;
1526: out3 <= 12'hc02;
1527: out3 <= 12'hc02;
1528: out3 <= 12'hc01;
1529: out3 <= 12'hc01;
1530: out3 <= 12'hc01;
1531: out3 <= 12'hc00;
1532: out3 <= 12'hc00;
1533: out3 <= 12'hc00;
1534: out3 <= 12'hc00;
1535: out3 <= 12'hc00;
1536: out3 <= 12'hc00;
1537: out3 <= 12'hc00;
1538: out3 <= 12'hc00;
1539: out3 <= 12'hc00;
1540: out3 <= 12'hc00;
1541: out3 <= 12'hc00;
1542: out3 <= 12'hc01;
1543: out3 <= 12'hc01;
1544: out3 <= 12'hc01;
1545: out3 <= 12'hc02;
1546: out3 <= 12'hc02;
1547: out3 <= 12'hc02;
1548: out3 <= 12'hc03;
1549: out3 <= 12'hc03;
1550: out3 <= 12'hc04;
1551: out3 <= 12'hc04;
1552: out3 <= 12'hc05;
1553: out3 <= 12'hc06;
1554: out3 <= 12'hc06;
1555: out3 <= 12'hc07;
1556: out3 <= 12'hc08;
1557: out3 <= 12'hc08;
1558: out3 <= 12'hc09;
1559: out3 <= 12'hc0a;
1560: out3 <= 12'hc0b;
1561: out3 <= 12'hc0c;
1562: out3 <= 12'hc0d;
1563: out3 <= 12'hc0e;
1564: out3 <= 12'hc0f;
1565: out3 <= 12'hc10;
1566: out3 <= 12'hc11;
1567: out3 <= 12'hc12;
1568: out3 <= 12'hc14;
1569: out3 <= 12'hc15;
1570: out3 <= 12'hc16;
1571: out3 <= 12'hc18;
1572: out3 <= 12'hc19;
1573: out3 <= 12'hc1a;
1574: out3 <= 12'hc1c;
1575: out3 <= 12'hc1d;
1576: out3 <= 12'hc1f;
1577: out3 <= 12'hc20;
1578: out3 <= 12'hc22;
1579: out3 <= 12'hc23;
1580: out3 <= 12'hc25;
1581: out3 <= 12'hc27;
1582: out3 <= 12'hc29;
1583: out3 <= 12'hc2a;
1584: out3 <= 12'hc2c;
1585: out3 <= 12'hc2e;
1586: out3 <= 12'hc30;
1587: out3 <= 12'hc32;
1588: out3 <= 12'hc34;
1589: out3 <= 12'hc36;
1590: out3 <= 12'hc38;
1591: out3 <= 12'hc3a;
1592: out3 <= 12'hc3c;
1593: out3 <= 12'hc3e;
1594: out3 <= 12'hc40;
1595: out3 <= 12'hc42;
1596: out3 <= 12'hc45;
1597: out3 <= 12'hc47;
1598: out3 <= 12'hc49;
1599: out3 <= 12'hc4c;
1600: out3 <= 12'hc4e;
1601: out3 <= 12'hc50;
1602: out3 <= 12'hc53;
1603: out3 <= 12'hc55;
1604: out3 <= 12'hc58;
1605: out3 <= 12'hc5a;
1606: out3 <= 12'hc5d;
1607: out3 <= 12'hc60;
1608: out3 <= 12'hc62;
1609: out3 <= 12'hc65;
1610: out3 <= 12'hc68;
1611: out3 <= 12'hc6b;
1612: out3 <= 12'hc6d;
1613: out3 <= 12'hc70;
1614: out3 <= 12'hc73;
1615: out3 <= 12'hc76;
1616: out3 <= 12'hc79;
1617: out3 <= 12'hc7c;
1618: out3 <= 12'hc7f;
1619: out3 <= 12'hc82;
1620: out3 <= 12'hc85;
1621: out3 <= 12'hc88;
1622: out3 <= 12'hc8b;
1623: out3 <= 12'hc8e;
1624: out3 <= 12'hc92;
1625: out3 <= 12'hc95;
1626: out3 <= 12'hc98;
1627: out3 <= 12'hc9c;
1628: out3 <= 12'hc9f;
1629: out3 <= 12'hca2;
1630: out3 <= 12'hca6;
1631: out3 <= 12'hca9;
1632: out3 <= 12'hcad;
1633: out3 <= 12'hcb0;
1634: out3 <= 12'hcb4;
1635: out3 <= 12'hcb7;
1636: out3 <= 12'hcbb;
1637: out3 <= 12'hcbe;
1638: out3 <= 12'hcc2;
1639: out3 <= 12'hcc6;
1640: out3 <= 12'hcca;
1641: out3 <= 12'hccd;
1642: out3 <= 12'hcd1;
1643: out3 <= 12'hcd5;
1644: out3 <= 12'hcd9;
1645: out3 <= 12'hcdd;
1646: out3 <= 12'hce1;
1647: out3 <= 12'hce4;
1648: out3 <= 12'hce8;
1649: out3 <= 12'hcec;
1650: out3 <= 12'hcf0;
1651: out3 <= 12'hcf5;
1652: out3 <= 12'hcf9;
1653: out3 <= 12'hcfd;
1654: out3 <= 12'hd01;
1655: out3 <= 12'hd05;
1656: out3 <= 12'hd09;
1657: out3 <= 12'hd0d;
1658: out3 <= 12'hd12;
1659: out3 <= 12'hd16;
1660: out3 <= 12'hd1a;
1661: out3 <= 12'hd1f;
1662: out3 <= 12'hd23;
1663: out3 <= 12'hd27;
1664: out3 <= 12'hd2c;
1665: out3 <= 12'hd30;
1666: out3 <= 12'hd35;
1667: out3 <= 12'hd39;
1668: out3 <= 12'hd3e;
1669: out3 <= 12'hd42;
1670: out3 <= 12'hd47;
1671: out3 <= 12'hd4c;
1672: out3 <= 12'hd50;
1673: out3 <= 12'hd55;
1674: out3 <= 12'hd5a;
1675: out3 <= 12'hd5e;
1676: out3 <= 12'hd63;
1677: out3 <= 12'hd68;
1678: out3 <= 12'hd6d;
1679: out3 <= 12'hd72;
1680: out3 <= 12'hd76;
1681: out3 <= 12'hd7b;
1682: out3 <= 12'hd80;
1683: out3 <= 12'hd85;
1684: out3 <= 12'hd8a;
1685: out3 <= 12'hd8f;
1686: out3 <= 12'hd94;
1687: out3 <= 12'hd99;
1688: out3 <= 12'hd9e;
1689: out3 <= 12'hda3;
1690: out3 <= 12'hda8;
1691: out3 <= 12'hdad;
1692: out3 <= 12'hdb2;
1693: out3 <= 12'hdb8;
1694: out3 <= 12'hdbd;
1695: out3 <= 12'hdc2;
1696: out3 <= 12'hdc7;
1697: out3 <= 12'hdcc;
1698: out3 <= 12'hdd2;
1699: out3 <= 12'hdd7;
1700: out3 <= 12'hddc;
1701: out3 <= 12'hde1;
1702: out3 <= 12'hde7;
1703: out3 <= 12'hdec;
1704: out3 <= 12'hdf2;
1705: out3 <= 12'hdf7;
1706: out3 <= 12'hdfc;
1707: out3 <= 12'he02;
1708: out3 <= 12'he07;
1709: out3 <= 12'he0d;
1710: out3 <= 12'he12;
1711: out3 <= 12'he18;
1712: out3 <= 12'he1d;
1713: out3 <= 12'he23;
1714: out3 <= 12'he28;
1715: out3 <= 12'he2e;
1716: out3 <= 12'he34;
1717: out3 <= 12'he39;
1718: out3 <= 12'he3f;
1719: out3 <= 12'he45;
1720: out3 <= 12'he4a;
1721: out3 <= 12'he50;
1722: out3 <= 12'he56;
1723: out3 <= 12'he5b;
1724: out3 <= 12'he61;
1725: out3 <= 12'he67;
1726: out3 <= 12'he6d;
1727: out3 <= 12'he72;
1728: out3 <= 12'he78;
1729: out3 <= 12'he7e;
1730: out3 <= 12'he84;
1731: out3 <= 12'he8a;
1732: out3 <= 12'he8f;
1733: out3 <= 12'he95;
1734: out3 <= 12'he9b;
1735: out3 <= 12'hea1;
1736: out3 <= 12'hea7;
1737: out3 <= 12'head;
1738: out3 <= 12'heb3;
1739: out3 <= 12'heb9;
1740: out3 <= 12'hebf;
1741: out3 <= 12'hec5;
1742: out3 <= 12'hecb;
1743: out3 <= 12'hed1;
1744: out3 <= 12'hed7;
1745: out3 <= 12'hedd;
1746: out3 <= 12'hee3;
1747: out3 <= 12'hee9;
1748: out3 <= 12'heef;
1749: out3 <= 12'hef5;
1750: out3 <= 12'hefb;
1751: out3 <= 12'hf01;
1752: out3 <= 12'hf07;
1753: out3 <= 12'hf0d;
1754: out3 <= 12'hf13;
1755: out3 <= 12'hf1a;
1756: out3 <= 12'hf20;
1757: out3 <= 12'hf26;
1758: out3 <= 12'hf2c;
1759: out3 <= 12'hf32;
1760: out3 <= 12'hf38;
1761: out3 <= 12'hf3e;
1762: out3 <= 12'hf45;
1763: out3 <= 12'hf4b;
1764: out3 <= 12'hf51;
1765: out3 <= 12'hf57;
1766: out3 <= 12'hf5d;
1767: out3 <= 12'hf64;
1768: out3 <= 12'hf6a;
1769: out3 <= 12'hf70;
1770: out3 <= 12'hf76;
1771: out3 <= 12'hf7c;
1772: out3 <= 12'hf83;
1773: out3 <= 12'hf89;
1774: out3 <= 12'hf8f;
1775: out3 <= 12'hf95;
1776: out3 <= 12'hf9c;
1777: out3 <= 12'hfa2;
1778: out3 <= 12'hfa8;
1779: out3 <= 12'hfae;
1780: out3 <= 12'hfb5;
1781: out3 <= 12'hfbb;
1782: out3 <= 12'hfc1;
1783: out3 <= 12'hfc7;
1784: out3 <= 12'hfce;
1785: out3 <= 12'hfd4;
1786: out3 <= 12'hfda;
1787: out3 <= 12'hfe1;
1788: out3 <= 12'hfe7;
1789: out3 <= 12'hfed;
1790: out3 <= 12'hff3;
1791: out3 <= 12'hffa;
1792: out3 <= 12'h0;
1793: out3 <= 12'h6;
1794: out3 <= 12'hd;
1795: out3 <= 12'h13;
1796: out3 <= 12'h19;
1797: out3 <= 12'h1f;
1798: out3 <= 12'h26;
1799: out3 <= 12'h2c;
1800: out3 <= 12'h32;
1801: out3 <= 12'h39;
1802: out3 <= 12'h3f;
1803: out3 <= 12'h45;
1804: out3 <= 12'h4b;
1805: out3 <= 12'h52;
1806: out3 <= 12'h58;
1807: out3 <= 12'h5e;
1808: out3 <= 12'h64;
1809: out3 <= 12'h6b;
1810: out3 <= 12'h71;
1811: out3 <= 12'h77;
1812: out3 <= 12'h7d;
1813: out3 <= 12'h84;
1814: out3 <= 12'h8a;
1815: out3 <= 12'h90;
1816: out3 <= 12'h96;
1817: out3 <= 12'h9c;
1818: out3 <= 12'ha3;
1819: out3 <= 12'ha9;
1820: out3 <= 12'haf;
1821: out3 <= 12'hb5;
1822: out3 <= 12'hbb;
1823: out3 <= 12'hc2;
1824: out3 <= 12'hc8;
1825: out3 <= 12'hce;
1826: out3 <= 12'hd4;
1827: out3 <= 12'hda;
1828: out3 <= 12'he0;
1829: out3 <= 12'he6;
1830: out3 <= 12'hed;
1831: out3 <= 12'hf3;
1832: out3 <= 12'hf9;
1833: out3 <= 12'hff;
1834: out3 <= 12'h105;
1835: out3 <= 12'h10b;
1836: out3 <= 12'h111;
1837: out3 <= 12'h117;
1838: out3 <= 12'h11d;
1839: out3 <= 12'h123;
1840: out3 <= 12'h129;
1841: out3 <= 12'h12f;
1842: out3 <= 12'h135;
1843: out3 <= 12'h13b;
1844: out3 <= 12'h141;
1845: out3 <= 12'h147;
1846: out3 <= 12'h14d;
1847: out3 <= 12'h153;
1848: out3 <= 12'h159;
1849: out3 <= 12'h15f;
1850: out3 <= 12'h165;
1851: out3 <= 12'h16b;
1852: out3 <= 12'h171;
1853: out3 <= 12'h176;
1854: out3 <= 12'h17c;
1855: out3 <= 12'h182;
1856: out3 <= 12'h188;
1857: out3 <= 12'h18e;
1858: out3 <= 12'h193;
1859: out3 <= 12'h199;
1860: out3 <= 12'h19f;
1861: out3 <= 12'h1a5;
1862: out3 <= 12'h1aa;
1863: out3 <= 12'h1b0;
1864: out3 <= 12'h1b6;
1865: out3 <= 12'h1bb;
1866: out3 <= 12'h1c1;
1867: out3 <= 12'h1c7;
1868: out3 <= 12'h1cc;
1869: out3 <= 12'h1d2;
1870: out3 <= 12'h1d8;
1871: out3 <= 12'h1dd;
1872: out3 <= 12'h1e3;
1873: out3 <= 12'h1e8;
1874: out3 <= 12'h1ee;
1875: out3 <= 12'h1f3;
1876: out3 <= 12'h1f9;
1877: out3 <= 12'h1fe;
1878: out3 <= 12'h204;
1879: out3 <= 12'h209;
1880: out3 <= 12'h20e;
1881: out3 <= 12'h214;
1882: out3 <= 12'h219;
1883: out3 <= 12'h21f;
1884: out3 <= 12'h224;
1885: out3 <= 12'h229;
1886: out3 <= 12'h22e;
1887: out3 <= 12'h234;
1888: out3 <= 12'h239;
1889: out3 <= 12'h23e;
1890: out3 <= 12'h243;
1891: out3 <= 12'h248;
1892: out3 <= 12'h24e;
1893: out3 <= 12'h253;
1894: out3 <= 12'h258;
1895: out3 <= 12'h25d;
1896: out3 <= 12'h262;
1897: out3 <= 12'h267;
1898: out3 <= 12'h26c;
1899: out3 <= 12'h271;
1900: out3 <= 12'h276;
1901: out3 <= 12'h27b;
1902: out3 <= 12'h280;
1903: out3 <= 12'h285;
1904: out3 <= 12'h28a;
1905: out3 <= 12'h28e;
1906: out3 <= 12'h293;
1907: out3 <= 12'h298;
1908: out3 <= 12'h29d;
1909: out3 <= 12'h2a2;
1910: out3 <= 12'h2a6;
1911: out3 <= 12'h2ab;
1912: out3 <= 12'h2b0;
1913: out3 <= 12'h2b4;
1914: out3 <= 12'h2b9;
1915: out3 <= 12'h2be;
1916: out3 <= 12'h2c2;
1917: out3 <= 12'h2c7;
1918: out3 <= 12'h2cb;
1919: out3 <= 12'h2d0;
1920: out3 <= 12'h2d4;
1921: out3 <= 12'h2d9;
1922: out3 <= 12'h2dd;
1923: out3 <= 12'h2e1;
1924: out3 <= 12'h2e6;
1925: out3 <= 12'h2ea;
1926: out3 <= 12'h2ee;
1927: out3 <= 12'h2f3;
1928: out3 <= 12'h2f7;
1929: out3 <= 12'h2fb;
1930: out3 <= 12'h2ff;
1931: out3 <= 12'h303;
1932: out3 <= 12'h307;
1933: out3 <= 12'h30b;
1934: out3 <= 12'h310;
1935: out3 <= 12'h314;
1936: out3 <= 12'h318;
1937: out3 <= 12'h31c;
1938: out3 <= 12'h31f;
1939: out3 <= 12'h323;
1940: out3 <= 12'h327;
1941: out3 <= 12'h32b;
1942: out3 <= 12'h32f;
1943: out3 <= 12'h333;
1944: out3 <= 12'h336;
1945: out3 <= 12'h33a;
1946: out3 <= 12'h33e;
1947: out3 <= 12'h342;
1948: out3 <= 12'h345;
1949: out3 <= 12'h349;
1950: out3 <= 12'h34c;
1951: out3 <= 12'h350;
1952: out3 <= 12'h353;
1953: out3 <= 12'h357;
1954: out3 <= 12'h35a;
1955: out3 <= 12'h35e;
1956: out3 <= 12'h361;
1957: out3 <= 12'h364;
1958: out3 <= 12'h368;
1959: out3 <= 12'h36b;
1960: out3 <= 12'h36e;
1961: out3 <= 12'h372;
1962: out3 <= 12'h375;
1963: out3 <= 12'h378;
1964: out3 <= 12'h37b;
1965: out3 <= 12'h37e;
1966: out3 <= 12'h381;
1967: out3 <= 12'h384;
1968: out3 <= 12'h387;
1969: out3 <= 12'h38a;
1970: out3 <= 12'h38d;
1971: out3 <= 12'h390;
1972: out3 <= 12'h393;
1973: out3 <= 12'h395;
1974: out3 <= 12'h398;
1975: out3 <= 12'h39b;
1976: out3 <= 12'h39e;
1977: out3 <= 12'h3a0;
1978: out3 <= 12'h3a3;
1979: out3 <= 12'h3a6;
1980: out3 <= 12'h3a8;
1981: out3 <= 12'h3ab;
1982: out3 <= 12'h3ad;
1983: out3 <= 12'h3b0;
1984: out3 <= 12'h3b2;
1985: out3 <= 12'h3b4;
1986: out3 <= 12'h3b7;
1987: out3 <= 12'h3b9;
1988: out3 <= 12'h3bb;
1989: out3 <= 12'h3be;
1990: out3 <= 12'h3c0;
1991: out3 <= 12'h3c2;
1992: out3 <= 12'h3c4;
1993: out3 <= 12'h3c6;
1994: out3 <= 12'h3c8;
1995: out3 <= 12'h3ca;
1996: out3 <= 12'h3cc;
1997: out3 <= 12'h3ce;
1998: out3 <= 12'h3d0;
1999: out3 <= 12'h3d2;
2000: out3 <= 12'h3d4;
2001: out3 <= 12'h3d6;
2002: out3 <= 12'h3d7;
2003: out3 <= 12'h3d9;
2004: out3 <= 12'h3db;
2005: out3 <= 12'h3dd;
2006: out3 <= 12'h3de;
2007: out3 <= 12'h3e0;
2008: out3 <= 12'h3e1;
2009: out3 <= 12'h3e3;
2010: out3 <= 12'h3e4;
2011: out3 <= 12'h3e6;
2012: out3 <= 12'h3e7;
2013: out3 <= 12'h3e8;
2014: out3 <= 12'h3ea;
2015: out3 <= 12'h3eb;
2016: out3 <= 12'h3ec;
2017: out3 <= 12'h3ee;
2018: out3 <= 12'h3ef;
2019: out3 <= 12'h3f0;
2020: out3 <= 12'h3f1;
2021: out3 <= 12'h3f2;
2022: out3 <= 12'h3f3;
2023: out3 <= 12'h3f4;
2024: out3 <= 12'h3f5;
2025: out3 <= 12'h3f6;
2026: out3 <= 12'h3f7;
2027: out3 <= 12'h3f8;
2028: out3 <= 12'h3f8;
2029: out3 <= 12'h3f9;
2030: out3 <= 12'h3fa;
2031: out3 <= 12'h3fa;
2032: out3 <= 12'h3fb;
2033: out3 <= 12'h3fc;
2034: out3 <= 12'h3fc;
2035: out3 <= 12'h3fd;
2036: out3 <= 12'h3fd;
2037: out3 <= 12'h3fe;
2038: out3 <= 12'h3fe;
2039: out3 <= 12'h3fe;
2040: out3 <= 12'h3ff;
2041: out3 <= 12'h3ff;
2042: out3 <= 12'h3ff;
2043: out3 <= 12'h400;
2044: out3 <= 12'h400;
2045: out3 <= 12'h400;
2046: out3 <= 12'h400;
2047: out3 <= 12'h400;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D2_46012(addr, out, clk);
input clk;
output [11:0] out;
reg [11:0] out, out2, out3;
input [10:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 12'h0;
1: out3 <= 12'hffd;
2: out3 <= 12'hffa;
3: out3 <= 12'hff7;
4: out3 <= 12'hff3;
5: out3 <= 12'hff0;
6: out3 <= 12'hfed;
7: out3 <= 12'hfea;
8: out3 <= 12'hfe7;
9: out3 <= 12'hfe4;
10: out3 <= 12'hfe1;
11: out3 <= 12'hfdd;
12: out3 <= 12'hfda;
13: out3 <= 12'hfd7;
14: out3 <= 12'hfd4;
15: out3 <= 12'hfd1;
16: out3 <= 12'hfce;
17: out3 <= 12'hfcb;
18: out3 <= 12'hfc7;
19: out3 <= 12'hfc4;
20: out3 <= 12'hfc1;
21: out3 <= 12'hfbe;
22: out3 <= 12'hfbb;
23: out3 <= 12'hfb8;
24: out3 <= 12'hfb5;
25: out3 <= 12'hfb2;
26: out3 <= 12'hfae;
27: out3 <= 12'hfab;
28: out3 <= 12'hfa8;
29: out3 <= 12'hfa5;
30: out3 <= 12'hfa2;
31: out3 <= 12'hf9f;
32: out3 <= 12'hf9c;
33: out3 <= 12'hf99;
34: out3 <= 12'hf95;
35: out3 <= 12'hf92;
36: out3 <= 12'hf8f;
37: out3 <= 12'hf8c;
38: out3 <= 12'hf89;
39: out3 <= 12'hf86;
40: out3 <= 12'hf83;
41: out3 <= 12'hf80;
42: out3 <= 12'hf7c;
43: out3 <= 12'hf79;
44: out3 <= 12'hf76;
45: out3 <= 12'hf73;
46: out3 <= 12'hf70;
47: out3 <= 12'hf6d;
48: out3 <= 12'hf6a;
49: out3 <= 12'hf67;
50: out3 <= 12'hf64;
51: out3 <= 12'hf60;
52: out3 <= 12'hf5d;
53: out3 <= 12'hf5a;
54: out3 <= 12'hf57;
55: out3 <= 12'hf54;
56: out3 <= 12'hf51;
57: out3 <= 12'hf4e;
58: out3 <= 12'hf4b;
59: out3 <= 12'hf48;
60: out3 <= 12'hf45;
61: out3 <= 12'hf41;
62: out3 <= 12'hf3e;
63: out3 <= 12'hf3b;
64: out3 <= 12'hf38;
65: out3 <= 12'hf35;
66: out3 <= 12'hf32;
67: out3 <= 12'hf2f;
68: out3 <= 12'hf2c;
69: out3 <= 12'hf29;
70: out3 <= 12'hf26;
71: out3 <= 12'hf23;
72: out3 <= 12'hf20;
73: out3 <= 12'hf1d;
74: out3 <= 12'hf1a;
75: out3 <= 12'hf16;
76: out3 <= 12'hf13;
77: out3 <= 12'hf10;
78: out3 <= 12'hf0d;
79: out3 <= 12'hf0a;
80: out3 <= 12'hf07;
81: out3 <= 12'hf04;
82: out3 <= 12'hf01;
83: out3 <= 12'hefe;
84: out3 <= 12'hefb;
85: out3 <= 12'hef8;
86: out3 <= 12'hef5;
87: out3 <= 12'hef2;
88: out3 <= 12'heef;
89: out3 <= 12'heec;
90: out3 <= 12'hee9;
91: out3 <= 12'hee6;
92: out3 <= 12'hee3;
93: out3 <= 12'hee0;
94: out3 <= 12'hedd;
95: out3 <= 12'heda;
96: out3 <= 12'hed7;
97: out3 <= 12'hed4;
98: out3 <= 12'hed1;
99: out3 <= 12'hece;
100: out3 <= 12'hecb;
101: out3 <= 12'hec8;
102: out3 <= 12'hec5;
103: out3 <= 12'hec2;
104: out3 <= 12'hebf;
105: out3 <= 12'hebc;
106: out3 <= 12'heb9;
107: out3 <= 12'heb6;
108: out3 <= 12'heb3;
109: out3 <= 12'heb0;
110: out3 <= 12'head;
111: out3 <= 12'heaa;
112: out3 <= 12'hea7;
113: out3 <= 12'hea4;
114: out3 <= 12'hea1;
115: out3 <= 12'he9e;
116: out3 <= 12'he9b;
117: out3 <= 12'he98;
118: out3 <= 12'he95;
119: out3 <= 12'he92;
120: out3 <= 12'he8f;
121: out3 <= 12'he8d;
122: out3 <= 12'he8a;
123: out3 <= 12'he87;
124: out3 <= 12'he84;
125: out3 <= 12'he81;
126: out3 <= 12'he7e;
127: out3 <= 12'he7b;
128: out3 <= 12'he78;
129: out3 <= 12'he75;
130: out3 <= 12'he72;
131: out3 <= 12'he6f;
132: out3 <= 12'he6d;
133: out3 <= 12'he6a;
134: out3 <= 12'he67;
135: out3 <= 12'he64;
136: out3 <= 12'he61;
137: out3 <= 12'he5e;
138: out3 <= 12'he5b;
139: out3 <= 12'he58;
140: out3 <= 12'he56;
141: out3 <= 12'he53;
142: out3 <= 12'he50;
143: out3 <= 12'he4d;
144: out3 <= 12'he4a;
145: out3 <= 12'he47;
146: out3 <= 12'he45;
147: out3 <= 12'he42;
148: out3 <= 12'he3f;
149: out3 <= 12'he3c;
150: out3 <= 12'he39;
151: out3 <= 12'he36;
152: out3 <= 12'he34;
153: out3 <= 12'he31;
154: out3 <= 12'he2e;
155: out3 <= 12'he2b;
156: out3 <= 12'he28;
157: out3 <= 12'he26;
158: out3 <= 12'he23;
159: out3 <= 12'he20;
160: out3 <= 12'he1d;
161: out3 <= 12'he1b;
162: out3 <= 12'he18;
163: out3 <= 12'he15;
164: out3 <= 12'he12;
165: out3 <= 12'he0f;
166: out3 <= 12'he0d;
167: out3 <= 12'he0a;
168: out3 <= 12'he07;
169: out3 <= 12'he05;
170: out3 <= 12'he02;
171: out3 <= 12'hdff;
172: out3 <= 12'hdfc;
173: out3 <= 12'hdfa;
174: out3 <= 12'hdf7;
175: out3 <= 12'hdf4;
176: out3 <= 12'hdf2;
177: out3 <= 12'hdef;
178: out3 <= 12'hdec;
179: out3 <= 12'hde9;
180: out3 <= 12'hde7;
181: out3 <= 12'hde4;
182: out3 <= 12'hde1;
183: out3 <= 12'hddf;
184: out3 <= 12'hddc;
185: out3 <= 12'hdda;
186: out3 <= 12'hdd7;
187: out3 <= 12'hdd4;
188: out3 <= 12'hdd2;
189: out3 <= 12'hdcf;
190: out3 <= 12'hdcc;
191: out3 <= 12'hdca;
192: out3 <= 12'hdc7;
193: out3 <= 12'hdc4;
194: out3 <= 12'hdc2;
195: out3 <= 12'hdbf;
196: out3 <= 12'hdbd;
197: out3 <= 12'hdba;
198: out3 <= 12'hdb8;
199: out3 <= 12'hdb5;
200: out3 <= 12'hdb2;
201: out3 <= 12'hdb0;
202: out3 <= 12'hdad;
203: out3 <= 12'hdab;
204: out3 <= 12'hda8;
205: out3 <= 12'hda6;
206: out3 <= 12'hda3;
207: out3 <= 12'hda1;
208: out3 <= 12'hd9e;
209: out3 <= 12'hd9b;
210: out3 <= 12'hd99;
211: out3 <= 12'hd96;
212: out3 <= 12'hd94;
213: out3 <= 12'hd91;
214: out3 <= 12'hd8f;
215: out3 <= 12'hd8c;
216: out3 <= 12'hd8a;
217: out3 <= 12'hd88;
218: out3 <= 12'hd85;
219: out3 <= 12'hd83;
220: out3 <= 12'hd80;
221: out3 <= 12'hd7e;
222: out3 <= 12'hd7b;
223: out3 <= 12'hd79;
224: out3 <= 12'hd76;
225: out3 <= 12'hd74;
226: out3 <= 12'hd72;
227: out3 <= 12'hd6f;
228: out3 <= 12'hd6d;
229: out3 <= 12'hd6a;
230: out3 <= 12'hd68;
231: out3 <= 12'hd66;
232: out3 <= 12'hd63;
233: out3 <= 12'hd61;
234: out3 <= 12'hd5e;
235: out3 <= 12'hd5c;
236: out3 <= 12'hd5a;
237: out3 <= 12'hd57;
238: out3 <= 12'hd55;
239: out3 <= 12'hd53;
240: out3 <= 12'hd50;
241: out3 <= 12'hd4e;
242: out3 <= 12'hd4c;
243: out3 <= 12'hd49;
244: out3 <= 12'hd47;
245: out3 <= 12'hd45;
246: out3 <= 12'hd42;
247: out3 <= 12'hd40;
248: out3 <= 12'hd3e;
249: out3 <= 12'hd3c;
250: out3 <= 12'hd39;
251: out3 <= 12'hd37;
252: out3 <= 12'hd35;
253: out3 <= 12'hd33;
254: out3 <= 12'hd30;
255: out3 <= 12'hd2e;
256: out3 <= 12'hd2c;
257: out3 <= 12'hd2a;
258: out3 <= 12'hd27;
259: out3 <= 12'hd25;
260: out3 <= 12'hd23;
261: out3 <= 12'hd21;
262: out3 <= 12'hd1f;
263: out3 <= 12'hd1d;
264: out3 <= 12'hd1a;
265: out3 <= 12'hd18;
266: out3 <= 12'hd16;
267: out3 <= 12'hd14;
268: out3 <= 12'hd12;
269: out3 <= 12'hd10;
270: out3 <= 12'hd0d;
271: out3 <= 12'hd0b;
272: out3 <= 12'hd09;
273: out3 <= 12'hd07;
274: out3 <= 12'hd05;
275: out3 <= 12'hd03;
276: out3 <= 12'hd01;
277: out3 <= 12'hcff;
278: out3 <= 12'hcfd;
279: out3 <= 12'hcfb;
280: out3 <= 12'hcf9;
281: out3 <= 12'hcf7;
282: out3 <= 12'hcf5;
283: out3 <= 12'hcf2;
284: out3 <= 12'hcf0;
285: out3 <= 12'hcee;
286: out3 <= 12'hcec;
287: out3 <= 12'hcea;
288: out3 <= 12'hce8;
289: out3 <= 12'hce6;
290: out3 <= 12'hce4;
291: out3 <= 12'hce2;
292: out3 <= 12'hce1;
293: out3 <= 12'hcdf;
294: out3 <= 12'hcdd;
295: out3 <= 12'hcdb;
296: out3 <= 12'hcd9;
297: out3 <= 12'hcd7;
298: out3 <= 12'hcd5;
299: out3 <= 12'hcd3;
300: out3 <= 12'hcd1;
301: out3 <= 12'hccf;
302: out3 <= 12'hccd;
303: out3 <= 12'hccb;
304: out3 <= 12'hcca;
305: out3 <= 12'hcc8;
306: out3 <= 12'hcc6;
307: out3 <= 12'hcc4;
308: out3 <= 12'hcc2;
309: out3 <= 12'hcc0;
310: out3 <= 12'hcbe;
311: out3 <= 12'hcbd;
312: out3 <= 12'hcbb;
313: out3 <= 12'hcb9;
314: out3 <= 12'hcb7;
315: out3 <= 12'hcb5;
316: out3 <= 12'hcb4;
317: out3 <= 12'hcb2;
318: out3 <= 12'hcb0;
319: out3 <= 12'hcae;
320: out3 <= 12'hcad;
321: out3 <= 12'hcab;
322: out3 <= 12'hca9;
323: out3 <= 12'hca7;
324: out3 <= 12'hca6;
325: out3 <= 12'hca4;
326: out3 <= 12'hca2;
327: out3 <= 12'hca1;
328: out3 <= 12'hc9f;
329: out3 <= 12'hc9d;
330: out3 <= 12'hc9c;
331: out3 <= 12'hc9a;
332: out3 <= 12'hc98;
333: out3 <= 12'hc97;
334: out3 <= 12'hc95;
335: out3 <= 12'hc93;
336: out3 <= 12'hc92;
337: out3 <= 12'hc90;
338: out3 <= 12'hc8e;
339: out3 <= 12'hc8d;
340: out3 <= 12'hc8b;
341: out3 <= 12'hc8a;
342: out3 <= 12'hc88;
343: out3 <= 12'hc87;
344: out3 <= 12'hc85;
345: out3 <= 12'hc83;
346: out3 <= 12'hc82;
347: out3 <= 12'hc80;
348: out3 <= 12'hc7f;
349: out3 <= 12'hc7d;
350: out3 <= 12'hc7c;
351: out3 <= 12'hc7a;
352: out3 <= 12'hc79;
353: out3 <= 12'hc77;
354: out3 <= 12'hc76;
355: out3 <= 12'hc75;
356: out3 <= 12'hc73;
357: out3 <= 12'hc72;
358: out3 <= 12'hc70;
359: out3 <= 12'hc6f;
360: out3 <= 12'hc6d;
361: out3 <= 12'hc6c;
362: out3 <= 12'hc6b;
363: out3 <= 12'hc69;
364: out3 <= 12'hc68;
365: out3 <= 12'hc66;
366: out3 <= 12'hc65;
367: out3 <= 12'hc64;
368: out3 <= 12'hc62;
369: out3 <= 12'hc61;
370: out3 <= 12'hc60;
371: out3 <= 12'hc5e;
372: out3 <= 12'hc5d;
373: out3 <= 12'hc5c;
374: out3 <= 12'hc5a;
375: out3 <= 12'hc59;
376: out3 <= 12'hc58;
377: out3 <= 12'hc57;
378: out3 <= 12'hc55;
379: out3 <= 12'hc54;
380: out3 <= 12'hc53;
381: out3 <= 12'hc52;
382: out3 <= 12'hc50;
383: out3 <= 12'hc4f;
384: out3 <= 12'hc4e;
385: out3 <= 12'hc4d;
386: out3 <= 12'hc4c;
387: out3 <= 12'hc4a;
388: out3 <= 12'hc49;
389: out3 <= 12'hc48;
390: out3 <= 12'hc47;
391: out3 <= 12'hc46;
392: out3 <= 12'hc45;
393: out3 <= 12'hc43;
394: out3 <= 12'hc42;
395: out3 <= 12'hc41;
396: out3 <= 12'hc40;
397: out3 <= 12'hc3f;
398: out3 <= 12'hc3e;
399: out3 <= 12'hc3d;
400: out3 <= 12'hc3c;
401: out3 <= 12'hc3b;
402: out3 <= 12'hc3a;
403: out3 <= 12'hc39;
404: out3 <= 12'hc38;
405: out3 <= 12'hc37;
406: out3 <= 12'hc36;
407: out3 <= 12'hc35;
408: out3 <= 12'hc34;
409: out3 <= 12'hc33;
410: out3 <= 12'hc32;
411: out3 <= 12'hc31;
412: out3 <= 12'hc30;
413: out3 <= 12'hc2f;
414: out3 <= 12'hc2e;
415: out3 <= 12'hc2d;
416: out3 <= 12'hc2c;
417: out3 <= 12'hc2b;
418: out3 <= 12'hc2a;
419: out3 <= 12'hc29;
420: out3 <= 12'hc29;
421: out3 <= 12'hc28;
422: out3 <= 12'hc27;
423: out3 <= 12'hc26;
424: out3 <= 12'hc25;
425: out3 <= 12'hc24;
426: out3 <= 12'hc23;
427: out3 <= 12'hc23;
428: out3 <= 12'hc22;
429: out3 <= 12'hc21;
430: out3 <= 12'hc20;
431: out3 <= 12'hc1f;
432: out3 <= 12'hc1f;
433: out3 <= 12'hc1e;
434: out3 <= 12'hc1d;
435: out3 <= 12'hc1c;
436: out3 <= 12'hc1c;
437: out3 <= 12'hc1b;
438: out3 <= 12'hc1a;
439: out3 <= 12'hc1a;
440: out3 <= 12'hc19;
441: out3 <= 12'hc18;
442: out3 <= 12'hc18;
443: out3 <= 12'hc17;
444: out3 <= 12'hc16;
445: out3 <= 12'hc16;
446: out3 <= 12'hc15;
447: out3 <= 12'hc14;
448: out3 <= 12'hc14;
449: out3 <= 12'hc13;
450: out3 <= 12'hc12;
451: out3 <= 12'hc12;
452: out3 <= 12'hc11;
453: out3 <= 12'hc11;
454: out3 <= 12'hc10;
455: out3 <= 12'hc10;
456: out3 <= 12'hc0f;
457: out3 <= 12'hc0f;
458: out3 <= 12'hc0e;
459: out3 <= 12'hc0e;
460: out3 <= 12'hc0d;
461: out3 <= 12'hc0d;
462: out3 <= 12'hc0c;
463: out3 <= 12'hc0c;
464: out3 <= 12'hc0b;
465: out3 <= 12'hc0b;
466: out3 <= 12'hc0a;
467: out3 <= 12'hc0a;
468: out3 <= 12'hc09;
469: out3 <= 12'hc09;
470: out3 <= 12'hc08;
471: out3 <= 12'hc08;
472: out3 <= 12'hc08;
473: out3 <= 12'hc07;
474: out3 <= 12'hc07;
475: out3 <= 12'hc07;
476: out3 <= 12'hc06;
477: out3 <= 12'hc06;
478: out3 <= 12'hc06;
479: out3 <= 12'hc05;
480: out3 <= 12'hc05;
481: out3 <= 12'hc05;
482: out3 <= 12'hc04;
483: out3 <= 12'hc04;
484: out3 <= 12'hc04;
485: out3 <= 12'hc04;
486: out3 <= 12'hc03;
487: out3 <= 12'hc03;
488: out3 <= 12'hc03;
489: out3 <= 12'hc03;
490: out3 <= 12'hc02;
491: out3 <= 12'hc02;
492: out3 <= 12'hc02;
493: out3 <= 12'hc02;
494: out3 <= 12'hc02;
495: out3 <= 12'hc01;
496: out3 <= 12'hc01;
497: out3 <= 12'hc01;
498: out3 <= 12'hc01;
499: out3 <= 12'hc01;
500: out3 <= 12'hc01;
501: out3 <= 12'hc01;
502: out3 <= 12'hc00;
503: out3 <= 12'hc00;
504: out3 <= 12'hc00;
505: out3 <= 12'hc00;
506: out3 <= 12'hc00;
507: out3 <= 12'hc00;
508: out3 <= 12'hc00;
509: out3 <= 12'hc00;
510: out3 <= 12'hc00;
511: out3 <= 12'hc00;
512: out3 <= 12'hc00;
513: out3 <= 12'hc00;
514: out3 <= 12'hc00;
515: out3 <= 12'hc00;
516: out3 <= 12'hc00;
517: out3 <= 12'hc00;
518: out3 <= 12'hc00;
519: out3 <= 12'hc00;
520: out3 <= 12'hc00;
521: out3 <= 12'hc00;
522: out3 <= 12'hc00;
523: out3 <= 12'hc01;
524: out3 <= 12'hc01;
525: out3 <= 12'hc01;
526: out3 <= 12'hc01;
527: out3 <= 12'hc01;
528: out3 <= 12'hc01;
529: out3 <= 12'hc01;
530: out3 <= 12'hc02;
531: out3 <= 12'hc02;
532: out3 <= 12'hc02;
533: out3 <= 12'hc02;
534: out3 <= 12'hc02;
535: out3 <= 12'hc03;
536: out3 <= 12'hc03;
537: out3 <= 12'hc03;
538: out3 <= 12'hc03;
539: out3 <= 12'hc04;
540: out3 <= 12'hc04;
541: out3 <= 12'hc04;
542: out3 <= 12'hc04;
543: out3 <= 12'hc05;
544: out3 <= 12'hc05;
545: out3 <= 12'hc05;
546: out3 <= 12'hc06;
547: out3 <= 12'hc06;
548: out3 <= 12'hc06;
549: out3 <= 12'hc07;
550: out3 <= 12'hc07;
551: out3 <= 12'hc07;
552: out3 <= 12'hc08;
553: out3 <= 12'hc08;
554: out3 <= 12'hc08;
555: out3 <= 12'hc09;
556: out3 <= 12'hc09;
557: out3 <= 12'hc0a;
558: out3 <= 12'hc0a;
559: out3 <= 12'hc0b;
560: out3 <= 12'hc0b;
561: out3 <= 12'hc0c;
562: out3 <= 12'hc0c;
563: out3 <= 12'hc0d;
564: out3 <= 12'hc0d;
565: out3 <= 12'hc0e;
566: out3 <= 12'hc0e;
567: out3 <= 12'hc0f;
568: out3 <= 12'hc0f;
569: out3 <= 12'hc10;
570: out3 <= 12'hc10;
571: out3 <= 12'hc11;
572: out3 <= 12'hc11;
573: out3 <= 12'hc12;
574: out3 <= 12'hc12;
575: out3 <= 12'hc13;
576: out3 <= 12'hc14;
577: out3 <= 12'hc14;
578: out3 <= 12'hc15;
579: out3 <= 12'hc16;
580: out3 <= 12'hc16;
581: out3 <= 12'hc17;
582: out3 <= 12'hc18;
583: out3 <= 12'hc18;
584: out3 <= 12'hc19;
585: out3 <= 12'hc1a;
586: out3 <= 12'hc1a;
587: out3 <= 12'hc1b;
588: out3 <= 12'hc1c;
589: out3 <= 12'hc1c;
590: out3 <= 12'hc1d;
591: out3 <= 12'hc1e;
592: out3 <= 12'hc1f;
593: out3 <= 12'hc1f;
594: out3 <= 12'hc20;
595: out3 <= 12'hc21;
596: out3 <= 12'hc22;
597: out3 <= 12'hc23;
598: out3 <= 12'hc23;
599: out3 <= 12'hc24;
600: out3 <= 12'hc25;
601: out3 <= 12'hc26;
602: out3 <= 12'hc27;
603: out3 <= 12'hc28;
604: out3 <= 12'hc29;
605: out3 <= 12'hc29;
606: out3 <= 12'hc2a;
607: out3 <= 12'hc2b;
608: out3 <= 12'hc2c;
609: out3 <= 12'hc2d;
610: out3 <= 12'hc2e;
611: out3 <= 12'hc2f;
612: out3 <= 12'hc30;
613: out3 <= 12'hc31;
614: out3 <= 12'hc32;
615: out3 <= 12'hc33;
616: out3 <= 12'hc34;
617: out3 <= 12'hc35;
618: out3 <= 12'hc36;
619: out3 <= 12'hc37;
620: out3 <= 12'hc38;
621: out3 <= 12'hc39;
622: out3 <= 12'hc3a;
623: out3 <= 12'hc3b;
624: out3 <= 12'hc3c;
625: out3 <= 12'hc3d;
626: out3 <= 12'hc3e;
627: out3 <= 12'hc3f;
628: out3 <= 12'hc40;
629: out3 <= 12'hc41;
630: out3 <= 12'hc42;
631: out3 <= 12'hc43;
632: out3 <= 12'hc45;
633: out3 <= 12'hc46;
634: out3 <= 12'hc47;
635: out3 <= 12'hc48;
636: out3 <= 12'hc49;
637: out3 <= 12'hc4a;
638: out3 <= 12'hc4c;
639: out3 <= 12'hc4d;
640: out3 <= 12'hc4e;
641: out3 <= 12'hc4f;
642: out3 <= 12'hc50;
643: out3 <= 12'hc52;
644: out3 <= 12'hc53;
645: out3 <= 12'hc54;
646: out3 <= 12'hc55;
647: out3 <= 12'hc57;
648: out3 <= 12'hc58;
649: out3 <= 12'hc59;
650: out3 <= 12'hc5a;
651: out3 <= 12'hc5c;
652: out3 <= 12'hc5d;
653: out3 <= 12'hc5e;
654: out3 <= 12'hc60;
655: out3 <= 12'hc61;
656: out3 <= 12'hc62;
657: out3 <= 12'hc64;
658: out3 <= 12'hc65;
659: out3 <= 12'hc66;
660: out3 <= 12'hc68;
661: out3 <= 12'hc69;
662: out3 <= 12'hc6b;
663: out3 <= 12'hc6c;
664: out3 <= 12'hc6d;
665: out3 <= 12'hc6f;
666: out3 <= 12'hc70;
667: out3 <= 12'hc72;
668: out3 <= 12'hc73;
669: out3 <= 12'hc75;
670: out3 <= 12'hc76;
671: out3 <= 12'hc77;
672: out3 <= 12'hc79;
673: out3 <= 12'hc7a;
674: out3 <= 12'hc7c;
675: out3 <= 12'hc7d;
676: out3 <= 12'hc7f;
677: out3 <= 12'hc80;
678: out3 <= 12'hc82;
679: out3 <= 12'hc83;
680: out3 <= 12'hc85;
681: out3 <= 12'hc87;
682: out3 <= 12'hc88;
683: out3 <= 12'hc8a;
684: out3 <= 12'hc8b;
685: out3 <= 12'hc8d;
686: out3 <= 12'hc8e;
687: out3 <= 12'hc90;
688: out3 <= 12'hc92;
689: out3 <= 12'hc93;
690: out3 <= 12'hc95;
691: out3 <= 12'hc97;
692: out3 <= 12'hc98;
693: out3 <= 12'hc9a;
694: out3 <= 12'hc9c;
695: out3 <= 12'hc9d;
696: out3 <= 12'hc9f;
697: out3 <= 12'hca1;
698: out3 <= 12'hca2;
699: out3 <= 12'hca4;
700: out3 <= 12'hca6;
701: out3 <= 12'hca7;
702: out3 <= 12'hca9;
703: out3 <= 12'hcab;
704: out3 <= 12'hcad;
705: out3 <= 12'hcae;
706: out3 <= 12'hcb0;
707: out3 <= 12'hcb2;
708: out3 <= 12'hcb4;
709: out3 <= 12'hcb5;
710: out3 <= 12'hcb7;
711: out3 <= 12'hcb9;
712: out3 <= 12'hcbb;
713: out3 <= 12'hcbd;
714: out3 <= 12'hcbe;
715: out3 <= 12'hcc0;
716: out3 <= 12'hcc2;
717: out3 <= 12'hcc4;
718: out3 <= 12'hcc6;
719: out3 <= 12'hcc8;
720: out3 <= 12'hcca;
721: out3 <= 12'hccb;
722: out3 <= 12'hccd;
723: out3 <= 12'hccf;
724: out3 <= 12'hcd1;
725: out3 <= 12'hcd3;
726: out3 <= 12'hcd5;
727: out3 <= 12'hcd7;
728: out3 <= 12'hcd9;
729: out3 <= 12'hcdb;
730: out3 <= 12'hcdd;
731: out3 <= 12'hcdf;
732: out3 <= 12'hce1;
733: out3 <= 12'hce2;
734: out3 <= 12'hce4;
735: out3 <= 12'hce6;
736: out3 <= 12'hce8;
737: out3 <= 12'hcea;
738: out3 <= 12'hcec;
739: out3 <= 12'hcee;
740: out3 <= 12'hcf0;
741: out3 <= 12'hcf2;
742: out3 <= 12'hcf5;
743: out3 <= 12'hcf7;
744: out3 <= 12'hcf9;
745: out3 <= 12'hcfb;
746: out3 <= 12'hcfd;
747: out3 <= 12'hcff;
748: out3 <= 12'hd01;
749: out3 <= 12'hd03;
750: out3 <= 12'hd05;
751: out3 <= 12'hd07;
752: out3 <= 12'hd09;
753: out3 <= 12'hd0b;
754: out3 <= 12'hd0d;
755: out3 <= 12'hd10;
756: out3 <= 12'hd12;
757: out3 <= 12'hd14;
758: out3 <= 12'hd16;
759: out3 <= 12'hd18;
760: out3 <= 12'hd1a;
761: out3 <= 12'hd1d;
762: out3 <= 12'hd1f;
763: out3 <= 12'hd21;
764: out3 <= 12'hd23;
765: out3 <= 12'hd25;
766: out3 <= 12'hd27;
767: out3 <= 12'hd2a;
768: out3 <= 12'hd2c;
769: out3 <= 12'hd2e;
770: out3 <= 12'hd30;
771: out3 <= 12'hd33;
772: out3 <= 12'hd35;
773: out3 <= 12'hd37;
774: out3 <= 12'hd39;
775: out3 <= 12'hd3c;
776: out3 <= 12'hd3e;
777: out3 <= 12'hd40;
778: out3 <= 12'hd42;
779: out3 <= 12'hd45;
780: out3 <= 12'hd47;
781: out3 <= 12'hd49;
782: out3 <= 12'hd4c;
783: out3 <= 12'hd4e;
784: out3 <= 12'hd50;
785: out3 <= 12'hd53;
786: out3 <= 12'hd55;
787: out3 <= 12'hd57;
788: out3 <= 12'hd5a;
789: out3 <= 12'hd5c;
790: out3 <= 12'hd5e;
791: out3 <= 12'hd61;
792: out3 <= 12'hd63;
793: out3 <= 12'hd66;
794: out3 <= 12'hd68;
795: out3 <= 12'hd6a;
796: out3 <= 12'hd6d;
797: out3 <= 12'hd6f;
798: out3 <= 12'hd72;
799: out3 <= 12'hd74;
800: out3 <= 12'hd76;
801: out3 <= 12'hd79;
802: out3 <= 12'hd7b;
803: out3 <= 12'hd7e;
804: out3 <= 12'hd80;
805: out3 <= 12'hd83;
806: out3 <= 12'hd85;
807: out3 <= 12'hd88;
808: out3 <= 12'hd8a;
809: out3 <= 12'hd8c;
810: out3 <= 12'hd8f;
811: out3 <= 12'hd91;
812: out3 <= 12'hd94;
813: out3 <= 12'hd96;
814: out3 <= 12'hd99;
815: out3 <= 12'hd9b;
816: out3 <= 12'hd9e;
817: out3 <= 12'hda1;
818: out3 <= 12'hda3;
819: out3 <= 12'hda6;
820: out3 <= 12'hda8;
821: out3 <= 12'hdab;
822: out3 <= 12'hdad;
823: out3 <= 12'hdb0;
824: out3 <= 12'hdb2;
825: out3 <= 12'hdb5;
826: out3 <= 12'hdb8;
827: out3 <= 12'hdba;
828: out3 <= 12'hdbd;
829: out3 <= 12'hdbf;
830: out3 <= 12'hdc2;
831: out3 <= 12'hdc4;
832: out3 <= 12'hdc7;
833: out3 <= 12'hdca;
834: out3 <= 12'hdcc;
835: out3 <= 12'hdcf;
836: out3 <= 12'hdd2;
837: out3 <= 12'hdd4;
838: out3 <= 12'hdd7;
839: out3 <= 12'hdda;
840: out3 <= 12'hddc;
841: out3 <= 12'hddf;
842: out3 <= 12'hde1;
843: out3 <= 12'hde4;
844: out3 <= 12'hde7;
845: out3 <= 12'hde9;
846: out3 <= 12'hdec;
847: out3 <= 12'hdef;
848: out3 <= 12'hdf2;
849: out3 <= 12'hdf4;
850: out3 <= 12'hdf7;
851: out3 <= 12'hdfa;
852: out3 <= 12'hdfc;
853: out3 <= 12'hdff;
854: out3 <= 12'he02;
855: out3 <= 12'he05;
856: out3 <= 12'he07;
857: out3 <= 12'he0a;
858: out3 <= 12'he0d;
859: out3 <= 12'he0f;
860: out3 <= 12'he12;
861: out3 <= 12'he15;
862: out3 <= 12'he18;
863: out3 <= 12'he1b;
864: out3 <= 12'he1d;
865: out3 <= 12'he20;
866: out3 <= 12'he23;
867: out3 <= 12'he26;
868: out3 <= 12'he28;
869: out3 <= 12'he2b;
870: out3 <= 12'he2e;
871: out3 <= 12'he31;
872: out3 <= 12'he34;
873: out3 <= 12'he36;
874: out3 <= 12'he39;
875: out3 <= 12'he3c;
876: out3 <= 12'he3f;
877: out3 <= 12'he42;
878: out3 <= 12'he45;
879: out3 <= 12'he47;
880: out3 <= 12'he4a;
881: out3 <= 12'he4d;
882: out3 <= 12'he50;
883: out3 <= 12'he53;
884: out3 <= 12'he56;
885: out3 <= 12'he58;
886: out3 <= 12'he5b;
887: out3 <= 12'he5e;
888: out3 <= 12'he61;
889: out3 <= 12'he64;
890: out3 <= 12'he67;
891: out3 <= 12'he6a;
892: out3 <= 12'he6d;
893: out3 <= 12'he6f;
894: out3 <= 12'he72;
895: out3 <= 12'he75;
896: out3 <= 12'he78;
897: out3 <= 12'he7b;
898: out3 <= 12'he7e;
899: out3 <= 12'he81;
900: out3 <= 12'he84;
901: out3 <= 12'he87;
902: out3 <= 12'he8a;
903: out3 <= 12'he8d;
904: out3 <= 12'he8f;
905: out3 <= 12'he92;
906: out3 <= 12'he95;
907: out3 <= 12'he98;
908: out3 <= 12'he9b;
909: out3 <= 12'he9e;
910: out3 <= 12'hea1;
911: out3 <= 12'hea4;
912: out3 <= 12'hea7;
913: out3 <= 12'heaa;
914: out3 <= 12'head;
915: out3 <= 12'heb0;
916: out3 <= 12'heb3;
917: out3 <= 12'heb6;
918: out3 <= 12'heb9;
919: out3 <= 12'hebc;
920: out3 <= 12'hebf;
921: out3 <= 12'hec2;
922: out3 <= 12'hec5;
923: out3 <= 12'hec8;
924: out3 <= 12'hecb;
925: out3 <= 12'hece;
926: out3 <= 12'hed1;
927: out3 <= 12'hed4;
928: out3 <= 12'hed7;
929: out3 <= 12'heda;
930: out3 <= 12'hedd;
931: out3 <= 12'hee0;
932: out3 <= 12'hee3;
933: out3 <= 12'hee6;
934: out3 <= 12'hee9;
935: out3 <= 12'heec;
936: out3 <= 12'heef;
937: out3 <= 12'hef2;
938: out3 <= 12'hef5;
939: out3 <= 12'hef8;
940: out3 <= 12'hefb;
941: out3 <= 12'hefe;
942: out3 <= 12'hf01;
943: out3 <= 12'hf04;
944: out3 <= 12'hf07;
945: out3 <= 12'hf0a;
946: out3 <= 12'hf0d;
947: out3 <= 12'hf10;
948: out3 <= 12'hf13;
949: out3 <= 12'hf16;
950: out3 <= 12'hf1a;
951: out3 <= 12'hf1d;
952: out3 <= 12'hf20;
953: out3 <= 12'hf23;
954: out3 <= 12'hf26;
955: out3 <= 12'hf29;
956: out3 <= 12'hf2c;
957: out3 <= 12'hf2f;
958: out3 <= 12'hf32;
959: out3 <= 12'hf35;
960: out3 <= 12'hf38;
961: out3 <= 12'hf3b;
962: out3 <= 12'hf3e;
963: out3 <= 12'hf41;
964: out3 <= 12'hf45;
965: out3 <= 12'hf48;
966: out3 <= 12'hf4b;
967: out3 <= 12'hf4e;
968: out3 <= 12'hf51;
969: out3 <= 12'hf54;
970: out3 <= 12'hf57;
971: out3 <= 12'hf5a;
972: out3 <= 12'hf5d;
973: out3 <= 12'hf60;
974: out3 <= 12'hf64;
975: out3 <= 12'hf67;
976: out3 <= 12'hf6a;
977: out3 <= 12'hf6d;
978: out3 <= 12'hf70;
979: out3 <= 12'hf73;
980: out3 <= 12'hf76;
981: out3 <= 12'hf79;
982: out3 <= 12'hf7c;
983: out3 <= 12'hf80;
984: out3 <= 12'hf83;
985: out3 <= 12'hf86;
986: out3 <= 12'hf89;
987: out3 <= 12'hf8c;
988: out3 <= 12'hf8f;
989: out3 <= 12'hf92;
990: out3 <= 12'hf95;
991: out3 <= 12'hf99;
992: out3 <= 12'hf9c;
993: out3 <= 12'hf9f;
994: out3 <= 12'hfa2;
995: out3 <= 12'hfa5;
996: out3 <= 12'hfa8;
997: out3 <= 12'hfab;
998: out3 <= 12'hfae;
999: out3 <= 12'hfb2;
1000: out3 <= 12'hfb5;
1001: out3 <= 12'hfb8;
1002: out3 <= 12'hfbb;
1003: out3 <= 12'hfbe;
1004: out3 <= 12'hfc1;
1005: out3 <= 12'hfc4;
1006: out3 <= 12'hfc7;
1007: out3 <= 12'hfcb;
1008: out3 <= 12'hfce;
1009: out3 <= 12'hfd1;
1010: out3 <= 12'hfd4;
1011: out3 <= 12'hfd7;
1012: out3 <= 12'hfda;
1013: out3 <= 12'hfdd;
1014: out3 <= 12'hfe1;
1015: out3 <= 12'hfe4;
1016: out3 <= 12'hfe7;
1017: out3 <= 12'hfea;
1018: out3 <= 12'hfed;
1019: out3 <= 12'hff0;
1020: out3 <= 12'hff3;
1021: out3 <= 12'hff7;
1022: out3 <= 12'hffa;
1023: out3 <= 12'hffd;
1024: out3 <= 12'h0;
1025: out3 <= 12'hffa;
1026: out3 <= 12'hff3;
1027: out3 <= 12'hfed;
1028: out3 <= 12'hfe7;
1029: out3 <= 12'hfe1;
1030: out3 <= 12'hfda;
1031: out3 <= 12'hfd4;
1032: out3 <= 12'hfce;
1033: out3 <= 12'hfc7;
1034: out3 <= 12'hfc1;
1035: out3 <= 12'hfbb;
1036: out3 <= 12'hfb5;
1037: out3 <= 12'hfae;
1038: out3 <= 12'hfa8;
1039: out3 <= 12'hfa2;
1040: out3 <= 12'hf9c;
1041: out3 <= 12'hf95;
1042: out3 <= 12'hf8f;
1043: out3 <= 12'hf89;
1044: out3 <= 12'hf83;
1045: out3 <= 12'hf7c;
1046: out3 <= 12'hf76;
1047: out3 <= 12'hf70;
1048: out3 <= 12'hf6a;
1049: out3 <= 12'hf64;
1050: out3 <= 12'hf5d;
1051: out3 <= 12'hf57;
1052: out3 <= 12'hf51;
1053: out3 <= 12'hf4b;
1054: out3 <= 12'hf45;
1055: out3 <= 12'hf3e;
1056: out3 <= 12'hf38;
1057: out3 <= 12'hf32;
1058: out3 <= 12'hf2c;
1059: out3 <= 12'hf26;
1060: out3 <= 12'hf20;
1061: out3 <= 12'hf1a;
1062: out3 <= 12'hf13;
1063: out3 <= 12'hf0d;
1064: out3 <= 12'hf07;
1065: out3 <= 12'hf01;
1066: out3 <= 12'hefb;
1067: out3 <= 12'hef5;
1068: out3 <= 12'heef;
1069: out3 <= 12'hee9;
1070: out3 <= 12'hee3;
1071: out3 <= 12'hedd;
1072: out3 <= 12'hed7;
1073: out3 <= 12'hed1;
1074: out3 <= 12'hecb;
1075: out3 <= 12'hec5;
1076: out3 <= 12'hebf;
1077: out3 <= 12'heb9;
1078: out3 <= 12'heb3;
1079: out3 <= 12'head;
1080: out3 <= 12'hea7;
1081: out3 <= 12'hea1;
1082: out3 <= 12'he9b;
1083: out3 <= 12'he95;
1084: out3 <= 12'he8f;
1085: out3 <= 12'he8a;
1086: out3 <= 12'he84;
1087: out3 <= 12'he7e;
1088: out3 <= 12'he78;
1089: out3 <= 12'he72;
1090: out3 <= 12'he6d;
1091: out3 <= 12'he67;
1092: out3 <= 12'he61;
1093: out3 <= 12'he5b;
1094: out3 <= 12'he56;
1095: out3 <= 12'he50;
1096: out3 <= 12'he4a;
1097: out3 <= 12'he45;
1098: out3 <= 12'he3f;
1099: out3 <= 12'he39;
1100: out3 <= 12'he34;
1101: out3 <= 12'he2e;
1102: out3 <= 12'he28;
1103: out3 <= 12'he23;
1104: out3 <= 12'he1d;
1105: out3 <= 12'he18;
1106: out3 <= 12'he12;
1107: out3 <= 12'he0d;
1108: out3 <= 12'he07;
1109: out3 <= 12'he02;
1110: out3 <= 12'hdfc;
1111: out3 <= 12'hdf7;
1112: out3 <= 12'hdf2;
1113: out3 <= 12'hdec;
1114: out3 <= 12'hde7;
1115: out3 <= 12'hde1;
1116: out3 <= 12'hddc;
1117: out3 <= 12'hdd7;
1118: out3 <= 12'hdd2;
1119: out3 <= 12'hdcc;
1120: out3 <= 12'hdc7;
1121: out3 <= 12'hdc2;
1122: out3 <= 12'hdbd;
1123: out3 <= 12'hdb8;
1124: out3 <= 12'hdb2;
1125: out3 <= 12'hdad;
1126: out3 <= 12'hda8;
1127: out3 <= 12'hda3;
1128: out3 <= 12'hd9e;
1129: out3 <= 12'hd99;
1130: out3 <= 12'hd94;
1131: out3 <= 12'hd8f;
1132: out3 <= 12'hd8a;
1133: out3 <= 12'hd85;
1134: out3 <= 12'hd80;
1135: out3 <= 12'hd7b;
1136: out3 <= 12'hd76;
1137: out3 <= 12'hd72;
1138: out3 <= 12'hd6d;
1139: out3 <= 12'hd68;
1140: out3 <= 12'hd63;
1141: out3 <= 12'hd5e;
1142: out3 <= 12'hd5a;
1143: out3 <= 12'hd55;
1144: out3 <= 12'hd50;
1145: out3 <= 12'hd4c;
1146: out3 <= 12'hd47;
1147: out3 <= 12'hd42;
1148: out3 <= 12'hd3e;
1149: out3 <= 12'hd39;
1150: out3 <= 12'hd35;
1151: out3 <= 12'hd30;
1152: out3 <= 12'hd2c;
1153: out3 <= 12'hd27;
1154: out3 <= 12'hd23;
1155: out3 <= 12'hd1f;
1156: out3 <= 12'hd1a;
1157: out3 <= 12'hd16;
1158: out3 <= 12'hd12;
1159: out3 <= 12'hd0d;
1160: out3 <= 12'hd09;
1161: out3 <= 12'hd05;
1162: out3 <= 12'hd01;
1163: out3 <= 12'hcfd;
1164: out3 <= 12'hcf9;
1165: out3 <= 12'hcf5;
1166: out3 <= 12'hcf0;
1167: out3 <= 12'hcec;
1168: out3 <= 12'hce8;
1169: out3 <= 12'hce4;
1170: out3 <= 12'hce1;
1171: out3 <= 12'hcdd;
1172: out3 <= 12'hcd9;
1173: out3 <= 12'hcd5;
1174: out3 <= 12'hcd1;
1175: out3 <= 12'hccd;
1176: out3 <= 12'hcca;
1177: out3 <= 12'hcc6;
1178: out3 <= 12'hcc2;
1179: out3 <= 12'hcbe;
1180: out3 <= 12'hcbb;
1181: out3 <= 12'hcb7;
1182: out3 <= 12'hcb4;
1183: out3 <= 12'hcb0;
1184: out3 <= 12'hcad;
1185: out3 <= 12'hca9;
1186: out3 <= 12'hca6;
1187: out3 <= 12'hca2;
1188: out3 <= 12'hc9f;
1189: out3 <= 12'hc9c;
1190: out3 <= 12'hc98;
1191: out3 <= 12'hc95;
1192: out3 <= 12'hc92;
1193: out3 <= 12'hc8e;
1194: out3 <= 12'hc8b;
1195: out3 <= 12'hc88;
1196: out3 <= 12'hc85;
1197: out3 <= 12'hc82;
1198: out3 <= 12'hc7f;
1199: out3 <= 12'hc7c;
1200: out3 <= 12'hc79;
1201: out3 <= 12'hc76;
1202: out3 <= 12'hc73;
1203: out3 <= 12'hc70;
1204: out3 <= 12'hc6d;
1205: out3 <= 12'hc6b;
1206: out3 <= 12'hc68;
1207: out3 <= 12'hc65;
1208: out3 <= 12'hc62;
1209: out3 <= 12'hc60;
1210: out3 <= 12'hc5d;
1211: out3 <= 12'hc5a;
1212: out3 <= 12'hc58;
1213: out3 <= 12'hc55;
1214: out3 <= 12'hc53;
1215: out3 <= 12'hc50;
1216: out3 <= 12'hc4e;
1217: out3 <= 12'hc4c;
1218: out3 <= 12'hc49;
1219: out3 <= 12'hc47;
1220: out3 <= 12'hc45;
1221: out3 <= 12'hc42;
1222: out3 <= 12'hc40;
1223: out3 <= 12'hc3e;
1224: out3 <= 12'hc3c;
1225: out3 <= 12'hc3a;
1226: out3 <= 12'hc38;
1227: out3 <= 12'hc36;
1228: out3 <= 12'hc34;
1229: out3 <= 12'hc32;
1230: out3 <= 12'hc30;
1231: out3 <= 12'hc2e;
1232: out3 <= 12'hc2c;
1233: out3 <= 12'hc2a;
1234: out3 <= 12'hc29;
1235: out3 <= 12'hc27;
1236: out3 <= 12'hc25;
1237: out3 <= 12'hc23;
1238: out3 <= 12'hc22;
1239: out3 <= 12'hc20;
1240: out3 <= 12'hc1f;
1241: out3 <= 12'hc1d;
1242: out3 <= 12'hc1c;
1243: out3 <= 12'hc1a;
1244: out3 <= 12'hc19;
1245: out3 <= 12'hc18;
1246: out3 <= 12'hc16;
1247: out3 <= 12'hc15;
1248: out3 <= 12'hc14;
1249: out3 <= 12'hc12;
1250: out3 <= 12'hc11;
1251: out3 <= 12'hc10;
1252: out3 <= 12'hc0f;
1253: out3 <= 12'hc0e;
1254: out3 <= 12'hc0d;
1255: out3 <= 12'hc0c;
1256: out3 <= 12'hc0b;
1257: out3 <= 12'hc0a;
1258: out3 <= 12'hc09;
1259: out3 <= 12'hc08;
1260: out3 <= 12'hc08;
1261: out3 <= 12'hc07;
1262: out3 <= 12'hc06;
1263: out3 <= 12'hc06;
1264: out3 <= 12'hc05;
1265: out3 <= 12'hc04;
1266: out3 <= 12'hc04;
1267: out3 <= 12'hc03;
1268: out3 <= 12'hc03;
1269: out3 <= 12'hc02;
1270: out3 <= 12'hc02;
1271: out3 <= 12'hc02;
1272: out3 <= 12'hc01;
1273: out3 <= 12'hc01;
1274: out3 <= 12'hc01;
1275: out3 <= 12'hc00;
1276: out3 <= 12'hc00;
1277: out3 <= 12'hc00;
1278: out3 <= 12'hc00;
1279: out3 <= 12'hc00;
1280: out3 <= 12'hc00;
1281: out3 <= 12'hc00;
1282: out3 <= 12'hc00;
1283: out3 <= 12'hc00;
1284: out3 <= 12'hc00;
1285: out3 <= 12'hc00;
1286: out3 <= 12'hc01;
1287: out3 <= 12'hc01;
1288: out3 <= 12'hc01;
1289: out3 <= 12'hc02;
1290: out3 <= 12'hc02;
1291: out3 <= 12'hc02;
1292: out3 <= 12'hc03;
1293: out3 <= 12'hc03;
1294: out3 <= 12'hc04;
1295: out3 <= 12'hc04;
1296: out3 <= 12'hc05;
1297: out3 <= 12'hc06;
1298: out3 <= 12'hc06;
1299: out3 <= 12'hc07;
1300: out3 <= 12'hc08;
1301: out3 <= 12'hc08;
1302: out3 <= 12'hc09;
1303: out3 <= 12'hc0a;
1304: out3 <= 12'hc0b;
1305: out3 <= 12'hc0c;
1306: out3 <= 12'hc0d;
1307: out3 <= 12'hc0e;
1308: out3 <= 12'hc0f;
1309: out3 <= 12'hc10;
1310: out3 <= 12'hc11;
1311: out3 <= 12'hc12;
1312: out3 <= 12'hc14;
1313: out3 <= 12'hc15;
1314: out3 <= 12'hc16;
1315: out3 <= 12'hc18;
1316: out3 <= 12'hc19;
1317: out3 <= 12'hc1a;
1318: out3 <= 12'hc1c;
1319: out3 <= 12'hc1d;
1320: out3 <= 12'hc1f;
1321: out3 <= 12'hc20;
1322: out3 <= 12'hc22;
1323: out3 <= 12'hc23;
1324: out3 <= 12'hc25;
1325: out3 <= 12'hc27;
1326: out3 <= 12'hc29;
1327: out3 <= 12'hc2a;
1328: out3 <= 12'hc2c;
1329: out3 <= 12'hc2e;
1330: out3 <= 12'hc30;
1331: out3 <= 12'hc32;
1332: out3 <= 12'hc34;
1333: out3 <= 12'hc36;
1334: out3 <= 12'hc38;
1335: out3 <= 12'hc3a;
1336: out3 <= 12'hc3c;
1337: out3 <= 12'hc3e;
1338: out3 <= 12'hc40;
1339: out3 <= 12'hc42;
1340: out3 <= 12'hc45;
1341: out3 <= 12'hc47;
1342: out3 <= 12'hc49;
1343: out3 <= 12'hc4c;
1344: out3 <= 12'hc4e;
1345: out3 <= 12'hc50;
1346: out3 <= 12'hc53;
1347: out3 <= 12'hc55;
1348: out3 <= 12'hc58;
1349: out3 <= 12'hc5a;
1350: out3 <= 12'hc5d;
1351: out3 <= 12'hc60;
1352: out3 <= 12'hc62;
1353: out3 <= 12'hc65;
1354: out3 <= 12'hc68;
1355: out3 <= 12'hc6b;
1356: out3 <= 12'hc6d;
1357: out3 <= 12'hc70;
1358: out3 <= 12'hc73;
1359: out3 <= 12'hc76;
1360: out3 <= 12'hc79;
1361: out3 <= 12'hc7c;
1362: out3 <= 12'hc7f;
1363: out3 <= 12'hc82;
1364: out3 <= 12'hc85;
1365: out3 <= 12'hc88;
1366: out3 <= 12'hc8b;
1367: out3 <= 12'hc8e;
1368: out3 <= 12'hc92;
1369: out3 <= 12'hc95;
1370: out3 <= 12'hc98;
1371: out3 <= 12'hc9c;
1372: out3 <= 12'hc9f;
1373: out3 <= 12'hca2;
1374: out3 <= 12'hca6;
1375: out3 <= 12'hca9;
1376: out3 <= 12'hcad;
1377: out3 <= 12'hcb0;
1378: out3 <= 12'hcb4;
1379: out3 <= 12'hcb7;
1380: out3 <= 12'hcbb;
1381: out3 <= 12'hcbe;
1382: out3 <= 12'hcc2;
1383: out3 <= 12'hcc6;
1384: out3 <= 12'hcca;
1385: out3 <= 12'hccd;
1386: out3 <= 12'hcd1;
1387: out3 <= 12'hcd5;
1388: out3 <= 12'hcd9;
1389: out3 <= 12'hcdd;
1390: out3 <= 12'hce1;
1391: out3 <= 12'hce4;
1392: out3 <= 12'hce8;
1393: out3 <= 12'hcec;
1394: out3 <= 12'hcf0;
1395: out3 <= 12'hcf5;
1396: out3 <= 12'hcf9;
1397: out3 <= 12'hcfd;
1398: out3 <= 12'hd01;
1399: out3 <= 12'hd05;
1400: out3 <= 12'hd09;
1401: out3 <= 12'hd0d;
1402: out3 <= 12'hd12;
1403: out3 <= 12'hd16;
1404: out3 <= 12'hd1a;
1405: out3 <= 12'hd1f;
1406: out3 <= 12'hd23;
1407: out3 <= 12'hd27;
1408: out3 <= 12'hd2c;
1409: out3 <= 12'hd30;
1410: out3 <= 12'hd35;
1411: out3 <= 12'hd39;
1412: out3 <= 12'hd3e;
1413: out3 <= 12'hd42;
1414: out3 <= 12'hd47;
1415: out3 <= 12'hd4c;
1416: out3 <= 12'hd50;
1417: out3 <= 12'hd55;
1418: out3 <= 12'hd5a;
1419: out3 <= 12'hd5e;
1420: out3 <= 12'hd63;
1421: out3 <= 12'hd68;
1422: out3 <= 12'hd6d;
1423: out3 <= 12'hd72;
1424: out3 <= 12'hd76;
1425: out3 <= 12'hd7b;
1426: out3 <= 12'hd80;
1427: out3 <= 12'hd85;
1428: out3 <= 12'hd8a;
1429: out3 <= 12'hd8f;
1430: out3 <= 12'hd94;
1431: out3 <= 12'hd99;
1432: out3 <= 12'hd9e;
1433: out3 <= 12'hda3;
1434: out3 <= 12'hda8;
1435: out3 <= 12'hdad;
1436: out3 <= 12'hdb2;
1437: out3 <= 12'hdb8;
1438: out3 <= 12'hdbd;
1439: out3 <= 12'hdc2;
1440: out3 <= 12'hdc7;
1441: out3 <= 12'hdcc;
1442: out3 <= 12'hdd2;
1443: out3 <= 12'hdd7;
1444: out3 <= 12'hddc;
1445: out3 <= 12'hde1;
1446: out3 <= 12'hde7;
1447: out3 <= 12'hdec;
1448: out3 <= 12'hdf2;
1449: out3 <= 12'hdf7;
1450: out3 <= 12'hdfc;
1451: out3 <= 12'he02;
1452: out3 <= 12'he07;
1453: out3 <= 12'he0d;
1454: out3 <= 12'he12;
1455: out3 <= 12'he18;
1456: out3 <= 12'he1d;
1457: out3 <= 12'he23;
1458: out3 <= 12'he28;
1459: out3 <= 12'he2e;
1460: out3 <= 12'he34;
1461: out3 <= 12'he39;
1462: out3 <= 12'he3f;
1463: out3 <= 12'he45;
1464: out3 <= 12'he4a;
1465: out3 <= 12'he50;
1466: out3 <= 12'he56;
1467: out3 <= 12'he5b;
1468: out3 <= 12'he61;
1469: out3 <= 12'he67;
1470: out3 <= 12'he6d;
1471: out3 <= 12'he72;
1472: out3 <= 12'he78;
1473: out3 <= 12'he7e;
1474: out3 <= 12'he84;
1475: out3 <= 12'he8a;
1476: out3 <= 12'he8f;
1477: out3 <= 12'he95;
1478: out3 <= 12'he9b;
1479: out3 <= 12'hea1;
1480: out3 <= 12'hea7;
1481: out3 <= 12'head;
1482: out3 <= 12'heb3;
1483: out3 <= 12'heb9;
1484: out3 <= 12'hebf;
1485: out3 <= 12'hec5;
1486: out3 <= 12'hecb;
1487: out3 <= 12'hed1;
1488: out3 <= 12'hed7;
1489: out3 <= 12'hedd;
1490: out3 <= 12'hee3;
1491: out3 <= 12'hee9;
1492: out3 <= 12'heef;
1493: out3 <= 12'hef5;
1494: out3 <= 12'hefb;
1495: out3 <= 12'hf01;
1496: out3 <= 12'hf07;
1497: out3 <= 12'hf0d;
1498: out3 <= 12'hf13;
1499: out3 <= 12'hf1a;
1500: out3 <= 12'hf20;
1501: out3 <= 12'hf26;
1502: out3 <= 12'hf2c;
1503: out3 <= 12'hf32;
1504: out3 <= 12'hf38;
1505: out3 <= 12'hf3e;
1506: out3 <= 12'hf45;
1507: out3 <= 12'hf4b;
1508: out3 <= 12'hf51;
1509: out3 <= 12'hf57;
1510: out3 <= 12'hf5d;
1511: out3 <= 12'hf64;
1512: out3 <= 12'hf6a;
1513: out3 <= 12'hf70;
1514: out3 <= 12'hf76;
1515: out3 <= 12'hf7c;
1516: out3 <= 12'hf83;
1517: out3 <= 12'hf89;
1518: out3 <= 12'hf8f;
1519: out3 <= 12'hf95;
1520: out3 <= 12'hf9c;
1521: out3 <= 12'hfa2;
1522: out3 <= 12'hfa8;
1523: out3 <= 12'hfae;
1524: out3 <= 12'hfb5;
1525: out3 <= 12'hfbb;
1526: out3 <= 12'hfc1;
1527: out3 <= 12'hfc7;
1528: out3 <= 12'hfce;
1529: out3 <= 12'hfd4;
1530: out3 <= 12'hfda;
1531: out3 <= 12'hfe1;
1532: out3 <= 12'hfe7;
1533: out3 <= 12'hfed;
1534: out3 <= 12'hff3;
1535: out3 <= 12'hffa;
1536: out3 <= 12'h0;
1537: out3 <= 12'h6;
1538: out3 <= 12'hd;
1539: out3 <= 12'h13;
1540: out3 <= 12'h19;
1541: out3 <= 12'h1f;
1542: out3 <= 12'h26;
1543: out3 <= 12'h2c;
1544: out3 <= 12'h32;
1545: out3 <= 12'h39;
1546: out3 <= 12'h3f;
1547: out3 <= 12'h45;
1548: out3 <= 12'h4b;
1549: out3 <= 12'h52;
1550: out3 <= 12'h58;
1551: out3 <= 12'h5e;
1552: out3 <= 12'h64;
1553: out3 <= 12'h6b;
1554: out3 <= 12'h71;
1555: out3 <= 12'h77;
1556: out3 <= 12'h7d;
1557: out3 <= 12'h84;
1558: out3 <= 12'h8a;
1559: out3 <= 12'h90;
1560: out3 <= 12'h96;
1561: out3 <= 12'h9c;
1562: out3 <= 12'ha3;
1563: out3 <= 12'ha9;
1564: out3 <= 12'haf;
1565: out3 <= 12'hb5;
1566: out3 <= 12'hbb;
1567: out3 <= 12'hc2;
1568: out3 <= 12'hc8;
1569: out3 <= 12'hce;
1570: out3 <= 12'hd4;
1571: out3 <= 12'hda;
1572: out3 <= 12'he0;
1573: out3 <= 12'he6;
1574: out3 <= 12'hed;
1575: out3 <= 12'hf3;
1576: out3 <= 12'hf9;
1577: out3 <= 12'hff;
1578: out3 <= 12'h105;
1579: out3 <= 12'h10b;
1580: out3 <= 12'h111;
1581: out3 <= 12'h117;
1582: out3 <= 12'h11d;
1583: out3 <= 12'h123;
1584: out3 <= 12'h129;
1585: out3 <= 12'h12f;
1586: out3 <= 12'h135;
1587: out3 <= 12'h13b;
1588: out3 <= 12'h141;
1589: out3 <= 12'h147;
1590: out3 <= 12'h14d;
1591: out3 <= 12'h153;
1592: out3 <= 12'h159;
1593: out3 <= 12'h15f;
1594: out3 <= 12'h165;
1595: out3 <= 12'h16b;
1596: out3 <= 12'h171;
1597: out3 <= 12'h176;
1598: out3 <= 12'h17c;
1599: out3 <= 12'h182;
1600: out3 <= 12'h188;
1601: out3 <= 12'h18e;
1602: out3 <= 12'h193;
1603: out3 <= 12'h199;
1604: out3 <= 12'h19f;
1605: out3 <= 12'h1a5;
1606: out3 <= 12'h1aa;
1607: out3 <= 12'h1b0;
1608: out3 <= 12'h1b6;
1609: out3 <= 12'h1bb;
1610: out3 <= 12'h1c1;
1611: out3 <= 12'h1c7;
1612: out3 <= 12'h1cc;
1613: out3 <= 12'h1d2;
1614: out3 <= 12'h1d8;
1615: out3 <= 12'h1dd;
1616: out3 <= 12'h1e3;
1617: out3 <= 12'h1e8;
1618: out3 <= 12'h1ee;
1619: out3 <= 12'h1f3;
1620: out3 <= 12'h1f9;
1621: out3 <= 12'h1fe;
1622: out3 <= 12'h204;
1623: out3 <= 12'h209;
1624: out3 <= 12'h20e;
1625: out3 <= 12'h214;
1626: out3 <= 12'h219;
1627: out3 <= 12'h21f;
1628: out3 <= 12'h224;
1629: out3 <= 12'h229;
1630: out3 <= 12'h22e;
1631: out3 <= 12'h234;
1632: out3 <= 12'h239;
1633: out3 <= 12'h23e;
1634: out3 <= 12'h243;
1635: out3 <= 12'h248;
1636: out3 <= 12'h24e;
1637: out3 <= 12'h253;
1638: out3 <= 12'h258;
1639: out3 <= 12'h25d;
1640: out3 <= 12'h262;
1641: out3 <= 12'h267;
1642: out3 <= 12'h26c;
1643: out3 <= 12'h271;
1644: out3 <= 12'h276;
1645: out3 <= 12'h27b;
1646: out3 <= 12'h280;
1647: out3 <= 12'h285;
1648: out3 <= 12'h28a;
1649: out3 <= 12'h28e;
1650: out3 <= 12'h293;
1651: out3 <= 12'h298;
1652: out3 <= 12'h29d;
1653: out3 <= 12'h2a2;
1654: out3 <= 12'h2a6;
1655: out3 <= 12'h2ab;
1656: out3 <= 12'h2b0;
1657: out3 <= 12'h2b4;
1658: out3 <= 12'h2b9;
1659: out3 <= 12'h2be;
1660: out3 <= 12'h2c2;
1661: out3 <= 12'h2c7;
1662: out3 <= 12'h2cb;
1663: out3 <= 12'h2d0;
1664: out3 <= 12'h2d4;
1665: out3 <= 12'h2d9;
1666: out3 <= 12'h2dd;
1667: out3 <= 12'h2e1;
1668: out3 <= 12'h2e6;
1669: out3 <= 12'h2ea;
1670: out3 <= 12'h2ee;
1671: out3 <= 12'h2f3;
1672: out3 <= 12'h2f7;
1673: out3 <= 12'h2fb;
1674: out3 <= 12'h2ff;
1675: out3 <= 12'h303;
1676: out3 <= 12'h307;
1677: out3 <= 12'h30b;
1678: out3 <= 12'h310;
1679: out3 <= 12'h314;
1680: out3 <= 12'h318;
1681: out3 <= 12'h31c;
1682: out3 <= 12'h31f;
1683: out3 <= 12'h323;
1684: out3 <= 12'h327;
1685: out3 <= 12'h32b;
1686: out3 <= 12'h32f;
1687: out3 <= 12'h333;
1688: out3 <= 12'h336;
1689: out3 <= 12'h33a;
1690: out3 <= 12'h33e;
1691: out3 <= 12'h342;
1692: out3 <= 12'h345;
1693: out3 <= 12'h349;
1694: out3 <= 12'h34c;
1695: out3 <= 12'h350;
1696: out3 <= 12'h353;
1697: out3 <= 12'h357;
1698: out3 <= 12'h35a;
1699: out3 <= 12'h35e;
1700: out3 <= 12'h361;
1701: out3 <= 12'h364;
1702: out3 <= 12'h368;
1703: out3 <= 12'h36b;
1704: out3 <= 12'h36e;
1705: out3 <= 12'h372;
1706: out3 <= 12'h375;
1707: out3 <= 12'h378;
1708: out3 <= 12'h37b;
1709: out3 <= 12'h37e;
1710: out3 <= 12'h381;
1711: out3 <= 12'h384;
1712: out3 <= 12'h387;
1713: out3 <= 12'h38a;
1714: out3 <= 12'h38d;
1715: out3 <= 12'h390;
1716: out3 <= 12'h393;
1717: out3 <= 12'h395;
1718: out3 <= 12'h398;
1719: out3 <= 12'h39b;
1720: out3 <= 12'h39e;
1721: out3 <= 12'h3a0;
1722: out3 <= 12'h3a3;
1723: out3 <= 12'h3a6;
1724: out3 <= 12'h3a8;
1725: out3 <= 12'h3ab;
1726: out3 <= 12'h3ad;
1727: out3 <= 12'h3b0;
1728: out3 <= 12'h3b2;
1729: out3 <= 12'h3b4;
1730: out3 <= 12'h3b7;
1731: out3 <= 12'h3b9;
1732: out3 <= 12'h3bb;
1733: out3 <= 12'h3be;
1734: out3 <= 12'h3c0;
1735: out3 <= 12'h3c2;
1736: out3 <= 12'h3c4;
1737: out3 <= 12'h3c6;
1738: out3 <= 12'h3c8;
1739: out3 <= 12'h3ca;
1740: out3 <= 12'h3cc;
1741: out3 <= 12'h3ce;
1742: out3 <= 12'h3d0;
1743: out3 <= 12'h3d2;
1744: out3 <= 12'h3d4;
1745: out3 <= 12'h3d6;
1746: out3 <= 12'h3d7;
1747: out3 <= 12'h3d9;
1748: out3 <= 12'h3db;
1749: out3 <= 12'h3dd;
1750: out3 <= 12'h3de;
1751: out3 <= 12'h3e0;
1752: out3 <= 12'h3e1;
1753: out3 <= 12'h3e3;
1754: out3 <= 12'h3e4;
1755: out3 <= 12'h3e6;
1756: out3 <= 12'h3e7;
1757: out3 <= 12'h3e8;
1758: out3 <= 12'h3ea;
1759: out3 <= 12'h3eb;
1760: out3 <= 12'h3ec;
1761: out3 <= 12'h3ee;
1762: out3 <= 12'h3ef;
1763: out3 <= 12'h3f0;
1764: out3 <= 12'h3f1;
1765: out3 <= 12'h3f2;
1766: out3 <= 12'h3f3;
1767: out3 <= 12'h3f4;
1768: out3 <= 12'h3f5;
1769: out3 <= 12'h3f6;
1770: out3 <= 12'h3f7;
1771: out3 <= 12'h3f8;
1772: out3 <= 12'h3f8;
1773: out3 <= 12'h3f9;
1774: out3 <= 12'h3fa;
1775: out3 <= 12'h3fa;
1776: out3 <= 12'h3fb;
1777: out3 <= 12'h3fc;
1778: out3 <= 12'h3fc;
1779: out3 <= 12'h3fd;
1780: out3 <= 12'h3fd;
1781: out3 <= 12'h3fe;
1782: out3 <= 12'h3fe;
1783: out3 <= 12'h3fe;
1784: out3 <= 12'h3ff;
1785: out3 <= 12'h3ff;
1786: out3 <= 12'h3ff;
1787: out3 <= 12'h400;
1788: out3 <= 12'h400;
1789: out3 <= 12'h400;
1790: out3 <= 12'h400;
1791: out3 <= 12'h400;
1792: out3 <= 12'h400;
1793: out3 <= 12'h400;
1794: out3 <= 12'h400;
1795: out3 <= 12'h400;
1796: out3 <= 12'h400;
1797: out3 <= 12'h400;
1798: out3 <= 12'h3ff;
1799: out3 <= 12'h3ff;
1800: out3 <= 12'h3ff;
1801: out3 <= 12'h3fe;
1802: out3 <= 12'h3fe;
1803: out3 <= 12'h3fe;
1804: out3 <= 12'h3fd;
1805: out3 <= 12'h3fd;
1806: out3 <= 12'h3fc;
1807: out3 <= 12'h3fc;
1808: out3 <= 12'h3fb;
1809: out3 <= 12'h3fa;
1810: out3 <= 12'h3fa;
1811: out3 <= 12'h3f9;
1812: out3 <= 12'h3f8;
1813: out3 <= 12'h3f8;
1814: out3 <= 12'h3f7;
1815: out3 <= 12'h3f6;
1816: out3 <= 12'h3f5;
1817: out3 <= 12'h3f4;
1818: out3 <= 12'h3f3;
1819: out3 <= 12'h3f2;
1820: out3 <= 12'h3f1;
1821: out3 <= 12'h3f0;
1822: out3 <= 12'h3ef;
1823: out3 <= 12'h3ee;
1824: out3 <= 12'h3ec;
1825: out3 <= 12'h3eb;
1826: out3 <= 12'h3ea;
1827: out3 <= 12'h3e8;
1828: out3 <= 12'h3e7;
1829: out3 <= 12'h3e6;
1830: out3 <= 12'h3e4;
1831: out3 <= 12'h3e3;
1832: out3 <= 12'h3e1;
1833: out3 <= 12'h3e0;
1834: out3 <= 12'h3de;
1835: out3 <= 12'h3dd;
1836: out3 <= 12'h3db;
1837: out3 <= 12'h3d9;
1838: out3 <= 12'h3d7;
1839: out3 <= 12'h3d6;
1840: out3 <= 12'h3d4;
1841: out3 <= 12'h3d2;
1842: out3 <= 12'h3d0;
1843: out3 <= 12'h3ce;
1844: out3 <= 12'h3cc;
1845: out3 <= 12'h3ca;
1846: out3 <= 12'h3c8;
1847: out3 <= 12'h3c6;
1848: out3 <= 12'h3c4;
1849: out3 <= 12'h3c2;
1850: out3 <= 12'h3c0;
1851: out3 <= 12'h3be;
1852: out3 <= 12'h3bb;
1853: out3 <= 12'h3b9;
1854: out3 <= 12'h3b7;
1855: out3 <= 12'h3b4;
1856: out3 <= 12'h3b2;
1857: out3 <= 12'h3b0;
1858: out3 <= 12'h3ad;
1859: out3 <= 12'h3ab;
1860: out3 <= 12'h3a8;
1861: out3 <= 12'h3a6;
1862: out3 <= 12'h3a3;
1863: out3 <= 12'h3a0;
1864: out3 <= 12'h39e;
1865: out3 <= 12'h39b;
1866: out3 <= 12'h398;
1867: out3 <= 12'h395;
1868: out3 <= 12'h393;
1869: out3 <= 12'h390;
1870: out3 <= 12'h38d;
1871: out3 <= 12'h38a;
1872: out3 <= 12'h387;
1873: out3 <= 12'h384;
1874: out3 <= 12'h381;
1875: out3 <= 12'h37e;
1876: out3 <= 12'h37b;
1877: out3 <= 12'h378;
1878: out3 <= 12'h375;
1879: out3 <= 12'h372;
1880: out3 <= 12'h36e;
1881: out3 <= 12'h36b;
1882: out3 <= 12'h368;
1883: out3 <= 12'h364;
1884: out3 <= 12'h361;
1885: out3 <= 12'h35e;
1886: out3 <= 12'h35a;
1887: out3 <= 12'h357;
1888: out3 <= 12'h353;
1889: out3 <= 12'h350;
1890: out3 <= 12'h34c;
1891: out3 <= 12'h349;
1892: out3 <= 12'h345;
1893: out3 <= 12'h342;
1894: out3 <= 12'h33e;
1895: out3 <= 12'h33a;
1896: out3 <= 12'h336;
1897: out3 <= 12'h333;
1898: out3 <= 12'h32f;
1899: out3 <= 12'h32b;
1900: out3 <= 12'h327;
1901: out3 <= 12'h323;
1902: out3 <= 12'h31f;
1903: out3 <= 12'h31c;
1904: out3 <= 12'h318;
1905: out3 <= 12'h314;
1906: out3 <= 12'h310;
1907: out3 <= 12'h30b;
1908: out3 <= 12'h307;
1909: out3 <= 12'h303;
1910: out3 <= 12'h2ff;
1911: out3 <= 12'h2fb;
1912: out3 <= 12'h2f7;
1913: out3 <= 12'h2f3;
1914: out3 <= 12'h2ee;
1915: out3 <= 12'h2ea;
1916: out3 <= 12'h2e6;
1917: out3 <= 12'h2e1;
1918: out3 <= 12'h2dd;
1919: out3 <= 12'h2d9;
1920: out3 <= 12'h2d4;
1921: out3 <= 12'h2d0;
1922: out3 <= 12'h2cb;
1923: out3 <= 12'h2c7;
1924: out3 <= 12'h2c2;
1925: out3 <= 12'h2be;
1926: out3 <= 12'h2b9;
1927: out3 <= 12'h2b4;
1928: out3 <= 12'h2b0;
1929: out3 <= 12'h2ab;
1930: out3 <= 12'h2a6;
1931: out3 <= 12'h2a2;
1932: out3 <= 12'h29d;
1933: out3 <= 12'h298;
1934: out3 <= 12'h293;
1935: out3 <= 12'h28e;
1936: out3 <= 12'h28a;
1937: out3 <= 12'h285;
1938: out3 <= 12'h280;
1939: out3 <= 12'h27b;
1940: out3 <= 12'h276;
1941: out3 <= 12'h271;
1942: out3 <= 12'h26c;
1943: out3 <= 12'h267;
1944: out3 <= 12'h262;
1945: out3 <= 12'h25d;
1946: out3 <= 12'h258;
1947: out3 <= 12'h253;
1948: out3 <= 12'h24e;
1949: out3 <= 12'h248;
1950: out3 <= 12'h243;
1951: out3 <= 12'h23e;
1952: out3 <= 12'h239;
1953: out3 <= 12'h234;
1954: out3 <= 12'h22e;
1955: out3 <= 12'h229;
1956: out3 <= 12'h224;
1957: out3 <= 12'h21f;
1958: out3 <= 12'h219;
1959: out3 <= 12'h214;
1960: out3 <= 12'h20e;
1961: out3 <= 12'h209;
1962: out3 <= 12'h204;
1963: out3 <= 12'h1fe;
1964: out3 <= 12'h1f9;
1965: out3 <= 12'h1f3;
1966: out3 <= 12'h1ee;
1967: out3 <= 12'h1e8;
1968: out3 <= 12'h1e3;
1969: out3 <= 12'h1dd;
1970: out3 <= 12'h1d8;
1971: out3 <= 12'h1d2;
1972: out3 <= 12'h1cc;
1973: out3 <= 12'h1c7;
1974: out3 <= 12'h1c1;
1975: out3 <= 12'h1bb;
1976: out3 <= 12'h1b6;
1977: out3 <= 12'h1b0;
1978: out3 <= 12'h1aa;
1979: out3 <= 12'h1a5;
1980: out3 <= 12'h19f;
1981: out3 <= 12'h199;
1982: out3 <= 12'h193;
1983: out3 <= 12'h18e;
1984: out3 <= 12'h188;
1985: out3 <= 12'h182;
1986: out3 <= 12'h17c;
1987: out3 <= 12'h176;
1988: out3 <= 12'h171;
1989: out3 <= 12'h16b;
1990: out3 <= 12'h165;
1991: out3 <= 12'h15f;
1992: out3 <= 12'h159;
1993: out3 <= 12'h153;
1994: out3 <= 12'h14d;
1995: out3 <= 12'h147;
1996: out3 <= 12'h141;
1997: out3 <= 12'h13b;
1998: out3 <= 12'h135;
1999: out3 <= 12'h12f;
2000: out3 <= 12'h129;
2001: out3 <= 12'h123;
2002: out3 <= 12'h11d;
2003: out3 <= 12'h117;
2004: out3 <= 12'h111;
2005: out3 <= 12'h10b;
2006: out3 <= 12'h105;
2007: out3 <= 12'hff;
2008: out3 <= 12'hf9;
2009: out3 <= 12'hf3;
2010: out3 <= 12'hed;
2011: out3 <= 12'he6;
2012: out3 <= 12'he0;
2013: out3 <= 12'hda;
2014: out3 <= 12'hd4;
2015: out3 <= 12'hce;
2016: out3 <= 12'hc8;
2017: out3 <= 12'hc2;
2018: out3 <= 12'hbb;
2019: out3 <= 12'hb5;
2020: out3 <= 12'haf;
2021: out3 <= 12'ha9;
2022: out3 <= 12'ha3;
2023: out3 <= 12'h9c;
2024: out3 <= 12'h96;
2025: out3 <= 12'h90;
2026: out3 <= 12'h8a;
2027: out3 <= 12'h84;
2028: out3 <= 12'h7d;
2029: out3 <= 12'h77;
2030: out3 <= 12'h71;
2031: out3 <= 12'h6b;
2032: out3 <= 12'h64;
2033: out3 <= 12'h5e;
2034: out3 <= 12'h58;
2035: out3 <= 12'h52;
2036: out3 <= 12'h4b;
2037: out3 <= 12'h45;
2038: out3 <= 12'h3f;
2039: out3 <= 12'h39;
2040: out3 <= 12'h32;
2041: out3 <= 12'h2c;
2042: out3 <= 12'h26;
2043: out3 <= 12'h1f;
2044: out3 <= 12'h19;
2045: out3 <= 12'h13;
2046: out3 <= 12'hd;
2047: out3 <= 12'h6;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 11
// Gap: 1
module codeBlock41778(clk, reset, next_in, next_out,
i2_in,
i1_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [9:0] i2_in;
reg [9:0] i2;
input [4:0] i1_in;
reg [4:0] i1;
input [11:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(10, 1) shiftFIFO_46356(.X(next), .Y(next_out), .clk(clk));
wire [10:0] a57;
wire [9:0] a59;
wire [10:0] a60;
wire signed [11:0] a70;
wire signed [11:0] a71;
wire [11:0] a58;
reg [10:0] tm15;
reg signed [11:0] tm16;
reg signed [11:0] tm23;
reg signed [11:0] tm44;
reg signed [11:0] tm54;
reg [11:0] a61;
wire [10:0] a62;
reg signed [11:0] tm17;
reg signed [11:0] tm24;
reg signed [11:0] tm45;
reg signed [11:0] tm55;
wire [11:0] a63;
reg signed [11:0] tm18;
reg signed [11:0] tm25;
reg signed [11:0] tm46;
reg signed [11:0] tm56;
reg signed [11:0] tm19;
reg signed [11:0] tm26;
reg signed [11:0] tm47;
reg signed [11:0] tm57;
reg signed [11:0] tm20;
reg signed [11:0] tm27;
reg signed [11:0] tm48;
reg signed [11:0] tm58;
wire signed [11:0] tm5;
wire signed [11:0] a64;
wire signed [11:0] tm6;
wire signed [11:0] a66;
reg signed [11:0] tm21;
reg signed [11:0] tm28;
reg signed [11:0] tm49;
reg signed [11:0] tm59;
reg signed [11:0] tm7;
reg signed [11:0] tm8;
reg signed [11:0] tm22;
reg signed [11:0] tm29;
reg signed [11:0] tm50;
reg signed [11:0] tm60;
reg signed [11:0] tm51;
reg signed [11:0] tm61;
wire signed [11:0] a65;
wire signed [11:0] a67;
wire signed [11:0] a68;
wire signed [11:0] a69;
reg signed [11:0] tm52;
reg signed [11:0] tm62;
wire signed [11:0] Y0;
wire signed [11:0] Y1;
wire signed [11:0] Y2;
wire signed [11:0] Y3;
reg signed [11:0] tm53;
reg signed [11:0] tm63;
wire [0:0] tm1;
assign tm1 = 1'h1;
wire [9:0] tm2;
assign tm2 = 10'h3ff;
wire [10:0] tm4;
assign tm4 = 11'h400;
assign a57 = i2 << 1;
assign a59 = tm2 << i1;
assign a60 = {a59, tm1[0:0]};
assign a70 = X2;
assign a71 = X3;
assign a62 = {a61[0:0], a61[10:1]};
assign a64 = tm5;
assign a66 = tm6;
assign Y0 = tm53;
assign Y1 = tm63;
D1_43962 instD1inst0_43962(.addr(a63[10:0]), .out(tm5), .clk(clk));
D2_46012 instD2inst0_46012(.addr(a63[10:0]), .out(tm6), .clk(clk));
addfxp #(12, 1) add41797(.a({1'b0, a57}), .b({11'b0, tm1}), .clk(clk), .q(a58)); // 0
subfxp #(12, 1) sub41829(.a({1'b0, a62}), .b({1'b0, tm4}), .clk(clk), .q(a63)); // 2
multfix #(12, 2) m41851(.a(tm7), .b(tm22), .clk(clk), .q_sc(a65), .q_unsc(), .rst(reset));
multfix #(12, 2) m41873(.a(tm8), .b(tm29), .clk(clk), .q_sc(a67), .q_unsc(), .rst(reset));
multfix #(12, 2) m41891(.a(tm8), .b(tm22), .clk(clk), .q_sc(a68), .q_unsc(), .rst(reset));
multfix #(12, 2) m41902(.a(tm7), .b(tm29), .clk(clk), .q_sc(a69), .q_unsc(), .rst(reset));
subfxp #(12, 1) sub41880(.a(a65), .b(a67), .clk(clk), .q(Y2)); // 9
addfxp #(12, 1) add41909(.a(a68), .b(a69), .clk(clk), .q(Y3)); // 9
always @(posedge clk) begin
if (reset == 1) begin
tm7 <= 0;
tm22 <= 0;
tm8 <= 0;
tm29 <= 0;
tm8 <= 0;
tm22 <= 0;
tm7 <= 0;
tm29 <= 0;
end
else begin
i2 <= i2_in;
i1 <= i1_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm15 <= a60;
tm16 <= a70;
tm23 <= a71;
tm44 <= X0;
tm54 <= X1;
a61 <= (a58 & tm15);
tm17 <= tm16;
tm24 <= tm23;
tm45 <= tm44;
tm55 <= tm54;
tm18 <= tm17;
tm25 <= tm24;
tm46 <= tm45;
tm56 <= tm55;
tm19 <= tm18;
tm26 <= tm25;
tm47 <= tm46;
tm57 <= tm56;
tm20 <= tm19;
tm27 <= tm26;
tm48 <= tm47;
tm58 <= tm57;
tm21 <= tm20;
tm28 <= tm27;
tm49 <= tm48;
tm59 <= tm58;
tm7 <= a64;
tm8 <= a66;
tm22 <= tm21;
tm29 <= tm28;
tm50 <= tm49;
tm60 <= tm59;
tm51 <= tm50;
tm61 <= tm60;
tm52 <= tm51;
tm62 <= tm61;
tm53 <= tm52;
tm63 <= tm62;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock46016(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [11:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_46359(.X(next), .Y(next_out), .clk(clk));
wire signed [11:0] a9;
wire signed [11:0] a10;
wire signed [11:0] a11;
wire signed [11:0] a12;
wire signed [12:0] tm11;
wire signed [12:0] tm12;
wire signed [12:0] tm13;
wire signed [12:0] tm14;
wire signed [11:0] Y0;
wire signed [11:0] Y1;
wire signed [11:0] Y2;
wire signed [11:0] Y3;
wire signed [11:0] t21;
wire signed [11:0] t22;
wire signed [11:0] t23;
wire signed [11:0] t24;
assign a9 = X0;
assign a10 = X2;
assign a11 = X1;
assign a12 = X3;
assign Y0 = t21;
assign Y1 = t22;
assign Y2 = t23;
assign Y3 = t24;
assign t21 = tm11[12:1];
assign t22 = tm12[12:1];
assign t23 = tm13[12:1];
assign t24 = tm14[12:1];
addfxp #(13, 1) add46028(.a({{1{a9[11]}}, a9}), .b({{1{a10[11]}}, a10}), .clk(clk), .q(tm11)); // 0
addfxp #(13, 1) add46043(.a({{1{a11[11]}}, a11}), .b({{1{a12[11]}}, a12}), .clk(clk), .q(tm12)); // 0
subfxp #(13, 1) sub46058(.a({{1{a9[11]}}, a9}), .b({{1{a10[11]}}, a10}), .clk(clk), .q(tm13)); // 0
subfxp #(13, 1) sub46073(.a({{1{a11[11]}}, a11}), .b({{1{a12[11]}}, a12}), .clk(clk), .q(tm14)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 1012
// Gap: 1024
module rc46097(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
wire [23:0] t0;
wire [23:0] s0;
assign t0 = {X0, X1};
wire [23:0] t1;
wire [23:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[23:12];
assign Y1 = s0[11:0];
assign Y2 = s1[23:12];
assign Y3 = s1[11:0];
perm46095 instPerm46360(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
// Latency: 1012
// Gap: 1024
module perm46095(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 1024;
parameter logDepth = 10;
parameter width = 24;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] ybuff0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] ybuff1;
input clk, next, reset;
output next_out;
wire next0;
reg inFlip0, outFlip0;
reg inActive, outActive;
wire [logBanks-1:0] inBank0, outBank0;
wire [logDepth-1:0] inAddr0, outAddr0;
wire [logBanks-1:0] outBank_a0;
wire [logDepth-1:0] outAddr_a0;
wire [logDepth+logBanks-1:0] addr0, addr0b, addr0c;
wire [logBanks-1:0] inBank1, outBank1;
wire [logDepth-1:0] inAddr1, outAddr1;
wire [logBanks-1:0] outBank_a1;
wire [logDepth-1:0] outAddr_a1;
wire [logDepth+logBanks-1:0] addr1, addr1b, addr1c;
reg [logDepth-1:0] inCount, outCount, outCount_d, outCount_dd, outCount_for_rd_addr, outCount_for_rd_data;
assign addr0 = {inCount, 1'd0};
assign addr0b = {outCount, 1'd0};
assign addr0c = {outCount_for_rd_addr, 1'd0};
assign addr1 = {inCount, 1'd1};
assign addr1b = {outCount, 1'd1};
assign addr1c = {outCount_for_rd_addr, 1'd1};
wire [width+logDepth-1:0] w_0_0, w_0_1, w_1_0, w_1_1;
reg [width-1:0] z_0_0;
reg [width-1:0] z_0_1;
wire [width-1:0] z_1_0, z_1_1;
wire [logDepth-1:0] u_0_0, u_0_1, u_1_0, u_1_1;
always @(posedge clk) begin
end
assign inBank0[0] = addr0[1] ^ addr0[0];
assign inAddr0[0] = addr0[2];
assign inAddr0[1] = addr0[3];
assign inAddr0[2] = addr0[4];
assign inAddr0[3] = addr0[5];
assign inAddr0[4] = addr0[6];
assign inAddr0[5] = addr0[7];
assign inAddr0[6] = addr0[8];
assign inAddr0[7] = addr0[9];
assign inAddr0[8] = addr0[10];
assign inAddr0[9] = addr0[0];
assign outBank0[0] = addr0b[10] ^ addr0b[0];
assign outAddr0[0] = addr0b[1];
assign outAddr0[1] = addr0b[2];
assign outAddr0[2] = addr0b[3];
assign outAddr0[3] = addr0b[4];
assign outAddr0[4] = addr0b[5];
assign outAddr0[5] = addr0b[6];
assign outAddr0[6] = addr0b[7];
assign outAddr0[7] = addr0b[8];
assign outAddr0[8] = addr0b[9];
assign outAddr0[9] = addr0b[10];
assign outBank_a0[0] = addr0c[10] ^ addr0c[0];
assign outAddr_a0[0] = addr0c[1];
assign outAddr_a0[1] = addr0c[2];
assign outAddr_a0[2] = addr0c[3];
assign outAddr_a0[3] = addr0c[4];
assign outAddr_a0[4] = addr0c[5];
assign outAddr_a0[5] = addr0c[6];
assign outAddr_a0[6] = addr0c[7];
assign outAddr_a0[7] = addr0c[8];
assign outAddr_a0[8] = addr0c[9];
assign outAddr_a0[9] = addr0c[10];
assign inBank1[0] = addr1[1] ^ addr1[0];
assign inAddr1[0] = addr1[2];
assign inAddr1[1] = addr1[3];
assign inAddr1[2] = addr1[4];
assign inAddr1[3] = addr1[5];
assign inAddr1[4] = addr1[6];
assign inAddr1[5] = addr1[7];
assign inAddr1[6] = addr1[8];
assign inAddr1[7] = addr1[9];
assign inAddr1[8] = addr1[10];
assign inAddr1[9] = addr1[0];
assign outBank1[0] = addr1b[10] ^ addr1b[0];
assign outAddr1[0] = addr1b[1];
assign outAddr1[1] = addr1b[2];
assign outAddr1[2] = addr1b[3];
assign outAddr1[3] = addr1b[4];
assign outAddr1[4] = addr1b[5];
assign outAddr1[5] = addr1b[6];
assign outAddr1[6] = addr1b[7];
assign outAddr1[7] = addr1b[8];
assign outAddr1[8] = addr1b[9];
assign outAddr1[9] = addr1b[10];
assign outBank_a1[0] = addr1c[10] ^ addr1c[0];
assign outAddr_a1[0] = addr1c[1];
assign outAddr_a1[1] = addr1c[2];
assign outAddr_a1[2] = addr1c[3];
assign outAddr_a1[3] = addr1c[4];
assign outAddr_a1[4] = addr1c[5];
assign outAddr_a1[5] = addr1c[6];
assign outAddr_a1[6] = addr1c[7];
assign outAddr_a1[7] = addr1c[8];
assign outAddr_a1[8] = addr1c[9];
assign outAddr_a1[9] = addr1c[10];
nextReg #(1010, 10) nextReg_46365(.X(next), .Y(next0), .reset(reset), .clk(clk));
shiftRegFIFO #(2, 1) shiftFIFO_46368(.X(next0), .Y(next_out), .clk(clk));
memArray2048_46095 #(numBanks, logBanks, depth, logDepth, width)
memSys(.inFlip(inFlip0), .outFlip(outFlip0), .next(next), .reset(reset),
.x0(w_1_0[width+logDepth-1:logDepth]), .y0(ybuff0),
.inAddr0(w_1_0[logDepth-1:0]),
.outAddr0(u_1_0),
.x1(w_1_1[width+logDepth-1:logDepth]), .y1(ybuff1),
.inAddr1(w_1_1[logDepth-1:0]),
.outAddr1(u_1_1),
.clk(clk));
always @(posedge clk) begin
if (reset == 1) begin
z_0_0 <= 0;
z_0_1 <= 0;
inFlip0 <= 0; outFlip0 <= 1; outCount <= 0; inCount <= 0;
outCount_for_rd_addr <= 0;
outCount_for_rd_data <= 0;
end
else begin
outCount_d <= outCount;
outCount_dd <= outCount_d;
if (inCount == 1009)
outCount_for_rd_addr <= 0;
else
outCount_for_rd_addr <= outCount_for_rd_addr+1;
if (inCount == 1011)
outCount_for_rd_data <= 0;
else
outCount_for_rd_data <= outCount_for_rd_data+1;
z_0_0 <= ybuff0;
z_0_1 <= ybuff1;
if (inCount == 1009) begin
outFlip0 <= ~outFlip0;
outCount <= 0;
end
else
outCount <= outCount+1;
if (inCount == 1023) begin
inFlip0 <= ~inFlip0;
end
if (next == 1) begin
if (inCount >= 1009)
inFlip0 <= ~inFlip0;
inCount <= 0;
end
else
inCount <= inCount + 1;
end
end
assign w_0_0 = {x0, inAddr0};
assign w_0_1 = {x1, inAddr1};
assign y0 = z_1_0;
assign y1 = z_1_1;
assign u_0_0 = outAddr_a0;
assign u_0_1 = outAddr_a1;
wire wr_ctrl_st_0;
assign wr_ctrl_st_0 = inCount[0];
switch #(logDepth+width) in_sw_0_0(.x0(w_0_0), .x1(w_0_1), .y0(w_1_0), .y1(w_1_1), .ctrl(wr_ctrl_st_0));
wire rdd_ctrl_st_0;
assign rdd_ctrl_st_0 = outCount_for_rd_data[9];
switch #(width) out_sw_0_0(.x0(z_0_0), .x1(z_0_1), .y0(z_1_0), .y1(z_1_1), .ctrl(rdd_ctrl_st_0));
wire rda_ctrl_st_0;
assign rda_ctrl_st_0 = outCount_for_rd_addr[9];
switch #(logDepth) rdaddr_sw_0_0(.x0(u_0_0), .x1(u_0_1), .y0(u_1_0), .y1(u_1_1), .ctrl(rda_ctrl_st_0));
endmodule
module memArray2048_46095(next, reset,
x0, y0,
inAddr0,
outAddr0,
x1, y1,
inAddr1,
outAddr1,
clk, inFlip, outFlip);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 1024;
parameter logDepth = 10;
parameter width = 24;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
nextReg #(1024, 10) nextReg_46373(.X(next), .Y(next0), .reset(reset), .clk(clk));
memMod #(depth*2, width, logDepth+1)
memMod0(.in(x0), .out(y0), .inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}), .writeSel(1'b1), .clk(clk));
memMod #(depth*2, width, logDepth+1)
memMod1(.in(x1), .out(y1), .inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}), .writeSel(1'b1), .clk(clk));
endmodule
module multfix(clk, rst, a, b, q_sc, q_unsc);
parameter WIDTH=35, CYCLES=6;
input signed [WIDTH-1:0] a,b;
output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg signed [2*WIDTH-1:0] q[CYCLES-1:0];
wire signed [2*WIDTH-1:0] res;
integer i;
assign res = q[CYCLES-1];
assign q_unsc = res[WIDTH-1:0];
assign q_sc = {res[2*WIDTH-1], res[2*WIDTH-4:WIDTH-2]};
always @(posedge clk) begin
q[0] <= a * b;
for (i = 1; i < CYCLES; i=i+1) begin
q[i] <= q[i-1];
end
end
endmodule
module addfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a+b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule
module subfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a-b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:36:16 10/29/2011
// Design Name: M_uxa_ps2_shfreg
// Module Name: /Users/kc5tja/tmp/kestrel/2/nexys2/uxa/ps2io/T_uxa_ps2_shfreg.v
// Project Name: ps2io
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: M_uxa_ps2_shfreg
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module T_uxa_ps2_shfreg;
// Inputs
reg ps2_d_i;
reg ps2_c_i;
reg reset_i;
reg sys_clk_i;
// Outputs
wire [7:0] d_o;
wire frame_o;
// Instantiate the Unit Under Test (UUT)
M_uxa_ps2_shfreg uut (
.ps2_d_i(ps2_d_i),
.ps2_c_i(ps2_c_i),
.d_o(d_o),
.frame_o(frame_o),
.reset_i(reset_i),
.sys_clk_i(sys_clk_i)
);
always begin
#40 sys_clk_i <= 1;
#40 sys_clk_i <= 0;
end
initial begin
// Initialize Inputs
ps2_d_i = 1;
ps2_c_i = 1;
reset_i = 1;
sys_clk_i = 0;
#80 reset_i = 0;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#320 ;
if(d_o != 8'b01100100) begin
$display("Deserializer failed to grab byte correctly.");
$stop;
end
if(frame_o != 1) begin
$display("Deserializer failed to sync to the PS/2 frame.");
$stop;
end
reset_i = 1;
#80 reset_i = 0;
if(d_o != 8'b11111111) begin
$display("Deserializer didn't reset when instructed.");
$stop;
end
if(frame_o != 0) begin
$display("Frame indicator didn't reset when instructed.");
$stop;
end
end
endmodule
|
// ====================================================================
// MAH PONK
//
// Copyright (C) 2007, Viacheslav Slavinsky
// This design and core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
// An open table tennis game for VGA displays.
//
// Author: Viacheslav Slavinsky, http://sensi.org/~svo
//
// Design File: analinput.v
// Analog input module.
// Implements SPI and alternatingly queries 2 channels of ADxxxx.
//
// Pins description:
// clk input clock, same as used for SPI SCK
// pay output paddle A y-coordinate
// pby output paddle B y-coordinate
// miso input MISO
// mosi output MOSI
// cs output ADC CS
// sck output SCK
module analinput(clk, pay, pby, miso, mosi, cs, sck);
parameter PADDLESIZE = 0;
parameter SCREENHEIGHT = 0;
input clk;
output reg[9:0] pay;
output reg[9:0] pby;
input miso;
output reg mosi;
output reg cs;
output sck;
parameter state0 = 0, state1 = 1, state2 = 2, state3 = 3;
reg [1:0] state;
reg [4:0] sckcount;
reg [11:0] datain;
reg ab;
assign sck = clk;
always @(posedge sck) begin
case(state)
state0:
begin
ab <= 1;
state <= state1;
end
state1:
begin
ab <= !ab;
cs <= 0;
mosi <= !ab;
sckcount <= 15;
state <= state2;
end
state2:
begin
if (sckcount != 0)
sckcount <= sckcount - 1'b1;
else
state <= state3;
end
state3:
begin
cs <= 1;
mosi <= 0;
if (ab == 0) begin
pay <= paddlelimiter(datain[11:3]);
end else begin
pby <= paddlelimiter(datain[11:3]);
end
state <= state1;
end
default:
state <= state0;
endcase
end
always @(negedge sck) begin
if (state == state2)
datain <= (datain << 1) | miso;
else if (state == state1)
datain <= 0;
end
//
// Limit paddle position to stay within screen coordinates
//
function [9:0] paddlelimiter;
input [9:0] py;
begin
if (py < PADDLESIZE/2)
paddlelimiter = PADDLESIZE/2;
else
if (py > SCREENHEIGHT-96/2)
paddlelimiter = SCREENHEIGHT-PADDLESIZE/2;
else
paddlelimiter = py;
end
endfunction
endmodule
// $Id: analinput.v,v 1.6 2007/08/27 22:14:46 svo Exp $
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_SYMBOL_V
`define SKY130_FD_SC_HD__O21A_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_SYMBOL_V
|
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